V62/21610-01XE-T [TI]
采用航天增强型塑料的抗辐射、四通道、3/1 数字隔离器 | DBQ | 16;
| 型号： | V62/21610-01XE-T |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用航天增强型塑料的抗辐射、四通道、3/1 数字隔离器 | DBQ | 16 |
| 文件： | 总40页 (文件大小：2028K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISOS141-SEP
ZHCSNI5 –MAY 2021
ISOS141-SEP 抗辐射高速四通道数字隔离器
1 特性
3 说明
• 抗辐射
ISOS141-SEP 抗辐射器件是采用小型 16 引脚 QSOP
封装的高性能四通道数字隔离器。每条隔离通道的逻辑
输入和输出缓冲器均由双电容二氧化硅 (SiO2) 绝缘栅
相隔离。该器件具有 100Mbps 的高数据速率、10.7ns
的低传播延迟和 4ns 的通道间严格偏移，支持近地轨
道(LEO) 航天应用。ISOS141-SEP 器件具有三个正向
通道和一个反向通道，如果失去输入功率或信号，默认
输出为低电平。使能引脚可用于将各输出置于高阻抗，
适用于多主驱动应用，还可降低功耗。
– 电离辐射总剂量(TID) 特征值（无ELDRS）=
30krad(Si)
– TID RLAT/RHA = 30krad(Si)
– 单粒子锁定(SEL) 在125°C 下对LET 的抗扰度
= 43MeV⋅cm2/mg
– 单粒子绝缘击穿(SEDR) 在500VDC 下的抗扰度
(43MeV⋅cm2/mg)
• 增强型航天塑料（航天EP）
– 符合NASA ASTM E595 释气规格要求
– 供应商项目图(VID) V62/21610
– 军用级温度范围（-55°C 至125°C）
– 同一晶圆制造场所
ISOS141-SEP 在隔离 CMOS 或 LVCMOS 数字 I/O
时，具有高电磁抗扰度和低辐射、低功耗特性。该器件
具有 100kV/µs 的高共模瞬态抗扰度，可轻松缓解系统
级 ESD、EFT 和浪涌问题，还通过创新的芯片设计简
化了辐射方面的合规性。
– 同一组装和测试场所
– 金键合线，NiPdAu 铅涂层
– 晶圆批次可追溯性
– 延长了产品生命周期
器件信息
封装
封装尺寸（标称值）
器件型号
ISOS141FDBQSEP
– 延长了产品变更通知周期
• 600VRMS 连续工作电压
• 节6.7：
30krad(Si) RLAT/RHA
16 引线
4.90mm × 3.90mm
ISOS141FDBQTSEP
30krad(Si) RLAT/RHA
QSOP (DBQ)
– DIN VDE V 0884-11:2017-01
– UL 1577 组件认证计划
• 100 Mbps 数据速率
1
2
3
4
5
6
7
8
16
V
V
CC1
CC2
• 宽电源电压范围：2.25V 至5.5V
• 2.25V 至5.5V 电平转换
• 默认输出低
• 低功耗，1Mbps 时每通道的电流典型值为1.5mA
• 低传播延迟：典型值为10.7ns（5V 电源供电时）
• 通道间偏斜小：最大4ns（5V 电源供电时）
• CMTI 典型值为±100kV/μs
GND1
INA
15 GND2
14 OUTA
13 OUTB
12 OUTC
11 IND
10 EN2
INB
INC
OUTD
EN1
• 系统级ESD、EFT、浪涌和磁抗扰度
• 小型QSOP (DBQ-16) 封装
GND1
9 GND2
2 应用
VCCI = 输入电源，VCC2 = 输出电源
GND1 = 输入接地，GND2 = 输出接地
• 近地轨道(LEO) 航天应用
• 信号隔离（RS-422、RS-485、CAN、SPI）
• 栅极驱动器隔离或GaN 直流/直流转换器的隔离式
反馈
简化原理图
• 航天级隔离式直流/直流模块
• 航天器电池管理系统(BMS)
• 卫星推进电源处理单元(PPU)
• 发射器和着陆器系统
• 通信有效载荷
• 雷达成像有效载荷
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFN1
ISOS141-SEP
ZHCSNI5 –MAY 2021
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Table of Contents
6.18 Insulation Characteristics Curves........................... 15
6.19 Typical Characteristics............................................16
7 Operating Life Deration.................................................17
8 Parameter Measurement Information..........................18
9 Detailed Description......................................................20
9.1 Overview...................................................................20
9.2 Functional Block Diagram.........................................20
9.3 Feature Description...................................................21
9.4 Device Functional Modes..........................................22
10 Application and Implementation................................23
10.1 Application Information........................................... 23
10.2 Typical Application.................................................. 24
11 Power Supply Recommendations..............................28
12 Layout...........................................................................29
12.1 Layout Guidelines................................................... 29
12.2 Layout Example...................................................... 29
13 Device and Documentation Support..........................30
13.1 Documentation Support.......................................... 30
13.2 Receiving Notification of Documentation Updates..30
13.3 Community Resources............................................30
13.4 Trademarks.............................................................30
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Power Ratings ............................................................6
6.6 Insulation Specifications ............................................ 7
6.7 Safety-Related Certifications ..................................... 8
6.8 Safety Limiting Values ................................................8
6.9 Electrical Characteristics—5-V Supply ...................... 9
6.10 Supply Current Characteristics—5-V Supply ...........9
6.11 Electrical Characteristics—3.3-V Supply ................10
6.12 Supply Current Characteristics—3.3-V Supply ......10
6.13 Electrical Characteristics—2.5-V Supply ...............11
6.14 Supply Current Characteristics—2.5-V Supply ...... 11
6.15 Switching Characteristics—5-V Supply ..................12
6.16 Switching Characteristics—3.3-V Supply ...............13
6.17 Switching Characteristics—2.5-V Supply ...............14
Information.................................................................... 31
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
May 2021
*
Initial release.
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5 Pin Configuration and Functions
VCC1
GND1
INA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
IND
INB
INC
OUTD
EN1
EN2
GND1
GND2
Not to scale
图5-1. ISOS141-SEP DBQ Package 16-pin QSOP Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
Number
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in
high-impedance state when EN1 is low.
EN1
7
I
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in
high-impedance state when EN2 is low.
EN2
10
2
8
GND1
Ground connection for VCC1
Ground connection for VCC2
—
—
9
GND2
15
3
INA
INB
I
I
Input, channel A
Input, channel B
Input, channel C
Input, channel D
Output, channel A
Output, channel B
Output, channel C
Output, channel D
Power supply, side 1
Power supply, side 2
4
INC
5
I
IND
11
14
13
12
6
I
OUTA
OUTB
OUTC
OUTD
VCC1
VCC2
O
O
O
O
—
—
1
16
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6 Specifications
6.1 Absolute Maximum Ratings
See(1)
MIN
MAX
UNIT
Supply voltage (2) VCC1, VCC2
-0.5
6
V
Voltage at INx,
V
-0.5
-15
VCCX + 0.5 (3)
V
OUTx, ENx
Output current
Temperature
Io
15
150
150
mA
°C
Operating junction temperature, TJ
Storage temperature, Tstg
-65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±6000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
V(ESD)
Electrostatic discharge
±1500
±8000
V
Contact discharge per IEC 61000-4-2;
Isolation barrier withstand test(3) (4)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC1 , VCC2
Supply Voltage
2.25
5.5
V
(1)
Vcc
UVLO threshold when supply voltage is rising
(UVLO+)
2
1.8
2.25
V
V
Vcc
UVLO threshold when supply voltage is falling
(UVLO-)
1.7
Vhys
Supply voltage UVLO hysteresis
(UVLO)
100
200
mV
V
0.7 x VCC(2I)
VIH
VIL
High level Input voltage
Low level Input voltage
VCCI
0
-4
-2
-1
0.3 x VCCI
V
mA
mA
mA
mA
mA
mA
Mbps
°C
VCCO = 5 V (2)
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 5 V
IOH
High level output current
Low level output current
4
2
IOL
VCCO = 3.3 V
VCCO = 2.5 V
1
DR
TA
Data Rate
0
100
125
Ambient temperature
-55
25
(1) VCC1 and VCC2 can be set independent of one another
(2) VCCI = Input-side VCC; VCCO = Output-side VCC
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UNIT
6.4 Thermal Information
ISOS141
DBQ (SOIC)
16 PINS
109
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
54.4
51.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
14.2
ψJT
51.4
ψJB
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISOS141
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
200
75
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 50-MHz 50% duty cycle
square wave
PD1
PD2
125
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6.6 Insulation Specifications
VALUE
UNIT
DBQ-16
PARAMETER
TEST CONDITIONS
CLR
CPG
External clearance(1)
External creepage(1)
Shortest terminal-to-terminal distance through air
>3.7
mm
mm
Shortest terminal-to-terminal distance across the
package surface
>3.7
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
>21
>600
I
um
V
Overvoltage category per IEC 60664-1
I-III
Rated mains voltage ≤300 VRMS
DIN VDE V 0884-11:2017-01 (2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
848
600
848
VPK
VRMS
VDC
AC voltage; Time dependent dielectric breakdown
(TDDB) Test
See 图10-7
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM
t = 60 s (qualification);
VTEST = 1.2 x VIOTM
,
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
4242
VPK
,
t= 1 s (100% production)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.3 x VIOSM (qualification)
VIOSM
4000
VPK
Method a, After Input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
≤5
Vpd(m) = 1.2 x VIORM, tm = 10 s
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 x VIORM, tm = 10 s
≤5
≤5
qpd
Apparent charge(4)
pC
Method b; At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.5 x VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Isolation resistance(5)
~1
pF
VIO = 0.4 x sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
>1012
>1011
>109
2
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
55/125/21
UL 1577
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 x VISO , t = 1 s (100% production)
VISO
Maximum withstanding isolation voltage
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these
specifications.
(2) This coupler is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
VDE
UL
Certifying according to UL 1577 Component Recognition Program
Certifying according to DIN VDE V 0884-11:2017-01
Maximum transient isolation voltage, 4242 VPK (DBQ-16); Maximum
repetitive peak isolation voltage, 848 VPK (DBQ-16); Maximum surge Single protection, 3000 VRMS
isolation voltage, 4000 VPK (DBQ-16)
Basic certificate: planned
File number: planned
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DBQ-16 PACKAGE
RθJA =109°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C
See 图6-1
209
319
417
mA
RθJA = 109°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
See 图6-1
IS
Safety input, output, or supply current
mA
RθJA = 109°C/W, VI = 2.75 V, TJ = 150°C,
TA = 25°C
See 图6-1
R
θJA = 109°C/W, TJ = 150°C, TA = 25°C
PS
TS
Safety input, output, or total power
Maximum safety temperature
1147
150
mW
°C
See 图6-2
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -4 mA; See 图8-1
IOL = 4 mA; See 图8-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
Input threshold voltage hysteresis
High-level input current
VCCO - 0.4 (1)
V
VOL
0.4
V
V
(1)
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
V
V
VIH = VCCI (1) at INx or ENx
VIL = 0 V at INx or ENx
10
µA
µA
IIL
Low-level input current
-10
85
VI = VCC or 0 V, VCM = 1200
V; See 图8-4
CMTI
Ci
Common mode transient immunity
Input Capacitance (2)
100
2
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 5 V
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISOS141
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1
0.8
4.3
1.8
1.5
2
1.5
1.1
6.3
2.7
2.3
3
EN1 = EN2 = 0 V; VI = 0 V (ISOS141)
EN1 = EN2 = 0 V; VI = VCCI (1)(ISOS141)
EN1 = EN2 = VCCI; VI = 0 V (ISOS141)
EN1 = EN2 = VCCI; VI = VCCI (ISOS141)
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - Disable
Supply current - DC signal
(2)
4.8
3.2
3.2
2.8
3.7
4.2
8.6
18
6.8
mA
4.9
4.6
4.1
5.2
5.7
11.3
22
1 Mbps
Supply current - AC signal All channels switching with square
10 Mbps
(3)
wave clock input; CL = 15 pF
100 Mbps
(1) VCCI = Input-side VCC
(2) Supply current valid for ENx = VCCx and ENx = open
(3) Supply current valid for ENx = VCCx
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -2mA; See 图8-1
IOL = 2mA; See 图8-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
VCCO - 0.3 (1)
V
VOL
0.3
V
V
V
(1)
VIT+(IN)
VIT-(IN)
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
Input threshold voltage
hysteresis
VI(HYS)
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI (1) at INx or ENx
VIL = 0 V at INx or ENx
10
µA
µA
-10
85
VI = VCC or 0 V, VCM = 1200
V; See 图8-4
Common mode transient
immunity
CMTI
Ci
100
2
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f =
1 MHz, VCC = 5 V
Input Capacitance (2)
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISOS141
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1
0.8
4.3
1.9
1.5
2
1.5
1.1
6.3
2.7
2.3
3
EN1 = EN2 = 0 V; VI = 0 V (ISOS141)
EN1 = EN2 = 0 V; VI = VCC1 (1)(ISOS141)
EN1 = EN2 = VCCI; VI = 0 V (ISOS141)
EN1 = EN2 = VCCI; VI = VCCI (ISOS141)
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - Disable
Supply current - DC signal
(2)
4.8
3.2
3.2
2.7
3.5
3.7
6.8
13.7
6.8
mA
4.9
4.6
4.1
5
1 Mbps
Supply current - AC signal All channels switching with square
10 Mbps
(3)
wave clock input; CL = 15 pF
5.2
9.3
16.4
100 Mbps
(1) VCCI = Input-side VCC
(2) Supply current valid for ENx = VCCx and ENx = open
(3) Supply current valid for ENx = VCCx
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -1mA; See 图8-1
IOL = 1mA; See 图8-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
VCCO - 0.2 (1)
V
VOL
0.2
V
V
V
(1)
VIT+(IN)
VIT-(IN)
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
Input threshold voltage
hysteresis
VI(HYS)
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI (1) at INx or ENx
VIL = 0 V at INx or ENx
10
µA
µA
-10
85
VI = VCC or 0 V, VCM = 1200
V; See 图8-4
Common mode transient
immunity
CMTI
Ci
100
2
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f =
1 MHz, VCC = 5 V
Input Capacitance (2)
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISOS141
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1
0.8
4.3
1.8
1.4
2
1.5
1.1
6.3
2.7
2.3
3
EN1 = EN2 = 0 V; VI = 0 V (ISOS141)
EN1 = EN2 = 0 V; VI = VCC1 (1)(ISOS141)
EN1 = EN2 = VCCI; VI = 0 V (ISOS141)
EN1 = EN2 = VCCI; VI = VCCI (ISOS141)
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - Disable
Supply current - DC signal
(2)
4.7
3.2
3.1
2.7
3.4
3.5
5.6
10.8
6.8
mA
4.9
4.6
4
1 Mbps
4.9
4.9
8.3
13.8
Supply current - AC signal All channels switching with square
10 Mbps
(3)
wave clock input; CL = 15 pF
100 Mbps
(1) VCCI = Input-side VCC
(2) Supply current valid for ENx = VCCx and ENx = open
(3) Supply current valid for ENx = VCCx
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MAX UNIT
6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
10.7
16
4.9
4
ns
ns
ns
ns
ns
ns
ns
ns
See 图8-1
|
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.4
3.9
3.9
20
20
Output signal rise time
2.4
2.4
9
See 图8-1
tf
Output signal fall time
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
9
Enable propagation delay, high impedance-to-high output for
ISOS141 with F suffix
See 图8-2
tPZH
tPZL
tDO
tie
3
7
8.5
20
µs
ns
Enable propagation delay, high impedance-to-low output for
ISOS141 with F suffix
Measured from the time VCC goes
below 1.7V. See 图8-3
Default output delay time from input power loss
Time interval error
0.1
0.8
0.3
µs
ns
216 –1 PRBS data at 100 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
11
16
5
ns
ns
ns
ns
ns
ns
ns
ns
See 图8-1
|
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.1
4.5
3
Output signal rise time
1.3
1.3
17
See 图8-1
tf
Output signal fall time
3
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
30
30
17
Enable propagation delay, high impedance-to-high output for
ISOS141 with F suffix
See 图8-2
tPZH
tPZL
tDO
tie
3.2
17
8.5
30
µs
ns
Enable propagation delay, high impedance-to-low output for
ISOS141 with F suffix
Measured from the time VCC goes
below 1.7V. See 图8-3
Default output delay time from input power loss
Time interval error
0.1
0.9
0.3
µs
ns
216 –1 PRBS data at 100 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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MAX UNIT
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
12
18.5
5.1
4.1
4.6
3.5
3.5
40
ns
ns
ns
ns
ns
ns
ns
ns
See 图8-1
|
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
Output signal rise time
1
1
See 图8-1
tf
Output signal fall time
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
22
22
40
Enable propagation delay, high impedance-to-high output for
ISOS141 with F suffix
See 图8-2
tPZH
tPZL
tDO
tie
3.3
18
8.5
40
µs
ns
Enable propagation delay, high impedance-to-low output for
ISOS141 with F suffix
Measured from the time VCC goes
below 1.7V. See 图8-3
Default output delay time from input power loss
Time interval error
0.1
0.7
0.3
µs
ns
216 –1 PRBS data at 100 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Insulation Characteristics Curves
450
1400
1200
1000
800
600
400
200
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
400
350
300
250
200
150
100
50
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D004
D002
图6-2. Thermal Derating Curve for Safety Limiting
图6-1. Thermal Derating Curve for Safety Limiting
Power for DBQ-16 Package
Current for DBQ-16 Package
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6.19 Typical Characteristics
20
9
8
7
6
5
4
3
2
1
0
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
18
16
14
12
10
8
ICC2 at 5 V
6
4
2
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D008
D007
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
图6-3. Supply Current vs Data Rate (With 15-pF 图6-4. Supply Current vs Data Rate (With No Load)
Load)
6
5
4
3
2
1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
-15
-10
High-Level Output Current (mA)
-5
0
0
5 10
Low-Level Output Current (mA)
15
D011
D012
TA = 25°C
TA = 25°C
图6-5. High-Level Output Voltage vs High-level
图6-6. Low-Level Output Voltage vs Low-Level
Output Current
Output Current
2.10
2.05
2.00
1.95
1.90
1.85
1.80
14
13
12
11
10
VCC1 Rising
VCC2 Rising
VCC1 Falling
VCC2 Falling
1.75
1.70
tPHL at 2.5 V
tPLH at 2.5 V
tPHL at 3.3 V
tPLH at 3.3 V
tPHL at 5 V
tPLH at 5 V
9
8
1.65
-55
-5
45
95
125
-55
-25
5
35
65
95
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
D013
D014
图6-7. Power Supply Undervoltage Threshold vs
图6-8. Propagation Delay Time vs Free-Air
Free-Air Temperature
Temperature
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7 Operating Life Deration
The information in this section is provided solely for your convenience and does not extend or modify the
warranty provided under TI's standard terms and conditions for TI semiconductor products.
1. Silicon operating life design goal is 100000 power-on hours (POH) at 105 °C junction temperature (does not include package
interconnect life).
2. The predicted operating lifetime versus junction temperature is based on reliability modeling using wirebond lifetime as the
dominant failure mechanism affecting device wear out for the specific device process and design characteristics.
Wirebond Life Derating Curve
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8 Parameter Measurement Information
V
CCI
V
50%
I
50%
IN
OUT
0 V
V
t
t
PHL
PLH
Input
Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr ≤3 ns, tf ≤3ns, ZO
= 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-1. Switching Characteristics Test Circuit and Voltage Waveforms
V
CCO
V
CC
R
L
= 1 kꢀ 1%
V
/ 2
CC
V
/ 2
CC
V
I
IN
OUT
0 V
V
0 V
O
t
t
PLZ
PZL
V
OH
EN
0.5 V
V
V
O
50%
C
L
OL
See Note B
Input
Generator
(See Note A)
V
I
50 ꢀ
V
CC
V
O
IN
OUT
3 V
V / 2
CC
V
/ 2
CC
V
I
0 V
t
PZH
EN
See Note B
R
L
= 1 kꢀ 1%
V
OH
C
L
50%
Input
Generator
(See Note A)
0.5 V
V
O
V
I
0 V
t
50 ꢀ
PHZ
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤10 kHz, 50% duty cycle, tr ≤3 ns, tf ≤3 ns, ZO
= 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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V
I
See Note B
V
CC
V
CC
V
1.7 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
图8-3. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CCO
CCI
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
C
L
V
or V
OL
OH
See Note A
œ
GNDO
GNDI
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-4. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISOS141-SEP has an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a
silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. If the ENx pin is low
then the output goes to high impedance. The ISOS141-SEP device also incorporates advanced circuit
techniques to maximize the CMTI performance and minimize the radiated emissions due to the high frequency
carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, 图 9-1, shows a
functional block diagram of a typical channel.
9.2 Functional Block Diagram
Transmitter
Receiver
EN
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
Copyright © 2016, Texas Instruments Incorporated
图9-1. Conceptual Block Diagram of a Digital Capacitive Isolator
图9-2 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
图9-2. On-Off Keying (OOK) Based Modulation Scheme
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9.3 Feature Description
表9-1 provides an overview of the device features.
表9-1. Device Features
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
PART NUMBER
CHANNEL DIRECTION
PACKAGE
RATED ISOLATION(1)
ISOS141-SEP
With F suffix
3 Forward,
1 Reverse
100 Mbps
Low
DBQ-16
3000 VRMS / 4242 VPK
(1) See 节6.7 for detailed isolation ratings.
9.3.1 Radiation Tolerance
Total Ionizing Dose (TID)— ISOS141-SEP is a radiation tolerant, TI Space Enhanced Plastic (Space EP)
device, and as such it has a Total Ionizing Dose (TID) level specified in the “Device Information” table on the
front page. Testing and qualification of these products is done on a wafer level according to MIL-STD-883, Test
Method 1019. Radiation Lot Acceptance Testing (RLAT) is performed at the 30-krad TID levels. A TID
characterization report is available. Group E TID RLAT data are available with lot shipments as part of the QCI
summary reports.
Single-Event Effects (SEE)— one-time SEE characterization was performed according to EIA/JEDEC
standard, EIA/JEDEC57 to linear energy transfer (LET) = 43 MeV⋅cm2/mg. During testing, no Single-Event
Latch-Up (SEL) or Single-Event Dielectric Rupture (SEDR) were observed.
Neutron Displacement Damage (NDD)— ISOS141-SEP was irradiated up to 1 × 1012 n/cm2 . A sample size of
15 units was exposed to radiation testing per MILSTD-883, Method 1017 for Neutron Irradiation.
Radiation Testing and Characterization Reports— are available for all radiation effects described in this
section, to find the latest reports go to the ISOS141-SEP Technical Documentation section on TI.com.
9.3.2 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. Although system-level performance
and reliability depends, to a large extent, on the application board design and layout, the ISOS141-SEP device
incorporates many chip-level design improvements for overall system robustness. Some of these improvements
include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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9.4 Device Functional Modes
表9-2 lists the functional modes for the ISOS141-SEP.
表9-2. Function Table
OUTPUT
ENABLE
(ENx)
INPUT
(INx)(2)
OUTPUT
(OUTx)
VCCI
VCCO
COMMENTS
H
L
H or open
H or open
H
L
Normal Operation:
A channel output assumes the logic state of its input.
PU
X
PU
PU
Default mode: When INx is open, the corresponding channel output
goes to its default logic state. Default is Low for ISOS141-SEP with F
suffix.
Open
X
H or open
L
Default
Z
A low value of output enable causes the outputs to be high-
impedance.
Default mode: When VCCI is unpowered, a channel output assumes
the logic state based on the selected default option. Default is Low for
ISOS141-SEP with F suffix.
PD
X
PU
PD
X
X
H or open
Default
When VCCI transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel
output assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined(1)
.
X
Undetermined When VCCO transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
(1) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
(2) A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
9.4.1 Device I/O Schematics
Input (ISOS141-SEP with F suffix)
V
V
V
CCI
CCI
CCI
985 ꢀ
INx
1.5 Mꢀ
Enable
Output
V
CCO
V
V
V
V
CCO
CCO
CCO
CCO
2 Mꢀ
~20 ꢀ
1970 ꢀ
OUTx
ENx
图9-3. Device I/O Schematics
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10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The ISOS141-SEP four channel digital isolator provides flexibility for multiple use cases in LEO applications.
Used in conjunction with isolated power supplies, these devices help prevent noise currents on data buses, such
as UART, SPI, RS-485, RS-232, and CAN from damaging sensitive circuitry. It can also be used to isolate
multiple static signals in a system to provide additional redundancy and robustness. When designing with digital
isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform to any
specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The
isolator is typically placed between the data controller (that is, MCU or FPGA), and a data converter or a line
transceiver, regardless of the interface type or standard.
Additionally, this digital isolator can be used as a logic-level translator in addition to providing isolation. Since an
isolation barrier separates the two sides, each side can be sourced independently with any voltage within
recommended operating conditions. The supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1
and VCC2. As an example, it is possible to supply ISOS141-SEP VCC1 with 3.3 V (which is within 2.25 V to 5.5 V)
and VCC2 with 5V (which is also within 2.25 V to 5.5 V).
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10.2 Typical Application
图 10-1 shows ISOS141-SEP in the GaN half bridge circuit being used to isolate PWM signals from the half-
bridge controller on the primary side to the half-bridge gate driver on the secondary side to achieve higher
efficiency through synchronous rectification.
La
LDO
-
15 V
+
VBUS
INA240-SEP
OUT
Output
Ls1
Ls2
Vin
OUTB
OUTA
RT
HSOUT
LSOUT
HS
LS
Half-Bridge
Driver
Feedback Network
FAULT
Lp
Vo
Ro
CS
Half-Bridge
Controller
Compensation Network
RSC
SS
Comp
VSENSE
SP
REFCAP
CS/ILIM
SRA
TPS73801-SEP
LDO
PS
SRB
GND
5 V
Rsense
Deadtime Control
Current Sense Filter
ISOS141F-SEP
TPS73801-SEP
LDO
5 V
Vcc1
Vcc2
INA
INB
OUTA
LS1OUT
LS2OUT
LS1
LS2
Half-Bridge
Driver
OUTB
INC
OUTC
IND
OUTD
Gnd1
Gnd2
Demodulator
Modulator
Isolation
图10-1. Isolated 75V to 5V 50W GaN-Based Half-Bridge Topology
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10.2.1 Design Requirements
To design with these devices, use the parameters listed in 表10-1.
表10-1. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 to 5.5 V
0.1 µF
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
10.2.2 Detailed Design Procedure
The ISOS141-SEP device only require two external bypass capacitors to operate.
2 mm maximum
from VCC1
2 mm maximum
from VCC2
0.1 µF
0.1 µF
VCC2
VCC1
1
16
GND1
GND2
2
3
15
14
INA
INB
INC
OUTA
OUTB
OUTC
13
4
12
11
10
9
5
6
7
8
IND
OUTD
EN2
EN1
GND2
GND1
图10-2. Typical ISOS141-SEP Circuit Hook-up
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10.2.3 Application Curve
The following typical eye diagrams of the ISOS141-SEP device indicates low jitter and wide open eye at the
maximum data rate of 100 Mbps.
Time = 2.5 ns / div
Time = 2.5 ns / div
图10-3. Eye Diagram at 100 Mbps PRBS 216 –1, 5 图10-4. Eye Diagram at 100 Mbps PRBS 216 –1,
V and 25°C 3.3 V and 25°C
Time = 2.5 ns / div
图10-5. Eye Diagram at 100 Mbps PRBS 216 –1, 2.5 V and 25°C
10.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 10-6 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
图 10-7 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the insulation withstand capability of DBQ-16 package is 600 VRMS with a lifetime of
>1000 years as illustrated in 图 10-7. Factors, such as package size, pollution degree, and material group can
limit the working voltage of a component.
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A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
图10-6. Test Setup for Insulation Lifetime Measurement
1.E+12
1.E+11
1.E+10
1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
87.5%
>1000 Yrs
>1000 Yrs
TDDB Line (< 1 ppm Fail Rate)
VDE Safety Margin Zone
Operating Zone
20%
200
1200
2200
3200
4200
5200
6200
7200
Applied Voltage (VRMS
)
Working Isolation Voltage = 600 VRMS
TA upto 150 oC
Projected Insulation Lifetime = >>100 Years
Applied Voltage Frequency = 60 Hz
图10-7. Insulation Lifetime Projection Data
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11 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible.
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12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see 图 12-1). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
0 ~ 4.5
r
Power plane
Low-speed traces
图12-1. Layout Example Schematic
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Radiation hardened 3.3V CAN transceiver in space enhanced plastic package with
standby mode datasheet
• Texas Instruments, Radiation hardened RS-422 dual differential drivers and receivers in space Enhanced
Plastic datasheet
• Texas Instruments, Radiation-hardened, 2.2-V to 20-V, 1-A low-noise adjustable output LDO in Space
Enhanced Plastic datasheet
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
application report
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
13.4 Trademarks
所有商标均为其各自所有者的财产。
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISOS141FDBQSEP
ISOS141FDBQTSEP
V62/21610-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SSOP
DBQ
DBQ
DBQ
DBQ
16
16
16
16
75
250
250
75
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
141FSE
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
141FSE
141FSE
141FSE
V62/21610-01XE-T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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21-Jul-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
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EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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