V62/22611-01XF_技术文档

ADC12DJ5200-EP

ZHCSQC1C –JUNE 2022 –REVISED MARCH 2023

ADC12DJ5200-EP 10.4GSPS 单通道或5.2GSPS 双通道

12 位射频采样模数转换器(ADC)

1 特性

3 描述

• 高可靠性增强型产品：

ADC12DJ5200-EP 器件是一款射频采样千兆采样模数

转换器 (ADC)，可对从直流到 10GHz 以上的输入频率

进行直接采样。 ADC12DJ5200-EP 可配置为双通道

5.2GSPS ADC 或单通道 10.4GSPS ADC。支持高达

10GHz 的可用输入频率范围，可对频率捷变系统的

L、S、C 和X 频带进行直接射频采样。

– 受控基线：一个组装和测试基地、一个制造基

地、更长的产品生命周期、更长的产品变更通知

周期和产品可追溯性

• ADC 内核：

– 12 位分辨率

– 单通道模式下的采样率高达10.4 GSPS

– 双通道模式下的采样率高达5.2 GSPS

• 性能规格：

– 本底噪声（-20 dBFS，V_FS= 1V_PP-DIFF）：

• 双通道模式：-151.8 dBFS/Hz

• 单通道模式：-154.4 dBFS/Hz

– ENOB（双通道，F_IN= 2.4 GHz）：8.6 位

• V_CMI为0V 时的缓冲模拟输入：

– 模拟输入带宽(-3dB)：8 GHz

– 可用输入频率范围：> 10 GHz

– 满量程输入电压（V_FS，默认值）：0.8 V_PP

• 无噪声孔径延迟(t_AD) 调节：

ADC12DJ5200-EP 使用具有多达 16 个串行通道的高

速JESD204C 输出接口，支持高达17.16Gbps 的线路

速率。通过 JESD204C 子类 1 支持确定性延迟和多器

件同步。JESD204C 接口可进行配置，对线路速率和

通道数进行权衡。支持 8b/10b 和 64b/66b 数据编码方

案。64b/66b 编码支持前向纠错 (FEC)，可改进误码

率。此接口向后兼容JESD204B 接收器。

无噪声孔径延迟调节和 SYSREF 窗口等创新的同步特

性可简化多通道应用的系统设计。提供可选的数字下变

频器 (DDC)，以便将数字信号频谱下变频到基带信号

并降低接口速率。可编程 FIR 滤波器可实现片上均

衡。

– 精确采样控制：19 fs 步长

– 简化同步和交错

– 温度和电压不变延迟

• 简便易用的同步特性：

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

ADC12DJ5200-EP

FCBGA (144) 10.00mm × 10.00mm

– 自动SYSREF 计时校准

– 样片标记时间戳

(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附

录。

• JESD204C 串行数据接口：

NCOA0 NCOA1 NCOB0 NCOB1 CALTRG PD

SCLK

– 最大通道速率：17.16 Gbps

– 支持64b/66b 和8b/10b 编码

– 8b/10b 模式兼容JESD204B

• 可选数字下变频器(DDC)：

SDI

SDO

SCS\

SPI Registers and

Device Control

TMSTP+

TMSTP-

DA0+

DA0-

Crossbar MUX

or Interleaving

Input

MUX

JESD204C

Link

ADC

A

INA+

INA-

Digital Down

Converter (DDC)

Block

DA7+

DA7-

Over-

range

PFIR

Block

DDC Options:

DDC Bypass

SYNCSE\

– 4 倍、8 倍、16 倍和32 倍复杂抽取

– 每个DDC 均具有四个独立的32 位NCO

• 峰值射频输入功率(Diff)：+26.5 dBm（+ 27.5

dBFS，560x 满量程功率）

• 可实现均衡的可编程FIR 滤波器

• 功耗：4W

Decimate-by-4

Decimate-by-8

Decimate-by-16

Decimate-by-32

DB0+

DB0-

INB+

INB-

Input

MUX

JESD204C

Link

ADC

B

DB7+

DB7-

Aperture

Delay Adjust

JMODE

CLK+

CLK-

Clock Distribution

and Synchronization

ORA0

ORA1

ORB0

ORB1

Status

Indicators

SYSREF+

SYSREF-

SYSREF

Windowing

CALSTAT

TDIODE+

TDIODE-

• 电源：1.1V/1.9V

ADC12DJ5200-EP 方框图

2 应用

• 宽带数字转换器

• 电子战（信号情报、电子情报）

• 卫星通信(SATCOM)

• 射频采样软件定义无线电(SDR)

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSGV2

ADC12DJ5200-EP

ZHCSQC1C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

Table of Contents

7.2 Functional Block Diagram.........................................62

7.3 Feature Description...................................................63

7.4 Device Functional Modes..........................................95

7.5 Programming.......................................................... 130

7.6 SPI Register Map....................................................132

8 Application Information Disclaimer...........................195

8.1 Application Information........................................... 195

8.2 Typical Applications................................................ 195

8.3 Initialization Set Up................................................. 199

8.4 Power Supply Recommendations...........................199

8.5 Layout..................................................................... 201

9 Device and Documentation Support..........................206

9.1 Device Support....................................................... 206

9.2 Documentation Support.......................................... 206

9.3 Receiving Notification of Documentation Updates..207

9.4 Support Resources................................................. 207

9.5 Trademarks.............................................................207

9.6 静电放电警告.......................................................... 207

9.7 术语表..................................................................... 207

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 描述................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 9

6.1 Absolute Maximum Ratings........................................ 9

6.2 ESD Ratings............................................................... 9

6.3 Recommended Operating Conditions.......................10

6.4 Thermal Information..................................................10

6.5 Electrical Characteristics: DC Specifications............ 11

6.6 Electrical Characteristics: Power Consumption........ 13

6.7 Electrical Characteristics: AC Specifications

(Dual-Channel Mode)..................................................14

6.8 Electrical Characteristics: AC Specifications

(Single-Channel Mode)............................................... 20

6.9 Timing Requirements................................................27

6.10 Switching Characteristics........................................29

6.11 Typical Characteristics............................................ 33

7 Detailed Description......................................................61

7.1 Overview...................................................................61

Information.................................................................. 207

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from February 15, 2023 to March 11, 2023 (from Revision B (February 2023) to

Revision C (March 2023))

Page

• Changed the JESD204C Transport Layer Data Formats section...................................................................101

• Changed the Ramp Test Mode to add further clarification............................................................................. 123

• Changed the superscript in CAL_LP register description table. For example, 223 changed to 2²³............... 132

Changes from July 26, 2022 to November 17, 2022 (from Revision A (July 2022) to Revision B

(November 2022))

Page

• 将文件从预告信息更改为量产数据 ................................................................................................................... 1

• Changed that ramp test pattern stops either at the end of the multiframe or at 0xFF of there are more than

256 octets in a frame in Ramp Test Mode......................................................................................................123

• Added when transport test mode output starts in Short and Long Transport Test Mode .............................. 123

• Added short test pattern for N' = 12 in Short Transport Test Pattern .............................................................123

Changes from Revision * (June 2022) to Revision A (July 2022)

Page

• Changed the Functional Block Diagram .......................................................................................................... 62

English Data Sheet: SLVSGV2

2

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5 Pin Configuration and Functions

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

AGND

INA+

INAœ

AGND

DA3+

DA3œ

DA2+

DA2œ

DGND

TMSTP+

TMSTPœ

AGND

SYNCSE

VA11

AGND

VA19

AGND

INB+

AGND

VA11

AGND

INBœ

AGND

PD

AGND

NCOA0

NCOA1

CALTRIG

CALSTAT

VD11

DA7+

ORA0

ORA1

SCS

DA7œ

VD11

DGND

VD11

DGND

VD11

DGND

VD11

DB7œ

DB3œ

DA6+

VD11

DGND

VD11

DGND

VD11

DGND

VD11

DB6+

DB2+

DA6œ

DA5+

DA5œ

DA4+

DA4œ

DB4œ

DB4+

DB5œ

DB5+

DB6œ

DB2œ

DGND

DA1+

DA1œ

DA0+

DA0œ

DB0œ

DB0+

DB1œ

DB1+

DGND

BG

VA11

AGND

VA19

CLK+

AGND

VA19

AGND

VA19

SCLK

G

H

J

CLKœ

SDI

AGND

VD11

SDO

AGND

VA11

NCOB1

NCOB0

AGND

ORB1

ORB0

DB7+

DB3+

K

SYSREF+

SYSREFœ

AGND

TDIODE+

AGND

TDIODEœ

AGND

L

AGND

M

AGND

DGND

Not to scale

图5-1. ALR Package, 144-Ball Flip Chip BGA

Top View

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Product Folder Links: ADC12DJ5200-EP

English Data Sheet: SLVSGV2

ADC12DJ5200-EP

ZHCSQC1C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

表5-1. Pin Functions

TYPE

DESCRIPTION

NAME

NO.

A1, A2, A3,

A6, A7, B2,

B3, B4, B5,

B6, B7, C6,

D1, D6, E1,

E6, F2, F3,

F6, G2, G3,

G6, H1, H6,

J1, J6, L2, L3,

L4, L5, L6, L7,

M1, M2, M3,

M6, M7

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit

board.

AGND

—

Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited

capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be

left disconnected if not used.

BG

C3

F7

E7

O

I

Foreground calibration status output or device alarm output. Functionality is programmed

through CAL_STATUS_SEL. This pin can be left disconnected if not used.

CALSTAT

CALTRIG

Foreground calibration trigger input. This pin is only used if hardware calibration triggering is

selected in CAL_TRIG_EN, otherwise software triggering is performed using

CAL_SOFT_TRIG. Tie this pin to GND if not used.

Device (sampling) clock positive input. The clock signal is strongly recommended to be AC-

coupled to this input for best performance. In single-channel mode, the analog input signal is

sampled on both the rising and falling edges. In dual-channel mode, the analog signal is

sampled on the rising edge. This differential input has an internal untrimmed 100-Ωdifferential

termination and is self-biased to the optimal input common-mode voltage as long as

DEVCLK_LVPECL_EN is set to 0.

CLK+

F1

I

Device (sampling) clock negative input. TI strongly recommends using AC-coupling for best

performance.

G1

I

CLK–

High-speed serialized data output for channel A, lane 0, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

DA0+

E12

O

High-speed serialized data output for channel A, lane 0, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

F12

C12

D12

A10

A11

A8

O

DA0–

DA1+

DA1–

DA2+

DA2–

DA3+

DA3–

High-speed serialized data output for channel A, lane 1, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 1, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized-data output for channel A, lane 2, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized-data output for channel A, lane 3, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

A9

4

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表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NO.

High-speed serialized data output for channel A, lane 4, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

DA4+

E11

O

High-speed serialized data output for channel A, lane 4, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

F11

C11

D11

B10

B11

B8

O

DA4–

DA5+

DA5–

DA6+

DA6–

DA7+

DA7–

DB0+

High-speed serialized data output for channel A, lane 5, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 5, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 6, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors. This pin can be left disconnected if not used.

High-speed serialized data output for channel A, lane 6, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 7, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel A, lane 7, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

B9

High-speed serialized data output for channel B, lane 0, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

H12

High-speed serialized data output for channel B, lane 0, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

G12

K12

J12

O

DB0–

DB1+

High-speed serialized data output for channel B, lane 1, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used.

High-speed serialized data output for channel B, lane 1, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

DB1–

High-speed serialized data output for channel B, lane 2, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

DB2+

M10

M11

O

High-speed serialized data output for channel B, lane 2, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

DB2–

High-speed serialized data output for channel B, lane 3, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

DB3+

M8

M9

O

High-speed serialized data output for channel B, lane 3, negative connection. This pin can be

left disconnected if not used.

DB3–

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Product Folder Links: ADC12DJ5200-EP

English Data Sheet: SLVSGV2

ADC12DJ5200-EP

ZHCSQC1C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NO.

High-speed serialized data output for channel B, lane 4, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

DB4+

H11

O

—

High-speed serialized data output for channel B, lane 4, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

G11

K11

J11

L10

L11

L8

DB4–

DB5+

DB5–

DB6+

DB6–

DB7+

High-speed serialized data output for channel B, lane 5, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 5, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 6, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 6, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 7, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ωdifferential

termination at the receiver. This pin can be left disconnected if not used, or connected to any

voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors.

High-speed serialized data output for channel B, lane 7, negative connection. This pin can be

left disconnected if not used, or connected to any voltage level between GND (0V) and VD11

(1.1V) using 0 OHM to 1MOHM resistors.

L9

DB7–

A12, B12, D9,

D10, F9, F10,

G9, G10, J9,

J10, L12, M12

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit

board.

DGND

Channel A analog input positive connection. INA± is recommended for use in single channel

mode for optimal performance. The differential full-scale input voltage is determined by the

FS_RANGE_A register (see the Full-Scale Voltage (V_FS) Adjustment section). This input is

terminated to ground through a 50-Ωtermination resistor. The input common-mode voltage is

typically be set to 0 V (GND) and must follow the recommendations in the Recommended

Operating Conditions table. This pin can be left disconnected if not used.

INA+

A4

A5

I

Channel A analog input negative connection. INA± is recommended for use in single channel

mode for optimal performance. See INA+ (pin A4) for detailed description. This input is

terminated to ground through a 50-Ωtermination resistor. This pin can be left disconnected if

not used.

INA–

Channel B analog input positive connection. INA± is recommended for use in single channel

mode for optimal performance. The differential full-scale input voltage is determined by the

FS_RANGE_B register (see the Full-Scale Voltage (V_FS) Adjustment section). This input is

terminated to ground through a 50-Ωtermination resistor. The input common-mode voltage

must typically be set to 0 V (GND) and must follow the recommendations in the Recommended

Operating Conditions table. This pin can be left disconnected if not used.

INB+

M4

M5

I

Channel B analog input negative connection. INA± is recommended for use in single channel

mode for optimal performance. See INB+ for detailed description. This input is terminated to

ground through a 50-Ωtermination resistor. This pin can be left disconnected if not used.

INB–

6

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English Data Sheet: SLVSGV2

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表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NO.

C7

D7

K7

LSB of NCO selection control for DDC A. NCOA0 and NCOA1 select which NCO, of a possible

four NCOs, is used for digital mixing when using a complex output JMODE. The remaining

unselected NCOs continue to run to maintain phase coherency and can be swapped in by

changing the values of NCOA0 and NCOA1 (when CMODE = 1). This pin is an asynchronous

input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more

information. Tie this pin to GND if not used.

NCOA0

NCOA1

NCOB0

I

MSB of NCO selection control for DDC A. Tie this pin to GND if not used.

LSB of NCO selection control for DDC B. NCOB0 and NCOB1 select which NCO, of a possible

four NCOs, is used for digital mixing when using a complex output JMODE. The remaining

unselected NCOs continue to run to maintain phase coherency and can be swapped in by

changing the values of NCOB0 and NCOB1 (when CMODE = 1). This pin is an asynchronous

input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more

information. Tie this pin to GND if not used.

NCOB1

ORA0

J7

I

MSB of NCO selection control for DDC B. Tie this pin to GND if not used.

Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog

input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The

minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more

information. This pin can be left disconnected if not used.

C8

O

Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog

input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The

minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more

information. This pin can be left disconnected if not used.

ORA1

ORB0

ORB1

D8

K8

J8

O

Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog

input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The

minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more

information. This pin can be left disconnected if not used.

Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog

input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The

minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more

information. This pin can be left disconnected if not used.

This pin disables all analog circuits and serializer outputs when set high for temperature diode

calibration or to reduce power consumption when the device is not being used. Tie this pin to

GND if not used.

PD

K6

F8

I

Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial

programming data in and out. The Using the Serial Interface section describes the serial

interface in more detail. Supports 1.1-V and 1.8-V CMOS levels.

SCLK

Serial interface chip select active low input. The Using the Serial Interface section describes

the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has a 82-

kΩpullup resistor to VD11.

SCS

SDI

E8

G8

I

Serial interface data input. The Using the Serial Interface section describes the serial interface

in more detail. Supports 1.1-V and 1.8-V CMOS levels.

Serial interface data output. The Using the Serial Interface section describes the serial interface

in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-

V CMOS levels during serial interface read operations. This pin can be left disconnected if not

used.

SDO

H8

O

Single-ended JESD204C SYNC signal. This input is an active low input that is used to initialize

the JESD204C serial link in 8B/10B modes when SYNC_SEL is set to 0. The 64B/66B modes

do not use the SYNC signal for initialization, however it may be used for NCO synchronization.

When toggled low in 8B/10B modes this input initiates code group synchronization (see the

Code Group Synchronization (CGS) section). After code group synchronization, this input must

be toggled high to start the initial lane alignment sequence (see the Initial Lane Alignment

Sequence (ILAS) section). A differential SYNC signal can be used instead by setting

SYNC_SEL to 1 and using TMSTP± as a differential SYNC input. Tie this pin to GND if

differential SYNC (TMSTP±) is used as the JESD204C SYNC signal.

SYNCSE

C2

I

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表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NO.

The SYSREF positive input is used to achieve synchronization and deterministic latency across

the JESD204C interface. This differential input (SYSREF+ to SYSREF–) has an internal

untrimmed 100-Ωdifferential termination and can be AC-coupled when SYSREF_LVPECL_EN

is set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination

changes to 50 Ωto ground on each input pin (SYSREF+ and SYSREF–) and can be DC-

coupled when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when

SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode

voltage range provided in the Recommended Operating Conditions table.

SYSREF+

K1

I

L1

K2

I

SYSREF negative input

SYSREF–

Temperature diode positive (anode) connection. An external temperature sensor can be

connected to TDIODE+ and TDIODE–to monitor the junction temperature of the device. This

pin can be left disconnected if not used.

TDIODE+

Temperature diode negative (cathode) connection. This pin can be left disconnected if not

used.

K3

I

TDIODE–

Timestamp input positive connection or differential JESD204C SYNC positive connection. This

input is a timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set to 1.

This differential input is used as the JESD204C SYNC signal input when SYNC_SEL is set 1.

This input can be used as both a timestamp and differential SYNC input at the same time,

allowing feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active

low signaling when used as a JESD204C SYNC. For additional usage information, see the

Timestamp section.

TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to

TMSTP–) has an internal untrimmed 100-Ωdifferential termination and can be AC-coupled

when TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ωto ground on each

input pin (TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set

to 1. This pin is not self-biased and therefore must be externally biased for both AC- and DC-

coupled configurations. The common-mode voltage must be within the range provided in the

Recommended Operating Conditions table when both AC and DC coupled. This pin can be left

disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204C SYNC

and timestamp is not required.

TMSTP+

B1

I

Timestamp input positive connection or differential JESD204C SYNC negative connection. This

pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for

JESD204C SYNC and timestamp is not required.

C1

I

TMSTP–

C5, D2, D3,

D5, E5, F5,

G5, H5, J2,

J3, J5, K5

VA11

1.1-V analog supply

1.9-V analog supply

1.1-V digital supply

C4, D4, E2,

E3, E4, F4,

G4, H2, H3,

H4, J4, K4

VA19

VD11

I

C9, C10, E9,

E10, G7, H7,

H9, H10, K9,

K10

8

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–1.32

–0.1

MAX

2.35

1.32

0.1

UNIT

V

VA19⁽²⁾

VA11⁽²⁾

V_DD

Supply voltage range

VD11⁽³⁾

Voltage between VD11 and VA11

V_GND

Voltage between AGND and DGND

V

DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–,

TMSTP+, TMSTP–⁽³⁾

VD11 +

0.5⁽⁵⁾

–0.5

–1

VA11 + 0.5⁽⁴⁾

CLK+, CLK–, SYSREF+, SYSREF–⁽²⁾

VA19 +

0.5⁽⁶⁾

BG, TDIODE+, TDIODE–⁽²⁾

V_PIN

Pin voltage range

V

INA+, INA–, INB+, INB–⁽²⁾

1

CALSTAT, CALTRIG, NCOA0, NCOA1,

NCOB0, NCOB1, ORA0, ORA1, ORB0, ORB1,

PD, SCLK, SCS, SDI, SDO, SYNCSE ⁽²⁾

VA19 +

0.5⁽⁶⁾

–0.5

I_MAX(ANY)

I_MAX(INx)

25

50

mA

Peak input current (any input except INA+, INA–, INB+, INB–)

Peak input current (INA+, INA–, INB+, INB–)

–25

–50

differential with Z_S-DIFF= 100 Ω, up to 21

26.5

16.4

100

dBm

mA

days⁽⁷⁾

P_MAX(INx)

Peak RF input power (INA+, INA–, INB+, INB–)

Single-ended with Z_S-SE= 50 Ω

Peak total input current (sum of absolute value of all currents forced in or out, not including power-

supply current)

I_MAX(ALL)

T_j

Junction temperature

Storage temperature

150

°C

T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Measured to AGND.

(3) Measured to DGND.

(4) Maximum voltage not to exceed VA11 absolute maximum rating.

(5) Maximum voltage not to exceed VD11 absolute maximum rating.

(6) Maximum voltage not to exceed VA19 absolute maximum rating.

(7) Tested continuously for 21 days with F_IN= 1.2GHz on a typical device. At the end of testing, the device was not damaged. During the

overdrive, the ADC is still properly converting the input signal, although it will be saturated for voltages beyond the input fullscale.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.8

1.05

–50

0

NOM

1.9

1.1

0

MAX

UNIT

VA19, analog 1.9-V supply⁽²⁾

2.0

1.15

100

V_DD

Supply voltage range

VA11, analog 1.1-V supply⁽²⁾

VD11, digital 1.1-V supply⁽³⁾

INA+, INA–, INB+, INB–⁽²⁾

CLK+, CLK–, SYSREF+, SYSREF–^{(2) (4)}

TMSTP+, TMSTP–^{(3) (5)}

V

mV

V

V_CMI

Input common-mode voltage

0.3

0.55

0

CLK+ to CLK–, SYSREF+ to SYSREF–,

TMSTP+ to TMSTP–

0.4

1.0

2.0

V_ID

Input voltage, peak-to-peak differential

V_PP-DIFF

0.8⁽⁶⁾

INA+ to INA–, INB+ to INB–

TDIODE+ to TDIODE–

I_{C_TD}

C_L

Temperature diode input current

BG maximum load capacitance

BG maximum output current

Input clock duty cycle

100

µA

pF

µA

%

50

100

I_O

DC

T_A

30

50

70

Operating free-air temperature

Operating junction temperature

-55

125

°C

T_J

150⁽⁽¹⁾⁾

(1) Die is designed for Tj = 150 °C operation and for device and die metallization degradation up to 150,000 POH continuous operation at

Tj = 125 °C. Prolonged use above a junction temperature of Tj =105 °C may, however, increase the package failure-in-time (FIT) rate.

(2) Measured to AGND.

(3) Measured to DGND.

(4) TI strongly recommends that CLK± be AC-coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self-bias to the optimal input

common-mode voltage for best performance. TI recommends AC-coupling for SYSREF± unless DC-coupling is required, in which

case, the LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).

(5) TMSTP± does not have internal biasing that requires TMSTP± to be biased externally whether AC-coupled with TMSTP_LVPECL_EN

= 0 or DC-coupled with TMSTP_LVPECL_EN= 1.

(6) The ADC output code saturates when V_IDfor INA± or INB± exceeds the programmed full-scale voltage(V_FS) set by FS_RANGE_A for

INA± or FS_RANGE_B for INB±.

6.4 Thermal Information

10mmx10mm FC-BGA

THERMAL METRIC⁽¹⁾

UNIT

144 PINS

23.9

0.8

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

8.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.23

8.4

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

English Data Sheet: SLVSGV2

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6.5 Electrical Characteristics: DC Specifications

typical values at T_J= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC ACCURACY

Resolution

Resolution with no missing codes

12

0.14

Bits

Maximum positive excursion from ideal step size

Maximum negative excursion from ideal step size

DNL

Differential nonlinearity

LSB

–0.13

Maximum positive excursion from ideal transfer

function

2.0

LSB

INL

Integral nonlinearity

Maximum negative excursion from ideal transfer

function

–2.4

ANALOG INPUTS (INA+, INA–, INB+, INB–)

CAL_OS = 0

CAL_OS = 1

±0.50

±0.15

mV

V_OFF

Offset error

Input offset voltage adjustment

range

Available offset correction range (see OS_CAL or

OADJ_x_INx)

V_{OFF_ADJ}

±50

mV

Foreground calibration at nominal temperature only

Foreground calibration at each temperature

18

-5.5

V_{OFF_DRIFT}

Offset drift

µV/°C

Foreground and FGOS calibration at each

temperature

0

825

Default full-scale voltage (FS_RANGE_A =

FS_RANGE_B = 0xA000)

750

975

910

560

Analog differential input full-scale

range

Maximum full-scale voltage (FS_RANGE_A =

FS_RANGE_B = 0xFFFF)

V_FS

1060

500

mV_PP

%/°C

Minimum full-scale voltage (FS_RANGE_A =

FS_RANGE_B = 0x2000)

Default FS_RANGE_A and FS_RANGE_B setting,

foreground calibration at each temperature, inputs

driven by a 50-Ωsource, includes effect of R_INdrift

Analog differential input full-scale

range drift

V_{FS_DRIFT}

0.033

Analog differential input full-scale

range matching

Matching between INA± and INB±, default setting,

dual-channel mode

V_{FS_MATCH}

R_IN

0.625%

50

Single-ended input resistance to

AGND

Each input pin is terminated to AGND, measured at

T_A= 25°C

48

52

Ω

Input termination linear temperature

coefficient

R_{IN_TEMPCO}

14.7

mΩ/°C

Single-channel mode measured at DC

Dual-channel mode measured at DC

0.4

C_IN

Single-ended input capacitance

pF

TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)

Forced forward current of 100 µA. Offset voltage

(approximately 0.792 V at 0°C) varies with process

and must be measured for each part. Offset

measurement must be done with the device

unpowered or with the PD pin asserted to minimize

device self-heating.

Temperature diode voltage slope

mV/°C

ΔV_BE

–1.65

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6.5 Electrical Characteristics: DC Specifications (continued)

typical values at T_J= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BAND-GAP VOLTAGE OUTPUT (BG)

V_BG

Reference output voltage

Reference output temperature drift

1.1

V

I_L≤100 µA

V_{BG_DRIFT}

µV/°C

–64

CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)

Differential termination with DEVCLK_LVPECL_EN

= 0, SYSREF_LVPECL_EN = 0, and

TMSTP_LVPECL_EN = 0

100

50

Z_T

Internal termination

Ω

Single-ended termination to GND (per pin) with

DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN

= 0, and TMSTP_LVPECL_EN = 0

Self-biasing common-mode voltage for CLK± when

AC-coupled (DEVCLK_LVPECL_EN must be set to

0)

0.3

Self-biasing common-mode voltage for SYSREF±

when AC-coupled (SYSREF_LVPECL_EN must be

set to 0) and with receiver enabled

Input common-mode voltage, self-

biased

0.28

V_CM

V

(SYSREF_RECV_EN = 1)

Self-biasing common-mode voltage for SYSREF±

when AC-coupled (SYSREF_LVPECL_EN must be

set to 0) and with receiver disabled

(SYSREF_RECV_EN = 0)

C_{L_DIFF}

C_{L_SE}

Differential input capacitance

Single-ended input capacitance

Between positive and negative differential input pins

Each input to ground

0.04

0.5

pF

SERDES OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)

Differential output voltage, peak-to-

peak

V_OD

540

600

650 mV_PP-DIFF

100-Ωload

V_CM

Output common-mode voltage

Differential output impedance

AC coupled

VD11 / 2

100

V

Z_DIFF

Ω

CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, NCOA0, NCOA1, NCOB0, NCOB1, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE

V_IH

V_IL

I_IH

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

required input voltage

0.7

V

0.45

40

µA

pF

V

I_IL

–40

C_I

3.4

V_OH

V_OL

High-level output voltage

Low-level output voltage

1.65

I_LOAD= –400 µA

I_LOAD= 400 µA

150

mV

English Data Sheet: SLVSGV2

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6.6 Electrical Characteristics: Power Consumption

typical values at T_J= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mA

W

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

I_VA19

I_VA11

I_VD11

P_DIS

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

934

Power mode 1: JMODE 1 (single-channel

mode, 16 lanes, 8B/10B encoding, DDC

bypassed), foreground calibration

845

1170

4.01

935

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

1050

1000

1650

4.98

mA

W

Power mode 2: JMODE 30 (single-

channel mode, 8 lanes, 64B/66B

encoding, DDC bypassed), foreground

calibration

850

1195

4.0

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

1242

1030

1265

4.90

1320

1030

1250

5.03

936

mA

W

Power mode 3: JMODE 1 (single-channel

mode, 16 lanes, 8B/10B encoding, DDC

bypassed), background calibration

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

Power mode 4: JMODE 3 (dual-channel

mode, 16 lanes, 8B/10B encoding, DDC

bypassed), background calibration

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

Power mode 5: JMODE 22 (single-

channel mode, 8 lanes, 8B/10B encoding,

4x decimation), foreground calibration

845

2350

5.3

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

1014

845

mA

W

Power mode 6: JMODE 11 (dual-channel

mode, 8 lanes, 8B/10B encoding, 4x

decimation), foreground calibration

2260

5.34

44

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

30

Power mode 7: PD pin held high, clock

disabled

56

0.18

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)

typical values at T_J= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 3, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Foreground calibration

Background calibration

8.1

Full-power input bandwidth

FPBW

XTALK

GHz

(–3 dB)⁽¹⁾

8.1

Aggressor = 1 GHz, –1 dBFS

Aggressor = 3 GHz, –1 dBFS

Aggressor = 6 GHz, –1 dBFS

–77

–71

–63

Channel-to-channel

crosstalk

dB

Errors/

sample

CER

Code error rate

Maximum CER, does not include JESD204C interface BER

10^–18

DC input noise standard

deviation

No input, foreground calibration, excludes DC offset, includes fixed

interleaving spur (f_S/ 2 spur)

NOISE_DC

2.3

LSB

Noise spectral density,

excludes fixed interleaving

spur (f_S/ 2 spur)

Maximum full-scale voltage (V_FS= 1.0 V_PP), A_IN= –20 dBFS

Default full-scale voltage (V_FS= 0.8 V_PP), A_IN= –20 dBFS

–152.0

dBFS/

Hz

NSD

NF

–150.4

23.0

22.6

55.6

55.9

56.3

57.2

55.4

55.8

56.3

Maximum full-scale voltage (V_FS= 1.0 V_PP), A_IN= –20 dBFS

Default full-scale voltage (V_FS= 0.8 V_PP), A_IN= –20 dBFS

A_IN= –1 dBFS

dB

Noise figure, Z_S= 100 Ω

A_IN= –3 dBFS

f_IN= 347 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

48

52

51

A_IN= –1 dBFS, T_A= -55℃

A_IN= –1 dBFS, T_A= 25℃

A_IN= –1 dBFS, T_A= 125℃

A_IN= –3 dBFS

54.7

f_IN= 2397 MHz

Signal-to-noise ratio,

excluding DC, HD2 to

55.2

56.2

56.3

53.0

54.0

56.0

51.4

52.6

55.6

49.6

51.1

55.2

SNR

dBFS

A_IN= –12 dBFS

HD9, f_S/ 2, f_S/ 2 –f_IN

,

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

English Data Sheet: SLVSGV2

14

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)

typical values at T_J= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 3, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

54.5

55.3

56.1

56.3

54.4

55.3

56.1

MAX

UNIT

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

46

49

48

A_IN= –1 dBFS, T_A= -55℃

A_IN= –1 dBFS, T_A= 25℃

A_IN= –1 dBFS, T_A= 125℃

A_IN= –3 dBFS

53.9

f_IN= 2397 MHz

Signal-to-noise and

54.7

56.1

55.7

51.5

53.2

55.8

48.8

51.5

55.5

46.2

49.2

55.0

SINAD

distortion ratio, excluding DC

and f_S/ 2 fixed spurs

dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)

typical values at T_J= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 3, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

8.8

8.9

9.0

9.1

8.7

8.9

9.0

MAX

UNIT

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= -12 dBFS

7.35

7.85

7.7

A_IN= –1 dBFS, T_A= -55℃

A_IN= –1 dBFS, T_A= 25℃

A_IN= –1 dBFS, T_A= 125℃

A_IN= –3 dBFS

8.7

f_IN= 2397 MHz

Effective number of bits,

excluding DC and f_S/ 2 fixed

spurs

8.8

9.0

8.3

8.5

9.0

7.8

8.3

8.9

7.4

7.9

8.8

65

67

73

67

64

69

74

65

67

73

68

59

64

73

54

61

75

50

56

71

ENOB

bits

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

52

A_IN= –3 dBFS

Spurious-free dynamic

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

SFDR

range, excluding DC and f_S

2 fixed spurs

/

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

English Data Sheet: SLVSGV2

16

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)

typical values at T_J= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 3, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

AIN = –1 dBFS

A_IN= –3 dBFS

MIN

TYP

–74

–76

–84

–76

–78

–77

–81

–72

–82

–73

–64

–69

–83

–65

–67

–79

–59

–63

–81

–65

–72

–81

–65

–76

–81

–67

–74

–84

–71

–65

–66

–79

–55

–62

–82

–50

–56

–80

MAX

UNIT

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

-58

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

2nd-order harmonic

distortion

HD2

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

AIN = –1 dBFS

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

-58

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

HD3

3rd-order harmonic distortion

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)

typical values at T_J= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 3, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

AIN = –1 dBFS

A_IN= –3 dBFS

MIN

TYP

–69

–70

–76

–71

–67

–70

–77

–68

–74

–70

–67

–68

–74

–68

–77

–61

–63

–71

MAX

UNIT

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

-52

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_S/ 2 –f_INinput signal

dependent interleaving spur

dBFS

f_S/ 2 –f_IN

f_IN= 4197 MHz

f_IN= 5997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

f_S/ 2 fixed interleaving spur,

independent of input signal

f_S/ 2

-55

dBFS

A_IN= –20 dBFS

–73

AIN = –1 dBFS

A_IN= –3 dBFS

–74

–75

–80

–76

–73

–74

–79

–74

–75

–80

–76

–71

–74

–78

–68

–72

–79

–71

–73

–78

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

-62

A_IN= –3 dBFS

Worst spur, excluding DC,

HD2, HD3, f_S/ 2 and f_S/ 2 -

f_INspurs

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

SPUR

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

English Data Sheet: SLVSGV2

18

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)

typical values at T_J= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 3, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

–78

–82

–90

–85

–82

–85

–86

–78

–83

–92

–81

–70

–75

–85

–56

–63

–91

–48

–54

–83

MAX

UNIT

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –9 dBFS per tone, V_FS= 1.0 V_PP

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –9 dBFS per tone, V_FS= 1.0 V_PP

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

f₁= 343 MHz,

f₂= 353 MHz

f₁= 993 MHz,

f₂= 1003 MHz

f₁= 2393 MHz,

f₂= 2403 MHz

3rd-order intermodulation

distortion

IMD3

dBFS

f₁= 4193 MHz,

f₂= 4203 MHz

f₁= 5993 MHz,

f₂= 6003 MHz

f₁= 7993 MHz,

f₂= 8003 MHz

(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB

below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input

bandwidth.

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)

typical values at T_A= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,

f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating junction temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Foreground calibration

Background calibration

7.9

Full-power input bandwidth

(–3 dB)⁽¹⁾

FPBW

GHz

7.9

Errors/

sample

CER

Code error rate

Maximum CER, does not include JESD204C interface BER

10^–18

DC input noise standard

deviation

No input, foreground calibration, excludes DC offset, includes fixed

interleaving spurs (f_S/ 2 and f_S/ 4 spurs), OS_CAL enabled

NOISE_DC

3.1

LSB

Noise spectral density,

excludes fixed interleaving

spurs (f_S/ 2 and f_S/ 4 spur)

Maximum full-scale voltage (V_FS= 1.0 V_PP), A_IN= –20 dBFS

Default full-scale voltage (V_FS= 0.8 V_PP), A_IN= –20 dBFS

–154.2

dBFS/

Hz

NSD

NF

–152.9

20.8

20.0

55.4

55.8

56.5

56.9

55.3

55.8

56.3

Maximum full-scale voltage (V_FS= 1.0 V_PP), A_IN= –20 dBFS

Default full-scale voltage (V_FS= 0.8 V_PP), A_IN= –20 dBFS

A_IN= –1 dBFS

dB

Noise figure, Z_S= 100 Ω

A_IN= –3 dBFS

f_IN= 347 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

48

52

51

A_IN= –1 dBFS, T_A= -55℃

A_IN= –1 dBFS, T_A= 25℃

A_IN= –1 dBFS, T_A= 125℃

A_IN= –3 dBFS

54.6

f_IN= 2397 MHz

Signal-to-noise ratio,

excluding DC, HD2 to

HD9, f_S/ 2, f_S/ 4_,f_S/ 2 –

f_IN,f_S/ 4 ± f_IN

55.3

56.4

56.2

53.0

54.0

56.0

51.4

52.7

55.8

49.5

51.0

55.4

SNR

dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

English Data Sheet: SLVSGV2

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)

typical values at T_A= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,

f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating junction temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

53.5

54.4

55.7

55.4

53.0

54.1

55.4

50.7

52.1

55.1

52.4

49.4

50.9

54.6

48.2

50.7

54.8

45.4

48.2

54.2

8.6

MAX

UNIT

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

Signal-to-noise and

distortion ratio, excluding DC

and f_S/ 2 fixed spurs

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

SINAD

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

8.7

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

9.0

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

8.9

8.5

8.7

A_IN= –3 dBFS

8.9

A_IN= –12 dBFS

A_IN= –1 dBFS

8.1

8.4

A_IN= –3 dBFS

Effective number of bits,

excluding DC and f_S/ 2 fixed

spurs

8.9

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

ENOB

bits

8.4

7.9

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

8.2

A_IN= –3 dBFS

8.8

A_IN= –12 dBFS

A_IN= –1 dBFS

7.7

8.1

A_IN= –3 dBFS

8.8

A_IN= –12 dBFS

A_IN= –1 dBFS

7.3

7.7

A_IN= –3 dBFS

8.7

A_IN= –12 dBFS

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)

typical values at T_A= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,

f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating junction temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

63

A_IN= –1 dBFS

67

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

73

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

65

61

64

A_IN= –3 dBFS

72

A_IN= –12 dBFS

A_IN= –1 dBFS

55

57

A_IN= –3 dBFS

Spurious free dynamic

range, excluding DC, f_S/ 4

and f_S/ 2 fixed spurs

67

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

SFDR

dBFS

58

55

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

57

A_IN= –3 dBFS

65

A_IN= –12 dBFS

A_IN= –1 dBFS

55

60

A_IN= –3 dBFS

70

A_IN= –12 dBFS

A_IN= –1 dBFS

51

55

A_IN= –3 dBFS

66

A_IN= –12 dBFS

A_IN= –1 dBFS

–74

–75

–88

–76

–78

–88

–76

–81

–83

–77

–71

–74

–84

–59

–64

–80

–54

–57

–74

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

-58

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

2nd-order harmonic

distortion

HD2

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

English Data Sheet: SLVSGV2

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)

typical values at T_A= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,

f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating junction temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

–63

–70

–82

–67

–65

–74

–83

–65

–71

–86

–68

–62

–68

–83

–55

–64

–83

–51

–57

–78

–66

–70

–77

–70

–62

–65

–73

–55

–56

–67

–57

–55

–57

–65

–59

–61

–71

–57

–58

–66

MAX

UNIT

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

-58

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

HD3

3rd-order harmonic distortion

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_S/ 2 –f_INinput signal

dependent interleaving spur

dBFS

f_S/ 2 –f_IN

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)

typical values at T_A= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,

f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating junction temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

–71

–73

–80

–71

–70

–77

–69

–71

–78

–70

–67

–69

–75

–67

–69

–77

–67

–68

–77

–64

–72

MAX

UNIT

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

-52

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_S/ 4 ± f_INinput signal

dependent interleaving spur

f_S/ 4 ± f_IN

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –20 dBFS, OS_CAL disabled

A_IN= –20 dBFS, OS_CAL enabled

f_S/ 2 fixed interleaving spur,

independent of input signal

f_S/ 2

f_S/ 4

dBFS

f_S/ 4 fixed interleaving spur,

independent of input signal

-55

A_IN= –20 dBFS

–67

English Data Sheet: SLVSGV2

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)

typical values at T_A= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,

f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating junction temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

–76

–75

–80

–75

–73

–74

–79

–74

–77

–82

–78

–70

–73

–77

–70

–72

–78

–66

–70

–79

MAX

UNIT

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 347 MHz

f_IN= 997 MHz

f_IN= 2397 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

-62

A_IN= –3 dBFS

Worst spur, excluding DC,

HD2, HD3, f_S/ 2, f_S/ 4, f_S/ 2

- f_IN, and f_S/ 4 ± f_IN

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

SPUR

dBFS

f_IN= 4197 MHz

f_IN= 5997 MHz

f_IN= 7997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)

typical values at T_A= 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA±,

f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default

settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR =

EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at

nominal supply voltages and over the operating junction temperature range provided in the Recommended Operating

Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

–77

–82

–92

–82

–80

–83

–85

–80

–86

–94

–82

–71

–76

–86

–59

–66

–88

–50

–57

–85

MAX

UNIT

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –9 dBFS per tone, V_FS= 1.0 V_PP

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –9 dBFS per tone, V_FS= 1.0 V_PP

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

f₁= 343 MHz,

f₂= 353 MHz

f₁= 993 MHz,

f₂= 1003 MHz

f₁= 2393 MHz,

f₂= 2403 MHz

3rd-order intermodulation

distortion

IMD3

dBFS

f₁= 4193 MHz,

f₂= 4203 MHz

f₁= 5993 MHz,

f₂= 6003 MHz

f₁= 7993 MHz,

f₂= 8003 MHz

(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB

below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input

bandwidth.

English Data Sheet: SLVSGV2

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6.9 Timing Requirements

typical values at T_J= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

MIN

NOM

MAX

UNIT

DEVICE (SAMPLING) CLOCK (CLK+, CLK–)

f_CLK

Input clock frequency (CLK±), both single-channel and dual-channel modes⁽¹⁾

t_CLK

Input clock period (CLK±), both single-channel and dual-channel modes⁽¹⁾

SYSREF (SYSREF+, SYSREF–)

800

5200

1250

MHz

ps

192.3

Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time

t_INV(SYSREF)

t_INV(TEMP)

t_INV(VA11)

48

0.02

ps

violation, as measured by SYSREF_POS status register, SYSREF_ZOOM = 1⁽³⁾

Drift of invalid SYSREF capture region over temperature, positive number indicates a

shift toward MSB of SYSREF_POS register, SYSREF_ZOOM = 1

ps/°C

ps/mV

Drift of invalid SYSREF capture region over VA11 supply voltage, positive number

indicates a shift toward MSB of SYSREF_POS register, SYSREF_ZOOM = 1

-0.03

SYSREF_ZOOM = 0

Delay of SYSREF_POS LSB⁽⁴⁾

39

24

t_STEP(SP)

ps

SYSREF_ZOOM = 1

Minimum SYSREF± assertion duration with SYSREF Windowing after SYSREF± rising

edge event

5*T_CLK+4

.5

t_{(PH_SYS)}

t_{(PL_SYS)}

ns

Minimum SYSREF± de-assertion duration with SYSREF Windowing after SYSREF±

falling edge event

5*T_CLK+4

.5

JESD204B SYNC TIMING (SYNCSE OR TMSTP±)

JMODE = 10, 21, 23

19

10

JMODE = 11, 14, 22, 24,

61

JMODE = 12, 15, 16, 25,

26, 27, 56, 57, 58, 62, 63,

66, 67, 69, 70

18

23

17

Minimum hold time from multiframe or extended

multiblock boundary (SYSREF rising edge captured high)

to de-assertion of JESD204C SYNC signal (SYNCSE if

SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) for NCO

synchronization (NCO_SYNC_ILA = 1)⁽²⁾

t_CLK

cycles

t_H(SYNCSE)

JMODE = 13

JMODE = 36, 37, 38, 52,

53, 54, 55, 59, 60, 65, 68,

71

JMODE = 39

21

9

JMODE = 46, 47, 48, 49,

64

JMODE = 10, 21, 23

–2

7

JMODE = 11, 14, 22, 24,

61

JMODE = 12, 15, 16, 25,

26, 27, 56, 57, 58, 62, 63,

66, 67, 69, 70

–1

–6

0

Minimum setup time from de-assertion of JESD204C

SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP± if

SYNC_SEL = 1) to multiframe or extended multiblock

boundary (SYSREF rising edge captured high) for NCO

synchronization (NCO_SYNC_ILA = 1)⁽²⁾

t_CLK

cycles

t_SU(SYNCSE)

JMODE = 13

JMODE = 36, 37, 38, 52,

53, 54, 55, 59, 60, 65, 68,

71

JMODE = 39

–4

8

JMODE = 46, 47, 48, 49,

64

t_(SYNCSE)

SYNCSE minimum assertion time to trigger link resynchronization

4

Frames

SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)

f_CLK(SCLK)

t_(PH)

Serial clock frequency

15.625

MHz

ns

Serial clock high value pulse duration

Serial clock low value pulse duration

Setup time from SCS to rising edge of SCLK

Hold time from rising edge of SCLK to SCS

32

30

t_(PL)

ns

t_SU(SCS)

t_H(SCS)

ns

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6.9 Timing Requirements (continued)

typical values at T_J= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

MIN

25

3

NOM

MAX

UNIT

t_SU(SDI)

t_H(SDI)

Setup time from SDI to rising edge of SCLK

Hold time from rising edge of SCLK to SDI

ns

(1) Unless functionally limited to a smaller range in the JESD204C Modes table based on programmed JMODE.

(2) This parameter only applies to JMODE settings that use 8B/10B encoding or settings that use 64B/66B encoding and 4x or 8x

decimation. SYNC is not used for 64B/66B encoding modes unless the DDC block and NCOs are used and require synchronization.

(3) Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the SYSREF Position Detector and

Sampling Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified

by t_INV(SYSREF), indicates the portion of the CLK± period(t_CLK), as measured by SYSREF_SEL, that may result in a setup and hold

violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that

used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in

SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and

SYSREF±.

(4) It is recommended to use SYSREF_ZOOM = 0 below f_CLK= 3GHz and SYSREF_ZOOM = 1 above f_CLK= 3GHz

English Data Sheet: SLVSGV2

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6.10 Switching Characteristics

typical values at T_J= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DEVICE (SAMPLING) CLOCK (CLK+, CLK–)

Sampling (aperture) delay from the CLK±

rising edge (dual-channel mode) or rising

and falling edge (single-channel mode) to

sampling instant

TAD_COARSE = 0x00, TAD_FINE =

0x00, and TAD_INV = 0

t_AD

360

289

ps

Coarse adjustment (TAD_COARSE =

0xFF)

Maximum t_ADadjust programmable delay,

t_TAD(MAX)

not including clock inversion (TAD_INV = 0)

Fine adjustment (TAD_FINE = 0xFF)

Coarse adjustment (TAD_COARSE)

Fine adjustment (TAD_FINE)

4.9

1.13

19

ps

fs

t_TAD(STEP)

t_ADadjust programmable delay step size

Minimum t_ADadjust coarse setting

(TAD_COARSE = 0x00, TAD_INV = 0),

dither disabled (ADC_DITH_EN = 0)

50

60

fs

Minimum t_ADadjust coarse setting

(TAD_COARSE = 0x00, TAD_INV = 0),

dither enabled (ADC_DITH_EN = 1)

Maximum t_ADadjust coarse setting

(TAD_COARSE = 0xFF) excluding

TAD_INV (TAD_INV = 0), dither disabled

(ADC_DITH_EN = 0)

t_AJ

Aperture jitter, rms

65⁽³⁾

Maximum t_ADadjust coarse setting

(TAD_COARSE = 0xFF) excluding

TAD_INV (TAD_INV = 0), dither enabled

(ADC_DITH_EN = 1)

74⁽³⁾

SERIAL DATA OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)

f_SERDES

UI

Serialized output bit rate

1

17.16

1000

Gbps

ps

Serialized output unit interval

58.2

20% to 80%, 8H8L test pattern, 17.16

Gbps

t_TLH

t_THL

Low-to-high transition time (differential)

High-to-low transition time (differential)

18.9

18.8

9.0

ps

20% to 80%, 8H8L test pattern, 17.16

Gbps

PRBS-7 test pattern, JMODE = 19, 12.8

Gbps

DDJ

DCD

EBUJ

RJ

Data dependent jitter, peak-to-peak

Even-odd jitter, peak-to-peak

ps

PRBS-9 test pattern, JMODE = 30,

17.16 Gbps

10.0

.33

PRBS-7 test pattern, JMODE = 19, 12.8

Gbps

PRBS-9 test pattern, JMODE = 30,

17.16 Gbps

.6

PRBS-7 test pattern, JMODE = 19, 12.8

Gbps

1.7

Effective bounded uncorrelated jitter, peak-

to-peak

PRBS-9 test pattern, JMODE = 30,

17.16 Gbps

1.93

0.85

0.88

23.3

22.6

8H8L test pattern, JMODE = 19, 12.8

Gbps

Unbounded random jitter, RMS

PRBS-9 test pattern, JMODE = 30,

17.16 Gbps

PRBS-7 test pattern, JMODE = 19, 12.8

Gbps

Total jitter, peak-to-peak, with unbounded

random jitter portion defined with respect to

a BER = 1e-15 (Q = 7.94)

TJ

PRBS-9 test pattern, JMODE = 30,

17.16 Gbps

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6.10 Switching Characteristics (continued)

typical values at T_J= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC CORE LATENCY

JMODE = 0, 30, 32

2.5

-9.5

2

JMODE = 1, 5, 19, 40, 42, 44

JMODE = 2, 31, 33

JMODE = 3, 7, 20

JMODE = 6, 50

-10

-13.5

-14

JMODE = 8, 51

JMODE = 10, 37

JMODE = 11, 47

JMODE = 12, 53

JMODE = 13, 39

JMODE = 14, 15, 49, 55

JMODE = 16

183

171

167

372

364

356

Deterministic delay from the CLK± edge

that samples the reference sample to the

CLK± edge that samples SYSREF going

high⁽¹⁾

JMODE = 21, 36

JMODE = 22, 46

JMODE = 23, 38

JMODE = 24, 48

JMODE = 25, 52

JMODE = 26, 54

JMODE = 27

148

t_ADC

142

t_CLKcycles

223.5

219.5

138

211.5

207.5

6.5

JMODE = 34

JMODE = 35

6

JMODE = 41, 43, 45

JMODE = 56, 59

JMODE = 57, 58, 60

JMODE = 61, 62, 63, 64, 65

JMODE = 66, 67, 68

JMODE = 69, 70, 71

-10.0

750

742

403.5

1514

777.5

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6.10 Switching Characteristics (continued)

typical values at T_J= 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, f_IN= 347 MHz, A_IN= –1

dBFS, f_CLK= 5.12 GHz, filtered 1-V_PPsine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and

VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1),

and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and

over the operating junction temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

JESD204C AND SERIALIZER LATENCY

JMODE = 0

92

159

93

111

182

111

188

168

215

168

103

102

166

305

165

134

119

118

JMODE = 1

JMODE = 2

JMODE = 3

159

143

191

143

85

JMODE = 5

JMODE = 6, 8, 12, 15, 25, 26

JMODE = 7, 11, 22

JMODE = 10

JMODE = 13, 21, 23

JMODE = 14, 24

JMODE = 16, 27

JMODE = 19, 20

JMODE = 30, 31

JMODE = 32, 34, 36

JMODE = 33, 35, 37

JMODE = 38

85

143

280

143

114

102

103

102

103

205

206

179

267

268

143

191

280

179

268

267

191

280

268

267

Delay from the CLK± rising edge that

samples SYSREF high to the first bit of the

multiframe (8B/10B encoding) or extended

multiblock (64B/66B encoding) on the

JESD204C serial output lane

t_TX

JMODE = 39

118 t_CLKcycles

JMODE = 40

229

200

202

291

165

213

305

199

289

212

304

288

corresponding to the reference sample of

(2)

t_ADC

JMODE = 41

JMODE = 42, 43, 48, 49

JMODE = 44, 45, 46, 47

JMODE = 50, 52, 54

JMODE = 51, 53, 55

JMODE = 56, 61

JMODE = 57, 62

JMODE = 58, 63

JMODE = 59, 64

JMODE = 60

JMODE = 65

JMODE = 66, 69

JMODE = 67, 70

JMODE = 68

JMODE = 71

SERIAL PROGRAMMING INTERFACE (SDO)

Delay from the falling edge of the 16th SCLK cycle during read operation for SDO

transition from tri-state to valid data

t_(OZD)

1

ns

t_(ODZ)

t_(OD)

Delay from the SCS rising edge for SDO transition from valid data to tri-state

Delay from the falling edge of SCLK during read operation to SDO valid

10

12

ns

1

(1) t_ADCis an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high

capture point, in which case the total latency is smaller than the delay given by t_TX

.

(2) The values given for t_TXinclude deterministic and non-deterministic delays. Over process, temperature, and voltage, the delay will

vary. JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper

receiver RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local

multiframe clock (LMFC) cycle.

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(3) t_AJincreases because of additional attenuation on the internal clock path.

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6.11 Typical Characteristics

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

2

0

-55

-57.5

-60

-2

-62.5

-65

-4

-67.5

-70

-6

-72.5

-75

-8

-10

-12

ch B to ch A

ch A to ch B

Single Channel (DES) Mode

Dual Channel Mode

-77.5

-80

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

0

2000

4000

6000

8000

10000

Input Frequency (MHz)

Dual channel mode, JMODE 3

图6-2. Crosstalk vs Input Frequency

spacer

图6-1. Input Amplitude vs Input Frequency

0.25

0.2

2

1.5

1

0.15

0.1

0.5

0

0.05

0

-0.05

-0.1

-0.15

-0.2

-0.25

-0.5

-1

-1.5

-2

0

500 1000 1500 2000 2500 3000 3500 4000

ADC Code

500 1000 1500 2000 2500 3000 3500 4000

ADC Code

D143

D144

图6-3. DNL vs ADC Code

图6-4. INL vs ADC Code

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

D080

D081

图6-5. DES Mode: Single Tone FFT at 347 MHz

图6-6. DES Mode: Single Tone FFT at 897 MHz

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

D082

D083

图6-7. DES Mode: Single Tone FFT at 2397 MHz

图6-8. DES Mode: Single Tone FFT at 4197 MHz

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

D084

D085

图6-9. DES Mode: Single Tone FFT at 5597 MHz

图6-10. DES Mode: Single Tone FFT at 7997 MHz

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-110

-120

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

D086

D087

each tone at -7 dBFS, 100MHz Tone Spacing

each tone at -7 dBFS, 100 MHz Tone Spacing

图6-12. DES Mode: Two Tone FFT at 897 MHz

图6-11. DES Mode: Two Tone FFT at 347 MHz

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

D088

D089

each tone at -7 dBFS, 100 MHz Tone Spacing

图6-13. DES Mode: Two Tone FFT at 2397 MHz

图6-14. DES Mode: Two Tone FFT at 4197 MHz

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

0

1000

2000 3000

Output Frequency (MHz)

4000

5000

D090

D091

each tone at -7 dBFS, 100 MHz Tone Spacing

图6-15. DES Mode: Two Tone FFT at 5597 MHz

each tone at -7 dBFS, 100 MHz Tone Spacing

图6-16. DES Mode: Two Tone FFT at 7997 MHz

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

500

1000 1500

Output Frequency (MHz)

2000

2500

0

500

1000 1500

Output Frequency (MHz)

2000

2500

D092

D093

图6-17. Dual Channel Mode: Single Tone FFT at 347 MHz

图6-18. Dual Channel Mode: Single Tone FFT at 897 MHz

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

500

1000 1500

Output Frequency (MHz)

2000

2500

0

500

1000 1500

Output Frequency (MHz)

2000

2500

D094

D095

图6-19. Dual Channel Mode: Single Tone FFT at 2397 MHz

图6-20. Dual Channel Mode: Single Tone FFT at 4197 MHz

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

500

1000 1500

Output Frequency (MHz)

2000

2500

0

500

1000 1500

Output Frequency (MHz)

2000

2500

D096

D097

图6-21. Dual Channel Mode: Single Tone FFT at 5597 MHz

图6-22. Dual Channel Mode: Single Tone FFT at 7997 MHz

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

500

1000 1500

Output Frequency (MHz)

2000

2500

0

500

1000 1500

Output Frequency (MHz)

2000

2500

D098

D099

each tone at -7 dBFS, 100 MHz Tone Spacing

图6-23. Dual Channel Mode: Two Tone FFT at 347 MHz

图6-24. Dual Channel Mode: Two Tone FFT at 897 MHz

36

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

500

1000 1500

Output Frequency (MHz)

2000

2500

0

500

1000 1500

Output Frequency (MHz)

2000

2500

D100

D101

each tone at -7 dBFS, 100 MHz Tone Spacing

图6-25. Dual Channel Mode: Two Tone FFT at 2397 MHz

图6-26. Dual Channel Mode: Two Tone FFT at 4197 MHz

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

500

1000 1500

Output Frequency (MHz)

2000

2500

0

500

1000 1500

Output Frequency (MHz)

2000

2500

D102

D103

each tone at -7 dBFS, 100 MHz Tone Spacing

图6-27. Dual Channel Mode: Two Tone FFT at 5597 MHz

图6-28. Dual Channel Mode: Two Tone FFT at 7997 MHz

58

57

56

55

54

56

54

52

50

53

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

52

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

48

51

50

F_IN= 5597MHz

F_IN= 7997MHz

46

2000

4000

6000

Sample Rate (MSPS)

8000

10000

2000

4000

6000

Sample Rate (MSPS)

8000

10000

A_IN= –1 dBFS

A_IN= –6 dBFS

图6-29. DES Mode: SNR vs Sample Rate and Input Frequency

图6-30. DES Mode: SNR vs Sample Rate and Input Frequency

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

58

57.5

57

70

65

60

55

50

45

40

35

30

56.5

56

55.5

55

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

54.5

54

2000

4000

6000

Sample Rate (MSPS)

8000

10000

2000

4000

6000

Sample Rate (MSPS)

8000

10000

A_IN= –12 dBFS

A_IN= –1 dBFS

图6-31. DES Mode: SNR vs Sample Rate and Input Frequency

图6-32. DES Mode: SFDR vs Sample Rate and Input Frequency

80

75

70

65

60

55

58

57

56

55

54

53

50

52

F_IN= 347MHz

45

40

35

30

51

50

49

48

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

2000

4000

6000

Sample Rate (MSPS)

8000

10000

2000

4000

6000

Sample Rate (MSPS)

8000

10000

A_IN= –6 dBFS

A_IN= –12 dBFS

图6-33. DES Mode: SFDR vs Sample Rate and Input Frequency 图6-34. DES Mode: SFDR vs Sample Rate and Input Frequency

-50

-152

Dither off

-55

Dither default

-152.5

-153

-60

-65

-70

-75

-80

-85

-90

-95

-100

-153.5

-154

-154.5

-155

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

-155.5

-156

2000

4000

6000

Sample Rate (MSPS)

8000

10000

A_IN= –1 dBFS

0

1000 2000 3000 4000 5000 6000 7000 8000

Input Frequency (MHz)

图6-35. DES Mode: HD2 vs Sample Rate and Input Frequency

JMODE 1, A_IN= –80 dBFS

图6-36. DES Mode: NSD vs Input Frequency

38

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

2000

4000

6000

Sample Rate (MSPS)

8000

10000

2000

4000

6000

Sample Rate (MSPS)

8000

10000

A_IN= –6 dBFS

A_IN= –12 dBFS

图6-37. DES Mode: HD2 vs Sample Rate and Input Frequency

图6-38. DES Mode: HD2 vs Sample Rate and Input Frequency

-50

-55

-60

-65

-70

-75

-50

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

-80

F_IN= 347MHz

-85

-90

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

-95

-100

2000

4000

6000

Sample Rate (MSPS)

8000

10000

2000

4000

6000

Sample Rate (MSPS)

8000

10000

A_IN= –1 dBFS

A_IN= –6 dBFS

图6-39. DES Mode: HD3 vs Sample Rate and Input Frequency

图6-40. DES Mode: HD3 vs Sample Rate and Input Frequency

-50

-35

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

-40

-45

-50

-55

-60

-65

-70

-75

2000

4000

6000

Sample Rate (MSPS)

8000

10000

2000

4000

6000

Sample Rate (MSPS)

8000

10000

spacer

A_IN= –12 dBFS

图6-42. DES Mode: Fs/2 - F_INvs Sample Rate and Input

图6-41. DES Mode: HD3 vs Sample Rate and Input Frequency

Frequency

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

-50

-55

-60

-65

-70

-75

-80

-85

-90

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

2000

4000

6000

Sample Rate (MSPS)

8000

10000

2000

4000

6000

Sample Rate (MSPS)

8000

10000

图6-43. DES Mode: Fs/4 + F_INvs Sample Rate and Input

图6-44. DES Mode: Fs/4 - F_INvs Sample Rate and Input

Frequency

58

56

54

52

50

58

57

56

55

54

53

52

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

48

51

50

46

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

A_IN= –1 dBFS

A_IN= –6 dBFS

图6-45. Dual Channel Mode: SNR vs Sample Rate and Input

图6-46. Dual Channel Mode: SNR vs Sample Rate and Input

Frequency

58

57

56

75

70

65

60

55

50

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

55

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

45

40

54

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

A_IN= –12 dBFS

A_IN= –1 dBFS

图6-47. Dual Channel Mode: SNR vs Sample Rate and Input

Frequency

图6-48. Dual Channel Mode: SFDR vs Sample Rate and Input

Frequency

40

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English Data Sheet: SLVSGV2

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ZHCSQC1C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

80

75

70

65

60

55

50

80

78

76

74

72

70

68

66

64

62

60

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

A_IN= –6 dBFS

A_IN= –12 dBFS

图6-49. Dual Channel Mode: SFDR vs Sample Rate and Input

图6-50. Dual Channel Mode: SFDR vs Sample Rate and Input

Frequency

-50

-55

-60

-65

-70

-75

-80

-85

-90

-148

Ch A, Dither off

Ch A, Dither on

Ch B, Dither off

Ch B, Dither on

-148.5

-149

-149.5

-150

-150.5

-151

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

-151.5

-152

-95

-100

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

-152.5

-153

A_IN= –1 dBFS

0

1000 2000 3000 4000 5000 6000 7000 8000

Input Frequency (MHz)

图6-52. Dual Channel Mode: HD2 vs Sample Rate and Input

JMODE 3, A_IN= –80 dBFS

Frequency

图6-51. Dual Channel Mode: NSD and Input Frequency

-50

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

A_IN= –6 dBFS

A_IN= –12 dBFS

图6-53. Dual Channel Mode: HD2 vs Sample Rate and Input

图6-54. Dual Channel Mode: HD2 vs Sample Rate and Input

Frequency

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English Data Sheet: SLVSGV2

ADC12DJ5200-EP

ZHCSQC1C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

A_IN= –1 dBFS

A_IN= –6 dBFS

图6-55. Dual Channel Mode: HD3 vs Sample Rate and Input

图6-56. Dual Channel Mode: HD3 vs Sample Rate and Input

Frequency

-50

-75

-80

-85

-90

-95

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

-100

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

图6-58. Dual Channel Mode: Fs/2 - F_INvs Sample Rate and

A_IN= –12 dBFS

Input Frequency

图6-57. Dual Channel Mode: HD3 vs Sample Rate and Input

Frequency

58

57

56

55

54

60

59

58

57

56

55

54

53

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz, Dither off

53

52

51

50

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

52

51

50

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-59. DES Mode: SNR vs Input Amplitude and Frequency

图6-60. DES Mode: SNR vs Input Amplitude and Dither

42

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English Data Sheet: SLVSGV2

ADC12DJ5200-EP

ZHCSQC1C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz, Dither off

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-61. DES Mode: SFDR vs Input Amplitude and Frequency

图6-62. DES Mode: SFDR vs Input Amplitude and Dither

-60

F_IN= 347MHz

F_IN= 897MHz

F_IN= 347MHz, Dither off

F_IN= 347MHz, Dither on

-65

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

-70

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

-75

-80

-75

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

-80

-70

-60

-50

Input Ampitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-63. DES Mode: HD2 vs Input Amplitude and Frequency

图6-64. DES Mode: HD2 vs Input Amplitude and Dither

-50

-40

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 347MHz, Dither off

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

-55

-50

-60

-70

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

-65

-70

-75

-80

-85

-90

-95

-100

-80

-90

-100

-110

-80

-70

-60

-50

Input Ampitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-65. DES Mode: HD3 vs Input Amplitude and Frequency

图6-66. DES Mode: HD3 vs Input Amplitude and Dither

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Product Folder Links: ADC12DJ5200-EP

English Data Sheet: SLVSGV2

ADC12DJ5200-EP

ZHCSQC1C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

-50

-60

-40

-50

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz, Dither off

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

-70

-60

-80

-70

-90

-80

-100

-110

-120

-90

-100

-110

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-67. DES Mode: Fs/2 - F_INvs Input Amplitude and Frequency

图6-68. DES Mode: Fs/2 - F_INvs Input Amplitude and Dither

-60

-40

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 347MHz, Dither off

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

-65

-50

-70

-60

-70

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

-75

-80

-85

-80

-90

-95

-90

-100

-105

-110

-100

-110

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-69. DES Mode: Fs/4 + F_INvs Input Amplitude and

图6-70. DES Mode: Fs/4 + F_INvs Input Amplitude and Dither

Frequency

-60

-40

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 347MHz, Dither off

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

-65

-50

-70

-60

-70

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

-75

-80

-85

-80

-90

-95

-90

-100

-105

-110

-100

-110

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-71. DES Mode: Fs/4 - F_INvs Input Amplitude and Frequency

图6-72. DES Mode: Fs/4 - F_INvs Input Amplitude and Dither

44

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Product Folder Links: ADC12DJ5200-EP

English Data Sheet: SLVSGV2

ADC12DJ5200-EP

ZHCSQC1C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

58

57

56

55

54

53

52

51

50

60

59

58

57

56

55

54

53

52

51

50

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz, Dither off

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-73. Dual Channel Mode: SNR vs Input Amplitude and

图6-74. Dual Channel Mode: SNR vs Input Amplitude and Dither

Frequency

85

80

75

70

90

85

80

75

70

65

F_IN= 347MHz

F_IN= 347MHz, Dither off

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

60

55

50

60

55

50

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-75. Dual Channel Mode: SFDR vs Input Amplitude and

图6-76. Dual Channel Mode: SFDR vs Input Amplitude and

Frequency

Dither

-50

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz, Dither off

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

-55

-60

-70

-60

-65

-70

-75

-80

-85

-90

-95

-100

-80

-90

-100

-110

-80

-70

-60

-50

Input Ampitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-77. Dual Channel Mode: HD2 vs Input Amplitude and

图6-78. Dual Channel Mode: HD2 vs Input Amplitude and Dither

Frequency

Submit Document Feedback

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Product Folder Links: ADC12DJ5200-EP

English Data Sheet: SLVSGV2

ADC12DJ5200-EP

ZHCSQC1C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

-50

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz, Dither off

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

-60

-70

-80

-90

-100

-110

-80

-70

-60

-50

Input Ampitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-79. Dual Channel Mode: HD3 vs Input Amplitude and

图6-80. Dual Channel Mode: HD3 vs Input Amplitude and Dither

Frequency

-60

-70

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz, Dither off

-65

F_IN= 347MHz, Dither on

F_IN= 2397MHz, Dither off

F_IN= 2397MHz, Dither on

F_IN= 5597MHz, Dither off

F_IN= 5597MHz, Dither on

-75

-80

-70

-75

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

-80

-70

-60

-50

Input Amplitude (dBFS)

-40

-30

-20

-10

0

图6-81. Dual Channel Mode: Fs/2 - F_INvs Input Amplitude and

图6-82. Dual Channel Mode: Fs/2 - F_INvs Input Amplitude and

Frequency

Dither

56

54

52

50

48

70

65

60

55

50

46

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

44

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

42

40

F_IN= 5597MHz

F_IN= 7997MHz

45

0.2

0.4

0.6

0.8

1

Clock Amplitude (V)

1.2

1.4

1.6

1.8

2

0.4

0.6

0.8

1

Clock Amplitude (V)

1.2

1.4

1.6

1.8

2

图6-83. DES Mode: SNR vs Clock Amplitude

图6-84. DES Mode: SFDR vs Clock Amplitude

English Data Sheet: SLVSGV2

46

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Product Folder Links: ADC12DJ5200-EP

ADC12DJ5200-EP

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

56

54

52

50

48

46

44

42

40

70

65

60

55

50

45

40

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

F_IN= 347MHz

F_IN= 897MHz

F_IN= 2397MHz

F_IN= 4197MHz

F_IN= 5597MHz

F_IN= 7997MHz

0.2

0.4

0.6

0.8

1

Clock Amplitude (V)

1.2

1.4

1.6

1.8

2

0.2

0.4

0.6

0.8

1

Clock Amplitude (V)

1.2

1.4

1.6

1.8

2

图6-85. Dual Channel Mode: SNR vs Clock Amplitude

图6-86. Dual Channel Mode: SFDR vs Clock Amplitude

66

56

55

54

53

52

51

50

49

48

SFDR

SINAD

SNR

64

62

60

58

56

54

52

50

BG

FG

FG25

LPBG

47

46

-80 -60 -40 -20

0

20 40 60 80 100 120 140

-80 -60 -40 -20

0

20 40 60 80 100 120 140

Temperature (èC)

FG calibration at each temperature

FG25 is calibrated at 25°C and held at other temperatures,

other modes recalibrated at each temperature

图6-87. DES Mode: SNR, SINAD and SFDR vs Temperature

图6-88. DES Mode: SNR vs Temperature and Calibration Mode

-60

70

HD2

HD3

non-HD spur

BG

FG

FG25

LPBG

-62

68

-64

66

64

-66

-68

-70

-72

-74

-76

-78

-80

62

60

58

56

54

52

50

-80 -60 -40 -20

0

20 40 60 80 100 120 140

-80 -60 -40 -20

0

20 40 60 80 100 120 140

Temperature (èC)

FG calibration at each temperature

FG25 is calibrated at 25°C and held at other temperatures,

other modes recalibrated at each temperature

图6-89. DES Mode: HD2, HD3 and Worst non-HD Spur vs

Temperature

图6-90. DES Mode: SFDR vs Temperature and Calibration Mode

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

56

55

54

53

52

51

50

49

48

47

46

70

68

66

64

62

60

58

56

54

52

50

SFDR

SINAD

SNR

BG

FG

FG25

LPBG

-80 -60 -40 -20

0

20 40 60 80 100 120 140

Temperature (èC)

-80 -60 -40 -20

0

20 40 60 80 100 120 140

Temperature (èC)

FG25 is calibrated at 25°C and held at other temperatures,

other modes recalibrated at each temperature

FG calibration at each temperature

图6-92. Dual Channel Mode: SNR vs Temperature and

图6-91. Dual Channel Mode: SNR, SINAD and SFDR vs

Calibration Mode

Temperature

-60

70

HD2

HD3

non-HD spur

BG

FG

FG25

LPBG

-62

68

-64

66

64

-66

-68

-70

-72

-74

-76

-78

-80

62

60

58

56

54

52

50

-80 -60 -40 -20

0

20 40 60 80 100 120 140

-80 -60 -40 -20

0

20 40 60 80 100 120 140

Temperature (èC)

FG calibration at each temperature

FG25 is calibrated at 25°C and held at other temperatures,

other modes recalibrated at each temperature

图6-93. Dual Channel Mode: HD2, HD3 and Worst non-HD Spur

vs Temperature

图6-94. Dual Channel Mode: SFDR vs Temperature and

Calibration Mode

64

-60

SFDR

SINAD

SNR

HD2

HD3

non-HD Spur

-62

-64

-66

-68

-70

-72

-74

-76

62

60

58

56

54

52

50

-0.05

-0.025

Supply Voltage (% Variation from Nominal)

0

0.025

0.05

-0.05

-0.025

Supply Voltage (% Variation from Nominal)

0

0.025

0.05

All supplies varied together

图6-95. DES Mode: SNR, SINAD and SFDR vs Supply Voltage

图6-96. DES Mode: HD2, HD3 and Worst non-HD Spur vs

Supply Voltage

48

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

-64

-66

-68

-70

-72

-74

-76

72

70

68

66

64

62

60

58

56

54

52

HD2

HD3

non-HD Spur

SFDR

SINAD

SNR

-0.05

-0.025

0

0.025

Supply Voltage (% Variation from Nominal)

0.05

-0.05

-0.025

0

0.025

Supply Voltage (% Variation from Nominal)

0.05

All supplies varied together

图6-98. Dual Channel Mode: HD2, HD3 and Worst non-HD Spur

vs Supply Voltage

图6-97. Dual Channel Mode: SNR, SINAD and SFDR vs Supply

Voltage

70

65

60

55

50

45

40

35

-40

Fs/2 - Fin

Fs/4 - Fin

Fs/4 + Fin

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

30

SFDR

SINAD

SNR

25

20

-0.4

-0.3

-0.2

Input Common Mode Voltage (V)

-0.1

0

0.1

0.2

0.3

0.4

-0.4

-0.3

-0.2

Input Common Mode Voltage (V)

-0.1

0

0.1

0.2

0.3

0.4

D141

D142

图6-99. SNR, SFDR and SINAD vs Input Common Mode Voltage

图6-100. Fs/2 - F_INand Fs/4 ± F_INvs Input Common Mode

Voltage

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

F_IN= 347MHz

F_IN= 4197MHz

F_IN= 7997MHz

-50

-60

-70

-80

-90

-100

-110

-80

-70

-60

-50

-40

-30

Input Amplitude (dBFS)

-20

-10

0

1000 2000 3000 4000 5000 6000 7000 8000

Input Frequency (MHz)

spacer

each tone at -7dBFS

图6-102. DES Mode: IMD3 vs Input Amplitude

图6-101. DES Mode: IMD3 vs Input Frequency

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

75

70

65

60

55

50

45

347MHz/-12dBFS

347MHz/-7dBFS

4197MHz/-12dBFS

4197MHz/-7dBFS

7997MHz/-12dBFS

7997MHz/-7dBFS

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Tone Spacing (MHz)

0

1000 2000 3000 4000 5000 6000 7000 8000

Center Frequency (MHz)

each tone at -7dBFS

图6-103. DES Mode: IMD3 vs Tone Spacing

图6-104. DES Mode: Two Tone SFDR vs Input Frequency

85

82.5

80

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

77.5

75

72.5

70

67.5

65

62.5

60

57.5

55

F_IN= 347MHz

F_IN= 4197MHz

F_IN= 7997MHz

52.5

50

47.5

-80

-70 -60

-50

-40

-30

Input Amplitude (dBFS)

-20

-10

0

1000 2000 3000 4000 5000 6000 7000 8000

Input Frequency (MHz)

spacer

each tone at -7dBFS

图6-105. DES Mode: Two Tone SFDR vs Input Amplitude

图6-106. Dual Chanel Mode: IMD3 vs Input Frequency

-40

0

F_IN= 347MHz

F_IN= 4197MHz

F_IN= 7997MHz

347MHz/-12dBFS

347MHz/-7dBFS

4197MHz/-12dBFS

4197MHz/-7dBFS

7997MHz/-12dBFS

7997MHz/-7dBFS

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-50

-60

-70

-80

-90

-100

-110

-80

-70

-60

-50

-40

-30

Input Amplitude (dBFS)

-20

-10

0

100 200 300 400 500 600 700 800 900 1000

Tone Spacing (MHz)

图6-107. Dual Chanel Mode: IMD3 vs Input Amplitude

图6-108. Dual Chanel Mode: IMD3 vs Tone Spacing

50

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

75

70

65

60

55

50

45

85

82.5

80

77.5

75

72.5

70

67.5

65

62.5

60

57.5

55

52.5

50

47.5

45

F_IN= 347MHz

F_IN= 4197MHz

F_IN= 7997MHz

0

1000 2000 3000 4000 5000 6000 7000 8000

Center Frequency (MHz)

-80

-70

-60

-50

-40

Input Amplitude (dBFS)

-30

-20

-10

图6-109. Dual Chanel Mode: Two Tone SFDR vs Input

图6-110. Dual Chanel Mode: Two Tone SFDR vs Input

Frequency

Amplitude

1.25

1.2

1.15

1.1

1.05

1

0.95

0.9

0.85

0.8

BG

FG

LPBG

0.75

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

JMode

D125

All modes capable of F_S= 10.4GSPS

图6-111. DES Mode: I_VA19vs JMODE at 10.4GSPS

1.25

1.2

BG

FG

LPBG

1.15

1.1

1.05

1

0.95

0.9

0.85

0.8

0.75

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

JMode

D126

All modes capable of F_S= 10.4GSPS

图6-112. DES Mode: I_VA11vs JMODE at 10.4GSPS

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

2.5

2.25

2

1.75

1.5

1.25

1

0.75

0.5

BG

FG

LPBG

0.25

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70 75

JMode

D127

All modes capable of F_S= 10.4GSPS

图6-113. DES Mode: I_VD11vs JMODE at 10.4GSPS

7

6

5

4

3

2

1

0

BG

FG

LPBG

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

JMode

D128

All modes capable of F_S= 10.4GSPS

图6-114. DES Mode: Power Dissipation vs JMODE at 10.4GSPS

1.5

1.45

1.4

BG

FG

LPBG

1.35

1.3

1.25

1.2

1.15

1.1

1.05

1

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

JMode

D129

All modes capable of F_S= 5.2GSPS

图6-115. Dual Channel Mode: I_VA19vs JMODE at 5.2GSPS

English Data Sheet: SLVSGV2

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

1.25

1.2

1.15

BG

FG

LPBG

1.1

1.05

1

0.95

0.9

0.85

0.8

0.75

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

JMode

D130

All modes capable of F_S= 5.2GSPS

图6-116. Dual Channel Mode: I_VA11vs JMODE at 5.2GSPS

2.5

2.25

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

BG

FG

LPBG

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

JMode

D131

All modes capable of F_S= 5.2GSPS

图6-117. Dual Channel Mode: I_VD11vs JMODE at 5.2GSPS

7

6

5

4

3

2

1

BG

FG

LPBG

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

JMode

D132

All modes capable of F_S= 5.2GSPS

图6-118. Dual Channel Mode: Power Dissipation vs JMODE at 5.2GSPS

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

1.4

1.2

1

0.8

0.6

0.4

0.2

0

BG

FG

LPBG

0

5

10

15

20

JMode

25

30

35

40

D133

At maximum possible sample rate per 表7-23

图6-119. Other Modes with Lower Maximum F_S: I_VA19vs JMODE

1

0.95

0.9

0.85

0.8

0.75

0.7

0.65

0.6

BG

FG

LPBG

0.55

0.5

0

5

10

15

20

JMode

25

30

35

40

D134

At maximum possible sample rate per 表7-23

图6-120. Other Modes with Lower Maximum F_S: I_VA11vs JMODE

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

BG

FG

LPBG

0

5

10

15

20

JMode

25

30

35

40

D135

At maximum possible sample rate per 表7-23

图6-121. Other Modes with Lower Maximum F_S: I_VD11vs JMODE

English Data Sheet: SLVSGV2

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6.11 Typical Characteristics

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

7

6

5

4

3

2

BG

FG

1

LPBG

0

5

10

15

20

JMode

25

30

35

40

D136

At maximum possible sample rate per 表7-23

图6-122. Other Modes with Lower Maximum F_S: Power Dissipation vs JMODE

1.4

1.2

1

1.2

1

0.8

0.6

0.4

0.8

0.6

0.4

0.2

0

BG

FG

LPBG

BG

FG

LPBG

0.2

0

2000

4000

6000

Sample Rate (MSPS)

8000

10000

4000

6000

Sample Rate (MSPS)

8000

10000

independent of JMODE

图6-123. DES Mode: I_VA19vs Sample Rate

independent of JMODE

图6-124. DES Mode: I_VA11vs Sample Rate

2

1.4

1.75

1.2

1

1.5

1.25

1

0.8

0.6

0.4

0.2

0.75

0.5

0.25

0

BG

FG

LPBG

BG

FG

LPBG

2000

3000

4000 5000

Sample Rate (MSPS)

6000

7000

D108

2000

4000

6000

Sample Rate (MSPS)

8000

10000

JMODE 21

JMODE 1

图6-126. DES Mode: I_VD11vs Sample Rate

图6-125. DES Mode: I_VD11vs Sample Rate

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

1.3

1.2

1.1

1

2

1.8

1.6

1.4

1.2

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.8

0.6

0.4

0.2

0

BG

FG

LPBG

BG

FG

LPBG

2000

4000

6000

Sample Rate (MSPS)

8000

10000

2000

4000

6000

Sample Rate (MSPS)

8000

10000

D109

D110

JMODE 30

JMODE 61

图6-127. DES Mode: I_VD11vs Sample Rate

图6-128. DES Mode: I_VD11vs Sample Rate

5

4.5

4

5

4.5

4

3.5

3

3.5

3

2.5

2

2.5

2

1.5

1

BG

FG

LPBG

BG

FG

LPBG

0.5

0

0.5

0

2000

4000

6000

Sample Rate (MSPS)

8000

10000

2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 7000

Sample Rate (MSPS)

D111

D112

JMODE 1

JMODE 21

图6-129. DES Mode: Power Dissipation vs Sample Rate

图6-130. DES Mode: Power Dissipation vs Sample Rate

5

4.5

4

6

5

4

3

2

3.5

3

2.5

2

1.5

1

BG

FG

LPBG

BG

FG

LPBG

1

0.5

0

2000

4000

6000

Sample Rate (MSPS)

8000

10000

4000

6000

Sample Rate (MSPS)

8000

10000

D113

D114

JMODE 30

JMODE 61

图6-131. DES Mode: Power Dissipation vs Sample Rate

图6-132. DES Mode: Power Dissipation vs Sample Rate

56

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

1.5

1.45

1.4

1.2

BG

FG

LPBG

1

1.35

1.3

0.8

0.6

0.4

0.2

0

1.25

1.2

1.15

1.1

BG

FG

LPBG

1.05

1

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

D115

D116

independent of JMODE

图6-133. Dual Channel Mode: I_VA19vs Sample Rate

图6-134. Dual Channel Mode: I_VA11vs Sample Rate

1.4

2.5

1.2

1

2

1.5

1

0.8

0.6

0.4

0.2

0.5

BG

FG

BG

FG

LPBG

0

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

0

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

D117

D118

JMODE 3

JMODE 11

图6-135. Dual Channel Mode: I_VD11vs Sample Rate

图6-136. Dual Channel Mode: I_VD11vs Sample Rate

1.4

2

1.75

1.5

1.2

1

1.25

1

0.8

0.6

0.75

0.4

0.2

0.5

BG

FG

LPBG

BG

FG

LPBG

0.25

0

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

D119

D120

JMODE 31

JMODE 59

图6-137. Dual Channel Mode: I_VD11vs Sample Rate

图6-138. Dual Channel Mode: I_VD11vs Sample Rate

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

BG

FG

LPBG

BG

FG

LPBG

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

D121

D122

JMODE 3

JMODE 11

图6-139. Dual Channel Mode: Power Dissipation vs Sample

图6-140. Dual Channel Mode: Power Dissipation vs Sample

Rate

6

5

4

3

2

6

5

4

3

2

BG

FG

LPBG

BG

FG

LPBG

1

0

1

0

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

1000 1500 2000 2500 3000 3500 4000 4500 5000 5500

Sample Rate (MSPS)

D123

D124

JMODE 31

JMODE 59

图6-141. Dual Channel Mode: Power Dissipation vs Sample

图6-142. Dual Channel Mode: Power Dissipation vs Sample

Rate

1000

800

4.6

4.55

4.5

Zoomed area in following plot

600

400

4.45

4.4

200

4.35

4.3

0

4.25

4.2

-200

-400

-600

-800

-1000

4.15

4.1

4.05

JMODE 1 (DES)

JMODE 3

4

3.95

0

10000

20000

30000

Sample #

40000

50000

60000

D137

-80 -60 -40 -20

0

20 40 60 80 100 120 140

Temperature (èC)

图6-144. Background Calibration Core Transition (AC Signal)

图6-143. Power Dissipation vs Temperature

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

2048

1536

1024

512

Zoomed area in following plot

0

-512

-1024

-1536

-2048

34000

34200

34400

34600

34800

35000

D138

0

10000 20000 30000 40000 50000 60000

Sample #

D139

图6-145. Background Calibration Core Transition (AC Signal -

图6-146. Background Calibration Core Transition (DC Signal)

zoomed)

1900

1880

1860

1840

1820

1800

1780

1760

1740

1720

8000

ADC output code

Zoomed area

in next plot

Input pulse (8 GHz BW)

7000

6000

5000

4000

3000

2000

1000

0

1700

25000 27500 30000 32500 35000 37500 40000 42500 45000

Sample #

D140

-6000

-2000

2000

6000

Time (ps)

10000

14000

图6-147. Background Calibration Core Transition (DC Signal -

zoomed)

图6-148. Pulse Overdrive Recovery

7000

11000

10000

9000

8000

7000

6000

5000

4000

3000

2000

1000

ADC output code

Input pulse (8 GHz BW)

6000

5000

4000

3000

2000

Zoomed area

in next plot

ADC Output Code

Matched Sinewave

1000

5600 5620 5640 5660 5680 5700 5720 5740 5760 5780 5800

Time (ps)

0

25

50

75

100 125 150 175 200 225

Time (ps)

图6-149. Pulse Overdrive Recovery Zoomed

图6-150. Sinewave Overdrive Recovery

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6.11 Typical Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), input signal applied to INA± in single-channel modes, f_IN= 347 MHz, A_IN= –1 dBFS, f_CLK= maximum-rated clock

frequency, filtered, 1-V_PPsine-wave clock, JMODE = 1, dither enabled with default settings, VA11, VD11 and VS11 noise

suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and

background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD,

ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs

4500

ADC Output Code

Matched Sinewave

4000

3500

3000

2500

2000

1500

30

35

40

45

50

55

60

65

70

Time (ps)

图6-151. Sinewave Overdrive Recovery

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7 Detailed Description

7.1 Overview

ADC12DJ5200-EP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly

sample input frequencies from DC to above 10 GHz. In dual-channel mode, the device can sample up to 5.2

GSPS and up to 10.4 GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel

mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the

needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input

bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-

channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The device uses a high-speed JESD204C output interface with up to 16 serialized lanes and subclass-1

compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to

17.16 Gbps and can be configured to trade-off bit rate and number of lanes. Both 8B/10B and 64B/66B data

encoding schemes are supported. The 64B/66B encoding schemes support forward error correction (FEC) for

improved bit error rates. The JESD204C interface is backwards compatible with JESD204B receivers when

using 8B/10B encoding modes.

A number of synchronization features, including noiseless aperture delay (t_AD) adjustment and SYSREF

windowing, simplify system design for multi-channel systems. Aperture delay adjustment can be used to simplify

SYSREF capture, to align the sampling instance between multiple ADCs or to sample an ideal location of a front-

end track and hold (T&H) amplifier output. SYSREF windowing offers a simplistic way to measure invalid timing

regions of SYSREF relative to the device clock and then choose an optimal sampling location. Dual-edge

sampling (DES) is implemented in single-channel mode to reduce the maximum clock rate applied to the ADC to

support a wide range of clock sources and relax setup and hold timing for SYSREF capture.

The device provides foreground and background calibration options for gain, offset and static linearity errors.

Foreground calibration is run at system start up or at specified times during which the ADC is offline and not

sending data to the logic device. Background calibration allows the ADC to run continually while the cores are

calibrated in the background so that the system does not experience downtime. The calibration routine is also

used to match the gain and offset between sub-ADC cores to minimize spurious artifacts from time interleaving.

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7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Device Comparison

The devices listed in 表 7-1 are part of a pin-to-pin compatible, high-speed, wide-bandwidth ADC family. The

family is offered to provide a scalable family of devices for varying resolution, sampling rate and signal

bandwidth.

表7-1. Device Family Comparison

MAXIMUM

SAMPLING RATE

DUAL CHANNEL

DECIMATION

SINGLE CHANNEL

DECIMATION

INTERFACE

(MAX LINERATE)

PART NUMBER

RESOLUTION

ADC12DJ5200RF

ADC12DJ5200-EP

ADC12DJ5200-SP

JESD204B /

JESD204C

(17.16 Gbps)

Single 10.4 GSPS

Dual 5.2 GSPS

12-bit

Complex: 4x, 8x, 16x, 32x Complex: 4x, 8x, 16x, 32x

JESD204B /

JESD204C

(17.16 Gbps)

Single 10.4 GSPS

Dual 5.2 GSPS

ADC08DJ5200RF

ADC12DJ4000RF

8-bit

None

JESD204B /

JESD204C

(17.16 Gbps)

Single 8 GSPS

Dual 4 GSPS

12-bit

Complex: 4x, 8x

Single 6.4 GSPS

Dual 3.2 GSPS

Real: 2x

Complex: 4x, 8x, 16x

JESD204B

(12.8 Gbps)

ADC12DJ3200

ADC08DJ3200

ADC12DJ2700

12-bit

8-bit

None

Single 6.4 GSPS

Dual 3.2 GSPS

JESD204B

(12.8 Gbps)

None

Single 5.4 GSPS

Dual 2.7 GSPS

Real: 2x

Complex: 4x, 8x, 16x

JESD204B

(12.8 Gbps)

12-bit

7.3.2 Analog Inputs

The analog inputs of the device have internal buffers to enable high input bandwidth and to isolate sampling

capacitor glitch noise from the input circuit. Analog inputs must be driven differentially because operation with a

single-ended signal results in degraded performance. Both AC-coupling and DC-coupling of the analog inputs is

supported. The analog inputs are designed for an input common-mode voltage (V_CMI) of 0 V, which is terminated

internally through single-ended, 50-Ω resistors to ground (GND) on each input pin. DC-coupled input signals

must have a common-mode voltage that meets the device input common-mode requirements specified as V_CMI

in the Recommended Operating Conditions table. The 0-V input common-mode voltage simplifies the interface

to split-supply, fully-differential amplifiers and to a variety of transformers and baluns. The device includes

internal analog input protection to protect the ADC inputs during overranged input conditions; see the Analog

Input Protection section. 图7-1 provides a simplified analog input model.

AGND

Analog Input

Protection

Diodes

50 ꢀ

INA+, INB+

ADC

INAœ, INBœ

Input Buffer

50 ꢀ

图7-1. ADC12DJ5200-EP Analog Input Internal Termination and Protection Diagram

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There is minimal degradation in analog input bandwidth when using single-channel mode versus dual-channel

mode. Either analog input (INA+ and INA– or INB+ and INB–) can be used in single-channel mode. The

desired input can be chosen using SINGLE_INPUT in the input mux control register. A calibration needs to be

performed after switching the input mux for the changes to take effect. Further, two inputs can be used in single-

channel mode to drive the interleaved ADCs separately using the SINGLE_INPUT register setting. This mode is

called dual-input single-channel mode. Dual-input single-channel mode is equivalent to dual channel mode,

except ADC B samples out-of-phase with ADC A (single-channel mode sample timing). This mode is available

when a single-channel mode JMODE setting is chosen.

7.3.2.1 Analog Input Protection

The analog inputs are protected against overdrive conditions by internal clamping diodes that are capable of

sourcing or sinking input currents during overrange conditions, see the voltage and current limits in the Absolute

Maximum Ratings table. The overrange protection is also defined for a peak RF input power in the Absolute

Maximum Ratings table, which is frequency independent. Operation above the maximum conditions listed in the

Recommended Operating Conditions table results in an increase in failure-in-time (FIT) rate, so the system must

correct the overdrive condition as quickly as possible. 图7-1 shows the analog input protection diodes.

7.3.2.2 Full-Scale Voltage (V_FS) Adjustment

Input full-scale voltage (V_FS) adjustment is available, in fine increments, for each analog input through the

FS_RANGE_A register setting (see the INA full-scale range adjust register) and FS_RANGE_B register setting

(see the INB full-scale range adjust register) for INA± and INB±, respectively. The available adjustment range is

specified in the Electrical Characterization: DC Specifications table. Larger full-scale voltages improve SNR and

noise floor (in dBFS/Hz) performance, but can degrade harmonic distortion. The full-scale voltage adjustment is

useful for matching the full-scale range of multiple ADCs when developing a multi-converter system or for

external interleaving of multiple ADC12DJ5200-EP's to achieve higher sampling rates.

7.3.2.3 Analog Input Offset Adjust

In foreground calibration mode, the input offset voltage for each input and for each ADC core can be adjusted

through SPI registers. The OADJ_A_FG0_VINx and OADJ_A_FG90_VINx registers (registers 0x344 to 0x34A)

are used to adjust ADC core A's offset voltage when sampling analog input x (where x is A for INA± or B for

INB±) where the FG0 register is used for dual channel mode and FG90 is used for single channel mode.

OADJ_B_FG0_VINx is used to adjust ADC core B's offset voltage when sampling input x. OADJ_B_FG0_VINx

applies to both single channel mode and dual channel mode. To adjust the offset voltage in dual channel mode

simply adjust the offset for the ADC core sampling the desired input. In single channel mode, both ADC core A's

offset and ADC core B's offset must be adjusted together. The difference in the two core's offsets in single

channel mode will result in a spur at f_S/2 that is independent of the input. These registers can be used to

compensate the f_S/2 spur in single channel mode. See the Calibration Modes and Trimming section for more

information.

7.3.3 ADC Core

The ADC12DJ5200-EP consists of a total of six ADC cores. The cores are interleaved for higher sampling rates

and swapped on-the-fly for calibration as required by the operating mode. This section highlights the theory and

key features of the ADC cores.

7.3.3.1 ADC Theory of Operation

The differential voltages at the analog inputs are captured by the rising edge of CLK± in dual-channel mode or

by the rising and falling edges of CLK± in single-channel mode. After capturing the input signal, the ADC

converts the analog voltage to a digital value by comparing the voltage to the internal reference voltage. If the

voltage on INA– or INB– is higher than the voltage on INA+ or INB+, respectively, then the digital output is a

negative 2's complement value. If the voltage on INA+ or INB+ is higher than the voltage on INA– or INB–,

respectively, then the digital output is a positive 2's complement value. 方程式 1 can calculate the differential

voltage at the input pins from the digital output.

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Code

2

^N

V_IN

where

=

V_FS

(1)

• Code is the signed decimal output code (for example, –2048 to +2047)

• N is the ADC resolution

• and V_FSis the full-scale input voltage of the ADC as specified in the Recommended Operating Conditions

table, including any adjustment performed by programming FS_RANGE_A or FS_RANGE_B

7.3.3.2 ADC Core Calibration

ADC core calibration is required to optimize the analog performance of the ADC cores. Calibration must be

repeated when operating conditions change significantly, namely temperature, in order to maintain optimal

performance. The device has a built-in calibration routine that can be run as a foreground operation or a

background operation. Foreground operation requires ADC downtime, where the ADC is no longer sampling the

input signal, to complete the process. Background calibration can be used to overcome this limitation and allow

constant operation of the ADC. See the Calibration Modes and Trimming section for detailed information on each

mode.

7.3.3.3 Analog Reference Voltage

The reference voltage for the ADC12DJ5200-EP is derived from an internal band-gap reference. A buffered

version of the reference voltage is available at the BG pin for user convenience. This output has an output-

current capability of ±100 µA. The BG output must be buffered if more current is required. No provision exists for

the use of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-

range register settings.

7.3.3.4 ADC Over-range Detection

To make sure that system gain management has the quickest possible response time, a low-latency configurable

over-range function is included. The over-range function works by monitoring the converted samples at the ADC

to quickly detect if the ADC is near saturation or already in an over-range condition. The absolute value of the

ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1. These thresholds apply to

both channel A and channel B in dual-channel mode. 表 7-2 lists how an ADC sample is converted to an

absolute value for a comparison of the thresholds.

表7-2. Conversion of ADC Sample for Over-range Comparison

ADC SAMPLE

(Offset Binary)

ADC SAMPLE

(2's Complement)

ABSOLUTE VALUE

111 1111 (127)

1111 1111 (255)

1000 0000 (128)

0001 0000 (16)

0000 0000 (0)

0111 1111(+127)

0000 0000 (0)

111 0000 (112)

111 1111 (127)

1000 0001 0000 (–112)

1000 0000 0000 (–128)

If the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the monitoring period, then the

over-range bit associated with the threshold is set to 1; otherwise, the over-range bit is 0. In dual-channel mode,

the over-range status can be monitored on the ORA0 and ORA1 pins for channel A and the ORB0 and ORB1

pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and ORx1 corresponds to the OVR_T1

threshold. In single-channel mode, the over-range status for the OVR_T0 threshold is determined by monitoring

both the ORA0 and ORB0 outputs and the OVR_T1 threshold is determined by monitoring both ORA1 and

ORB1 outputs. In single-channel mode, the two outputs for each threshold must be OR'd together to determine

whether an over-range condition occurred. OVR_N can be used to set the output pulse duration from the last

over-range event. 表7-3 lists the over-range pulse lengths for the various OVR_N settings.

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表7-3. Overrange Monitoring Period for the ORA0, ORA1, ORB0, and ORB1 Outputs

OVERRANGE PULSE LENGTH SINCE LAST OVERRANGE

EVENT (DEVCLK Cycles)

OVR_N

0

1

2

3

4

5

6

7

8

16

32

64

128

256

512

1024

Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is

triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set

much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of −12 dBFS). If the input

signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never

tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of

time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of

the signal is above −12 dBFS).

7.3.3.5 Code Error Rate (CER)

ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle

codes, resulting from metastability caused by non-ideal comparator limitations. The device uses a unique ADC

architecture that inherently allows significant code error rate improvements from traditional pipeline, flash or

successive approximation register (SAR) ADCs. The code error rate of the device is multiple orders of

magnitude better than what can be achieved in alternative architectures at equivalent sampling rates providing

significant signal reliability improvements.

7.3.4 Temperature Monitoring Diode

A built-in thermal monitoring diode is made available on the TDIODE+ and TDIODE–pins. This diode facilitates

temperature monitoring and characterization of the device in higher ambient temperature environments.

Although the on-chip diode is not highly characterized, the diode can be used effectively by performing a

baseline measurement (offset) at a known ambient or board temperature and creating a linear equation with the

diode voltage slope provided in the Electrical Characteristics: DC Specifications table. Perform offset

measurement with the device unpowered or with the PD pin asserted to minimize device self-heating.

Recommended monitoring devices include the LM95233 device and similar remote-diode temperature

monitoring products from Texas Instruments.

7.3.5 Timestamp

The TMSTP+ and TMSTP– differential input can be used as a time-stamp input to mark a specific sample

based on the timing of an external trigger event relative to the sampled signal. TIMESTAMP_EN (see the LSB

control bit output register) must be set in order to use the timestamp feature and output the timestamp data.

When enabled, the LSB of the 8-bit output sample is used to output the timestamp status. The trigger must be

applied to the differential TMSTP+ and TMSTP– inputs. The trigger can be asynchronous to the ADC sampling

clock and is sampled at approximately the same time as the analog input.

7.3.6 Clocking

The clocking subsystem of the device has two input signals, device clock (CLK+, CLK–) and SYSREF

(SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (t_AD

adjust), a clock duty cycle corrector and a SYSREF capture block. 图7-2 describes the clocking subsystem.

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Duty Cycle

Correction

t_ADAdjust

Clock Distribution

and Synchronization

(ADC cores, digital,

JESD204C, etc.)

CLK+

CLK-

E

RS

A

IN

V

F

_

O

IN

C

_

D

_

D

A

T

D

A

T

SYSREF Capture

Automatic

SYSREF

Calibration

SYSREF+

SYSREF-

SYSREF Windowing

SYSREF_POS SYSREF_SEL

SRC_EN

图7-2. Clocking Subsystem

The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing

and serializer outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within

the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the

device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture

the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment

(t_ADadjust) allows the user to shift the sampling instance of the ADC in fine steps in order to synchronize

multiple ADC12DJ5200-EPs or to fine-tune system latency. Duty cycle correction is implemented in the device to

ease the requirements on the external device clock while maintaining high performance. 表 7-4 summarizes the

device clock interface in dual-channel mode and single-channel mode.

表7-4. Device Clock vs Mode of Operation

MODE OF OPERATION

Dual-channel mode

SAMPLING RATE VS f_CLK

SAMPLING INSTANT

Rising edge

1 × f_CLK

Single-channel mode

2 × f_CLK

Rising and falling edge

SYSREF is a system timing reference used for JESD204C subclass-1 implementations of deterministic latency.

SYSREF is used to achieve deterministic latency and for multi-device synchronization. SYSREF must be

captured by the correct device clock edge in order to achieve repeatable latency and synchronization. The

ADC12DJ5200-EP includes SYSREF windowing and automatic SYSREF calibration to ease the requirements

on the external clocking circuits and to simplify the synchronization process. SYSREF can be implemented as a

single pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division

of, the local multiframe clock frequency in 8B/10B encoding modes or the local extended multiblock clock

frequency in 64B/66B encoding modes. 方程式 2 is used to calculate valid SYSREF frequencies in 8B/10B

encoding modes and 方程式3 in 64B/66B encoding modes.

R ì f_CLK

f_SYSREF

=

10

ì

F

ì

K

ì

n

(2)

(3)

Rì f_CLK

66ì32ìEìn

f_SYSREF

=

where

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• R and F are set by the JMODE setting (see Operating Modes)

• f_CLKis the device clock frequency (CLK±)

• K is the programmed multiframe length (see Operating Modes for valid K settings)

• E is the number of multiblocks in an extended multiblock.

• n is any positive integer

7.3.6.1 Noiseless Aperture Delay Adjustment (t_ADAdjust)

The device contains a delay adjustment on the device clock (sampling clock) input path, called t_ADadjust, that

can be used to shift the sampling instance within the device in order to align sampling instances among multiple

devices or for external interleaving of multiple devices. Further, t_ADadjust can be used for automatic SYSREF

calibration to simplify synchronization; see the Automatic SYSREF Calibration section. Aperture delay

adjustment is implemented in a way that adds no additional noise to the clock path; however, a slight

degradation in aperture jitter (t_AJ) is possible at large values of TAD_COARSE because of internal clock path

attenuation. The degradation in aperture jitter can result in minor SNR degradations at high input frequencies

(see t_AJin the Switching Characteristics table). This feature is programmed using TAD_INV, TAD_COARSE, and

TAD_FINE in the DEVCLK timing adjust ramp control register. Setting TAD_INV inverts the input clock resulting

in a delay equal to half the clock period. 表7-5 summarizes the step sizes and ranges of the TAD_COARSE and

TAD_FINE variable analog delays. All three delay options are independent and can be used in conjunction. All

clocks within the device are shifted by the programmed t_ADadjust amount, which results in a shift of the timing of

the JESD204C serialized outputs and affects the capture of SYSREF.

表7-5. t_ADAdjust Adjustment Ranges

ADJUSTMENT PARAMETER

ADJUSTMENT STEP

DELAY SETTINGS

MAXIMUM DELAY

TAD_INV

1 / (f_CLK× 2)

1

1 / (f_CLK× 2)

See t_TAD(STEP)in the Switching

Characteristics table

See t_TAD(MAX)in the Switching

Characteristics table

TAD_COARSE

TAD_FINE

256

See t_TAD(STEP)in the Switching

Characteristics table

See t_TAD(MAX)in the Switching

Characteristics table

In order to maintain timing alignment between converters, stable and matched power-supply voltages and device

temperatures must be provided.

Aperture delay adjustment can be changed on-the-fly during normal operation but may result in brief upsets to

the JESD204C data link. Use TAD_RAMP to reduce the probability of the JESD204C link losing synchronization;

see the Aperture Delay Ramp Control section.

7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)

The ADC12DJ5200-EP contains a function to gradually adjust the t_ADadjust setting towards the newly written

TAD_COARSE value. This functionality allows the t_ADadjust setting to be adjusted with minimal internal clock

circuitry glitches. The TAD_RAMP_RATE parameter allows either a slower (one TAD_COARSE LSB per 256

t_CLKcycles) or faster ramp (four TAD_COARSE LSBs per 384 t_CLKcycles) to be selected. The TAD_RAMP_EN

parameter enables the ramp feature and any subsequent writes to TAD_COARSE initiate a new cramp.

7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency

The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic

latency. The ADC12DJ5200-EP uses the JESD204C subclass-1 method to achieve deterministic latency and

synchronization. Subclass 1 requires that the SYSREF signal be captured by a deterministic device clock (CLK±)

edge at each system power-on and at each device in the system. This requirement imposes setup and hold

constraints on SYSREF relative to CLK±, which can be difficult to meet at giga-sample clock rates over all

system operating conditions. The device includes a number of features to simplify this synchronization process

and to relax system timing constraints:

• The device uses dual-edge sampling (DES) in single-channel mode to reduce the CLK± input frequency by

half and double the timing window for SYSREF (see 表7-4)

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• A SYSREF position detector (relative to CLK±) and selectable SYSREF sampling position aid the user in

meeting setup and hold times over all conditions; see the SYSREF Position Detector section

• Easy-to-use automatic SYSREF calibration uses the aperture timing adjust block (t_ADadjust) to shift the ADC

sampling instance based on the phase of SYSREF (rather than adjusting SYSREF based on the phase of the

ADC sampling instance); see the Automatic SYSREF Calibration section

7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)

The SYSREF windowing block is used to first detect the position of SYSREF relative to the CLK± rising edge

and then to select a desired SYSREF sampling instance, which is a delay version of CLK±, to maximize setup

and hold timing margins. In many cases a single SYSREF sampling position (SYSREF_SEL) is sufficient to meet

timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However,

this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF

as operating conditions change or to remove system-to-system variation at production test by finding a unique

optimal value at nominal conditions for each system.

This section describes proper usage of the SYSREF windowing block. First, apply the device clock and SYSREF

to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the

SYSREF_POS bits of the SYSREF capture position register. ADC12DJ5200-EP must see at least 3 rising edges

of SYSREF before the SYSREF_POS output is valid. Each bit of SYSREF_POS represents a potential SYSREF

sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling position has a

potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the positions of

SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting SYSREF_SEL in the

clock control register 0 to the value corresponding to that SYSREF_POS position. In general, the middle

sampling position between two setup and hold instances is chosen. Ideally, SYSREF_POS and SYSREF_SEL

are performed at the nominal operating conditions of the system (temperature and supply voltage) to provide

maximum margin for operating condition variations. This process can be performed at final test and the optimal

SYSREF_SEL setting can be stored for use at every system power up. Further, SYSREF_POS can be used to

characterize the skew between CLK± and SYSREF± over operating conditions for a system by sweeping the

system temperature and supply voltages. For systems that have large variations in CLK± to SYSREF± skew, this

characterization can be used to track the optimal SYSREF sampling position as system operating conditions

change. In general, a single value can be found that meets timing over all conditions for well-matched systems,

such as those where CLK± and SYSREF± come from a single clocking device.

备注

SYSREF_SEL must be set to 0 when using automatic SYSREF calibration; see the Automatic

SYSREF Calibration section.

The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When

SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are

finer. See the Switching Characteristics table for delay step sizes when SYSREF_ZOOM is enabled and

disabled. In general, SYSREF_ZOOM = 1 is recommended to be used above f_CLK= 3GHz and SYSREF_ZOOM

= 0 below f_CLK= 3GHz. Bits 0 and 23 of SYSREF_POS are always be set to 1 because there is insufficient

information to determine if these settings are close to a timing violation, although the actual valid window can

extend beyond these sampling positions. The value programmed into SYSREF_SEL is the decimal number

representing the desired bit location in SYSREF_POS. 表 7-6 lists some example SYSREF_POS readings and

the optimal SYSREF_SEL settings. Although 24 sampling positions are provided by the SYSREF_POS status

register, SYSREF_SEL only allows selection of the first 16 sampling positions, corresponding to SYSREF_POS

bits 0 to 15. The additional SYSREF_POS status bits are intended only to provide additional knowledge of the

SYSREF valid window. In general, lower values of SYSREF_SEL are selected because of delay variation over

supply voltage, however in the fourth example a value of 15 provides additional margin and can be selected

instead.

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表7-6. Examples of SYSREF_POS Readings and SYSREF_SEL Selections

SYSREF_POS[23:0]

OPTIMAL SYSREF_SEL

0x02E[7:0]

(Largest Delay)

0x02C[7:0]⁽¹⁾

(Smallest Delay)

0x02D[7:0]⁽¹⁾

SETTING

b10000000

b10011000

b10000000

b10001100

b0110000 0

b00000000

b01100000

b00000011

b01100011

b00011001

b00110001

b0 0000001

b00000001

b00011001

8 or 9

12

6 or 7

4 or 15

6

(1) Red coloration indicates the bits that are selected, as given in the last column of this table.

7.3.6.3.2 Automatic SYSREF Calibration

The ADC12DJ5200-EP has an automatic SYSREF calibration feature to alleviate the often challenging setup

and hold times associated with capturing SYSREF for giga-sample data converters. Automatic SYSREF

calibration uses the t_ADadjust feature to shift the device clock to maximize the SYSREF setup and hold times or

to align the sampling instance based on the SYSREF rising edge.

The device must have a proper device clock applied and be programmed for normal operation before starting the

automatic SYSREF calibration. When ready to initiate automatic SYSREF calibration, a continuous SYSREF

signal must be applied. SYSREF must be a continuous (periodic) signal when using the automatic SYSREF

calibration. Start the calibration process by setting SRC_EN high in the SYSREF calibration enable register after

configuring the automatic SYSREF calibration using the SRC_CFG register. Upon setting SRC_EN high, the

device searches for the optimal t_ADadjust setting until the device clock falling edge is internally aligned to the

SYSREF rising edge. TAD_DONE in the SYSREF calibration status register can be monitored tomake sure the

SYSREF calibration has finished. By aligning the device clock falling edge with the SYSREF rising edge,

automatic SYSREF calibration maximizes the internal SYSREF setup and hold times relative to the device clock

and also sets the sampling instant based on the SYSREF rising edge. After the automatic SYSREF calibration

finishes, the rest of the startup procedure can be performed to finish bringing up the system.

For multi-device synchronization, the SYSREF rising edge timing must be matched at all devices and therefore

trace lengths must be matched from a common SYSREF source to each device. Any skew between the

SYSREF rising edge at each device results in additional error in the sampling instance between devices,

however repeatable deterministic latency from system startup to startup through each device must still be

achieved. No other design requirements are needed in order to achieve multi-device synchronization as long as

a proper elastic buffer release point is chosen in the JESD204C receiver.

图 7-3 provides a timing diagram of the SYSREF calibration procedure. The optimized setup and hold times are

shown as t_SU(OPT)and t_H(OPT), respectively. Device clock and SYSREF are referred to as internal in this diagram

because the phase of the internal signals are aligned within the device and not to the external (applied) phase of

the device clock or SYSREF.

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Sampled Input Signal

Internal Unadjusted

Device Clock

Internal Calibrated

Device Clock

t_TAD(SRC)

Internal SYSREF

t_CAL(SRC)

t_H(OPT)

t_SU(OPT)

Before calibration, device clock falling edge does

not align with SYSREF rising edge

SRC_EN

(SPI register bit)

Calibration

enabled

After calibration, device clock falling edge

aligns with SYSREF rising edge

TAD_DONE

(SPI register bit)

Calibration

finished

图7-3. SYSREF Calibration Timing Diagram

When finished, the t_ADadjust setting found by the automatic SYSREF calibration can be read from SRC_TAD in

the SYSREF calibration status register. After calibration, the system continues to use the calibrated t_ADadjust

setting for operation until the system is powered down. However, if desired, the user can then disable the

SYSREF calibration and fine-tune the t_ADadjust setting according to the systems needs. Alternatively, the use of

the automatic SYSREF calibration can be done at product test (or periodic recalibration) of the optimal t_ADadjust

setting for each system. This value can be stored and written to the TAD register (TAD_INV, TAD_COARSE, and

TAD_FINE) upon system startup.

Do not run the SYSREF calibration when the ADC calibration (foreground or background) is running. If

background calibration is the desired use case, disable the background calibration when the SYSREF calibration

is used, then re-enable the background calibration after TAD_DONE goes high. SYSREF_SEL in the clock

control register 0 must be set to 0 when using SYSREF calibration.

SYSREF calibration searches the TAD_COARSE delays using both non-inverted (TAD_INV = 0) and inverted

clock polarity (TAD_INV = 1) to minimize the required TAD_COARSE setting in order to minimize loss on the

clock path to reduce aperture jitter (t_AJ).

7.3.7 Programmable FIR Filter (PFIR)

The output of the ADCs can be sent through programmable finite-impulse-response (PFIR) digital filter for

equalization of the frequency response. The filter can be setup in a few modes of operation to allow independent

equalization of each channel in dual channel mode, equalization in single channel mode or as a time-varying

filter in dual channel mode (such as for I/Q correction). The various PFIR operating modes are given in 表7-7.

表7-7. PFIR Operating Modes

Center Tap

Resolution

Center Tap LSB

Weight

Non-Center Tap

Resolution

Non-Center Tap LSB

Weight

PFIR Mode

Filter Coefficients

Dual Channel

Equalization

18 bits

2^-16

12 bits

2^-10, 2^-11...2^-16

9 per channel

9

Single Channel

Equalization

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表7-7. PFIR Operating Modes (continued)

Center Tap

Resolution

Center Tap LSB

Weight

Non-Center Tap

Resolution

Non-Center Tap LSB

Weight

PFIR Mode

Filter Coefficients

9 per coefficient set, 2

coefficient sets

Time Varying Filter

18 bits

2^-16

12 bits

2^-10, 2^-11...2^-16

Programming information for the various PFIR modes is given in 表 7-8. The coefficients are programmed into

the PFIR_Ax and PFIR_Bx registers.

表7-8. Programmable FIR Filter Mode Programming

PFIR Mode

PFIR Disabled

PFIR_MODE

PFIR_SHARE

PFIR_MERGE

0

2

X

0

1

0

X

0

1

Dual Channel Equalization

Single Channel Equalization

Time Varying Filter

7.3.7.1 Dual Channel Equalization

When the ADC is operating in dual channel mode (based on the JMODE setting) then the PFIR filter can be set

in dual channel equalization mode. This mode allows independent frequency equalization of the two ADC

channels. The filter for each channel consists of 9 coefficients that can be independently set. The center tap for

each filter has a resolution of 18 bits and the LSB has a weight of 2^-16. The non-center taps have a resolution of

12-bits with programmable LSB weight of 2^-10, 2^-11, 2^-12, 2^-13, 2^-14, 2^-15or 2^-16. All non-center taps have the

same LSB weight. The block diagram for dual channel equalization is shown in 图7-4.

图7-4. Dual Channel Equalization PFIR Block Diagram

7.3.7.2 Single Channel Equalization

When the ADC is operating in single channel mode (based on the JMODE setting) then the PFIR filter can be set

in single channel equalization mode. This mode allows frequency equalization of the ADC. The filter consists of 9

coefficients that can be independently set. The center tap of the filter has a resolution of 18 bits and the LSB has

a weight of 2^-16. The non-center taps have a resolution of 12-bits with programmable LSB weight of 2^-10, 2^-11

,

2^-12, 2^-13, 2^-14, 2^-15or 2^-16. All non-center taps have the same LSB weight. The block diagram for single channel

equalization is shown in 图7-5.

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图7-5. Single Channel Equalization PFIR Block Diagram

7.3.7.3 Time Varying Filter

When the ADC is operating in dual-input single channel mode (based on the JMODE setting and

SINGLE_INPUT setting) then the PFIR filter can be set in time varying filter mode. This mode enables a time

varying filter with two coefficient sets that are alternated between on a per sample basis. Each coefficient set

consists of 9 coefficients that can be independently set. The center tap of the filter has a resolution of 18 bits and

the LSB has a weight of 2^-16. The non-center taps have a resolution of 12-bits with programmable LSB weight of

2^-10, 2^-11, 2^-12, 2^-13, 2^-14, 2^-15or 2^-16. All non-center taps have the same LSB weight. The block diagram for time

varying filter mode is shown in 图 7-6 and an alternate block diagram is given in 图 7-7 which shows the

equivalent filter in an I/Q correction-type topology.

图7-6. Time Varying Filter PFIR Block Diagram

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图7-7. Alternate I/Q Correction-Type Filter Block Diagram

7.3.8 Digital Down Converters (DDC)

After converting the analog voltage to a digital value, the digitized sample can either be sent directly to the

JESD204C interface block (DDC bypass) or sent to the digital down converter (DDC) block for frequency

conversion and decimation. The DDC block can be used in both dual channel mode and single channel mode.

Frequency conversion and decimation allows a specific frequency band to be selected and reduces the amount

of data sent over the data interface. The DDC first mixes the desired band to complex baseband (0 Hz) by

performing a complex mixing operating using the numerically-controlled oscillator (NCO) as the local oscillator

(LO). The DDC then low-pass filters the baseband signal to remove unwanted frequency images and any signals

that may potentially alias into the desired band. It finally decimates (down samples) the data to reduce the data

rate. Note that the filtering and decimation operations are actually performed as a single operation in the device.

The DDC is designed with sufficient precision such that the digital processing does not degrade the noise

spectral density (NSD) performance of the ADC. 图 7-8 illustrates the DDC block in the device in dual channel

mode while 图 7-9 shows the DDC block of the device in single channel mode. In dual channel mode, the input

data for each DDC can be selected to come from either ADC channel A or ADC channel B by using the

DIG_BIND_x SPI registers. Channel B has the same structure with the input data selected by DIG_BIND_B and

the NCO selection mux controlled by pins NCOB[1:0] or through CSELB[1:0]. Only one DDC is available for use

in single channel mode.

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DDC

NCO Bank A

MUX

NCOA[1:0]

or CSELA[1:0]

Real

12-bit @ Fs

Complex

15-bit @ Fs

Complex

15-bit @ Fs/D

ADC

Channel A

D

JESD204C

Link A

Complex

Mixer

DIG_BIND_A

Real

12-bit @ Fs

JMODE

DDC Bypass

DDC

NCO Bank B

MUX

JMODE

NCOA[1:0]

or CSELA[1:0]

Real

12-bit @ Fs

Complex

15-bit @ Fs

Complex

15-bit @ Fs/D

D

ADC

Channel B

JESD204C

Link B

Complex

Mixer

DIG_BIND_B

Real

12-bit @ Fs

JMODE

DDC Bypass

图7-8. Digital Down Conversion Block in Dual Channel Mode

DDC

NCO Bank A

ADC

Channel A

NCOA[1:0]

or CSELA[1:0]

JESD204C

Link A

MUX

Real

Complex

12-bit @ Fs

15-bit @ Fs

15-bit @ Fs/D

D

Complex

Mixer

JMODE

Real

12-bit @ Fs

DDC Bypass

JMODE

CLK

ADC

Channel B

JESD204C

Link B

图7-9. Digital Down Conversion Block in Single Channel Mode

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7.3.8.1 Rounding and Saturation

Throughout the DDC, rounding and saturation is used. Samples are rounded to the nearest output code. If the

sample is exactly between two output codes, it is rounded to the even output code (convergent rounding). This

method introduces no bias or statistical DC offset to the rounded result.

In the FIR filters, rounding only occurs on the filter output. No intermediate rounding should be done.

7.3.8.2 Numerically-Controlled Oscillator and Complex Mixer

The DDC contains a complex numerically-controlled oscillator (NCO) and a complex mixer. 方程式 4 shows the

complex exponential sequence generated by the oscillator.

x[n] = e^jωn

(4)

The frequency (ω) is specified by a 32-bit register setting (see the Basic NCO Frequency Setting Mode section

and the Rational NCO Frequency Setting Mode section). The complex exponential sequence is multiplied by the

real input from the ADC to mix the desired carrier to a frequency equal to f_IN+ f_NCO, where f_INis the analog input

frequency after aliasing (in under-sampling systems) and f_NCOis the programmed NCO frequency.

7.3.8.2.1 NCO Fast Frequency Hopping (FFH)

Fast frequency hopping (FFH) is made possible by each DDC having four independent NCOs that can be

controlled by the NCOA0 and NCOA1 pins for DDC A and the NCOB0 and NCOB1 pins for DDC B. Each NCO

has independent frequency settings (see the Basic NCO Frequency Setting Mode section) and initial phase

settings (see the NCO Phase Offset Setting section) that can be set independently. Further, all NCOs have

independent phase accumulators that continue to run when the specific NCO is not selected, allowing the NCOs

to maintain their phase between selection so that downstream processing does not need to perform carrier

recovery after each hop, for instance.

NCO hopping occurs when the NCO GPIO pins change state. The pins are controlled asynchronously and

therefore synchronous switching is not possible. Associated latencies are demonstrated in 图 7-10, where t_TX

and t_ADCare provided in the Switching Characteristics table. All latencies in 表7-9 are approximations only.

DDC Block

NCO Bank

t_GPIO-MIXER

t_MIXER-TX

MUX

NCOx[1:0]

Dx0+/-

Dx1+/-

Dx2+/-

INx+

INx-

ADC

N

JESD204C

Complex

Mixer

Decimate-by-N

(based on JMODE)

Dx7+/-

t_ADC-MIXER

图7-10. NCO Fast Frequency Hopping Latency Diagram

表7-9. NCO Fast Frequency Hopping Latency Definitions

LATENCY PARAMETER

VALUE OR CALCULATION

UNITS

t_GPIO-MIXER

~45 to ~68

t_CLKcycles

t_ADC-MIXER

~37

t_MIXER-TX

(t_TX+ t_ADC) –t_ADC-MIXER

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7.3.8.2.2 NCO Selection

Within each channel DDC, four different frequency and phase settings are available for use. Each of the four

settings use a different phase accumulator within the NCO. Because all four phase accumulators are

independent and continuously running, rapid switching between different NCO frequencies is possible allowing

for phase coherent frequency hopping.

The specific frequency-phase pair used for each channel is selected through the NCOA[1:0] or NCOB[1:0] input

pins when CMODE is set to 1. Alternatively, the selected NCO can be chosen through SPI by CSELA for DDC A

and CSELB for DDC B by setting CMODE to 0 (default). The logic table for NCO selection is provided in 表 7-10

for both the GPIO and SPI selection options.

表7-10. Logic Table for NCO Selection Using GPIO or SPI

NCO SELECTION

NCO 0 using GPIO

NCO 1 using GPIO

NCO 2 using GPIO

NCO 3 using GPIO

NCO 0 using SPI

NCO 1 using SPI

NCO 2 using SPI

NCO 3 using SPI

CMODE

NCOx1

NCOx0

CSELx[1]

CSELx[0]

1

0

1

X

0

1

X

0

1

0

1

0

1

X

The frequency for each phase accumulator is programmed independently through the FREQAx, FREQBx (x = 0

to 3) and, optionally, NCO_RDIV register settings. The phase offset for each accumulator is programmed

independently through the PHASEAx and PHASEBx (x = 0 to 3) register settings.

7.3.8.2.3 Basic NCO Frequency Setting Mode

In basic NCO frequency-setting mode (NCO_RDIV = 0x0000), the NCO frequency setting is set by the 32-bit

register value, FREQAx and FREQBx (x = 0 to 3). The NCO frequency for DDC A can be calculated using 方程

式 5, where FREQAx can be replaced by FREQBx to calculate the NCO frequency for DDC B. FREQAx and

FREQBx can be considered either a 2's complement number (–2147483648 to 2147483647) or as an offset

binary number (0 to 4294967295).

ƒ_(NCO)= FREQAx × 2^–32× ƒ_(DEVCLK)(x = 0 –3)

(5)

备注

Changing the FREQAx and FREQBx register settings during operation results in a non-deterministic

NCO phase. If deterministic phase is required, the NCOs must be resynchronized; see the NCO

Phase Synchronization section.

7.3.8.2.4 Rational NCO Frequency Setting Mode

In basic NCO frequency mode, the frequency step size is very small and many frequencies can be synthesized,

but sometimes an application requires very specific frequencies that fall between two frequency steps. For

example with ƒ_Sequal to 2457.6 MHz and a desired ƒ_(NCO)equal to 5.02 MHz, the value for FREQAx is

8773085.867. Truncating the fractional portion results in an ƒ_(NCO)equal to 5.0199995 MHz, which is not the

desired frequency.

To produce the desired frequency, the NCO_RDIV parameter is used to force the phase accumulator to arrive at

specific frequencies without error. First, select a frequency step size (ƒ_(STEP)) that is appropriate for the NCO

frequency steps required. The typical value of ƒ_(STEP)is 10 kHz. Next, use 方程式 6 to program the NCO_RDIV

value.

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¦

(

/ ¦_STEP

)

DEVCLK

NCO_RDIV =

64

(6)

The result of 方程式 6 must be an integer value. If the value is not an integer, adjust either of the parameters

until the result is an integer value.

For example, select a value of 1920 for NCO_RDIV.

备注

NCO_RDIV values larger than 8192 can degrade the NCO SFDR performance and are not

recommended.

Now use 方程式7 to calculate the FREQAx register value.

FREQAx = round 2³²´ ¦_NCO/ ¦_DEVCLK

(

)

(7)

Alternatively, the following equations can be used:

ƒ_(NCO)

N =

ƒ_(STEP)

(8)

(9)

FREQAx = round 2²⁶´ N / NCO_RDIV

(

)

表7-11 lists common values for NCO_RDIV in 10-kHz frequency steps.

表7-11. Common NCO_RDIV Values (For 10-kHz Frequency Steps)

f_CLK(MHz)

2457.6

NCO_RDIV

3840

1966.08

1600

3072

2500

1474.56

1228.8

2304

1920

7.3.8.2.5 NCO Phase Offset Setting

The NCO phase-offset setting for each NCO is set by the 16-bit register value PHASEAx and PHASEBx (where

x = 0 to 3). The value is left-justified into a 32-bit field and then added to the phase accumulator.

Use 方程式10 to calculate the phase offset in radians.

Φ(rad) = PHASEA/Bx × 2^–16× 2 × π(x = 0 to 3)

(10)

7.3.8.2.6 NCO Phase Synchronization

The NCOs must be synchronized after setting or changing the value of FREQAx or FREQBx. NCO

synchronization is performed when the JESD204C link is initialized or by SYSREF, based on the settings of

NCO_SYNC_ILA and NCO_SYNC_NEXT. The procedures are as follows for the JESD204C initialization

procedure and the SYSREF procedure for both DC-coupled and AC-coupled SYSREF signals.

NCO synchronization using the JESD204C SYNC signal ( SYNCSE or TMSTP±). Although the 64B/66B

encoding modes do not use the SYNC signal to initialize the JESD204C link, it can still be used for NCO

synchronization with this method:

1. The device must be programmed for normal operation

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2. Set NCO_SYNC_ILA to 1 to enable NCO synchronization using the SYNC signal

3. Set JESD_EN to 0

4. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings

5. In the JESD204C receiver (logic device), deassert the SYNC signal by setting SYNC high

6. Set JESD_EN to 1

7. Assert the SYNC signal by setting SYNC low in the JESD204C receiver. This start the code group

synchronization (CGS) process in 8B/10B encoding modes or arms the trigger in 64B/66B encoding modes.

8. After achieving CGS (or when ready to synchronize), deassert the SYNC signal by setting SYNC high at the

same time for all ADCs in order synchronize the NCOs in each ADC. The SYNC signal must meet the

required setup and hold times (as specified in the Tining Requirements table)

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NCO synchronization using SYSREF (DC-coupled):

1. The device must be programmed for normal operation

2. Set JESD_EN to 1 to start the JESD204C link (the SYNC signal can respond as normal during the CGS

process)

3. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings

4. Verify that SYSREF is disabled (held low)

5. Arm NCO synchronization by setting NCO_SYNC_NEXT to 1

6. Issue a single SYSREF pulse to all ADCs to synchronize NCOs within all devices

NCO synchronization using SYSREF (AC-coupled):

1. The device must be programmed for normal operation

2. Set JESD_EN to 1 to start the JESD204C link (the SYNC signal can respond as normal during the CGS

process)

3. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings

4. Run SYSREF continuously

5. Arm NCO synchronization by setting NCO_SYNC_NEXT to 1 at the same time at all ADCs by timing the

rising edge of SCLK for the last data bit (LSB) at the end of the SPI write so that the SCLK rising edge

occurs after a SYSREF rising edge and early enough before the next SYSREF rising edge so that the trigger

is armed before the next SYSREF rising edge (a long SYSREF period is recommended)

6. NCOs in all ADCs are synchronized by the next SYSREF rising edge

7.3.8.3 Decimation Filters

The decimation filters are arranged to provide a programmable overall decimation of 4 or 8. All decimation filters

operate on complex data (from the complex digital mixer) and the outputs have a resolution of 15 bits. The

decimation filters are implemented as linear phase finite impulse response (FIR) filters. 表 7-12 lists the effective

output sample rates, available signal bandwidths, output formats, and stop-band attenuation for each decimation

mode.

表7-12. Output Sample Rates and Signal Bandwidths

ƒ_(DEVCLK)

DECIMATION

SETTING

OUTPUT FORMAT

OUTPUT RATE MAX ALIAS PROTECTED SIGNAL

STOP-BAND

ATTENUATION

PASS-BAND

RIPPLE

(MSPS)

BANDWIDTH (MHz)

No decimation (DDC

bypass)

Real signal,

12-bit data

< ±0.001 dB

ƒ_(DEVCLK)

ƒ_(DEVCLK)/ 2

—

Complex signal,

15-bit data

Decimate-by-4

Decimate-by-8

Decimate-by-16

Decimate-by-32

> 90 dB

ƒ_(DEVCLK)/ 4

ƒ_(DEVCLK)/ 8

ƒ_(DEVCLK)/ 16

ƒ_(DEVCLK)/ 32

0.8 × ƒ_(DEVCLK)/ 4

0.8 × ƒ_(DEVCLK)/ 8

0.8 × ƒ_(DEVCLK)/ 16

0.8 × ƒ_(DEVCLK)/ 32

Complex signal,

15-bit data

Complex signal,

15-bit data

Complex signal,

15-bit data

图 7-11 to 图 7-18 provide the composite decimation filter responses. The black portion of the trace shows the

pass-band region, or alias-protected region, of the response. The red portion of the trace shows the transition

region of the response as well as any frequency regions that will alias into the transition region. The transition

region is not alias protected and therefore desired signals should only be placed in the pass-band region of the

filter response. The blue portion of the trace shows the frequency regions that will alias into the pass-band after

decimation and therefore define the stop-band region of the frequency response. The stop-band attenuation is

defined to sufficient filter any undesired images or signals to prevent them from aliasing into the desired pass-

band. Use analog filtering before the analog inputs (INA± or INB±) for additional attenuation of signals that fall

within this band or to sufficiently reduce signals at the ADC inputs that may produce harmonics, interleaving

spurs or other undesired spurious signals that will alias into the desired signal band (before the complex mixing

and decimation operations).

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0.001

0.0005

0

Passband

Transition Band

Passband

Transition Band

Aliasing Band

-20

-40

-60

-80

-0.0005

-0.001

-100

-120

0

0.02

0.04

0.06

0.08

Normalized Frequency (Fs)

0.1

0.12

0.1

0.2 0.3

Normalized Frequency (Fs)

0.4

0.5

h4co

图7-12. Decimate-by-4 Composite Zoomed Pass-

图7-11. Decimate-by-4 Composite Response

Band Response

0.001

0

Passband

Transition Band

Passband

Transition Band

Aliasing Band

-20

-40

0.0005

0

-60

-80

-0.0005

-0.001

-100

-120

0

0.01

0.02

0.03

0.04

Normalized Frequency (Fs)

0.05

0.06

0

0.1

0.2 0.3

Normalized Frequency (Fs)

0.4

0.5

h8co

图7-14. Decimate-by-8 Composite Zoomed Pass-

图7-13. Decimate-by-8 Composite Response

Band Response

0.001

10

Passband

Transition Band

Passband

Transition Band

Aliasing Band

-10

-30

0.0005

-50

-70

0

-90

-0.0005

-0.001

-110

-130

0

0.005

0.01

0.015

0.02

Normalized Frequency (Fs)

0.025

0.03

0

0.1

0.2 0.3

Normalized Frequency (Fs)

0.4

0.5

h16c

图7-16. Decimate-by-16 Composite Zoomed Pass-

图7-15. Decimate-by-16 Composite Response

Band Response

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0.001

0.0005

0

-20

Passband

Transition Band

Aliasing Band

-40

-60

-80

-0.0005

-0.001

-100

-120

0

0.0025

0.005

0.0075

0.01

Normalized Frequency (Fs)

0.0125

0.015

0

0.1

0.2 0.3

Normalized Frequency (Fs)

0.4

0.5

h32c

图7-18. Decimate-by-32 Composite Zoomed Pass-

图7-17. Decimate-by-32 Composite Response

Band Response

For maximum efficiency, a group of high-speed filter blocks are implemented with specific blocks used for each

decimation setting to achieve the composite responses illustrated in 图 7-11 to 图 7-18. 表 7-13 describes the

combination of filter blocks used for each decimation setting and 表 7-14 lists the coefficient details and

decimation factor of each filter block. The coefficients are symmetric with the center tap indicated by bold text.

表7-13. Decimation Mode Filter Usage

DECIMATION SETTING

FILTER BLOCKS USED (Listed in Order of Operation)

4

8

CS40, CS80

CS20, CS40, CS80

16

32

CS10, CS20, CS40, CS80

CS5, CS10, CS20, CS40, CS80

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表7-14. Filter Coefficient Details

FILTER COEFFICIENT SET (Decimation Factor of Filter, Scale factor)

CS10 (2, 2^-11CS20 (2, 2^-14CS40 (2, 2^-17

–327

CS5 (2, 2^-5

)

CS80 (2, 2^-19

)

109

0

109

0

–1

0

–1

0

–65

0

–65

0

–327

0

–37

0

–37

0

2231

0

9

577

1024

577

2231

0

118

0

118

0

–837

0

–837

0

16

4824

8192

4824

–8881

0

–8881

0

–291

0

39742

65536

39742

612

0

–1159

0

2031

0

2031

0

–3356

0

–3356

0

5308

0

5308

0

–8140

0

–8140

0

12284

0

12284

0

–18628

0

–18628

0

29455

0

29455

0

–53191

0

–53191

0

166059

262144

166059

7.3.8.4 Output Data Format

The DDC output data consists of 15-bit complex data plus the two over-range threshold-detection control bits.表

7-15 shows the data output format for the DDC modes.

表7-15. Complex Decimation Output Sample Format

16-BIT OUTPUT WORD

I/Q

SAMPLE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

I

DDC in-phase (I) 15-bit output data

DDC quadrature (Q) 15-bit output data

OVR_T0

OVR_T1

Q

7.3.8.5 Decimation Settings

7.3.8.5.1 Decimation Factor

The decimation setting is adjustable over the following settings and is set by the JMODE parameter. See

Operating Modes for the available JMODE values and the corresponding decimation settings.

• DDC Bypass: No decimation, real output

• Decimate-by-4: Complex output

• Decimate-by-8: Complex output

• Decimate-by-16: Complex output

• Decimate-by-32: Complex output

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7.3.8.5.2 DDC Gain Boost

The DDC gain boost (see the DDC configuration register) provides additional gain through the DDC block.

Setting BOOST to 1 sets the total decimation filter chain gain to 6.02 dB. With a setting of 0, the total decimation

filter chain has a 0-dB gain. Only use this setting when the negative image of the input signal is filtered out by

the decimation filters, otherwise clipping may occur. There is no reduction in analog performance when gain

boost is enabled or disabled, but care must be taken to understand the reference output power for proper

performance calculations.

7.3.9 JESD204C Interface

The ADC12DJ5200-EP uses a JESD204C high-speed serial interface for data converters to transfer data from

the ADC to the receiving logic device. Many of the available JESD204C output formats are backwards

compatible with existing JESD204B receivers, including many of the JESD204B modes in the ADC12DJ2700

and ADC12DJ3200. The device serialized lanes are capable of operating with both 8B/10B encoding and

64B/66B encoding. A maximum of 16 lanes can be used to lower lane rates for interfacing with speed-limited

logic devices. There are a few differences between 8B/10B and 64B/66B encoded JESD204C, which will be

described throughout this section. 图 7-19 shows a simplified block diagram of the 8B/10B encoded JESD204C

interface and 图7-20 shows a simplified block diagram of the 64B/66B encoded JESD204C interface.

ADC

JESD204C Block

TRANSPORT

LAYER

SCRAMBLER

(Optional)

8B/10B

LINK LAYER

SERDES

TX PHY

ADC

ANALOG

CHANNEL

Logic Device

JESD204B or JESD204C Block

APPLICATION

LAYER

TRANSPORT

LAYER

DESCRAMBLE

(Optional)

8B/10B

LINK LAYER

SERDES

RX PHY

图7-19. Simplified 8B/10B Encoded JESD204C Interface Diagram

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ADC

JESD204C Block

TRANSPORT

LAYER

SCRAMBLER

(Required)

64B/66B

LINK LAYER

SERDES

TX PHY

ADC

ANALOG

CHANNEL

Logic Device

JESD204C Block

APPLICATION

LAYER

TRANSPORT

LAYER

DESCRAMBLE

(Required)

64B/66B

LINK LAYER

SERDES

RX PHY

图7-20. Simplified 64B/66B Encoded JESD204C Interface Diagram

The various signals used in the JESD204C interface and the associated the device pin names are summarized

briefly in 表 7-16 for reference. Most of the signals are common between 8B/10B and 64B/66B encoded

JESD204C, except for SYNC which is not needed to achieve block synchronization for 64B/66B encoding. The

sync header encoded into the data stream is used for block synchronization instead of the SYNC signal.

表7-16. Summary of JESD204C Signals

SIGNAL NAME

PIN NAMES

8B/10B

64B/66B

DESCRIPTION

High-speed serialized data

after 8B/10B or 64B/66B

encoding

Data

Yes

DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)

Link initialization signal

(handshake), toggles low to

start code group

synchronization (CGS)

process. Not used for

64B/66B encoding modes,

unless it is used for NCO

synchronization purposes.

SYNC

Yes

No

SYNCSE, TMSTP+, TMSTP–

ADC sampling clock, also

used for clocking digital logic

and output serializers

Device clock

SYSREF

Yes

CLK+, CLK–

System timing reference used

to deterministically reset the

internal local multiframe clock

(LMFC) or local extended

multiblock clock (LEMC)

counters in each JESD204C

device

SYSREF+, SYSREF–

Not all optional features of JESD204C are supported by the device. The list of features that are supported and

the features that are not supported is provided in 表7-17.

表7-17. Declaration of Supported JESD204C Features

REFERENCE

LETTER IDENTIFIER

FEATURE

SUPPORT IN ADC12DJ5200-EP

CLAUSE

clause 8

clause 7

a

b

c

8B/10B link layer

64B/66B link layer

64B/80B link layer

Supported

Not supported

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表7-17. Declaration of Supported JESD204C Features (continued)

REFERENCE

CLAUSE

LETTER IDENTIFIER

FEATURE

SUPPORT IN ADC12DJ5200-EP

The command channel when using the

64B/66B or 64B/80B link layer

d

e

f

clause 7

Not supported

Supported

Forward error correction (FEC) when using

the 64B/66B or 64B/80B link layer

CRC3 when using the 64B/66B or 64B/80B

link layer

clause 7

Not supported

Supported

A physical SYNC pin when using the 8B/10B

link layer

g

h

clause 8

Not supported, but subclass 1 transmitter is

compatible with subclass 0 receiver

clause 7, clause 8

Subclass 0

i

j

clause 7, clause 8

clause 8

Subclass 1

Subclass 2

Supported

Not supported

Supported

k

clause 7, clause 8

Lane alignment within a single link

Subclass 1 with support for a lane alignment

on a multipoint link by means of the

MULTIREF signal

l

clause 7, clause 8

Not supported

SYNC interface timing is compatible with

JESD204A

m

n

clause 8

Supported

SYNC interface timing is compatible with

JESD204B

7.3.9.1 Transport Layer

The transport layer takes samples from the ADC output and maps the samples into octets inside of frames. The

transport layer is common to both 8B/10B and 64B/66B encoding modes. These frames are then mapped onto

the available lanes. The mapping of octets into frames and frames onto lanes is defined by the transport layer

settings such as L, M, F, S, N and N'. An octet is 8 bits (before 8B/10B or 64B/66B encoding), a frame consists

of F octets and the frames are mapped onto L lanes. Samples are N bits, but sent as N' bits across the link. The

samples come from M converters and there are S samples per converter per frame cycle. M is sometimes

artificially increased in order to obtain a more desirable mapping, for instance lower latency may be achieved

with a larger M value for long frames.

There are a number of predefined transport layer modes in the device that are defined in Operating Modes . The

high level configuration parameters for the transport layer in the device are described in 表 7-21. The transport

layer mode is chosen by simply setting the JMODE register setting. For reference, the various configuration

parameters for JESD204C are defined in 表7-22.

The link layer further maps the frames into multiframes when using 8B/10B encoding or blocks, multiblocks and

extended multiblocks when using 64B/66B encoding.

7.3.9.2 Scrambler

A data scrambler is available to scramble the data before transmission across the channel. Scrambling is used

to remove the possibility of spectral peaks in the transmitted data due to repetitive data streams. The scrambler

is optional for 8B/10B encoded modes, however it is mandatory for 64B/66B encoded modes in order to have

sufficient spectral content for clock recovery and adaptive equalization and to maintain DC balance to allow AC

coupling of the transmitter to the receiver. The scrambler operates on the data before encoding, such that the

8B/10B scrambler scrambles the 8-bit octets before 10-bit encoding and the 64B/66B scrambler scrambles the

64-bit block before the sync header insertion (66-bit encoding). The JESD204C receiver automatically

synchronizes its descrambler to the incoming scrambled data stream. For 8B/10B encoding, the initial lane

alignment sequence (ILA) is never scrambled. Scrambling can be enabled by setting SCR (in the JESD204C

control register) for 8B/10B encoding modes, but it is automatically enabled in 64B/66B modes. The scrambling

polynomial is different for 8B/10B encoding and 64B/66B encoding schemes as defined by the JESD204C

standard.

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7.3.9.3 Link Layer

The link layer serves multiple purposes in JESD204C for both 8B/10B and 64B/66B encoding schemes, however

there are some differences in implementation for each encoding scheme. In general, the link layer's

responsibilities include scrambling of the data (see Scrambler), establishing the code (8B/10B) or block (64B/

66B) boundaries and the multiframe (8B/10B) or multiblock (64B/66B) boundaries, initializing the link, encoding

the data, and monitoring the health of the link. This section is split into an 8B/10B section (8B/10B Link Layer)

and a 64B/66B section (64B/66B Link Layer) in order to cover the specific implementation for each encoding

scheme.

7.3.9.4 8B/10B Link Layer

This section covers the link layer for the 8B/10B encoding operating modes including initialization of the

character, frame and multiframe boundaries, alignment of the lanes, 8B/10B encoding and monitoring of the

frame and multiframe alignment during operation.

7.3.9.4.1 Data Encoding (8B/10B)

The data link layer converts the 8-bit octets from the transport layer into 10-bit characters for transmission across

the link using 8B/10B encoding. 8B/10B encoding specifies DC balance to allow use of AC-coupling between the

SerDes transmitter and receiver, and maintains a sufficient number of edge transitions for the receiver to reliably

recover the data clock. 8B/10B encoding also provides some error detection since a single bit error in a

character likely results in either not being able to find the 10-bit character in the 8B/10B decoder lookup table or

an incorrect character disparity.

7.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)

The frames from the transport layer are combined into multiframes which are used in the process of achieving

deterministic latency in subclass 1 implementations. The length of a multiframe is set by the K parameter which

defines the number of frames in a multiframe. JESD204C increases the maximum allowed number of frames per

multiframe (K) from 32 in JESD204B to 256 in JESD204C to allow a longer multi-frame to ease deterministic

latency requirements. The total allowed range of K is defined by the inequality ceil(17/F) ≤ K ≤ min(256,

floor(1024/F)) where ceil() and floor() are the ceiling and floor function, respectively. The local multiframe clock

(LMFC) keeps track of the start and end of a multiframe for deterministic latency and data synchronization

purposes. The LMFC is reset by the SYSREF signal to a deterministic phase in both the transmitter and receiver

in order to act as a timing reference for deterministic latency. The LMFC clock frequency is given in 方程式 11

where f_BITis the serialized bit rate (line rate) of the SerDes interface and F and K are as defined above. The

frequency of SYSREF must equal to or an integer division of f_LMFCwhen using 8B/10B encoding modes if

SYSREF is a continuous signal.

f_LMFC= f_BIT/ (10 × F × K)

(11)

7.3.9.4.3 Code Group Synchronization (CGS)

The first step in initializing the JESD204C link, after the LMFC is deterministically reset by SYSREF, is for the

receiver to find the boundaries of the encoded 10-bit characters sent across each SerDes lane. This process is

called code group synchronization (CGS). The receiver first asserts the SYNC signal (set to logic '0') when ready

to initialize the link. The transmitter responds to the request by sending a stream of K28.5 comma characters.

The receiver aligns its character clock to the K28.5 character sequence and CGS is achieved after successfully

receiving four consecutive K28.5 characters. The receiver deasserts SYNC (set to logic '1') on the next LMFC

edge after CGS is achieved and waits for the transmitter to start the initial lane alignment sequence (ILAS).

7.3.9.4.4 Initial Lane Alignment Sequence (ILAS)

After the transmitter detects the SYNC signal deassert (logic '0' to logic '1' transition), the transmitter waits until

its next LMFC edge to start sending the initial lane alignment sequence (ILAS). The ILAS consists of four

multiframes each containing a predetermined sequence. The receiver searches for the start of the ILAS to

determine the frame and multiframe boundaries. Each multiframe of the ILAS starts with a /R/ character (K28.0)

and ends with a /A/ character (K28.3) and either can be used to detect the boundary of a multiframe. Each lane

starts buffering its data in the elastic buffer once the ILAS reaches the receiver, starting with the /R/ character,

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until all receivers have received the ILAS and subsequently release the ILAS from all lanes at the same time in

order to align the lanes. The elastic buffer release point is chosen to avoid ambiguity in the release of the data

caused by variation in the data delay (arrival of the ILAS at the receiver for each lane). The second multiframe of

the ILAS contains configuration parameters for the JESD204C link configuration that can be used by the receiver

to verify that the transmitter and receiver configurations match.

7.3.9.4.5 Frame and Multiframe Monitoring

The ADC12DJ5200-EP supports frame and multiframe monitoring for verifying the health of the JESD204C link

when using 8B/10B encoding. The scheme changes depending on the use of scrambling. The implementation

when scrambling is disabled is covered first. If the last octet of the current frame matches the last octet of the

previous frame, then the last octet of the current frame is encoded as an /F/ (K28.7) character. If the current

frame is also the last frame of a multiframe, then an /A/ (K28.3) character is used instead. Neither an /F/ or /A/

character should occur in a normal data stream, except when replaced by the transmitter for alignment

monitoring. When the receiver detects an /F/ or /A/ character in the normal data stream the receiver checks to

see if the character occurs at the location expected to be the end of a frame or multiframe. If the character

occurs at a location other than the end of a frame or multiframe then either the transmitter or receiver has

become misaligned. The receiver replaces the alignment character with the appropriate data character upon

reception of a properly aligned /F/ or /A/ character. The appropriate data character is the last octet of the

previously received frame. This scheme increases the probability of an alignment character for non-scrambled

data streams.

The implementation when scrambling is enabled is slightly different since the octets is randomized. If the last

octet of a frame is 0xFC (before 8B/10B encoding) then the transmitter encodes the octet as an /F/ (/K28.7/)

character. If the last octet of a multiframe is 0x7C (before 8B/10B encoding) then the transmitter encodes the

octet as an /A/ (/K28.3/) character. The location of the /A/ and /F/ characters is monitored to verify proper frame

and multiframe alignment. The receiver replaces the alignment characters by simply replacing an /F/ character

with the 0xFC octet and an /A/ character with the 0x7C octet.

The receiver can report an error if multiple alignment characters occur in the incorrect location or do not occur

when expected. Upon detection of a frame or multiframe misalignment, the receiver should trigger a link

realignment by asserting SYNC. SYSREF should also be reissued to verify that the LMFC in the transmitter and

receiver have proper alignment before restarting the link.

7.3.9.5 64B/66B Link Layer

This section covers the link layer for the 64B/66B encoding operating modes which includes scrambling of the

data, addition of the sync headers (64B/66B encoding), the structure of the block and multiblock, the sync

header, cyclic redundancy checking (CRC), forward error correction (FEC) and link alignment.

7.3.9.5.1 64B/66B Encoding

The frames formed by the transport layer are packed into 8-octet long blocks (64 bits). This 64-bit block is

scrambled and then a 2-bit sync header (SH) is appended to form a 66-bit transmission block. The sync header

is used for block synchronization by marking the end of a block as well as allowing for cyclic redundancy

checking (CRC), forward error correction (FEC) or a command channel. The structure of a block is given in 表

7-18 where SH represents the appended 2-bit sync header.

表7-18. Structure of 64B/66B Block with Sync Header

SH

OCTET0

OCTET1

OCTET2

OCTET3

OCTET4

OCTET5

OCTET6

OCTET7

[0:1]

[2:9]

[10:17]

[18:25]

[26:33]

[34:41]

[42:49]

[50:57]

[58:65]

7.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)

A multiblock is a 32 block container which consists of a concatenation of 32 blocks. An extended multiblock is a

concatenation of multiple multiblocks, where E defines the number of multiblocks in an extended multiblock. A

frame can be split between blocks and multiblocks, but there must be an integer number of frames in an

extended multiblock. An extended multiblock is only necessary when a multiblock does not have an integer

number of frames. If an extended multiblock is not used, because a multiblock contains an integer number of

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frames, then the E parameter is equal to 1 to indicate that there is one multiblock in an extended multiblock.

Values of E greater than 1 are not supported in ADC12DJ5200-EP.

An extended multiblock is analogous to a multiframe in the 8B/10B transport layer. The local extended mutiblock

clock (LEMC) keeps track of the start and end of a multiblock for deterministic latency and data synchronization

purposes in the same way the LMFC tracks the start and end of a multiframe in 8B/10B encoding. The LEMC is

reset by the SYSREF signal to a deterministic phase in both the transmitter and receiver in order to act as a

timing reference for deterministic latency. The LEMC clock frequency is defined by 方程式 12 where f_BITis the

serialized bit rate (line rate) of the SerDes interface. The frequency of SYSREF must equal to or an integer

division of f_LMFCwhen using 64B/66B encoding modes if SYSREF is a continuous signal.

f_LEMC= f_BIT/ (66 × 32 × E)

(12)

7.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header

The sync header contains two bits that are always opposite of each other (either 01 or 10). The JESD204C

receiver can find the block boundaries by looking for a 66-bit boundary that always contains a 0 to 1 or 1 to 0

transition. Although 0 to 1 and 1 to 0 transitions will occur at other locations in a block, it is impossible for the

sequence to appear at a fixed location, other than the proper sync header location, in successive blocks for a

long period of time. The sync header indicates the start of a block and can be used for block alignment

monitoring. If a 00 or a 11 bit sequence is seen at the assumed sync header location of a block, then block

alignment may have been lost. Multiple occurrences of incorrect sync header bits should trigger a search for the

sync header after sending SYSREF to all devices to reset LEMC alignment.

A sync header ([0:1]) of 01 corresponds to transmission of a 1 while a sync header of 10 corresponds to a

transmission of a 0. The transmitted bit from the sync header of each block of a multiblock are combined into a

32-bit word called the sync header stream. The sync header stream is used to transmit data in parallel with the

user data in order to synchronize the link by marking the borders of multiblocks and extended multiblocks. In

addition, the sync header stream provides one of either CRC, FEC or a command channel. The device supports

CRC-12 and FEC and does not support CRC-3 or the command channel.

The 32-bit sync header stream always ends with a 00001 bit sequence, called the end-of-multiblock (EoMB)

signal, that indicates the end of a multiblock. For CRC and command channel modes, a 00001 sequence will

never occur in any other location in the sync header stream. For FEC mode, it is possible for a 00001 sequence

to appear in another location within the sync header stream, however it is improbable to see the 00001

sequence in the same location within a sequence of multiple multiblocks. Therefore, in FEC mode it may take

more than one multiblock to find the end of a multiblock. The end of an extended multiblock is found for all

modes by monitoring bit 22 of the sync header stream, the EoEMB bit, which indicates the end of an extended

multiblock when set to a 1. The EoMB (00001) and EoEMB signals, as well as fixed 1s in the sync header

stream for CRC and command channel modes, form the pilot signal of the sync header stream.

The defined format for each form of the sync header stream are defined in the following sections.

7.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode

The cyclic redundancy check (CRC) mode is available to allow detection of potential bit errors during

transmission. Support for the 12-bit word CRC-12 mode is required by JESD204C, while a 3-bit word CRC-3

mode is optional. The device does not support the CRC-3 mode and therefore this section is specific to the

CRC-12 mode only. The transmitter computes the CRC-12 parity bits from the scrambled data bits of the 32

blocks of a multiblock. The 12-bit CRC parity word is then transmitted in the sync header stream of the next

multiblock. The receiver computes the 12-bit parity word of the received multiblock and compares it against the

received 12-bit parity word of the next multiblock. A difference indicates that there is at least one error in the

received data bits or in the received 12-bit parity word. The minimum latency to the detection of a bit error in the

first data bit of a multiblock is 46 blocks.

The mapping of the sync header stream when using the CRC-12 mode is shown in 表7-19. CRC[x] corresponds

to bit x of the 12-bit CRC word. Cmd[x] corresponds to bit x of the 7 bit command word, which are always set to

0's in the device. The 00001 bit sequence at the end of the sync header stream is the pilot signal that is used to

identify the end of a multiblock. The 1s that occur throughout the sync header makes suer the pilot signal is only

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seen at the end of the sync header, allowing multiblock alignment after only a single multiblock has been

received. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last multiblock of an extended

multiblock.

表7-19. Sync Header Stream Bit Mapping for CRC-12 Mode

Bit

0

Function

CRC[11]

CRC[10]

CRC[9]

1

Bit

Function

CRC[5]

CRC[4]

CRC[3]

1

Bit

16

17

18

19

20

21

22

23

Function

Cmd[6]

Cmd[5]

Cmd[4]

1

Bit

24

25

26

27

28

29

30

31

Function

8

Cmd[2]

1

9

Cmd[1]

2

10

11

12

13

14

15

Cmd[0]

3

0

1

4

CRC[8]

CRC[7]

CRC[6]

1

CRC[2]

CRC[1]

CRC[0]

1

Cmd[3]

1

5

6

EoEMB

1

7

The CRC-12 encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 12-bit parity

word using the generator polynomial given by 方程式13. The polynomial is sufficient to detect all 2-bit errors in a

multiblock, spanning any distance, and burst error sequences of up to 12-bits in length. The probability of not

detecting a 3-bit error spanning any distance in a multiblock is approximately 0.004%.

0x987 == x¹²+x⁹+x⁸+x³+x²+x+1

(13)

The full parity bit generation for CRC-12 is shown in 图 7-21. The input is a 2048 bit sequence, built from the 32

scrambled blocks of a multiblock (sync header is not included). The 12-bit parity word, CRC[11:0], is taken from

the S_xblocks after the full 2048 bit sequence is processed. The S_xblocks are initialized with 0's before

processing each multiblock. For more information on the CRC-12 parity word generation, refer to the JESD204C

standard.

32-block input

(2048 bits)

1

x

x²

x³

x⁸

x⁹

x¹²

S₁₁

S₀

S₁

S₂

S₃

S₄

S₅

S₆

S₇

S₈

S₉

S₁₀

CRC[0]

CRC[1]

CRC[2]

CRC[3] CRC[4] CRC[5] CRC[6] CRC[7]

CRC[8]

CRC[9] CRC[10] CRC[11]

图7-21. CRC-12 Parity Bit Generator

7.3.9.5.3.2 Forward Error Correction (FEC) Mode

Forward error correction (FEC) is an optional feature in JESD204C and is supported by the device. Whereas

CRC-12 mode can only detect errors on the link, FEC is able to detect and correct errors in order to improve the

bit error rate (BER) for error-sensitive applications. Many applications can tolerate random bit errors, however

some applications, such as an oscilloscope, rely on long error-free measurements in order to detect a certain

response from the device under test (DUT). An error in these applications may result in a false-positive detection

of the response.

A scrambled multiblock of 32 blocks (2048 bits) is input into the FEC parity bit generator to generate the 26-bit

parity word. The parity word is sent in the sync header stream of the next multiblock. The receiver then

calculates its own 26-bit parity word and calculates the difference between the locally generated and received

parity word, called the syndrome of the received bits. If the syndrome is 0, then all bits are assumed to have

been received correctly, while any value other than 0 indicates at least one error in either the data bits or the

parity word. If the syndrome is non-zero, then it can be used to determine the most likely error and then correct

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the error. The minimum latency from a bit error to detection and correct of a bit error in the first bit of a multiblock

is 58 blocks.

The mapping of the sync header stream when using FEC mode is shown in 表 7-20. FEC[x] corresponds to bit x

of the 26-bit FEC word. The 00001 bit sequence at the end of the sync header stream is the pilot signal that is

used to identify the end of a multiblock. It is possible for a 00001 sequence to appear in another location within

the sync header stream in FEC mode, however it is improbable to see the 00001 sequence in the same location

within a sequence of multiple multiblocks. Therefore, in FEC mode it may take more than one multiblock to find

the end of a multiblock. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last multiblock of

an extended multiblock.

表7-20. Sync Header Stream Bit Mapping for FEC Mode

Bit

0

Function

FEC[25]

FEC[24]

FEC[23]

FEC[22]

FEC[21]

FEC[20]

FEC[19]

FEC[18]

Bit

Function

FEC[17]

FEC[16]

FEC[15]

FEC[14]

FEC[13]

FEC[12]

FEC[11]

FEC[10]

Bit

16

17

18

19

20

21

22

23

Function

FEC[9]

FEC[8]

FEC[7]

FEC[6]

FEC[5]

FEC[4]

EoEMB

FEC[3]

Bit

24

25

26

27

28

29

30

31

Function

8

FEC[2]

1

9

FEC[1]

2

10

11

12

13

14

15

FEC[0]

3

0

1

4

5

6

7

The FEC encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 26-bit parity word

using the generator polynomial given by 方程式 14. The 2048 scrambled input bits plus 26 parity bits forms a

shortened (2074, 2048) binary cyclic code. The (2074, 2048) binary cyclic code is shortened from the cyclic Fire

code (8687, 8661). This polynomial can correct up to a 9-bit burst error per multiblock.

g(x) = (x¹⁷+1)(x⁹+x⁴+1) == x²⁶+x²¹+x¹⁷+x⁹+x⁴+1

(14)

The full 26-bit FEC parity word generation is shown in 图 7-22. The input is a 2048 bit sequence, built from the

32 scrambled blocks of a multiblock (sync header is not included). The 26-bit parity word, FEC[25:0], is taken

from the S_xblocks after the full 2048 bit sequence is processed. The S_xblocks are initialized with 0's before

processing each multiblock. For more information on the FEC parity word generation, refer to the JESD204C

standard.

32-block input

(2048 bits)

1

x⁴

x⁹

x¹⁷

x²¹

S₀

S₁

S₂

S₃

S₄

S₈

S₉

S₁₆

S₁₇

S₂₀

S₂₁

S₂₄

S₂₅

...

FEC[21] FEC[24] FEC[25]

FEC[0] FEC[1] FEC[2] FEC[3]

FEC[4]

FEC[8]

FEC[9]

FEC[16]

FEC[17]

FEC[20]

图7-22. FEC Parity Bit Generator

FEC decoding and error correction are not covered here. For full details on FEC decoding and error correction,

refer to the JESD204C standard.

7.3.9.5.4 Initial Lane Alignment

The 64B/66B link layer does not use an initial lane alignment sequence (ILAS) like the 8B/10B link layer.

Therefore, the receiver must use a different scheme to align lanes using the elastic buffer. In 8B/10B mode, the

ILAS triggers the elastic buffer to start buffering the data for each lane. After all lanes have started buffering the

data, the elastic buffers for each lane are released at a release point determined by the release buffer delay

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(RBD) parameter and the phase of the LMFC. In 64B/66B mode, the process starts by having all lanes achieve

block, multiblock and extended multiblock alignment. Once all lanes have achieved alignment, the receiver can

begin buffering data in the elastic buffers at the start of the next extended multiblock on each lane. The data is

released at the next release point after all lanes have seen the start of an extended multiblock and have started

buffering the data. The release point is defined relative to the LEMC edge and the programmed RBD value, the

most intuitive of which is to release on the LEMC edge itself. The release point must be chosen to avoid the

region of the LEMC containing variation in the data delay on each lane from startup to startup.

7.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring

Synchronization of blocks, multiblocks and extended multiblocks by monitoring the sync header of each block

and EoMB and EoEMB bit of the sync header stream. A block will always begin with a 0 to 1 or 1 to 0 transition

(sync header). A single missed sync header can occur due to a bit error, however it there are a number of sync

header errors within a set number of blocks, then block synchronization has been lost and block synchronization

should be reinitialized. It is possible to still have block synchronization, but to lose multiblock or extended

multiblock synchronization. Multiblock synchronization is monitored by looking for the EoMB signal, 00001, at the

end of the sync header stream for each multiblock. If multiple EoMB signals are erroneous within a number of

blocks, multiblock synchronization has been lost and multiblock synchronization should be reinitialized. If an

erroneous EoEMB bit is received for multiple extended multiblocks within a number of extended multiblocks,

such as a 1 for a multiblock that is not the end of an extended multiblock or a 0 for a multiblock that is the end of

an extended multiblock, then multiblock synchronization is lost and extended multiblock synchronization should

be reinitialized. If multiblock or extended multiblock synchronization is lost, SYSREF should be applied to the

erroneous devices in order to reestablish the LEMC before the synchronization process begins.

7.3.9.6 Physical Layer

The JESD204C physical layer consists of a current mode logic (CML) output driver and receiver. The receiver

consists of a clock detection and recovery (CDR) unit to extract the data clock from the serialized data stream

and can contain a continuous time linear equalizer (CTLE) and/or discrete feedback equalizer (DFE) to correct

for the low-pass response of the physical transmission channel. Likewise, the transmitter can contain pre-

equalization to account for frequency dependent losses across the channel. The total reach of the SerDes links

depends on the data rate, board material, connectors, equalization, noise and jitter, and required bit-error

performance. The SerDes lanes do not have to be matched in length because the receiver aligns the lanes

during the initial lane alignment sequence.

7.3.9.6.1 SerDes Pre-Emphasis

The device high-speed output drivers can pre-equalize the transmitted data stream by using pre-emphasis in

order to compensate for the low-pass response of the transmission channel. Configurable pre-emphasis settings

allow the output drive waveform to be optimized for different PCB materials and signal transmission distances.

The pre-emphasis setting is adjusted through the serializer pre-emphasis setting SER_PE (in the serializer pre-

emphasis control register). Higher values increase the pre-emphasis to compensate for more lossy PCB

materials. This adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver.

Adjust the pre-emphasis setting to optimize the eye-opening for the specific hardware configuration and line

rates needed.

7.3.9.7 JESD204C Enable

The JESD204C interface must be disabled through JESD_EN (in the JESD204C enable register) while any of

the other JESD204C parameters are being changed. When JESD_EN is set to 0, the block is held in reset and

the serializers are powered down. The clocks for this section are also gated off to further save power. When the

parameters are set as desired, the JESD204C block can be enabled (JESD_EN is set to 1).

7.3.9.8 Multi-Device Synchronization and Deterministic Latency

JESD204C subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices

achieve the same deterministic latency then they can be considered synchronized. This latency must be

achieved from system startup to startup to be deterministic. There are two key requirements to achieve

deterministic latency. The first is proper capture of SYSREF for which the device provides a number of features

to simplify this requirement at giga-sample clock rates (see the SYSREF Capture section for more information).

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SYSREF resets either the LMFC in 8B/10B encoding mode or the LEMC is 64B/66B encoding mode. The LMFC

and LEMC are analogous between the two modes and are now referred to as LMFC/LEMC.

The second requirement is to choose a proper elastic buffer release point in the receiver. Because the device is

an ADC, the device is the transmitter (TX) in the JESD204C link and the logic device is the receiver (RX). The

elastic buffer is the key block for achieving deterministic latency, and does so by absorbing variations in the

propagation delays of the serialized data as the data travels from the transmitter to the receiver. A proper release

point is one that provides sufficient margin against delay variations. An incorrect release point results in a latency

variation of one LMFC/LEMC period. Choosing a proper release point requires knowing the average arrival time

of data at the elastic buffer, referenced to an LMFC/LEMC edge, and the total expected delay variation for all

devices. With this information the region of invalid release points within the LMFC/LEMC period can be defined,

which stretches from the minimum to maximum delay for all lanes. Essentially, the designer must make sure the

data for all lanes arrives at all devices after the previous release point occurs, and before the next release point

occurs.

图 7-23 provides a timing diagram that demonstrates this requirement. In this figure, the data for two ADCs is

shown. The second ADC has a longer routing distance (t_PCB) and results in a longer link delay. First, the invalid

region of the LMFC/LEMC period is marked off as determined by the data arrival times for all devices. Then, the

release point is set by using the release buffer delay (RBD) parameter to shift the release point an appropriate

number of frame clocks from the LMFC/LEMC edge so that the release point occurs within the valid region of the

LMFC/LEMC cycle. In the case of 图 7-23, the LMFC/LEMC edge (RBD = 0) is a good choice for the release

point because there is sufficient margin on each side of the valid region.

Nominal Link Delay

Link Delay

(Arrival at Elastic Buffer)

Variation

ADC 1 Data

t_TX

t_PCB

t_RX-DESER

Propagation

Choose LMFC/LEMC

edge as release point

(RBD = 0)

ADC 2 Data

Propagation

t_TX

t_PCB

t_RX-DESER

Release point

margin

TX LMFC/LEMC

RX LMFC/LEMC

Time

Invalid Region

of LMFC/LEMC

Valid Region of

LMFC/LEMC

图7-23. LMFC/LEMC Valid Region Definition for Elastic Buffer Release Point Selection

The TX and RX LMFC/LEMCs do not necessarily need to be phase aligned, but knowledge of their phase is

important for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within

every LMFC/LEMC cycle, but the buffers only release when all lanes have arrived. Therefore, the total link delay

can exceed a single LMFC/LEMC period; see JESD204B multi-device synchronization: Breaking down the

requirements for more information.

7.3.9.9 Operation in Subclass 0 Systems

ADC12DJ5200-EP can operate with subclass 0 compatibility provided that multi-ADC synchronization and

deterministic latency are not required. With these limitations, the device can operate without the application of

SYSREF. The internal LMFC/LEMC is automatically self-generated with unknown timing. SYNC is used as

normal to initiate the CGS and ILAS in 8B/10B mode.

7.3.10 Alarm Monitoring

A number of built-in alarms are available to monitor internal events. Several types of alarms and upsets are

detected by this feature:

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1. Serializer FIFO alarm (FIFO overflow or underflow)

2. Serializer PLL is not locked

3. JESD204C link is enabled, but not transmitting data (not in the data transmission state)

4. SYSREF causes internal clocks to be realigned

5. An upset that impacts the NCO phase

6. An upset that impacts the JESD204C clocks

When an alarm occurs, a bit for each specific alarm is set in ALM_STATUS. Each alarm bit remains set until the

host system writes a 1 to clear the alarm. If the alarm type is not masked (see the alarm mask register), then the

alarm is also indicated by the ALARM register. The CALSTAT output pin can be configured as an alarm output

that goes high when an alarm occurs; see the CAL_STATUS_SEL bit in the calibration pin configuration register.

7.3.10.1 Clock Upset Detection

The CLK_ALM register bit indicates if the internal clocks have been upset. The clocks in channel A are

continuously compared to channel B. If the clocks differ for even one DEVCLK / 2 cycle, the CLK_ALM register

bit is set and remains set until cleared by the host system by writing a 1. For the CLK_ALM register bit to

function properly, follow these steps:

1. Program JESD_EN = 0

2. The part must be configured to use both channels (PD_ACH = 0, PD_BCH = 0)

3. Program JESD_EN = 1

4. Write CLK_ALM = 1 to clear CLK_ALM

5. Monitor the CLK_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured

6. When exiting global power-down (via MODE or the PD pin), the CLK_ALM status bit may be set and must be

cleared by writing a 1 to CLK_ALM

7.3.10.2 FIFO Upset Detection

The FIFO_ALM bit indicates if an underflow or overflow condition has occurred on any of the JESD204C

serializer lanes within the synchronizing FIFO between the digital logic block and serializer outputs. The

FIFO_LANE_ALM register bits can be used to determine which lane triggered the underflow or overflow

condition alarm. If the FIFO pointers are upset due to an undesired clock shift or other single event or incorrect

clocking frequencies, the FIFO_LANE_ALM bit for the erroneous lane is set to 1. If the INIT_ON_FIFO_ALM bit

is set, then the serializers, FIFO and JESD204C block automatically reinitialize.

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7.4 Device Functional Modes

The ADC12DJ5200-EP can be configured to operate in a number of functional modes. These modes are

described in this section.

7.4.1 Dual-Channel Mode

ADC12DJ5200-EP can be used as a dual-channel ADC where the sampling rate is equal to the clock frequency

(f_S= f_CLK) provided at the CLK+ and CLK– pins. The two inputs, AIN± and BIN±, serve as the respective inputs

for each channel in this mode. This mode is chosen simply by setting JMODE to the appropriate setting for the

desired configuration as described in Operating Modes. The analog inputs can be swapped by setting

DUAL_INPUT (see the input mux control register). One channel can be powered down to operate

ADC12DJ5200-EP as a single channel at the maximum sampling rate of dual channel mode to save power

compared to single channel mode operating at half the rate.

7.4.2 Single-Channel Mode (DES Mode)

The ADC12DJ5200-EP can also be used as a single-channel ADC where the sampling rate is equal to two times

the clock frequency (f_S= 2 × f_CLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the

two ADC channels together to form a single-channel ADC at twice the sampling rate. This mode is chosen

simply by setting JMODE to the appropriate setting for the desired configuration as described in Operating

Modes. INA± or INB±, can serve as the input to the ADC, however INA± is recommended for highest

performance. The analog input can be selected using SINGLE_INPUT (see the input mux control register). A

calibration needs to be performance after switching the input mux for the changes to take effect.

7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)

The ADC12DJ5200-EP can also be used as a single-channel ADC where the sampling rate is equal to two times

the clock frequency (f_S= 2 × f_CLK) provided at the CLK+ and CLK– pins. This mode interleaves the two

channels by sampling them out-of-phase and each channel samples separate analog inputs (INA± and INB±).

The effective sampling rate is twice the device clock input (CLK±). This mode is useful for sampling the output of

interleaved track-and-hold analog front-ends. This mode is chosen by setting JMODE to a single channel mode

as described in Operating Modes and setting SINGLE_INPUT to use both INA± and INB± (see the input mux

control register). The digital processing and JESD204C interface operate as if the device is in single-channel

mode sampling only one of the inputs.

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7.4.4 JESD204C Modes

The ADC12DJ5200-EP can be programmed as a single-channel or dual-channel ADC and a number JESD204C

output formats. 表 7-21 summarizes the basic operating mode configuration parameters and whether they are

user configured or derived.

表7-21. ADC12DJ5200-EP Operating Mode Configuration Parameters

USER CONFIGURED

PARAMETER

DESCRIPTION

VALUE

OR DERIVED

JESD204C operating mode, automatically

derives the rest of the JESD204C

parameters, single-channel or dual-channel

mode

Set by JMODE (see the JESD204C mode

register)

JMODE

User configured

1 = single-channel mode, 0 = dual-channel

mode

DES

R

Derived

See Operating Modes

Number of bits transmitted per lane per CLK±

cycle. The JESD204C line rate is the CLK±

frequency times R. This parameter sets the

SerDes PLL multiplication factor or controls

bypassing of the SerDes PLL.

See Operating Modes

Links

K

Number of JESD204C links used

Derived

Set by KM1 (see the JESD204C K parameter

register), see the allowed values in Operating

Modes. This parameter is ignored in 64B/66B

modes.

Number of frames per multiframe (8B/10B

mode)

User configured

Number of multiblocks per extended

multiblock (64B/66B mode)

Always set to '1' in ADC12DJ5200-EP. This

parameter is ignored in 8B/10B modes.

E

Derived

There are a number of parameters required to define the JESD204C transport layer format, all of which are sent

across the link during the initial lane alignment sequence in 8B/10B mode. 64B/66B mode does not use the

ILAS, however the transport layer uses the same parameters. In the ADC12DJ5200-EP, most parameters are

automatically derived based on the selected JMODE; however, a few are configured by the user. 表 7-22

describes these parameters.

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表7-22. JESD204C Initial Lane Alignment Sequence Parameters

USER CONFIGURED

OR DERIVED

PARAMETER

DESCRIPTION

VALUE

ADJCNT

ADJDIR

BID

LMFC adjustment amount (not applicable)

LMFC adjustment direction (not applicable)

Bank ID

Derived

Always 0

CF

Number of control words per frame

Always set to 0 in ILAS, see Operating

Modes for actual usage

CS

Control bits per sample

Derived

Set by DID (see the JESD204C DID

parameter register), see Lane Assignments

DID

F

Device identifier, used to identify the link

User configured

Number of octets (bytes) per frame (per lane) Derived

See Operating Modes

Always 0

High-density format (samples split between

lanes)

HD

JESDV

K

Derived

JESD204 standard revision

Derived

Always 1

Set by the KM1 register, see the JESD204C

K parameter register

Number of frames per multiframe

User configured

L

Number of serial output lanes per link

Lane identifier for each lane

Derived

See Operating Modes

LID

See Lane Assignments

Number of converters used to determine lane

bit packing; may not match number of ADC

channels in the device

M

Derived

See Operating Modes

Sample resolution (before adding control and

tail bits)

N

N'

S

Derived

See Operating Modes

Bits per sample after adding control and tail

bits

Number of samples per converter (M) per

frame

SCR

Scrambler enabled

Device subclass version

Reserved field 1

User configured

Derived

Set by the JESD204C control register

SUBCLASSV

RES1

Always 1

Always 0

Derived

RES2

Reserved field 2

Derived

Checksum for ILAS checking (sum of all

above parameters modulo 256)

CHKSUM

Derived

Computed based on parameters in this table

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7.4.4.2 JESD204C Modes continued

Configuring the ADC12DJ5200-EP is made easy by using a single configuration parameter called JMODE (see

the JESD204C mode register). Using Operating Modes, the correct JMODE value can be found for the desired

operating mode. The modes listed in Operating Modes are the only available operating modes. This table also

gives a range and allowable step size for the K parameter (set by KM1, see the JESD204C K parameter

register), which sets the multiframe length in number of frames.

The ADC12DJ5200-EP has a total of 16 high-speed output drivers that are grouped into two 8-lane JESD204C

links. All operating modes use two links with up to eight lanes per link. The lanes and their derived configuration

parameters are described in the Lane Assignement and Parameters table. For a specified JMODE, the lowest

indexed lanes for each link are used and the higher indexed lanes for each link are automatically powered down.

Always route the lowest indexed lanes to the logic device.

表7-24. ADC12DJ5200-EP Lane Assignment and Parameters

DEVICE PIN

DESIGNATION

JESD204C LINK

DID (User Configured)

LID (Derived)

DA0±

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

DA1±

DA2±

Set by DID (see the JESD204C DID parameter

register), the effective DID is equal to the DID register

setting (DID)

DA3±

A

DA4±

DA5±

DA6±

DA7±

DB0±

DB1±

DB2±

Set by DID (see the JESD204C DID parameter

register), the effective DID is equal to the DID register

setting plus 1 (DID+1)

DB3±

B

DB4±

DB5±

DB6±

DB7±

7.4.4.3 JESD204C Transport Layer Data Formats

Output data are formatted in a specific optimized fashion for each JMODE setting based on the transport layer

settings for that JMODE. When the DDC is not used (decimation = 1) the 12-bit offset binary values are mapped

into octets. For the DDC mode, the 16-bit values (15-bit complex data plus 1 overrange bit) are mapped into

octets. The following tables show the specific mapping formats for a single frame for each JMODE. The symbol

definitions used in the JMODE tables is provided in 表 7-25. In all mappings the tail bits (T) are 0 (zero). All

samples are formatted as MSB first, LSB last.

表7-25. JMODE Table Symbol Definitions

NOTATION

S[n]

MODE

DESCRIPTION

Single channel, DDC bypassed

Dual channel, DDC bypassed

Sample n from ADC in single channel mode when DDC is bypassed

Sample n from channel A in dual channel mode when DDC is bypassed

Tail bits, always set to 0

A[n]

B[n]

T

—

AI[n], AQ[n]

BI[n], BQ[n]

Dual channel, DDC enabled

Complex I/Q sample n from DDC A in dual channel mode

Complex I/Q sample n from DDC B in dual channel mode

Overrange flag for channel A, set high if channel A sample n exceeds

overrange threshold 0 (OVR_T0)

ORA0[n]

Dual channel, DDC enabled

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表7-25. JMODE Table Symbol Definitions (continued)

NOTATION

MODE

DESCRIPTION

Overrange flag for channel A, set high if channel A sample n exceeds

overrange threshold 1 (OVR_T1)

ORA1[n]

Dual channel, DDC enabled

Overrange flag for channel B, set high if channel B sample n exceeds

overrange threshold 0 (OVR_T0)

ORB0[n]

ORB1[n]

Dual channel, DDC enabled

Overrange flag for channel B, set high if channel B sample n exceeds

overrange threshold 1 (OVR_T1)

I[n], Q[n]

OR0[n]

OR1[n]

Single channel, DDC enabled

Complex I/Q sample n from the DDC in single channel mode

Overrange flag, set high if sample n exceeds overrange threshold 0 (OVR_T0)

Overrange flag, set high if sample n exceeds overrange threshold 1 (OVR_T1)

表7-26. JMODE 0 (12-bit, Single Channel, DDC Bypass, 8 lanes)

OCTET

NIBBLE

DA0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

S[0]

S[2]

S[4]

S[6]

S[1]

S[3]

S[5]

S[7]

S[8]

S[16]

S[18]

S[20]

S[22]

S[17]

S[19]

S[21]

S[23]

S[24]

S[26]

S[28]

S[30]

S[25]

S[27]

S[29]

S[31]

S[32]

S[34]

S[36]

S[38]

S[33]

S[35]

S[37]

S[39]

DA1

S[10]

S[12]

S[14]

S[9]

DA2

DA3

DB0

DB1

S[11]

S[13]

S[15]

DB2

DB3

表7-26 also applies to JMODE 30.

表7-27. JMODE 1 (12-bit, Single Channel, DDC Bypass, 16 lanes)

OCTET

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

S[0]

S[2]

S[4]

S[6]

S[8]

S[10]

S[12]

S[14]

S[1]

S[3]

S[5]

S[7]

S[9]

S[11]

S[13]

S[15]

S[16]

S[18]

S[20]

S[22]

S[24]

S[26]

S[28]

S[30]

S[17]

S[19]

S[21]

S[23]

S[25]

S[27]

S[29]

S[31]

S[32]

S[34]

S[36]

S[38]

S[40]

S[42]

S[44]

S[46]

S[33]

S[35]

S[37]

S[39]

S[41]

S[43]

S[45]

S[47]

S[48]

S[50]

S[52]

S[54]

S[56]

S[58]

S[60]

S[62]

S[49]

S[51]

S[53]

S[55]

S[57]

S[59]

S[61]

S[63]

S[64]

S[66]

S[68]

S[70]

S[72]

S[74]

S[76]

S[78]

S[65]

S[67]

S[69]

S[71]

S[73]

S[75]

S[77]

S[79]

表7-27 also applies to JMODE 40.

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表7-28. JMODE 2 (12-Bit, Dual Channel, DDC Bypass, 8 Lanes)

OCTET

NIBBLE

DA0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

A[0]

A[1]

A[2]

A[3]

B[0]

B[1]

B[2]

B[3]

A[4]

A[5]

A[6]

A[7]

B[4]

B[5]

B[6]

B[7]

A[8]

A[12]

A[13]

A[14]

A[15]

B[12]

B[13]

B[14]

B[15]

A[16]

A[17]

A[18]

A[19]

B[16]

B[17]

B[18]

B[19]

DA1

A[9]

DA2

A[10]

A[11]

B[8]

DA3

DB0

DB1

B[9]

DB2

B[10]

B[11]

DB3

表7-28 also applies to JMODE 31.

表7-29. JMODE 3 (12-Bit, Dual Channel, DDC Bypass, 16 Lanes)

OCTET

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

A[0]

A[1]

A[2]

A[3]

A[4]

A[5]

A[6]

A[7]

B[0]

B[1]

B[2]

B[3]

B[4]

B[5]

B[6]

B[7]

A[8]

A[16]

A[17]

A[18]

A[19]

A[20]

A[21]

A[22]

A[23]

B[16]

B[17]

B[18]

B[19]

B[20]

B[21]

B[22]

B[23]

A[24]

A[25]

A[26]

A[27]

A[28]

A[29]

A[30]

A[31]

B[24]

B[25]

B[26]

B[27]

B[28]

B[29]

B[30]

B[31]

A[32]

A[33]

A[34]

A[35]

A[36]

A[37]

A[38]

A[39]

B[32]

B[33]

B[34]

B[35]

B[36]

B[37]

B[38]

B[39]

A[9]

A[10]

A[11]

A[12]

A[13]

A[14]

A[15]

B[8]

B[9]

B[10]

B[11]

B[12]

B[13]

B[14]

B[15]

表7-29 also applies to JMODE 41.

表7-30. JMODE 5 (8-bit, Single Channel, 8 Lanes)

OCTET

0

NIBBLE

DA0

0

1

S[0]

S[2]

S[4]

S[6]

S[1]

S[3]

S[5]

S[7]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-30 also applies to JMODE 44.

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表7-31. JMODE 6 (8-bit, Single Channel, 16 Lanes)

OCTET

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

0

1

S[0]

S[2]

S[4]

S[6]

S[8]

S[10]

S[12]

S[14]

S[1]

S[3]

S[5]

S[7]

S[9]

S[11]

S[13]

S[15]

表7-31 also applies to JMODE 50.

表7-32. JMODE 7 (8-bit, Dual Channel, 8 Lanes)

OCTET

0

NIBBLE

DA0

0

1

A[0]

A[1]

A[2]

A[3]

B[0]

B[1]

B[2]

B[3]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-32 also applies to JMODE 45.

表7-33. JMODE 8 (8-bit, Dual Channel, 16 Lanes)

OCTET

0

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

0

1

A[0]

A[1]

A[2]

A[3]

A[4]

A[5]

A[6]

A[7]

B[0]

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表7-33. JMODE 8 (8-bit, Dual Channel, 16 Lanes) (continued)

OCTET

NIBBLE

DB1

0

1

B[1]

B[2]

B[3]

B[4]

B[5]

B[6]

B[7]

DB2

DB3

DB4

DB5

DB6

DB7

表7-33 also applies to JMODE 51.

表7-34. JMODE 10 (15-bit, Dual Channel, Decimate-by-4, 4 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

AI[0], ORA0[0]

AQ[0], ORA1[0]

BI[0], ORB0[0]

BQ[0], ORB1[0]

DA1

DB0

DB1

表7-34 also applies to JMODE 37.

表7-35. JMODE 11 (15-bit, Dual Channel, Decimate-by-4, 8 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

AI[0], ORA0[0]

AI[1], ORA0[1]

AQ[0], ORA1[0]

AQ[1], ORA1[1]

BI[0], ORB0[0]

BI[1], ORB0[1]

BQ[0], ORB1[0]

BQ[1], ORB1[1]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-35 also applies to JMODE 47.

表7-36. JMODE 12 (15-bit, Dual Channel, Decimate-by-4, 16 lanes)

OCTET

0

1

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

0

1

2

3

AI[0], ORA0[0]

AI[1], ORA0[1]

AI[2], ORA0[2]

AI[3], ORA0[3]

AQ[0], ORA1[0]

AQ[1], ORA1[1]

AQ[2], ORA1[2]

AQ[3], ORA1[3]

BI[0], ORB0[0]

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表7-36. JMODE 12 (15-bit, Dual Channel, Decimate-by-4, 16 lanes) (continued)

OCTET

NIBBLE

DB1

0

1

0

1

2

3

BI[1], ORB0[1]

BI[2], ORB0[2]

BI[3], ORB0[3]

BQ[0], ORB1[0]

BQ[1], ORB1[1]

BQ[2], ORB1[2]

BQ[3], ORB1[3]

DB2

DB3

DB4

DB5

DB6

DB7

表7-36 also applies to JMODE 53.

表7-37. JMODE 13 (15-bit, Dual Channel, Decimate-by-8, 2 lanes)

OCTET

NIBBLE

DA0

0

1

2

3

0

1

2

3

4

5

6

7

AI[0], ORA0[0]

BI[0], ORB0[0]

AQ[0], ORA1[0]

BQ[0], ORB1[0]

DB0

表7-37 also applies to JMODE 39,JMODE 56, JMODE 59, JMODE 66 and JMODE 68.

表7-38. JMODE 14 (15-bit, Dual Channel, Decimate-by-8, 4 lanes)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

AI[0], ORA0[0]

AQ[0], ORA1[0]

BI[0], ORB0[0]

BQ[0], ORB1[0]

DA1

DB0

DB1

表7-38 also applies to JMODE 49, JMODE 57, JMODE 60 and JMODE 67.

表7-39. JMODE 15 (15-bit, Dual Channel, Decimate-by-8, 8 lanes)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

AI[0], ORA0[0]

AI[1], ORA0[1]

AQ[0], ORA1[0]

AQ[1], ORA1[1]

BI[0], ORB0[0]

BI[1], ORB0[1]

BQ[0], ORB1[0]

BQ[1], ORB1[1]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-39 also applies to JMODE 55 and JMODE 58.

表7-40. JMODE 16 (15-bit, Dual Channel, Decimate-by-8, 16 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

AI[0], ORA0[0]

AI[1], ORA0[1]

AI[2], ORA0[2]

AI[3], ORA0[3]

AQ[0], ORA1[0]

AQ[1], ORA1[1]

DA1

DA2

DA3

DA4

DA5

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表7-40. JMODE 16 (15-bit, Dual Channel, Decimate-by-8, 16 lanes) (continued)

OCTET

NIBBLE

DA6

0

1

0

1

2

3

AQ[2], ORA1[2]

AQ[3], ORA1[3]

BI[0], ORB0[0]

BI[1], ORB0[1]

BI[2], ORB0[2]

BI[3], ORB0[3]

BQ[0], ORB1[0]

BQ[1], ORB1[1]

BQ[2], ORB1[2]

BQ[3], ORB1[3]

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

表7-41. JMODE 19 (12-bit, Single Channel, DDC Bypass, 12 lanes)

OCTET

0

1

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DB0

DB1

DB2

DB3

DB4

DB5

0

1

2

3

S[0][11:0]

S[2][11:8]

S[2][7:0]

S[10][7:0]

S[3][7:0]

S[11][7:0]

S[4][11:4]

S[12][11:4]

S[5][11:4]

S[13][11:4]

S[4][3:0]

S[12][3:0]

S[5][3:0]

S[13][3:0]

S[6][11:0]

S[14][11:0]

S[7][11:0]

S[15][11:0]

S[8][11:0]

S[1][11:0]

S[9][11:0]

S[10][11:8]

S[3][11:8]

S[11][11:8]

表7-41 also applies to JMODE 42.

表7-42. JMODE 20 (12-bit, Dual Channel, DDC Bypass, 12 lanes)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

A[0][11:0]

A[1][11:8]

DA1

A[1][7:0]

A[5][7:0]

B[1][7:0]

B[5][7:0]

A[2][11:4]

A[6][11:4]

B[2][11:4]

B[6][11:4]

DA2

A[2][3:0]

A[6][3:0]

B[2][3:0]

B[6][3:0]

A[3][11:0]

A[7][11:0]

B[3][11:0]

B[7][11:0]

DA3

A[4][11:0]

B[0][11:0]

B[4][11:0]

A[5][11:8]

B[1][11:8]

B[5][11:8]

DA4

DA5

DB0

DB1

DB2

DB3

DB4

DB5

表7-42 also applies to JMODE 43.

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表7-43. JMODE 21 (15-bit, Single Channel, Decimate-by-4, 4 lanes)

OCTET

NIBBLE

DA0

0

1

I[0], OR0[0]

I[1], OR0[1]

Q[0], OR1[0]

Q[1], OR1[1]

DA1

DB0

DB1

表7-43 also applies to JMODE 36.

表7-44. JMODE 22 (15-bit, Single Channel, Decimate-by-4, 8 lanes)

OCTET

NIBBLE

DA0

0

1

I[0], OR0[0]

I[1], OR0[1]

I[2], OR0[2]

I[3], OR0[3]

Q[0], OR1[0]

Q[1], OR1[1]

Q[2], OR1[2]

Q[3], OR1[3]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-44 also applies to JMODE 46.

表7-45. JMODE 23 (15-bit, Single Channel, Decimate-by-8, 2 lanes)

OCTET

NIBBLE

DA0

0

1

I[0], OR0[0]

Q[0], OR1[0]

DB0

表7-45 also applies to JMODE 38, JMODE 61, JMODE 64, JMODE 69 and JMODE 71.

表7-46. JMODE 24 (15-bit, Single Channel, Decimate-by-8, 4 lanes)

OCTET

NIBBLE

DA0

0

1

I[0], OR0[0]

I[1], OR0[1]

Q[0], OR1[0]

Q[1], OR1[1]

DA1

DB0

DB1

表7-46 also applies to JMODE 48, JMODE 62, JMODE 65 and JMODE 70.

表7-47. JMODE 25 (15-bit, Single Channel, Decimate-by-4, 16 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

I[0], OR0[0]

I[1], OR0[0]

I[2], OR0[1]

I[3], OR0[1]

I[4], OR0[2]

I[5], OR0[2]

DA1

DA2

DA3

DA4

DA5

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表7-47. JMODE 25 (15-bit, Single Channel, Decimate-by-4, 16 lanes) (continued)

OCTET

NIBBLE

DA6

0

1

0

1

2

3

I[6], OR0[3]

I[7], OR0[3]

Q[0], OR1[0]

Q[1], OR1[0]

Q[2], OR1[1]

Q[3], OR1[1]

Q[4], OR1[2]

Q[5], OR1[2]

Q[6], OR1[3]

Q[7], OR1[3]

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

表7-47 also applies to JMODE 52.

表7-48. JMODE 26 (15-bit, Single Channel, Decimate-by-8, 8 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

I[0], OR0[0]

I[1], OR0[1]

I[2], OR0[2]

I[3], OR0[3]

Q[0], OR1[0]

Q[1], OR1[1]

Q[2], OR1[2]

Q[3], OR1[3]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

表7-48 also applies to JMODE 54 and JMODE 63.

表7-49. JMODE 27 (15-bit, Single Channel, Decimate-by-8, 16 lanes)

OCTET

0

1

NIBBLE

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

0

1

2

3

I[0], OR0[0]

I[1], OR0[1]

I[2], OR0[2]

I[3], OR0[3]

I[4], OR0[4]

I[5], OR0[5]

I[6], OR0[6]

I[7], OR0[7]

Q[0], OR1[0]

Q[1], OR1[1]

Q[2], OR1[2]

Q[3], OR1[3]

Q[4], OR1[4]

Q[5], OR1[5]

Q[6], OR1[6]

Q[7], OR1[7]

表7-50. JMODE 32 (12-bit, Single Channel, DDC Bypass, 6 lanes)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

S[0][11:0]

S[2][11:8]

DA1

S[2][7:0]

S[4][11:4]

DA2

S[4][3:0]

S[6][11:0]

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表7-50. JMODE 32 (12-bit, Single Channel, DDC Bypass, 6 lanes) (continued)

OCTET

NIBBLE

DB0

0

1

0

1

2

3

S[1][11:0]

S[3][11:8]

DB1

S[3][7:0]

S[5][11:4]

DB2

S[5][3:0]

S[7][11:0]

表7-51. JMODE 33 (12-bit, Dual Channel, DDC Bypass, 6 lanes)

OCTET

NIBBLE

DA0

0

1

0

1

2

3

A[0][11:0]

A[1][11:8]

DA1

A[1][7:0]

B[1][7:0]

A[2][11:4]

B[2][11:4]

DA2

A[2][3:0]

B[2][3:0]

A[3][11:0]

B[3][11:0]

DB0

B[0][11:0]

B[1][11:8]

DB1

DB2

表7-52. JMODE 34 (8-bit, Single Channel, 4 lanes)

OCTET

0

NIBBLE

DA0

0

1

S[0]

S[2]

S[1]

S[3]

DA1

DB0

DB1

表7-53. JMODE 35 (8-bit, Dual Channel, 4 lanes)

OCTET

0

NIBBLE

DA0

0

1

A[0]

A[1]

B[0]

B[1]

DA1

DB0

DB1

表7-54. JMODE 37 (15-bit, Dual Channel, Decimate-by-4, 4 lanes)

OCTET

0

1

NIBBLE

DA0

0

1

2

3

AI[0], ORA0[0]

AQ[0], ORA1[0]

BI[0], ORB0[0]

BQ[0], ORB1[0]

DA1

DB0

DB1

表7-55. JMODE 38 (15-bit, Single Channel, Decimate-by-8, 2 lanes)

OCTET

NIBBLE

DA0

0

1

I[0], OR0[0]

Q[0], OR1[0]

DB0

表7-56. JMODE 39 (15-bit, Dual Channel, Decimate-by-8, 2 lanes)

OCTET

NIBBLE

DA0

0

1

2

3

0

1

2

3

4

5

6

7

AI[0], ORA0[0]

BI[0], ORB0[0]

AQ[0], ORA1[0]

BQ[0], ORB1[0]

DB0

English Data Sheet: SLVSGV2

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表7-57. JMODE 56 (15-bit, Dual Channel, Decimate-by-16, 2 lanes)

OCTET

0

1

2

3

NIBBLE

DA0

0

1

2

3

4

5

6

7

AI[0], ORA0[0]

BI[0], ORB0[0]

AQ[0], ORA1[0]

BQ[0], ORB1[0]

DB0

7.4.4.4 64B/66B Sync Header Stream Configuration

The sync header stream can be used to identify bit errors on the link or to correct bit errors. Two modes of

operation are available in the device. Cyclic redundancy checking (CRC) can be used to identify bit errors. The

device only supports 12-bit CRC (CRC-12) and does not support the optional 3-bit CRC-3 described by

JESD204C. Alternatively, forward error correction (FEC) can be used to identify bit errors and then correct bit

errors. For information on CRC-12, see Cyclic Redundancy Check (CRC) Mode. For information on FEC, see

Forward Error Correction (FEC) Mode. Set the sync header stream configuration by using the sync header mode

register.