V62P22612-01XE_技术文档

LMK04832-SEP

ZHCSPJ6A –OCTOBER 2022 –REVISED NOVEMBER 2022

LMK04832-SEP 符合JESD204B/C 标准的航天级、超低噪声、双环路时钟抖动

清除器

1 特性

3 说明

• VID#：V62/22612

LMK04832-SEP 是一款适用于航天应用、支持JEDEC

JESD204B/C 的高性能时钟调节器。

– 电离辐射总剂量30krad（无ELDRS）

– SEL 抗扰度> 43MeV × cm²/mg

– SEFI 抗扰度> 43MeV × cm²/mg

• 环境温度范围：-55°C 至125°C

• 最高时钟输出频率：3255MHz

• 多模式：双PLL、单PLL 和时钟分配

• 6GHz 外部VCO 或分配输入

PLL2 可以配置 14 个时钟输出以驱动 7 个

JESD204B/C 转换器或其他逻辑器件（使用器件和

SYSREF 时钟）。SYSREF 可以通过直流和交流耦合

提供。14 个输出中的每一个输出都可以单独配置为用

于传统时钟系统的高性能输出（不限于 JESD204B/C

应用）。

• 超低噪声（2500MHz 时）：

无论有无 SYSREF 生成或重新计时，该器件都可以配

置为在双 PLL、单 PLL 或时钟分配模式下运行。PLL2

可以使用内部或外部VCO 工作。

– 54fs RMS 抖动（12kHz 至20MHz）

– 64fs RMS 抖动（100Hz 至20MHz）

– –157.6dBc/Hz 本底噪声

• 超低噪声（3200MHz 时）：

– 61fs RMS 抖动（12kHz 至20MHz）

– 67fs RMS 抖动（100Hz 至100MHz）

– –156.5dBc/Hz 本底噪声

高性能与多种特性（如功耗和性能权衡调节、双

VCO、动态数字延迟和保持）相结合，可提供灵活的

高性能时钟树。

封装信息

等级

• PLL2

封装⁽¹⁾

器件型号

– –230dBc/Hz PLL FOM

– –128dBc/Hz PLL 1/f

– 相位检测器频率高达320MHz

– 两个集成VCO：2440MHz 至2600MHz

和2945MHz 至3255MHz

V62P22612-01XE

30krad

64 引脚

PAP0064E

10mm x 10mm

LMK04832MPAPSEP

LMK0483PAP/EM

工程样片⁽²⁾

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

(2) 这些器件不适用于飞行系统用途，仅用于工程评估。

• 多达14 个差分器件时钟

– CML、LVPECL、LCPECL、HSDS、LVDS 和

2xLVCMOS 可编程输出

CPOUT1

FIN1

Input Switching/Holdover

CLKIN0

• 最多1 个缓冲VCXO/XO 输出

FIN0

CLKIN1/

FIN1/

FPCLKIN

Phase

Switchable R Divider

÷2

Detector/

Charge

Pump

– LVPECL、LVDS、2xLVCMOS 可编程输出

• 1-1023 CLKOUT 分频器

• 1-8191 SYSREF 分频器

PLL1

CLKIN2/

OSCOUT

N Divider

CPOUT2

N Divider

• SYSREF 时钟25ps 阶跃模拟延迟

• 器件时钟和SYSREF 数字延迟和动态数字延迟

• PLL1 保持模式

• PLL1 或PLL2 0 延迟

• 高可靠性

– 受控基线

Phase

Detector/

Charge

Pump

OSCIN

CLKIN1

CLKOUT6

CLKOUT8

SYSREFDIV

PLL2

SCK

Control

Registers

SDIO

SPI

X2

R Divider

CS#

Clock Distribution Path

STATUS_LD1

CLKOUT0

CLKOUT1

÷1,÷2,..,÷1023

ꢀ

SYSREF/SYNC

STATUS_LD2

RESET/GPO

CLKIN_SEL0

CLKIN_SEL1

Device

Control

SYSREFDIV

Divider

14 Di eren al

– 一个组装/测试场所

– 一个制造场所

– 延长的产品生命周期

– 延长的产品变更通知

– 产品可追溯性

...

SYNC/SYSREF

Distribution Path

Outputs

SYNC

CLKOUT12

ꢀ

CLKIN0

Pulser

÷1,÷2,..,÷1023

ꢀ

CLKOUT13

方框图

2 应用

• 通信有效负载

• 雷达成像有效载荷

• 命令和数据处理

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS838

LMK04832-SEP

ZHCSPJ6A –OCTOBER 2022 –REVISED NOVEMBER 2022

www.ti.com.cn

Table of Contents

8.3 Feature Description...................................................25

8.4 Device Functional Modes..........................................36

8.5 Programming............................................................ 38

8.6 Register Maps...........................................................39

9 Application and Implementation..................................85

9.1 Application Information............................................. 85

9.2 Typical Application.................................................... 89

9.3 Power Supply Recommendations.............................92

9.4 Layout....................................................................... 93

10 Device and Documentation Support..........................96

10.1 Device Support....................................................... 96

10.2 Documentation Support.......................................... 96

10.3 接收文档更新通知................................................... 96

10.4 支持资源..................................................................96

10.5 Trademarks.............................................................96

10.6 Electrostatic Discharge Caution..............................96

10.7 术语表..................................................................... 96

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................7

6.6 Timing Requirements................................................13

6.7 Timing Diagram.........................................................13

6.8 Typical Characteristics .............................................14

7 Parameter Measurement Information..........................15

7.1 Charge Pump Current Specification Definitions........15

7.2 Differential Voltage Measurement Terminology........ 16

8 Detailed Description......................................................17

8.1 Overview...................................................................17

8.2 Functional Block Diagram.........................................22

Information.................................................................... 97

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (October 2022) to Revision A (November 2022)

Page

• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1

2

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5 Pin Configuration and Functions

VCC5_DIG

CLKIN1_P/FIN1_P/FBCLKIN_P

CLKIN1_N/FIN1_N/FBCLK_N

VCC6_PLL1

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

CLKOUT2_N

CLKOUT2_P

CLKOUT3_N

CLKOUT3_P

LDOBYP2

2

3

4

CLKIN0_P

5

CLKIN0_N

6

LDOBYP1

VCC7_OSCOUT

OSCOUT_P/CLKIN2_P

OSCOUT_N/CLKIN2_N

VCC8_OSCIN

7

VCC1_VCO

FIN0_N

8

DAP

9

FIN0_P

10

11

12

13

14

15

16

GND

OSCIN_P

SYNC/SYSREF_REQ

RESET/GPO

CLKOUT1_N

CLKOUT1_P

CLKOUT0_N

CLKOUT0_P

OSCIN_N

VCC9_CP2

CPOUT2

VCC10_PLL2

STATUS_LD2

Not to scale

图5-1. PAP Package 64-Pin HTQFP Top View

表5-1. Pin Functions

I/O

TYPE

DESCRIPTION

NO.

NAME

VCC5_DIG

1

PWR

Power supply for the digital circuitry.

–

CLKIN1_P: Reference Clock input port 1 for PLL1. FIN1_P: External

VCO input or clock distribution input. FBCLKIN_P: Feedback input for

external clock feedback input (0–delay mode).

CLKIN1_P/

FIN1_P/

FBCLKIN_P

2

I

ANLG

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表5-1. Pin Functions (continued)

I/O

TYPE

DESCRIPTION

NO.

NAME

CLKIN1_N

FIN1_N

Reference Clock input port 1 for PLL1.

External VCO input or clock distribution input.

3

I

ANLG

FBCLK_N

Feedback input for external clock feedback input (0–delay mode).

4

5

6

7

VCC6_PLL1

CLKIN0_P

PWR

ANLG

Power supply for PLL1, charge pump 1, holdover DAC

–

I

Reference Clock input port 0 for PLL1.

CLKIN0_N

VCC7_OSCOUT

OSCOUT_P

CLKIN2_P

PWR

Power supply for OSCOUT pins.

Buffered output of OSCIN pins

Reference Clock input port 2 for PLL1.

Buffered output of OSCIN pins

Reference Clock input port 2 for PLL1.

Power supply for OSCIN

–

8

9

I/O

Programmable

OSCOUT_N

CLKIN2_N

I/O

Programmable

PWR

10

11

12

13

14

15

16

17

VCC8_OSCIN

OSCIN_P

–

I

ANLG

Feedback to PLL1 and reference input to PLL2. AC-coupled.

OSCIN_N

VCC9_CP2

CPOUT2

PWR

ANLG

Power supply for PLL2 charge pump.

Charge pump 2 output.

–

O

VCC10_PLL2

STATUS_LD2

CLKOUT9_P

PWR

Power supply for PLL2.

–

I/O

Programmable

Programmable status pin.

Clock output 9. For JESD204B/C systems suggest SYSREF Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

O

Programmable

18

19

20

CLKOUT9_N

CLKOUT8_P

CLKOUT8_N

Clock output 8. For JESD204B/C systems suggest Device Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

Programmable

PWR

21

22

VCC11_CG3

Power supply for clock outputs 8, 9, 10, and 11.

–

CLKOUT10_P

Clock output 10. For JESD204B/C systems suggest Device Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

O

Programmable

23

24

25

CLKOUT10_N

CLKOUT11_P

CLKOUT11_N

Clock output 11. For JESD204B/C systems suggest SYSREF Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

O

Programmable

26

27

28

CLKin_SEL0

CLKIN_SEL1

CLKOUT13_P

I/O

Programmable

Programmable status pin.

Clock output 13. For JESD204B/C systems suggest SYSREF Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

O

Programmable

29

CLKOUT13_N

Clock output 12. For JESD204B/C systems suggest Device Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

30

31

32

33

34

35

CLKOUT12_P

CLKOUT12_N

VCC12_CG0

CLKOUT0_P

CLKOUT0_N

CLKOUT1_P

Programmable

PWR

Power supply for clock outputs 0, 1, 12, and 13.

–

Clock output 0. For JESD204B/C systems suggest Device Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

O

Programmable

Clock output 1. For JESD204B/C systems suggest SYSREF Clock.

Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

O

Programmable

36

37

CLKOUT1_N

RESET/GPO

I

CMOS

GND

Device reset input or GPO

SYNC/

SYSREF_REQ

Synchronization input or SYSREF_REQ for requesting continuous

SYSREF.

38

39

GND

This pin should be grounded.

–

4

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表5-1. Pin Functions (continued)

I/O

TYPE

DESCRIPTION

NO.

40

41

42

43

44

45

NAME

FIN0_P

FIN0_N

High-speed input for external VCO or clock distribution. Supports /2 for

frequency greater than 3250 MHz.

I

ANLG

VCC1_VCO

LDOBYP1

PWR

ANLG

Power supply for VCO and clock distribution.

–

LDO Bypass, bypassed to ground with 10-µF capacitor.

LDO Bypass, bypassed to ground with a 0.1-µF capacitor.

LDOBYP2

CLKOUT3_P

Clock output 3. For JESD204B/C systems suggest SYSREF Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

O

Programmable

46

CLKOUT3_N

47

48

49

50

51

52

53

54

CLKOUT2_P

CLKOUT2_N

VCC2_CG1

CS#

Clock output 2. For JESD204B/C systems suggest Device Clock.

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

PWR

CMOS

PWR

Power supply for clock outputs 2 and 3.

–

I

Chip Select

SCK

I

SPI Clock

SDIO

I/O

SPI Data

VCC3_SYSREF

CLKOUT5_P

Power supply for SYSREF divider and SYNC.

–

Clock output 5. For JESD204B/C systems suggest SYSREF Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

O

Programmable

55

CLKOUT5_N

Clock output 4. For JESD204B/C systems suggest Device Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

56

57

58

59

60

61

CLKOUT4_P

CLKOUT4_N

VCC4_CG2

CLKOUT6_P

CLKOUT6_N

CLKOUT7_P

O

Programmable

PWR

Power supply for clock outputs 4, 5, 6 and 7.

–

Clock output 6. For JESD204B/C systems suggest Device Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

O

Programmable

Clock output 7. For JESD204B/C systems suggest SYSREF Clock.⁽¹⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or

2xLVCMOS.

O

Programmable

62

CLKOUT7_N

63

STATUS_LD1

CPOUT1

DAP

I/O

O

Programmable

ANLG

Programmable status pin.

64

Charge pump 1 output.

DAP

GND

DIE ATTACH PAD, connect to GND.

–

(1) Actual best allocation of device clocks and SYSREF depends upon frequency planning to group common frequencies.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

SYMBOL

V_DD,V_{DD_A}

V_IN

PARAMETER

MIN

–0.3

MAX

3.6

UNIT

V

Power supply voltage

Input voltage

V_DD+ 0.3

V

Differential input current (CLKIN_P/N,

OSCIN_P/N,FIN0_P/N,FIN1_P/N

I_IN

5

mA

T_J

Junction Temperature

Storage temperature

150

°C

T_stg

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

SYMBOL

PARAMETER

CONDITION

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,

all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/JEDEC

JS-002, all pins⁽²⁾

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over case temperature range (unless otherwise noted)

SYMBOL

PARAMETER

MIN

3.135

–55

NOM

3.3

MAX

3.465

125

UNIT

V_DD

IO supply voltage

V

V_{DD_A}

T_A

Core supply voltage

Ambient Temperature

3.3

°C

6.4 Thermal Information

PAP (HTQFP)

SYMBOL

THERMAL METRIC⁽¹⁾

UNIT

64 PINS

21.3

8.3

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-board thermal resistance

6.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

Ψ_JT

6.8

Ψ_JB

R_θJC(bot)

0.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

VDD, VDD_A = 3.3 V ± 5 %, –55 °C ≤T_A≤125 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Current Consumption

Power Down Supply Current

Device Powered Down

3.3

5

4 CML 32 mA clocks in

bypass

3 LVDS clock /12

4 SYSREF as LCPECL

3 SYSREF as LVDS

980

850

700

4 CML 32 mA clocks in

bypass

3 LVDS clock /12

4 SYSREF as LCPECL

(low state)

PLL1 locked to

external VCXO and

PLL2 locked to

internal VCO

I_CC

mA

Supply Current⁽¹⁾

3 SYSREF as LVDS

(low state)

4 CML 32 mA clocks in

bypass

3 LVDS clock /12

7 SYSREF outputs

powered down

CLKIN Specifications

LOS Circuitry

LOS_EN = 1

0.001

125

250

CLKinX-

TYPE=1(MOS)

AC Coupled Input

PLL1

PLL2

CLKinX-TYPE=0

(Bipolar)

0.001

750

MHz

500

f_CLKINx

CLKinX_TYPE=0

(Bipolar)

0-delay with external

feedback (CLKIN1)

0-delay

750

Distribution Mode

CLKIN1/FIN1 Pin only AC Coupled Input

0.001

0.15

3250

V/ns

SLEW_CLKINInput Slew Rate⁽²⁾

V_CLKINx/FIN1Single-ended clock input voltage

V_IDCLKINX/

0.5

Input pin AC coupled; complementary pin AC

coupled to GND

0.5

0.125

0.25

2.4 Vpp

1.55

|V|

FIN1

Differential clock input voltage⁽³⁾

V_SSCLKINx/

AC coupled

3.1 Vpp

|mV|

FIN1

CLKIN0/1/2 (Bipolar)

CLKIN0/1 (MOS)

CLKIN2 (MOS)

0

55

20

|V_CLKINX

offset|

-

DC offset voltage between CLKIN /

CLKINX* Each Pin AC Coupled

V_CLKINVIH

V_CLKINVIL

High Input Voltage

Low Input Voltage

V_CLKIN-V_IH

V_CLKIN-V_IL

DC Coupled Input

2

0

Vcc

0.4

V

FIN0 Input Pin

f_FIN0

FIN0_DIV2_EN=1

FIN0_DIV2_EN=2

1

3250 MHz

6400 MHz

1.55 Vpp

3.1 Vpp

AC Coupled Slew

Rate > 150 V/us

External Input Frequency

f_FIN0

V_IDFIN0

V_SSFIN0

0.125

0.25

Differential Input Voltage

AC Coupled

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VDD, VDD_A = 3.3 V ± 5 %, –55 °C ≤T_A≤125 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PLL 1 Specifications

f_PD1

Phase Detector Frequency

40 MHz

PLL1_CP_GAIN = 350 µA

–117

–118

–221.5

–223

50

PN10kHz

PLL Normalized 1/f Noise⁽⁴⁾

PLL1_CP_GAIN = 1550 µA

PLL1_CP_GAIN = 350 µA

PLL1_CP_GAIN = 1550 µA

dBc/Hz

PN FOM

PLL Figure of Merit⁽⁵⁾

PLL1_CP_GAIN=0

PLL1_CP_GAIN=1

PLL1_CP_GAIN=2

PLL1_CP_GAIN=4

PLL1_CP_GAIN=8

150

I_CPOUT1

Charge Pump Current⁽⁶⁾

VCPout=Vcc/2

250

µA

450

850

I_CPOUT1%MI Charge Pump Sink / Source

V_CPout1= Vcc/2, T =

25 °C

V_CPout1= Vcc/2, T = 25

°C

1

2

10

%

S

Mismatch

I_CPOUT1V_TUNMagnitude of Charge Pump Current 0.5 V < V_CPout1< V_CC0.5 V < V_CPout1< V_CC

-

Variation vs. Charge Pump Voltage - 0.5 V T_A= 25 °C

0.5 V T_A= 25 °C

E

I_CPOUT1%TE Charge Pump Current vs.

%

MP

Temperature Varation

Charge Pump TRI_STATE Leakage

Current

I_CPOUT1TRI

OSCIN Input

nA

EN_PLL2_REF_2X=0

EN_PLL2_REF_2X=1

0.001

0.15

500

320

f_OSCIN

MHz

V/ns

SLEW_OSCINInput Slew Rate

0.5

Input voltage for OSCIN_P or

OSCIN_N

AC coupled; single-ended; unused pin AC

coupled to GND

V_OSCIN

0.2

2.4 Vpp

V_IDOSCIN

V_SSOSCIN

0.2

0.4

1.55

|V|

Differential voltage swing⁽³⁾

AC coupled

3.1 Vpp

DC offset voltage between

CLKINx_P/CLKINx_N. Each Pin AC

Coupled

V_CLKINxOffse

t

20

mV

320 MHz

dBc/Hz

PLL 2 Specifications

f_PD

Phase Detector Frequency

PLL2_CP_GAIN = 1600 uA

PLL2_CP_GAIN = 3200 uA

PLL2_CP_GAIN = 1600 uA

PLL2_CP_GAIN = 3200 uA

PLL2_CP_GAIN=2

–123

–128

–226.5

–230

1600

PN10kHz

PLL Normalized 1/f Noise⁽⁴⁾

PLL Figure of Merit⁽⁵⁾

PN FOM

I_CPOUT

Charge Pump Current Magnitude⁽⁶⁾V_CPOUT=Vcc/2

µA

PLL2_CP_GAIN=3

3200

I_CPOUT1%MI Charge Pump Sink / Source

V_CPOUT= Vcc/2, T =

25 °C

V_CPOUT1= Vcc/2, T = 25

°C

1

2

3

10

%

S

Mismatch

Magnitude of Charge Pump Current 0.5 V < V_CPOUT1

Variation vs. Charge Pump Voltage V_CC- 0.5 V T_A= 25 °C 0.5 V T_A= 25 °C

<

0.5 V < V_CPOUT1< V_CC

-

I_CPout1V_TUNE

I_CPOUT%TE Charge Pump Current vs.

%

MP

Temperature Variation

Charge Pump TRI_STATE Leakage

Current

I_CPOUT1TRI

nA

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VDD, VDD_A = 3.3 V ± 5 %, –55 °C ≤T_A≤125 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Internal VCO Specifications

VCO0

VCO1

VCO0

VCO1

VCO0

VCO1

10 kHz

100 kHz

2440

2945

2600

MHz

3255

f_VCO

VCO Frequency Range

13

26

K_VCO

|ΔT_CL

VCO Tuning Sensitivity

MHz/V

Allowable temperature Drift for Continuous Lock⁽⁷⁾

150

180

^oC

|

–88.4

–117

VCO0 at 2440 MHz

800 kHz

1 MHz

–137.5

–139.7

–152.6

–85.7

10 MHz

10 kHz

100 kHz

800 kHz

1 MHz

L(f)VCO

Open Loop VCO Phase Noise

dBc/Hz

–115.8

–137

VCO0 at 2580 MHz

–138.6

–151.8

–82.6

10 MHz

10 kHz

100 kHz

800 kHz

1 MHz

–112.3

–134.9

–137.2

–151.1

–81

VCO1 at 2945 MHz

10 MHz

10 kHz

100 kHz

800 kHz

1 MHz

L(f)VCO

Open Loop VCO Phase Noise

dBc/Hz

–110.4

–134.3

–135.6

–149.3

VCO1 at 3250 MHz

10 MHz

Output Clock Skew and Timing

Same Pair of Device clocks and same format

Even to Even or Odd to Odd, Same Format

35

15

SKEW_CLKOU

Output to Output Skew

ps

TX

Even clock to Odd

Clock

35

Additive Jitter in Distribution Mode from FIN Pin (note 6)

LVCMOS

LVDS

50

40

35

40

35

245.76 MHz Output

Additive jitter, Distribution mode with Frequency,

LVPECL

LCPECL

HSDS

L(f)_CLKOUT

fs

no divide

12k-20MHz

integration bandwidth

CML

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VDD, VDD_A = 3.3 V ± 5 %, –55 °C ≤T_A≤125 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

LVCMOS Outputs

f_CLKOUT

Frequency

Noise Floor

5 pF Load

250 MHz

dBc/Hz

L(f)_CLKOUT

245.76 MHz

1 mA load

20 MHz Offset

–160

Vcc–

V_OH

Output High Voltage

V

0.1

V_OL

I_OH

Output Low Voltage

Output High Current

Output Low Current

Output Duty Cycle

1 mA load

FD=1.65V

Vd=1.65V

0.1

V

mA

%

–28

28

I_OL

ODC

50

LVDS Clock Outputs

L(f)_CLKOUT

T_R/T_F

Noise Floor

245.76 MHz output

20 MHz Offset

dBc/Hz

ps

–159.5

175

20% to 80% Rise/Fall Time, f_OUT≥1 GHz

V_OD

Differential Output Voltage

350

mV

Change in V_ODfor complimentary

output states

60

1.375

35

mV

V

ΔV_OD

V_OS

–60

DC Measurement, AC coupled to receiver input

R_L= 100 Ωdifferential

Output Offset Voltage

1.125

1.25

Change on VOS for complimentary

Output states

mV

mA

ΔV_OS

I_SHORT

Short circuit Output Current

24

–24

LCPECL Clock Outputs

L(f)_CLKOUT

T_R/T_F

V_OH

Noise Floor

245.76 MHz output

_OUT≥1 GHz

20 MHz Offset

dBc/Hz

–162.5

135

20% to 80% Rise/Fall Time

Output High Voltage

Output Low Voltage

ps

V

f

1.4

DC Measurement with

50-Ωto 0.5V

V_OL

0.6

V

DC Measurement with

50-Ωto 0.5V

V_OD

Differential Output Voltage

870

mV

LVPECL Clock Outputs

245.76 MHz output,

LVPECL 2.0 V

L(f)_CLKOUT

T_R/T_F

Noise Floor

20 MHz Offset

dBc/Hz

ps

–163

20% to 80% Rise/Fall Time

135

f

_OUT≥1 GHz

LVPECL 1.6 V

LVPECL 2.0 V

Vcc–1

V_OH

Output High Voltage

V

Vcc–

DC Measurement

termination 50 Ωto

Vcc-2 V

1.1

Vcc–

LVPECL 1.6 V

1.8

V_OL

Output Low Voltage

V

LVPECL 2.0 V

LVPECL 1.6 V

Vcc–2

0.7

2.5 GHz, Em = 120 Ω

to GND, R_L= AC

coupled 100 Ω

V_OD

Differential Output Voltage

LVPECL 2.0 V

0.9

HSDS Clock Outputs

L(f)_CLKOUT

T_R/T_F

Noise Floor

20% to 80% Rise/Fall Time

245.76 MHz output

20 MHz Offset

dBc/Hz

ps

–162

170

f

_OUT≥1 GHz

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VDD, VDD_A = 3.3 V ± 5 %, –55 °C ≤T_A≤125 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Vcc–

HSDS 6 mA

0.9

V_OH

Output High Voltage

V

Vcc–

HSDS 8 mA

1.0

DC Measurement with

50 Ωto 0.5V

Vcc–

HSDS 6 mA

HSDS 8 mA

1.5

V_OL

Output Low Voltage

Output Voltage

V

Vcc–

1.7

HSDS 6 mA

HSDS 8 mA

HSDS 6 mA

HSDS 8 mA

0.5

V_OD

0.75

DC Measurement with

50 Ωto 0.5V

80

mV

115

–80

Change on VOS for complimentary

Output states

ΔV_OD

–115

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VDD, VDD_A = 3.3 V ± 5 %, –55 °C ≤T_A≤125 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

SYMBOL

CML Outputs

L(f)_CLKOUT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Noise Floor

20 MHz Offset

dBc/Hz

–163

140

CML 16 mA

T_R/T_F

V_OH

20% to 80% Rise/Fall Time

Output High Voltage

CML 24 mA

CML 32 mA

140

ps

V

f

_OUT≥1.5 GHz

140

Vcc-0.1

50 Ωpull up to Vcc, DC Measurement

Vcc–

CML 16 mA

0.8

50 Ωpull up to Vcc,

CML 24 mA

Vcc–

V_OL

Output Low Voltage

V

DC Measurement

1.1

Vcc–

CML 32 mA

CML 16 mA

1.4

680

1000

1300

550

50 Ωpull up to Vcc,

DC Measurement

CML 24 mA

mV

CML 32 mA

V_OD

Output Voltage

CML 16 mA

CML 24 mA

50 Ωpull up to Vcc,

DC Measurement, R_L

= AC coupled 100 Ω,

250 MHz

815

CML 32 mA

1070

Digital Outputs (CLKin_SELX,STATUS_LDX, and RESET/GPO,SDIO)

Vcc–

V_OH

Output High Voltage

Output Low Voltage

V

0.4

V_OL

0.4

V

Digital Inputs

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.2

V

0.5

80

25

RESET/GPO,SYNC,SCK,SDIO, CS#

I_IH

High-level input current

uA

SYNC

V_IH= V_CC

CLKINX_SEL,RESET/GPO,SYNC,SCK,SDIO,

CS#

I_IL

Low-level input current

5

–5

uA

SYNC

V_IL= 0 V

(1) Use the TICS Pro tool to calculate Icc for a specific configuration

(2) Device will function with slew rate as low as 0.15 V/ns, however a slew rate of 0.5 V/ns or higher is recommended to get the best

phase noise performance.

(3) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.

(4) The normalized PLL 1/f noise is a specification in modeling PLL in-band phase noise is that is close to the carrier and has a

characteristic 10 dB/decade slope. PN10 kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10 kHz =

LPLL_flicker(10 kHz) - 20 log(f_OUT/ 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's

contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high

compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can

be masked by the reference oscillator performance if a low-power or noisy source is used. The total PLL in-band phase noise

performance is the sum of LPLL_flicker(f) and LPLL_flat(f)

(5) The PLL figure of merit is a normalized metric used to quantify the flat portion of the in-band phase noise. It is calculated as PN_FOM

= LPLL_flat(f) - 20 log(N) - 10 log(f_PDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz

bandwidth and f_PDXis the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). This metric is

measured using a CLKIN input. If the OSCin input is used, the metric is about 2 dB worse.

(6) This parameter is programmable to more states than are shown in the electrical specifications

(7) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was

at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of

programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over

the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be

necessary to reload the appropriate register to ensure it stays in lock. This parameter is indirectly tested.

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6.6 Timing Requirements

VDD, VDD_A = 3.3 V ± 5 %, –55 °C ≤TA ≤125 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

SYMBOL

PARAMETER

MIN

NOM

MAX UNIT

Timing Requirements

td_S

Setup time for SDI edge to SCK rising edge

Hold time for SDI edge to SCK rising edge

40

20

ns

td_H

t_SCK

t_HIGH

t_LOW

t_CS

Period of SCK

400

120

40

High width of SCK

Low width of SCK

Setup time for CS# falling edge to SCK rising edge

Hold time for CS# rising edge from SCK rising edge

SCK falling edge to valid read back data

t_CH

40

t_DV

120

ns

6.7 Timing Diagram

Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK

signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed.

A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the CS* signal

should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is

sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this

programming.

4-wire mode read back has same timing as SDIO pin.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

SDIO

(WRITE)

A12 to A0,

D7 to D2

R/W

A14

A13

D1

D0

td_S

td_H

SCK

tc_H

tc_S

t_HIGH

t_LOW

t_SCK

SDIO

(Read)

D7 to

D2

D1

D0

td_V

CS*

图6-1. SPI Timing Diagram

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6.8 Typical Characteristics

Jitter from 100 Hz to 100 MHz = 63.6 fs rms.

Output is CLKOUT4 as CML 32 mA with 68-nH to 20-ΩDC

bias.

Jitter from 100 Hz to 100 MHz = 67 fs rms.

Output is CLKOUT4 as CML 32 mA with 68-nH to 20-ΩDC

bias.

Other settings are CLKout4_5_IDL = 1

and CLKout4_5_BYP = 1.

Other settings are CLKout4_5_IDL = 1

and CLKout4_5_BYP = 1.

PLL2 Loop Filter R2 = 470 Ω, C2 = 150 nF,

Charge Pump = 3200 µA.

PLL2 Loop Filter R2 = 470 Ω, C2 = 150 nF,

Charge Pump = 3200 µA.

Reference is R&S SMA100B Signal Generator with option

SMAB - B711 through Prodyn BIB-100G Balun to OSCin.

Reference is R&S SMA100B Signal Generator with option

SMAB - B711 through Prodyn BIB-100G Balun to OSCin.

图6-2. PLL2 With VCO1 Performance at 2500 MHz

With 312.5-MHz OSCin/Phase Detector Frequency

图6-3. PLL2 With VCO1 Performance at 3200 MHz

With 320-MHz OSCin/Phase Detector Frequency

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7 Parameter Measurement Information

7.1 Charge Pump Current Specification Definitions

I1 = Charge Pump Sink Current at V_CPout= V_CC- ΔV

I2 = Charge Pump Sink Current at V_CPout= V_CC/2

I3 = Charge Pump Sink Current at V_CPout= ΔV

I4 = Charge Pump Source Current at V_CPout= V_CC- ΔV

I5 = Charge Pump Source Current at V_CPout= V_CC/2

I6 = Charge Pump Source Current at V_CPout= ΔV

ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.

7.1.1 Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage

7.1.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch

7.1.3 Charge Pump Output Current Magnitude Variation vs Ambient Temperature

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7.2 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions causing confusion

when reading data sheets or communicating with other engineers. This section will address the measurement

and description of a differential signal so that the reader will be able to understand and distinguish between the

two different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and noninverting signal. The symbol for this first measurement is typically V_IDor V_ODdepending on if

an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the noninverting signal

with respect to the inverting signal. The symbol for this second measurement is V_SSand is a calculated

parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its

differential pair. V_SScan be measured directly by oscilloscopes with floating references, otherwise this value can

be calculated as twice the value of V_ODas described in the first description.

图 7-1 shows the two different definitions side-by-side for inputs and 图 7-2 shows the two different definitions

side-by-side for outputs. The V_IDand V_ODdefinitions show V_Aand V_BDC levels that the noninverting and

inverting signals toggle between with respect to ground. V_SSinput and output definitions show that if the

inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now

increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the

differential signal can be measured.

V_IDand V_ODare often defined as volts (V) and V_SSis often defined as volts peak-to-peak (V_PP).

V_IDDefinition

V_SSDefinition for Input

Noninverting Clock

V_A

V_B

2 × V_ID

V_ID

Inverting Clock

V_ID= | V_AV_B

|

V_SS= 2 × V_ID

GND

图7-1. Two Different Definitions for Differential Input Signals

V_ODDefinition

V_SSDefinition for Output

Non-Inverting Clock

V_A

V_B

2·V_OD

V_OD

Inverting Clock

V_OD= | V_A- V_B

|

V_SS= 2·V_OD

GND

图7-2. Two Different Definitions for Differential Output Signals

Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for

more information.

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8 Detailed Description

8.1 Overview

This device is very flexible to meet many application requirements. Use cases include dual loop, dual loop 0-

delay nested, dual loop 0-delay cascaded, single loop, single loop 0-delay, and clock distribution.

The device may be used in JESD204B/C systems by providing a device clock and SYSREF to target devices,

however traditional (non-JESD204B/C) systems are possible by programming pairs of outputs to share the clock

divider or any mix of JESD204B/C and traditional outputs.

8.1.1 Differences from the LMK04832

The LMK04832 is a widely known device that is similar to this device. However, these devices are not the same

and there are some differences.

表8-1. Differences Between the LMK04832-SEP and LMK04832

Attribute

Radiation Hardened

Temperature

LMK04832

LMK04832-SEP

No

50 MeV

–40ºC to +85ºC

10 × 10 mm

n/a

–55ºC to +125ºC

10 × 10 mm

Package

Pin Rotation

Rotated 180° from LMK04832

Yes, Pins 40/41 are FIN0_P/FIN0_N

GND (Pin 39)

6.4 GHz CLK/VCO Input Pin

Pin After SYNC/SYSREFREQ Pin

Programming Speed

No, Pins 8/9 are NC

NC (Pin 7)

5 MHz

2.5 MHz

8.1.1.1 Jitter Cleaning

The dual loop PLL architecture provides the lowest jitter performance over a wide range of output frequencies

and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external reference clock and

uses an external VCXO to provide a frequency accurate, low phase noise reference clock for the second stage

frequency multiplication PLL (PLL2).

PLL1 typically uses a narrow loop bandwidth (typically 10 Hz to 200 Hz) to retain the frequency accuracy of the

reference clock input signal while at the same time suppressing the higher offset frequency phase noise that the

reference clock may have accumulated along its path or from other circuits. This cleaned reference clock

provides the reference input to PLL2.

The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically 50

kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency

phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO.

Ultra-low jitter is achieved by allowing the phase noise of the external VCXO to dominate the final output phase

noise at low offset frequencies and the phase noise of the internal VCO to dominate the final output phase noise

at high offset frequencies. This results in best overall phase noise and jitter performance.

8.1.1.2 JEDEC JESD204B/C Support

This device clocks up to seven JESD204B/C targets using seven device clocks and seven SYSREF clocks and

allows every clock output to be configured as a device clock or SYSREF clock.

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8.1.2 Clock Inputs

备注

CLKIN1 can be used as a reference for dual loop, single loop, or clock distribution mode, providing

flexibility configuring the device for different operation modes from one clock input.

8.1.2.1 Inputs for PLL1

CLKIN0, CLKIN1, and CLKIN2 are the three redundant inputs with their own PLL1 R dividers that can be used

as a reference input to PLL1. The switching between these inputs can either be automatic or manual. For

manual switching, CLKIN_SEL0 and CLKIN_SEL1 pins can be used for faster speed. These input pins are also

shared for other functions.

• CLKIN1 is shared for use as an external 0-delay feedback (FBCLKIN), or for use with an external VCO (FIN).

• CLKIN2 is shared for use as OSCout. To use CLKIN2 as an input power down OSCout, see the VCO_MUX,

OSCout_MUX, OSCout_FMT section.

8.1.2.2 Inputs for PLL2

In dual loop configurations, the PLL2 reference is from OSCin. However, in single PLL2 loop operation, it is also

possible to use any of the three CLKIN inputs of PLL1 as a reference to PLL2.

8.1.2.3 Inputs When Using Clock Distribution Mode

For clock distribution mode, a reference signal may be applied to the FIN0 or FIN1 pins. CLKIN0 can be used to

distribute a SYSREF signal through the device. In this use case, CLKIN0 is re-clocked by CLKIN1. The FIN0

pins are generally recommended over the FIN1 pins because they allow higher frequency, use a lower noise

path, and cannot be used for other functions (like redundant input).

8.1.3 PLL1

PLL1 allows low offset jitter cleaning as well as the use of redundant inputs and frequency holdover.

8.1.3.1 Frequency Holdover

Frequency holdover keeps the clock outputs on frequency with minimum drift when the reference is lost until a

valid reference clock signal is re-established. This can only be used if PLL1 is used.

8.1.3.2 External VCXO for PLL1

When PLL1 is used, an external VCXO is required. The close-in noise performance of this VCXO is critical for

good jitter cleaning performance. The OSCout pin is powered on by default and gives a buffered copy of the

PLL1 feedback and PLL2 reference input at OSCin. This reference input is typically a low noise VCXO or XO.

This output can be used to clock external devices such as microcontrollers, FPGAs, CPLDs, and so forth, before

the device is programmed.

• The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS.

• The VCXO buffered output can be synchronized to the VCO clock distribution outputs by using Cascaded 0-

Delay Mode.

8.1.4 PLL2

8.1.4.1 Internal VCOs for PLL2

PLL2 has two internal VCOs. The output of the selected VCO is routed to the Clock Distribution Path. This same

selection is also fed back to the PLL2 phase detector through a prescaler and N-divider.

8.1.4.2 External VCO Mode

An external VCO can be used with PLL2 with the input for the external VCO coming through FIN0 or FIN1,

although FIN0 is generally preferred.

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备注

The FIN0_P/FIN0_N input is generally recommended because it is lower noise, supports higher input

frequency (up to 6 GHz if the div2 is used), and it leaves CLKIN1 available for redundant inputs.

FIN1_P/FIN1_N inputs are generally NOT recommended, for the reasons stated above, although they

can be used.

8.1.5 Clock Distribution

There are a total of 14 PLL2 clock outputs driven from the internal or external VCO.

All clock outputs have programmable output types. They can be programmed to CML, LVPECL, LVDS, HSDS, or

LCPECL. All odd clock outputs plus CLKOUT8 and CLKOUT10 may be programmed to LVCMOS.

In addition to these 14 clocks, there is also an additional OSCout output for a total of 15 differential output

clocks. OSCout may be a buffered version of OSCIN, DCLKOUT6, DCLKOUT8, or SYSREF. Its output format is

programmable to LVDS, LVPECL, or LVCMOS.

The following sections discuss specific features of the clock distribution channels that allow the user to control

various aspects of the output clocks.

8.1.5.1 Clock Divider

There are seven clock dividers. In a traditional clocking system, each divider can drive two outputs. The divider

range is 1 to 1023. Duty cycle correction may be enabled for the output. When the divider is used even clocks

may not output CML.

In a JESD204B/C system, one clock output is a device clock driven from the clock divider and the other paired

clock is from the SYSREF divider. For connectivity flexibility, either the even or odd clock output may be driven

by the clock divider or be the SYSREF output.

8.1.5.2 High Performance Divider Bypass Mode

The even clock outputs (CLKOUT0/2/4/6/8/10/12) may bypass the clock divider to achieve the best possible

noise floor and output swing. In this mode, the only usable output format is CML.

8.1.5.3 SYSREF Clock Divider

The SYSREF divider supports a divide range of 8 to 8191 (even and odd). There is no duty cycle correction for

the SYSREF divider. The SYSREF output may be routed to all clock outputs.

8.1.5.4 Device Clock Delay

The device clocks support digital delay for phase adjustment of the clock outputs.

The digital delay allows outputs to be delayed from 8 to 1023 VCO cycles. The delay step can be as small as

half the period of the clock distribution path. For example, a 3.2-GHz VCO frequency results in 156.25-ps steps.

The digital delay value takes effect on the clock output phase after a SYNC event.

8.1.5.5 Dynamic Digital Delay

The device clock dividers support a dynamic digital delay feature which allows the clock to be delayed by one full

device clock cycle. With a single programming, an adjustment of up to 255 one cycle delays may occur. When

making a multi-step adjustment, the adjustments are periodically applied to reduce impact to the clock.

Dynamic phase adjustments of half a clock distribution cycle are possible by half step.

The SYSREF digital delay value is reused for dynamic digital delay. To achieve a one cycle delay program the

SYSREF digital delay value to one greater than half the SYSREF divide value.

8.1.5.6 SYSREF Delay: Global and Local

The SYSREF divider includes a digital delay block which allows a global phase shift with respect to the device

clocks.

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Each clock output pair includes a local SYSREF analog and digital delay for unique phase adjustment of each

SYSREF clock.

The local analog delay allows for approximately 21-ps steps. Turning-on analog delay adds an additional 124 ps

of delay in the clock path. The digital delay step can be as small as half the period of the clock distribution path.

For example, a 3.2-GHz VCO frequency results in 156.25-ps steps.

The local digital delay and half step allows a SYSREF output to be delayed from 1.5 to 11 clock distribution path

cycles.

8.1.5.7 Programmable Output Formats

All clock outputs can be programmed to an LVDS, HSDS, LVPECL, or LCPECL output type. Odd clock outputs

in addition to CLKOUT8 and CLKOUT10 may also be programmed to LVCMOS. All odd clock outputs can also

be programmed to CML. When in bypass mode the even clock output may only be CML.

The OSCout can be programmed to an LVDS, LVPECL, or LVCMOS output type.

Any HSDS output type can be programmed to 6-mA or 8-mA amplitude levels.

Any LVPECL output type can be programmed to 1600-mVpp or 2000-mVpp amplitude levels. The 2000-mVpp

LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp differential

swing for compatibility with many data converters and is also known as 2VPECL.

LCPECL allows for DC-coupling SYSREF to low voltage JESD204B/C targets.

8.1.5.8 Clock Output Synchronization

Using the SYNC input causes all active clock outputs to share a rising edge as programmed by fixed digital

delay.

The SYNC event must occur for digital delay values to take effect.

8.1.6 0-Delay

Two types of 0-delay mode are supported.

1. Cascaded 0-delay

2. Nested 0-delay

Cascaded 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input clock

(OSCIN) to the phase of a clock output selected by the feedback mux. The 0-delay feedback uses internal

feedback from the CLKOUT6, CLKOUT8, or SYSREF. The 0-delay feedback can also be from an external

feedback through the FBCLKIN pins. The FB_MUX selects the feedback source. The OSCIN has a fixed

deterministic phase relationship to the feedback clock, therefore OSCout will also have a fixed deterministic

phase relationship to the feedback clock. In this mode, PLL1 input clock (CLKINx) also has a fixed deterministic

phase relationship to PLL2 input clock (OSCIN); this results in a fixed deterministic phase relationship between

all clocks from CLKINx to the clock outputs.

Nested 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL1 input clock

(CLKINx) to the phase of a clock output selected by the feedback mux. The 0-delay feedback uses internal

feedback from the CLKOUT6, CLKOUT8, or SYSREF. The 0-delay feedback can also be from an external

feedback through the FBCLKIN port. The FB_MUX selects the feedback source.

Without using 0-delay mode, there will be n possible fixed phase relationships from clock input to clock output

depending on the clock output divide value.

Using an external 0-delay feedback reduces the number of available clock inputs by one.

8.1.7 Status Pins

The status pins can be monitored for feedback or in some cases used for input depending upon device

programming. For example:

• The CLKin_SEL0 pin may indicate the LOS (loss-of-signal) for CLKIN0.

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• The CLKin_SEL1 pin may be an input for selecting the active clock input.

• The Status_LD1 pin may indicate if the device is locked.

• The Status_LD2 pin may indicate if PLL2 is locked.

The status pins can be programmed to a variety of other outputs including PLL divider outputs, combined PLL

lock detect signals, PLL1 Vtune railing, readback, and so forth. Refer to Register Maps for more information.

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8.2 Functional Block Diagram

图8-1 shows the high level block diagram.

Switching Control

Input clock switching

and Holdover

CLKin0

CLKIN0_P

_OUT

CLKIN0_N

_MUX

CLKin0

Switchable CLKIN0/1/2

R Divider (1 to 16,383)

CLKin

MUX

PLL 1

Phase

Detector/

Charge

Pump

CPOUT1

N1 Divider

(1 to 16,383)

CLKin1

_OUT

_MUX

CLKIN1_P/FIN_P/FBCLKIN_P

CLKIN1_N/FIN_N/FBCLKIN_N

Fin1

FB Mux

CLKOUT6

CLKOUT8

SYSREF Div

FB_

MUX

PLL1

_NCLK

_MUX

OSCOUT_P/CLKIN2_P

OSCOUT_N/CLKIN2_N

MUX

2X

Partially

Integrated

Loop Filter

PLL2

_REF

_2X_EN

R2 Divider

(1 to 4,095)

Internal Dual

Core VCO

PLL2

Phase

OSCIN_P

OSCIN_N

Detector/

Charge

Pump

PLL2

_NCLK

_MUX

N2 Divider

(1 to 262,143)

STATUS_LD1

STATUS_LD2

RESET/GPO

CLKIN_SEL0

CLKIN_SEL1

Device

Control

VCO0

VCO1

Clock Distribution Path

N2 Prescaler

(2 to 8)

VCO_

MUX

÷ 2

SCK

SDIO

CS#

MUX

FIN0_P

FIN0_N

Control

Registers

SPI

Fin1

SYSREF/SYNC Control

Divider

(8 to 8191)

CLKOUT12_P

CLKOUT12_N

Dig. Delay

Div (1 to 1023)

A. Delay

SYSREF/SYNC

Distribution Path

D

SYNC

D

CLKOUT13_P

CLKOUT13_N

CLKin0

Pulser

CLKOUT10_P

CLKOUT10_N

Dig. Delay

Div (1 to 1023)

A. Delay

CLKOUT0_P

CLKOUT0_N

Div (1 to 1023)

A. Delay

Dig. Delay

CLKOUT11_P

CLKOUT11_N

CLKOUT1_P

CLKOUT1_N

CLKOUT8_P

CLKOUT8_N

Dig. Delay

Div (1 to 1023)

A. Delay

CLKOUT2_P

CLKOUT2_N

Div (1 to 1023)

A. Delay

Dig. Delay

CLKOUT9_P

CLKOUT9_N

CLKOUT3_P

CLKOUT3_N

CLKOUT6_P

CLKOUT6_N

CLKOUT4_P

CLKOUT4_N

Div (1 to 1023)

A. Delay

Dig. Delay

Div (1 to 1023)

A. Delay

CLKOUT5_P

CLKOUT5_N

CLKOUT7_P

CLKOUT7_N

图8-1. High Level Block Diagram

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CLKout0, 2, 4, 6, 8, 10, 12

CLKoutX_

CLKoutX_Y_PD

Device Clock (DCLK)

FMT

DCLKX

_BYP

CML

DCLKX_Y

_POL

VCO

DCLKX_Y_ DCLKX_Y_

CLKoutX_

SRC_MUX

DCLKX_Y_

HS

DDLY

DIV

DCC

DCLKX_Y_

DCC

(8 to 1023)

(1 to 1023)

DDLYdX_Y_EN

DCLKout6/8 to FB_MUX

CLKoutX_Y_ODL

SYNC_

DISx

CLKoutX_Y_IDL

SYSREF_GBL_PD

SCLKX_Y_DIS_MODE

SYSREF Clock (SCLK)

SCLKX_Y

_ADLY_EN

SYSREF/SYNC

SCLKX_Y_

DDLY

SCLKX_Y

_HS

Analog

DLY

CLKoutY_

SRC_MUX

CLKoutY_

FMT

SYSREF_CLR

CLKout1, 3, 5, 7, 9, 11, 13

X = Even Numbers

Y = Odd Numbers

Legend

SPI Register

SYSREF/SYNC Clock

VCO/Distribution Clock

图8-2. Device and SYSREF Clock Output Block

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SPI Register: SYNC_EN

Must Be Set To Enable Any

SYNC/SYSREF Functionality

CLKIN0

CLKin0_

DEMUX

PLL1

D

SYNC_PLL1_DLD

PLL1_DLD

SYNC_PLL2_DLD

PLL2_DLD

SYSREF_REQ_EN

SYNC

_MODE

SYSREF_

MUX

SYNC

_POL

D

PULSER MODE

SYSREF_PULSE_CNT

One

Shot

Pulser

VCO0

VCO1

SYSREF_PLSR_PD

SYNC/SYSREF

VCO

_MUX

SYSREF

DDLY

SYSREF

Divider

SYSREF_

1SHOT_MUX

FIN0

External

VCO

SYSREF_PD

SYSREF_DDLY_PD

DCLKout6

DCLKout8

OSCin

OSCout

_MUX

SYNC_

DISSYSREF

FB_MUX

OSCout

CLKin1

CLKIN1

FB_MUX

PLL1

CLKin1_

DEMUX

DCLKout0, 2, 4, 6, 8, 10, 12

Clock

VCO Frequency

DDLY

(4 to 32)

Divider

(1 to 32)

Output

Buffer

Distribution Path

DCC

SYNC_

DISX

SYSREF/SYNC

Digital

DLY

Analog

DLY

Output

Buffer

Legend

SYSREF_CLR

SYSREF/SYNC Clock

VCO/Distribution Clock

SPI Register

SDCLKout1, 3, 5, 7, 9, 11, 13

图8-3. SYNC/SYSREF Clocking Paths

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8.3 Feature Description

8.3.1 Synchronizing PLL R Dividers

In some cases, it is necessary to synchronize PLL R dividers to enable determinism of clocks outputs to inputs.

This typically is required when the fraction Total PLL N divide / Total PLL R divide does not reduce to N / 1.

8.3.1.1 PLL1 R Divider Synchronization

It is possible to use the CLKIN0 or SYNC pin to synchronize the PLL1 R divider. To do this, the device is set up

for synchronization, the PLL1 R divider is armed for synchronization, and then the rising sync edge arrives from

either the SYNC pin or CLKIN0. After the PLL1 R divider is armed, PLL1 is unlocked until the synchronization

edge arrives and allows the divider to operate and the PLL to lock. The procedure to synchronize PLL1 R is as

follows:

1. Setup device for synchronizing PLL1 R:

• PLL1R_SYNC_EN = 0x1

• PLL1R_SYNC_SRC = 0x1 (SYNC pin) or 0x2 (CLKIN0)

• CLKin0_DEMUX = 0x2 (PLL1)

• CLKin1_DEMUX = 0x2 (PLL1)

• CLKin0_TYPE = 0x1 (MOS) for DC-coupled or CLKin0_TYPE = 0x0 (Bipolar) for AC-coupled

2. Arm PLL1 R divider for synchronization

• PLL1R_RST = 1, then 0.

• PLL1 is unlocked.

3. Send rising edge on SYNC pin or CLKIN0.

• PLL1 R divider is released from reset and PLL1 relocks.

It is necessary to meet a setup and hold time when CLKIN0 or SYNC pin goes high to ensure deterministic reset

of the PLL1 R divider.

The SYNC_POL bit has no effect on SYNC polarity for PLL1 R synchronization.

8.3.1.2 PLL2 R Divider Synchronization

The SYNC pin must be used to synchronized the PLL2 R divider. When PLL2R_SYNC_EN = 1, as long as the

SYNC pin is held high, the PLL2 R divider is held in reset. When the SYNC pin is returned low, the divider is

allowed to continue dividing. While PLL2R_SYNC_EN = 1 and SYNC pin is high PLL2 is unlocked.

It is necessary to meet a setup and hold time when SYNC pin goes low to ensure deterministic reset of the PLL2

R divider.

The SYNC_POL bit has no effect on SYNC polarity for PLL2 R synchronization.

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8.3.2 SYNC/SYSREF

The SYNC and SYSREF signals share the same SYNC/SYSREF Clock Distribution path. To properly use SYNC

and/or SYSREF for JESD204B/C, it is important to understand the SYNC/SYSREF system. 图 8-2 shows the

detailed diagram of a clock output block with SYNC circuitry included. 图 8-3 shows the interconnects and

highlights some important registers used in controlling the device for SYNC/SYSREF purposes.

To reset or synchronize a divider, the following conditions must be met:

1. SYNC_EN must be set. This ensures proper operation of the SYNC circuitry.

2. SYSREF_MUX and SYNC_MODE must be set to a proper combination to provide a valid SYNC/SYSREF

signal.

• If SYSREF block is being used, the SYSREF_PD bit must be clear.

• If the SYSREF Pulser is being used, the SYSREF_PLSR_PD bit must be clear.

• For each CLKOUTx or CLKOUTy being used for SYSREF, the respective SCLKX_Y_PD bit must be

cleared.

3. DCLKX_Y_DDLY_PD and SYSREF_DDLY_PD bits must be clear to power up the digital delay circuitry used

during SYNC to cause deterministic phase between the device clock dividers and the global SYSREF

divider.

4. The SYNC_DISX bit must be clear to allow SYNC/SYSREF signal to divider circuit. The SYSREF_MUX

register selects the SYNC source which resets the SYSREF/CLKOUTx dividers, provided the corresponding

SYNC_DISX bit is clear.

5. Other bits which impact the operation of SYNC such as SYNC_1SHOT_EN may be set as desired.

6. After these dividers are synchronized, the DCLKX_Y_DDLY_PD and SYSREF_DDLY_PD bits may be set to

save current. Clearing them to power up may disrupt the output clock phase.

表8-2 shows the some possible combinations of SYSREF_MUX and SYNC_MODE.

表8-2. Some Possible SYNC Configurations

NAME

SYNC_MODE

SYSREF_MUX

OTHER

DESCRIPTION

No SYNC will occur.

SYNC Disabled

0

CLKin0_DEMUX ≠0

Basic SYNC functionality, SYNC pin polarity is

selected by SYNC_POL.

To achieve SYNC through SPI, toggle the SYNC_POL

bit.

Pin or SPI SYNC

1

0

CLKin0_DEMUX ≠0

Differential input

SYNC

X

2

0 or 1

2

CLKin0_DEMUX = 0

Differential CLKin0 now operates as SYNC input.

JESD204B/C

Pulser on pin

transition.

Produce SYSREF_PULSE_CNT programmed

number of pulses on pin transition. SYNC_POL can

be used to cause SYNC through SPI.

SYSREF_PULSE_CNT

sets pulse count

JESD204B/C

Pulser on SPI

programming.

SYSREF_PULSE_CNT

sets pulse count

Programming SYSREF_PULSE_CNT register starts

sending the number of pulses.

3

1

2

1

SYSREF operational,

SYSREF Divider as

required for training frame for non-JESD converters such as LM97600.

size.

Allows precise SYNC for n-bit frame training patterns

Re-clocked SYNC

When SYNC pin is asserted, continuous SYSREF

External SYSREF

request

SYSREF_REQ_EN = 1

Pulser powered up

pulses occur. Turning on and off of the pulses is

synchronized to prevent runt pulses from occurring on

SYSREF.

0

2

3

SYSREF_PD = 0

SYSREF_DDLY_PD = 0

Continuous

SYSREF

X

Continuous SYSREF signal.

SYSREF_PLSR_PD = 1

(1)

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NAME

表8-2. Some Possible SYNC Configurations (continued)

SYNC_MODE

SYSREF_MUX

OTHER

DESCRIPTION

Re-clocked

SYSREF

distribution

SYSREF_DDLY_PD = 1

SYSREF_PLSR_PD = 1

SYSREF_PD = 1.

Fan-out of CLKin0 reclocked to the clock distribution

path.

0

(1) SCLKX_Y_PD = 0 as required per SYSREF output. This applies to any SYNC or SYSREF output on SCLKX_Y when SCLKX_Y_MUX

= 1 (SYSREF output)

备注

The SYNC/SYSREF signal is reclocked by the Clock Distribution Path, therefore an active clock must

be present on the Clock Distribution Path (either from VCO or FIN0/FIN1 pins in distribution mode) for

SYNC to take effect.

备注

Any device clock divider or the SYSREF divider which does not have the SYNC_DISX bit or

SYNC_DISSYSREF bit set will reset while SYNC/SYSREF Distribution Path is high. This is especially

important for the SYSREF divider which has the ability to reset itself if the SYNC_DISSYSREF = 0! Be

sure to set SYNC_DISX/SYNC_DISSYSREF bits as required.

备注

While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC procedure requires to first program

Divide-by-4 and then back to Divide-by-2 or Divide-by-3 before doing SYNC.

8.3.3 JEDEC JESD204B/C

8.3.3.1 How to Enable SYSREF

表8-3 summarizes the bits required to make the SYSREF functionality operational.

表8-3. SYSREF Bits

REGISTER

0x140

FIELD

VALUE

DESCRIPTION

SYSREF_PD

0

Must be clear, power-up SYSREF circuitry including the SYSREF divider.

SYSREF_DDLY

_PD

Must be clear to power-up digital delay circuitry. Must be powered up during initial SYNC

to ensure deterministic timing to other clock dividers.

0x140

0x143

0

1

SYNC_EN

Must be set, enable SYNC.

Do not hold local SYSREF DDLY block in reset except at start.

Anytime SYSREF_PD = 1, because of user programming or device RESET, it is

necessary to set SYSREF_CLR for 15 VCO clock cycles to clear the local SYSREF digital

delay. After the delay is cleared, SYSREF_CLR must be cleared to allow SYSREF to

operate.

0x143

SYSREF_CLR

1 →0

Enabling JESD204B/C operation involves synchronizing all the clock dividers with the SYSREF divider, then

configuring the actual SYSREF functionality.

8.3.3.1.1 Setup of SYSREF Example

The following procedure is a programming example for a system which is to operate with a 3000-MHz VCO

frequency. Use CLKOUT0 and CLKOUT2 to drive converters at 1500 MHz. Use CLKOUT4 to drive an FPGA at

150 MHz. Synchronize the converters and FPGA using a two SYSREF pulses at 10 MHz.

1. Program registers 0x000 to 0x555 (refer to Recommended Programming Sequence). Key to prepare for

SYSREF operations:

a. Prepare for manual SYNC: SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0

b. Setup output dividers as per example: DCLK0_1_DIV and DCLK2_3_DIV = 2 for frequency of 1500

MHz. DCLK4_5_DIV = 20 for frequency of 150 MHz.

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c. Setup output dividers as per example: SYSREF_DIV = 300 for 10-MHz SYSREF.

d. Setup SYSREF: SYSREF_PD = 0, SYSREF_DDLY_PD = 0, DCLK0_1_DDLY_PD = 0,

DCLK2_3_DDLY_PD = 0, DCLK4_5_DDLY_PD = 0, SYNC_EN = 1, SYSREF_PLSR_PD = 0,

SYSREF_PULSE_CNT = 1 (2 pulses). SCLK0_1_PD = 0, SCLK2_3_PD = 0, SCLK4_5_PD = 0.

e. Clear Local SYSREF DDLY: SYSREF_CLR = 1.

2. Establish deterministic phase relationships between SYSREF and Device Clock for JESD204B/C:

a. Set device clock and SYSREF divider digital delays: DCLK0_1_DDLY, DCLK2_3_DDLY,

DCLK4_5_DDLY, and SYSREF_DDLY.

b. Set device clock digital delay half steps: DCLK0_1_HS, DCLK2_3_HS, DCLK4_5_HS.

c. Set SYSREF clock digital delay as required to achieve known phase relationships: SCLK0_1_DDLY,

SCLK2_3_DDLY, and SCLK4_5_DDLY. If half step adjustments are required SCLK0_1_HS,

SCLK2_3_HS, and SCLK4_5_HS.

d. To allow SYNC to affect dividers: SYNC_DIS0 = 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0,

SYNC_DISSYSREF = 0.

e. Perform SYNC by toggling SYNC_POL = 1 then SYNC_POL = 0.

3. Now that dividers are synchronized, disable SYNC from resetting these dividers. It is not desired for

SYSREF to reset it's own divider or the dividers of the output clocks.

a. Prevent SYNC (SYSREF) from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1,

SYNC_DISSYSREF = 1.

4. Release reset of local SYSREF digital delay.

a. SYSREF_CLR = 0. Note this bit needs to be set for only 15 clock distribution path clocks after

SYSREF_PD = 0.

5. Set SYSREF operation.

a. Allow pin SYNC event to start pulser: SYNC_MODE = 2.

b. Select pulser as SYSREF signal: SYSREF_MUX = 2.

6. Complete! Assert the SYNC pin or toggle the SYNC_POL to send a series of 2 SYSREF pulses.

8.3.3.1.2 SYSREF_CLR

The local digital delay of the SCLKX_Y_DDLY is implemented as a shift buffer. To ensure no unwanted pulses

occur at this SYSREF output at start-up, when using SYSREF, requires clearing the buffers by setting

SYSREF_CLR = 1 for 15 VCO clock cycles. After a reset, this bit is set, so it must be cleared before SYSREF

output is used.

If the SYSREF pulser is used. It is also required to set SYSREF_CLR = 1 for 15 VCO clock cycles after the

SYSREF pulser is powered up.

8.3.3.2 SYSREF Modes

8.3.3.2.1 SYSREF Pulser

This mode allows for the output of 1, 2, 4, or 8 SYSREF pulses for every SYNC pin event or SPI programming.

This implements the gapped periodic functionality of the JEDEC JESD204B/C specification.

When in SYSREF Pulser mode, the user can adjust the SYSREF_PULSE_CNT field in register 0x13E to

program the pulser to send out a set number of pulses.

8.3.3.2.2 Continuous SYSREF

This mode allows for continuous output of the SYSREF clock.

备注

TI does not recommend continuous operation of the SYSREF clock due to crosstalk from the SYSREF

clock to device clock. JESD204B/C is designed to operate with a single burst of pulses to initialize the

system at start-up, after which it is theoretically not required to send another SYSREF because the

system will continue to operate with deterministic phases.

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8.3.3.2.3 SYSREF Request

This mode allows an external source to synchronously turn on or off a continuous stream of SYSREF pulses

using the SYNC/SYSREF_REQ pin.

Setup the mode by programming SYSREF_REQ_EN = 1 and SYSREF_MUX = 2 (Pulser). The pulser does not

need to be powered for this mode of operation.

When the SYSREF_REQ pin is asserted, the SYSREF_MUX is synchronously set to continuous mode,

providing continuous pulses at the SYSREF frequency until the SYSREF_REQ pin is unasserted. When the

SYSREF_REQ pin is unasserted, the final SYSREF pulse completes sending synchronously.

8.3.4 Digital Delay

Digital (coarse) delay allows a group of outputs to be delayed by 8 to 1023 clock distribution path cycles. The

delay step can be as small as half the period of the clock distribution path cycle by using the DCLKX_Y_HS bit.

There are two different ways to use the digital delay:

1. Fixed digital delay

2. Dynamic digital delay

In both delay modes, the regular clock divider is substituted with an alternative divide value.

8.3.4.1 Fixed Digital Delay

Fixed digital delay value takes effect on the clock outputs after a SYNC event. As such, the outputs will be LOW

for a while during the SYNC event. Applications that cannot accept clock breakup when adjusting digital delay

during application run time should use dynamic digital delay to adjust phase.

8.3.4.1.1 Fixed Digital Delay Example

Assuming the device already has the following initial configurations and the application delays CLKOUT2 by one

VCO cycle compared to CLKOUT0:

• VCO frequency = 2949.12 MHz

• CLKOUT0 = 368.64 MHz (DCLK0_1_DIV = 8, CLKOUT0_SRC_MUX = 0 (Device Clock))

• CLKOUT2 = 368.64 MHz (DCLK2_3_DIV = 8, CLKOUT2_SRC_MUX = 0 (Device Clock))

The following steps should be followed:

1. Set DCLK0_1_DDLY = 8 and DCLK2_3_DDLY = 9. Static delay for each clock.

2. Set DCLK0_1_DDLY_PD = 0 and DCLK2_3_DDLY_PD = 0. Power up the digital delay circuit.

3. Set SYNC_DIS0 = 0 and SYNC_DIS2 = 0. Allow the outputs to be synchronized.

4. Perform SYNC by asserting, then unasserting SYNC. The can be done by either using the SYNC_POL bit or

the SYNC pin.

5. Now that the SYNC is complete, you can power down DCLK0_1_DDLY_PD = 1 and/or DCLK2_3_DDLY_PD

= 1 to save power.

6. Set SYNC_DIS0 = 1 and SYNC_DIS2 = 1. Prevent the output from being synchronized, as this is very

important for steady-state operation when using JESD204B/C.

No CLKout during SYNC

CLKout0

368.64 MHz

CLKout2

368.64 MHz

SYNC event

1 VCO cycle delay

图8-4. Fixed Digital Delay Example

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8.3.4.2 Dynamic Digital Delay

Dynamic digital delay allows the phase of clocks to be changed with respect to each other with little impact to the

clock signal.

For the device clock dividers this is accomplished by substituting the regular clock divider with an alternate divide

value of one larger than the regular divider for one cycle. This substitution will occur a number of times equal to

the value programmed into the DDLYd_STEP_CNT field for all outputs with DDLYdX_EN = 1.

For the SYSREF divider, an alternate divide value is substituted for the regular divide value. This substitution will

occur a number of times equal to the value programmed into the DDLYd_STEP_CNT if DDLYd_SYSREF_EN =

1. To achieve one cycle delay as is done for the device clock dividers, set the SYSREF_DDLY value to one

greater than SYSREF_DIV+SYSREF_DIV/2. For example, for a SYSREF divider of 100, to achieve 1 cycle

delay, SYSREF_DDLY = 100 + 50 + 1 = 151.

While using the Dynamic Digital Delay feature, CLKin_OVERRIDE must be set to 0.

• By programming a larger alternate divider (delay) value, the phase of the adjusted outputs are delayed with

respect to the other clocks.

• By programming a smaller alternate divider (delay) value, the phase of the adjusted outputs are advanced

with respect to the other clocks.

8.3.4.3 Single and Multiple Dynamic Digital Delay Example

In this example, two separate adjustments are made to the device clocks. In the first adjustment, a single delay

of one VCO cycle occurs between CLKOUT2 and CLKOUT0. In the second adjustment, two delays of one VCO

cycle occur between CLKOUT2 and CLKOUT0. At this point in the example, CLKOUT2 is delayed three VCO

cycles behind CLKOUT0.

Assuming the device already has the following initial configurations:

• VCO frequency: 2949.12 MHz

• CLKOUT0 = 368.64 MHz, DCLK0_1_DIV = 8

• CLKOUT2 = 368.64 MHz, DCLK2_3_DIV = 8

The following steps illustrate the example above:

1. Set DCLK2_3_DDLY = 4. First part of delay for CLKOUT2.

2. Set DCLK2_3_DDLY_PD = 0. Enable the digital delay for CLKOUT2.

3. Set DDLYd0_EN = 0 and DDLYd2_EN = 1. Enable dynamic digital delay for CLKOUT2 but not CLKOUT0.

4. Set DDLYd_STEP_CNT = 1. This begins the first adjustment.

Before step 4, CLKOUT2 clock edge is aligned with CLKOUT0.

After step 4, CLKOUT2 counts nine clock distribution path cycles to the next rising edge, one greater than the

divider value, effectively delaying CLKOUT2 by one VCO cycle with respect to CLKOUT0. This is the first

adjustment.

5. Set DDLYd_STEP_CNT = 2. This begins the second adjustment.

Before step 5, CLKOUT2 clock edge was delayed one clock distribution path cycle from DCLKOUT0.

After step 5, CLKOUT2 counts nine clock distribution path cycles twice, each time one greater than the divide

value, effectively delaying CLKOUT2 by two clock distribution path cycles with respect to CLKOUT0. This is the

second adjustment.

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VCO

2949.12 MHz

CLKout0

368.64 MHz

CLKout2

368.64 MHz

First

Adjustment

DCLK2_3_DIV + 1

CLKout2

368.64 MHz

Second

Adjustment

DCLK2_3_DIV + 1

图8-5. Single and Multiple Adjustment Dynamic Digital Delay Example

8.3.5 SYSREF to Device Clock Alignment

To ensure proper JESD204B/C operation, the timing relationship between the SYSREF and the Device clock

must be adjusted for optimum setup and hold time as shown in 图 8-6. The global SYSREF digital delay

(SYSREF_DDLY), local SYSREF digital delay (SCLKX_Y_DDLY), local SYSREF half step (SCLKX_Y_HS), and

local SYSREF analog delay (SCLKX_Y_ADLY, SCLK2_3_ADLY_EN) can be adjusted to provide the required

setup and hold time between SYSREF and Device Clock. It is also possible to adjust the device clock digital

delay (DCLKX_Y_DDLY) and half step (DCLK0_1_HS, DCLK0_1_DCC) to adjust phase with respect to

SYSREF.

图8-6. SYSREF to Device Clock Timing alignment

Depending on the DCLKout_X path settings, local SCLK_X_Y_DDLY might need adjustment factor. Following

equation can be used to calculate the required Digital Delay Values to align SYSREF to the corresponding

DCLKOUT

SYSREF_DDLY = DCLKX_Y_DDLY –1 + DCLK_DIV_ADJUST + DCLK_HS_ADJUST –SCLK_X_Y_DDLY

(1)

SYSREF_DDLY > 7; SCLK_X_Y_DDLY > 1.

表8-4. DCLK_DIV_ADJUST

DCLKX_Y_DIV

DCLK_DIV_ADJUST

>6

6

0

–1

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表8-4. DCLK_DIV_ADJUST (continued)

DCLKX_Y_DIV

DCLK_DIV_ADJUST

5

3

4

0

3 ⁽¹⁾

2 ⁽¹⁾

–2

(1) Refer to the SYNC requirement SYNC/SYSREF

表8-5. DCLK_HS_ADJUST

DCLK & HS

DCLK_HS_ADJUST

0

1

0

1

For example: DCLKX_Y_DIV = 32, DCLKX_Y_DDLY = 10, DCC&HS = 1;

SYSREF_DDLY=10 –1 + 0 + 1 –2 = 8

8.3.6 Input Clock Switching

Manual, pin select, and automatic are three different kinds clock input switching modes can be selected

according to the combination of bits as illustrated in 图8-7.

Input Clock Select

It is required for CLKin1

to be selected for

distribution mode.

Recommend using

CLKin_SEL_MANUAL

CLKin_SEL_

AUTO_EN

Yes

No

Active CLKin is set Auto

Mode State Machine

CLKin_SEL_

PIN_EN

Yes

No

Active CLKin is set by

CLKin_SEL_MANUAL

CLKin_SEL_

PIN_POL

Yes

No

Active CLKin is set by

CLKin_SEL# and Status_LD1

pins, inverted.

Active CLKin is set by

CLKin_SEL# and Status_LD1

pins.

图8-7. CLKINx Input Reference

The following sections provide information about how the active input clock is selected and what causes a

switching event in the various clock input selection modes.

8.3.6.1 Input Clock Switching - Manual Mode

When CLKin_SEL_AUTO_EN = 0 and CLKin_SEL_PIN_EN = 0, the active CLKin is selected by

CLKin_SEL_MANUAL. Programming a value of 0, 1, or 2 to CLKin_SEL_MANUAL causes CLKin0, CLKin1, or

CLKin2, respectively, to be the selected active input clock. In this mode, the EN_CLKinX bits are overridden

such that the CLKinX buffer operates even if CLKinX is disabled with EN_CLKinX = 0.

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If holdover is entered in this mode by setting CLKin_SEL_MANUAL = 3, then the device will re-lock to the

selected CLKin upon holdover exit.

8.3.6.2 Input Clock Switching - Pin Select Mode

When CLKin_SEL_AUTO_EN = 0 and CLKin_SEL_PIN_EN = 1, the active CLKin is selected by the

CLKin_SEL# and Status_LD1 pins.

Configuring Pin Select Mode

The CLKin_SEL0_TYPE must be programmed to an input value for the CLKin_SEL0 pin to function as an input

for pin select mode.

The CLKin_SEL1_TYPE must be programmed to an input value for the CLKin_SEL1 pin to function as an input

for pin select mode.

The polarity of the clock input select pins can be inverted with the CLKin_SEL_PIN_POL bit.

The pin select mode overrides the EN_CLKinX bits such that the CLKinX buffer operates even if CLKinX is

disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers enabled (EN_CLKinX =

1) that could be switched to.

8.3.6.3 Input Clock Switching - Automatic Mode

When CLKin_SEL_AUTO_EN = 1, LOS_EN = 1, and HOLDOVER_EXIT_MODE = 0 (Exit based on LOS), the

active clock is selected in priority order with CLKin0 being the highest priority, CLKin1 second, and CLKin2 third.

For a clock input to be eligible to be switched to, it must be enabled using EN_CLKinX. The LOS_TIMEOUT

should also be set to a frequency below the input frequency.

To ensure LOS is valid for AC-coupled inputs, the MOS mode must be set for the CLKin and no termination is

allowed to be between the pins unless the pins are DC-blocked. For example, no 100-Ω termination across

CLKin0 and CLKin0* pins on IC side of AC-coupling capacitors.

8.3.7 Digital Lock Detect (DLD)

Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference

path (R) and the feedback path (N) of the PLL. When the time error, which is phase error, between the two

signals is less than a specified window size (ε) a lock detect count increments. When the lock detect count

reaches a user specified value, PLL1_DLD_CNT or PLL2_DLD_CNT, lock detect is asserted true. Once digital

lock detect is true, a single phase comparison outside the specified window will cause digital lock detect to be

asserted false. This is illustrated in 图8-8.

NO

PLLX

Lock Detected = False

Lock Count = 0

YES

Increment

PLLX Lock Count

PLLX

Lock Detected = True

PLLX Lock Count =

PLLX_DLD_CNT

START

Phase Error < g

YES

NO

图8-8. Digital Lock Detect Flowchart

This incremental lock detect count feature functions as a digital filter to ensure that lock detect is not asserted for

only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial

phase lock.

See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to

achieve a specified frequency accuracy in ppm with lock detect.

The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be

programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.

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8.3.7.1 Calculating Digital Lock Detect Frequency Accuracy

See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to

achieve a specified frequency accuracy in ppm with lock detect.

The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Exiting

Holdover for more information.

8.3.8 Holdover

Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock

reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed

tuning voltage is set on CPout1 to operate PLL1 in open loop.

8.3.8.1 Enable Holdover

Program HOLDOVER_EN = 1 to enable holdover mode.

Holdover mode can be configured to set the CPout1 voltage upon holdover entry to a fixed user defined voltage

(EN_MAN_DAC = 1) or a tracked voltage (EN_MAN_DAC = 0).

8.3.8.1.1 Fixed (Manual) CPout1 Holdover Mode

By programming MAN_DAC_EN = 1, then the MAN_DAC value will be set on the CPout1 pin during holdover.

The user can optionally enable CPout1 voltage tracking (TRACK_EN = 1), read back the tracked DAC value,

then re-program MAN_DAC value to a user desired value based on information from previous DAC read backs.

This allows the most user control over the holdover CPout1 voltage, but also requires more user intervention.

8.3.8.1.2 Tracked CPout1 Holdover Mode

By programming MAN_DAC_EN = 0 and TRACK_EN = 1, the tracked voltage of CPout1 is set on the CPout1

pin during holdover. When the DAC has acquired the current CPout1 voltage, the DAC_Locked signal is set,

which may be observed on Status_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or PLL2_LD_MUX,

respectively.

Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector

frequency divided by (DAC_CLK_MULT × DAC_CLK_CNTR).

The DAC update rate should be programmed for ≤100 kHz to ensure DAC holdover accuracy.

The ability to program slow DAC update rates, for example one DAC update per 4.08 seconds when using 1024-

kHz PLL1 phase detector frequency with DAC_CLK_MULT = 16,384 and DAC_CLK_CNTR = 255, allows the

device to look-back and set CPout1 at a previous good CPout1 tuning voltage values before the event which

caused holdover to occur.

The current voltage of DAC value can be read back using RB_DAC_VALUE, see the RB_DAC_VALUE section.

8.3.8.2 During Holdover

PLL1 is run in open-loop mode.

• PLL1 charge pump is set to TRI-STATE.

• PLL1 DLD is unasserted.

• The HOLDOVER status is asserted

• During holdover, if PLL2 was locked prior to entry of holdover mode, PLL2 DLD continues to be asserted.

• CPout1 voltage is set to:

– a voltage set in the MAN_DAC register (MAN_DAC_EN = 1).

– a voltage determined to be the last valid CPout1 voltage (MAN_DAC_EN = 0).

• PLL1 attempts to lock with the active clock input.

The HOLDOVER status signal can be monitored on the Status_LD1 or Status_LD2 pin by programming the

PLL1_DLD_MUX or PLL2_DLD_MUX register to Holdover Status.

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8.3.8.3 Exiting Holdover

Holdover mode can be exited in one of two ways.

• Manually, by programming the device from the host.

• Automatically, when the LOS signal unasserts for a clock that provides a valid input to PLL1.

8.3.8.4 Holdover Frequency Accuracy and DAC Performance

When in holdover mode, PLL1 runs in open loop and the DAC sets the CPout1 voltage. If fixed CPout1 mode is

used, then the output of the DAC is dependent upon the MAN_DAC register. If tracked CPout1 mode is used,

then the output of the DAC is approximately the same voltage at the CPout1 pin before holdover mode was

entered. When using Tracked mode and MAN_DAC_EN = 1, the DAC value during holdover is loaded with the

programmed value in MAN_DAC and not the tracked value.

When in Tracked CPout1 mode, the DAC has a worst-case tracking error of ±2 LSBs once PLL1 tuning voltage

is acquired. The step size is approximately 3.2 mV, therefore the VCXO frequency error during holdover mode

caused by the DAC tracking accuracy is ±6.4 mV × Kv, where Kv is the tuning sensitivity of the VCXO in use.

Therefore, the accuracy of the system when in holdover mode in ppm is:

6.4 mV × Kv × 1e6

Holdover accuracy (ppm) =

VCXO Frequency

(2)

As an example, consider a system with a 19.2-MHz clock input, a 153.6-MHz VCXO with a Kv of 17 kHz/V. The

accuracy of the system in holdover in ppm is:

±0.71 ppm = ±6.4 mV × 17 kHz/V × 1e6 / 153.6 MHz

(3)

It is important to account for this frequency error when determining the allowable frequency error window to

cause holdover mode to exit.

8.3.9 PLL2 Loop Filter

PLL2 has an integrated loop filter of C1i = 60 pF, R3 = 2400 Ω, C3 = 50 pF, R4 = 200 Ω and C4 = 10 pF as

shown in 图 8-9. Loop filter components C1, C2, and R2 can be solved using TI software. See Device Support

for more information.

图8-9. PLL2 On-Chip Loop Filter

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8.4 Device Functional Modes

This device can be configured for many different use cases. The following simplified block diagrams help show

the user the different use cases of the device.

8.4.1 DUAL PLL

8.4.1.1 Dual Loop

图 8-10 shows the typical use case of dual loop mode. In dual loop mode, the reference to PLL1 is from CLKin0,

CLKin1, or CLKin2. An external VCXO is used to provide feedback for the first PLL and a reference to the

second PLL. This first PLL cleans the jitter with the VCXO by using a narrow loop bandwidth. The VCXO may be

buffered through the OSCout port. The VCXO is used as the reference to PLL2 and may be doubled using the

frequency doubler. The internal VCO drives up to seven divide/delay blocks which drive up to 14 clock outputs.

Hitless switching and holdover functionality are optionally available when the input reference clock is lost.

Holdover works by forcing a DAC voltage to the tuning voltage of the VCXO.

It is also possible to use an external VCO in place of PLL2's internal VCO. In this case one less CLKin is

available as a reference as CLKin1 is used for external input.

External

Loop Filter

OSCOUT_P

OSCOUT_N

External

VCXO

CLKINx_P

CLKINx_N

PLL1

Phase

Detector/

Charge

Pump

R

CPOUT2

7 Blocks

External

Loop Filter

Up to 3

inputs

Device Clock

Divider

Digital Delay

R

N

PLL2

CLKOUTx_P

CLKOUTx_N

Phase

Detector/

Charge

Pump

Divider

N

Divider

Up to 14 Clock or

SYSREF Outputs

PLL1

7 Blocks

SYSREF

CLKOUTy_P

CLKOUTy_N

SYSREF

Global SYSREF

Divider and Delay

Digital Delay

Analog Delay

图8-10. Simplified Functional Block Diagram for Dual Loop Mode

8.4.1.2 Dual Loop With Cascaded 0-Delay

图 8-11 shows the use case of cascaded 0-delay dual loop mode. This configuration differs from dual loop mode

图8-10 in that the feedback for PLL2 is driven by a clock output instead of the VCO output directly.

It is also possible to use an external VCO in place of the internal VCO of the PLL2, but one less CLKin is

available as a reference and the external 0-delay feedback is not available.

External

Loop Filter

OSCOUT_P

OSCOUT_N

External

VCXO

CLKINx_P

CLKINx_N

PLL1

Phase

Detector/

Charge

Pump

R

CPOUT2

7 Blocks

External

Loop Filter

Up to 3

inputs

Device Clock

Divider

Digital Delay

R

N

PLL2

CLKOUTx_P

CLKOUTx_N

Phase

Detector/

Charge

Pump

Divider

N

Divider

Up to 14 Clock or

SYSREF Outputs

PLL1

7 Blocks

SYSREF

CLKOUTy_P

CLKOUTy_N

SYSREF

Global SYSREF

Divider and Delay

Digital Delay

Analog Delay

Internal or external loopback, user programmable

图8-11. Simplified Functional Block Diagram for Cascaded 0-Delay Dual Loop Mode

8.4.1.3 Dual Loop With Nested 0-Delay

图 8-12 shows the use case of nested 0-delay dual loop mode. This configuration is similar to the dual PLL in 图

8-10 except that the feedback to the first PLL is driven by a clock output. The PLL2 reference OSCIN is not

deterministic to the CLKIN or feedback clock.

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External

Loop Filter

OSCOUT_P

OSCOUT_N

External

VCXO

CLKINx_P

CLKINx_N

PLL1

Phase

Detector/

Charge

Pump

R

CPOUT2

7 Blocks

External

Loop Filter

Up to 3

inputs

Device Clock

Divider

Digital Delay

R

N

PLL2

CLKOUTx_P

CLKOUTx_N

Phase

Detector/

Charge

Pump

Divider

N

Divider

Up to 14 Clock or

SYSREF Outputs

PLL1

7 Blocks

SYSREF

CLKOUTy_P

CLKOUTy_N

SYSREF

Global SYSREF

Divider and Delay

Digital Delay

Analog Delay

Internal or external loopback, user programmable

图8-12. Simplified Functional Block Diagram for Nested 0-Delay Dual Loop Mode

8.4.2 Single PLL

8.4.2.1 PLL2 Single Loop

图 8-13 shows the use case of PLL2 single loop mode. When used with a high-frequency clean reference

performance as good as dual loop mode may be achieved. Traditionally the OSCIN is used as a reference to

PLL2, but it is also possible to use CLKINx as a reference to PLL2.

External

Loop Filter

OSCOUT_P

OSCOUT_N

CPOUT2

7 Blocks

OSCIN_P

OSCIN_N

Device Clock

Divider

R

N

PLL2

CLKOUTx_P

CLKOUTx_N

Phase

Detector/

Charge

Pump

Divider

Up to 4

Inputs

Digital Delay

CLKINx_P

CLKINx_N

Up to 14 Clock or

SYSREF Outputs

7 Blocks

SYSREF

CLKOUTy_P

CLKOUTy_N

SYSREF

Global SYSREF

Divider and Delay

Digital Delay

Analog Delay

图8-13. Simplified Functional Block Diagram for Single Loop Mode

8.4.2.2 PLL2 With External VCO

You can use the FIN0/FIN1 input pins to add an external VCO. The input may be single-ended or differential. At

high frequency, the input impedance to FIN0/FIN1 is low. A resistive pad is recommended for matching.

External Loop Filter

OSCOUT_P

FIN0_P

FIN0_N

7 Blocks

OSCOUT_N

CPOUT2

OSCIN_P

OSCIN_N

Device Clock

Divider

Digital Delay

R

N

PLL2

Phase

Detector/

Charge

Pump

CLKOUTx_P

CLKOUTx_N

Divider

Up to3

Inputs

PLL2

Up to 14 Clock or

SYSREF Outputs

CLKINx_P

CLKINx_N

7 Blocks

SYSREF

CLKOUTy_P

CLKOUTy_N

SYSREF

Global SYSREF

Divider and Delay

Digital Delay

Analog Delay

图8-14. Simplified Functional Block Diagram for Single Loop Mode With External VCO

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8.4.3 Distribution Mode

图8-15 shows the use case of distribution mode. As in all the other use cases, OSCIN to OSCOUT can be used

as a buffer to OSCIN or from clock distribution path through CLKOUT6, CLKOUT8, or the SYSREF divider.

At high frequency, the input impedance to FIN0/FIN1 is low and a resistive pad is recommended for matching.

OSCIN_P

OSCIN_N

OSCOUT_P

OSCOUT_N

CLKOUT6/8

FIN0_P

7 Blocks

FIN0_N

Device Clock

Divider

Digital Delay

Analog Delay

÷2

CLKOUTx_P

CLKOUTx_N

CLKIN1_P/FIN1_P

CLKIN1_N/FIN1_N

Up to 14 Clock or

SYSREF Outputs

7 Blocks

CLKOUTx_P

CLKOUTx_N

SYSREF

Global SYSREF

Divider and Delay

SYSREF

CLKIN1_P/FIN1_P

CLKIN1_N/FIN1_N

Digital Delay

Analog Delay

图8-15. Simplified Functional Block Diagram for Distribution Mode

8.5 Programming

The device is programmed using 24-bit registers. Each register consists of a 1-bit command field (R/W), a 15-bit

address field (A14 to A0) and a 8-bit data field (D7 to D0). The contents of each register is clocked in MSB first

(R/W), and the LSB (D0) last. During programming, the CS* signal is held low. The serial data is clocked in on

the rising edge of the SCK signal. After the LSB is clocked in, the CS* signal goes high to latch the contents into

the shift register. TI recommends to program registers in numeric order (for example, 0x000 to 0x555 with

exceptions noted in the Recommended Programming Sequence). Each register consists of one or more fields

which control the device functionality. See the Electrical Characteristics table and 图6-1 for timing details.

8.5.1 Recommended Programming Sequence

Registers are generally programmed in numeric order with 0x000 being the first and 0x555 being the last register

programmed. The recommended programming sequence from POR involves:

1. Program register 0x000 with RESET = 1.

2. Program defined registers from 0x000 to 0x165.

3. If PLL2 is used, program 0x173 with PLL2_PD and PLL2_PRE_PD clear to allow PLL2 to lock after PLL2_N

is programmed.

4. Continue programming defined registers from 0x166 to 0x555.

备注

When using the internal VCO, PLL2_N registers 0x166, 0x167, and 0x168 must be programmed after

other PLL2 dividers are programed to ensure proper VCO frequency calibration. This is also true for

PLL2_N_CAL registers 0x163, 0x164, 0x165 when PLL2_NCLK_MUX = 1. So if any divider such as

PLL2_R is altered to change the VCO frequency, the VCO calibration must be run again by

programming PLL2_N.

Power up PLL2 by setting PLL2_PRE_PD = 0 and PLL2_PD = 0 in register 0x173 before

programming PLL2_N.

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8.6 Register Maps

8.6.1 Register Map for Device Programming

表 8-6 provides the register map for device programming. Any register can be read from the same data address

it is written to.

表8-6. Register Map

ADDRESS

DATA[7:0]

[14:0]

23:8

7

6

5

4

3

2

1

0

SPI_3WIRE

_DIS

0x000

RESET

0

POWER

DOWN

0x002

0

0x003

0x004

0x005

0x006

0x00C

0x00D

0x100

0x101

ID_DEVICE_TYPE

ID_PROD[7:0]

ID_PROD[15:8]

ID_MASKREV

ID_VNDR[15:8]

ID_VNDR[7:0]

DCLK0_1_DIV[7:0]

DCLK0_1_DDLY[7:0]

CLKout0_1_OD

L

DCLK0_1_DDLY

_PD

0x102

0x103

0x104

0x105

CLKout0_1_PD

CLKout0_1_IDL

DCLK0_1_DDLY[9:8]

DCLK0_1_BYP DCLK0_1_DCC DCLK0_1_POL

SCLK0_1_DIS_MODE SCLK0_1_POL

SCLK0_1_ADLY

SCLK0_1_DDLY

DCLK0_1_DIV[9:8]

CLKout0_SRC_

MUX

0

1

0

DCLK0_1_PD

SCLK0_1_PD

DCLK0_1_HS

SCLK0_1_HS

CLKout1_SRC_

MUX

SCLK0_1_ADLY

_EN

0

0x106

0x107

0x108

0x109

0

CLKout1_FMT

CLKout0_FMT

DCLK2_3_DIV[7:0]

DCLK2_3_DDLY[7:0]

DCLK2_3_DDLY

CLKout2_3_OD

L

0x10A

0x10B

0x10C

0x10D

CLKout2_3_PD

CLKout2_3_IDL

DCLK2_3_DDLY[9:8]

DCLK2_3_DIV[9:8]

_PD

CLKout2_SRC_

MUX

0

1

0

DCLK2_3_PD

DCLK2_3_BYP DCLK2_3_DCC DCLK2_3_POL

DCLK2_3_HS

SCLK2_3_HS

CLKout3_SRC_

MUX

SCLK2_3_PD

SCLK2_3_DIS_MODE

SCLK2_3_ADLY

SCLK2_3_DDLY

SCLK2_3_POL

SCLK2_3_ADLY

_EN

0

0x10E

0x10F

0x110

0x111

0

CLKout3_FMT

CLKout2_FMT

DCLK4_5_DIV[7:0]

DCLK4_5_DDLY[7:0]

DCLK4_5_DDLY

CLKout4_5_OD

L

0x112

0x113

0x114

0x115

CLKout4_5_PD

CLKout4_5_IDL

DCLK4_5_DDLY[9:8]

DCLK4_5_DIV[9:8]

_PD

CLKout4_SRC_

MUX

0

1

0

DCLK4_5_PD

DCLK4_5_BYP DCLK4_5_DCC DCLK4_5_POL

DCLK4_5_HS

SCLK4_5_HS

CLKout5_SRC_

MUX

SCLK4_5_PD

SCLK4_5_DIS_MODE

SCLK4_5_ADLY

SCLK4_5_POL

SCLK4_5_ADLY

_EN

0

0x116

0x117

0x118

0

SCLK4_5_DDLY

CLKout4_FMT

CLKout5_FMT

DCLK6_7_DIV[7:0]

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表8-6. Register Map (continued)

ADDRESS

[14:0]

DATA[7:0]

23:8

7

6

5

4

3

2

1

0

0x119

DCLK6_7_DDLY[7:0]

CLKout6_7_OD

L

DCLK6_7_DDLY

_PD

0x11A

0x11B

0x11C

0x11D

CLKout6_7_PD

CLKout6_7_IDL

DCLK6_7_DDLY[9:8]

DCLK6_7_BYP DCLK6_7_DCC DCLK6_7_POL

SCLK6_7_DIS_MODE SCLK6_7_POL

SCLK6_7_ADLY

SCLK6_7_DDLY

DCLK6_7_DIV[9:8]

CLKout6_SRC_

MUX

0

1

0

DCLK6_7_PD

SCLK6_7_PD

DCLK6_7_HS

SCLK6_7_HS

CLKout7_SRC_

MUX

SCLK6_7_ADLY

_EN

0

0x11E

0x11F

0x120

0x121

0

CLKout7_FMT

CLKout6_FMT

DCLK8_9_DIV[7:0]

DCLK8_9_DDLY[7:0]

DCLK8_9_DDLY

CLKout8_9_OD

L

0x122

0x123

0x124

0x125

CLKout8_9_PD

CLKout8_9_IDL

DCLK8_9_DDLY[9:8]

DCLK8_9_DIV[9:8]

_PD

CLKout8_SRC_

MUX

0

1

0

DCLK8_9_PD

DCLK8_9_BYP DCLK8_9_DCC DCLK8_9_POL

DCLK8_9_HS

SCLK8_9_HS

CLKout9_SRC_

MUX

SCLK8_9_PD

SCLK8_9_DIS_MODE

SCLK8_9_ADLY

SCLK8_9_POL

SCLK8_9_ADLY

_EN

0

0x126

0x127

0x128

0x129

0

SCLK8_9_DDLY

CLKout8_FMT

CLKout9_FMT

DCLK10_11_DIV[7:0]

DCLK10_11_DDLY[7:0]

CLKout10_11_P CLKout10_11_O CLKout10_11_I DCLK10_11_DD

0x12A

0x12B

0x12C

0x12D

DCLK10_11_DDLY[9:8]

DCLK10_11_DIV[9:8]

D

DL

LY_PD

CLKout10_SRC

_MUX

DCLK10_11_BY DCLK10_11_DC DCLK10_11_PO

0

1

DCLK10_11_PD

DCLK10_11_HS

SCLK10_11_HS

P

C

L

CLKout11_SRC

_MUX

SCLK10_11_PO

L

0

SCLK10_11_PD

SCLK10_11_DIS_MODE

SCLK10_11_ADLY

SCLK10_11_AD

LY_EN

0

0x12E

0x12F

0x130

0x131

0

SCLK10_11_DDLY

CLKout10_FMT

CLKout11_FMT

DCLK12_13_DIV[7:0]

DCLK12_13_DDLY[7:0]

CLKout12_13_P CLKout12_13_O CLKout12_13_I DCLK12_13_DD

0x132

0x133

0x134

0x135

DCLK12_13_DDLY[9:8]

DCLK12_13_DIV[9:8]

D

DL

LY_PD

CLKout12_SRC

_MUX

DCLK12_13_BY DCLK12_13_DC DCLK12_13_PO

0

1

DCLK12_13_PD

DCLK12_13_HS

SCLK12_13_HS

P

C

L

CLKout13_SRC

_MUX

SCLK12_13_PO

L

0

SCLK12_13_PD

SCLK12_13_DIS_MODE

SCLK12_13_ADLY

SCLK12_13_DDLY

SCLK12_13_AD

LY_EN

0

0x136

0x137

0x138

0

CLKout13_FMT

VCO_MUX

CLKout12_FMT

OSCout_FMT

0

OSCout_MUX

SYSREF_REQ_

EN

0x139

0

SYNC_BYPASS

0

SYSREF_MUX

0x13A

0x13B

0x13C

0x13D

SYSREF_DIV[12:8]

SYSREF_DIV[7:0]

0

SYSREF_DDLY[12:8]

SYSREF_DDLY[7:0]

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表8-6. Register Map (continued)

ADDRESS

[14:0]

DATA[7:0]

23:8

7

6

5

4

3

2

1

0

0x13E

0

SYSREF_PULSE_CNT

PLL2_RCLK_

MUX

PLL2_NCLK_

MUX

0x13F

0x140

0

PLL1_NCLK_MUX

FB_MUX

FB_MUX_EN

SYSREF_GBL_

SYSREF_DDLY SYSREF_PLSR

PLL1_PD

VCO_LDO_PD

DDLYd12_EN

VCO_PD

OSCin_PD

SYSREF_PD

DDLYd4_EN

PD

_PD

DDLYd_

SYSREF_EN

0x141

0x142

0x143

DDLYd10_EN

DDLYd8_EN

DDLYd6_EN

DDLYd2_EN

DDLYd0_EN

DDLYd_STEP_CNT

SYNC_1SHOT_

EN

SYNC_PLL2_

DLD

SYNC_PLL1_

DLD

SYSREF_CLR

SYNC_POL

SYNC_EN

SYNC_MODE

SYNC_DISSYS

REF

0x144

0x145

0x146

SYNC_DIS12

SYNC_DIS10

SYNC_DIS8

SYNC_DIS6

SYNC_DIS4

FIN0_DIV2_EN

CLKin2_TYPE

SYNC_DIS2

SYNC_DIS0

PLL1R_SYNC_

EN

PLL2R_SYNC_

EN

2

PLL1R_SYNC_SRC

FIN0_INPUT_TYPE

CLKin_SEL_PIN CLKin_SEL_PIN

CLKin2_EN

CLKin1_EN

CLKin0_EN

CLKin1_TYPE

CLKin0_TYPE

_EN

_POL

CLKin_SEL_

AUTO_

REVERT_EN

CLKin_SEL_

AUTO_EN

0x147

CLKin_SEL_MANUAL

CLKin1_DEMUX

CLKin0_DEMUX

0x148

0x149

0x14A

0x14B

0

CLKin_SEL0_MUX

CLKin_SEL1_MUX

RESET_MUX

CLKin_SEL0_TYPE

CLKin_SEL1_TYPE

RESET_TYPE

SDIO_RDBK_

TYPE

0

HOLDOVER_

FORCE

LOS_TIMEOUT

LOS_EN

TRACK_EN

MAN_DAC_EN

MAN_DAC[9:8]

0x14C

0x14D

0x14E

0x14F

MAN_DAC[7:0]

0

DAC_TRIP_LOW

DAC_TRIP_HIGH

DAC_CLK_MULT

DAC_CLK_CNTR

CLKin_OVERRI

DE

HOLDOVER_

EXIT_MODE

HOLDOVER_ LOS_EXTERNA HOLDOVER_ CLKin_SWITCH HOLDOVER_

0x150

0

PLL1_DET

L_INPUT

HOLDOVER_DLD_CNT[13:8]

HOLDOVER_DLD_CNT[7:0]

CLKin0_R[13:8]

VTUNE_DET

_CP_TRI

EN

0x151

0x152

0x153

0x154

0x155

0x156

0x157

0x158

0x159

0x15A

0x15B

0x15C

0x15D

0x15E

0x15F

0x160

0x161

0

CLKin0_R[7:0]

CLKin1_R[7:0]

CLKin2_R[7:0]

PLL1_N[7:0]

CLKin1_R[13:8]

CLKin2_R[13:8]

PLL1_N[13:8]

PLL1_WND_SIZE

PLL1_CP_TRI

PLL1_CP_POL

PLL1_CP_GAIN

PLL1_DLD_CNT[13:8]

0

PLL1_DLD_CNT[7:0]

0

HOLDOVER_EXIT_NADJ

PLL1_LD_TYPE

PLL2_R

PLL1_LD_MUX

0

PLL2_R

PLL2_REF_2X_

EN

0x162

PLL2_P

0

OSCin_FREQ

PLL2_XTAL_EN

0x163

0x164

0

PLL2_N_CAL[17:16]

PLL2_N_CAL[15:8]

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表8-6. Register Map (continued)

ADDRESS

[14:0]

DATA[7:0]

23:8

7

6

5

4

3

2

1

0

0x165

0x166

0x167

0x168

0x169

0x16A

0x16B

0x173

0x177

PLL2_N_CAL[7:0]

0

PLL2_N[17:16]

PLL2_N[15:8]

PLL2_N[7:0]

0

PLL2_WND_SIZE

PLL2_CP_GAIN

PLL2_CP_POL

PLL2_CP_TRI

PLL2_DLD_EN

0

PLL2_DLD_CNT[13:8]

PLL2_DLD_CNT[7:0]

0

PLL2_PRE_PD

PLL2_PD

FIN0_PD

0

PLL1R_RST

CLR_PLL1_LD_ CLR_PLL2_LD_

0x182

0x183

0

LOST

RB_PLL1_DLD_

LOST

RB_PLL2_DLD_

LOST

RB_PLL1_DLD

RB_PLL2_DLD

RB_CLKin2_

SEL

RB_CLKin1_

SEL

RB_CLKin0_

SEL

RB_CLKin2_

LOS

RB_CLKin1_

LOS

RB_CLKin0_

LOS

0x184

0x185

0x188

0x555

RB_DAC_VALUE[9:8]

RB_DAC_VALUE[7:0]

RB_

HOLDOVER

RB_DAC_

LOCKED

0

X

RB_DAC_RAIL RB_DAC_HIGH RB_DAC_LOW

SPI_LOCK

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8.6.2 Device Register Descriptions

The following section details the fields of each register, the Power-On-Reset Defaults, and specific descriptions

of each bit.

In some cases similar fields are located in multiple registers. In this case specific outputs may be designated as

X or Y. In these cases, the X represents even numbers from 0 to 12 and the Y represents odd numbers from 1 to

13. In the case where X and Y are both used in a bit name, then Y = X + 1.

8.6.2.1 System Functions

8.6.2.1.1 RESET, SPI_3WIRE_DIS

This register contains the RESET function and the ability to turn off 3-wire SPI mode. To use a 4-wire SPI mode,

selecting SPI Read back in one of the output MUX settings. For example CLKin0_SEL_MUX or RESET_MUX. It

is possible to have 3-wire and 4-wire readback at the same time.

表8-7. Register 0x000

BIT

7

NAME

RESET

NA

POR DEFAULT

DESCRIPTION

0: Normal operation

1: Reset (automatically cleared)

0

6:5

Reserved

Disable 3-wire SPI mode.

0: 3 Wire Mode enabled

1: 3 Wire Mode disabled

4

SPI_3WIRE_DIS

NA

0

3:0

NA

Reserved

8.6.2.1.2 POWERDOWN

This register contains the POWERDOWN function.

表8-8. Register 0x002

BIT

7:1

NAME

POR DEFAULT

DESCRIPTION

NA

POWERDOWN

0

Reserved

0: Normal operation

1: Power down device.

0

8.6.2.1.3 ID_DEVICE_TYPE

This register contains the product device type. This is read only register.

表8-9. Register 0x003

BIT

NAME

POR DEFAULT

DESCRIPTION

7:0

ID_DEVICE_TYPE

6

PLL product device type.

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8.6.2.1.4 ID_PROD

These registers contain the product identifier. This is a read only register.

表8-10. ID_PROD Field Registers

MSB

LSB

0x004[7:0] / ID_PROD[15:8]

0x005[7:0] / ID_PROD[7:0]

表8-11. Registers 0x004 and 0x005

REGISTER

0x004

BIT

7:0

FIELD NAME

ID_PROD[7:0]

ID_PROD[15:8]

POR DEFAULT

DESCRIPTION

LSB of the product identifier.

MSB of the product identifier.

99 (0x63)

0x005

209 (0xD1)

8.6.2.1.5 ID_MASKREV

This register contains the IC version identifier. This is a read only register.

表8-12. Register 0x006

BIT

NAME

POR DEFAULT

DESCRIPTION

7:0

ID_MASKREV

112 (0x70)

IC version identifier

8.6.2.1.6 ID_VNDR

These registers contain the vendor identifier. This is a read only register.

表8-13. ID_VNDR Field Registers

MSB

LSB

0x00C[7:0] / ID_VNDR[15:8]

0x00D[7:0] / ID_VNDR[7:0]

表8-14. Registers 0x00C, 0x00D

REGISTER BIT

NAME

POR DEFAULT

DESCRIPTION

0x00C

0x00D

7:0

ID_VNDR[15:8]

ID_VNDR[7:0]

81 (0x51)

MSB of the vendor identifier.

LSB of the vendor identifier.

4 (0x04)

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8.6.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls

8.6.2.2.1 DCLKX_Y_DIV

The device clock divider can drive up to two outputs, an even (X) and an odd (Y) clock output. Divide is a 10 bit

number and split across two registers.

表8-15. DCLKX_Y_DIV Field Registers

MSB

LSB

0x0102[1:0] = DCLK0_1_DIV[9:8]

0x010A[1:0] = DCLK2_3_DIV[9:8]

0x0112[1:0] = DCLK4_5_DIV[9:8]

0x011A[1:0] = DCLK6_7_DIV[9:8]

0x0122[1:0] = DCLK8_9_DIV[9:8]

0x012A[1:0] = DCLK10_11_DIV[9:8]

0x0132[1:0] = DCLK12_13_DIV[9:8]

0x100[7:0] = DCLK0_1_DIV[7:0]

0x108[7:0] = DCLK2_3_DIV[7:0]

0x110[7:0] = DCLK4_5_DIV[7:0]

0x118[7:0] = DCLK6_7_DIV[7:0]

0x120[7:0] = DCLK8_9_DIV[7:0]

0x128[7:0] = DCLK10_11_DIV[7:0]

0x130[7:0] = DCLK12_13_DIV[7:0]

表8-16. Registers 0x100, 0x108, 0x110, 0x118, 0x120, 0x128, and 0x130

0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132

REGISTER

BIT NAME

POR DEFAULT

DESCRIPTION

0x102,

0x10A,

0x112,

0x11A,

0x122,

DCLKX_Y_DIV sets the divide value for the clock output, the divide

may be even or odd. Both even or odd divides output a 50% duty

cycle clock if duty cycle correction (DCC) is enabled.

1:0

7:0

DCLKX_Y_DIV[9:8]

X_Y = 0_1 →2

X_Y = 2_3 →4

X_Y = 4_5 →8

X_Y = 6_7 →8

X_Y = 8_9 →8

X_Y = 10_11 →8

X_Y = 12_13 →2

Field Value

0 (0x00)

Divider Value

Reserved

1 ⁽¹⁾

0x12A, 0x132

1 (0x01)

0x100,

0x108,

0x110, 0x118,

0x120,

2 (0x02)

2

...

DCLKX_Y_DIV[7:0]

1022 (0x3FE)

1023 (0x3FF)

1022

1023

0x128, and

0x130

(1) Duty cycle correction must also be enabled, DCLKX_Y_DCC = 1.

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8.6.2.2.2 DCLKX_Y_DDLY

This register controls the digital delay for the device clock outputs.

表8-17. DCLKX_Y_DDLY Field Registers

MSB

LSB

0x0102[2:3] = DCLK0_1_DDLY[9:8]

0x010A[2:3] = DCLK2_3_DDLY[9:8]

0x0112[2:3] = DCLK4_5_DDLY[9:8]

0x011A[2:3] = DCLK6_7_DDLY[9:8]

0x0122[2:3] = DCLK8_9_DDLY[9:8]

0x012A[2:3] = DCLK10_11_DDLY[9:8]

0x0132[2:3] = DCLK12_13_DDLY[9:8]

0x101[7:0] = DCLK0_1_DDLY[7:0]

0x109[7:0] = DCLK2_3_DDLY[7:0]

0x111[7:0] = DCLK4_5_DDLY[7:0]

0x119[7:0] = DCLK6_7_DDLY[7:0]

0x121[7:0] = DCLK8_9_DDLY[7:0]

0x129[7:0] = DCLK10_11_DDLY[7:0]

0x131[7:0] = DCLK12_13_DDLY[7:0]

表8-18. Registers 0x101, 0x109, 0x111, 0x119, 0x121, 0x129, 0x131

0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132

REGISTER

BIT NAME

POR DEFAULT

DESCRIPTION

0x102,

0x10A,

0x112,

0x11A,

0x122,

Static digital delay which takes effect after a SYNC.

Field Value

0 (0x00)

1 (0x01)

...

Delay Values

Reserved

2:3 DCLKX_Y_DDLY[9:8]

Reserved

0x12A, 0x132

...

10 (0x0A)

7 (0x07)

8 (0x08)

9 (0x09)

...

Reserved

0x101,

0x109, 0x111,

0x119,

8

9

7:0 DCLKX_Y_DDLY[7:0]

0x121,

...

0x129, 0x131

1022 (0x3FE)

1023 (0x3FF)

1022

1023

Depending on the DCLK divide value, there may be an adjustment in phase delay required. 表 8-19 illustrate the

impact of different divide values on the final digital delay.

表8-19. Digital Delay Adjustment based on Divide Values

DIVIDE VALUE

DIGITAL DELAY ADJUSTMENT

–2⁽¹⁾

0

2, 3

4, 7 to 1023

5

6

+2

+1

(1) Before SYNC, program divider to Divide-by-4, then back to Divide-by-2 or Divide-by-3 to ensure '-2' delay relationship.

For example, 表 8-20 shows a system with clock outputs having divide values /2,/4,/5 and /6 to share a common

edge.

表8-20. Digital Delay Adjustment Illustration

DIVIDE VALUE

PROGRAMMED DDLY

ACTUAL DDLY

2

4

5

6

13

11

8

11

10

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8.6.2.2.3 CLKoutX_Y_PD, CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKX_Y_DDLY_PD, DCLKX_Y_DDLY[9:8],

DCLKX_Y_DIV[9:8]

表8-21. Registers 0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132

BIT

NAME

POR DEFAULT

DESCRIPTION

Power down the clock group defined by X and Y.

0: Enabled

7

CLKoutX_Y_PD

1

1: Power down entire clock group including both CLKoutX and CLKoutY.

Sets output drive level for clocks. This has no impact for the even clock output

in bypass mode.

0: Normal operation

6

CLKoutX_Y_ODL

0

1: Higher current consumption and lower noise floor.

Sets input drive level for clocks.

0: Normal operation

1: Higher current consumption and lower noise floor.

5

4

CLKoutX_Y_IDL

0

Powerdown the device clock digital delay circuitry.

0: Enabled

DCLKX_Y_DDLY_PD

1: Power down static digital delay for device clock divider.

3:2

1:0

DCLKX_Y_DDLY[9:8]

DCLKX_Y_DIV[9:8]

0

MSB of static digital delay, see DCLKX_Y_DDLY.

MSB of device clock divide value, see 表8-16.

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8.6.2.2.4 CLKoutX_SRC_MUX, DCLKX_Y_PD, DCLKX_Y_BYP, DCLKX_Y_DCC, DCLKX_Y_POL, DCLKX_Y_HS

These registers control the analog delay properties for the device clocks.

表8-22. Registers 0x103, 0x10B, 0x113, 0x11B, 0x123, 0x12B, 0x133

BIT

7

NAME

NA

POR DEFAULT

DESCRIPTION

0

1

Reserved

6

NA

Select CLKoutX clock source. Source must also be powered up.

5

4

CLKoutX_SRC_MUX

DCLKX_Y_PD

0

0: Device Clock

1: SYSREF

Power down the clock group defined by X and Y.

0: Enabled

1: Power down enter clock group X_Y.

Enable high performance bypass path for even clock outputs.

0: CLKoutX not in high performance bypass mode. CML is not valid for

CLKoutX_FMT.

3

2

DCLKX_BYP

0

1: CLKoutX in high performance bypass mode. Only CML clock format is valid.

Duty cycle correction for device clock divider. Required for half step.

0: No duty cycle correction.

DCLKX_Y_DCC

1: Duty cycle correction enabled.

Invert polarity of device clock output. This also applies to CLKoutX in high

performance bypass mode. Polarity invert is a method to get a half-step phase

adjustment in high performance bypass mode or /1 divide value.

0: Normal polarity

1

0

DCLKX_Y_POL

DCLKX_Y_HS

0

1: Invert polarity

Sets the device clock half step value. Must be set to zero (0) for a divide of 1.

No effect if DCLKX_Y_DCC = 0.

0: No phase adjustment

1: Adjust device clock phase –0.5 clock distribution path cycles.

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8.6.2.2.5 CLKoutY_SRC_MUX, SCLKX_Y_PD, SCLKX_Y_DIS_MODE, SCLKX_Y_POL, SCLKX_Y_HS

These registers set the half step for the device clock, the SYSREF output MUX, the SYSREF clock digital delay,

and half step.

表8-23. Registers 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

Select CLKoutX clock source. Source must also be powered up.

5

4

CLKoutY_SRC_MUX

SCLKX_Y_PD

0

1

0: Device Clock

1: SYSREF

Power down the SYSREF clock output circuitry.

0: SYSREF enabled

1: Power down SYSREF path for clock pair.

Set disable mode for clock outputs controlled by SYSREF. Some cases will

assert when SYSREF_GBL_PD = 1.

Field Value

0 (0x00)

Disable Mode

Active in normal operation

1 (0x01)

If SYSREF_GBL_PD = 1, the output is

a logic low, otherwise it is active.

3:2

SCLKX_Y_DIS_MODE

0

2 (0x02)

If SYSREF_GBL_PD = 1, the output is

a nominal Vcm voltage for odd clock

channels⁽¹⁾and low for even clocks.

Otherwise outputs are active.

3 (0x03)

Output is a nominal Vcm voltage⁽¹⁾

Sets the polarity of clock on SCLKX_Y when SYSREF clock output is selected

with CLKoutX_MUX or CLKoutY_MUX.

0: Normal

1: Inverted

1

0

SCLKX_Y_POL

SCLKX_Y_HS

0

Sets the local SYSREF clock half step value.

0: No phase adjustment

1: Adjust device SYSREF phase -0.5 clock distribution path cycles.

(1) If LVPECL mode is used with emitter resistors to ground, the output Vcm will be approximately 0 V, each pin will be approximately 0 V.

If CML mode is used with pullups to V_CC, the output V_CMwill be approximately V_CCV, each pin will be approximately V_CCV.

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8.6.2.2.6 SCLKX_Y_ADLY_EN, SCLKX_Y_ADLY

These registers set the analog delay parameters for the SYSREF outputs.

表8-24. Registers 0x105, 0x10D, 0x115, 0x11D, 0x125, 0x12D, 0x135

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

Enables analog delay for the SYSREF output.

0: Disabled

1: Enabled

SCLKX_Y

_ADLY_EN

5

0

SYSREF analog delay in approximately 21 ps steps. Selecting analog delay

adds an additional 125 ps in propagation delay. Range is 125 ps to 608 ps.

Field Value

0 (0x0)

1 (0x1)

2 (0x2)

3 (0x3)

...

Delay Value

125 ps

146 ps (+21 ps from 0x00)

167 ps (+42 ps from 0x00)

188 ps (+63 ps from 0x00)

...

SCLKX_Y

_ADLY

4:0

0

14 (0xE)

15 (0xF)

587 ps (+462 ps from 0x00)

608 ps (+483 ps from 0x00)

8.6.2.2.7 SCLKX_Y_DDLY

表8-25. Registers 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136

BIT

NAME

POR DEFAULT

DESCRIPTION

7:4

NA

0

Reserved

Sets the number of VCO cycles to delay SDCLKout by

Field Value

0 (0x00)

Delay Cycles

Bypass

1 (0x01)

2

3:0

SCLKX_Y_DDLY

0

2 (0x02)

3

...

10 (0x0A)

11 to 15 (0x0B to 0x0F)

11

Reserved

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8.6.2.2.8 CLKoutY_FMT, CLKoutX_FMT

The difference in the tables is that some of the clock outputs have inverted CMOS polarity settings.

表8-26. Registers 0x107 (CLKout0_1), 0x11F (CLKout6_7), 0x12F (CLKout10_11)

BIT

NAME

POR DEFAULT

DESCRIPTION

Set CLKoutY clock format

Field Value

0 (0x00)

Output Format

Powerdown

1 (0x01)

LVDS

2 (0x02)

HSDS 6 mA

3 (0x03)

HSDS 8 mA

4 (0x04)

LVPECL 1600 mV

LVPECL 2000 mV

LCPECL

5 (0x05)

6 (0x06)

7:4

CLKoutY_FMT

0

7 (0x07)

CML 16 mA

8 (0x08)

CML 24 mA

9 (0x09)

CML 32 mA

10 (0x0A)

CMOS (Off/Inv)

CMOS (Norm/Off)

CMOS (Inv/Inv)

CMOS (Inv/Norm)

CMOS (Norm/Inv)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

CMOS (Norm/Norm)

Set CLKoutX clock format

Output Format

DCLKX_BYP = 0

Output Format

DCLKX_BYP = 1

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

Powerdown

Reserved

CML 16 mA

CML 24 mA

CML 32 mA

Reserved

LVDS

HSDS 6 mA

HSDS 8 mA

LVPECL 1600 mV

LVPECL 2000 mV

LCPECL

3:0

CLKoutX_FMT

0

Reserved

CMOS (Off/Inv)⁽¹⁾

CMOS (Norm/Off)⁽¹⁾

CMOS (Inv/Inv)⁽¹⁾

CMOS (Inv/Norm)⁽¹⁾

CMOS (Norm/Inv)⁽¹⁾

CMOS (Norm/Norm)⁽¹⁾

(1) Only valid for CLKout10.

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表8-27. Registers 0x10F (CLKout2_3), 0x117 (CLKout4_5), 0x127 (CLKout8_9), 0x137 (CLKout12_13)

BIT

NAME

POR DEFAULT

DESCRIPTION

Set CLKoutY clock format

Field Value

0 (0x00)

Output Format

Powerdown

1 (0x01)

LVDS

2 (0x02)

HSDS 6 mA

HSDS 8 mA

LVPECL 1600 mV

LVPECL 2000 mV

LCPECL

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7:4

CLKoutY_FMT

0

7 (0x07)

CML 16 mA

8 (0x08)

CML 24 mA

9 (0x09)

CML 32 mA

10 (0x0A)

CMOS (Off/Norm)

CMOS (Inv/Off)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

CMOS (Norm/Norm)

CMOS (Norm/Inv)

CMOS (Inv/Norm)

CMOS (Inv/Inv)

15 (0x0F)

Set CLKoutX clock format

Output Format

DCLKX_BYP = 0

Output Format

DCLKX_BYP = 1

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

Powerdown

Reserved

CML 16 mA

CML 24 mA

CML 32 mA

Reserved

LVDS

HSDS 6 mA

HSDS 8 mA

LVPECL 1600 mV

LVPECL 2000 mV

LCPECL

3:0

CLKoutX_FMT

0

Reserved

CMOS (Off/Norm)⁽¹⁾

CMOS (Inv/Off)⁽¹⁾

CMOS (Norm/Norm)⁽¹⁾

CMOS (Norm/Inv)⁽¹⁾

CMOS (Inv/Norm)⁽¹⁾

CMOS (Inv/Inv)⁽¹⁾

(1) Only valid for CLKout8.

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8.6.2.3 SYSREF, SYNC, and Device Config

8.6.2.3.1 VCO_MUX, OSCout_MUX, OSCout_FMT

表8-28. Register 0x138

BIT

NAME

POR DEFAULT

DESCRIPTION

7

NA

0

Reserved

Selects clock distribution path source from VCO0, VCO1, or CLKIN (external

VCO)

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

VCO Selected

VCO 0

6:5

VCO_MUX

2

0

VCO 1

FIN1 / CLKIN1 (external VCO)

FIN0

Select the source for OSCout:

0: Buffered OSCIN

4

OSCout_MUX

1: Feedback Mux

Selects the output format of OSCout. When powered down, these pins may be

used as CLKIN2.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

OSCOUT Format

Power down (CLKIN2)

LVDS

Reserved

LVPECL 1600 mVpp

LVPECL 2000 mVpp

LVCMOS (Norm / Inv)

LVCMOS (Inv / Norm)

LVCMOS (Norm / Norm)

LVCMOS (Inv / Inv)

LVCMOS (Off / Norm)

LVCMOS (Off / Inv)

LVCMOS (Norm / Off)

LVCMOS (Inv / Off)

LVCMOS (Off / Off)

3:0

OSCout_FMT

4

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8.6.2.3.2 SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX

This register sets the source for the SYSREF outputs. Refer to 图8-3 and SYNC/SYSREF.

表8-29. Register 0x139

BIT

7:6

5

NAME

POR DEFAULT

DESCRIPTION

NA

0

Reserved

NA

Enables the SYNC/SYSREF_REQ pin to force the SYSREF_MUX = 3 for

continuous pulses. When using this feature enable pulser and set

SYSREF_MUX = 2 (Pulser).

4

SYSREF_REQ_EN

0

Bypass SYNC polarity invert and other circuitry.

0: Normal

1: SYNC signal is bypassed

3

2

SYNC_BYPASS

NA

0

Reserved

Selects the SYSREF source.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

SYSREF Source

Normal SYNC

1:0

SYSREF_MUX

0

Re-clocked

SYSREF Pulser

SYSREF Continuous

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8.6.2.3.3 SYSREF_DIV

These registers set the value of the SYSREF output divider.

表8-30. SYSREF_DIV[12:0]

MSB

LSB

0x13A[4:0] = SYSREF_DIV[12:8]

0x13B[7:0] = SYSREF_DIV[7:0]

表8-31. Registers 0x13A and 0x13B

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x13A

7:5

NA

0

Reserved

Divide value for the SYSREF outputs.

Field Value

0 to 7 (0x00 to 0x07)

8 (0x08)

Divide Value

0x13A

0x13B

4:0

7:0

SYSREF_DIV[12:8]

SYSREF_DIV[7:0]

12

0

Reserved

8

9

9 (0x09)

...

8190 (0x1FFE)

8191 (0X1FFF)

8190

8191

8.6.2.3.4 SYSREF_DDLY

These registers set the delay of the SYSREF digital delay value.

表8-32. SYSREF Digital Delay Register Configuration, SYSREF_DDLY[12:0]

MSB

LSB

0x13C[4:0] / SYSREF_DDLY[12:8]

0x13D[7:0] / SYSREF_DDLY[7:0]

表8-33. Registers 0X13C and 0X13D

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x13C

7:5

NA

0

Reserved

Sets the value of the SYSREF digital delay.

Field Value

0x00 to 0x07

8 (0x08)

Delay Value

0x13C

0x13D

4:0

7:0

SYSREF_DDLY[12:8]

SYSREF_DDLY[7:0]

0

8

Reserved

8

9

9 (0x09)

...

8190 (0x1FFE)

8191 (0X1FFF)

8190

8191

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8.6.2.3.5 SYSREF_PULSE_CNT

This register sets the number of SYSREF pulses if SYSREF is not in continuous mode. See SYSREF_REQ_EN,

SYNC_BYPASS, SYSREF_MUX for further description of SYSREF's outputs.

Programming the register causes the specified number of pulses to be output if "SYSREF Pulses" is selected by

SYSREF_MUX and SYSREF functionality is powered up.

表8-34. Register 0x13E

BIT

NAME

POR DEFAULT

DESCRIPTION

7:2

NA

0

Reserved

Sets the number of SYSREF pulses generated when not in continuous mode.

See SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX for more

information on SYSREF modes.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Number of Pulses

1 pulse

1:0

SYSREF_PULSE_CNT

3

2 pulses

4 pulses

8 pulses

8.6.2.3.6 PLL2_RCLK_MUX, PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN

This register controls the feedback feature.

表8-35. Register 0x13F

BIT

7

NAME

PLL2_RCLK_MUX

NA

POR DEFAULT

DESCRIPTION

Selects the source for PLL2 reference.

0

0: OSCIN

1: Currently selected CLKIN.

6

Reserved

Selects the input to the PLL2 N Divider

0: PLL2 Prescaler

5

PLL2_NCLK_MUX

1: Feedback Mux

Selects the input to the PLL1 N Divider.

0: OSCIN

1: Feedback Mux

4:3

2:1

0

PLL1_NCLK_MUX

0

2: PLL2 Prescaler

When in 0-delay mode, the feedback mux selects the clock output to be fed

back into the PLL1 N Divider.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Source

CLKOUT6

FB_MUX

CLKOUT8

SYSREF Divider

External

When using 0-delay, FB_MUX_EN must be set to 1 power up the feedback

mux.

0: Feedback mux powered down

1: Feedback mux enabled

FB_MUX_EN

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8.6.2.3.7 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD,

SYSREF_PLSR_PD

This register contains power-down controls for OSCIN and SYSREF functions.

表8-36. Register 0x140

BIT

NAME

POR DEFAULT

DESCRIPTION

Power down PLL1

0: Normal operation

1: Power down

7

PLL1_PD

1

Power down VCO_LDO

0: Normal operation

1: Power down

6

5

4

VCO_LDO_PD

VCO_PD

1

0

Power down VCO

0: Normal operation

1: Power down

Power down the OSCIN port.

0: Normal operation

1: Power down

OSCin_PD

Power down individual SYSREF outputs depending on the setting of

SCLKX_Y_DIS_MODE for each SYSREF output. SYSREF_GBL_PD allows

many SYSREF outputs to be controlled through a single bit.

0: Normal operation

3

2

SYSREF_GBL_PD

SYSREF_PD

0

1: Activate Power down Mode

Power down the SYSREF circuitry and divider. If powered down, SYSREF

output mode cannot be used. SYNC cannot be provided either.

0: SYSREF can be used as programmed by individual SYSREF output

registers.

1: Power down

Power down the SYSREF digital delay circuitry.

0: Normal operation, SYSREF digital delay may be used. Must be powered up

during SYNC for deterministic phase relationship with other clocks.

1: Power down

1

0

SYSREF_DDLY_PD

SYSREF_PLSR_PD

0

Power down the SYSREF pulse generator.

0: Normal operation

1: Power down

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8.6.2.3.8 DDLYdSYSREF_EN, DDLYdX_EN

This register enables dynamic digital delay for enabled device clocks and SYSREF when DDLYd_STEP_CNT is

programmed.

表8-37. Register 0x141

BIT

NAME

POR DEFAULT

DESCRIPTION

Enables dynamic digital delay on

SYSREF outputs

7

DDLYd _SYSREF_EN

0

Enables dynamic digital delay on

DCLKout12

6

5

4

3

2

1

0

DDLYd12_EN

DDLYd10_EN

DDLYd8_EN

DDLYd6_EN

DDLYd4_EN

DDLYd2_EN

DDLYd0_EN

0

Enables dynamic digital delay on

DCLKout10

Enables dynamic digital delay on

DCLKout8

0: Disabled

1: Enabled

Enables dynamic digital delay on

DCLKout6

Enables dynamic digital delay on

DCLKout4

Enables dynamic digital delay on

DCLKout2

Enables dynamic digital delay on

DCLKout0

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8.6.2.3.9 DDLYd_STEP_CNT

This register sets the number of dynamic digital delay adjustments that will occur. Upon programming, the

dynamic digital delay adjustment begins for each clock output with dynamic digital delay enabled. Dynamic

digital delay can only be started by SPI.

Other registers must be set: SYNC_MODE = 3

表8-38. Register 0x142

BIT

NAME

POR DEFAULT

DESCRIPTION

Sets the number of dynamic digital delay adjustments that will occur.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

Dynamic Digital Delay Adjustments

No Adjust

1 step

7:0

DDLYd_STEP_CNT

0

2 steps

3 steps

...

254 (0xFE)

255 (0xFF)

254 steps

255 steps

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8.6.2.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD,

SYNC_MODE

This register sets general SYNC parameters such as polarization, and mode. Refer to 图 8-3 for block diagram.

Refer to 表8-2 for using SYNC_MODE for specific SYNC use cases.

表8-39. Register 0x143

BIT

NAME

POR DEFAULT

DESCRIPTION

Except during SYSREF Setup Procedure (see SYNC/SYSREF), this bit should

always be programmed to 0. While this bit is set, extra current is used.

7

SYSREF_CLR

0

SYNC one shot enables edge sensitive SYNC.

0: SYNC is level sensitive and outputs will be held in SYNC as long as SYNC

is asserted.

6

SYNC_1SHOT_EN

0

1: SYNC is edge sensitive, outputs will be SYNCed on rising edge of SYNC.

This results in the clock being held in SYNC for a minimum amount of time.

Sets the polarity of the SYNC pin.

0: Normal

1: Inverted

5

4

SYNC_POL

SYNC_EN

0

Enables the SYNC functionality.

0: Disabled

1: Enabled

0: Off

3

2

SYNC_PLL2_DLD

SYNC_PLL1_DLD

0

1: Assert SYNC until PLL2 DLD = 1

0: Off

1: Assert SYNC until PLL1 DLD = 1

Sets the method of generating a SYNC event.

Field Value

SYNC Generation

Prevent SYNC Pin, SYNC_PLL1_DLD

flag, or SYNC_PLL2_DLD flag from

generating a SYNC event.

0 (0x00)

SYNC event generated from SYNC

pin or if enabled the

SYNC_PLL1_DLD flag or

SYNC_PLL2_DLD flag.

1 (0x01)

2 (0x02)

1:0

SYNC_MODE

1

For use with pulser - SYNC/SYSREF

pulses are generated by pulser block

via SYNC Pin or if enabled

SYNC_PLL1_DLD flag or

SYNC_PLL2_DLD flag.

For use with pulser - SYNC/SYSREF

pulses are generated by pulser block

when programming register 0x13E

(SYSREF_PULSE_CNT) is written to

(see SYSREF_PULSE_CNT).

3 (0x03)

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8.6.2.3.11 SYNC_DISSYSREF, SYNC_DISX

SYNC_DISX will prevent a clock output from being synchronized or interrupted by a SYNC event or when

outputting SYSREF.

表8-40. Register 0x144

BIT

NAME

POR DEFAULT

DESCRIPTION

Prevent the SYSREF clocks from becoming synchronized during a SYNC

event. If SYNC_DISSYSREF is enabled, the device will continue to operate

normally during a SYNC event.

7

SYNC_DISSYSREF

0

6

5

4

3

2

1

0

SYNC_DIS12

SYNC_DIS10

SYNC_DIS8

SYNC_DIS6

SYNC_DIS4

SYNC_DIS2

SYNC_DIS0

0

Prevent the device clock output from becoming synchronized during a SYNC

event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled,

then the device will continue to operate normally during a SYNC event or

SYSREF clock.

8.6.2.3.12 PLL1R_SYNC_EN, PLL1R_SYNC_SRC, PLL2R_SYNC_EN, FIN0_DIV2_EN, FIN0_INPUT_TYPE

These bits are used when synchronizing PLL1 and PLL2 R dividers.

表8-41. Register 0x145

BIT

NAME

POR DEFAULT

DESCRIPTION

7

NA

0

Reserved

Enable synchronization for PLL1 R divider

0: Not enabled

1: Enabled

6

PLL1R_SYNC_EN

PLL1R_SYNC_SRC

0

Select the source for PLL1 R divider synchronization

Field Value

Definition

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Reserved

SYNC Pin

CLKIN0

5:4

Reserved

Enable synchronization for PLL2 R divider. Synchronization for PLL2 R always

comes from the SYNC pin.

0: Not enabled

1: Enabled

3

2

PLL2R_SYNC_EN

FIN0_DIV2_EN

0

Sets the input path to use or bypass the divide-by-2.

0: Bypassed (÷1)

1: Divided (÷2)

Program input type to hardware interface used.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

Differential Input

1:0

FIN0_INPUT_TYPE

0

Single Ended Input (FIN0_P)

Single Ended Input (FIN0_N)

Reserved

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8.6.2.4 (0x146 - 0x149) CLKIN Control

8.6.2.4.1 CLKin_SEL_PIN_EN, CLKin_SEL_PIN_POL, CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE,

CLKin1_TYPE, CLKin0_TYPE

This register has CLKin enable and type controls. See Input Clock Switching for more info on how clock input

selection works.

表8-42. Register 0x146

BIT

NAME

POR DEFAULT

DESCRIPTION

7

CLKin_SEL_PIN_EN

0

Enables pin control according to Input Clock Switching.

Inverts the CLKin polarity for use in pin select mode.

6

5

4

3

CLKin_SEL_PIN_POL

CLKin2_EN

0

1

0: Active High

1: Active Low

Enable CLKin2 to be used during auto-switching.

0: Not enabled for auto mode

1: Enabled for auto clock switching mode

Enable CLKin1 to be used during auto-switching.

0: Not enabled for auto mode

1: Enabled for auto clock switching mode

CLKin1_EN

Enable CLKin0 to be used during auto-switching.

0: Not enabled for auto mode

CLKin0_EN

1: Enabled for auto clock switching mode

2

1

CLKin2_TYPE

CLKin1_TYPE

0

There are two buffer types for CLKin0,

1, and 2: bipolar and CMOS. Bipolar is

recommended for differential inputs

like LVDS or LVPECL. CMOS is

recommended for DC-coupled single

ended inputs.

When using bipolar, CLKinX and

CLKinX* must be AC-coupled.

When using CMOS, CLKinX and

CLKinX* may be AC or DC-coupled if

the input signal is differential. If the

input signal is single-ended the used

input may be either AC or DC-coupled

and the unused input must AC

grounded.

0: Bipolar

1: MOS

0

CLKin0_TYPE

0

8.6.2.4.2 CLKin_SEL_AUTO_REVERT_EN, CLKin_SEL_AUTO_EN, CLKin_SEL_MANUAL, CLKin1_DEMUX,

CLKin0_DEMUX

表8-43. Register 0x147

BIT

7

NAME

POR DEFAULT

DESCRIPTION

If the active clock is detected on a higher priority clock while the device is in

auto clock switching mode, the clock input is immediately switched. Highest

priority input is lowest numbered active clock input.

CLKin_SEL_

AUTO_REVERT_EN

0

6

CLKin_SEL_AUTO_EN

CLKin_SEL_MANUAL

Enables pin control according to 图8-7.

Selects the clock input when in manual mode according to 图8-7.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

CLKIN0

CLKIN1

CLKIN2

Holdover

5:4

1

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BIT

表8-43. Register 0x147 (continued)

NAME

POR DEFAULT

DESCRIPTION

Selects where the output of the CLKin1 buffer is directed.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

CLKin1 Destination

FIN

3:2

CLKin1_DEMUX

0

Feedback Mux (0-delay mode)

PLL1

Off

Selects where the output of the CLKin0 buffer is directed.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

CLKin0 Destination

SYSREF Mux

Reserved

PLL1

1:0

CLKin0_DEMUX

3

Off

8.6.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE

This register has CLKin_SEL0 controls.

表8-44. Register 0x148

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

This set the output value of the CLKin_SEL0 pin. This register only applies if

CLKin_SEL0_TYPE is set to an output mode

Field Value

Output Format

Logic Low

0 (0x00)

1 (0x01)

CLKin0 LOS

CLKin0 Selected

DAC Locked

DAC Low

2 (0x02)

5:3

CLKin_SEL0_MUX

0

3 (0x03)

4 (0x04)

5 (0x05)

DAC High

6 (0x06)

SPI Readback

Reserved

7 (0x07)

This sets the IO type of the CLKin_SEL0 pin.

Field Value

0 (0x00)

Configuration

Function

Input

Input mode, see Input

Clock Switching - Pin

Select Mode for

description of input

mode.

1 (0x01)

Input with pullup resistor

Input with pulldown

resistor

2 (0x02)

3 (0x03)

4 (0x04)

2:0

CLKin_SEL0_TYPE

2

Output (push-pull)

Output modes; the

CLKin_SEL0_MUX

register for description of

outputs.

Output inverted (push-

pull)

5 (0x05)

6 (0x06)

Reserved

Output (open-drain)

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8.6.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE

This register has CLKin_SEL1 controls and register readback SDIO pin type.

表8-45. Register 0x149

BIT

NAME

POR DEFAULT

DESCRIPTION

7

NA

0

Reserved

Sets the SDIO pin to open drain when during SPI readback in 3 wire mode.

6

SDIO_RDBK_TYPE

1

0: Output, push-pull

1: Output, open drain.

This set the output value of the CLKin_SEL1 pin. This register only applies if

CLKin_SEL1_TYPE is set to an output mode.

Field Value

Output Format

Logic Low

0 (0x00)

1 (0x01)

CLKin1 LOS

CLKin1 Selected

DAC Locked

DAC Low

2 (0x02)

5:3

CLKin_SEL1_MUX

0

3 (0x03)

4 (0x04)

5 (0x05)

DAC High

6 (0x06)

SPI Readback

Reserved

7 (0x07)

This sets the IO type of the CLKin_SEL1 pin.

Field Value

0 (0x00)

Configuration

Function

Input

Input mode, see Input

Clock Switching - Pin

Select Mode for

description of input

mode.

1 (0x01)

Input with pullup resistor

Input with pulldown

resistor

2 (0x02)

3 (0x03)

4 (0x04)

2:0

CLKin_SEL1_TYPE

2

Output (push-pull)

Output modes; see the

CLKin_SEL1_MUX

register for description of

outputs.

Output inverted (push-

pull)

5 (0x05)

6 (0x06)

Reserved

Output (open-drain)

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8.6.2.5 RESET_MUX, RESET_TYPE

This register contains control of the RESET pin.

表8-46. Register 0x14A

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

This sets the output value of the RESET pin. This register only applies if

RESET_TYPE is set to an output mode.

Field Value

Output Format

Logic Low

0 (0x00)

1 (0x01)

Reserved

5:3

RESET_MUX

0

2 (0x02)

CLKin2 Selected

DAC Locked

DAC Low

3 (0x03)

4 (0x04)

5 (0x05)

DAC High

6 (0x06)

SPI Readback

This sets the IO type of the RESET pin.

Field Value

0 (0x00)

Configuration

Function

Input

1 (0x01)

Input with pullup resistor

Reset Mode

Reset pin high = Reset

Input with pulldown

resistor

2 (0x02)

3 (0x03)

4 (0x04)

2:0

RESET_TYPE

2

Output (push-pull)

Output inverted (push-

pull)

Output modes; see the

RESET_MUX register for

description of outputs.

5 (0x05)

6 (0x06)

Reserved

Output (open-drain)

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8.6.2.6 (0x14B - 0x152) Holdover

8.6.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]

This register contains the holdover functions.

表8-47. Register 0x14B

BIT

NAME

POR DEFAULT

DESCRIPTION

This controls the amount of time in which no activity on a CLKin forces a clock

switch event.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Timeout

5 MHz typical

25 MHz typical

100 MHz typical

200 MHz typical

7:6

LOS_TIMEOUT

0

Enables the LOS (Loss-of-Signal) timeout control. Valid for MOS clock inputs.

5

4

LOS_EN

0

0: Disabled

1: Enabled

Enable the DAC to track the PLL1 tuning voltage, optionally for use in holdover

mode. After device reset, tracking starts at DAC code = 512.

Tracking can be used to monitor PLL1 voltage in any mode.

0: Disabled

TRACK_EN

1: Enabled, will only track when PLL1 is locked.

This bit forces holdover mode. When holdover mode is forced, if

MAN_DAC_EN = 1, then the DAC will set the programmed MAN_DAC value.

Otherwise, the tracked DAC value will set the DAC voltage.

0: Disabled

HOLDOVER

_FORCE

3

0

1: Enabled.

This bit enables the manual DAC mode.

2

MAN_DAC_EN

MAN_DAC[9:8]

1

2

0: Automatic

1: Manual

1:0

See MAN_DAC for more information on the MAN_DAC settings.

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8.6.2.6.2 MAN_DAC

These registers set the value of the DAC in holdover mode when used manually.

表8-48. MAN_DAC[9:0]

MSB

LSB

0x14B[1:0]

0x14C[7:0]

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

See LOS_TIMEOUT, LOS_EN, TRACK_EN,

HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8] for

information on these bits.

0x14B

7:2

Sets the value of the manual DAC when in manual DAC

mode.

Field Value

0 (0x00)

DAC Value

0x14B

0x14C

1:0

7:0

MAN_DAC[9:8]

MAN_DAC[7:0]

2

0

1

1 (0x01)

2 (0x02)

2

...

1022 (0x3FE)

1023 (0x3FF)

1022

1023

8.6.2.6.3 DAC_TRIP_LOW

This register contains the high value at which holdover mode is entered.

表8-49. Register 0x14D

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

Voltage from GND at which holdover is entered if HOLDOVER_VTUNE_DET

is enabled.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Trip Value

1 x Vcc / 64

2 x Vcc / 64

3 x Vcc / 64

4 x Vcc / 64

...

5:0

DAC_TRIP_LOW

0

61 (0x17)

62 (0x18)

63 (0x19)

62 x Vcc / 64

63 x Vcc / 64

64 x Vcc / 64

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8.6.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH

This register contains the multiplier for the DAC clock counter and the low value at which holdover mode is

entered.

表8-50. Register 0x14E

BIT

NAME

POR DEFAULT

DESCRIPTION

This is the multiplier for the DAC_CLK_CNTR which sets the rate at which the

DAC value is tracked.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

DAC Multiplier Value

4

7:6

DAC_CLK_MULT

0

64

1024

16384

Voltage from Vcc at which holdover is entered if HOLDOVER_VTUNE_DET is

enabled.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Trip Value

1 x Vcc / 64

2 x Vcc / 64

3 x Vcc / 64

4 x Vcc / 64

...

5:0

DAC_TRIP_HIGH

0

61 (0x17)

62 (0x18)

63 (0x19)

62 x Vcc / 64

63 x Vcc / 64

64 x Vcc / 64

8.6.2.6.5 DAC_CLK_CNTR

This register contains the value of the DAC when in tracked mode.

表8-51. Register 0x14F

BIT

NAME

POR DEFAULT

DESCRIPTION

This with DAC_CLK_MULT set the rate at which the DAC is updated. The

update rate is = DAC_CLK_MULT * DAC_CLK_CNTR / PLL1 PDF

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Value

0

1

2

7:0

DAC_CLK_CNTR

127

3

...

253 (0xFD)

254 (0xFE)

255 (0xFF)

253

254

255

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8.6.2.6.6 CLKin_OVERRIDE, HOLDOVER_EXIT_MODE, HOLDOVER_PLL1_DET, LOS_EXTERNAL_INPUT,

HOLDOVER_VTUNE_DET, CLKin_SWITCH_CP_TRI, HOLDOVER_EN

This register has controls for enabling clock in switch events.

表8-52. Register 0x150

BIT

NAME

POR DEFAULT

DESCRIPTION

7

NA

0

Reserved

When manual clock select is enabled, then CLKin_SEL_MANUAL = 0/1/2

selects a manual clock input. CLKin_OVERRIDE = 1 will force that clock input.

CLKin_OVERRIDE = 1 is used with clock distribution mode for best

performance.

CLKin

_OVERRIDE

6

0

0: Normal, no override.

1: Force select of only CLKin0/1/2 as specified by CLKin_SEL_MANUAL in

manual mode. Dynamic digital delay will not operate.

0: Exit based on LOS status. If clock is active by LOS, then begin exit.

1: Exit based on PLL1 DLD. When the PLL1 phase detector confirming valid

clock.

HOLDOVER_

EXIT_MODE

5

4

0

This enables the HOLDOVER when PLL1 lock detect signal transitions from

high to low.

0: PLL1 DLD does not cause a clock switch event

1: PLL1 DLD causes a clock switch event

HOLDOVER

_PLL1_DET

Use external signals for LOS status instead of internal LOS circuitry.

CLKin_SEL0 pin is used for CLKin0 LOS, CLKin_SEL1 pin is used for CLKin1

LOS, and Status_LD1 is used for CLKin2 LOS. For any of these pins to be

valid, the corresponding _TYPE register must be programmed as an input.

0: Disabled

3

2

LOS_EXTERNAL_INPUT

0

1: Enabled

Enables the DAC Vtune rail detector. When the DAC achieves a specified

Vtune, if this bit is enabled, the current clock input is considered invalid and an

input clock switch event is generated.

0: Disabled

HOLDOVER_

VTUNE_DET

1: Enabled

Enable clock switching with tri-stated charge pump.

0: Not enabled.

1: PLL1 charge pump tri-states during clock switching.

1

0

CLKin_SWITCH_CP_TRI

HOLDOVER_EN

0

Sets whether holdover mode is active or not.

0: Disabled

1: Enabled

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8.6.2.6.7 HOLDOVER_DLD_CNT

表8-53. HOLDOVER_DLD_CNT[13:0]

MSB

LSB

0x151[5:0] / HOLDOVER_DLD_CNT[13:8]

0x152[7:0] / HOLDOVER_DLD_CNT[7:0]

This register has the number of valid clocks of PLL1 PDF before holdover is exited.

表8-54. Registers 0x151 and 0x152

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x151

7:6

NA

0

Reserved

The number of valid clocks of PLL1 PDF before holdover

mode is exited.

HOLDOVER

_DLD_CNT[13:8]

Field Value

0 (0x00)

Count Value

0x151

0x152

5:0

7:0

2

0

1

1 (0x01)

2 (0x02)

2

...

HOLDOVER

_DLD_CNT[7:0]

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

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8.6.2.7 (0x153 - 0x15F) PLL1 Configuration

8.6.2.7.1 CLKin0_R

表8-55. CLKin0_R[13:0]

MSB

LSB

0x153[5:0] / CLKin0_R[13:8]

0x154[7:0] / CLKin0_R[7:0]

These registers contain the value of the CLKin0 divider.

表8-56. Registers 0x153 and 0x154

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x153

7:6

NA

0

Reserved

The value of PLL1 N counter when CLKin0 is selected.

Field Value

0 (0x00)

Divide Value

0x153

0x154

5:0

7:0

CLKin0_R[13:8]

CLKin0_R[7:0]

0

Reserved

1 (0x01)

1

2

2 (0x02)

...

120

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

8.6.2.7.2 CLKin1_R

MSB

表8-57. CLKin1_R[13:0]

LSB

0x155[5:0] / CLKin1_R[13:8]

0x156[7:0] / CLKin1_R[7:0]

These registers contain the value of the CLKin1 R divider.

表8-58. Registers 0x155 and 0x156

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x155

7:6

NA

0

Reserved

The value of PLL1 R counter when CLKin1 is selected.

Field Value

0 (0x00)

Divide Value

0x155

0x156

5:0

7:0

CLKin1_R[13:8]

CLKin1_R[7:0]

0

Reserved

1 (0x01)

1

2

2 (0x02)

...

150

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

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8.6.2.7.3 CLKin2_R

表8-59. CLKin2_R[13:0]

MSB

LSB

0x157[5:0] / CLKin2_R[13:8]

0x158[7:0] / CLKin2_R[7:0]

表8-60. Registers 0x157 and 0x158

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x157

7:6

NA

0

Reserved

The value of PLL1 R counter when CLKin2 is selected.

Field Value

0 (0x00)

Divide Value

0x157

0x158

5:0

7:0

CLKin2_R[13:8]

CLKin2_R[7:0]

0

Reserved

1 (0x01)

1

2

2 (0x02)

...

150

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

8.6.2.7.4 PLL1_N

表8-61. PLL1_N[13:0]

MSB

LSB

0x159[5:0] / PLL1_N[13:8]

0x15A[7:0] / PLL1_N[7:0]

These registers contain the N divider value for PLL1.

表8-62. Registers 0x159 and 0x15A

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x159

7:6

NA

0

Reserved

The value of PLL1 N counter.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Divide Value

0x159

0x15A

5:0

7:0

PLL1_N[13:8]

PLL1_N[7:0]

0

Not Valid

1

2

120

...

4,095 (0xFFF)

4,095

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8.6.2.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN

This register controls the PLL1 phase detector.

表8-63. Register 0x15B

BIT

NAME

POR DEFAULT

DESCRIPTION

PLL1_WND_SIZE sets the window size used for digital lock detect for PLL1. If

the phase error between the reference and feedback of PLL1 is less than

specified time, then the PLL1 lock counter increments.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

4 ns

7:6

PLL1_WND_SIZE

3

9 ns

19 ns

43 ns

This bit allows for the PLL1 charge pump output pin, CPout1, to be placed into

TRI-STATE.

0: PLL1 CPout1 is active

1: PLL1 CPout1 is at TRI-STATE

5

4

PLL1_CP_TRI

PLL1_CP_POL

0

1

PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use

positive slope.

A positive slope VCXO increases output frequency with increasing voltage. A

negative slope VCXO decreases output frequency with increasing voltage.

0: Negative Slope VCO/VCXO

1: Positive Slope VCO/VCXO

This bit programs the PLL1 charge pump output current level.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

...

Gain

50 µA

150 µA

250 µA

350 µA

450 µA

...

3:0

PLL1_CP_GAIN

4

14 (0x0E)

15 (0x0F)

1450 µA

1550 µA

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8.6.2.7.6 PLL1_DLD_CNT

表8-64. PLL1_DLD_CNT[13:0]

MSB

LSB

0x15C[5:0] / PLL1_DLD_CNT[13:8]

0x15D[7:0] / PLL1_DLD_CNT[7:0]

This register contains the value of the PLL1 DLD counter.

表8-65. Registers 0x15C and 0x15D

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x15C

7:6

NA

0

Reserved

The reference and feedback of PLL1 must be within the

window of phase error as specified by PLL1_WND_SIZE for

this many phase detector cycles before PLL1 digital lock

detect is asserted.

PLL1_DLD

_CNT[13:8]

0x15C

0x15D

5:0

7:0

32

Field Value

0 (0x00)

Delay Value

Reserved

1 (0x01)

1

2 (0x02)

2

3

3 (0x03)

PLL1_DLD

_CNT[7:0]

0

...

16,382 (0x3FFE)

16,383 (0x3FFF)

16,382

16,383

8.6.2.7.7 HOLDOVER_EXIT_NADJ

表8-66. Register 0x15E

BIT

NAME

POR DEFAULT

DESCRIPTION

7:5

NA

0

Reserved

When holdover exists, PLL1 R counter and PLL1 N

counter are reset. HOLDOVER_EXIT_NADJ is a 2s

complement number which provides a relative timing

offset between PLL1 R and PLL1 N divider.

4:0

HOLDOVER_EXIT_NADJ

30

74

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8.6.2.7.8 PLL1_LD_MUX, PLL1_LD_TYPE

This register configures the PLL1 LD pin.

表8-67. Register 0x15F

BIT

NAME

POR DEFAULT

DESCRIPTION

This sets the output value of the Status_LD1 pin.

Field Value

0 (0x00)

MUX Value

Logic Low

1 (0x01)

PLL1 DLD

2 (0x02)

PLL2 DLD

3 (0x03)

PLL1 & PLL2 DLD

Holdover Status

DAC Locked

Reserved

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

SPI Readback

DAC Rail

7:3

PLL1_LD_MUX

1

8 (0x08)

9 (0x09)

DAC Low

10 (0x0A)

DAC High

11 (0x0B)

PLL1_N /2

12 (0x0C)

PLL1_N / 4

PLL2_N / 2

PLL2_N / 4

PLL1_R / 2

PLL1_R / 4

PLL2_R⁽¹⁾/ 2

PLL2_R / 4⁽¹⁾

13 (0x0D)

14 (0x0E)

15 (0x0F)

16 (0x10)

17 (0x11)

18 (0x12)

Sets the IO type of the Status_LD1 pin.

Field Value

TYPE

0 (0x00)

1 (0x01)

Input for External CLKin2 LOS

Input for External CLKin2 LOS (pullup)

Input for External CLKin2 LOS

(pulldown)

2:0

PLL1_LD_TYPE

6

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

Output (push-pull)

Output inverted (push-pull)

Reserved

Output (open-drain)

(1) Only valid when PLL2_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD).

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8.6.2.8 (0x160 - 0x16E) PLL2 Configuration

8.6.2.8.1 PLL2_R

表8-68. PLL2_R[11:0]

MSB

LSB

0x160[3:0] / PLL2_R[11:8]

0x161[7:0] / PLL2_R[7:0]

This register contains the value of the PLL2 R divider.

表8-69. Registers 0x160 and 0x161

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x160

7:4

NA

0

Reserved

Valid values for the PLL2 R divider.

Field Value

0 (0x00)

Divide Value

0x160

0x161

3:0

7:0

PLL2_R[11:8]

PLL2_R[7:0]

0

2

Not Valid

1 (0x01)

1

2

2 (0x02)

3 (0x03)

3

...

4,094 (0xFFE)

4,095 (0xFFF)

4,094

4,095

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8.6.2.8.2 PLL2_P, OSCin_FREQ, PLL2_REF_2X_EN

This register sets other PLL2 functions.

表8-70. Register 0x162

BIT

NAME

POR DEFAULT

DESCRIPTION

The PLL2 N Prescaler divides the output of the VCO as selected by

Mode_MUX1 and is connected to the PLL2 N divider.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Value

8

2

3

4

5

6

7

7:5

PLL2_P

2

The frequency of the PLL2 reference input to the PLL2 Phase Detector

(OSCIN_P/OSCIN_N pins) must be programmed to support proper operation

of the frequency calibration routine which locks the internal VCO to the target

frequency.

Field Value

0 (0x00)

OSCIN Frequency

0 to 63 MHz

4:2

OSCin_FREQ

3

1 (0x01)

>63 MHz to 127 MHz

>127 MHz to 255 MHz

Reserved

2 (0x02)

3 (0x03)

4 (0x04)

>255 MHz to 500 MHz

Reserved

5 (0x05) to 7(0x07)

1

0

NA

0

1

Reserved

Enabling the PLL2 reference frequency doubler allows for higher phase

detector frequencies on PLL2 than would normally be allowed with the given

VCXO frequency.

Higher phase detector frequencies reduces the PLL2 N values which makes

the design of wider loop bandwidth filters possible.

0: Doubler Disabled

PLL2_REF_2X_EN

1: Doubler Enabled

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8.6.2.8.3 PLL2_N_CAL

PLL2_N_CAL[17:0]

PLL2 never uses 0-delay during frequency calibration. These registers contain the value of the PLL2 N divider

used with PLL2 pre-scaler during calibration for cascaded 0-delay mode. Once calibration is complete, PLL2 will

use the PLL2_N value. Cascaded 0-delay mode occurs when PLL2_NCLK_MUX = 1.

表8-71. PLL2_N_CAL[17:0]

—

MSB

LSB

0x163[1:0] / PLL2_N_CAL[17:16]

0x164[7:0] / PLL2_N_CAL[15:8]

0x165[7:0] / PLL2_N_CAL[7:0]

表8-72. Registers 0x163, 0x164, and 0x165

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x163

7:2

NA

0

Reserved

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Divide Value

0x163

0x164

0x165

1:0

7:0

PLL2_N _CAL[17:16]

PLL2_N_CAL[15:8]

PLL2_N_CAL[7:0]

0

Not Valid

1

2

0

...

12

262,143 (0x3FFFF)

262,143

8.6.2.8.4 PLL2_N

This register disables frequency calibration and sets the PLL2 N divider value. Programming register 0x168

starts a VCO calibration routine if PLL2_FCAL_DIS = 0.

表8-73. PLL2_N[17:0]

—

MSB

LSB

0x166[1:0] / PLL2_N[17:16]

0x167[7:0] / PLL2_N[15:8]

0x168[7:0] / PLL2_N[7:0]

表8-74. Registers 0x166, 0x167, and 0x168

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x166

7:3

NA

0

Reserved

Setting this to 1 disables PLL2 frequency calibration on

programming of register 0x168

2

PLL2_FCAL_DIS

Field Value

0 (0x00)

Divide Value

0x166

0x167

0x168

1:0

PLL2_N[17:16]

PLL2_N[15:8]

PLL2_N[7:0]

0

Not Valid

1 (0x01)

1

7:0

2 (0x02)

2

...

12

262,143 (0x3FFFF)

262,143

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8.6.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI

This register controls the PLL2 phase detector.

表8-75. Register 0x169

BIT

NAME

POR DEFAULT

DESCRIPTION

7

NA

0

Reserved

PLL2_WND_SIZE sets the window size used for digital lock detect for PLL2. If

the phase error between the reference and feedback of PLL2 is less than

specified time, then the PLL2 lock counter increments.

Maximum Phase Detector

Field Value

Frequency / Window Size

6:5

PLL2_WND_SIZE

2

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Reserved

320 MHz / 1 ns

240 MHz / 1.8 ns

160 MHz / 2.6 ns

This bit programs the PLL2 charge pump output current level. The table below

also shows the impact of the PLL2 TRISTATE bit in conjunction with

PLL2_CP_GAIN.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

Reserved

1600 µA

4:3

PLL2_CP_GAIN

3

3200 µA

PLL2_CP_POL sets the charge pump polarity for PLL2. The internal VCO

requires the negative charge pump polarity to be selected. Many VCOs use

positive slope.

A positive slope VCO increases output frequency with increasing voltage. A

negative slope VCO decreases output frequency with increasing voltage.

2

PLL2_CP_POL

0

Field Value

Description

0

1

Negative Slope VCO/VCXO

Positive Slope VCO/VCXO

PLL2_CP_TRI TRI-STATEs the output of the PLL2 charge pump.

1

0

PLL2_CP_TRI

PLL2_DLD_EN

0

0: Disabled

1: TRI-STATE

PLL2 DLD circuitry is enabled when the PLL2 DLD is used to provide an output

to a lock detect status pin. PLL2_DLD_EN allows enabling the PLL2 DLD

circuitry without needing to provide PLL2 DLD to a status pin. This enables

PLL2 DLD status to be read back using SPI while allowing the Status pins to

be used for other purposes.

0: PLL2 DLD circuitry is on only of PLL2 DLD or PLL1 + PLL2 DLD signal is

output from a Status_LD_MUX.

1: PLL2 DLD circuitry is forced on.

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8.6.2.8.6 PLL2_DLD_CNT

表8-76. PLL2_DLD_CNT[13:0]

MSB

LSB

0x16A[5:0] / PLL2_DLD_CNT[13:8]

0x16B[7:0] / PLL2_DLD_CNT[7:0]

This register has the value of the PLL2 DLD counter.

表8-77. Registers 0x16A and 0x16B

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x16A

7

NA

0

Reserved

The reference and feedback of PLL2 must be within the

window of phase error as specified by PLL2_WND_SIZE for

PLL2_DLD_CNT cycles before PLL2 digital lock detect is

asserted.

PLL2_DLD

_CNT[13:8]

0x16A

0x16B

5:0

7:0

32

Field Value

0 (0x00)

Divide Value

Not Valid

1 (0x01)

1

2 (0x02)

2

3

3 (0x03)

PLL2_DLD_CNT

0

...

16,382 (0x3FFE)

16,383 (0x3FFF)

16,382

16,383

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8.6.2.8.7 PLL2_LD_MUX, PLL2_LD_TYPE

This register sets the output value of the Status_LD2 pin.

表8-78. Register 0x16E

BIT

NAME

POR DEFAULT

DESCRIPTION

This sets the output value of the Status_LD2 pin.

Field Value

0 (0x00)

MUX Value

Logic Low

1 (0x01)

PLL1 DLD

2 (0x02)

PLL2 DLD

3 (0x03)

PLL1 & PLL2 DLD

Holdover Status

DAC Locked

Reserved

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

SPI Readback

DAC Rail

7:3

PLL2_LD_MUX

0

8 (0x08)

9 (0x09)

DAC Low

10 (0x0A)

11 (0x0B)

DAC High

PLL1_N / 2

PLL1_N / 4

PLL2_N / 2

PLL2_N / 4

PLL1_R / 2

PLL1_R / 4

PLL2_R / 2⁽¹⁾

PLL2_R / 4⁽¹⁾

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

16 (0x10)

17 (0x11)

18 (0x12)

Sets the IO type of the Status_LD2 pin.

Field Value

0 (0x00)

TYPE

Reserved

1 (0x01)

Reserved

2:0

PLL2_LD_TYPE

6

2 (0x02)

Reserved

3 (0x03)

Output (push-pull)

4 (0x04)

5 (0x05)

6 (0x06)

Output inverted (push-pull)

Reserved

Output (open drain)

(1) Only valid when PLL1_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD).

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8.6.2.9 (0x16F - 0x555) Misc Registers

8.6.2.9.1 PLL2_PRE_PD, PLL2_PD, FIN0_PD

表8-79. Register 0x173

BIT

NAME

POR DEFAULT

DESCRIPTION

7

N/A

0

Reserved

Powerdown PLL2 prescaler

0: Normal Operation

1: Powerdown

6

5

PLL2_PRE_PD

PLL2_PD

1

Powerdown PLL2

0: Normal Operation

1: Powerdown

Powerdown FIN0

0: Normal Operation

1: Powerdown

4

FIN0_PD

N/A

1

0

3:0

Reserved

8.6.2.9.2 PLL1R_RST

Refer to PLL1 R Divider Synchronization for more information on synchronizing PLL1 R divider.

表8-80. Register 0x177

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

When set, PLL1 R divider will be held in reset. PLL1 will never lock with

PLL1R_RST = 1. This bit is used in when synchronizing the PLL1 R divider.

0: PLL1 R divider normal operation.

5

PLL1R_RST

NA

0

1: PLL1 R divider held in reset.

4:0

Reserved

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8.6.2.9.3 CLR_PLL1_LD_LOST, CLR_PLL2_LD_LOST

表8-81. Register 0x182

BIT

NAME

POR DEFAULT

DESCRIPTION

7:2

NA

0

Reserved

To reset RB_PLL1_LD_LOST, write CLR_PLL1_LD_LOST with 1 and then 0.

0: RB_PLL1_LD_LOST will be set on next falling PLL1 DLD edge.

1: RB_PLL1_LD_LOST is held clear (0). User must clear this bit to allow

RB_PLL1_LD_LOST to become set again.

1

0

CLR_PLL1_LD_LOST

CLR_PLL2_LD_LOST

0

To reset RB_PLL2_LD_LOST, write CLR_PLL2_LD_LOST with 1 and then 0.

0: RB_PLL2_LD_LOST will be set on next falling PLL2 DLD edge.

1: RB_PLL2_LD_LOST is held clear (0). User must clear this bit to allow

RB_PLL2_LD_LOST to become set again.

8.6.2.9.4 RB_PLL1_LD_LOST, RB_PLL1_LD, RB_PLL2_LD_LOST, RB_PLL2_LD

For PLL2 DLD read back to be valid, either PLL2 DLD or PLL1 + PLL2 DLD signal must be output from the

status pins, or PLL2_DLD_EN bit must be set = 1.

表8-82. Register 0x183

BIT

NAME

POR DEFAULT

DESCRIPTION

7:4

N/A

0

Reserved

This is set when PLL1 DLD edge falls. Does not set if cleared while PLL1 DLD

is low.

3

2

1

RB_PLL1_LD_LOST

RB_PLL1_LD

0

Read back 0: PLL1 DLD is low.

Read back 1: PLL1 DLD is high.

This is set when PLL2 DLD edge falls. Does not set if cleared while PLL2 DLD

is low.

RB_PLL2_LD_LOST

PLL1_LD_MUX or PLL2_LD_MUX must select setting 2 (PLL2 DLD) for valid

reading of this bit.

Read back 0: PLL2 DLD is low.

0

RB_PLL2_LD

0

Read back 1: PLL2 DLD is high.

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8.6.2.9.5 RB_DAC_VALUE (MSB), RB_CLKinX_SEL, RB_CLKinX_LOS

This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator. The 2 MSBs

are shared with the RB_DAC_VALUE. See the RB_DAC_VALUE section for more information.

表8-83. Register 0x184

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

RB_DAC_VALUE[9:8]

See the RB_DAC_VALUE section.

Read back 0: CLKin2 is not selected for input to PLL1.

Read back 1: CLKin2 is selected for input to PLL1.

5

4

RB_CLKin2_SEL

RB_CLKin1_SEL

Read back 0: CLKin1 is not selected for input to PLL1.

Read back 1: CLKin1 is selected for input to PLL1.

Read back 0: CLKin0 is not selected for input to PLL1.

Read back 1: CLKin0 is selected for input to PLL1.

3

2

1

RB_CLKin0_SEL

N/A

Read back 1: CLKin1 LOS is active.

Read back 0: CLKin1 LOS is not active.

RB_CLKin1_LOS

Read back 1: CLKin0 LOS is active.

Read back 0: CLKin0 LOS is not active.

0

RB_CLKin0_LOS

8.6.2.9.6 RB_DAC_VALUE

Contains the value of the DAC for user readback.

表8-84. RB_DAC_VALUE[9:0]

MSB

LSB

0x184 [7:6] / RB_DAC_VALUE[9:8]

0x185 [7:0] / RB_DAC_VALUE[7:0]

表8-85. Registers 0x184 and 0x185

REGISTER

BIT

NAME

POR DEFAULT

RB_DAC_

VALUE[9:8]

0x184

7:6

2

DAC value is 512 on power on reset, if PLL1 locks upon

power-up the DAC value will change.

RB_DAC_

VALUE[7:0]

0x185

7:0

0

8.6.2.9.7 RB_HOLDOVER

表8-86. Register 0x188

BIT

NAME

POR DEFAULT

DESCRIPTION

7:5

N/A

Reserved

Read back 0: Not in HOLDOVER.

Read back 1: In HOLDOVER.

4

RB_HOLDOVER

N/A

3:0

Reserved

8.6.2.9.8 SPI_LOCK

Prevents SPI registers from being written to, except for 0x555.

This register cannot be read back.

表8-87. Register 0x555

BIT

NAME

POR DEFAULT

DESCRIPTION

0: Registers unlocked.

1 to 255: Registers locked.

7:0

SPI_LOCK

0

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

Texas Instruments provides the TICSPRO software to assist with device setup, frequency divider calculations,

and general device programming as well as the PLLatinum™ simulation software for loop filter design and phase

noise/jitter simulation on ti.com.

9.1.1 Treatment of Unused Pins

Not all pins are needed for every application. In general, power down the unused feature in software. The

unused pin may be left floating or grounded through a 1-kΩ resistor.

表9-1. Treatment of Unused Pins

PINS

TREATMENT IF UNUSED

1 kΩto GND or float pin

CLKOUTx_P/CLKOUTx_N

RESET/GPO

SYNC/SYSREF_REQ

FIN0_P/FIN0_N

STATUS_LD1,STATUS_LD2

CPOUT1,CPOUT2

OSCOUT_P/CLKIN2_P

OSCOUT_N/CLKIN2_N

9.1.2 Frequency Planning and Spur Minimization

Frequency planning refers to strategically assigning frequencies to outputs for the purposes of spur minimization.

Spurs vary as a function of output frequency, output format, and output assignments. Spurs can be directly

coupling from one output to the next or be caused by a mixing product. For instance, if one output is at 3 GHz

and another output is at 750 MHz, one can see a 750 MHz-spur coupling through the 3-GHz output. In some

situations, it is also possible to have a spur that occurs at the greatest common divisor of the two frequencies

(250 MHz in this case). In either case, the choice of which outputs the 3-GHz and 750-MHz frequencies are

assigned to can have an impact on spurs.

表9-2. Factors Impacting Spurs

Factor

General Guidelines and Tips

Output Frequency

To a point, higher frequencies tend to couple stronger to other outputs, but bypassing impacts this.

Stronger signals and single-ended signals tend to couple stronger to other outputs. LVDS tends to couple

less than LVPECL as well. For LVCMOS, consider using both sides of the output with one side inverted to

the other (Norm/Inv) to minimize crosstalk.

Output Format

Outputs that are physically closer and that share the same power supply tend to have stronger crosstalk.

Outputs are grouped by supply in the following manner: Clock Group 0: (CLK0,CLK1,CLK12,CLK13),

Clock Group 1: (CLK2, CLK3), Clock Group 2 (CLK4, CLK5, CLK6, CLK7), Clock Group 3 (CLK8, CLK9,

CLK10, CLK11). Use frequency planning to minimize spur levels to the most critical outputs.

Frequency Assignment to

Output

(Frequency Planning)

Frequency planning involves trial and error, but there is some strategy in planning. Try to ensure that the same

frequencies are placed on outputs that have the strongest crosstalk and that different frequencies are placed on

outputs that have weaker crosstalk

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表9-3. Crosstalk Matrix

CLK0,CLK1

n/a

CLK2,CLK3

M

CLK4,CLK5

CLK6,CLK7

CLK8,CLK9

L

CLK10,CLK11

M

CLK12,CLK13

CLK0,

CLK1

L

M

n/a

H

L

H

CLK2,

CLK3

M

L

n/a

M

L

H

L

M

CLK4,

CLK5

CLK6,

CLK7

L

n/a

L

M

CLK8,

CLK9

L

n/a

H

M

CLK10,

CLK11

M

H

M

n/a

H

CLK12,

CLK13

M

n/a

L = Low Crosstalk, M = Medium Crosstalk, H = High Crosstalk

9.1.3 Digital Lock Detect Frequency Accuracy

The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A

window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback

signals of the PLL for each event to occur. When a PLL digital lock event occurs, the digital lock detect of the

PLL is asserted true. When the holdover exit event occurs, the device will exit holdover mode when

HOLDOVER_EXIT_MODE = 1 (Exit based on DLD).

表9-4. Digital Lock Detect Related Fields

EVENT

PLL

PLL1

WINDOW SIZE

LOCK COUNT

PLL1 Locked

PLL2 Locked

Holdover exit

PLL1_WND_SIZE

PLL2_WND_SIZE

PLL1_WND_SIZE

PLL1_DLD_CNT

PLL2_DLD_CNT

PLL2

PLL1

HOLDOVER_DLD_CNT

For a digital lock detect event to occur, there must be a lock count number of phase detector cycles of PLLX

during which the time and phase error of the PLLX_R reference and PLLX_N feedback signal edges are within

the user programmable window size. There must be at least one lock count phase detector event before a lock

event occurs, therefore a minimum digital lock event time can be calculated as lock count / f_PDXwhere X = 1 for

PLL1 or 2 for PLL2.

By using 方程式 4, values for a lock count and window size can be chosen to set the frequency accuracy

required by the system in ppm before the digital lock detect event occurs:

1e6 × PLLX_WND_SIZE × f_PDX

ppm =

PLLX_DLD_CNT

(4)

The effect of the lock count value is that it shortens the effective lock window size by dividing the window size by

lock count.

If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by window

size, then the lock count value is reset to 0.

9.1.3.1 Minimum Lock Time Calculation Example

To calculate the minimum PLL2 digital lock time given a PLL2 phase detector frequency of 40 MHz and

PLL2_DLD_CNT = 10,000. Then, the minimum lock time of PLL2 will be 10,000 / 40 MHz = 250 µs.

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9.1.4 Driving CLKIN AND OSCIN Inputs

9.1.4.1 Driving CLKIN and OSCIN PINS With a Differential Source

CLKin and OSCin pins can be driven by differential signals. TI recommends setting the input mode to bipolar

(CLKinX_BUF_TYPE = 0) when using differential reference clocks. The device internally biases the input pins so

the differential interface should be AC-coupled. The recommended circuits for driving the CLKin pins with either

LVDS or LVPECL are shown in 图9-1 and 图9-2.

CLKINx_P

0.1 µF

LVDS

Output

100 Trace

(Di eren al)

Input

CLKINx_N

0.1 µF

图9-1. CLKINx_P/CLKINx_N or OSCIN Termination for an LVDS Reference Clock Source

CLKINx_P

0.1 µF

LVPECL

Output

100 Trace

(Di eren al)

Input

CLKINx_N

0.1 µF

图9-2. CLKINx_P/CLKINx_N or OSCIN Termination for an LVPECL Reference Clock Source

Finally, a reference clock source that produces a differential sine wave output can drive the CLKIN pins using the

following circuit. Note: the signal level must conform to the requirements for the CLKIN pins listed in the

Electrical Characteristics table.

CLKINx_P

0.1 µF

100 Trace

(Di eren al)

Input

CLKINx_N

Di eren al

Sinewave Clock

0.1 µ F

图9-3. CLKINx_P/CLKINx_N or OSCIN Termination for a Differential Sinewave Reference Clock Source

9.1.4.2 Driving CLKIN Pins With a Single-Ended Source

The CLKIN and OSCIN pins can be driven using a single-ended reference clock source, for example, either a

sine wave source or an LVCMOS/LVTTL source. CLKIN supports both AC coupling or DC coupling. OSCin must

use AC coupling. In the case of the sine wave source that is expecting a 50-Ω load, TI recommends using AC

coupling as shown in 图9-4 with a 50-Ωtermination.

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备注

The signal level must conform to the requirements for the CLKin or OSCin pins listed in the Electrical

Characteristics table.

To support LOS functionality, CLKinX_BUF_TYPE must be set to MOS mode (CLKinX_BUF_TYPE =

1) when AC-coupled. When AC coupling, if the 100-Ω termination is placed on the IC side of the

blocking capacitors, then the LOS functionality will not be valid.

CLKINx_P

50

0.1 µF

Input

Clock Source

CLKINx_N

0.1 µ F

图9-4. CLKINx_P/CLKINx_N Single-Ended Termination

If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC

coupling may be used. If DC coupling is used, the CLKinX_BUF_TYPE should be set to MOS buffer mode

(CLKinX_BUF_TYPE = 1) and the voltage swing of the source must meet the specifications for DC-coupled,

MOS-mode clock inputs given in the Electrical Characteristics table. If AC coupling is used, the

CLKinX_BUF_TYPE should be set to the bipolar buffer mode (CLKinX_BUF_TYPE = 0). The voltage swing at

the input pins must meet the specifications for AC-coupled, bipolar mode clock inputs given in the Electrical

Characteristics table. In this case, some attenuation of the clock input level may be required. A simple resistive

divider circuit before the AC-coupling capacitor is sufficient.

CLKINx_P

50

0.1 µF

Input

LVCMOS/LVTTL

Clock Source

CLKINx_N

0.1 µF

图9-5. DC-Coupled LVCMOS/LVTTL Reference Clock

9.1.5 OSCin Doubler for Best Phase Noise Performance

PLL2 OSCin input path includes an on-chip Frequency Doubler. To have the best phase noise performance, TI

recommends to maximize the PLL2 phase detector frequency. For example, using 122.88-MHz VCXO, PLL2

phase detector frequency can be increased to 245.76 MHz by setting PLL2_REF_2X_EN. Doubler path is a high

performance path for OSCin clock. For configuration where doubler cannot be used, TI recommends to use

Doubler and PLL2_RDIV = 2. To have deterministic phase relationship between input clock and output clocks, 0-

delay modes should be used (nested 0-delay mode for dual loop configuration instead of cascaded 0-delay

mode).

9.1.6 Radiation Environments

9.1.6.1 Total Ionizing Dose

Radiation Hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level

specified in the ordering information. Testing and qualification of these product is done according to MIL-

STD-883, test method 1019.

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9.1.6.2 Single Event Effect

One-time single event effect (SEE), including single event latch-up (SEL) and single event functional interrupt

(SEFI) testing was performed according to EIA/JEDEC Standard, EIA/JEDEC57. A test report is available upon

request.

9.2 Typical Application

This design example highlights the available tools used to design loop filters and create a programming map.

CLKOUT10

VCXO

Mul ple “clean” clocks

at di erent and much

higher frequencies

LMX2615-SP

Recovered

CLKOUT11

PLL+VCO

“dirty” clock

or clean clock

CLKIN0

OSCOUT

CLKOUT8

CLKOUT9

FPGA

Backup

Reference

Clock

LMK04832-SEP

CLKIN1

CLKOUT4 &

CLKOUT6

CLKOUT5 &

CLKOUT7

CLKOUT0 &

CLKOUT2

CLKOUT12,

CLKOUT13

D_DA_AC_C

ADC12DJ3200

QML-SP

CLKOUT1 &

CLKOUT3

Serializer/

Deserializer

图9-6. Typical Application

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9.2.1 Design Requirements

Clocks outputs:

• 1x 122.88 MHz LVCMOS

• 1x 122.88 MHz HSDS

• 1x 245.76 MHz LVPECL

• 1x 983.04 MHz LVDS

• 1x 2949.12 MHz CML

For best performance, the highest possible phase detector frequency is used at PLL2. As such, a 122.88-MHz

VCXO is used. Assume that the 2949.12-MHz CML clock is the most performance critical one.

9.2.2 Detailed Design Procedure

TI has the TICSPRO and PLLatinum^™simulation tools that can be used to determine register values and design

the loop filter. CML and LVPECL output formats have the best noise floor, but consume more current, therefore it

is best to use these formats when noise floor matters. As for frequency planning, CLKOUT4 has the most critical

output, and this output has a strong interaction with the CLKOUT6. To avoid a strong interaction, the CLKOUT6

was not used in this example and a spur was added to the CLKOUT4. The 122.88-MHz HSDS clock could

potentially generate a lot of spurs and mixing products, so this HSDS clock was placed on the CLKOUT8 that

has the weakest interaction with the other channels.

9.2.2.1 Device Selection

Enter the required frequencies into the tools. In this design, VCO0 and VCO1 both meet the design

requirements. VCO0 offers a relatively improved VCO performance over VCO1. In this case, choose VCO0 for

improved RMS jitter in the 12-kHz to 20-MHz integration range.

9.2.2.1.1 Clock Architect

Under the advanced tab of the Clock Architect, filtering of specific parts can be done using regular expressions

in the Part Filter box. [LMK04832.*] will filter for only the LMK04832 device (without brackets). More detailed

filters can be given such as the entire part name LMK04832_VCO0 to force an LMK04832 using VCO0 solution

if one is available.

9.2.2.2 Device Configuration and Simulation

The tools automatically configure the simulation to meet the input and output frequency requirements given, and

make assumptions about other parameters to give some default simulations. However, the user may chose to

make adjustments for more accurate simulations to their application. For example:

• Entering the VCO Gain of the external VCXO or possible external VCO used device.

• Adjust the charge pump current to help with loop filter component selection. Lower charge pump currents

result in smaller components but may increase impacts of leakage and at the lowest values reduce PLL

phase noise performance.

• Clock Architect allows loading a custom phase noise plot for reference or VCXO block. Typically, a custom

phase noise plot is entered for CLKin to match the reference phase noise to device; a phase noise plot for the

VCXO can additionally be provided to match the performance of VCXO used. For improved accuracy in

simulation and optimum loop filter design, be sure to load these custom noise profiles for use in application.

• The PLLatinum^™Simulation tool can also be used to design and simulate a loop filter.

9.2.2.3 Device Setup

Frequency Planning

• Even clock outputs have the simplest output path and lowest noise floor, so they were chosen.

• CLKOUT4 is used so therefore CLKOUT6 & CLKOUT7 should either not be used or at least be assigned the

same frequency as CLKOUT4.

• CLKOUT8 is used, so therefore CLKOUT10 & CLKOUT11 should either not be used or at least be assigned

the same frequency as CLKOUT8.

Output Formats

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• CML and LVPECL are chosen for the 983.04 and 2949.12 MHz clocks for the lower noise floor

• CMOS is chosen for the 122.88 MHz clock for lower current consumption

Programming

• Using the clock design tools configuration the TICS Pro software is manually updated with this information to

meet the required application.

• For best performance the input and output drive level bits may be set. Best noise floor performance is

achieved with CLKout2_3_IDL = 1 and CLKout2_3_ODL = 1.

• The CLKoutX_Y_ODL bit has no impact on even clock outputs in high performance bypass mode.

9.2.3 Application Curve

-80

OSCOUT

CLKOUT8

CLKOUT0

-85

-90

-95

-100

-105

-110

-115

-120

-125

-130

-135

-140

-145

-150

-155

-160

-165

-170

CLKOUT2

CLKOUT4

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

1x10⁸

Offset (Hz)

图9-7. Offset vs Phase Noise

表9-5. Offset vs Phase Noise

Phase Noise (dBc/Hz)

Frequency

(MHz)

Jitter

(fs)

Output

Format

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

10 MHz

Floor

OSCOUT

CLKOUT8

122.88

LVCMOS

132.2

87.7

-111.8

-137.3

-148.3

-144.4

-154.0

-155.4

-157.2

-155.9

-156.0

HSDS

(8 mA)

122.88

245.76

983.04

2949.12

-111.7

-98.0

-92.7

-81.4

-134.7

-127.6

-115.9

-106.5

-146.4

-139.1

-128.2

-118.8

-162.7

-161.9

-157.4

-154.7

-162.8

-162.6

-159.4

-158.0

LVPECL

(2 Vpp)

CLKOUT0

CLKOUT2

CLKOUT4

70.0

67.1

65.4

-137.2

-125.7

-116.3

-154.1

-141.4

-132.0

LVPECL

(1.6 Vpp)

CML

(32 mA)

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9.3 Power Supply Recommendations

9.3.1 Current Consumption

Current consumption varies considerably with the number of outputs and output formats. This can be calculated

the TI TICSPro software.

9.3.2 Cold Sparing Considerations

图9-8 below demonstrates how this part can be used for cold sparing

VCC1 = 3.3V ± 0.3V

VCC2 = 0V

+

–

+

–

Output of LMK

Device configured

as CMOS

220 ꢀ

Unpowered LMK

Device

(acting as cold spare)

CLKINX or SYNC

Powered

LMK Device

CLKinX

图9-8. Cold Sparing Devices Setup

9.3.2.1 Damage Prevention Details to Unpowered Device

Setting two devices in a cold sparing setup leads to the unpowered device receiving DC-coupled LVCMOS

pulses on the CLKIN0 or SYNC inputs periodically throughout the lifetime of the unpowered device. The

cumulative lifetime limit for the unpowered device DC input current is 10 hours at maximum junction

temperature. Also, the device can remain within specifications for much longer than this limit if the typical cold-

spare junction temperature is lower than maximum junction temperature. However, by placing a 220-Ω in series

between the output of the poweredde to the inputs of the unpowered devP, even when connected to a 3.3-V or

3.6-V powered system, DC pulses from the powered device do not damage the unpowered device. DC-coupling

3.3V or 3.6-V I/O can occur without the transmitter for the SYNC signal failing high and destroying the receiver,

or any other circuitry within the unpowered device. Also, the 220-Ωresistor limits the current to about 7 mA, with

less than 12 mW dissipated onto the unpowered device.

Additionally, if CLKIN is damaged or fails short in one of the CLKIN paths with the 220-Ω resistor in series to

ground on the fault path, the current is limited. The initial damage won't short to the outputs of the transmitter

powered device, and therefore, no damage occurs to the rest of the system. The inputs and outputs of each

device have separate power supply pins that are not connected internally; therefore, if the unpowered device is

powered, no issues can occur to the outputs, even if one of the inputs is damaged over the lifetime of the

unpowered device.

When driving the CLKINx or OSCin inputs of an unpowered device, signal levels up to ± 400 mV can be AC-

coupled through 0.01 µF across the operating frequency range. Under these constraints, the magnitude of the

RMS currents injected into the CLKinX ESD structures is within acceptable power and current limits across the

full junction temperature range and won't cause long-term degradation of function. Larger amplitudes, higher

frequencies, or different coupling capacitors can be acceptable as long as the signal is AC-coupled and the

unpowered current limit of 7 mA going into or coming out of the CLKIN or OSCIN pins is observed.

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CLKIN or OSCIN

0.01 ꢀF

Unpowered

Device

± 400 mV square

wave source

图9-9. AC-Coupled ± 400 mV Signal Inputted to Unpowered Device

9.4 Layout

9.4.1 Layout Guidelines

In general, the following general guidelines are useful to keep in mind.

• GND pins on the outer perimeter of the package may be routed on the package back to the DAP

• Ensure the DAP on device is well-grounded with many vias.

• Use a low loss dielectric material, such as Rogers 4350B, for optimal output power.

• For power supply bypassing, isolate each clock group .

In addition to this, there are special considerations for the routing of the outputs. The outputs are divided in to

several output groups.

• Clock Group 0: CLKOUT0, CLKOUT1, CLKOUT12, CLKOUT13

• Clock Group 1: CLKOUT2, CLKOUT3

• Clock Group 2: CLKOUT4, CLKOUT5, CLKOUT6, CLKOUT7

• Clock Group 3: CLKOUT8, CLKOUT9, CLKOUT10, CLKOUT11

It is optimal to isolate the power supply pins for these clock group pins with a ferrite bead to crosstalk between

the outputs, especially if the output groups have different frequencies. If there is flexibility in planning which

frequencies go to which outputs, crosstalk can be minimized by putting different frequencies in different output

groups (as opposed to putting them in the same output group).

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9.4.2 Layout Example

图9-10. Top Layer

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Emi er resistors for

LVPECL can be put on

back side of the board.

Resistors, Ferrite

Beads, and

Capacitors on back

side of board

provide power

supply ltering

图9-11. Bottom Layer

9.4.3 Thermal Management

Power consumption can be high enough to require attention from thermal management. For reliability and

performance reasons, the die temperature should be limited to a maximum of 125°C. That is, as an estimate, T_A

(ambient temperature) plus device power consumption times R_θJAshould not exceed 125°C.

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10 Device and Documentation Support

10.1 Device Support

10.1.1 Development Support

10.1.1.1 Clock Architect

Part selection, loop filter design, simulation.

To run the online Clock Architect tool, go to www.ti.com/clockarchitect.

10.1.1.2 PLLatinum Simulation

Supports loop filter design and simulation. All simulation is for a single loop, to perform dual loop simulations, the

result of the first PLL simulation must be loaded as a reference to the second PLL simulation.

To download the PLLatinum™ simulation tool, go to www.ti.com/tool/PLLATINUMSIM-SW

10.1.1.3 TICS Pro

EVM programming software. Can also be used to generate register map for programming and calculate current

consumption estimate.

For TICS Pro, go to www.ti.com/tool/TICSPRO-SW

10.2 Documentation Support

10.2.1 Related Documentation

For related documentation, see the following:

• AN-912 Common Data Transmission Parameters and their Definitions (SNLA036)

10.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.5 Trademarks

PLLatinum^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This data is subject to change

without notice and revision of this document.

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PACKAGE OUTLINE

TM

PAP0064E

PowerPAD TQFP - 1.2 mm max height

SCALE 1.300

PLASTIC QUAD FLATPACK

10.2

9.8

B

NOTE 3

64

49

PIN 1 ID

1

48

10.2

9.8

12.2

TYP

11.8

NOTE 3

16

33

17

32

A

0.27

64X

60X 0.5

0.17

0.08

C A B

4X 7.5

C

SEATING PLANE

1.2 MAX

(0.127)

TYP

SEE DETAIL A

17

32

0.25

GAGE PLANE

(1)

33

16

0.15

0.05

0.08 C

0 -7

0.75

0.45

65

6.08

4.67

DETAIL A

A

17

TYPICAL

1

48

49

64

4228332/A 01/2022

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs.

4. Strap features may not be present.

5. Reference JEDEC registration MS-026.

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EXAMPLE BOARD LAYOUT

TM

PAP0064E

PowerPAD TQFP - 1.2 mm max height

PLASTIC QUAD FLATPACK

(

8)

NOTE 8

(

6.08)

SYMM

SOLDER MASK

49

64

DEFINED PAD

64X (1.5)

(R0.05)

TYP

1

48

64X (0.3)

65

(11.4)

SYMM

(1.3 TYP)

60X (0.5)

33

16

(

0.2) TYP

VIA

METAL COVERED

BY SOLDER MASK

17

32

SEE DETAILS

(1.3 TYP)

(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:6X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4228332/A 01/2022

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,

Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,

plugged or tented.

10. Size of metal pad may vary due to creepage requirement.

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EXAMPLE STENCIL DESIGN

TM

PAP0064E

PowerPAD TQFP - 1.2 mm max height

PLASTIC QUAD FLATPACK

(

6.08)

BASED ON 0.125

THICK STENCIL

SYMM

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

64

49

64X (1.5)

1

48

64X (0.3)

(R0.05) TYP

SYMM

65

(11.4)

60X (0.5)

33

16

METAL COVERED

BY SOLDER MASK

17

32

(11.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:6X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

6.80 X 6.80

6.08 X 6.08 (SHOWN)

5.55 X 5.55

0.125

0.15

0.175

5.14 X 5.14

4228332/A 01/2022

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

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型号：	V62P22612-01XE
厂家：	TEXAS INSTRUMENTS
描述：	耐辐射且符合 JESD204C 标准的 30krad 超低噪声 3.2GHz、15 路输出时钟抖动清除器 \| PAP \| 64 时钟
文件：	总103页 (文件大小：2944K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

V62P22612-01XE [TI]

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