VCA8617_14 [TI]
8-Channel VARIABLE GAIN AMPLIFIER;
| 型号： | VCA8617_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Channel VARIABLE GAIN AMPLIFIER 放大器 |
| 文件： | 总35页 (文件大小：725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VCA8617
www.ti.com
SBOS308F –AUGUST 2004–REVISED NOVEMBER 2009
8-Channel VARIABLE GAIN AMPLIFIER
Check for Samples: VCA8617
1
FEATURES
DESCRIPTION
23
•
3V OPERATION
The VCA8617 is an 8-channel variable gain amplifier
ideally suited to portable ultrasound applications.
Excellent dynamic performance enables use in
low-power, high-performance portable applications.
Each channel consists of a 20dB gain Low-Noise
pre-Amplifier (LNA) and a Variable Gain Amplifier
(VGA). The differential outputs of the LNA can be
switched through the 8x10 cross-point switch, which
is programmable through the serial interface input
port.
•
LOW INPUT NOISE:
–
1.05nV/√Hz at fIN = 5MHz
EXTREMELY LOW POWER OPERATION:
103mW/CHANNEL
•
•
–
INTEGRATED LOW-PASS, ANTI-ALIASING
BUTTERWORTH FILTER
–
14.5MHz BANDWIDTH
•
•
•
•
•
INTEGRATED INPUT CLAMP DIODES
DIFFERENTIAL OUTPUT
The output of the LNA is fed directly into the VGA
stage. The VGA consists of two parts,
Voltage-Controlled Attenuator (VCA) and
a
a
INTEGRATED INPUT LNA
Programmable Gain Amplifier (PGA). The gain and
gain range of the PGA can be digitally configured
separately. The gain of the PGA can vary between
four discrete settings of 25dB, 30dB, 35dB, and
40dB. The VCA has four programmable maximum
attenuation settings: 29dB, 33dB, 36.5dB, and 40dB.
Also, the VCA can be continuously varied by a control
voltage from 0dB to a maximum of 29dB, 33dB,
36.5dB, and 40dB.
READABLE CONTROL REGISTERS
INTEGRATED CONTINUOUS WAVE (CW)
PROCESSOR
The output of the PGA feeds directly into an
integrated low-pass filter.
VCA8617
5x8
CW Processor
(8 x 10)
CW(0-9)
DOUT
FIFO
10
DIN
PG
Serial
CLK
CS
Interface
ATN
Analog
Control
VCNTRL
OUT1
OUT1
2-Pole
Filter
IN1
LNA
VCA
PGA
·
·
·
·
·
·
VLNA
OUT8
OUT8
2-Pole
Filter
IN8
LNA
VCA
PGA
VLNA
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2009, Texas Instruments Incorporated
VCA8617
SBOS308F –AUGUST 2004–REVISED NOVEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
VCA8617PAGT
VCA8617PAGR
Tape and Reel, 250
Tape and Reel, 1500
VCA8617
TQFP-64
PAG
−40°C to +85°C
VCA8617PAG
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range unless otherwise noted.
+AVDD
+3.6V
Analog Input
−0.3V to +AVDD + 0.3V
−0.3V to +AVDD + 0.3V
+100°C
Logic Input
Case Temperature
Junction Temperature
Storage Temperature
Thermal Resistance, Junction-to-Ambient (θ JA
+150°C
+150°C
)
66.6°C/W
Thermal Resistance, Junction-to-Case (θ JC
)
4.3°C/W
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2
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SBOS308F –AUGUST 2004–REVISED NOVEMBER 2009
ELECTRICAL CHARACTERISTICS: AVDD = DVDD = 3V
At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is
single-ended; pre-amp gain is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential,
unless otherwise noted.
VCA8617
PARAMETER
CONDITIONS
fIN = 5MHz
MIN
TYP
1.05
1.15
MAX
UNIT
Input Voltage Noise (TGC, Full Signal Chain)
Input Voltage Noise (CW)
PREAMPLIFIER (LNA)
Input Resistance
nV/√Hz
nV/√Hz
fIN = 5MHz
4.5
52
1
kΩ
pF
Input Capacitance
Input Bias Current
nA
Maximum Input Voltage(1)
Output Swing (Differential)
Bandwidth
200
2
mVPP
VPP
MHz
dB
100
20
1.4
Gain
Input Common-Mode Voltage
ACCURACY
V
Gain Slope
0.2V − 1.7V, VCNTRL
0.2V − 1.7V, VCNTRL
Differential
18
dB/V
dB
Gain Error
1.7
Output Offset Voltage
GAIN CONTROL INTERFACE
Input Voltage (VCACNTRL) Range
Input Resistance
0.65
mV
0 to 2.0
V
1
MΩ
μs
Response Time
40dB Gain Change, PG = 11
0.2
POWER SUPPLY
Specified Operating Range
Power-Down Delay
2.85
3.0
5
3.15
950
V
μs
Power-Up Delay
100
825
9
μs
Power Dissipation (TGC Mode)
Power-Down
Operating All Channels
mW
mW
PROGRAMMABLE VGA AND LOW-PASS FILTER
−3dB Cutoff (low-pass)
−3dB Cutoff (high-pass)
Slew Rate
14.5
400
300
10
MHz
kHz
V/µs
Ω
Output Impedance
Crosstalk
49
dB
Output Common-Mode Voltage
Output Swing (Differential)(2)
3rd-Harmonic Distortion
2nd-Harmonic Distortion
Group Delay Variation
CONTINUOUS WAVE PROCESSOR
V/I Converter Transconductance
Output Common-Mode Voltage
Maximum Output Swing
1.5
V
2
VPP
dB
–65
–60
±3
–50
–50
dB
ns
17
20
1.4
3.4
23
mA/V
V
mAPP
(1) Under conditions when input signal is within linear range of LNA.
(2) Under conditions when signal is within linear range of output amplifier.
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ELECTRICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is
single-ended; pre-amp gain is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential,
unless otherwise noted.
VCA8617
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUTS
VIN LOW (input low voltage)
VIN HIGH (input high voltage)
Input Current
0
0.6
DVDD
±1
V
2.1
V
µA
pF
Hz
Input Pin Capacitance
Clock Input Frequency
5
10k
25M
4
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SBOS308F –AUGUST 2004–REVISED NOVEMBER 2009
Top View
TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
IN6
AGND
IN5
1
2
48 OUT8
47 OUT8
46 OUT7
45 OUT7
44 OUT6
43 OUT6
42 OUT5
41 OUT5
40 OUT4
39 OUT4
38 OUT3
37 OUT3
36 OUT2
35 OUT2
34 OUT1
33 OUT1
3
AGND
DVDD
DGND
DOUT
CLK
4
5
6
7
8
VCA8617
DIN
9
CS
10
11
12
13
14
15
16
DGND
DVDD
AGND
IN4
AGND
IN3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN DESCRIPTIONS
PIN
DESIGNATOR
DVDD
DESCRIPTION
5, 12
Digital Supplies
2, 4, 13, 15, 17, 19, 27, 50, 54, 62, 64
AGND
IN(1−8)
CW(0−9)
VLNA
Analog Ground
1, 3, 14, 16, 18, 20, 61, 63
Single-Ended LNA Inputs
Continuous Wave Outputs
22−26, 55−59
51
Reference Voltage for LNA−internally generated; requires external bypass cap.
29
VFIL
Reference Voltage for Output Filter−internally generated; requires external bypass cap.
30
VCM
Common-Mode Voltage−internally generated; requires external bypass cap.
34, 36, 38, 40, 42, 44, 46, 48
OUT(1−8)
OUT(1−8)
VCNTRL
DIN
Positive Polarity PGA Outputs
Negative Polarity PGA Outputs
Attenuator Control Input
33, 35, 37, 39, 41, 43, 45, 47
52
9
Serial Data Input Pin
10
CS
Serial Data Chip Select
8
CLK
Serial Data Input Clock
7
DOUT
Serial Data Output Pin
21, 28, 53, 60
AVDD
Analog Supplies
6, 11
49
DGND
VREF
Digital Ground
Reference Voltage for Attenuator−internally generated; requires external bypass cap.
Reference Power Supply
32
VDDR
31
GNDR
Reference Ground
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INPUT REGISTER BIT MAPS
Table 1. Byte 1—Control Byte Register Map
BIT #
LSB
1
NAME
1
DESCRIPTION
Start bit; always a ‘1’—40-bit countdown starts upon first ‘1’ after chip select.
W/R
1 = Write, 0 = Read—Read prevents latching of DATA only—Control register remains
latched with existing data.
2
PWR
Power-Down control bit (all channels); 1 = Power-Down Mode Enabled (default),
0 = Normal Operation.
3
4
A0
A1
Attenuator control bit (ATN).
Attenuator control bit (ATN).
5
Mode
PG0
PG1
1 = TGC Control mode (CW powered down), 0 = Doppler mode (TGC powered down)
LSB of PGA Gain Control
6
MSB
MSB of PGA Gain Control
Table 2. Byte 2—First Data Byte
BIT #
NAME
DESCRIPTION
LSB
Data 1:0
Data 1:1
Data 1:2
Data 1:3
Data 2:0
Data 2:1
Data 2:2
Data 2:3
Channel 1, LSB of Matrix Control
Channel 1, Matrix Control
Channel 1, Matrix Control
Channel 1, MSB of Matrix Control
Channel 2, LSB of Matrix Control
Channel 2, Matrix Control
Channel 2, Matrix Control
Channel 2, MSB of Matrix Control
1
2
3
4
5
6
MSB
Table 3. Byte 3—Second Data Byte
BIT #
NAME
DESCRIPTION
LSB
Data 3:0
Data 3:1
Data 3:2
Data 3:3
Data 4:0
Data 4:1
Data 4:2
Data 4:3
Channel 3, LSB of Matrix Control
Channel 3, Matrix Control
Channel 3, Matrix Control
Channel 3, MSB of Matrix Control
Channel 4, LSB of Matrix Control
Channel 4, Matrix Control
Channel 4, Matrix Control
Channel 4, MSB of Matrix Control
1
2
3
4
5
6
MSB
6
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SBOS308F –AUGUST 2004–REVISED NOVEMBER 2009
Table 4. Byte 4—Third Data Byte
BIT #
NAME
DESCRIPTION
LSB
Data 5:0
Data 5:1
Data 5:2
Data 5:3
Data 6:0
Data 6:1
Data 6:2
Data 6:3
Channel 5, LSB of Matrix Control
Channel 5, Matrix Control
Channel 5, Matrix Control
Channel 5, MSB of Matrix Control
Channel 6, LSB of Matrix Control
Channel 6, Matrix Control
Channel 6, Matrix Control
Channel 6, MSB of Matrix Control
1
2
3
4
5
6
MSB
Table 5. Byte 5—Fourth Data Byte
BIT #
NAME
DESCRIPTION
LSB
Data 7:0
Data 7:1
Data 7:2
Data 7:3
Data 8:0
Data 8:1
Data 8:2
Data 8:3
Channel 7, LSB of Matrix Control
Channel 7, Matrix Control
Channel 7, Matrix Control
Channel 7, MSB of Matrix Control
Channel 8, LSB of Matrix Control
Channel 8, Matrix Control
Channel 8, Matrix Control
Channel 8, MSB of Matrix Control
1
2
3
4
5
6
MSB
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WRITE/READ TIMING
Generally follows SPI Timing Specification:
•
•
•
•
•
All writes and reads are 40 bits at a time. Each byte consists of 8 bits;
Separate write and read data lines;
Reads will follow the same bit stream pattern seen in the write cycle;
Reads will extract data from the FIFO, not the latched register;
DOUT data is continuously available and need not be enabled with a read cycle. Selecting a read cycle in the
control register only prevents latching of data. The control register remains latched.
WRITE CYCLE TIMING
t4
t7
CS
t2
t3
CLK
t5
t6
t1
DIN
LSB
1
2
3
4
5
6
MSB
NOTE: It is highly recommended that the clock be turned off after the required data has been programmed into the VCA8617.
SERIAL PORT TIMING TABLE
Chip Select (CS) must be held low (active LOW) during transfer. CS can be held permanently low.
PARAMETER
DESCRIPTION
MIN
40
20
20
10
5
TYP
MAX
UNITS
ns
t1
t2
t3
t4
t5
t6
t7
Serial CLK Period
Serial CLK HIGH Time
ns
Serial CLK LOW Time
ns
CS Falling Edge to Serial CLK Falling Edge
Data Setup Time
ns
ns
Data Hold Time
5
ns
Serial CLK Falling Edge to CS Rising Edge
10
ns
8
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SBOS308F –AUGUST 2004–REVISED NOVEMBER 2009
DATA SHIFT SEQUENCE
Shift Direction
DIN
MSB
MSB
MSB
MSB
MSB
6
6
6
6
6
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
LSB
LSB
LSB
LSB
LSB
DOUT
Table 6. Maximum Attenuation
Table 7. PGA Gain Settings
A1, A0
0, 0
MAXIMUM ATTENUATION
PG1, PG0
0, 0
PGA GAIN
25dB
29dB
33dB
0, 1
0, 1
30dB
1, 0
36.5dB
40dB
1, 0
35dB
1, 1
1, 1
40dB
Table 8. CW Coding for Each Channel
CW CODING
CHANNEL
(MSB, LSB)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CHANNEL DIRECTED TO:
Output 0
0
1
Output 1
2
Output 2
3
Output 3
4
Output 4
5
Output 5
6
Output 6
7
Output 7
8
Output 8
9
Output 9
10
11
12
13
14
15
Channel tied to +V (internal)
Channel tied to +V (internal)
Channel tied to +V (internal)
Channel tied to +V (internal)
Channel tied to +V (internal)
Channel tied to +V (internal)
Applies to bytes 2 through 5.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
GAIN vs VCNTRL
(PG = 00, 25dB)
GAIN vs VCNTRL
(PG = 01, 30dB)
60
55
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
ATN = 00
ATN = 00
ATN = 01
ATN = 01
ATN = 11
ATN = 10
ATN = 11
ATN = 10
0
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
VCNTRL (V)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
VCNTRL (V)
Figure 1.
Figure 2.
GAIN vs VCNTRL
(PG = 10, 35dB)
GAIN vs VCNTRL
(PG = 11, 40dB)
60
55
50
45
40
35
30
25
20
15
10
5
65
60
55
50
45
40
35
30
25
20
15
10
5
ATN = 00
ATN = 00
ATN = 01
ATN = 01
ATN = 11
ATN = 11
ATN = 10
ATN = 10
0
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
VCNTRL (V)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
VCNTRL (V)
Figure 3.
Figure 4.
10
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
GAIN ERROR vs VCNTRL
(PG = 00)
GAIN ERROR vs VCNTRL
(PG = 01)
2.0
1.5
2.0
1.5
ATN = 01
ATN = 00
1.0
1.0
ATN = 01
0.5
0.5
ATN = 00
0
0
ATN = 10
ATN = 11
−0.5
−1.0
−1.5
−2.0
−0.5
−1.0
−1.5
−2.0
ATN = 10
ATN = 11
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
VCNTRL (V)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
VCNTRL (V)
Figure 5.
Figure 6.
GAIN ERROR vs VCNTRL
(PG = 10)
GAIN ERROR vs VCNTRL
(PG = 11)
2.0
1.5
2.0
1.5
ATN = 01
ATN = 00
1.0
1.0
ATN = 01
ATN = 00
0.5
0.5
0
0
−0.5
−1.0
−1.5
−2.0
−0.5
−1.0
−1.5
−2.0
ATN = 11
ATN = 10
ATN = 11
ATN = 10
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
VCNTRL (V)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
VCNTRL (V)
Figure 7.
Figure 8.
GAIN ERROR vs VCNTRL vs FREQUENCY
GAIN ERROR vs VCNTRLvs TEMPERATURE
2.0
1.5
2.0
1.8
10MHz
1.6
1.4
1.0
1.2
1.0
5MHz
2MHz
0.5
+85°C
0.8
0.6
0
0.4
0.2
+25°C
−0.5
−1.0
−1.5
−2.0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-40°C
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
VCNTRL (V)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
VCNTRL (V)
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
TIME GAIN CONTROL (TGC) CURRENT
vs TEMPERATURE
CONTINUOUS WAVE (CW) CURRENT
vs TEMPERATURE
285
284
283
282
281
280
279
278
277
276
275
274
273
272
271
270
269
268
220
218
216
214
212
210
208
206
204
202
200
198
196
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
Temperature (°C)
Temperature (°C)
Figure 11.
Figure 12.
GAIN MATCH
GAIN MATCH
(VCNTRL = 0.2V)
(VCNTRL = 1.7V)
140
120
100
80
140
120
100
80
60
60
40
40
20
20
0
0
Delta Gain (dB)
Delta Gain (dB)
Figure 13.
Figure 14.
12
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
GAIN vs FREQUENCY
CW ACCURACY
(ATN = 00, VCNTRL = 0.2V)
900
800
700
600
500
400
300
200
100
0
50
45
40
35
30
25
20
15
10
5
PG = 11
PG = 10
PG = 01
PG = 00
0
−5
−10
−15
0.1
1
10
100
Frequency (MHz)
Transconductance (mA/V)
Figure 15.
Figure 16.
GAIN vs FREQUENCY
(ATN = 00, VCNTRL = 1.7V)
OUTPUT-REFERRED NOISE vs VCNTRL
(ATN = 00, fIN = 2MHz)
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
65
60
55
50
45
40
35
30
25
20
PG = 11
PG = 11
PG = 10
PG = 10
PG = 01
PG = 01
PG = 00
PG = 00
1.8 2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.1
1
10
100
VCNTRL (V)
Frequency (MHz)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
OUTPUT-REFERRED NOISE vs VCNTRL
(ATN = 00, fIN = 5MHz)
INPUT-REFERRED NOISE vs VCNTRL
(ATN = 00, fIN = 2MHz)
20
18
16
14
12
10
8
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
PG = 00
PG = 11
PG = 11
PG = 10
PG = 01
PG = 01
6
PG = 10
4
2
PG = 00
1.8 2.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VCNTRL (V)
VCNTRL (V)
Figure 19.
Figure 20.
INPUT-REFERRED NOISE vs VCNTRL
(ATN = 00, fIN = 5MHz)
NOISE FIGURE vs VCNTRL
(ATN = 00, fIN = 2MHz)
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
30
25
20
15
10
5
PG = 00
PG = 00
PG = 11
PG = 01
PG = 11
PG = 10
PG = 01
PG = 10
0.6
0
0
0.2
0.4
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VCNTRL (V)
VCNTRL (V)
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
NOISE FIGURE vs VCNTRL
(ATN = 00, fIN = 5MHz)
OUTPUT-REFERRED NOISE vs VCNTRL
(ATN = 11, fIN = 2MHz)
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
30
25
20
15
10
5
PG = 00
PG = 11
PG = 01
PG = 11
PG = 10
PG = 10
PG = 01
PG = 00
1.8 2.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VCNTRL (V)
VCNTRL (V)
Figure 23.
Figure 24.
OUTPUT-REFERRED NOISE vs VCNTRL
(ATN = 11, fIN = 5MHz)
INPUT-REFERRED NOISE vs VCNTRL
(ATN = 11, fIN = 2MHz)
1100
1000
900
800
700
600
500
400
300
200
100
0
80
70
60
50
40
30
20
10
0
PG = 00
PG = 01
PG = 11
PG = 10
PG = 01
PG = 00
PG = 11
PG = 10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VCNTRL (V)
VCNTRL (V)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
INPUT-REFERRED NOISE vs VCNTRL
(ATN = 11, fIN = 5MHz)
NOISE FIGURE vs VCNTRL
(ATN = 11, fIN = 2MHz)
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
PG = 00
PG = 01
PG = 10
PG = 00
PG = 01
PG = 11
PG = 11
PG = 10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VCNTRL (V)
VCNTRL (V)
Figure 27.
Figure 28.
NOISE FIGURE vs VCNTRL
(ATN = 11, fIN = 5MHz)
INPUT-REFERRED NOISE
(2MHz, 2V VCNTRL
)
40
35
30
25
20
15
10
5
1.25
1.20
1.15
1.10
1.05
1.00
AT00
AT11
PG = 00
PG = 01
PG = 11
PG = 10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
PG 00
PG 01
PG 10
PG 11
VCNTRL (V)
Gain Setting
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
INPUT-REFERRED NOISE
(5MHz, 2V VCNTRL
INPUT-REFERRED NOISE
(CW Output)
)
2.00
1.90
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
1.10
1.05
1.00
AT00
AT11
1
2
3
4
5
PG 00
PG 01
PG 10
PG 11
Frequency (MHz)
Gain Setting
Figure 31.
Figure 32.
DISTORTION vs FREQUENCY
DISTORTION vs FREQUENCY
(ATN = 00, PG = 00, VCNTL = 2.0V)
(ATN = 00, PG = 01, VCNTL = 2.0V)
−30
−35
−40
−45
−50
−55
−60
−65
−70
−75
−80
−30
−35
−40
−45
−50
−55
−60
−65
−70
−75
−80
2nd−Harmonic
3rd−Harmonic
2nd−Harmonic
3rd−Harmonic
1
10
1
10
Frequency (MHz)
Frequency (MHz)
Figure 33.
Figure 34.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
DISTORTION vs FREQUENCY
DISTORTION vs FREQUENCY
(ATN = 00, PG = 10, VCNTL = 2.0V)
(ATN = 00, PG = 11, VCNTL = 2.0V)
−30
−35
−40
−45
−50
−55
−60
−65
−70
−75
−80
−30
−35
−40
−45
−50
−55
−60
−65
−70
−75
−80
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
3rd−Harmonic
1
10
1
10
Frequency (MHz)
Frequency (MHz)
Figure 35.
Figure 36.
DISTORTION vs VCNTRL
DISTORTION vs VCNTRL
(ATN = 00, PG = 10, fIN = 2MHz, 750mVPP
)
(ATN = 01, PG = 10, fIN = 2MHz, 750mVPP)
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
2nd-Harmonic
3rd-Harmonic
2nd-Harmonic
3rd-Harmonic
1.7
0.2
0.5
0.8
1.1
1.4
1.7
2.0
0.2
0.5
0.8
1.1
1.4
2.0
VCNTRL (V)
VCNTRL (V)
Figure 37.
Figure 38.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
DISTORTION vs VCNTRL
DISTORTION vs VCNTRL
(ATN = 10, PG = 10, fIN = 2MHz, 750mVPP
)
(ATN = 11, PG = 10, fIN = 2MHz, 750mVPP)
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
Under this test condition, at lower VCA
control voltage, the LNA is overloaded.
2nd-Harmonic
2nd-Harmonic
3rd-Harmonic
3rd-Harmonic
0.2
0.5
0.8
1.1
1.4
1.7
2.0
VCNTRL (V)
VCNTRL (V)
Figure 39.
Figure 40.
DISTORTION vs VCNTRL
DISTORTION vs VCNTRL
(ATN = 00, PG = 00, 500mVPP, 2nd-Harmonic)
(ATN = 00, PG = 01, 500mVPP, 2nd-Harmonic)
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
10MHz
10MHz
5MHz
5MHz
2MHz
2MHz
1MHz
1MHz
VCNTRL (V)
VCNTRL (V)
Figure 41.
Figure 42.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
DISTORTION vs VCNTRL
DISTORTION vs VCNTRL
(ATN = 00, PG = 10, 500mVPP, 2nd-Harmonic)
(ATN = 00, PG = 10, 500mVPP, 2nd-Harmonic)
30
30
35
40
45
50
55
60
65
70
75
80
35
40
45
50
55
60
65
70
75
80
10MHz
10MHz
5MHz
5MHz
2MHz
2MHz
1MHz
1MHz
VCNTRL (V)
VCNTRL (V)
Figure 43.
Figure 44.
DISTORTION vs VCNTRL
DISTORTION vs VCNTRL
(ATN = 00, PG = 00, 500mVPP, 3rd-Harmonic)
(ATN = 00, PG = 01, 500mVPP, 3rd-Harmonic)
−30
−35
−40
−45
−50
−55
−60
−65
−70
−75
−80
−30
−35
−40
−45
−50
−55
−60
−65
−70
−75
−80
2MHz
10MHz
5MHz
10MHz
5MHz
1MHz
2MHz
1MHz
VCNTRL (V)
VCNTRL (V)
Figure 45.
Figure 46.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
DISTORTION vs VCNTRL
DISTORTION vs VCNTRL
(ATN = 00, PG = 10, 500mVPP, 3rd-Harmonic)
(ATN = 00, PG = 11, 500mVPP, 3rd-Harmonic)
30
35
40
45
50
55
60
65
70
75
80
30
35
40
45
50
55
60
65
70
75
80
10MHz
10MHz
5MHz
5MHz
2MHz
2MHz
1MHz
1MHz
VCNTRL (V)
VCNTRL (V) )
Figure 47.
Figure 48.
CROSSTALK vs VCNTRL
CROSSTALK vs VCNTRL
(ATN = 00, fIN = 2MHz, CH4 to CH5)
(ATN = 00, fIN = 5MHz, CH4 to CH5)
−30
−35
−40
−45
−50
−55
−60
−65
−70
−30
−35
−40
−45
−50
−55
−60
−65
−70
PG10
PG11
PG10
PG11
PG = 00
PG = 01
PG = 01
PG = 00
VCNTRL (V)
VCNTRL (V)
Figure 49.
Figure 50.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
CROSSTALK vs VCNTRL
CROSSTALK to VCNTRL
(ATN = 00, fIN = 10MHz, CH4 to CH5)
(ATN = 11, PG = 11, CH4 to CH5)
−30
−35
−40
−45
−50
−55
−60
−65
−70
−30
−35
−40
−45
−50
−55
−60
−65
−70
PG10
PG11
10MHz
5MHz
PG = 00
PG = 01
2MHz
VCNTRL (V)
VCNTRL (V)
Figure 51.
Figure 52.
CROSSTALK to VCNTRL; CH1 vs CHn
(at 5MHz, AT = 00, PG = 00)
CROSSTALK to VCNTRL; CH1 vs CHn
(at 5MHz, AT = 11, PG = 00)
30
35
40
45
50
55
60
30
35
40
45
50
55
60
1-2
1-3
1-4
1-2
1-3
1-4
1-6
1-5
1-5
1-7
1-6 1-7
1-8
1-8
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VCNTRL (V)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VCNTRL (V)
Figure 53.
Figure 54.
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TYPICAL CHARACTERISTICS: AVDD = DVDD = 3V (continued)
At TA = +25°C, load resistance = 1kΩ on each output to ground; the input to the preamp (LNA) is single-ended; pre-amp gain
is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted.
CROSSTALK to VCNTRL; CH1 vs CHn
(at 5MHz, AT = 00, PG = 11)
CROSSTALK to VCNTRL; CH1 vs CHn
(at 5MHz, AT = 11, PG = 11)
30
35
40
45
50
55
60
30
35
40
45
50
55
60
1-2
1-3
1-4
1-8
1-2
1-4
1-3
1-5
1-6
1-6
1-7
1-7
1-5
1-8
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VCNTRL (V)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VCNTRL (V)
Figure 55.
Figure 56.
INPUT IMPEDANCE
INPUT IMPEDANCE
0
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
−
10
20
30
40
50
60
70
80
−
−
−
−
−
−
−
0
−90
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
Figure 57.
Figure 58.
OVERLOAD RECOVERY vs TIME
(ATN = 00, PG = 00, VCNTRL = 1V)
OVERLOAD RECOVERY vs TIME
(ATN = 00, PG = 01, VCNTRL = 2V)
Output
(2V/div)
Output
(2V/div)
The signal is greater than 2VPP input, so the LNA is
severely overloaded. Overload recovery time is 528ns.
The signal is greater than 40mVPP input, so the LNA is in the linear region
and the output amplifier is overloaded. Overload recovery time is 400ns.
Input
(1V/div)
Input
(20mV/div)
Time (400ns/div)
Time (400ns/div)
Figure 59.
Figure 60.
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APPLICATION INFORMATION
to a little over 2VPP differential swing. This implies a
maximum input voltage swing of approximately
200mVPP to be operating in the linear range at 5MHz.
Larger input signals can be accepted by the LNA, but
distortion performance will degrade with larger input
signals.
NOTE: For current users of the VCA8613 who are
switching to the VCA8617, pin 32 of the VCA8617 is
a VDD reference pin and requires a minimum 0.1μF
bypass capacitor to ground.
INPUT CIRCUIT
CW DOPPLER PROCESSOR
The input of the VCA8617 integrates several
commonly-used elements. Before reaching the input
of the LNA, the receive signal should be coupled with
a capacitor of at least 10nF (preferably more). When
this ac-coupling element is inserted, the LNA input
bias point is held to a common-mode value of 1.4V
by an integrated 4.5kΩ resistor. This common-mode
value changes with temperature and may also vary
from chip to chip, but for each chip, it will be held
constant. Two back-to-back clipping diodes are in
parallel with this resistor. These diodes prevent
excessive input voltages from passing through to the
LNA input, preventing deep saturation effects in the
LNA itself. These integrated diodes are designed to
handle a dc-current of up to about 10mA. If the
application requires improved overload protection,
external Schottky diodes, such as the BAS40 series
by Infineon, should be considered.
The VCA8617 integrates many of the elements
necessary to allow for the implementation of a simple
CW Doppler processing circuit. One circuit that was
integrated was a V/I converter following the LNA, as
shown in Figure 61. The V/I converter converts the
differential LNA voltage output to a current, which is
then passed through an 8x10 switch matrix (see
Figure 62). Within this switch matrix, any of the eight
LNA outputs can be connected to any of 10 CW
output
pins.
This
example
is
a
simple
current-summing circuit, such that each CW output
can represent the sum of any or all the channel
currents. The transconductance of the V/I converter is
approximately 20mA/V relative to the LNA input. For
proper operation of the CW Doppler Processor, it is
mandatory to have
a
bias voltage on the
output/outputs that are selected (see Figure 63).
The CW output common-mode is 1.4V.
LOW-NOISE PRE-AMPLIFIER (LNA)
The CW outputs are typically routed to a passive
delay line, allowing coherent summing of the signals.
After summing, IQ separation and down conversion to
baseband precedes a pair of high-resolution, low
sample rate ADCs.
The VCA8617 integrates a low-noise pre-amplifier.
Because of the high level of integration in the system,
noise performance was traded for power
consumption, resulting in an extremely low-power
pre-amplifier, with 0.8nV/√Hz noise performance at
5MHz. The LNA is configured as a fixed-gain 20dB
amplifier. Of this total gain, 6dB results from the
single-ended to differential conversion accomplished
within the LNA itself. The output of the LNA is limited
VCM = 1.5V
Buffer
Cross-Point
Switch
LNA
CW Output
Input 1
4.5kW
20dB
Buffer
Control
Logic
VLNA
VCM = 1.5V
(+1.4V)
Figure 61. Basic CW Processing Block Diagram
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V/I
Converter
Channel 1
Input
CW0
CW1
CW2
CW3
SDI
Decode
Logic
CW4
CLK
CW5
CW6
CW7
CW8
CW9
+V
SDO
V/I
Converter
Channel 8
Input
SDI
Decode
Logic
SDO
Figure 62. Basic CW Cross-Point Switch Matrix for All Eight Channels
VCA8617
R
To CW Circuitry
CW Output
OPA
VBIAS = 1.2V to 1.6V
Figure 63. Operational Amplifier
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VOLTAGE-CONTROLLED ATTENUATOR
(VCA)—DETAIL
shown as two sub-elements, QNA and QNB. Selector
switches, driven by the MGS bits, activate either or
both of the sub-element FETs to adjust the maximum
RON and thus achieve the stepped attenuation
options.
The VCA is designed to have a dB-linear attenuation
characteristic; that is, the gain loss in dB is constant
for each equal increment of the VCNTRL control
voltage. Figure 64 shows a block diagram of the
VCA. The attenuator is essentially a variable voltage
divider consisting of one series input resistor, RS, and
10 identical shunt FETs, placed in parallel and
The VCA can be used to process either differential or
single-ended signals. Fully differential operation will
reduce 2nd-harmonic distortion by about 10dB for
full-scale signals.
controlled
by
sequentially-activated
clipping
Input impedance of the VCA varies with gain setting,
because of the changing resistances of the
programmable voltage divider structure. At large
attenuation factors (that is, low gain settings), the
impedance will approach the series resistor value of
approximately 120Ω.
amplifiers. Each clipping amplifier can be thought of
as a specialized voltage comparator with a soft
transfer characteristic and well-controlled output limit
voltages. The reference voltages V1 through V10 are
equally spaced over the 0V to 2.0V control voltage
range. As the control voltage rises through the input
range of each clipping amplifier, the amplifier output
will rise from 0V (FET completely ON) to VCM – VT
(FET nearly OFF), where VCM is the common source
voltage and VT is the threshold voltage of the FET. As
each FET approaches its OFF state and the control
voltage continues to rise, the next clipping
amplifier/FET combination takes over for the next
As with the LNA stage, the VCA output is ac-coupled
into the PGA. This ac-coupling means that the
attenuation-dependent dc common-mode voltage will
not propagate into the PGA, and so the PGA dc
output level will remain constant.
Finally, note that the VCACNTRL input consists of FET
gate inputs. This architecture provides very high
impedance and ensures that multiple VCA8617
devices may be connected in parallel with no
significant loading effects. The nominal voltage range
for the VCNTRL input spans from 0V to 2.0V.
Overdriving this input (greater than 3V) does not
affect the performance.
portion
of
the
piecewise-linear
attenuation
characteristic. Thus, low control voltages have most
of the FETs turned ON, while high control voltages
have most turned OFF. Each FET acts to decrease
the shunt resistance of the voltage divider formed by
RS and the parallel FET network.
The attenuator is comprised of two sections, with five
parallel clipping amplifier/FET combinations in each.
Special reference circuitry is provided so that the
(VCM − VT) limit voltage will track temperature and IC
process variations, minimizing the effects on the
attenuator control characteristic.
PGA POST-AMPLIFIER
See Figure 66 for a simplified circuit diagram of the
PGA. PGA gain is programmed through the serial
port, and can be configured to 24 different gain
settings of 25dB, 30dB, 35dB, and 40dB, as shown in
Table 9. A patented circuit has been implemented in
the PGA that allows for exceptional overload signal
recovery.
In addition to the analog VCACNTRL gain setting input,
the attenuator architecture provides digitally-
programmable adjustment in four steps, via the two
attenuation bits. These bits adjust the maximum
achievable gain (corresponding to minimum
attenuation in the VCA, with VCNTRL = 2.0V) in 5dB
increments. This function is accomplished by
providing multiple FET sub-elements for each of the
Q1 to Q10 FET shunt elements (see Figure 65). In the
simplified diagram of Figure 64, each shunt FET is
Table 9. PGA Gain Settings
PG1, PG0
0, 0
GAIN
25dB
30dB
35dB
0, 1
1, 0
1, 1
40dB
RS
OUTPUT
INPUT
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
VCM
A0
A1
Figure 64. Programmable Attenuator Section
26
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VCA8617
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Attenuator
Input
SBOS308F –AUGUST 2004–REVISED NOVEMBER 2009
A1-A10 Attenuator Stages
QS
Attenuator
Output
RS
Q1
A2
Q2
A3
Q3
A4
Q4
A5
Q5
Q6
Q7
A8
Q8
A9
Q9
A10
Q10
VCM
A1
A6
A7
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
Control
Input
C1-C10 Clipping Amplifiers
0dB
-4dB
Attenuation Characteristic of Individual FETs
V
CM - VT
0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
Characteristic of Attenuator Control Stage Output
Overall Control Characteristics of Attenuator
0dB
-40dB
0.2V
2.0V
Control Signal (VCNTRL
)
Figure 65. Piecewise Approximation to Logarithmic Control Characteristics
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SBOS308F –AUGUST 2004–REVISED NOVEMBER 2009
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OUTPUT FILTER
SERIAL INTERFACE
The VCA8617 integrates an almost three-pole,
15MHz low-pass Butterworth filter in the output stage.
The cutoff frequency is implemented with passive
semiconductor elements and as such, the cutoff
frequency will not be precise. The output pins of the
VCA8617, as shown in Figure 66, nominally sit at
approximately 1.5VDC. However, this dc voltage
varies slightly over PG gain settings as well as from
chip to chip as a result of process variations. For
users who cannot tolerate this slight variation, an ac
coupling capacitor is recommended between the VCA
outputs and the ADC inputs. The smaller the value of
this capacitor, the better, because it reduces the
pulse signal settling time. For the typical performance
charts in this data sheet, a 560pF capacitor was
used.
The serial interface of the VCA8617 allows flexibility
in the use of the part. The following parameters are
set from the serial control registers:
•
Mode
–
–
TGC mode
CW mode
•
•
•
Attenuation range
PGA gain
Power-down (this is the default state in which the
VCA8617 initializes)
•
CW output selection for each input channel
The serial interface uses an SPI™ style of interface
format. The Input Register Bit Maps show the
functionality of each control register.
Ω
2M
VCM
OUT+
80pF
VCM
Attenuator
80pF
−
OUT
VCM
Ω
2M
Figure 66. Simplified PGA and Output Filter Circuit
28
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VCA8617
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SBOS308F –AUGUST 2004–REVISED NOVEMBER 2009
LAYOUT CONSIDERATIONS
The VCA8617 is a multi-channel amplifier with
integrated digital controls, capable of high gains.
Layout of the VCA8617 is fairly straightforward. By
connecting all of the grounds (including the digital
grounds) to the analog ground, noise performance
can be maintained.
Power-supply decoupling and decoupling of the
control voltage (VCNTRL) pin are essential in order to
ensure that the noise performance be maintained. For
further help in determining basic values, refer to
Figure 67.
The analog ground should be
a
solid plane.
V
CNTRL
1
0.01mF
2.2mF
0.1mF
NOTE: (1) 0.1mF capacitor
(2) 2.2mF capacitor
(1)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
+3V
+3V
U
15
2.2mF
0.1mF
5
12
7
29
V
FIL
DV
DV
DD
DD
51
V
LNA
2.2mF
0.1mF
59
58
57
56
55
26
25
24
23
22
48
47
46
45
44
43
42
41
40
39
38
DOUT
CLK
DIN
CW0
DOUT
CLK
CW0
CW2
8
CW2
9
CW4
DIN
CW4
10
6
CS
CW6
CS
CW6
VCA8617
CW8
DGND
DGND
IN8
CW8
11
61
63
1
CW9
CW9
Input 8
Input 7
Input 6
Input 5
Input 4
Input 3
Input 2
Input 1
CW7
CW7
CW5
IN7
CW5
IN6
CW3
CW3
3
IN5
CW1
CW1
14
16
18
20
62
64
2
IN4
OUT8
OUT8
OUT7
OUT7
OUT6
OUT6
OUT5
OUT5
OUT4
OUT4
OUT3
OUT8
OUT8
OUT7
OUT7
OUT6
OUT6
OUT5
OUT5
OUT4
OUT4
OUT3
IN3
IN2
IN1
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
4
13
15
17
19
Figure 67. Basic Connection Diagram
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (November, 2007) to Revision F
Page
•
•
Corrected y-axis labels for Figure 59 .................................................................................................................................. 23
Corrected y-axis labels for Figure 60 .................................................................................................................................. 23
Changes from Revision D (May, 2005) to Revision E
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed "100mW/channel" feature to "103mW/channel" .................................................................................................... 1
Changed Electrical Characteristics measured voltage; included DVDD ................................................................................ 3
Added Input Common-Mode Voltage specification ............................................................................................................... 3
Changed Input Voltage Range typical specification from 20V to 2.0V ................................................................................. 3
Changed Electrical Characteristics measured voltage; included DVDD ................................................................................ 4
Replaced Figure 22 ............................................................................................................................................................ 14
Replaced Figure 23 ............................................................................................................................................................ 15
Replaced Figure 28 ............................................................................................................................................................ 16
Replaced Figure 29 ............................................................................................................................................................ 16
Replaced Figure 43 ............................................................................................................................................................ 20
Replaced Figure 44 ............................................................................................................................................................ 20
Replaced Figure 47 ............................................................................................................................................................ 21
Replaced Figure 48 ............................................................................................................................................................ 21
Revised Application Information Section ............................................................................................................................ 24
30
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Product Folder Link(s): VCA8617
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
VCA8617PAGR
ACTIVE
TQFP
PAG
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
VCA8617
VCA8617PAGRG4
VCA8617PAGT
ACTIVE
ACTIVE
TQFP
TQFP
PAG
PAG
64
64
TBD
Call TI
Call TI
-40 to 85
-40 to 85
250
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
VCA8617
VCA8617
VCA8617PAGTG4
ACTIVE
TQFP
PAG
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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