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VS3673UNION [TI]

DaVinci 数字媒体处理器 | ZCE | 338 | 0 to 85;
VS3673UNION
型号： VS3673UNION
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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DaVinci 数字媒体处理器 | ZCE | 338 | 0 to 85
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TMS320DM365  
www.ti.com  
SPRS457C–MARCH 2009–REVISED APRIL 2010  
TMS320DM365  
Digital Media System-on-Chip (DMSoC)  
Check for Samples: TMS320DM365  
1 TMS320DM365 Digital Media System-on-Chip (DMSoC)  
1.1 Features  
12  
MAC  
• Highlights  
– ARM® Javelle® Technology  
– Embedded ICE-RT Logic for Real-Time  
Debug  
– High-Performance Digital Media  
System-on-Chip (DMSoC)  
– Up to 300-MHz ARM926EJ-S Clock Rate  
• ARM9 Memory Architecture  
– 16K-Byte Instruction Cache  
– 8K-Byte Data Cache  
– 32K-Byte RAM  
– Two Video Image Co-processors  
(HDVICP, MJCP) Engines  
– Supports a Range of Encode, Decode, and  
Video Quality Operations  
– Video Processing Subsystem  
– 16K-Byte ROM  
•
•
•
HW Face Detect Engine  
Resize Engine from 1/16x to 8x  
16-Bit Parallel AFE (Analog Front-End)  
Interface Up to 120 MHz  
4:2:2 (8-/16-bit) Interface  
– Little Endian  
• Two Video Image Co-processors  
(HDVICP, MJCP) Engines  
– Support a Range of Encode and Decode  
Operations  
– H.264, MPEG4, MPEG2, MJPEG, JPEG,  
WMV9/VC1  
•
•
•
3 DACs for HD Analog Video Output  
Hardware On-Screen Display (OSD)  
• Video Processing Subsystem  
– Front End Provides:  
– Capable of 720p 30fps H.264 video  
processing  
– Peripherals include EMAC, USB 2.0 OTG,  
DDR2/NAND, 5 SPIs, 2 UARTs, 2  
MMC/SD/SDIO, Key Scan  
•
•
HW Face Detect Engine  
Hardware IPIPE for Real-Time Image  
Processing  
– 8 Different Boot Modes and Configurable  
Power-Saving Modes  
– Pin-to-pin and software compatible with  
DM368  
– Extended temperature (-40ºC – 85ºC)  
available for 300-Mhz device  
– 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core  
– Debug Interface Support  
–
Resize Engine  
–
–
Resize Images From 1/16x to 8x  
Separate Horizontal/Vertical  
Control  
–
Two Simultaneous Output Paths  
•
•
IPIPE Interface (IPIPEIF)  
Image Sensor Interface (ISIF) and CMOS  
Imager Interface  
16-Bit Parallel AFE (Analog Front End)  
Interface Up to 120 MHz  
Glueless Interface to Common Video  
Decoders  
– 338-Pin Ball Grid Array at 65nm Process  
Technology  
•
•
•
• High-Performance Digital Media  
System-on-Chip (DMSoC)  
– 216-, 270-, 300-MHz ARM926EJ-S Clock Rate  
– Fully Software-Compatible With ARM9™  
BT.601/BT.656/BT.1120 Digital YCbCr  
4:2:2 (8-/16-Bit) Interface  
– Extended temperature available for 300-Mhz  
device  
• ARM926EJ-S™ Core  
•
•
•
Histogram Module  
Lens distortion correction module (LDC)  
Hardware 3A statistics collection module  
(H3A)  
– Support for 32-Bit and 16-Bit  
(Thumb® Mode) Instruction Sets  
– DSP Instruction Extensions and Single Cycle  
– Back End Provides:  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2010, Texas Instruments Incorporated  
 
 
 
TMS320DM365  
SPRS457C–MARCH 2009–REVISED APRIL 2010  
www.ti.com  
•
•
Hardware On-Screen Display (OSD)  
Composite NTSC/PAL video encoder  
output  
• One 64-Bit Watch Dog Timer  
• Two UARTs (One fast UART with RTS and CTS  
Flow Control)  
•
8-/16-bit YCC and Up to 24-Bit RGB888  
Digital Output  
• Five Serial Port Interfaces (SPI) each with two  
Chip-Selects  
•
•
•
3 DACs for HD Analog Video Output  
LCD Controller  
BT.601/BT.656 Digital YCbCr 4:2:2  
(8-/16-Bit) Interface  
• One Master/Slave Inter-Integrated Circuit  
(I2C) Bus™  
• One Multi-Channel Buffered Serial Port  
(McBSP)  
– I2S  
• Analog-to-Digital Convertor (ADC)  
– AC97 Audio Codec Interface  
– S/PDIF via Software  
• Power Management and Real Time Clock  
Subsystem (PRTCSS)  
– Real Time Clock  
• 16-Bit Host-Port Interface (HPI)  
• 10/100 Mb/s Ethernet Media Access Controller  
(EMAC) - Digital Media  
– Standard Voice Codec Interface (AIC12)  
– SPI Protocol (Master Mode Only)  
– Direct Interface to T1/E1 Framers  
– Time Division Multiplexed Mode (TDM)  
– 128 Channel Mode  
– IEEE 802.3 Compliant  
– Supports Media Independent Interface (MII)  
– Management Data I/O (MDIO) Module  
• Key Scan  
• Four Pulse Width Modulator (PWM) Outputs  
• Four RTO (Real Time Out) Outputs  
• Up to 104 General-Purpose I/O (GPIO) Pins  
(Multiplexed with Other Device Functions)  
• Voice Codec  
• External Memory Interfaces (EMIFs)  
• Boot Modes  
– DDR2 and mDDR SDRAM 16-bit wide EMIF  
With 256 MByte Address Space (1.8-V I/O)  
– Asynchronous16-/8-bit Wide EMIF (AEMIF)  
– On-Chip ARM ROM Bootloader (RBL) to Boot  
From NAND Flash, MMC/SD, UART, USB,  
SPI, EMAC, or HPI  
– AEMIF (NOR and OneNAND)  
•
Flash Memory Interfaces  
• Configurable Power-Saving Modes  
• Crystal or External Clock Input (typically  
19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)  
• Flexible PLL Clock Generators  
• Debug Interface Support  
–
–
–
NAND (8-/16-bit Wide Data)  
16 MB NOR Flash, SRAM  
OneNAND(16-bit Wide Data)  
• Flash Card Interfaces  
– Two Multimedia Card (MMC) / Secure Digital  
(SD/SDIO)  
– SmartMedia/xD  
– IEEE-1149.1 (JTAG™)  
Boundary-Scan-Compatible  
– ETB (Embedded Trace Buffer) with 4K-Bytes  
Trace Buffer memory  
• Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
• USB Port with Integrated 2.0 High-Speed PHY  
that Supports  
– Device Revision ID Readable by ARM  
• 338-Pin Ball Grid Array (BGA) Package  
(ZCE Suffix), 0.65-mm Ball Pitch  
• 65nm Process Technology  
• 3.3-V and 1.8-V I/O, 1.2-V/ 1.35-V Internal  
• Community Resources  
– USB 2.0 High-Speed Device  
– USB 2.0 High-Speed Host (mini-host,  
supporting one external device)  
– USB On The Go (HS-USB OTG)  
– TI E2E Community  
– TI Embedded Processors Wiki  
• Four 64-Bit General-Purpose Timers (each  
configurable as two 32-bit timers)  
2
TMS320DM365 Digital Media System-on-Chip (DMSoC)  
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Product Folder Link(s): TMS320DM365  
Copyright © 2009–2010, Texas Instruments Incorporated  
TMS320DM365  
www.ti.com  
SPRS457C–MARCH 2009–REVISED APRIL 2010  
1.2 Description  
Developers can now deliver pixel-perfect images at up to 720p H.264 at 30fps in their digital video designs  
without concerns of video format support, constrained network bandwidth, limited system storage capacity  
or cost with the new TMS320DM365 digital media processor based on DaVinci technology from Texas  
Instruments Incorporated (TI). With multi-format HD video, the DM365 also features a suite of peripherals  
saving developers on system costs.  
This ARM9-based DM365 device offers speeds up to 300 MHz and supports production-qualified H.264,  
MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the  
right video codec for their application. These codecs are driven from video accelerators offloading  
compression needs from the ARM core so that developers can utilize the most performance from the ARM  
for their application. Video surveillance designers achieve greater compression efficiency providing more  
storage without straining the network bandwidth. Developers of media playback and camera-driven  
applications, such as video doorbells, digital signage, digital video recorders, portable media players and  
more can ensure interoperability as well as product scalability by taking advantage of the full suite of  
codecs supported on the DM365.  
Along with multi-format HD video, the DM365 enables seamless interface to most additional external  
devices required for video applications. The image sensor interface is flexible enough to support CCD,  
CMOS, and various other interfaces such as BT.565, BT1120. The DM365 also offers a high level of  
integration with HD display support including, 3 built-in 10-bit HD Analog Video Digital to Analog  
Converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, Host Port Interface (HPI),  
Analog to Digital Converter, and many more features saving developers on overall system costs as well as  
real estate on their circuit boards allowing for a slimmer, sleeker design.  
Copyright © 2009–2010, Texas Instruments Incorporated  
TMS320DM365 Digital Media System-on-Chip (DMSoC)  
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Product Folder Link(s): TMS320DM365  
3
 
 
TMS320DM365  
SPRS457C–MARCH 2009–REVISED APRIL 2010  
www.ti.com  
1.3 Functional Block Diagram  
Figure 1-1 shows the functional block diagram of the TMS320DM365 device.  
16 Bit  
16-Bit  
DDR2/  
mDDR  
DDR2  
Controller  
Camera  
AFE  
IPIPE  
Resizer  
EDMA  
ISIF  
3A  
Face Det  
Lens Dist  
NAND/  
Video FE  
OneNAND/  
NOR Flash,  
SmartMedia/  
xD  
NAND/SM  
Memory  
I/F  
8/16 Bit  
16 Bit  
SDTV/HDTV  
Analog Video  
3Ch  
DAC  
Video  
Encoder  
OSD  
Digital  
RGB/YUV  
HPI  
Host CPU  
Video BE  
VPSS  
DMA/Data and Configuration Bus  
ARM INTC  
USB2.0 HS w/OTG  
MMC/SD (x2)  
SPI (x5)  
ARM926EJ-S  
HDVICP  
MJCP  
UART (x2)  
I2C  
I-Cache RAM  
16 KB 32 KB  
Timer (x4-64b)  
WDT (x1-64b)  
D-Cache ROM  
8 KB 16 KB  
System  
I/O  
Interface  
GIO  
PWM (x4)  
RTO  
McBSP  
EMAC  
ADC  
Key Scan  
PRTCSS  
Voice Codec  
JTAG  
I/F  
CLOCK Ctrl  
PLL  
19.2 MHz, 24 MHz 32.768  
27 MHz or 36 MHz kHz  
PMIC/  
SW  
Figure 1-1. Functional Block Diagram  
4
TMS320DM365 Digital Media System-on-Chip (DMSoC)  
Copyright © 2009–2010, Texas Instruments Incorporated  
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Product Folder Link(s): TMS320DM365  
 
 
TMS320DM365  
www.ti.com  
SPRS457C–MARCH 2009–REVISED APRIL 2010  
1
TMS320DM365 Digital Media System-on-Chip  
6
Peripheral Information and Electrical  
(DMSoC) ................................................... 1  
1.1 Features .............................................. 1  
1.2 Description ........................................... 3  
1.3 Functional Block Diagram ............................ 4  
Specifications .......................................... 77  
6.1  
Parameter Information Device-Specific Information  
...................................................... 77  
Recommended Clock and Control Signal Transition  
6.2  
Behavior ............................................ 78  
Revision History (Revision C) ............................. 6  
6.3 Power Supplies ..................................... 78  
6.4 Power-Supply Sequencing ......................... 79  
6.5 Reset ............................................... 81  
6.6 Oscillators and Clocks .............................. 82  
2
Device Overview ........................................ 7  
2.1 Device Characteristics ............................... 7  
2.2 Device Compatibility ................................. 8  
2.3 ARM Subsystem Overview .......................... 8  
2.4 System Control Module ............................. 12  
2.5 Power Management ................................ 13  
2.6 Memory Map Summary ............................. 14  
2.7 Pin Assignments .................................... 16  
6.7  
Power Management and Real Time Clock  
Subsystem (PRTCSS) .............................. 86  
6.8 General-Purpose Input/Output (GPIO) ............. 88  
6.9 EDMA Controller .................................... 90  
6.10 External Memory Interface (EMIF) ................ 100  
6.11 MMC/SD ........................................... 122  
6.12 Video Processing Subsystem (VPSS) Overview  
..................................................... 125  
6.13 USB 2.0 ........................................... 151  
6.14 Universal Asynchronous Receiver/Transmitter  
(UART) ............................................ 159  
2.8 Terminal Functions ................................. 21  
2.9 Device Support ..................................... 47  
Device Configurations ................................ 51  
3
3.1 System Module Registers .......................... 51  
3.2 Boot Modes ......................................... 52  
3.3 Device Clocking .................................... 55  
3.4 Power and Sleep Controller (PSC) ................. 63  
3.5 Pin Multiplexing ..................................... 64  
3.6 Device Reset ....................................... 65  
3.7 Default Device Configurations ...................... 65  
3.8 Debugging Considerations ......................... 70  
6.15 Serial Port Interface (SPI) ......................... 161  
6.16 Inter-Integrated Circuit (I2C) ...................... 171  
6.17 Multi-Channel Buffered Serial Port (McBSP) ..... 174  
6.18 Timer .............................................. 183  
6.19 Pulse Width Modulator (PWM) .................... 185  
6.20 Real Time Out (RTO) ............................. 187  
6.21 Ethernet Media Access Controller (EMAC) ....... 189  
6.22 Management Data Input/Output (MDIO) .......... 195  
6.23 Host-Port Interface (HPI) Peripheral .............. 197  
6.24 Key Scan .......................................... 201  
6.25 Analog-to-Digital Converter (ADC) ................ 203  
6.26 Voice Codec ....................................... 203  
6.27 IEEE 1149.1 JTAG ................................ 205  
Mechanical Data ...................................... 208  
4
5
System Interconnect .................................. 71  
Device Operating Conditions ....................... 72  
5.1  
Absolute Maximum Ratings Over Operating Case  
Temperature Range  
(Unless Otherwise Noted) ................................. 72  
5.2 Recommended Operating Conditions .............. 73  
7
5.3  
Electrical Characteristics Over Recommended  
Ranges of Supply Voltage  
7.1 Thermal Data for ZCE ............................. 208  
7.2 Packaging Information ............................ 208  
and Operating Case Temperature (Unless  
Otherwise Noted) ................................... 75  
Copyright © 2009–2010, Texas Instruments Incorporated  
Contents  
5
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TMS320DM365  
SPRS457C–MARCH 2009–REVISED APRIL 2010  
www.ti.com  
Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
highlights the technical changes made to the SPRS457B device-specific data sheet to make it a  
SPRS457C revision.  
Revision C Updates  
See  
Additions/Changes/Deletions  
Section 1.1  
Added "Extended temperature available for 300-Mhz device" bullet to Features list.  
Deleted last 2 paragraphs and bulleted list. Updated 1st paragraph and divided 1st paragraph into 3  
paragraphs.  
Section 1.2  
Figure 2-6  
Updated device nomenclature.  
Updated pin names:  
Figure 2-4  
•
•
VDD_AEMIF18_33 to VDD_AEMIF1_18_33  
VDD_DDR18_33 to VDD_AENUF2_18_33  
Updated Power Supply and Description columns.  
Significant change to USB_VBUS pin description.  
Table 2-5  
•
Section 3.2.1  
Figure 3-1  
Updated 4-bit ECC bullet.  
Updated figure.  
Changed (2M/(N+1)) values from 544/38 to 272/18 and changed Video Encoder values from 1/10 to  
1/20 and 1/4 to 1/8.  
Table 3-6  
Section 5.1  
Section 5.2  
Table 6-1  
Updated operating case temperature ranges in table.  
Updated table and table notes.  
Updated table and added table note.  
Section 6.8  
Table 6-11  
Changed first two bullets and removed open drain I/O cell from last bullet.  
Added table.  
Table 6-21  
Updated PLL1C SYSCLK4PLLC1 table note.  
Updated PLL1C SYSCLK4PLLC1 table note.  
Changed Min. values from 90 to 125.  
Table 6-22  
Section 6.10.3  
Section 6.10.3.1.2  
Table 6-45  
Deleted, "DDR2/mDDR-400 speed grade" from second sentence.  
Changed Min and Max values for NO.s 2 and 3  
Changed Driver Output Resistance Full Speed Max value from 44 to 49.5.  
Removed last bullet.  
Table 6-57  
Section 6.16  
6
Contents  
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TMS320DM365  
www.ti.com  
SPRS457C–MARCH 2009–REVISED APRIL 2010  
2 Device Overview  
2.1 Device Characteristics  
Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device,  
including the peripherals, capacity of on-chip RAM, ARM operating frequency, the package type with pin  
count, etc.  
Table 2-1. Characteristics of the Processor  
HARDWARE FEATURES  
DEVICE  
DDR2 / mDDR Memory Controller  
DDR2 / mDDR (16-bit bus width)  
Asynchronous (8/16-bit bus width) RAM,  
Flash (NOR, NAND, OneNAND)  
Asynchronous EMIF (AEMIF)  
Flash Card Interfaces  
EDMA  
Two MMC/SD  
One SmartMedia/xD  
64 independent DMA channels  
Eight QDMA channels  
Four 64-Bit General Purpose (each  
configurable as two separate 32-bit timers)  
One 64-Bit Watch Dog  
Timers  
UART  
Two (one with RTS and CTS flow control)  
Five (each supports two slave devices)  
One (Master/Slave)  
SPI  
I2C  
Peripherals  
Not all peripherals pins are  
available at the same time (For  
more detail, see the Device  
Configuration section).  
10/100 Ethernet MAC with Management Data I/O  
Multi-Channel Buffered Serial Port [McBSP]  
One  
One McBSP  
Power Management and Real Time Clock Subsystem  
(PRTCSS)  
RTC (32.768kHz), GPIO  
Key Scan  
4 x 4 Matrix, 5 x 3 Matrix  
One  
Voice Codec  
Analog-to-Digital Converter (ADC)  
General-Purpose Input/Output Port  
Pulse width modulator (PWM)  
6-channel, 10-bit Interface  
Up to 104  
Four outputs  
One Input (VPFE)  
One Output (VPBE)  
Configurable Video Ports  
High Speed Device  
High Speed Host  
USB 2.0  
On The Go (HS-USB-OTG)  
Wireless Interfaces  
RTO  
Through SDIO  
Four Channels  
ARM  
16-KB I-cache, 8-KB D-cache, 32-KB RAM,  
16-KB ROM  
On-Chip CPU Memory  
Organization  
See Section 6.27.1, JTAG Register  
Description(s)  
JTAG BSDL_ID  
JTAGID register (address location: 0x01C4 0028)  
CPU Frequency (Maximum)  
MHz  
ARM: 216-MHz, 270-MHz, 300-MHz  
1.2 V or 1.35 V  
Core (V)  
I/O (V)  
Voltage  
3.3 V, 1.8 V  
Reference frequency options  
Configurable PLL controller  
19.2 MHz, 24 MHz, 27 MHz, 36 MHz  
PLL bypass, programmable PLL  
PLL Options  
BGA Package  
13 x 13 mm  
338-Pin BGA (ZCE)  
65 nm  
Process Technology  
Copyright © 2009–2010, Texas Instruments Incorporated  
Device Overview  
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Table 2-1. Characteristics of the Processor (continued)  
HARDWARE FEATURES  
DEVICE  
Product Preview (PP),  
Advance Information (AI),  
or Production Data (PD)  
Product Status(1)  
PD  
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.  
2.2 Device Compatibility  
The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.  
2.3 ARM Subsystem Overview  
The ARM Subsystem contains components required to provide the ARM926EJ-S (ARM) master control of  
the overall device system, including the components of the ARM Subsystem, the peripherals, and the  
external memories.  
The ARM is responsible for handling system functions such as system-level initialization, configuration,  
user interface, user command execution, connectivity functions, interface and control of the subsystem,  
etc. The ARM is master and performs these functions because it has a large program memory space and  
fast context switching capability, and is thus suitable for complex, multi-tasking, and general-purpose  
control tasks.  
2.3.1 Components of the ARM Subsystem  
The ARM Subsystem consists of the following components:  
•
ARM926EJ-S RISC processor, including:  
–
–
–
–
–
–
coprocessor 15 (CP15)  
MMU  
16KB Instruction cache  
8KB Data cache  
Write Buffer  
Java accelerator  
•
ARM Internal Memories  
–
–
32KB Internal RAM (32-bit wide access)  
16KB Internal ROM (ARM bootloader for non-AEMIF boot modes)  
•
•
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)  
System Control Peripherals  
–
–
–
–
ARM Interrupt Controller  
PLL Controller  
Power and Sleep Controller  
System Control Module  
The ARM also manages/controls all the device peripherals.  
Figure 2-1 shows the functional block diagram of the ARM Subsystem.  
8
Device Overview  
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SPRS457C–MARCH 2009–REVISED APRIL 2010  
ARM  
Master  
IF  
Interrupt  
Controller  
(AINTC)  
Master IF  
Arbiter  
Arbiter  
I-AHB  
D-AHB  
System  
Control  
I-TCM  
D-TCM  
Slave  
ARM926EJ-S  
Arbiter  
PLLC2  
IF  
PLLC1  
Power  
Sleep  
16K I$  
8K D$  
CP15  
MMU  
16K  
16K  
16K  
Controller  
(PSC)  
ROM  
RAM1  
RAM0  
Peripherals  
...  
Figure 2-1. ARM Subsystem Block Diagram  
2.3.2 ARM926EJ-S RISC CPU  
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of  
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications  
where full memory management, high performance, low die size, and low power are all important. The  
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to  
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor  
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,  
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code  
overhead.  
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both  
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a  
complete high performance subsystem, including:  
•
•
•
•
•
•
•
•
ARM926EJ -S integer core  
CP15 system control coprocessor  
Memory Management Unit (MMU)  
Separate instruction and data Caches  
Write buffer  
Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces  
Separate instruction and data AHB bus interfaces  
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)  
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available  
at http://www.arm.com  
Copyright © 2009–2010, Texas Instruments Incorporated  
Device Overview  
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2.3.3 CP15  
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and  
data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM  
subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions,  
when the ARM in a privileged mode such as supervisor or system mode.  
2.3.4 MMU  
The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux,  
WindowCE, ultron, ThreadX, etc. A single set of two level page tables stored in main memory is used to  
control the address translation, permission checks and memory region attributes for both data and  
instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the  
information held in the page tables. The MMU features are:  
•
•
Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.  
Mapping sizes are:  
–
–
–
–
1MB (sections)  
64KB (large pages)  
4KB (small pages)  
1KB (tiny pages)  
•
Access permissions for large pages and small pages can be specified separately for each quarter of  
the page (subpage permissions)  
•
•
•
•
Hardware page table walks  
Invalidate entire TLB, using CP15 register 8  
Invalidate TLB entry, selected by MVA, using CP15 register 8  
Lockdown of TLB entries, using CP15 register 10  
2.3.5 Caches and Write Buffer  
The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following  
features:  
•
•
Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)  
Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with  
two dirty bits in the Dcache  
•
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory  
region using the C and B bits in the MMU translation tables.  
•
•
Critical-word first cache refilling  
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,  
providing a mechanism for both lockdown, and controlling cache corruption  
•
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG  
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the  
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the  
possibility of TLB misses related to the write-back address.  
•
Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of  
the Dcache or Icache, and regions of virtual memory.  
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write  
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for  
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a  
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.  
2.3.6 Tightly Coupled Memory (TCM)  
ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt  
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Vector table. ARM internal ROM boot modes include NAND, MMC/SD, UART, USB, SPI, EMAC, and HPI.  
The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface  
that provides for separate instruction and data bus connections. Since the ARM TCM does not allow  
instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and  
instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM  
from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for  
direct accesses to the ARM internal memory from a non-ARM master. Because of the time-critical nature  
of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA  
transfers.  
Instruction and Data accesses are differentiated via accessing different memory map regions, with the  
instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. Placing the  
instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,  
as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB  
each, which allows simultaneous instruction and data accesses to be accomplished if the code and data  
are in separate banks.  
2.3.7 Advanced High-performance Bus (AHB)  
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the configuration bus  
and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB  
by the configuration bus and the external memories bus.  
2.3.8 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)  
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an  
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem also includes the Embedded Trace  
Buffer (ETB). The ETM consists of two parts:  
•
•
Trace Port provides real-time trace capability for the ARM9.  
Triggering facilities provide trigger resources, which include address and data comparators, counter,  
and sequencers.  
The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The  
ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace  
data.  
2.3.9 ARM Memory Mapping  
The ARM memory map is shown in Table 2-3 and Table 2-4. This section describes the memories and  
interfaces within the ARM's memory map.  
2.3.9.1 ARM Internal Memories  
The ARM has access to the following ARM internal memories:  
•
32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow  
simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data  
(D-TCM) to the different memory regions.  
•
16KB ARM Internal ROM  
2.3.9.2 External Memories  
The ARM has access to the following External memories:  
•
•
•
•
DDR2 / mDDR Synchronous DRAM  
Asynchronous EMIF / OneNAND / NOR  
NAND Flash  
Flash card devices:  
–
MMC/SD  
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–
–
xD  
SmartMedia  
2.3.10 Peripherals  
The ARM has access to all of the peripherals on the device.  
2.3.11 ARM Interrupt Controller (AINTC)  
The device ARM Interrupt Controller (AINTC) has the following features:  
•
•
•
Supports up to 64 interrupt channels (16 external channels)  
Interrupt mask for each channel  
Each interrupt channel can be mapped to a Fast Interrupt Request (FIQ) or to an Interrupt Request  
(IRQ) type of interrupt.  
•
•
•
Hardware prioritization of simultaneous interrupts  
Configurable interrupt priority (2 levels of FIQ and 6 levels of IRQ)  
Configurable interrupt entry table (FIQ and IRQ priority table entry) to reduce interrupt processing time  
The ARM core supports two interrupt types: FIQ and IRQ. See the ARM926EJ-S Technical Reference  
Manual for detailed information about the ARM’s FIQ and IRQ interrupts. Each interrupt channel is  
mappable to an FIQ or to an IRQ type of interrupt, and each channel can be enabled or disabled. The  
INTC supports user-configurable interrupt-priority and interrupt entry addresses. Entry addresses minimize  
the time spent jumping to interrupt service routines (ISRs). When an interrupt occurs, the corresponding  
highest priority ISR’s address is stored in the INTC’s ENTRY register. The IRQ or FIQ interrupt routine can  
read the ENTRY register and jump to the corresponding ISR directly. Thus, the ARM does not require a  
software dispatcher to determine the asserted interrupt.  
2.4 System Control Module  
The system control module is a system-level module containing status and top-level control logic required  
by the device. The system control module consists of a miscellaneous set of status and control registers,  
accessible by the ARM and supporting all of the following system features and operations:  
•
•
Device identification  
Device configuration  
–
–
Pin multiplexing control  
Device boot configuration status  
•
•
ARM interrupt and EDMA event multiplexing control  
Special peripheral status and control  
–
–
–
–
–
–
Timer64  
USB PHY control  
VPSS clock and video DAC control and status  
DDR VTP control  
Clockout circuitry  
GIO de-bounce control  
•
•
Power management  
Deep sleep  
Bandwidth Management  
Bus master DMA priority control  
–
–
For more information on the System Control Module refer to Section 3, Device Configurations and the  
TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).  
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2.5 Power Management  
The device is designed for minimal power consumption. There are two components to power  
consumption: active power and leakage power. Active power is the power consumed to perform work and  
scales with clock frequency and the amount of computations being performed. Active power can be  
reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to  
complete the required operation in the required time-line or to run at a clock setting until the work is  
complete and then drastically cut the clocks (e.g. to PLL Bypass mode) until additional work must be  
performed. Leakage power is due to static current leakage and occurs regardless of the clock rate.  
Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating  
junction temperatures. Leakage power can only be avoided by removing power completely from a device  
or subsystem. The device includes several power management modes which are briefly described in  
Table 2-2. See the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number  
SPRUFG5) for more information on power management.  
Table 2-2. Power Management Conditions  
GIO,  
UART,  
I2C  
SPI,  
PWM,  
TIMER  
POWER MGMT.  
APPLICATION  
SCENARIO  
OTHER  
PERIPH.  
CLOCKS  
DDR  
CLOCK/  
MODE  
CORE  
POWER  
OSC.  
POWER  
PLL  
CNTRLR.  
ARM926  
CLOCK  
PRTCSS  
DESCRIPTION  
CLOCKS CLOCKS  
This condition  
consumes the lowest  
possible power, except  
for the PRTCSS.  
PRTCSS  
Active  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
This mode consumes  
the second lowest  
Suspend / possible power, except  
Bypass  
Mode  
(not  
Deep Sleep Mode(1) Active  
On  
On  
Off  
On  
Off  
Off  
"Self-  
Refresh"  
for PRTCSS and core  
power, where only the  
deep sleep circuit is on  
in this mode.  
Active)  
This condition keeps  
the minimum possible  
modules powered-on  
Suspend / in order to wake up the  
Bypass  
Mode  
Standby  
Active  
On  
Off  
Off  
"Self-  
Refresh"  
device. Clocks are  
suspended except for  
GIO (interrupts),  
UART, and I2C (in  
slave mode).  
Most clocks are  
suspended, except for  
ARM, GIO, UART,  
SPI, I2C, PWM, and  
timers. Since ARM will  
not have access to  
DDR, its internal  
Cache will be either  
frozen or not  
Suspend /  
"Self-  
Refresh"  
Low-power  
(PLL Bypass Mode)  
Bypass  
Mode  
Active  
Active  
On  
On  
On  
On  
On  
On / Off  
On / Off  
On / Off  
accessed.  
The device, including  
system PLLs, are on.  
This condition  
Nominal  
Clock /  
System Running  
(PLL Mode)  
PLL Mode On  
On / Off  
On / Off  
On / Off  
Operation conserves the least  
amount of power.  
(1) For more details, see TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5)  
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2.6 Memory Map Summary  
Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of  
the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memories  
associated with its processor and various subsystems. To help simplify software development a unified  
memory map is used where possible to maintain a consistent view of device resources across all bus  
masters. The bus masters are the ARM, EDMA, EMAC, USB, HPI, MJCP, HDVICP and VPSS. The  
Master Peripherals are EMAC, USB, and HPI. Please refer to Section 4 for more details.  
Table 2-3. Memory Map  
Start Address  
0x0000 0000  
0x0000 4000  
0x0000 8000  
End Address  
0x0000 3FFF  
0x0000 7FFF  
0x0000 BFFF  
Size (Bytes)  
ARM  
Mem Map  
EDMA  
Mem Map  
Master Periph  
Mem Map  
VPSS  
Mem Map  
16K  
ARM RAM0  
(Instruction)  
16K  
ARM RAM1  
(Instruction)  
Reserved  
Reserved  
16K  
ARM ROM  
(Instruction)  
0x0000 C000  
0x0001 0000  
0x0001 4000  
0x0001 8000  
0x0001 C000  
0x0010 0000  
0x01BC 0000  
0x01BC 1000  
0x01BC 1800  
0x01BC 1900  
0x01BD 0000  
0x01C0 0000  
0x0000 FFFF  
0x0001 3FFF  
0x0001 7FFF  
0x0001 BFFF  
0x000F FFFF  
0x01BB FFFF  
0x01BC 0FFF  
0x01BC 17FF  
0x01BC 18FF  
0x01BC FFFF  
0x01BF FFFF  
0x01FF FFFF  
16K  
16K  
16K  
16K  
912K  
26M  
4K  
Reserved  
ARM RAM0 (Data)  
ARM RAM1 (Data)  
ARM ROM  
ARM RAM0  
ARM RAM1  
ARM ROM  
ARM RAM0  
ARM RAM1  
ARM ROM  
Reserved  
ARM ETB Mem  
ARM ETB Reg  
ARM IceCrusher  
Reserved  
2K  
Reserved  
256  
Reserved  
59136  
192K  
4M  
CFG Bus  
CFG Bus  
CFG Bus  
Peripherals  
Peripherals  
Peripherals  
0x0200 0000  
0x0A00 0000  
0x11F0 0000  
0x11F2 0000  
0x1200 0000  
0x09FF FFFF  
0x11EF FFFF  
0x11F1 FFFF  
0x11FF FFFF  
0x1207 FFFF  
128M  
127M - 16K  
128K  
ASYNC EMIF (Data) ASYNC EMIF (Data)  
Reserved  
MJCP DMA Port  
Reserved  
Reserved  
MJCP DMA Port  
Reserved  
896K  
512K  
HDVICP DMA Port1 HDVICP DMA Port1  
HDVICP  
DMA Port1  
0x1208 0000  
0x1210 0000  
0x1218 0000  
0x2000 0000  
0x120F FFFF  
0x1217 FFFF  
0x1FFF FFFF  
0x2000 7FFF  
512K  
512K  
Reserved  
HDVICP DMA Port2  
HDVICP DMA Port3  
Reserved  
Reserved  
222.5M  
32K  
DDR EMIF Control  
Regs  
DDR EMIF Control  
Regs  
0x2000 8000  
0x4200 0000  
0x4A00 0000  
0x8000 0000  
0x9000 0000  
0x41FF FFFF  
0x49FF FFFF  
0x7FFF FFFF  
0x8FFF FFFF  
0xFFFF FFFF  
544M-32K  
128M  
Reserved  
Reserved  
864M  
256M  
DDR EMIF  
Reserved  
DDR EMIF  
Reserved  
DDR EMIF  
Reserved  
DDR EMIF  
Reserved  
1792M  
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Table 2-4. ARM Configuration Bus Access to Peripherals  
Address  
Region  
EDMA CC  
EDMA TC0  
EDMA TC1  
EDMA TC2  
EDMA TC3  
Reserved  
UART0  
Start  
End  
Size  
64K  
1K  
0x01C0 0000  
0x01C1 0000  
0x01C1 0400  
0x01C1 0800  
0x01C1 0C00  
0x01C1 1000  
0x01C2 0000  
0x01C2 0400  
0x01C2 0800  
0x01C2 0C00  
0x01C2 1000  
0x01C2 1400  
0x01C2 1800  
0x01C2 1C00  
0x01C2 2000  
0x01C2 2400  
0x01C2 2800  
0x01C2 2C00  
0x01C2 3000  
0x01C2 3800  
0x01C2 3C00  
0x01C2 4000  
0x01C4 0000  
0x01C4 0800  
0x01C4 0C00  
0x01C4 1000  
0x01C4 2000  
0x01C4 8000  
0x01 C4 8400  
0x01C6 4000  
0x01C6 6000  
0x01C6 6800  
0x01C6 7000  
0x01C6 7800  
0x01C6 8000  
0x01C6 8800  
0x01C6 9000  
0x01C6 9400  
0x01C6 9800  
0x01C6 A000  
0x01C0 FFFF  
0x01C1 03FF  
0x01C1 07FF  
0x01C1 0BFF  
0x01C1 0FFF  
0x01C1 FFFF  
0x01C2 03FF  
0x01 20 7FFF  
0x01C2 0BFF  
0x01C2 0FFF  
0x01C2 13FF  
0x01C2 17FF  
0x01C2 1BFF  
0x01C2 1FFF  
0x01C2 23FF  
0x01C2 27FF  
0x01C2 2BFF  
0x01C2 2FFF  
0x01C2 37FF  
0x01C2 3BFF  
0x01C2 3FFF  
0x01C3 4FFF  
0x01C4 07FF  
0x01C4 0BFF  
0x01C4 0FFF  
0x01C4 1FFF  
0x01C4 7FFF  
0x01C4 83FF  
0x01C63FFF  
0x01C6 5FFF  
0x01C6 67FF  
0x01C6 6FFF  
0x01C6 77FF  
0x01C6 FFFF  
0x01C6 87FF  
0x01C6 87FF  
0x01C6 93FF  
0x01C6 97FF  
0x01C6 9FFF  
0x01C6 FFFF  
1K  
1K  
1K  
60 K  
1K  
Reserved  
Timer 3  
1K  
1K  
Real-time out  
I2C  
1K  
1K  
Timer 0  
1K  
Timer 1  
1K  
Timer 2  
1K  
PWM0  
1K  
PWM1  
1K  
PWM2  
1K  
PWM3  
1K  
SPI4  
2K  
Timer 4  
1K  
ADCIF  
1K  
Reserved  
System Module  
PLL Controller 1  
PLL Controller 2  
112K  
2K  
1K  
1K  
Power/Sleep Controller  
4K  
Reserved  
ARM Interrupt Controller  
Reserved  
24K  
1K  
111K  
8K  
USB OTG 2.0 Regs / RAM  
SPI0  
2K  
SPI1  
2K  
GPIO  
2K  
SPI2  
2K  
SPI3  
2K  
Reserved  
2K  
PRTCSS Interface Registers  
KEYSCAN  
1K  
1K  
HPI  
2K  
Reserved  
24K  
VPSS Subsystem  
ISP System Configuration Registers  
VPBE Clock Control Register  
Resizer Registers  
IPIPE Registers  
ISIF Registers  
0x01C7 0000  
0x01C7 0200  
0x01C7 0400  
0x01C7 0800  
0x01C7 1000  
0x01C7 00FF  
0x01C7 02FF  
0x01C7 07FF  
0x01C7 0FFF  
0x01C7 11FF  
256  
256  
1K  
2K  
512  
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Table 2-4. ARM Configuration Bus Access to Peripherals (continued)  
Address  
0x01C7 12FF  
IPIPEIF Registers  
H3A Registers  
Reserved  
0x01C7 1200  
0x01C7 1400  
0x01C7 1600  
0x01C7 1800  
0x01C7 1C00  
0x01C7 1D00  
0x01C7 1E00  
0x01C7 2000  
0x01D0 0000  
0x01D0 2000  
0x01D0 4000  
0x01D0 6000  
0x01D0 6400  
0x01D0 7000  
0x01D0 8000  
0x01D0 A000  
0x01D0 B000  
0x01D0 C000  
0x01D0 C400  
0x01D1 0000  
0x01D1 1000  
0x01D2 0000  
0x01D4 0000  
0x01E0 0000  
0x0200 0000  
0x0400 0000  
0x0600 0000  
0x0A00 0000  
768  
0x01C7 14FF  
0x01C7 17FF  
0x01C7 1BFF  
0x01C7 1CFF  
0x01C7 1DFF  
0x01C7 1FFF  
0x01CF FFFF  
0x01D0 1FFF  
0x01D0 3FFF  
0x01D0 5FFF  
0x01D0 63FF  
0x01D0 7FFF  
0x01D0 9FFF  
256  
512  
FDIF Registers  
OSD Registers  
Reserved  
1K  
256  
256  
VENC Registers  
Reserved  
512  
568K  
8K  
Multimedia / SD 1  
McBSP  
8K  
Reserved  
8K  
UART1  
1K  
Reserved  
3K  
EMAC Control Registers  
EMAC Control Module RAM  
EMAC Control Module Registers  
EMAC MDIO Control Registers  
Voice Codec  
0x01D40K7FFF  
8K  
0x01D0 AFFF  
0x01D0 B7FF  
0x01D0 C3FF  
0x01D0 FFFF  
0x01D1 0FFF  
0x01D1 FFFF  
0x01D3 FFFF  
0x01DF FFFF  
0x01FF FFFF  
0x03FF FFFF  
0x05FF FFFF  
0x09FF FFFF  
0x0FFF FFFF  
4K  
2K  
1K  
Reserved  
17K  
4K  
ASYNC EMIF Control  
Multimedia / SD 0  
Reserved  
60K  
128K  
768K  
2M  
Reserved  
Reserved  
ASYNC EMIF Data (CE0)  
ASYNC EMIF Data (CE1)  
Reserved  
32M  
32M  
64M  
96M  
Reserved  
2.7 Pin Assignments  
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in  
the smallest possible package. Pin multiplexing is controlled using a combination of hardware  
configuration at device reset and software programmable register settings.  
2.7.1 Pin Map (Bottom View)  
Figure 2-2 through Figure 2-5 show the pin assignments in four quadrants (A, B, C, and D). Note that  
micro-vias are not required.  
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V
DD12_  
CV  
CV  
CV  
V
V
J
PWCTRIO2  
RTCXO  
PWCTRIO1  
PECTRIO0  
RESET  
N.B.  
PWCTRIO4  
EMU1  
TDO  
PWCTRO3  
V
DDS18  
DD  
DD  
DD  
SS  
PRTCSS  
V
TRST  
V
CV  
DD  
H
DDS33  
SS  
SS_32K  
TMS  
RTCK  
GIO18  
GIO15  
GIO9  
CV  
V
DDA18_ADC  
RTCXI  
GIO20  
GIO16  
GIO14  
GIO12  
GIO11  
EMU0  
TDI  
N.B.  
G
F
DD  
V
V
GIO21  
GIO19  
GIO13  
N.B.  
TCK  
V
V
DDS33  
DDS33  
SSA_ADC  
SSA18_VC  
DDA18_VC  
V
GIO17  
DD18_SLDO  
GIO44  
ADC_CH4  
N.B.  
ADC_CH0  
V
E
D
C
GPIO46  
V
GIO49  
GIO3  
ADC_CH3  
MICIN  
V
DDRAM  
GIO2  
SSA33_VC  
LINEO  
SPP  
GIO1  
GIO47  
ADC_CH1  
GIO0  
MICIP  
GIO10  
GIO6  
GIO5  
GPIO45  
B
A
RSV0  
1
GIO48  
5
VCOM  
8
GIO8  
2
GIO7  
3
GIO4  
4
ADC_CH5  
ADC_CH2  
SPN  
9
6
7
(1) N.B stands for No-Ball.  
Figure 2-2. ZCE Pin Map [Quadrant A]  
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1
2
3
4
5
6
7
8
9
DDR_  
DQM1  
DDR_  
DQ12  
DDR_  
DQ8  
DDR_  
DQ6  
V
GIO32  
GIO35  
GIO36  
GIO41  
W
V
U
T
SS  
DDR_  
DQ15  
DDR_  
DQ14  
DDR_  
DQ11  
DDR_  
DQ5  
GIO28  
GIO23  
GIO29  
GIO27  
GIO22  
GIO33  
N.B.  
GIO34  
GIO31  
GIO38  
GIO40  
GIO37  
GIO39  
DDR_  
DQSN1  
DDR_  
DQSN0  
N.B.  
DDR_DQ9  
GIO26  
GIO25  
DDR_  
DQGATE0  
DDR_  
DQGATE1  
DDR_DQS1  
DDR_DQ13  
GIO24  
GIO30  
GIO43  
GIO42  
DDR_DQ10  
DDR_DQ7  
RSV1  
V
PP  
RSV2  
R
P
N
M
L
V
V
V
V
USB_DM  
USB_DP  
USB_ID  
MXI1  
V
V
V
V
DDS33  
DDS33  
DDS18  
SS  
DD18_DDR  
SSA18_USB  
SSA33_USB  
DDA33_USB  
V
V
SS  
V
USB_VBUS  
N.B.  
V
V
N.B.  
DDA18_PLL  
DD18_USB  
DDS33  
DD18_DDR  
VDDA12LDO_  
USB  
CV  
DD  
V
SS  
V
SS  
V
SS  
PWRCNTON  
PWRST  
V
SSA  
V
V
SS  
V
SS  
V
V
SS  
PWCTRO3  
PWCTRO2  
PWCTRIO6  
PWCTRO1  
PWCTRIO5  
DDMXI  
SS_MX1  
V
V
CV  
DD  
N.B.  
V
SS  
MXO1  
PWCTRO0  
DD12_PRTCSS  
K
DD18_PRTCSS  
(1) N.B stands for No-Ball.  
Figure 2-3. ZCE Pin Map [Quadrant B]  
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10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
DDR_BA0  
DDR_A2  
DDR_A6  
DDR_A8  
DDR_A11  
V
DDR_DQ4  
DDR_CLK  
DDR_CLK  
DDR_WE  
W
V
U
T
SS  
DDR_A12  
DDR_DQ1  
DDR_DQ0  
DDR_DQM0  
DDR_CAS  
DDR_A5  
DDR_A4  
DDR_A7  
EM_A3  
DDR_A10  
DDR_A9  
DDR_A13  
EM_A13  
EM_A12  
EM_A9  
DDR_DQ3  
DDR_BA2  
DDR_A1  
DDR_A0  
DDR_A3  
EM_A11  
EM_A10  
EM_A8  
EM_A4  
EM_D13  
EM_D9  
EM_A1  
EM_D5  
EM_D2  
N.B.  
N.B.  
DDR_RAS  
DDR_CS  
N.B.  
DDR_DQS0  
DDR_DQ2  
DDR_BA1  
EM_A7  
EM_BA1  
V
DDR_  
PADREFP  
DD_  
V
DDR_CKE  
EM_A5  
EM_D14  
EM_D11  
EM_A6  
EM_D15  
EM_D10  
EM_A2  
EM_D6  
EM_D0  
DD18_DDR  
R
P
N
M
L
AEMIF1_18_33  
V
DD_  
V
DDR_VREF  
V
V
SS  
EM_D12  
EM_D8  
EM_CLK  
EM_D4  
EM_D3  
EM_BA0  
DD18_DDR  
DD18_DDR  
AEMIF1_18_33  
V
V
SS  
V
SS  
N.B.  
DD18_DDR  
N.B.  
N.B.  
CV  
DD  
V
SS  
CV  
DD  
CV  
DD  
V
EM_CE[0]  
EM_A0  
N.B.  
EM_ADV  
EM_D7  
EM_D1  
DDS18  
V
DD_  
V
SS  
V
CV  
DD  
V
SS  
DDS33  
AEMIF2_18_33  
V
DD_  
V
SS  
V
SS  
CV  
DD  
N.B.  
K
AEMIF2_18_33  
(1) N.B stands for No-Ball.  
Figure 2-4. ZCE Pin Map [Quadrant C]  
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V
CV  
CV  
V
V
CV  
MMCSD0_CLK  
V
V
EM_WE  
EM_CE[1]  
EM_WAIT  
EM_OE  
SS  
DD  
SS  
DD  
J
SS  
MMCSD0_  
CMD  
MMCSD0_  
DATA3  
MMCSD0_  
DATA2  
MMCSD0_  
DATA0  
MMCSD0_  
DATA1  
V
V
V
SS  
DDS18  
DD  
DDS33  
N.B.  
DDS18  
DDS18  
H
G
F
V
SS  
N.B.  
YOUT1  
COUT4  
COUT0  
N.B.  
N.B.  
V
HSYNC  
YOUT5  
COUT5  
YOUT7  
YOUT3  
YOUT0  
VSYNC  
YOUT4  
COUT7  
COUT1  
FIELD  
YOUT6  
YOUT2  
COUT6  
COUT2  
LCD_OE  
EXTCLK  
SS  
V
V
V
V
V
SS  
DDS33  
SSA12_DAC  
DD_ISIF18_33  
DD_ISIF18_33  
C_WE_  
FIELD  
VDDA12_DAC  
V
SS  
VDDA33_VC  
VSSA18_  
DAC  
E
D
C
B
A
V
VREF  
YIN4  
YIN7  
PCLK  
N.B.  
YIN1  
HD  
YIN0  
CIN6  
COUT3  
CIN2  
DDA18_DAC  
N.B.  
VFB  
COMPPR  
IDACOUT  
COMPY  
YIN5  
VD  
YIN2  
CIN5  
CIN0  
VCLK  
TVOUT  
10  
COMPPB  
12  
YIN6  
13  
V
SS  
IREF  
11  
YIN3  
14  
CIN7  
15  
CIN4  
16  
CIN3  
17  
CIN1  
18  
19  
(1) N.B stands for No-Ball.  
Figure 2-5. ZCE Pin Map [Quadrant D]  
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2.8 Terminal Functions  
Table 2-5 provides a complete pin description list which shows external signal names, the associated pin  
(ball) numbers along with the mechanical package designator, the pin type, whether the pin has any  
internal pullup or pulldown resistors, and a functional pin description. For more detailed information on  
device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see  
Section 3.  
Table 2-5. Pin Descriptions  
Name  
CIN7(5)  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
A15  
C15  
B16  
A16  
A17  
C16  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
ISIF  
ISIF  
ISIF  
ISIF  
ISIF  
ISIF  
VDD_ISIF18_33  
VDD_ISIF18_33  
VDD_ISIF18_33  
VDD_ISIF18_33  
VDD_ISIF18_33  
VDD_ISIF18_33  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
Input Standard ISIF Analog Front End (AFE): raw[7]  
YCC 16-bit: time multiplexed between chroma:  
CB/CR[07]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the upper channel. Y/CB/CR[07]  
CIN6(5)  
CIN5(5)  
CIN4(5)  
Input Standard ISIF Analog Front End (AFE): raw[6]  
YCC 16-bit: time multiplexed between chroma:  
CB/CR[06]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the upper channel. Y/CB/CR[06]  
Input Standard ISIF Analog Front End (AFE): raw[5]  
YCC 16-bit: time multiplexed between chroma:  
CB/CR[05]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the upper channel. Y/CB/CR[05]  
Input Standard ISIF Analog Front End (AFE): raw[4]  
YCC 16-bit: time multiplexed between chroma:  
CB/CR[04]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the upper channel. Y/CB/CR[04]  
(5)  
CIN3  
Input Standard ISIF Analog Front End (AFE): raw[3]  
YCC 16-bit: time multiplexed between chroma:  
CB/CR[03]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the upper channel. Y/CB/CR[03]  
CIN2(5)  
Input Standard ISIF Analog Front End (AFE): raw[2]  
YCC 16-bit: time multiplexed between chroma:  
CB/CR[02]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the upper channel. Y/CB/CR[02]  
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.  
(2) Specifies the operating I/O supply voltage for each signal. See Section 6.3 , Power Supplies for more detail.  
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)  
(4) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the  
following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should  
be minimized.  
(5) The Y input (YIN[7:0]) and C input (CIN[7:0]) buses can be swapped by programming the field bit YCINSWP in the VPFE CCD  
Configuration (CCDCFG) register (0x01C7 0136h).  
IF YCINSWP bit is 0 (default) YIN[7:0] = Y signal / CIN[7:0] = C signal .  
IF YCINSWP bit is 1 YIN[7:0] = C signal / CIN[7:0] = Y signal  
For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8).  
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Table 2-5. Pin Descriptions (continued)  
Name  
CIN1(5)  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
A18  
B17  
C12  
I/O  
I/O  
I/O  
ISIF  
VDD_ISIF18_33  
VDD_ISIF18_33  
VDD_ISIF18_33  
IPD  
IPD  
IPD  
Input Standard ISIF Analog Front End (AFE): raw[1]  
YCC 16-bit: time multiplexed between chroma:  
CB/CR[01]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the upper channel. Y/CB/CR[01]  
CIN0(5)  
ISIF  
Input Standard ISIF Analog Front End (AFE): raw[0]  
YCC 16-bit: time multiplexed between chroma:  
CB/CR[00]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the upper channel. Y/CB/CR[00]  
YIN7(5) / GIO103  
/SPI3_SCLK  
ISIF/  
GIO /  
SPI3  
Input Standard ISIF Analog Front End (AFE): raw[15]  
YCC 16-bit: time multiplexed between luma: Y[07]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the lower channel. Y/CB/CR[07]  
GIO: GIO[103]  
SPI3: Clock  
YIN6(5) / GIO102  
/SPI3_SIMO  
A13  
B13  
D12  
I/O  
I/O  
I/O  
ISIF /  
GIO /  
SPI3  
VDD_ISIF18_33  
VDD_ISIF18_33  
VDD_ISIF18_33  
IPD  
IPD  
IPD  
Input Standard ISIF Analog Front End (AFE): raw[14]  
YCC 16-bit: time multiplexed between luma: Y[06]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the lower channel. Y/CB/CR[06]  
GIO: GIO[102]  
SPI3: Slave Input Master Output Data Signal  
Input Standard ISIF Analog Front End (AFE): raw[13]  
YIN5(6) / GIO101  
/SPI3_SCS[0]  
ISIF /  
GIO /  
SPI3  
YCC 16-bit: time multiplexed between luma: Y[05]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the lower channel. Y/CB/CR[05]  
GIO: GIO[101]  
SPI3: Chip Select 0  
YIN4(6) / GIO100 /  
SPI3_SOMI /  
SPI3_SCS[1]  
ISIF /  
GIO /  
SPI3  
Input Standard ISIF Analog Front End (AFE): raw[12]  
YCC 16-bit: time multiplexed between luma: Y[04]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the lower channel. Y/CB/CR[04]  
GIO: GIO[100]  
SPI3: Slave Output Master Input Data Signal  
SPI3: Chip Select 1  
(6) The Y input (YIN[7:0]) and C input (CIN[7:0]) buses can be swapped by programming the field bit YCINSWP in the VPFE CCD  
Configuration (CCDCFG) register (0x01C7 0136h).  
IF YCINSWP bit is 0 (default) YIN[7:0] = Y signal / CIN[7:0] = C signal .  
IF YCINSWP bit is 1 YIN[7:0] = C signal / CIN[7:0] = Y signal  
For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8).  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
YIN3(6) / GIO99  
YIN2(6) / GIO98  
YIN1(6) / GIO97  
YIN0(7) / GIO96  
A14  
B15  
D14  
D15  
I/O  
I/O  
I/O  
I/O  
ISIF /  
GIO  
VDD_ISIF18_33  
VDD_ISIF18_33  
VDD_ISIF18_33  
VDD_ISIF18_33  
IPD  
IPD  
IPD  
IPD  
Input Standard ISIF Analog Front End (AFE): raw[11]  
YCC 16-bit: time multiplexed between luma: Y[03]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the lower channel. Y/CB/CR[03]  
GIO: GIO[99]  
ISIF /  
GIO  
Input Standard ISIF Analog Front End (AFE): raw[10]  
YCC 16-bit: time multiplexed between luma: Y[02]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the lower channel. Y/CB/CR[02]  
GIO: GIO[98]  
ISIF /  
GIO  
Input Standard ISIF Analog Front End (AFE): raw[09]  
YCC 16-bit: time multiplexed between luma: Y[01]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the lower channel. Y/CB/CR[01]  
GIO: GIO[97]  
ISIF /  
GIO  
Input Standard ISIF Analog Front End (AFE): raw[08]  
YCC 16-bit: time multiplexed between luma: Y[00]  
YCC 08-bit (which allows for 2 simultaneous decoder  
inputs), it is time multiplexed between luma and  
chroma of the lower channel. Y/CB/CR[00]  
GIO: GIO[96]  
HD / GIO95  
VD / GIO94  
C14  
B14  
E13  
I/O  
I/O  
I/O  
ISIF /  
GIO  
VDD_ISIF18_33  
VDD_ISIF18_33  
VDD_ISIF18_33  
IPD  
IPD  
IPD  
Input Horizontal synchronization signal that can be either  
an input (slave mode) or an output (master mode).  
Tells the ISIF when a new line starts.  
GIO: GIO[95]  
ISIF /  
GIO  
Input Vertical synchronization signal that can be either an  
input (slave mode) or an output (master mode). Tells  
the ISIF when a new frame starts.  
GIO: GIO[94]  
C_WE_FIELD /  
GIO93 / CLKOUT0  
/ USBDRVVBUS  
ISIF /  
GIO /  
CLKOU  
T / USB  
Input Write enable input signal is used by external device  
(AFE/TG) to gate the DDR output of the ISIF module.  
Alternately, the field identification input signal is used  
by external device (AFE/TG) to indicate the which of  
two frames is input to the ISIF module for sensors  
with interlaced output. ISIF handles 1- or 2-field  
sensors in hardware.  
GIO: GIO[93]  
CLKOUT0: Clock Output  
USB: Digital output to control external 5 V supply  
Input Pixel clock input (strobe for lines CI7 through YI0)  
PCLK  
D13  
I/O/Z ISIF  
VDD_ISIF18_33  
IPD  
(7) The Y input (YIN[7:0]) and C input (CIN[7:0]) buses can be swapped by programming the field bit YCINSWP in the VPFE CCD  
Configuration (CCDCFG) register (0x01C7 0136h).  
IF YCINSWP bit is 0 (default) YIN[7:0] = Y signal / CIN[7:0] = C signal .  
IF YCINSWP bit is 1 YIN[7:0] = C signal / CIN[7:0] = Y signal  
For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8).  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
YOUT7(R7)(8)  
G16  
G19  
F15  
F18  
F16  
F19  
F17  
E16  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VENC  
VENC  
VENC  
VENC  
VENC  
VENC  
VENC  
VENC  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
Input Digital Video Out: VENC settings determine  
function(9)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
YOUT6(R6)(8)  
YOUT5(R5)(8)  
YOUT4(R4)(8)  
YOUT3(R3)(8)  
YOUT2(G7)(8)  
YOUT1(G6)(10)  
YOUT0(G5)(10)  
Input Digital Video Out: VENC settings determine  
function(9)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
Input Digital Video Out: VENC settings determine  
function(9)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
Input Digital Video Out: VENC settings determine  
function(9)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
Input Digital Video Out: VENC settings determine  
function(9)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
Input Digital Video Out: VENC settings determine  
function(9)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
Input Digital Video Out: VENC settings determine  
function(11)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
Input Digital Video Out: VENC settings determine  
function(11)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
HSYNC / GIO84  
VSYNC / GIO83  
LCD_OE / GIO82  
G15  
G18  
C19  
I/O  
I/O  
I/O  
VENC /  
GIO  
VDDS33  
VDDS33  
VDDS33  
Input Video Encoder: Horizontal Sync(11)  
GIO: GIO[84]  
Input Video Encoder: Vertical Sync(11)  
VENC /  
GIO  
GIO: GIO[83]  
(11)  
VENC /  
GIO  
Output Video Encoder: Data valid duration  
GIO: GIO[82]  
(8) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE  
CCD Configuration (CCDCFG) register (0x01C7 0136h). If the YCOUTSWP bit is 0 (default), YOUT[7:0] = Y signal / COUT[7:0] = C  
signal . If the YCOUTSWP bit is 1, YOUT[7:0] = C signal / COUT[7:0] = Y signal. For more information, see the TMS320DM36x Video  
Processing Front End (VPFE) Reference Guide (literature number SPRUFG8).  
(9) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the  
following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should  
be minimized.  
(10) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE  
CCD Configuration (CCDCFG) register (0x01C7 0136h). If the YCOUTSWP bit is 0 (default), YOUT[7:0] = Y signal / COUT[7:0] = C  
signal . If the YCOUTSWP bit is 1, YOUT[7:0] = C signal / COUT[7:0] = Y signal. For more information, see the TMS320DM36x Video  
Processing Front End (VPFE) Reference Guide (literature number SPRUFG8).  
(11) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the  
following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should  
be minimized.  
24  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
GIO80 / EXTCLK /  
B2 / PWM3  
B19  
I/O  
GIO /  
VENC /  
PWM3  
VDDS33  
IPD  
Input GIO: GIO[80]  
Video Encoder: External clock Input, used if clock  
rates > 27 MHz are needed, e.g. 74.25 MHz for  
HDTV digital output.  
Digital Video Out: B2(11)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
PWM3: PWM3 Output  
VCLK / GIO79  
GIO92 /  
B18  
E18  
I/O  
I/O  
VENC /  
GIO  
VDDS33  
Input Video Encoder: Video Output Clock(11)  
GIO: GIO[79]  
GIO /  
VENC /  
PWM0  
VDDS33  
Input GIO: GIO[92]  
COUT7(G4)(10)  
PWM0  
/
/
/
Digital Video Out: VENC settings determine  
function(11)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
PWM0: PWM0 Output  
GIO91 /  
E19  
I/O  
GIO /  
VENC /  
PWM1  
VDDS33  
Input GIO: GIO[91]  
COUT6(G3)(10)  
PWM1  
Digital Video Out: VENC settings determine  
function(11)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
PWM1: PWM1 Output  
GIO90 /  
E15  
I/O  
GIO /  
VDDS33  
Input GIO: GIO[90]  
COUT5(G2)(10)  
PWM2 / RTO0  
VENC  
/PWM2  
/ RTO0  
Digital Video Out: VENC settings determine  
function(11)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
PWM2: PWM2 Output  
RTO0: RTO0 Output  
GIO89 /  
COUT4(B7)  
PWM2 / RTO1  
E17  
I/O  
GIO /  
VDDS33  
Input GIO: GIO[89]  
(12)  
/
VENC /  
PWM2 /  
RTO1  
Digital Video Out: VENC settings determine  
function(13)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
PWM2: PWM2 Output  
RTO1: RTO1 Output  
(12) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE  
CCD Configuration (CCDCFG) register (0x01C7 0136h). If the YCOUTSWP bit is 0 (default), YOUT[7:0] = Y signal / COUT[7:0] = C  
signal . If the YCOUTSWP bit is 1, YOUT[7:0] = C signal / COUT[7:0] = Y signal. For more information, see the TMS320DM36x Video  
Processing Front End (VPFE) Reference Guide (literature number SPRUFG8).  
(13) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the  
following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should  
be minimized.  
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Device Overview  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
GIO88 /  
COUT3(B6)  
PWM2 / RTO2  
D16  
D19  
D18  
I/O  
I/O  
I/O  
GIO /  
VDDS33  
VDDS33  
VDDS33  
Input GIO: GIO[88]  
(12)  
/
/
/
VENC /  
PWM2 /  
RTO2  
Digital Video Out: VENC settings determine  
function(13)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
PWM2: PWM2 Output  
RTO2: RTO2 Output  
GIO87 /  
GIO /  
Input GIO: GIO[87]  
COUT2(B5)(12)  
PWM2 / RTO3  
VENC  
/PWM2  
/ RTO3  
Digital Video Out: VENC settings determine  
function(13)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
PWM2: PWM2 Output  
RTO3: RTO3 Output  
GIO86 /  
GIO /  
VENC /  
PWM3  
Input GIO: GIO[86]  
COUT1(B4)(12)  
PWM3 / STTRIG  
Digital Video Out: VENC settings determine  
function(13)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
PWM3: PWM3 Output  
STTRIG: Camera FLASH control trigger signal  
GIO85 /  
COUT0(B3)  
PWM3  
D17  
I/O  
GIO /  
VENC /  
PWM3  
VDDS33  
Input GIO: GIO[85]  
(14)  
/
Digital Video Out: VENC settings determine  
function(15)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
PWM3: PWM3 Output  
GIO81(OSCCFG) /  
LCD_FIELD / R2 /  
PWM3  
C18  
I/O  
GIO /  
VENC /  
PWM3  
VDDS33  
Input GIO: GIO[81]  
Note: This pin will be used as oscillator configuration  
(OSCCFG). The GIO81(OSCCFG) state is latched  
during reset, and it specifies the oscillation frequency  
range mode of the pin. See Section 3.7.6 for more  
details.  
Video Encoder: Field identifier for interlaced display  
formats(15)  
.
For more details, see the DM36x DMSoC Video  
Processor Back End User's Guide (SPRUFG9).  
Digital Video Out: R2(15)  
PWM3: PWM3 Output  
(14) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE  
CCD Configuration (CCDCFG) register (0x01C7 0136h). If the YCOUTSWP bit is 0 (default), YOUT[7:0] = Y signal / COUT[7:0] = C  
signal . If the YCOUTSWP bit is 1, YOUT[7:0] = C signal / COUT[7:0] = Y signal. For more information, see the TMS320DM36x Video  
Processing Front End (VPFE) Reference Guide (literature number SPRUFG8).  
(15) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the  
following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should  
be minimized.  
26  
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SPRS457C–MARCH 2009–REVISED APRIL 2010  
Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
VREF  
IREF  
D11  
A I/O Video  
DAC  
VDDA18_DAC  
Video DAC: Reference voltage for DAC.  
For more details, see Section 6.12.2.4, DAC and  
Video Buffer Electrical Data/Timing.  
Note: If the DAC peripheral is not used, this pin must  
be tied directly to VSS for proper device operation.  
A11  
A I/O Video  
DAC  
VDDA18_DAC  
Video DAC: Sets reference current for DAC. An  
external resistor with nominal value, 2400 ohms, is  
connected between IREF and VSS  
.
For more details, see Section 6.12.2.4, DAC and  
Video Buffer Electrical Data/Timing.  
Note: If the DAC peripheral is not used, this pin must  
be tied directly to VSS for proper device operation.  
IDACOUT  
B11  
B10  
A10  
A I/O Video  
DAC  
VDDA18_DAC  
VDDA18_DAC  
VDDA18_DAC  
Video DAC: Current source input from DAC. An  
external resistor with nominal value, 2100 ohms, is  
connected between IDACOUT and VFB.  
For more details, see Section 6.12.2.4, DAC and  
Video Buffer Electrical Data/Timing.  
Note: If the DAC peripheral is not used at all in the  
application, this pin can either be connected to VSS or  
be left open.  
VFB  
A I/O Video  
DAC  
Video DAC: Amplifier feedback node. An external  
resistor with nominal value, 2150 ohms, is connected  
between VFB and TVOUT.  
For more details, see Section 6.12.2.4, DAC and  
Video Buffer Electrical Data/Timing.  
Note: If the DAC peripheral is not used at all in the  
application, this pin can either be connected to VSS or  
be left open.  
TVOUT  
A I/O Video  
DAC  
Video DAC: DAC1video output. An external resistor  
with nominal value, 2150 ohms, is connected  
between TVOUT and VFB. This is the output node  
that drives the load (75 ohms).  
For more details, see Section 6.12.2.4, DAC and  
Video Buffer Electrical Data/Timing.  
Note: If the DAC peripheral is not used at all in the  
application, this pin can either be connected to VSS or  
be left open.  
COMPY  
B12  
A12  
A O Video  
DAC  
VDDA18_DAC  
Video DAC: Analog video signal component output Y  
Note: If the DAC peripheral is not used at all in the  
application, this pin can either be connected to VSS or  
be left open.  
COMPPB  
A O Video  
DAC  
VDDA18_DAC  
Video DAC: Analog video signal component output  
Pb  
Note: If the DAC peripheral is not used at all in the  
application, this pin can either be connected to VSS or  
be left open.  
COMPPR  
C11  
A O Video  
DAC  
VDDA18_DAC  
Video DAC: Analog video signal component output  
Pr  
Note: If the DAC peripheral is not used at all in the  
application, this pin can either be connected to VSS or  
be left open.  
VDDA18_DAC  
D10  
E12  
PWR Video  
DAC  
VDDA18_DAC  
Video DAC: Analog 1.8-V power  
Note: If the DAC peripheral is not used, this pin must  
be tied directly to VSS for proper device operation.  
VDDA12_DAC  
PWR Video  
Dac  
VDDA12_DAC  
Video DAC: Analog 1.2-V power  
Note: If the DAC peripheral is not used, this pin must  
be tied directly to VSS for proper device operation.  
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Table 2-5. Pin Descriptions (continued)  
Name  
VSSA18_DAC  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
E11  
GND Video  
DAC  
Video DAC: Analog 1.8-V ground  
Note: If the DAC peripheral is not used, this pin must  
be tied directly to VSS for proper device operation.  
VSSA12_DAC  
F11  
GND Video  
DAC  
Video DAC: Analog 1.2-V ground  
Note: If the DAC peripheral is not used, this pin must  
be tied directly to VSS for proper device operation.  
DDR_CLK  
DDR_CLK  
DDR_RAS  
DDR_CAS  
DDR_WE  
W11  
W12  
U12  
V12  
W13  
T12  
R13  
W6  
O
O
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
DDR Data Clock  
DDR Complementary Data Clock  
DDR Row Address Strobe  
DDR Column Address Strobe  
DDR Write Enable  
O
O
O
DDR_CS  
O
DDR Chip Select  
DDR_CKE  
DDR_DQM[1]  
DDR_DQM[0]  
DDR_DQS[1]  
O
DDR Clock Enable  
O
Data mask input for DDR_DQ[15:8]  
Data mask input for DDR_DQ[7:0]  
T11  
T7  
O
I/O  
Data strobe input/outputs for each byte of the 16-bit  
data bus used to synchronize the data transfers.  
Output to DDR2 when writing and inputs when  
reading. They are used to synchronize the data  
transfers.  
DDR_DQS1: For DDR_DQ[15:8]  
DDR_DQS[0]  
DDR_DQSN[1]  
DDR_DQSN[0]  
T10  
U6  
I/O  
I/O  
I/O  
DDR  
DDR  
DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
Data strobe input/outputs for each byte of the 16-bit  
data bus used to synchronize the data transfers.  
Output to DDR2 when writing and inputs when  
reading. They are used to synchronize the data  
transfers.  
DDR_DQS0: For DDR_DQ[7:0]  
DDR: Complimentary data strobe input/outputs for  
each byte of the 16-bit data bus. They are outputs to  
the DDR2 when writing and inputs when reading.  
They are used to synchronize the data transfers.  
Note: This signal is used in double ended differential  
memory interfaces supported by the device.  
U9  
DDR: Complimentary data strobe input/outputs for  
each byte of the 16-bit data bus. They are outputs to  
the DDR2 when writing and inputs when reading.  
They are used to synchronize the data transfers.  
Note: This signal is used in double ended differential  
memory interfaces supported by the device.  
DDR_BA[2]  
DDR_BA[1]  
DDR_BA[0]  
V13  
T13  
O
O
O
DDR  
DDR  
DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
Bank select outputs. Two are required for 1Gb DDR2  
memories.  
Bank select outputs. Two are required for 1Gb DDR2  
memories.  
W14  
Bank select outputs. Two are required for 1Gb DDR2  
memories.  
DDR_A13  
DDR_A12  
DDR_A11  
DDR_A10  
DDR_A9  
DDR_A8  
DDR_A7  
DDR_A6  
T16  
V17  
W18  
V16  
U16  
W17  
T15  
O
O
O
O
O
O
O
O
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
DDR Address Bus bit 13  
DDR Address Bus bit 12  
DDR Address Bus bit 11  
DDR Address Bus bit 10  
DDR Address Bus bit 09  
DDR Address Bus bit 08  
DDR Address Bus bit 07  
DDR Address Bus bit 06  
W16  
28  
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SPRS457C–MARCH 2009–REVISED APRIL 2010  
Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
DDR_A5  
V15  
U15  
T14  
W15  
V14  
U14  
V6  
O
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
VDD18_DDR  
DDR Address Bus bit 05  
DDR_A4  
O
DDR Address Bus bit 04  
DDR Address Bus bit 03  
DDR Address Bus bit 02  
DDR Address Bus bit 01  
DDR Address Bus bit 00  
DDR Data Bus bit 15  
DDR Data Bus bit 14  
DDR Data Bus bit 13  
DDR Data Bus bit 12  
DDR Data Bus bit 11  
DDR Data Bus bit 10  
DDR Data Bus bit 09  
DDR Data Bus bit 08  
DDR Data Bus bit 07  
DDR Data Bus bit 06  
DDR Data Bus bit 05  
DDR Data Bus bit 04  
DDR Data Bus bit 03  
DDR Data Bus bit 02  
DDR Data Bus bit 01  
DDR Data Bus bit 00  
DDR_A3  
O
DDR_A2  
O
DDR_A1  
O
DDR_A0  
O
DDR_DQ15  
DDR_DQ14  
DDR_DQ13  
DDR_DQ12  
DDR_DQ11  
DDR_DQ10  
DDR_DQ9  
DDR_DQ8  
DDR_DQ7  
DDR_DQ6  
DDR_DQ5  
DDR_DQ4  
DDR_DQ3  
DDR_DQ2  
DDR_DQ1  
DDR_DQ0  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
V7  
R7  
W7  
V8  
R8  
U8  
W8  
R9  
W9  
V9  
W10  
V10  
R10  
V11  
U11  
T8  
DDR_  
DQGATE0  
DDR: Loopback signal for external DQS gating.  
Route to DDR and back to DDR_DQGATE1 with  
same constraints as used for DDR clock and data.  
DDR_  
DQGATE1  
T9  
I
DDR  
VDD18_DDR  
DDR: Loopback signal for external DQS gating.  
Route to DDR and back to DDR_DQGATE0 with  
same constraints as used for DDR clock and data.  
DDR_VREF  
P11  
PWR DDR  
VDD18_DDR  
DDR: DDR_VREF is .5* VDD18_DDR = 0.9V for SSTL2  
specific reference voltage.  
DDR_PADREFP  
R11  
V18  
O
DDR  
VDD18_DDR  
DDR: External resistor ( 50 ohm to ground)  
EM_A13 / GIO78 /  
BTSEL[2]  
I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD  
Input Async EMIF: Address Bus bit[13]  
GIO /  
BTSEL[  
2]  
disable  
d by  
default  
33  
GIO: GIO[78]  
BTSEL[2]: See Section 3.2, Device Boot Modes for  
system usage of these pins.  
EM_A12 / GIO77 /  
BTSEL[1]  
U18  
I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD  
Input Async EMIF: Address Bus bit[12]  
GIO /  
BTSEL[  
1]  
disable  
d by  
default  
33  
GIO: GIO[77]  
BTSEL[1]: See Section 3.2, Device Boot Modes for  
system usage of these pins.  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
EM_A11 / GIO76 /  
BTSEL[0]  
V19  
I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD  
Input Async EMIF: Address Bus bit[11]  
GIO /  
BTSEL[  
0]  
disable  
d by  
default  
33  
GIO: GIO[76]  
BTSEL[0]: See Section 3.2, Device Boot Modes for  
system usage of these pins.  
EM_A10 / GIO75 /  
AECFG[2]  
U19  
I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD  
Input Async EMIF: Address Bus bit[10]  
GIO /  
AECFG  
[2]  
disable  
d by  
default  
33  
GIO: GIO[75]  
AECFG[2]: See Section 3.2, Device Boot Modes and  
Table 3-14, AECFG (Async EMIF Configuration) for  
system usage of these pins.  
EM_A9 / GIO74 /  
AECFG[1]  
T18  
I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD  
Input Async EMIF: Address Bus bit[09]  
GIO /  
AECFG  
[1]  
disable  
d by  
default  
33  
GIO: GIO[74]  
AECFG[1]: See Section 3.2, Device Boot Modes and  
Table 3-14, AECFG (Async EMIF Configuration) for  
system usage of these pins.  
EM_A8 / GIO73 /  
AECFG[0]  
T19  
I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD  
Input Async EMIF: Address Bus bit[08]  
GIO /  
AECFG  
[0]  
disable  
d by  
default  
33  
GIO: GIO[73]  
AECFG[0]: See Section 3.2, Device Boot Modes and  
Table 3-14, AECFG (Async EMIF Configuration) for  
system usage of these pins.  
EM_A7 / GIO72 /  
KEYA3  
T17  
R18  
R16  
R19  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Address Bus bit[07]  
GIO /  
33  
KEYSC  
AN  
GIO: GIO[72]  
Keyscan: A3  
EM_A6 / GIO71 /  
KEYA2  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Address Bus bit[06]  
GIO /  
33  
KEYSC  
AN  
GIO: GIO[71]  
Keyscan: A2  
EM_A5 / GIO70 /  
KEYA1  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Address Bus bit[05]  
GIO /  
33  
KEYSC  
AN  
GIO: GIO[70]  
Keyscan: A1  
EM_A4 / GIO69 /  
KEYA0  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Address Bus bit[04]  
GIO/KE  
33  
YSCAN  
GIO: GIO[69]  
Keyscan: A0  
30  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
EM_A3 / GIO68 /  
KEYB3  
R15  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Address Bus bit[03]  
GIO/  
33  
KEYSC  
AN  
GIO: GIO[68]  
Keyscan: B3  
EM_A2 / HCNTLA  
M18  
I/O/Z AEMIF/ VDD_AEMIF2_18_  
Output Async EMIF: Address Bus bit[02]  
HPI  
33  
HPI: The state of HCNTLA and HCNTLB determines  
if address, data, or control information is being  
transmitted between an external host and the device.  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_A1 / HHWIL  
M19  
L17  
I/O/Z AEMIF/ VDD_AEMIF2_18_  
Output Async EMIF: Address Bus bit[01]  
HPI  
33  
HPI: This pin is half-word identification input HHWIL.  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_A0 / GIO67 /  
KEYB2 / HCNTLB  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Input Async EMIF: Address Bus bit[00] Note that the  
EM_A0 is always a 32-bit address  
GIO /  
33  
KEYSC  
AN /  
HPI  
GIO: GIO[56]  
Keyscan: B2  
HPI: The state of HCNTLA and HCNTLB determines  
if address, data, or control information is being  
transmitted between an external host and the device.  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_BA1 / GIO66 /  
KEYB1 / HINTN  
R17  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Bank Address 1 signal = 16-bit  
address.  
GIO /  
33  
KEYSC  
AN /  
In 16-bit mode, lowest address bit.  
In 8-bit mode, second lowest address bit  
HPI  
GIO: GIO[66]  
Keyscan: B1  
HPI: This pin is host interrupt output HINT  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_BA0 / EM_A14  
/ GIO65 / KEYB0  
P17  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Bank Address 0 signal = 8-bit address.  
In 8-bit mode, lowest address bit.  
GIO /  
33  
KEYSC  
AN  
Async EMIF: Address line (bit[14] when using 16-bit  
memories.  
GIO: GIO[65]  
Keyscan: B0  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
EM_D15 / GIO64 /  
HD15  
P18  
P16  
P19  
P15  
N16  
N18  
N19  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Data Bus bit[15]  
GIO /  
33  
HPI  
GIO: GIO[64]  
HPI: Data bus bit [15]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_D14 / GIO63 /  
HD14  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Data Bus bit[14]  
GIO /  
33  
HPI  
GIO: GIO[63]  
HPI: Data bus bit [14]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_D13 / GIO62 /  
HD13  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Data Bus bit[13]  
GIO /  
33  
HPI  
GIO: GIO[62]  
HPI: Data bus bit [13]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_D12 / GIO61 /  
HD12  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Data Bus bit[12]  
GIO /  
33  
HPI  
GIO: GIO[61]  
HPI: Data bus bit [12]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_D11 / GIO60 /  
HD11  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Data Bus bit[11]  
GIO /  
33  
HPI  
GIO: GIO[60]  
HPI: Data bus bit [11]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_D10 / GIO59 /  
HD10  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Data Bus bit[10]  
GIO /  
33  
HPI  
GIO: GIO[59]  
HPI: Data bus bit [10]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_D9 / GIO58 /  
HD9  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Data Bus bit[09]  
GIO /  
33  
HPI  
GIO: GIO[58]  
32  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
HPI: Data bus bit [9]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_D8 / GIO57 /  
HD8  
N15  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Input Async EMIF: Data Bus bit[08]  
GIO /  
33  
HPI  
GIO: GIO[57]  
HPI: Data bus bit [8]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_D7 / HD7  
EM_D6 / HD6  
EM_D5 / HD5  
EM_D4 / HD4  
EM_D3 / HD3  
EM_D2 / HD2  
L16  
L18  
L19  
L15  
K15  
K19  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Input Async EMIF: Data Bus bit[07]  
HPI  
33  
HPI: Data bus bit [7]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Input Async EMIF: Data Bus bit[06]  
HPI  
33  
HPI: Data bus bit [6]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Input Async EMIF: Data Bus bit[05]  
HPI  
33  
HPI: Data bus bit [5]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Input Async EMIF: Data Bus bit[04]  
HPI  
33  
HPI: Data bus bit [4]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Input Async EMIF: Data Bus bit[03]  
HPI  
33  
HPI: Data bus bit [3]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Input Async EMIF: Data Bus bit[02]  
HPI  
33  
HPI: Data bus bit [2]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
EM_D1 / HD1  
K16  
K18  
M17  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Input Async EMIF: Data Bus bit[01]  
HPI  
33  
HPI: Data bus bit [1]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_D0 / HD0  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Input Async EMIF: Data Bus bit[00]  
HPI  
33  
HPI: Data bus bit [0]  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_CE[0] / GIO56  
/ HCS  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Output Async EMIF: Lowest numbered Chip Select. Can be  
programmed to be used for standard asynchronous  
memories (example:flash), OneNand or NAND  
memory. Used for the default boot and ROM boot  
modes.  
GIO /  
33  
HPI  
GIO: GIO[56]  
HPI: this pin is HPI chip select input.  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_CE[1] / GIO55  
/ HAS  
J17  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Output Async EMIF: Second Chip Select., Can be  
programmed to be used for standard asynchronous  
memories (example: flash), OneNand or NAND  
memory.  
GIO /  
33  
HPI  
GIO: GIO[55]  
HPI: This pin is host address strobe.  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_WE / GIO54 /  
HDS2  
J15  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Output Async EMIF: Write Enable  
GIO /  
33  
HPI  
GIO: GIO[54]  
HPI: This pin is host data strobe input 2.  
Note: HPI is pin multiplexed with Asynchronous  
EMIF at the output pin. HPI is available only when  
boot mode selected is HPI boot mode. In this  
configuration, the device will always act as a slave.  
EM_OE / GIO53 /  
HDS1  
J19  
J18  
I/O/Z AEMIF / VDD_AEMIF2_18_  
Output Async EMIF: Output Enable  
GIO /  
33  
HPI  
GIO: GIO[53]  
HPI: This pin is host data strobe input 1.  
Input Async EMIF: Async WAIT  
EM_WAIT / GIO52  
/ HRDY  
I/O/Z AEMIF / VDD_AEMIF2_18_  
IPU  
GIO /  
33  
HPI  
GIO: GIO[52]  
HPI: This pin is host ready output from DSP to host.  
EM_ADV / GIO51 /  
HR/W  
M16  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Output Async EMIF: Address Valid Detect for OneNAND  
interface  
GIO /  
33  
HPI  
GIO: GIO[51]  
34  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
HPI: This pin is host read or write select input.  
EM_CLK / GIO50  
M15  
D5  
A5  
C6  
E6  
B6  
E7  
T6  
I/O/Z AEMIF / VDD_AEMIF1_18_  
Output Async EMIF: Clock signal for OneNAND flash  
interface  
GIO  
33  
GIO: GIO[50]  
GIO49 /  
McBSP_DX  
I/O/Z GIO /  
McBSP  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
Input GIO: GIO[49]  
McBSP: Transmit Data  
Input GIO: GIO[48]  
GIO48 /  
McBSP_CLKX  
I/O/Z GIO /  
McBSP  
McBSP: Transmit Clock  
Input GIO: GIO[47]  
GIO47 /  
McBSP_FSX  
I/O/Z GIO /  
McBSP  
McBSP: Transmit Frame Sync  
Input GIO: GIO[46]  
GIO46 /  
McBSP_DR  
I/O/Z GIO /  
McBSP  
McBSP: Receive Data  
Input GIO: GIO[45]  
GIO45 /  
McBSP_CLKR  
I/O/Z GIO /  
McBSP  
McBSP: Receive Clock  
Input GIO: GIO[44]  
GIO44 /  
McBSP_FSR  
I/O/Z GIO /  
McBSP  
McBSP: Receive Frame Sync  
Input GIO: GIO[43]  
GIO43 /  
MMCSD1_CLK /  
EM_A20  
I/O/Z GIO /  
MMCS  
D1 /  
AEMIF  
MMCSD1: Clock  
Async EMIF: Address bit[20]  
Input GIO: GIO[42]  
GIO42 /  
MMCSD1_CMD /  
EM_A19  
R6  
W5  
U5  
R5  
I/O/Z GIO /  
MMCS  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
IPD  
IPD  
IPD  
IPD  
D1 /  
AEMIF  
MMCSD1: Command  
Async EMIF: Address bit[19]  
Input GIO: GIO[41]  
GIO41 /  
MMCSD1_DATA3 /  
EM_A18  
I/O/Z GIO /  
MMCS  
D /  
AEMIF  
MMCSD1: DATA3  
Async EMIF: Address bit[18]  
Input GIO: GIO[40]  
GIO40 /  
MMCSD1_DATA2 /  
EM_A17  
I/O/Z GIO /  
MMCS  
D1 /  
AEMIF  
MMCSD1: DATA2  
Async EMIF: Address bit[17]  
Input GIO: GIO[39]  
GIO39 /  
MMCSD1_DATA1 /  
EM_A16  
I/O/Z GIO /  
MMCS  
D1 /  
AEMIF  
MMCSD1: DATA1  
Async EMIF: Address bit[16]  
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Table 2-5. Pin Descriptions (continued)  
Name  
GIO38 /  
MMCSD1_DATA0 /  
EM_A15  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
V5  
I/O/Z GIO /  
MMCS  
VDDS33  
IPD  
Input GIO: GIO[38]  
D1 /  
AEMIF  
MMCSD1: DATA0  
Async EMIF: Address bit[15]  
Input GIO: GIO[37]  
GIO37 /  
T5  
I/O/Z GIO /  
VDDS33  
IPD  
SPI4_SCS[0]/  
McBSP_CLKS /  
CLKOUT0  
SPI4 /  
McBSP  
/
CLKOU  
T
SPI4: SPI4 Chip Select 0  
McBSP: CLKS pin to source an external clock  
CLKOUT: Output Clock 0  
GIO36 /  
SPI4_SCLK /  
EM_A21 / EM_A14  
W4  
W3  
I/O/Z GIO /  
SPI4 /  
VDDS33  
IPD  
IPD  
Input GIO: GIO[36]  
AEMIF  
SPI4: Clock  
Async EMIF: Address bit[21]  
Async EMIF: Address bit[14]  
GIO35 /  
I/O/Z GIO /  
SPI4  
VDDS33  
Input GIO: GIO[35]  
SPI4_SOMI /  
SPI4_SCS[1] /  
CLKOUT1  
/CLKO  
UT  
SPI4: Slave Out Master In data  
SPI4: SPI4 Chip Select 1  
CLKOUT: Output Clock 1  
GIO34 /  
V4  
V3  
I/O/Z GIO /  
SPI4 /  
VDDS33  
IPD  
IPD  
Input GIO: GIO[34]  
SPI4_SIMO /  
SPI4_SOMI /  
UART1_RXD  
UART1  
SPI4: Slave In Master Out data  
SPI4: Slave Out Master In data.  
UART1: RXD  
GIO33 /  
I/O/Z GIO /  
SPI2 /  
VDDS33  
Input GIO: GIO[33]  
SPI2_SCS[0] /  
USBDRVVBUS /  
R1  
USB  
/VENC  
SPI3: SPI3 Chip Select 0  
USB: USB: Digital output to control external 5 V  
supply  
VENC: Red output data bit 1  
GIO32 /  
SPI2_SCLK / R0  
W2  
U4  
I/O/Z GIO /  
SPI2 /  
VDDS33  
IPD  
IPD  
Input GIO: GIO[32]  
VENC  
SPI2: Clock  
VENC: Red output data bit 0  
GIO31 /  
I/O/Z GIO /  
SPI2 /  
VDDS33  
Input GIO: GIO[31]  
SPI2_SOMI /  
SPI2_SCS[1] /  
CLKOUT2  
CLKOU  
T
SPI2: Slave Out Master In data  
SPI2: SPI2 Chip Select 1  
36  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
CLKOUT: Output Clock 2  
Input GIO: GIO[30]  
GIO30 /  
SPI2_SIMO / G1  
T4  
U2  
V1  
T2  
I/O/Z GIO /  
SPI2 /  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
IPD  
IPD  
IPD  
IPD  
VENC  
SPI2: Slave In Master Out data  
VENC: Green output data bit 1  
Input GIO: GIO[29]  
GIO29 /  
SPI1_SCS[0] / G0  
I/O/Z GIO /  
SPI1 /  
VENC  
SPI1: SPI1 Chip Select 0  
VENC: Green output data bit 0  
GIO28 /  
SPI1_SCLK / B1  
I/O/Z GIO /  
SPI1 /  
Input GIO: GIO[28]  
VENC  
SPI1: Clock  
VENC: Blue output data bit 1  
GIO27 /  
SPI1_SOMI /  
SPI1_SCS[1] / B0  
I/O/Z GIO /  
SPI1 /  
Input GIO: GIO[27]  
VENC  
SPI1: Slave Out Master In data  
SPI1: SPI1 Chip Select 1  
VENC: Blue output data bit 1  
GIO26 /  
SPI1_SIMO  
U1  
T1  
I/O/Z GIO /  
SPI1  
VDDS33  
IPD  
IPD  
Input GIO: GIO[26]  
SPI1: Slave In Master Out data  
Input GIO: GIO[25]  
GIO25 /  
SPI0_SCS[0] /  
PWM1 /  
I/O/Z GIO /  
SPI0 /  
VDDS33  
PWM1 /  
UART1  
UART1_TXD  
SPI0: SPI0 Chip Select 0  
PWM1: Output  
UART1: Transmit data  
GIO24 /  
SPI0_SCLK  
T3  
V2  
I/O/Z GIO /  
SPI0  
VDDS33  
IPD  
IPD  
Input GIO: GIO[24]  
SPI0: Clock  
GIO23 /  
I/O/Z GIO /  
SPI0 /  
VDDS33  
Input GIO: GIO[23]  
SPI0_SOMI /  
SPI0_SCS[1] /  
PWM0  
PWM0  
SPI0: Slave Out Master In data  
SPI0: SPI0 Chip Select 1  
PWM0: Output  
GIO22 /  
SPI0_SIMO  
R2  
F3  
I/O/Z GIO /  
SPI0  
VDDS33  
IPD  
IPD  
Input GIO: GIO[22]  
SPI0: Slave In Master Out data  
Input GIO: GIO[21]  
GIO21 /  
UART1_RTS /  
I2C_SDA  
I/O/Z GIO /  
UART1  
VDDS33  
/ I2C  
UART1: RTS  
I2C: Serial Data  
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Table 2-5. Pin Descriptions (continued)  
Name  
GIO20 /  
UART1_CTS /  
I2C_SCL  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
F1  
I/O/Z GIO /  
UART1  
VDDS33  
IPD  
Input GIO: GIO[20]  
/ I2C  
UART1: CTS  
I2C: Serial Clock  
GIO19 /  
UART0_RXD  
E3  
E2  
E4  
I/O/Z GIO /  
UART0  
VDDS33  
VDDS33  
VDDS33  
IPD  
IPD  
IPD  
Input GIO: GIO[19]  
UART0: Receive data  
Input GIO: GIO[18]  
GIO18 /  
UART0_TXD  
I/O/Z GIO /  
UART0  
UART0: Transmit data  
Input GIO: GIO[17]  
GIO17 /  
EMAC_TX_EN /  
UART1_RXD  
I/O/Z GIO /  
EMAC /  
UART1  
EMAC: Transmit enable output  
UART1: Receive Data  
GIO16 /  
EMAC_TX_CLK /  
UART1_TXD  
E1  
I/O/Z GIO /  
EMAC /  
VDDS33  
IPD  
Input GIO: GIO[16]  
UART1  
EMAC: Transmit clock  
UART1: Transmit Data  
GIO15 /  
EMAC_COL  
D2  
D1  
D3  
C1  
B1  
B2  
C2  
A2  
A3  
B3  
I/O/Z GIO /  
EMAC  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
Input GIO: GIO[15]  
EMAC: Collision Detect input  
Input GIO: GIO[14]  
GIO14 /  
EMAC_TXD3  
I/O/Z GIO /  
EMAC  
EMAC: Transmit Data 3 output  
Input GIO: GIO[13]  
GIO13 /  
EMAC_TXD2  
I/O/Z GIO /  
EMAC  
EMAC: Transmit Data 2 output  
Input GIO: GIO[12]  
GIO12 /  
EMAC_TXD1  
I/O/Z GIO /  
EMAC  
EMAC: Transmit Data 1 output  
Input GIO: GIO[11]  
GIO11 /  
EMAC_TXD0  
I/O/Z GIO /  
EMAC  
EMAC: Transmit Data 0 output  
Input GIO: GIO[10]  
GIO10 /  
EMAC_RXD3  
I/O/Z GIO /  
EMAC  
EMAC: Receive Data 3 output  
Input GIO: GIO[09]  
GIO9 /  
EMAC_RXD2  
I/O/Z GIO /  
EMAC  
EMAC: Receive Data 2 output  
Input GIO: GIO[08]  
GIO8 /  
EMAC_RXD1  
I/O/Z GIO /  
EMAC  
EMAC: Receive Data 1 output  
Input GIO: GIO[07]  
GIO7 /  
EMAC_RXD0  
I/O/Z GIO /  
EMAC  
EMAC: Receive Data 0 output  
Input GIO: GIO[06]  
GIO6 /  
EMAC_RX_CLK  
I/O/Z GIO /  
EMAC  
EMAC: Receive clock  
38  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
GIO5 /  
EMAC_RX_DV  
B4  
A4  
C5  
C4  
D6  
I/O/Z GIO /  
EMAC  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
Input GIO: GIO[05]  
EMAC: Receive data valid input  
Input GIO: GIO[04]  
GIO4 /  
EMAC_RX_ER  
I/O/Z GIO /  
EMAC  
EMAC: Receive error input  
Input GIO: GIO[03]  
GIO3 /  
EMAC_CRS  
I/O/Z GIO /  
EMAC  
EMAC: Carrier sense input  
Input GIO: GIO[02]  
GIO2 / MDIO  
I/O/Z GIO /  
EMAC  
EMAC: Management Data I/O  
Input GIO: GIO[01]  
GIO1 / MDCLK  
I/O/Z GIO /  
EMAC  
EMAC: Management Data clock output  
Input GIO: GIO[00]  
USB D+ (differential signal pair)  
GIO0  
B5  
N1  
I/O/Z GIO  
VDDS33  
USB_DP  
A I/O USBPH  
Y
VDDA33_USB  
Note: If the USB peripheral is not used at all in the  
application, this pin should be connected to 3.3V .  
USB_DM  
P1  
P4  
A I/O USBPH  
Y
VDDA33_USB  
USB D- (differential signal pair)  
Note: If the USB peripheral is not used at all in the  
application, this pin should be connected to VSS  
.
VDDA33_USB  
PWR  
GND  
PWR  
3.3-V USB analog power supply  
Note: If the USB peripheral is not used at all in the  
application, this pin should be connected to 3.3V.  
VSSA33_USB  
P3  
3.3-V USB ground  
Note: If the USB peripheral is not used at all in the  
application, this pin should be connected to VSS  
.
VDDA12LDO_USB  
M5  
Output For proper device operation, even if the USB  
peripheral is not used, a 0.22µF capacitor must be  
connected as close as possible to the package, and  
the capacitor mst be connected to VSSA  
.
VDDA18_USB  
VSSA18_USB  
USB_ID  
N5  
P2  
M1  
PWR  
GND  
1.8-V USB analog power supply  
Note: If the USB peripheral is not used at all in the  
application, this pin should be connected to 1.8V.  
1.8-V USB ground  
Note: If the USB peripheral is not used at all in the  
application, this pin should be connected to VSS  
.
A I  
USBPH  
Y
VDDA33_USB  
USB operating mode identification pin.  
For device mode operation only, pull up this pin to  
VDD with a 1.5K ohm resistor.  
For host mode operation only, pull down this pin to  
ground (VSS) with a 1.5K ohm resistor.  
If using an OTG or mini-USB connector, this pin will  
be set properly via the cable/connector configuration.  
Note: If the USB peripheral is not used at all in the  
application, this pin should be connected to 3.3V.  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
USB_VBUS  
N2  
A I/O USBPH  
Y
USB_VBUS  
This pin is used by the USB Controller to detect a  
presence of 5V power (4.4V is the threshold) on the  
USB_VBUS line for normal operation. This power is  
sourced by the USB Component that is assuming the  
role of a Host. In other words, the power on the  
USB_VBUS line is not sourced by the Device. From  
DM365 perspective, when operating as a Host, it  
ensures that the external power supply that the  
DM365 has sourced is within the required voltage  
level (>= 4.4V) and when DM365 is operating as a  
Device, the presence of a 5V power on the VBUS  
Line is used to signify the presence of an external  
Host.  
Note 1: When the DM365 is operating as a Device, it  
uses the power on the USB_VBUS line to power up  
its internal pull-up resistor on the D+ line.  
Note2: If the USB peripheral is not used at all in the  
application, this pin should be connected to VSS  
.
MMCSD0_CLK  
MMCSD0_CMD  
MMCSD0_DATA3  
MMCSD0_DATA2  
MMCSD0_DATA1  
MMCSD0_DATA0  
MICIP  
J16  
H15  
H16  
H17  
H19  
H18  
B8  
O
MMCS  
D0  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
out  
MMCSD0: Clock  
I/O/Z MMCS  
D0  
Input MMCSD0: Command  
Input MMCSD0: DATA3  
Input MMCSD0: DATA2  
Input MMCSD0: DATA1  
Input MMCSD0: DATA0  
MIC positive input  
I/O/Z MMCS  
D0  
I/O/Z MMCS  
D0  
I/O/Z MMCS  
D0  
I/O/Z MMCS  
D0  
AI  
AI  
VCODE  
C
VDDA33_VC  
or  
VDDA18_VC  
Note: If the Voice Codec peripheral is not used, this  
pin must be tied directly to VSS for proper device  
operation.  
MICIN  
LINEO  
SPP  
C8  
C9  
B9  
VCODE  
C
VDDA33_VC  
or  
VDDA18_VC  
MIC negative input  
Note: If the Voice Codec peripheral is not used, this  
pin must be tied directly to VSS for proper device  
operation.  
AO  
AO  
VCODE  
C
VDDA33_VC  
or  
VDDA18_VC  
Line driver output  
Note: If the Voice Codec peripheral is not used, this  
pin can be left open or can be connected directly to  
Vss for proper device operation.  
VCODE  
C
VDDA33_VC  
or  
Speaker amplifier positive output  
VDDA18_VC  
Note: If the Voice Codec peripheral is not used, this  
pin can be left open or can be connected directly to  
Vss for proper device operation.  
SPN  
A9  
AO  
VCODE  
C
VDDA33_VC  
or  
VDDA18_VC  
Speaker amplifier negative output  
Note: If the Voice Codec peripheral is not used, this  
pin can be left open or can be connected directly to  
Vss for proper device operation.  
40  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
VCOM  
A8  
AI  
VCODE  
C
VDDA33_VC  
or  
VDDA18_VC  
Analog block common voltage.  
It is recommended that a 10µF capacitor be  
connected between this pin and ground to provide  
clean voltage.  
Note: If the Voice Codec peripheral is not used, this  
pin must be tied directly to VSS for proper device  
operation.  
VDDA18_VC  
VSSA18_VC  
VDDA33_VC  
VSSA33_VC  
ADC_CH0  
E9  
F9  
PWR  
GND  
PWR  
GND  
AI  
1.8-V Voice Codec module analog power supply  
Note: If the Voice Codec peripheral is not used, this  
pin must be tied directly to VSS for proper device  
operation.  
1.8-V Voice Codec module ground  
Note: If the Voice Codec peripheral is not used, this  
pin must be tied directly to VSS for proper device  
operation.  
E10  
D9  
E8  
3.3-V Voice Codec module power supply  
Note: If the Voice Codec peripheral is not used, this  
pin must be tied directly to VSS for proper device  
operation.  
3.3-V Voice Codec module ground  
Note: If the Voice Codec peripheral is not used, this  
pin must be tied directly to VSS for proper device  
operation.  
ADC  
ADC  
ADC  
ADC  
ADC  
ADC  
VDDA18_ADC  
VDDA18_ADC  
VDDA18_ADC  
VDDA18_ADC  
VDDA18_ADC  
VDDA18_ADC  
Analog-to-Digital converter channel 0  
Note: If the ADC is not used, it is recommended to  
either leave this pin open, as no connect, or tie this  
pin along with the other ADC_CHs together to a  
single resistor to ground.  
ADC_CH1  
ADC_CH2  
ADC_CH3  
ADC_CH4  
ADC_CH5  
B7  
A7  
D8  
D7  
A6  
AI  
AI  
AI  
AI  
AI  
Analog-to-Digital converter channel 1  
Note: If the ADC is not used, it is recommended to  
either leave this pin open, as no connect, or tie this  
pin along with the other ADC_CHs together to a  
single resistor to ground.  
Analog-to-Digital converter channel  
Note: If the ADC is not used, it is recommended to  
either leave this pin open, as no connect, or tie this  
pin along with the other ADC_CHs together to a  
single resistor to ground.  
Analog-to-Digital converter channel 3  
Note: If the ADC is not used, it is recommended to  
either leave this pin open, as no connect, or tie this  
pin along with the other ADC_CHs together to a  
single resistor to ground.  
Analog-to-Digital converter channel 4  
Note: If the ADC is not used, it is recommended to  
either leave this pin open, as no connect, or tie this  
pin along with the other ADC_CHs together to a  
single resistor to ground.  
Analog-to-Digital converter channel 5  
Note: If the ADC is not used, it is recommended to  
either leave this pin open, as no connect, or tie this  
pin along with the other ADC_CHs together to a  
single resistor to ground.  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
VDDA18_ADC  
G9  
PWR  
1.8- V Analog-to-Digital converter analog power  
supply  
Note: If the ADC is not used at all in an application,  
this pin can be directly connected to the 1.8-V supply  
without any filtering or to ground.  
VSSA_ADC  
F8  
J3  
GND  
1.8- V Analog-to-Digital converter ground  
PWCTRIO0  
I/O/Z PRTCS VDD18_PRTCSS  
S
Input PRTCSS: General Input / Output Signal 0  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
PWCTRIO1  
PWCTRIO2  
PWCTRIO3  
PWCTRIO4  
PWCTRIO5  
PWCTRIO6  
PWCTRO0  
PWCTRO1  
PWCTRO2  
PWCTRO3  
RTCXI  
J2  
J1  
J5  
J4  
K5  
K4  
K2  
L5  
L4  
L3  
G1  
I/O/Z PRTCS VDD18_PRTCSS  
S
Input PRTCSS: General Input / Output Signal 1  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
I/O/Z PRTCS VDD18_PRTCSS  
S
Input PRTCSS: General Input / Output Signal 2  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
I/O/Z PRTCS VDD18_PRTCSS  
S
Input PRTCSS: General Input / Output Signal 3  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
I/O/Z PRTCS VDD18_PRTCSS  
S
Input PRTCSS: General Input / Output Signal 4  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
I/O/Z PRTCS VDD18_PRTCSS  
S
Input PRTCSS: General Input / Output Signal 5  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
I/O/Z PRTCS VDD18_PRTCSS  
S
Input PRTCSS: General Input / Output Signal 6  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
O
O
PRTCS VDD18_PRTCSS  
S
Output PRTCSS: General Output Signal 0  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
PRTCS VDD18_PRTCSS  
S
Output PRTCSS: General Output Signal 1  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
I/O/Z PRTCS VDD18_PRTCSS  
S
Output PRTCSS: General Output Signal 2  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
O
I
PRTCS VDD18_PRTCSS  
S
Output PRTCSS: General Output Signal 3  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
PRTCS VDD12_PRTCSS  
S
Input PRTCSS: Crystal Input for PRTCSS oscillator  
Note: If the RTC calendar is not used, this pin should  
be pulled down.  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
42  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
RTCXO  
H1  
O
PRTCS VDD12_PRTCSS  
S
Output PRTCSS: Crystal Output for PRTCSS oscillator  
Note: If the RTC calendar is not used, this pin should  
be left unconnected.  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
PWRST  
M3  
M2  
I
I
PRTCS VDD12_PRTCSS  
S
Input PRTCSS: Reset signal for PRTCSS  
For more pin termination details, see Section 6.7,  
Power Management and Real Time Clock  
Subsystem (PRTCSS).  
PWRCNTON  
PRTCS VDD12_PRTCSS  
S
Input PRTCSS: Reset pin for system power sequencing  
For more pin details, see Section 6.7.  
RESET  
MXI1  
H3  
L1  
I
I
VDDS33  
Input Global chip reset  
CLOCK  
S
VDDMXI  
Input Crystal input for system oscillator  
Note: If an external oscillator is to be used, the  
external oscillator clock signal should be connected  
to the MXI1 pin with a 1.8V amplitude. The MXO1  
should be left unconnected and the VSS_MX1 signal  
should be connected to board ground (Vss).  
MXO1  
K1  
O
CLOCK  
S
VDDMXI  
Output Output for system oscillator  
Note: If an external oscillator is to be used, the  
external oscillator clock signal should be connected  
to the MXI1 pin with a 1.8V amplitude. The MXO1  
should be left unconnected and the VSS_MX1 signal  
should be connected to board ground (Vss).  
TCK  
F4  
F5  
G4  
G2  
H5  
F2  
G5  
H4  
I
I
EMULA  
TION  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
VDDS33  
IPU  
IPU  
Input JTAG test clock input  
Input JTAG test data input  
Output JTAG test data output  
Input JTAG test mode select  
Input JTAG test logic reset  
Output JTAG test clock output  
Input JTAG emulation 0 I/O  
Input JTAG emulation 1 I/O  
TDI  
EMULA  
TION  
TDO  
O
I
EMULA  
TION  
TMS  
EMULA  
TION  
IPU  
IPD  
TRST  
RTCK  
EMU0  
EMU1  
I
EMULA  
TION  
O
I/O  
I/O  
EMULA  
TION  
EMULA  
TION  
IPU  
IPU  
EMULA  
TION  
EMU[1:0] = 00 - Force Debug Scan chain (ARM and  
ARM ETB TAPs connected)  
EMU[1:0] = 11 - Normal Scan chain (ICEpick only)  
RSV2  
RSV1  
RSV0  
R4  
R1  
A1  
I
For proper device operation, this pin must be tied to  
ground.  
O
O
For proper device operation, this pin must be left  
unconnected.  
For proper device operation, this pin must be left  
unconnected.  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
CVDD  
G6  
G8  
PWR  
Core power (1.2-V or 1.35-V).  
H7  
H8  
H12  
J8  
J12  
J14  
K8  
K12  
L13  
M6  
M10  
M12  
M13  
J6  
VDD12_PRTCSS  
PWR  
Power supply for RTC oscillator, PRTCSS, and  
PRTCSS I/O (1.2-V or 1.35-V).  
K7  
VDDA18_PLL  
VDDRAM  
N4  
PWR  
O
Analog power for PLL (1.8 V).  
D4  
Output For proper device operation, this pin must be  
connected to a 1.0uF (6.2V) capacitor, and the other  
end of the capacitor must be connected to Vss  
.
Note: this pin is an internal power supply pin and  
should not be connected to any external power  
supply.”  
VDDS18  
G14  
H11  
H14  
J7  
PWR  
Power supply for 1.8-V I/O.  
M14  
P7  
VDD18_PRTCSS  
VDDMXI  
K6  
PWR  
PWR  
PWR  
Power supply for PRTCSS (1.8 V).  
L6  
Power supply for PLL oscillator (1.8 V).  
VDD18_SLDO  
E5  
Power supply for internal RAM.  
For proper device operation, this pin must always be  
connected to VDDS18  
.
VDD18_DDR  
N9  
N11  
P9  
PWR  
Power supply for DDR (1.8 V).  
P10  
P12  
R12  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
VDDS33  
F10  
F6  
PWR  
Power supply for 3.3-V I/O.  
F7  
H6  
H13  
L12  
N6  
P5  
P6  
VDD_AEMIF1_18_33  
P14  
R14  
K14  
L14  
PWR  
PWR  
Power supply for switchable AEMIF (3.3/1.8 V).  
VDD_AEMIF1_18_33 : can be used as a power supply for  
EM_A[3:13], EM_BA0, EM_BA1, EM_CE[0],  
EM_ADV, EM_CLK, EM_D[8:15] or as GPIO pins.  
See AEMIF pin descriptions.  
VDD_AEMIF2_18_33  
VDD_AEMIF2_18_33: can be used as a power supply for  
EM_A[0:2], EM_CE[1], EM_WE, EM_OE, EM_WAIT,  
EM_D[0:7] pins, HPI, or GPIO pins. See AEMIF pin  
descriptions.  
Example 1: VDD_AEMIF2_18_33 at 1.8-V for 8-bit NAND  
VDD_AEMIF1_18_33  
at  
3.3-V  
for  
GPIO.  
Example 2: VDD_AEMIF1_18_33 and VDD_AEMIF2_18_33 at  
1.8-V for 16-bit NAND.  
VDD_ISIF18_33  
F12  
F13  
PWR  
PWR  
Power supply for switchable ISIF (3.3/1.8 V).  
Example 1 VDD_ISIF_18_33 power supply can be at  
1.8V for VPFE pin functionality or it can be at 3.3V if  
other peripherals pin functionality is to be used like  
SPI3 or GPIO or CLKOUT0, or USBDRVVBUS.  
VPP  
R3  
PWR  
For proper device operation, this pin must always be  
connected to CVDD.  
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Table 2-5. Pin Descriptions (continued)  
Name  
BGA  
ID  
Type Group  
Power  
IPU  
Reset  
State  
Description(4)  
(1)  
Supply(2)  
IPD(3)  
VSS  
A19  
E14  
F14  
G11  
G12  
H9  
GND  
Digital ground  
H10  
J9  
J10  
J11  
J13  
K9  
K10  
K11  
L7  
L8  
L9  
L10  
L11  
M7  
M8  
M9  
M11  
N8  
N12  
N14  
P8  
P13  
W1  
W19  
L2  
VSS_MX1  
GND  
System oscillator - ground  
Note: Note: If an external oscillator is used, this pin  
must be connected to board ground (Vss).  
VSS_32K  
VSSA  
H2  
M4  
GND  
GND  
PRTCSS oscillator - ground  
Analog ground  
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2.9 Device Support  
2.9.1 Development Tools  
TI offers an extensive line of development tools for device systems, including tools to evaluate the  
performance of the processors, generate code, develop algorithm implementations, and fully integrate and  
debug software and hardware modules. The tools support documentation is electronically available within  
the Code Composer Studio™ Integrated Development Environment (IDE).  
The following products support development of device based applications:  
Software Development Tools:  
Code Composer Studio™ Integrated Development Environment (IDE): including Editor  
C/C++/Assembly Code Generation, and Debug plus additional development tools  
Hardware Development Tools:  
Extended Development System (XDS™) Emulator (supports TMS320DM365 DMSoC multiprocessor  
system debug) EVM (Evaluation Module)  
For a complete listing of development-support tools for the TMS320DM365 DMSoC platform, visit the  
Texas Instruments web site on the Worldwide Web at http://www.ti.com. For information on pricing and  
availability, contact the nearest TI field sales office or authorized distributor.  
2.9.2 Device Nomenclature  
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all  
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,  
TMP, or TMS (e.g., ). Texas Instruments recommends two of three possible prefix designators for its  
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development  
from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).  
Device development evolutionary flow:  
TMX  
TMP  
TMS  
Experimental device that is not necessarily representative of the final device's electrical  
specifications.  
Final silicon die that conforms to the device's electrical specifications but has not completed  
quality and reliability verification.  
Fully-qualified production device.  
Support tool development evolutionary flow:  
TMDX  
Development-support product that has not yet completed Texas Instruments internal  
qualification testing.  
TMDS  
Fully qualified development-support product.  
TMX and TMP devices and TMDX development-support tools are shipped against the following  
disclaimer:  
"Developmental product is intended for internal evaluation purposes."  
TMS devices and TMDS development-support tools have been characterized fully, and the quality and  
reliability of the device have been demonstrated fully. TI's standard warranty applies.  
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard  
production devices. Texas Instruments recommends that these devices not be used in any production  
system because their expected end-use failure rate is undefined. Only qualified production devices are to  
be used in production.  
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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the  
package type (for example, ZCE), the temperature range (for example, "Blank" is the commercial  
temperature range), and the device speed range in megahertz (for example, 202 is 202.5 MHz). The  
following figure provides a legend for reading the complete device name for any TMS320DM365 DMSoC  
platform member.  
TMS 320 DM365 ( ) ZCE ( ) 27 ( )  
F = Face Detection  
PREFIX  
TMX = Experimental device  
TMS = Qualified device  
SPEED GRADE  
21 = 216 MHz  
27 = 270 MHz  
30 = 300 MHZ  
DEVICE FAMILY  
320 = TMS320 DSP family  
TEMPERATURE GRADE  
Blank = 0 to 85C  
D = -40 to 85C  
DEVICE(B)  
DM365  
PACKAGE TYPE(A)  
ZCE = 338-pin plastic BGA, with Pb-free soldered balls  
SILICON REVISION(C)  
A. BGA = Ball Grid Array.  
B. For actual device part numbers (P/Ns) and ordering information, contact your nearest TI Sales Representative.  
C. For more information on silicon revision, see the TMS320DM365 Silicon Errata (literature number SPRZ294).  
Figure 2-6. Device Nomenclature  
2.9.3 Related Documentation From Texas Instruments  
The following documents describe the TMS320DM36x Digital Media System-on-Chip (DMSoC). Copies of  
these documents are available on the internet at www.ti.com.  
SPRZ294  
TMS320DM365 DMSoC Silicon Errata Describes the known exceptions to the functional  
specifications for the TMS320DM365 DMSoC.  
SPRUFG5 TMS320DM36x Digital Media System-on-Chip (DMSoC) ARM Subsystem Users Guide.  
This document describes the ARM Subsystem in the TMS320DM36x Digital Media  
System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S  
(ARM9) master control of the device. In general, the ARM is responsible for configuration  
and control of the device; including the components of the ARM Subsystem, the peripherals,  
and the external memories.  
SPRUFG8 TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Front End  
(VPFE) Users Guide. This document describes the Video Processing Front End (VPFE) in  
the TMS320DM36x Digital Media System-on-Chip (DMSoC).  
SPRUFG9 TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Back End  
(VPBE) Users Guide. This document describes the Video Processing Back End (VPBE) in  
the TMS320DM36x Digital Media System-on-Chip (DMSoC).  
SPRUFH0 TMS320DM36x Digital Media System-on-Chip (DMSoC) 64-bit Timer Users Guide. This  
document describes the operation of the software-programmable 64-bit timers in the  
TMS320DM36x Digital Media System-on-Chip (DMSoC).  
SPRUFH1 TMS320DM36x Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface (SPI)  
Users Guide. This document describes the serial peripheral interface (SPI) in the  
TMS320DM36x Digital Media System-on-Chip (DMSoC). The SPI is a high-speed  
synchronous serial input/output port that allows a serial bit stream of programmed length (1  
to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI  
is normally used for communication between the DMSoC and external peripherals. Typical  
applications include an interface to external I/O or peripheral expansion via devices such as  
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shift registers, display drivers, SPI EPROMs and analog-to-digital converters.  
SPRUFH2 TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous  
Receiver/Transmitter (UART) Users Guide. This document describes the universal  
asynchronous receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media  
System-on-Chip (DMSoC). The UART peripheral performs serial-to-parallel conversion on  
data received from a peripheral device, and parallel-to-serial conversion on data received  
from the CPU.  
SPRUFH3 TMS320DM36x Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C)  
Peripheral Users Guide. This document describes the inter-integrated circuit (I2C)  
peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The I2C peripheral  
provides an interface between the DMSoC and other devices compliant with the I2C-bus  
specification and connected by way of an I2C-bus.  
SPRUFH5 TMS320DM36x Digital Media System-on-Chip (DMSoC) Multimedia Card (MMC)/Secure  
Digital (SD) Card Controller Users Guide. This document describes the multimedia card  
(MMC)/secure digital (SD) card controller in the TMS320DM36x Digital Media  
System-on-Chip (DMSoC).  
SPRUFH6 TMS320DM36x Digital Media System-on-Chip (DMSoC) Pulse-Width Modulator (PWM)  
Users Guide. This document describes the pulse-width modulator (PWM) peripheral in the  
TMS320DM36x Digital Media System-on-Chip (DMSoC).  
SPRUFH7 TMS320DM36x Digital Media System-on-Chip (DMSoC) Real-Time Out (RTO) Controller  
Users Guide. This document describes the Real Time Out (RTO) controller in the  
TMS320DM36x Digital Media System-on-Chip (DMSoC).  
SPRUFH8 TMS320DM36x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output  
(GPIO) Users Guide. This document describes the general-purpose input/output (GPIO)  
peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The GPIO  
peripheral provides dedicated general-purpose pins that can be configured as either inputs  
or outputs.  
SPRUFH9 TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB)  
Controller Users Guide. This document describes the universal serial bus (USB) controller  
in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The USB controller supports  
data throughput rates up to 480 Mbps. It provides a mechanism for data transfer between  
USB devices and also supports host negotiation.  
SPRUFI0  
TMS320DM36x Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory  
Access (EDMA) Controller Users Guide. This document describes the operation of the  
enhanced direct memory access (EDMA3) controller in the TMS320DM36x Digital Media  
System-on-Chip (DMSoC). The EDMA controller's primary purpose is to service  
user-programmed data transfers between two memory-mapped slave endpoints on the  
DMSoC.  
SPRUFI1  
SPRUFI2  
TMS320DM36x Digital Media System-on-Chip (DMSoC) Asynchronous External  
Memory Interface (EMIF) Users Guide. This document describes the asynchronous  
external memory interface (EMIF) in the TMS320DM36x Digital Media System-on-Chip  
(DMSoC). The EMIF supports a glueless interface to a variety of external devices.  
TMS320DM36x Digital Media System-on-Chip (DMSoC) DDR2/Mobile DDR  
(DDR2/mDDR) Memory Controller Users Guide. This document describes the  
DDR2/mDDR memory controller in the TMS320DM36x Digital Media System-on-Chip  
(DMSoC). The DDR2/mDDR memory controller is used to interface with JESD79D-2A  
standard compliant DDR2 SDRAM and mobile DDR devices.  
SPRUFI3  
TMS320DM36x Digital Media System-on-Chip (DMSoC) Multibuffered Serial Port  
Interface (McBSP) User's Guide. This document describes the operation of the  
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multibuffered serial host port interface in the TMS320DM36x Digital Media System-on-Chip  
(DMSoC). The primary audio modes that are supported by the McBSP are the AC97 and IIS  
modes. In addition to the primary audio modes, the McBSP supports general serial port  
receive and transmit operation.  
SPRUFI4  
SPRUFI5  
SPRUFI7  
SPRUFI8  
SPRUFI9  
TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Host Port Interface  
(UHPI) User's Guide. This document describes the operation of the universal host port  
interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC).  
TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access  
Controller (EMAC) User's Guide. This document describes the operation of the ethernet  
media access controllerface in the TMS320DM36x Digital Media System-on-Chip (DMSoC).  
TMS320DM36x Digital Media System-on-Chip (DMSoC) Analog to Digital Converter  
(ADC) User's Guide. This document describes the operation of the analog to digital  
conversion in the TMS320DM36x Digital Media System-on-Chip (DMSoC).  
TMS320DM36x Digital Media System-on-Chip (DMSoC) Key Scan User's Guide. This  
document describes the key scan peripheral in the TMS320DM36x Digital Media  
System-on-Chip (DMSoC).  
TMS320DM36x Digital Media System-on-Chip (DMSoC) Voice Codec User's Guide. This  
document describes the voice codec peripheral in the TMS320DM36x Digital Media  
System-on-Chip (DMSoC). This module can access ADC/DAC data with internal FIFO (Read  
FIFO/Write FIFO). The CPU communicates to the voice codec module using 32-bit-wide  
control registers accessible via the internal peripheral bus.  
SPRUFJ0 TMS320DM36x Digital Media System-on-Chip (DMSoC) Power Management and  
Real-Time Clock Subsystem (PRTCSS) User's Guide. This document provides a  
functional description of the Power Management and Real-Time Clock Subsystem  
(PRTCSS) in the TMS320DM36x Digital Media System-on-Chip (DMSoC) and PRTC  
interface (PRTCIF).  
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3 Device Configurations  
This section provides a detailed overview of the device.  
3.1 System Module Registers  
The system module includes status and control registers for configuration of the device. Brief descriptions  
of the various registers are shown in Table 3-1. For more information on the System Module registers, see  
the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).  
Table 3-1. System Module Register Memory Map  
HEX ADDRESS  
0x01C4 0000  
REGISTER ACRONYM  
PINMUX0  
DESCRIPTION(1)  
Pin Mux 0 (Video In) Pin Mux Register  
0x01C4 0004  
0x01C4 0008  
0x01C4 000C  
0x01C4 0010  
0x01C4 0014  
0x01C4 0018  
0x01C4 001C  
0x01C4 0020  
0x01C4 0024  
0x01C4 0028  
0x01C4 002C  
0x01C4 0030  
0x01C4 0034  
0x01C4 0038  
0x01C4 003C  
0x01C4 0040  
0x01C4 0044  
0x01C4 0048  
0x01C4 004C  
0x01C4 0050  
0x01C4 0054  
0x01C4 0058  
0x01C4 005C  
0x01C4 0060  
0x01C4 0064  
0x01C4 0068  
0x01C4 006C  
0x01C4 0070  
0x01C4 0074  
0x01C4 0078  
0x01C4 007C  
0x01C4 0080  
0x01C4 0084  
0x01C4 0088  
PINMUX1  
Pin Mux 1 (Video Out) Pin Mux Register  
Pin Mux 2 (AEMIF) Pin Mux Register  
Pin Mux 3 (GIO/Misc) Pin Mux Register  
Pin Mux 4 (Misc) Pin Mux Register  
Boot Configuration  
PINMUX2  
PINMUX3  
PINMUX4  
BOOTCFG  
ARM_INTMUX  
EDMA_EVTMUX  
DDR_SLEW  
UHPICTL  
Multiplexing Control for Interrupts  
Multiplexing Control for EDMA Events  
DDR Slew Rate  
UHPI Control  
DEVICE_ID  
VDAC_CONFIG  
TIMER64_CTL  
USB_PHY_CTL  
MISC  
Device ID  
Video DAC Configuration  
Timer64 Input Control  
USB PHY Control  
Miscellaneous Control  
MSTPRI0  
Master Priorities Register 0  
Master Priorities Register 1  
VPSS Clock Mux Control  
Peripheral Clock Control  
DEEPSLEEP Control  
MSTPRI1  
VPSS_CLK_CTL  
PERI_CLKCTL  
DEEPSLEEP  
-
Reserved  
DEBOUNCE0  
DEBOUNCE1  
DEBOUNCE2  
DEBOUNCE3  
DEBOUNCE4  
DEBOUNCE5  
DEBOUNCE6  
DEBOUNCE7  
VTPIOCR  
Debounce for GIO0 Input  
Debounce for GIO1 Input  
Debounce for GIO2 Input  
Debounce for GIO3 Input  
Debounce for GIO4 Input  
Debounce for GIO5 Input  
Debounce for GIO6 Input  
Debounce for GIO7 Input  
VTP IO Control  
PUPDCTL0  
PUPDCTL1  
HDVICPBT  
PLL1_CONFIG  
PLL2_CONFIG  
IO cell pullup/down on/off control #0  
IO cell pullup/down on/off control #1  
HDVICP Boot Register  
PLL1 Configuration Register  
PLL2 Configuration Register  
(1) For more details on the system module registers, see the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number  
SPRUFG5).  
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3.2 Boot Modes  
The ARM can boot from either Asynchronous EMIF (OneNand/NOR) or from ARM ROM, as determined  
by the setting of the device configuration pins BTSEL[2:0]. The boot selection pins (BTSEL[2:0]) determine  
the ARM boot process. After reset (POR, warm reset, or max reset), ARM program execution begins in  
ARM ROM at 0x0000: 8000, except when BTSEL[2:0] = 001, indicating AEMIF (OneNand/NOR) flash  
boot.  
3.2.1 Boot Modes Overview  
The ARM ROM boot loader (RBL) executes when the BTSEL[2:0] pins indicate a condition other than the  
normal ARM EMIF boot.  
•
If BTSEL[2:0] = 001 - Asynchronous EMIF boot mode (NOR or OneNAND). This mode is handled by  
hardware control and does not involve the ROM. In the case of OneNAND, the user is responsible for  
putting any necessary boot code in the OneNAND's boot page. This code shall configure the AEMIF  
module for the OneNAND device. After the AEMIF module is configured, booting will continue  
immediately after the OneNAND’s boot page with the AEMIF module managing pages thereafter.  
•
The RBL supports 7 distinct boot modes:  
–
–
–
–
–
–
–
BTSEL[2:0] = 000 - NAND Boot mode  
BTSEL[2:0] = 010 - MMC0/SD0 Boot mode  
BTSEL[2:0] = 011 - UART0 Boot mode  
BTSEL[2:0] = 100 - USB Boot mode  
BTSEL[2:0] = 101 - SPI0 Boot mode  
BTSEL[2:0] = 110 - EMAC Boot mode  
BTSEL[2:0] = 111 - HPI Boot mode  
•
•
•
•
•
•
•
•
•
If NAND boot fails, then MMC/SD mode is tried.  
If MMC/SD boot fails, then MMC/SD boot is tried again.  
If UART boot fails, then UART boot is tried again.  
If USB boot fails, then USB boot is tried again.  
If SPI boot fails, then SPI boot is tried again.  
If EMAC boot fails, then EMAC boot is tried again.  
If HPI boot fails, then HPI boot is tried again.  
RBL shall update boot status (PASS/FAIL) in MISC register bits 8 and 9 in System control module.  
ARM ROM Boot - NAND Mode  
–
No support for a full firmware boot. Instead, copies a second stage user boot loader (UBL) from  
NAND flash to ARM internal RAM (AIM) and transfers control to the user-defined UBL.  
–
–
–
–
Support for NAND with page sizes up to 4096 bytes.  
Support for magic number error detection and retry (up to 24 times) when loading UBL  
Support for up to 30KB UBL (32KB IRAM - ~2KB for RBL stack)  
Optional, user-selectable, support for use of DMA and I-cache during RBL execution (i.e.,while  
loading UBL)  
–
–
Supports booting from 8-bit NAND devices (16-bit NAND devices are not supported)  
Uses/Requires 4-bit HW ECC (NAND devices with ECC requirements ≤ 4 bits per 512 bytes are  
supported)  
–
Supports NAND flash that requires chip select to stay low during the tR read time  
•
ARM ROM Boot - MMC/SD Mode  
–
No support for a full firmware boot. Instead, copies a second stage User Boot Loader (UBL) from  
MMC/SD to ARM Internal RAM (AIM) and transfers control to the user software.  
–
–
Support for MMC/SD Native protocol (MMC/SD SPI protocol is not supported)  
Support for descriptor error detection and retry (up to 24 times) when loading UBL  
52  
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–
–
Support for up to 30KB UBL (32KB - ~2KB for RBL stack)  
SDHC boot supported by RBL  
•
ARM ROM Boot - UART mode  
–
If the state of BTSEL[2:0] pins at reset is 011, then the UART boot mode executes. This mode  
enables a small program, referred to here as a user boot loader (UBL), to be downloaded to the  
on-chip ARM internal RAM via the on-chip serial UART and executed. A host program, (referred to  
as serial host utility program), manages the interaction with RBL and provides a means for operator  
feedback and input. The UART boot mode execution assumes the following UART settings:  
Time-Out 500 ms, one-shot Serial RS-232 port 115.2 Kbps, 8-bit, no parity, one stop bit Command,  
data, and checksum format Everything sent from the host to the device UART RBL must be in  
ASCII format  
–
–
No support for a full firmware boot. Instead, loads a second stage user boot loader (UBL) via UART  
to ARM internal RAM (AIM) and transfers control to the user software.  
Support for up to 30KB UBL (32KB - ~2KB for RBL stack)  
•
•
•
ARM ROM Boot – USB Mode  
–
No support for a full firmware boot. Instead, loads a second stage User Boot Loader (UBL) via USB  
to ARM Internal RAM (AIM) and transfers control to the users software.  
ARM ROM Boot – SPI Mode  
–
The device will copy UBL to ARM Internal RAM (AIM) via SPI interface from a SPI peripheral like  
SPI EEPROM. RBL will then transfer control to the UBL.  
ARM ROM Boot – EMAC Mode  
–
The device will send a boot request packet and the host/server will respond with the boot packets.  
RBL will wait for all boot packets to arrive and then transfer control to the UBL which is received via  
boot packets. In EMAC boot mode an I2C EEPROM or SPI EEPROM is necessary for  
programming EMAC descriptor (including EMAC address for the device)  
Note: If a magic number is not found in the EEPROM, then the EMAC boot mode will use a default  
MAC address. In this case, there will be no magic number support.  
•
ARM ROM Boot – HPI Mode  
–
The Host will copy UBL to ARM Internal RAM (AIM) via HPI interface and notify the ROM  
bootloader after copy is finished. RBL will then transfer control to the UBL.  
The general boot sequence is shown in Figure 3-1. For more information, refer to the TMS320DM36x  
DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).  
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Reset  
AEMIF  
No  
RBL  
Boot  
?
Yes  
ROM Boot Loader  
HPI  
NAND  
MMCSD  
UART  
USB  
SPI  
EMAC  
NAND  
MMCSD  
UART  
USB  
SPI  
EMAC  
HPI  
Boot  
Boot  
Boot  
Boot  
Boot  
Boot  
Boot  
Boot  
OK  
?
No  
Boot  
OK  
?
No  
Boot  
OK  
?
No  
Boot  
OK  
?
No  
Boot  
OK  
?
No  
Boot  
OK  
?
No  
Boot  
OK  
?
No  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
One NAND/NOR Boot  
UBL  
Figure 3-1. Boot Mode Functional Block Diagram  
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3.3 Device Clocking  
3.3.1 Overview  
The device requires one primary reference clock. The reference clock frequency may be generated either  
by crystal input or by external oscillator. The reference clock is the clock at the pins named MXI1/MXO1,  
and which drives two separate PLL controllers (PLLC1 and PLLC2). PLLC1 generates the clocks required  
by the ARM, EDMA, VPSS and the rest of the peripherals. PLL2 generates the clock required by the DDR  
PHY interface and is also capable of providing clocks to the ARM, USB, Video, or Voice Codec modules  
as well as a flexible clocking option. Figure 3-2 represents the clocking architecture for the ARM  
subsystem. For more information on device clocking and the system PLL controller please see the  
TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).  
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Figure 3-2. Clocking Architecture  
Oscillator (MXI1/MXO1)  
19.2/24/27/36 Mhz  
SPI4  
PLLC2  
PLLC1  
UART0  
I2C  
CLKOUT0  
PWM0-3  
CLKOUT2  
DIV1  
TIMER0-3/  
WDT  
PHYCLKSRC  
USB PHY  
RTO  
ADC  
MMC/SD0  
McBSP  
HDVICP  
ARMSS  
CLKOUT1  
MMC/SD1  
USB  
MJCP  
Voice  
Codec  
AEMIF  
UART1  
SPI0-3  
GPIO  
DIV2  
VPSS  
VENC_CLK_SRC  
VPSS_MUXSEL  
EXTCLK  
VPBE  
VPFE  
PCLK  
AINTC  
EMAC  
HPI  
DIV3  
KEYSCLKS  
DDR  
PHY  
PRTCCLKS  
EDMA  
DDRCLKS  
KeyScan  
PRTCSS  
DDR2  
EMIF  
VCLK  
32 Khz  
Oscillator  
3.3.2 PLL Controller Module  
Two PLL controllers provide clocks to different components of the chip. The PLL controller 1 (PLLC1)  
provides clocks to most of the components of the chip. The PLL controller 2 (PLLC2) provides clocks to  
the DDR PHY and is also capable of providing clocks to the ARM, USB, VPSS or the Voice Codec  
modules instead as well.  
As a module, the PLL controller provides the following:  
•
•
•
Glitch-free transitions (on changing PLL settings)  
Domain clocks alignment  
Clock gating  
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•
•
PLL bypass  
PLL power down  
The various clock outputs given by the PLL controller are as follows:  
•
•
•
Domain clocks: SYSCLKn  
Bypass domain clock: SYSCLKBP  
Auxiliary clock from reference clock: AUXCLK  
Various dividers that can be used are as follows:  
•
•
•
•
Pre-PLL divider: PREDIV  
Post-PLL divider: POSTDIV  
SYSCLK divider: PLLDIV1, …, PLLDIVn  
SYSCLKBP divider: BPDIV  
The Multiplier values supported are handled by:  
PLL multiplier control: PLLM  
Notes:  
•
•
•
•
PLLCxSYSCLKy is used to denote post divide clock output SYSCLKy from PLL controller x  
'x', which denotes PLL Controller number, can assume values 1 and 2  
'y', which denotes post divide clock outputs, can assume values 1 to 9 in case of PLLC1 and 1 to 5 in  
case of PLLC2  
The PLL Controllers for PLL1 and PLL2 are described in detail in the TMS320DM36x ARM Subsystem  
Reference Guide (literature number SPRUFG5).  
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3.3.3 PLLC1  
There are two PLLs on the device, and they are independently controlled. PLLC1 generates the  
frequencies needed for the ARM, Video Processing Sub System (VPSS), MJCP coprocessor block,  
EDMA, and peripherals.  
The reference clock for both PLLs is the single crystal input. Both PLLs will be of the same type . It should  
be noted that the USB2.0 PHY contains a third PLL embedded within it. Table 3-2, and Figure 3-3  
describe the customization of PLLC1.  
•
•
•
•
•
•
•
Provides primary system clock  
Software configurable  
Accepts clock input or internal oscillator input  
PLL pre-divider value is programmable  
PLL multiplier value is programmable  
PLL post-divider value is programmable . See the data manual for all supported configurations.  
Only SYSCLK [9:1] are used  
Table 3-2. PLLC1 Output Clocks  
PLLC1SYSCLKy  
PLLC1SYSCLK1  
PLLC1SYSCLK2  
PLLC1SYSCLK3  
PLLC1SYSCLK4  
Used By  
USB reference clock(1)  
PLLDIV Divider  
Programmable  
Programmable  
Programmable  
Programmable  
(1)  
ARM926EJ-S, HDVICP block clock  
MJCP and HDVICP bus interface clock  
Configuration bus clock, peripheral system interfaces,  
EDMA  
PLLC1SYSCLK5  
PLLC1SYSCLK6  
PLLC1SYSCLK7  
PLLC1SYSCLK8  
PLLC1SYSCLK9  
PLLC1OBSCLK  
PLLC1SYSCLKBP  
VPSS clock  
VENC clock(1)  
DDR 2x clock(1)  
MMC/SD0 clock  
CLKOUT2  
Programmable  
Programmable  
Programmable  
Programmable  
Programmable  
Programmable  
Programmable  
CLKOUT0  
USB reference clock(1)  
(1) These clock outputs are multiplexed with other clocks.  
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Figure 3-3. PLLC1 Configuration  
PLLEN  
PLLDIV1*  
SYSCLK1 (USB Reference Clock)  
Pre-DIV  
(Programmable)  
Post-DIV  
(Programmable)  
OSCIN  
PLL  
PLLDIV2*  
1
0
SYSCLK2 (ARM926EJ-S, HDVICP  
Block Clock)  
PLLDIV3*  
PLLDIV4*  
SYSCLK3 (MJCP and HDVICP  
Coprocessors Bus Interface Clock)  
PLLM  
(Programmable)  
SYSCLK4 (Config Bus, Peripheral System  
Interfaces, EDMA)  
PLLDIV5*  
PLLDIV6*  
PLLDIV7*  
PLLDIV8*  
SYSCLK5 (VPSS)  
SYSCLK6 (VENC Clock)  
SYSCLK7 (DDR 2x Clock)  
SYSCLK8 (MMC/SD0 Clock)  
PLLDIV9*  
BPDIV*  
SYSCLK9 (CLKOUT 2)  
SYSCLKBP ( USB Reference Clock)  
OBSCLK (CLKOUT0)  
OSCDIV1*  
* – Programmable  
3.3.4 PLLC2  
PLLC2 provides the USB reference clock , ARM926EJ-S, DDR 2x clock, Voice Codec clock and VENC  
27MHz, 74.25MHz clock. The PLLC2 functionality can be programmed via the PLLC2 registers. The  
following list, Table 3-3, and Figure 3-4 describe the customization of PLLC2.  
The PLLC2 customization includes the following features:  
•
PLLC2 provides DDR PHY, USB reference clock , ARM926EJ-S clock, VENC 27MHz, 74.25Hz clock  
and Voice codec clock  
•
•
•
•
•
•
Software configurable  
Accepts clock input or internal oscillator input (the same input as PLLC1)  
PLL pre-divider value is programmable  
PLL multiplier value is programmable  
PLL post-divider value is programmable  
Only SYSCLK [5:1] are used  
Table 3-3. PLLC2 Output Clocks  
PLLC2SYSCLKy  
PLLC2SYSCLK1  
PLLC2SYSCLK2  
PLLC2SYSCLK3  
PLLC2SYSCLK4  
PLLC2SYSCLK5  
PLLC2OBSCLK  
Used by  
USB reference clock(1)  
PLLDIV Divider  
Programmable  
Programmable  
Programmable  
Programmable  
Programmable  
Programmable  
(1)  
ARM926EJ-S, HDVICP block clock  
(1)  
DDR 2x clock  
Voice Codec clock  
(1)  
VENC clock  
CLKOUT1  
(1) These clock outputs are multiplexed with other clocks.  
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SYSCLK1  
(USB Reference Clock)  
PLLEN  
PLLDIV1*  
PLLDIV2*  
Pre-DIV  
OSCIN  
SYSCLK2 (ARM926EJ-S,  
HDVICP Block Clock)  
PLL  
Post-DIV*  
1
0
(Programmable)  
SYSCLK3 (DDR 2x Clock)  
PLLDIV3*  
PLLDIV4*  
PLLDIV5*  
PLLM  
(Programmable)  
SYSCLK4  
(Voice Codec Clock)  
SYSCLK5 (VENC Clock)  
OBSCLK  
(CLKOUT1)  
OSCDIV1*  
* – Programmable  
Figure 3-4. PLLC2 Configuration  
3.3.5 Processing, Video, EDMA and DDR EMIF Subsystems Maximum Operating  
Frequencies  
Table 3-4 shows the maximum speeds supported for each of the major blocks supported on the different  
speed grade devices.  
Table 3-4. Processing, Video, EDMA and DDR EMIF Subsystems Maximum Operating Frequencies  
DM365 - 216  
216 MHz  
173 MHz  
173 MHz  
173 MHz  
168 MHz  
173 MHz  
DM365 - 270  
270 MHz  
216 MHz  
216 MHz  
216 MHz  
168 MHz  
216 MHz  
DM365 - 300  
300 MHz  
270 MHz  
270 MHz  
270 MHz  
168 MHz  
270 MHz  
ARM926 RISC  
Co-Processor (HDVICP)  
Co-Processor (MJCP)  
DDR2  
mDDR  
VPSS Logic Block  
Peripheral System Bus  
and EDMA  
86.5 MHz  
108 MHz  
135 MHz  
VPBE-VENC  
VPFE(1)  
27 MHz  
74.25 MHz  
108 MHz  
74.25 MHz  
120 MHz  
86.5 MHz  
(1) The pixel clock (PCLK) of VPFE should meet the following conditions: PCLK <= 120MHz and PCLK < VPSS logic clock/2.  
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3.3.6 PLL Controller Clocking Configurations Examples  
The DM365 uses two PLLs to generate the two fundamental clocks used on the device. These two clocks  
feed two divider blocks which generate all of the functional clocks used by the peripherals and cores in the  
DM365. There are some peripheral clocks on the DM365 which are required to operate at a specific  
frequency by functional specification or convention. These frequencies are detailed in Table 3-5.  
Table 3-5. Specific Peripheral Operating Frequencies  
Clock  
VENC (standard definition)  
VENC (high definition)  
USB  
Required Frequency (MHz)  
Reason  
27  
74.25  
required to generate a valid NTSC signal  
required to generate a valid ATSC signal  
36, 24, or 19.2  
4.096  
required by the USB peripheral to generate a 48 MHz USB clock  
required to generate a precise 16 kHz audio sample rate  
Voice Codec  
Table 3-6, Table 3-7, , and Table 3-9 show examples of the PLL combinations that can be supported by  
DM365. Please see the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number  
SPRUFG5) for additional details on special peripherals, clocking considerations, and for additional PLL  
controller configuration details.  
Note 1: A 300-MHz configuration is possible using different PLL multiplier/divider combinations. However,  
an external clock source is required to provide 74.25 MHz for HD display.  
Note 2: HD 720p and above display mode resolutions are not supported on ARM 216-MHz clock rate  
devices.  
Note 3: There are example cases where the voice codec sampling frequency is listed as 15.98 kHz or  
16.002 kHz. The difference of 0.125% or 0.0125% versus 16 kHz specification should be acceptable for  
the majority of audio applications. If the DM365 voice codec is required to operate at precisely 16 kHz  
then the functional clock can be reduced to achieve precisely that sample frequency but the ARM926 and  
HDVICP will have to run at a reduced rate resulting in lower video performance.  
Table 3-6. 24-MHz Input Crystal Example(1) (2)(3)  
(4)  
PLL1  
PLL Output  
PLL2  
PLL Output  
ARM  
DDR  
MJCP  
HDVICP  
Voice Codec  
Video Encoder  
27MHz 74.25MHz  
(2M/(N+1))  
(2M/(N+1))  
(5)(MHz)  
(MHz)  
343.58  
272/18  
409.6  
256/15  
204.8  
216  
171.8  
171.8  
216  
171.8  
171.8  
1/100  
-
-
-
-
-
343.58  
432  
272/18  
18/1  
432  
270  
18/1  
90/8  
171.8  
216  
171.8  
216  
1/16  
1/10  
270  
1/66 (15.98  
kHz)  
486  
540  
162/8  
594  
594  
198/8  
297  
297  
243  
270  
243  
270  
243  
270  
1/145 (16.002 1/22  
kHz)  
1/8  
1/8  
360/16  
396/16  
1/145 (16.002 1/20  
kHz)  
(1) M = PLL controller multiplier. N = PLL controller divider.  
(2) All shaded frequencies derive from the PLL2 controller.  
(3) PLLC1SYSCLK4 (Configuration bus clock, peripheral system interfaces, EDMA) should be half of the PLLC1SYSCLK3 (MJCP and  
HDVICP bus interface clock).  
(4) The Voice Codec divider value is the combination of the PLL controller 2 SYSCLK4 and Peripheral Clock Control Register PLLDIV2 bit  
setting divider.  
(5) PLL Output is calculated by = Oscillator Input * (2M/(N+1)).  
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Table 3-7. 36-MHz Input Crystal Example(1)(2)(3)  
(4)  
PLL1  
PLL Output  
PLL2  
PLL Output  
ARM  
DDR  
MJCP  
HDVICP  
Voice Codec  
Video Encoder  
27MHz 74.25MHz  
(2M/(N+1))  
(2M/(N+1))  
(5)(MHz)  
(MHz)  
345  
432  
486  
540  
230/24  
432  
270  
594  
594  
12/1  
216  
270  
297  
297  
172.5  
216  
172.5  
172.5  
-
1/16  
-
12/1  
30/4  
216  
243  
270  
216  
243  
270  
1/66 (15.98kHz) 1/10  
1/22  
-
54/4  
66/4  
243  
-
1/8  
1/8  
580/29  
660/30  
270  
1/145 (16.002 1/22  
kHz)  
(1) M = PLL controller multiplier. N = PLL controller divider.  
(2) All shaded frequencies derive from the PLL2 controller.  
(3) PLLC1SYSCLK4 (Configuration bus clock, peripheral system interfaces, EDMA) should be half of the PLLC1SYSCLK3 (MJCP and  
HDVICP bus interface clock).  
(4) The Voice Codec divider value is the combination of the PLL controller 2 SYSCLK4 and Peripheral Clock Control Register PLLDIV2 bit  
setting divider.  
(5) PLL Output is calculated by = Oscillator Input * (2M/(N+1)).  
Table 3-8. 19.2-MHz Input Crystal Example(1)(2)(3)  
(4)  
PLL1  
PLL Output(5)  
PLL2  
PLL Output  
ARM  
DDR  
MJCP  
HDVICP  
Voice Codec  
Video Encoder  
27MHz 74.25MHz  
(2M/(N+1))  
(2M/(N+1))  
(MHz)  
(MHz)  
344.064  
448/25  
430.8  
112/5  
215.04  
172.032  
172.032  
172.032  
1/105  
-
-
-
-
-
344.064  
432  
448/25  
90/4  
432  
540  
90/4  
216  
270  
172.032  
216  
172.032  
216  
172.032  
216  
1/16  
1/20  
450/16  
1/132 (15.98  
KHz)  
486  
540  
540  
810/32  
450/16  
450/16  
594  
990/32  
990/32  
464/15  
297  
243  
270  
270  
243  
270  
270  
243  
270  
270  
1/145  
(16.002KHz)  
1/22  
1/8  
1/8  
-
594  
297  
1/145 (16.002 1/22  
KHz)  
593.92  
296.96  
1/145  
1/20  
(1) M = PLL controller multiplier. N = PLL controller divider.  
(2) All shaded frequencies derive from the PLL2 controller.  
(3) PLLC1SYSCLK4 (Configuration bus clock, peripheral system interfaces, EDMA) should be half of the PLLC1SYSCLK3 (MJCP and  
HDVICP bus interface clock).  
(4) The Voice Codec divider value is the combination of the PLL controller 2 SYSCLK4 and Peripheral Clock Control Register PLLDIV2 bit  
setting divider.  
(5) PLL Output is calculated by = Oscillator Input * (2M/(N+1)).  
Table 3-9. 27-MHz Input Crystal Example(1)(2)(3)  
PLL1  
PLL2  
PLL Output (2M/(N+1))  
ARM  
DDR  
MJCP  
HDVICP  
Voice Codec  
USB  
Video Encoder  
27 MHz 74.25 MHz  
(4)  
PLL Output(5) (2M/(N+1))  
(MHz)  
(MHz)  
345.6  
432  
64/5  
16/1  
216  
270  
8/1  
216  
270  
172.8  
172.8  
172.8  
-
1/18 (24 Mhz) 1/8  
1/18 (24Mhz) 1/10  
-
-
10/1  
154/8  
22/1  
44/2  
216  
216  
246  
270  
216  
216  
246  
270  
216  
216  
246  
270  
1/66 (15.98  
kHz)  
432  
492  
540  
16/1  
164/9  
20/1  
519.75  
594  
259.875  
297  
1/127  
(15.98kHz)  
1/18 (24Mhz) 1/16  
1/7  
1/8  
1/8  
1/145 (16.002 1/41 (12Mhz) 1/22  
kHz)  
594  
297  
1/145 (16.002 1/45 (12Mhz) 1/22  
kHz)  
(1) M = PLL controller multiplier. N = PLL controller divider.  
(2) All shaded frequencies derive from the PLL2 controller.  
(3) PLLC1SYSCLK4 (Configuration bus clock, peripheral system interfaces, EDMA) should be half of the PLLC1SYSCLK3 (MJCP and  
HDVICP bus interface clock).  
(4) The Voice Codec divider value is the combination of the PLL controller 2 SYSCLK4 and Peripheral Clock Control Register PLLDIV2 bit  
setting divider.  
(5) PLL Output is calculated by = Oscillator Input * (2M/(N+1)).  
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3.3.7 Peripheral Clocking Considerations  
The device supports several peripherals with special clocking considerations (VPBE, USB, Key Scan,  
ADC, Voice Codec, MJCP, HDVICP, AUXCLK, DDR2 EMIF). For more detail on these special  
considerations, see the Peripheral Clocking Considerations section of theTMS320DM36x DMSoC ARM  
Subsystem Reference Guide (literature number SPRUFG5).  
3.4 Power and Sleep Controller (PSC)  
In the device system, the Power and Sleep Controller (PSC) is responsible for managing transitions of  
system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in Figure 3-5. Many of  
the operations of the PSC are transparent to software, such as power-on-reset operations. However, the  
PSC provides you with an interface to control several important clock and reset operations.  
The PSC includes the following features:  
•
•
Manages chip power-on/off, clock on/off, and resets  
Provides a software interface to:  
–
–
Control module clock ON/OFF  
Control module resets  
•
Supports IcePick emulation features: power, clock, and reset  
DMSoC  
PLLC  
clks  
ARM  
arm_clock  
arm_mreset  
arm_power  
PSC  
Interrupt  
AINTC  
Emulation  
MODx  
RESETN  
module_clock  
module_mreset  
module_power  
Always on  
VDD  
domain  
Figure 3-5. Power and Sleep Controller (PSC)  
For more information on the PSC, see the TMS320DM36x DMSoC ARM Subsystem Reference Guide  
(literature number SPRUFG5).  
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3.5 Pin Multiplexing  
The device makes extensive use of pin multiplexing to accommodate the large number of peripheral  
functions in the smallest possible package. In order to accomplish this, pin multiplexing is controlled using  
a combination of hardware configuration (at device reset) and software control. No attempt is made by the  
hardware to ensure that the proper pin muxing has been selected for the peripherals or interface mode  
being used, thus proper pin muxing configuration is the responsibility of the board and software designers.  
An overview of the pin multiplexing is shown in Table 3-10.  
All pin multiplexing options are configurable by software via pin mux registers that reside in the System  
Control Module. The PinMux0 Register controls the Video In muxing, PinMux1 register controls Video Out  
signals, PinMux2 register controls AEMIF signals, PinMux3 registers control the multiplexing of the GIO  
signals, the PinMux4 register controls the SPI and MMC/SD0 signals. See the TMS320DM36x DMSoC  
ARM Subsystem Reference Guide (literature number SPRUFG5) for complete descriptions of the pin mux  
registers.  
The device configuration pins are multiplexed with AEMIF pins. Note that the AECFG[2:0] inputs only  
select the default AEMIF address pin muxing. The number of active address pins may be increased or  
reduced at any time by modifying the appropriate bits in the PinMux2 control register. After the device  
configuration pins are sampled at reset, they automatically change to function as AEMIF pins. For more  
details on AEMIF default configuration, see Section 3.7.5.  
Table 3-10. Peripheral Pin Mux Overview  
Peripheral  
VPFE (video in)  
VPBE (video out)  
AEMIF  
Muxed With  
GPIO and SPI3  
GPIO, PWM, and RTO  
GPIO  
Primary Function  
GPIO  
Secondary Function  
VPFE (video in)  
VPBE (video out)  
GPIO  
Tertiary Function  
SPI3  
GPIO  
PWM & RTO  
AEMIF  
GPIO  
McBSP  
GPIO  
McBSP  
MMC/SD0  
MMC/SD1  
CLKOUT  
MMC/SD0  
GPIO  
GPIO and EMIF  
GPIO  
MMC/SD1  
CLKOUT  
I2C  
EMIF  
GPIO  
I2C  
GPIO  
GPIO  
UART0/UART1  
GPIO  
GPIO  
UART  
SPI  
SPI0,SPI1,SPI2,SPI4 GPIO  
GPIO  
EMAC  
HPI  
GPIO  
GPIO  
EXTINT  
HPI  
EMAC  
AEMIF  
AEMIF  
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3.6 Device Reset  
There are five types of reset. The types of reset differ by how they are initiated and/or by their effect on  
the chip. Each type is briefly described in Table 3-11 and further described in the TMS320DM36x DMSoC  
ARM Subsystem Reference Guide (literature number SPRUFG5).  
Table 3-11. Reset Types  
Type  
Initiator  
Effect  
POR (Power-On-Reset)  
RESET pin low and TRST low  
Total reset of the chip (cold reset).  
Activates the POR signal on chip, which is used to reset  
test/emulation logic.  
Warm Reset  
Max Reset  
RESET pin low  
Resets everything except for test/emulation logic.  
ARM emulator stays alive during Warm reset.  
ARM emulator or Watchdog Timer  
(WDT)  
Same effect as warm reset.  
System Reset  
ARM emulator  
A soft reset.  
Soft reset maintains memory contents, and does not affect or reset  
clocks or power states.  
Module Reset  
ARM software  
Can independently apply reset to each module, via an MMR.  
Intended as a debug tool, and not necessarily for general use.  
3.7 Default Device Configurations  
After POR, warm reset, and max reset, the chip is in its default configuration. This section highlights the  
default configurations associated with PLLs, clocks, ARM boot mode, and AEMIF.  
Note: Default configuration is the configuration immediately after POR, warm reset, and max reset and  
just before the boot process begins. The boot ROM updates the configuration. See Section 3.2 for more  
information on the boot process.  
3.7.1 Device Configuration Pins  
The device configuration pins are described in Table 3-12. The device configuration pins are latched at  
reset and allow you to configure all of the following options at reset:  
•
•
ARM Boot Mode  
Asynchronous EMIF pin configuration  
These pins are described further in the following sections.  
Note: The device configuration pins are multiplexed with AEMIF pins. After the device configuration pins  
are sampled at reset, they automatically change to function as AEMIF pins. Pin multiplexing is described  
in Section 3.5.  
Table 3-12. Device Configuration  
Default Setting (by internal  
Sampled  
Pin  
pull-up/  
pull-down)  
Device Configuration Input  
Function  
Selects ARM boot mode  
BTSEL[2:0]  
EM_A[13:11]  
000  
000 = Boot from ROM (NAND)  
001 = Boot from AEMIF  
(Boot from ROM - NAND)  
010 = Boot from ROM (MMC/SD)  
011 = Boot from ROM (UART)  
100 = Boot from ROM (USB)  
101 = Boot from ROM (SPI)  
110 = Boot from ROM (EMAC)  
111 = Boot from ROM (HPI)  
AECFG[2:0]  
AEMIF Configuration(1)  
EM_A[10:8]  
000  
AECFG[2] = '0' for 8-bit AEMIF configuration  
AECFG[2] = '1' for 16-bit AEMIF configuration  
(8-bit NAND)  
(1) Other supported AECFG[2:0] combinations can be found in Table 3-14 .  
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Table 3-12. Device Configuration (continued)  
Default Setting (by internal  
Sampled  
Pin  
pull-up/  
pull-down)  
Device Configuration Input  
Function  
Oscillator Configuration  
OSCCFG  
GIO81  
0
OSCCFG = '0' for mode #1  
OSCCFG = '1' for mode #2  
(Mode #1)  
3.7.2 PLL Configuration  
After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations. The  
PLLs are in bypass mode and disabled by default. This means that the input reference clock at MXI1  
(typically 24 MHz) drives the chip after reset. For more information on device clocking, see Section 3.3 .  
The default state of the PLLs is reflected in the default state of the register bits in the PLLC registers.  
Refer to the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).  
3.7.3 Power Domain and Module State Configuration  
Only a subset of modules are enabled after reset by default. Table 3-13 shows which modules are  
enabled after reset. Table 3-13 shows that the following modules are enabled depending on the sampled  
state of the device configuration pins. For example, if UART boot mode is BTSEL[2:0] = 011, then the  
default state of the UART module is enabled. For more information on module configuration, refer to the  
TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).  
Table 3-13. LPSC Assignments and Module Configuration(1)  
LPSC/  
MODULE  
NUMBER  
MODULE NAME  
BTSEL [2:0]  
000  
001  
010  
011  
100  
101  
110  
111  
ROM  
(MMC/SD0  
)
ROM  
(NAND)  
ROM  
(UART0)  
ROM  
(USB)  
ROM  
(SPI0)  
ROM  
(EMAC)  
AEMIF  
ROM (HPI)  
0
1
EDMA CC  
EDMA TC0  
EDMA TC1  
EDMA TC2  
EDMA TC3  
TIMER3  
SPI1  
On  
On  
On  
On  
On  
On  
On  
On  
2
3
4
5
6
7
MMC_SD1  
McBSP  
8
9
USB  
On  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
PWM3  
SPI2  
RTO  
DDR EMIF  
AEMIF  
On  
On  
MMC/SD0  
Reserved  
TIMER4  
I2C  
On  
UART0  
On  
UART1  
(1) "(Blank)" in the above table indicates module is disabled.  
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(1)  
Table 3-13. LPSC Assignments and Module Configuration  
(continued)  
LPSC/  
MODULE  
NUMBER  
MODULE NAME  
BTSEL [2:0]  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
UHPI  
SPI0  
On  
On  
On  
PWM0  
PWM1  
PWM2  
GPIO  
TIMER0  
TIMER1  
TIMER2  
SYSTEM  
ARM  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
Reserved  
Reserved  
Reserved  
EMULATION  
Reserved  
Reserved  
SPI3  
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved  
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
On  
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved  
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved  
SPI4  
EMAC  
On  
RTC  
On  
On  
On  
On  
On  
On  
On  
On  
KEYSCAN  
ADC  
Voice Codec  
VDAC CLKREC  
VDAC CLK  
VPSS MASTER  
Reserved  
Reserved  
MJCP  
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved  
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved  
HDVICP  
3.7.4 ARM Boot Mode Configuration  
The ARM can boot from either Asynchronous EMIF (OneNand/NOR) or from ARM ROM, as determined  
by the setting of the device configuration pins BTSEL[2:0]. The boot selection pins (BTSEL[2:0]) determine  
the ARM boot process. After reset (POR, warm reset, or max reset), ARM program execution begins in  
ARM ROM at 0x0000: 8000, except when BTSEL[2:0] = 001, indicating AEMIF (OneNand/NOR) flash  
boot.  
Boot modes are further described in Section 3.2.  
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3.7.5 AEMIF Configuration  
3.7.5.1 AEMIF Pin Configuration  
The input pins AECFG[2:0] determine the AEMIF configuration immediately after reset. Pins that are not  
assigned to another peripheral and not enabled as address signals become GPIOs. These may be used  
as ALE and CLE signals for NAND Flash control if booting from internal ROM. If booting from NOR Flash  
then the appropriate number of address output must be enabled by the AECFG[2:0] inputs at reset. The  
enabled address signals are always contiguous from EM_BA[1] upwards; bits cannot be skipped. EM_A[0]  
does not represent the lowest AEMIF address bit. The device has 23 address lines and 2 chip selects with  
an 8-bit or 16-bit option. The device supports only 8-bit and 16-bit data widths for the AEMIF.  
•
16-bit mode: EM_BA[1] represents the LS address bit (the half-word address) and EM_BA[0]  
represents address bit (A[14]). The maximum number of address lines pins in 16-bit mode are 23,  
which include EM_BA[1] + EM_A[0:13] +EM_BA[0] (as pin A[14] via PINMUX2 register) + EM_A[15:20]  
+EM_A[21] (via PINMUX4 register)  
Note: Pins EM_A[15:21] are available by programming the PinMux4 register in software after boot, but  
must be pulled down externally so that valid voltage levels are provided on the full set of address pins  
during boot time. EM_A[15:21] come out of reset as GPIO pins per the PinMux4 register.  
•
8-bit mode: EM_BA[1:0] represent the 2 LS address bits. Additional selections are available by  
programming the PinMux2 register in software after boot. The maximum number of address lines in  
8-bit mode are 23, which include EM_BA[0:1] + EM_A[0:13] + A[14] (via PINMUX4 register) +  
EM_A[15:20].  
Note: Pins EM_A[15:20] are available by programming the PinMux4 register in software after boot, but  
must be pulled down externally so that valid voltage levels are provided on the full set of address pins  
during boot time. EM_A[15:20] come out of reset as GPIO pins per the PinMux4 register.  
For additional details about the PinMux2 and PinMux4 registers, see the TMS320DM36x DMSoC ARM  
Subsystem Reference Guide (literature number SPRUFG5).  
The device's pin-mux control logic allows all of the Asynchronous EMIF address pins to be used as  
GPIOs. If devices (such as NAND Flash) attached to the AEMIF require less than the 16 address pins  
provided, then the unused upper-order addresses may be configured as GPIOs. These pins must be  
configured at reset so that pins being driven by the AEMIF with addresses will not cause bus contention  
with pins being driven by the system as general purpose inputs.  
The AECFG[2:0] value does not affect the operation of the AEMIF module itself, only which of its address  
bits are seen on the device pins (resulting in the natural ramifications if devices don’t receive all address  
signals or if contention with general purpose inputs occurs). As shown in Table 3-14, the number of  
address bits enabled on the AEMIF is selectable from 0 to 16 at boot time, see notes above for additional  
support of up-to 23 address lines.  
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Table 3-14. AECFG (Async EMIF Configuration) Coding at Boot Time  
000  
001  
010  
100  
101  
110  
GPIO[65]  
GPIO[66]  
GPIO[67]  
EM_A[1]  
EM_A[2]  
GPIO[68]  
GPIO[69]  
GPIO[70]  
GPIO[71]  
GPIO[72]  
GPIO[73]  
GPIO[74]  
GPIO[75]  
GPIO[76]  
GPIO[77]  
GPIO[78]  
GPIO[57]  
GPIO[58]  
GPIO[59]  
GPIO[60]  
GPIO[61]  
GPIO[62]  
GPIO[63]  
GPIO[64]  
EM_A[14]  
EM_BA[1]  
EM_A[0]  
EM_A[1]  
EM_A[2]  
EM_A[3]  
EM_A[4]  
EM_A[5]  
EM_A[6]  
EM_A[7]  
EM_A[8]  
EM_A[9]  
EM_A[10]  
EM_A[11]  
EM_A[12]  
EM_A[13]  
GPIO[46]  
GPIO[47]  
GPIO[48]  
GPIO[49]  
GPIO[50]  
GPIO[51]  
GPIO[52]  
GPIO[53]  
EM_BA[0]  
EM_BA[1]  
EM_A[0]  
EM_A[1]  
EM_A[2]  
EM_A[3]  
EM_A[4]  
EM_A[5]  
EM_A[6]  
EM_A[7]  
EM_A[8]  
EM_A[9]  
EM_A[10]  
EM_A[11]  
EM_A[12]  
EM_A[13]  
GPIO[46]  
GPIO[47]  
GPIO[48]  
GPIO[49]  
GPIO[50]  
GPIO[51]  
GPIO[52]  
GPIO[53]  
GPIO[65]  
GPIO[66]  
GPIO[67]  
EM_A[1]  
EM_A[2]  
GPIO[68]  
GPIO[69]  
GPIO[70]  
GPIO[71]  
GPIO[72]  
GPIO[73]  
GPIO[74]  
GPIO[75]  
GPIO[76]  
GPIO[77]  
GPIO[78]  
EM_D[8]  
EM_D[9]  
EM_D[10]  
EM_D[11]  
EM_D[12]  
EM_D[13]  
EM_D[14]  
EM_D[15]  
EM_A[14]  
EM_BA[1]  
EM_A[0]  
EM_A[1]  
EM_A[2]  
EM_A[3]  
EM_A[4]  
EM_A[5]  
EM_A[6]  
EM_A[7]  
EM_A[8]  
EM_A[9]  
EM_A[10]  
EM_A[11]  
EM_A[12]  
EM_A[13]  
EM_D[8]  
EM_D[9]  
EM_D[10]  
EM_D[11]  
EM_D[12]  
EM_D[13]  
EM_D[14]  
EM_D[15]  
EM_BA[0]  
EM_BA[1]  
EM_A[0]  
EM_A[1]  
EM_A[2]  
EM_A[3]  
EM_A[4]  
EM_A[5]  
EM_A[6]  
EM_A[7]  
EM_A[8]  
EM_A[9]  
EM_A[10]  
EM_A[11]  
EM_A[12]  
EM_A[13]  
EM_D[8]  
EM_D[9]  
EM_D[10]  
EM_D[11]  
EM_D[12]  
EM_D[13]  
EM_D[14]  
EM_D[15]  
3.7.5.2 AEMIF Timing Configuration  
When AEMIF is enabled, the wait state registers are reset to the slowest possible configuration, which is  
88 cycles per access (16 cycles of setup, 64 cycles of strobe, and 8 cycles of hold). Thus, with a 24 MHz  
clock at MXI/MXO, the AEMIF is configured to run at (12 MHz/ 88) which equals approximately 136.36  
kHz.  
3.7.6 Oscillator Frequency Configuration  
The oscillator input pins, MXI1, MXO, are designed to operate in two frequency ranges depending on the  
GIO81(OSCCFG) pin sampled at reset, which should be set according to the required input frequency of  
operation. See Table 3-15 for details.  
Table 3-15. Operation Frequency  
MODE  
GIO81 (OSCCFG)  
OSCILLATION  
15 - 35MHz  
1
2
0
1
30 - 40MHz  
The frequency selection pin cannot be changed dynamically while the oscillator is running. They should  
only be set once before oscillator startup.  
The GIO81(OSCCFG) state is latched during reset, and it specifies the oscillation frequency mode as  
shown in Table 3-15.  
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3.8 Debugging Considerations  
3.8.1 Pullup/Pulldown Resistors  
Proper board design should ensure that input pins to the DMSoC device always be at a valid logic level  
and not floating. This may be achieved via pullup/pulldown resistors. The DMSoC features internal pullup  
(IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for  
external pullup/pulldown resistors.  
An external pullup/pulldown resistor needs to be used in the following situations:  
•
Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external  
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired  
value/state.  
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external  
pullup/pulldown resistor to pull the signal to the opposite rail.  
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly  
recommended that an external pullup/pulldown resistor be implemented. Although, internal  
pullup/pulldown resistors exist on these pins and they may match the desired configuration value,  
providing external connectivity can help ensure that valid logic levels are latched on these device boot and  
configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration  
pins adds convenience to the user in debugging and flexibility in switching operating modes.  
Tips for choosing an external pullup/pulldown resistor:  
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure  
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or  
pulldown resistors.  
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of  
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all  
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of  
the limiting device; which, by definition, have margin to the VIL and VIH levels.  
•
•
Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net  
will reach the target pulled value when maximum current from all devices on the net is flowing through  
the resistor. The current to be considered includes leakage current plus, any other internal and  
external pullup/pulldown resistors on the net.  
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance  
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer  
can drive the net to the opposite logic level (including margin).  
•
•
Remember to include tolerances when selecting the resistor value.  
For pullup resistors, also remember to include tolerances on the DVDD rail.  
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria.  
Users should confirm this resistor value is correct for their specific application.  
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and configuration  
pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific  
application.  
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for  
the device, see Section 5.2, Recommended Operating Conditions.  
For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal  
functions table.  
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4 System Interconnect  
The device uses a 64-bit crossbar architecture to control access between device processors, subsystems  
and peripherals. There are eleven transfer masters (TCs have separate read and write connections)  
connected to the crossbar; ARM, the Video Processing Subsystem (VPSS), the master peripherals (USB,  
EMAC, HPI), and four EDMA transfer controllers. These can be connected to seven separate slave ports;  
ARM, the DDR EMIF, CFG bus peripherals, MJCP, and HDVICP. Not all masters may connect to all  
slaves. Connection paths are indicated by √ at intersection points shown in Table 4-1.  
Table 4-1. System Connection Matrix  
SLAVE MODULE  
DMA  
Master  
ARM Internal  
Memory  
MPEG/JPEG  
Coprocessor  
Memory  
HD Video Image  
Coprocessor  
Memory  
Config Bus Registers  
DDR EMIF  
Memory  
and  
Memory  
ARM  
√
√
√
√
√
√
√
√
√
VPSS  
DMA Master Peripherals  
(USB, EMAC, HPI)  
EDMA3TC0  
EDMA3TC1  
EDMA3TC2  
EDMA3TC3  
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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5 Device Operating Conditions  
5.1 Absolute Maximum Ratings Over Operating Case Temperature Range  
(1) (2)  
(Unless Otherwise Noted)  
All 1.2-V / 1.35-V supplies  
-0.3 V to 1.6 V  
-0.3 V to 2.45 V  
-0.3 V to 3.8 V  
-0.5 V to 2.6 V  
-0.5 V to 3.8 V  
0 V to 5.5 V  
Supply voltage ranges  
Input voltage ranges  
All 1.8 V supplies  
All 3.3 V supplies  
All 1.8 V I/Os  
All 3.3 V I/Os  
USB_VBUS  
Commercial Temperature Tc  
Extended Temperature [D version devices] Tc  
Tstg  
0°C to 85 °C  
Operating case temperature ranges  
Storage temperature ranges  
-40°C to 85 °C  
-55°C to 150°C  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to VSS.  
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5.2 Recommended Operating Conditions  
NAME  
DESCRIPTION  
MIN  
1.14  
1.28  
NOM  
1.2  
MAX UNIT  
CVDD  
Core Supply Voltage  
216, 270-MHz devices  
300-MHz devices  
1.26  
1.42  
V
1.35  
PRTCSS Oscillator and  
PRTCSS Core Supply Voltage  
VDD12_PRTCSS  
216, 270-MHz devices  
1.14  
1.2  
1.26  
V
V
300-MHz devices  
1.28  
1.14  
1.28  
1.14  
1.28  
1.35  
1.2  
1.42  
1.26  
1.42  
1.26  
1.42  
VDDA12_DAC  
1.2-V DAC Supply Voltage  
VPP Supply Voltage  
216, 270-MHz devices  
300-MHz devices  
1.35  
1.2  
(1)  
VPP  
216, 270-MHz devices  
300-MHz devices  
V
V
1.35  
VDDS18  
1.8-V Supply Voltage  
VDD18_PRTCSS  
VDDMXI  
1.8-V PWR CTRL Supply Voltage  
1.8-V System Oscillator Supply Voltage  
1.8-V DDR2 Supply Voltage  
1.8-V PLL Supply Voltage  
1.8-V USB Supply Voltage  
1.8-V Voice CODEC Supply Voltage  
1.8-V USB Supply Voltage  
1.8-V ADC Supply Voltage  
1.8-V DAC Supply Voltage  
1.8/3.3-V switchable EMIF1 Supply Voltage  
1.8/3.3-V switchable EMIF2 Supply Voltage  
1.8/3.3-V switchable ISIF Supply Voltage  
3.3-V Supply Voltage  
VDD18_DDR  
VDDA18_PLL  
VDDA18_USB  
VDDA18_VC  
VDDA18_USB  
VDDA18_ADC  
VDDA18_DAC  
VDD_AEMIF1_18_33  
VDD_AEMIF2_18_33  
VDD_ISIF18_33  
VDDS33  
1.71  
1.8  
1.89  
V
Supply  
Voltage  
1.71/3.14  
3.14  
1.8/3.3  
3.3  
1.89/3.46  
3.46  
V
V
VDDA33_USB  
VDDA33_VC  
VSS  
3.3-V USB Supply Voltage  
3.3-V Voice CODEC Supply Voltage  
Core, USB Digital ground  
OSC (MX1) ground(2)  
VSS_MX1  
VSS_32K  
OSC (32K) ground(2)  
VSSA  
PLL ground(3)  
VSSA18_USB  
VSSA33_USB  
VSSA33_VC  
VSSA18_VC  
VSSA_ADC  
VSSA18_DAC  
VSSA12_DAC  
USB ground  
Supply  
Ground  
3.3-V USB ground  
0
0
0
V
3.3-V Voice CODEC ground  
1.8-V Voice CODEC ground  
ADC ground  
1.8-V DAC ground  
1.2-V DAC ground  
High-level input voltage(4), excludes switchable I/O  
(3.3V I/O)  
2
V
V
Voltage Input  
High  
VIH  
High-level input voltage, non-DDR2 I/O, excludes switchable I/O  
(1.8V I/O)  
0.7VDDS18  
(1) For proper device operation, this pin must always be connected to CVDD  
.
(2) Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground (see  
Section 6.6.1 ).  
(3) For proper device operation, keep this pin separate from digital ground.  
(4) These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os. DDR2/mDDR I/Os are 1.8 V I/Os and  
adhere to JESD79-2A standard, USB I/Os adhere to USB2.0 spec.  
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NAME  
DESCRIPTION  
MIN  
NOM  
MAX UNIT  
0.75*VDD  
12_PRTC  
SS  
High-level input voltage I/O (1.2-V or 1.35-V)  
(PWRCNT/PWRST/RTCXI/RTCXO)  
VIH12RTC  
V
HIgh-level switchable input  
voltage(4)  
3.3V I/O mode  
2
(VDD_AEMIF1_18_33,  
VDD_AEMIF2_18_33,  
VDD_ISIF_18_33 powered  
I/Os)(5)(6)(7)(8)  
VIH1833  
V
1.8V I/O mode  
0.7VDDS18  
Low-level input voltage(4), excludes switchable I/O  
(3.3V I/O)  
Low-level input voltage(4), non-DDR2 I/O, excludes switchable I/O  
(1.8V I/O)  
0.8  
V
V
VIL  
0.3*VDDS  
18  
0.25*VDD  
12_PRTC  
SS  
RTC Low-level input voltage(4)  
(1.2V I/O)  
VIL12RTC  
V
V
Voltage Input  
Low  
Low-level switchable input  
voltage(4)  
(VDD_AEMIF1_18_33,  
VDD_AEMIF2_18_33,  
VDD_ISIF_18_33 powered  
I/Os)  
3.3V I/O mode  
1.8V I/O mode  
0.8  
VIL1833  
0.3*VDDS  
18  
VREF  
DAC reference voltage  
475  
2376  
74.25  
500  
2400  
75  
525  
2424  
75.75  
mV  
Ω
RBIAS  
RLOAD_X  
CBG  
DAC full-scale current adjust resistor  
Output resistor  
HD 3CH DAC(9)  
Ω
Bypass capacitor  
0.1  
uF  
ROUT  
Output resistor (ROUT), between TVOUT and VFB pins  
Feedback resistor, between VFB and IDACOUT pins.  
Full-scale current adjust resistor  
Bypass capacitor  
2128.5  
2079  
2150  
2100  
2400  
0.1  
2171.5  
2121  
Ω
RFB  
Video Buffer(9)  
RBIAS  
CBG  
Ω
uF  
USB_VBUS  
VDDA12LDO_USB  
fs  
USB external charge pump input  
Internal LDO output(10)  
0
8
5.25  
V
USB  
0.22  
µF  
Sampling frequency  
16  
256fs  
2
kHz  
kHz  
MHz  
°C  
Voice Codec  
ADC  
-
System clock  
FSCLK  
SCLK frequency  
Default Temperature  
0
85  
Operating case temperature  
range  
Temperature  
Tc  
Extended Temperature [D version  
devices]  
-40  
85  
°C  
(5) VDD_AEMIF1_18_33 : can be used as a power supply for EM_A[3:13], EM_BA0, EM_BA1, EM_CE[0], EM_ADV, EM_CLK, EM_D[8:15  
]pins, Keyscan, or GPIO pins.  
(6) VDD_AEMIF2_18_33: can be used as a power supply for EM_A[0:2], EM_CE[1], EM_WE, EM_OE, EM_WAIT, EM_D[0:7] pins, HPI,  
Keyscan, or GPIO pins.  
(7) Example 1: VDD_AEMIF2_18_33 at 1.8-V for 8-bit NAND VDD_AEMIF1_18_33 at 3.3-V for GPIO.  
Example 2: VDD_AEMIF1_18_33 and VDD_AEMIF2_18_33 at 1.8-V for 16-bit NAND.  
(8) VDD_ISIF_18_33: can be used as a power supply for VPFE pins (CIN[7:0], YIN[7:0], C_WE_FIELD, PCLK), or SPI3  
(SPI3_SCLK,SPI3_SIMO,SPI3_SCS[0], SPI3_SCS[1]) or USBDRVVBUS or GPIO pins.  
(9) See Section 6.12.2.4 . Also, resistors should be E-96 spec line (3 digits with 1% accuracy).  
(10) For proper device operation, this pin must be connected to a 0.22mF capacitor to VDDA12LDO_USB  
.
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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage  
and Operating Case Temperature (Unless Otherwise Noted)  
(1)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
High-level output voltage  
(3.3V I/O)  
VDDS33 = MIN, IOH = -2mA  
2.4  
High-level output voltage  
(3.3V I/O)  
VOH  
VDDS33 = MIN, IOH = -100mA  
VDDS18 = MIN, IOH = -2mA  
VDDS33 = MIN, IOL = 2mA  
VDDS33 = MIN, IOL = 100mA  
VDDS18 = MIN, IOH = 2mA  
VI = VSS to V DD  
2.94  
V
High-level output voltage  
(1.8V I/O)  
VDDS18  
-
0.45  
Voltage  
Output(2)  
Low-level output voltage  
(3.3V I/O)  
0.4  
0.2  
Low-level output voltage  
(3.3V I/O)  
VOL  
V
Low-level output voltage  
(1.8V I/O)  
0.45  
±10  
Input current for I/O without  
internal pull-up/pull-down  
II  
Input current for I/O with  
II(pullup)  
II(pulldown)  
VI = VSS to VDD  
100  
(4)  
internal pull-up(3)  
Input current for I/O with  
Current  
Input/Output  
VI = VSS to VDD  
-100  
(4)  
internal pull-down(3)  
mA  
IOH  
IOL  
High-level output current  
Low-level output current  
All peripherals  
All peripherals  
-4000  
4000  
VO = VDD or VSS  
(internal pull disabled)  
(5)  
IOZ  
I/O off-state output current  
±20  
CI  
Input capacitance  
Output capacitance  
Resolution  
4
4
Capacitance  
pF  
CO  
Resolution  
10  
Bits  
RLOAD = 75 Ω  
(video buffer disabled)  
INL  
Integral non-linearity, best fit  
Differential non-linearity  
-1.5  
1.5  
1
LSB  
RLOAD = 75 Ω  
(video buffer disabled)  
DNL  
-1  
0
LSB  
HD 3CH  
DAC  
VOUT  
Output compliance range  
Zero Scale Offset Error  
Gain Error  
IFS = 6.67 mA, RLOAD = 75 Ω  
VREF  
0.5  
5
V
ZSET  
%
%
%
G_ERR  
Ch_match  
-5  
Channel matching  
+/-2  
Output high voltage  
(top of 75% NTSC or PAL colorbar)  
VOH(VIDBUF)  
VOL(VIDBUF)  
1.35  
V
Output low voltage  
(bottom of sync tip)  
0.35  
10  
Video Buffer  
RES  
VOUT  
Resolution  
bits  
V
Output Voltage  
RLOAD = 75 Ω  
0.35  
1.35  
(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.  
(2) These I/O specifications apply to regular 3.3 V and 1.8V I/Os and do not apply to DDR2/mDDR, USB I/Os. DDR2/mDDR I/Os are 1.8 V  
I/Os and adhere to JESD79-2A standard, USB I/Os adhere to USB2.0 spec.  
(3) This specification applies only to pins with an internal pullup (PU) or pulldown (PD). See or Section 2.8 for pin descriptions.  
(4) To pull up a signal to the opposite supply rail, a 1 kΩ resistor is recommended.  
(5) IOZ applies to output only pins, indicating off-state (Hi-Z) output leakage current.  
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(1)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
MIC in to ADC (gain = 20 dB)  
Vmic  
Full scale input  
Gain error  
0.063  
0
Vrms  
dB  
V
GeAD  
Vcom  
Common voltage  
THD + N  
0.9  
-62  
70  
-1db, 1kHz  
A-weighted  
A-weighted  
dB  
dB  
dB  
kΩ  
pF  
DNR  
SNR  
67  
Input resistance  
Input capacitance  
10  
10  
DAC-to-Line Output  
Full scale output  
Gain error  
0.8  
0
Vrms  
dB  
V
Common voltage  
THD + N  
1.5  
-60  
70  
70  
dB  
dB  
dB  
kΩ  
pF  
DNR  
A-weighted  
A-weighted  
SNR  
Load resistance  
Load capacitance  
10  
Voice  
Codec  
20  
50  
DAC-to-Speaker Output  
RL = 8Ω, THD = 10%  
A-weighted  
Output power  
240  
120  
mW  
mVrms  
Ω
Output noise  
Load resistance  
Load capacitance  
8
pF  
Decimation filter in ADC  
Pass band  
0.375fs  
+/- 0.2  
0.562fs  
40  
kHz  
dB  
Pass band ripple  
Stop band  
kHz  
dB  
Stop band attenuation  
HPF cutoff frequency  
1.25mfs  
Hz  
Interpolation filter in DAC  
Pass band  
0.437fs  
+/- 0.2  
0.562fs  
40  
kHz  
dB  
Pass band ripple  
Stop band  
kHz  
dB  
Stop band attenuation  
Static differential non-linearity error  
Static integral non-linearity error  
Zero scale offset error  
Full scale offset error  
DNL  
INL  
FSCLK = 2MHz  
FSCLK = 2MHz  
-1  
-3  
-6  
-6  
2.5  
3
LSB  
LSB  
LSB  
LSB  
ADC  
ZSET  
FSET  
6
6
76  
Device Operating Conditions  
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6 Peripheral Information and Electrical Specifications  
6.1 Parameter Information Device-Specific Information  
Tester Pin Electronics  
Data Sheet Timing Reference Point  
42 Ω  
3.5 nH  
Output  
Under  
Test  
Transmission Line  
Z0 = 50 Ω  
(see note)  
Device Pin  
(see note)  
4.0 pF  
1.85 pF  
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its  
transmission line effects must be taken into account. A model of the tester pin electronics is shown in Figure 6-1. A  
transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The  
transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or  
longer) from the data sheet timings.  
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the  
device pin and the input signals are driven between 0V and the appropriate I/O supply for the signal.  
Figure 6-1. Test Load Circuit for AC Timing Measurements  
The load capacitance value stated is only for characterization and measurement of AC timing signals. This  
load capacitance value does not indicate the maximum load the device is capable of driving.  
6.1.1 Signal Transition Levels  
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,  
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.  
V
ref  
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements  
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,  
VOLMAX and VOH MIN for output clocks.  
V
ref  
= V MIN (or V MIN)  
IH OH  
V
ref  
= V MAX (or V MAX)  
IL OL  
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels  
6.1.2 Timing Parameters and Board Routing Analysis  
The timing parameter values specified in this data sheet do not include delays by board routings. As a  
good board design practice, such delays must always be taken into account. Timing values may be  
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer  
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS  
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing  
Analysis Application Report (literature number SPRA839). If needed, external logic hardware such as  
buffers may be used to compensate any timing differences.  
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6.2 Recommended Clock and Control Signal Transition Behavior  
All clocks and control signals should transition between VIH and VIL (or between VIL and VIH) in a  
monotonic manner.  
6.3 Power Supplies  
The power supplies are summarized in Table 6-1.  
Table 6-1. Power Supplies  
CUSTOMER  
BOARD SUPPLY  
TOLERANCE  
PACKAGE  
PLANE  
DEVICE PLANE  
DESCRIPTION  
1.2V or 1.35V  
±5%  
1.2V or 1.35V CVDD  
VDD12_PRTCSS  
Core power supply  
RTC oscillator power supply  
PWR CTRL power supply  
PWR CTRL 1.2-V or 1.35-V I/O power supply  
DAC 1.2-V or 1.35-V analog power supply  
VPP power supply  
VDDA12_DAC  
VPP  
VDD18_PRTCSS  
VDDMXI  
1.8 V  
±5%  
1.8 V  
PWR CTRL 1.8-V power supply  
MXI1 (oscillator) 1.8-V power supply  
VDD18_SLDO  
Power supply for internal RAM  
For proper device operation, this pin must be connected to VDDS18  
.
VDD18_DDR  
VDDA18_PLL  
VDDA18_USB  
VDDA18_VC  
VDDA18_DAC  
VDDS18  
1.8-V DDR2 Supply Voltage  
1.8-V PLL Analog Supply Voltage  
1.8-V USB Analog Supply Voltage  
1.8-V Voice Codec Module Analog Supply Voltage  
1.8-V DAC Analog Supply Voltage  
1.8-V Supply Voltage  
VDDA18_ADC  
VDDS33  
1.8-V ADC Supply Voltage  
3.3 V  
±5%  
±5%  
3.3 V  
3.3-V I/O Supply Voltage  
VDDA33_USB  
VDDA33_VC  
VDD_AEMIF1_18_33  
3.3-V USB Analog Supply Voltage  
3.3-V Voice Codec Module Analog Supply Voltage  
(1)  
1.8/3.3 V  
1.8/3.3 V  
Switchable 3.3/1.8-V EMIF1 Supply Voltage  
Note: Power supply is switchable for AEMIF and its multiplexed  
(2)  
peripherals (3.3/1.8 V)  
.
(3)  
VDD_AEMIF2_18_33  
Switchable 3.3/1.8-V EMIF2 Supply Voltage  
Note: Power supply is switchable for AEMIF and its multiplexed  
(2)  
peripherals (3.3/1.8 V)  
.
(4)  
VDD_ISIF18_33  
Switchable 3.3/1.8-V ISIF Supply Voltage  
Note: Power supply is switchable for ISIF and its multiplexed  
peripherals (3.3V/1.8V)(5)  
0 V  
0 V  
0 V  
0 V  
0 V  
0 V  
VSS_MX1  
Oscillator (MXI1) ground  
Note: For proper device operation, connect to external crystal  
capacitor ground and must be kept separate from other grounds.  
VSS_32K  
Oscillator (32K) ground  
Note: For proper device operation, connect to external crystal  
capacitor ground and must be kept separate from other grounds.  
VSS  
Ground  
(1) VDD_AEMIF1_18_33 : can be used as a power supply for EM_A[3:13], EM_BA0, EM_BA1, EM_CE[0], EM_ADV, EM_CLK, EM_D[8:15  
]pins, Keyscan, or GPIO pins.  
(2) Example 1: VDD_AEMIF2_18_33 at 1.8-V for 8-bit NAND VDD_AEMIF1_18_33 at 3.3-V for GPIO.  
Example 2: VDD_AEMIF1_18_33 and VDD_AEMIF2_18_33 at 1.8-V for 16-bit NAND.  
(3) VDD_AEMIF2_18_33: can be used as a power supply for EM_A[0:2], EM_CE[1], EM_WE, EM_OE, EM_WAIT, EM_D[0:7] pins, HPI,  
Keyscan, or GPIO pins.  
(4) VDD_ISIF_18_33: can be used as a power supply for VPFE pins (CIN[7:0], YIN[7:0], C_WE_FIELD, PCLK), or SPI3  
(SPI3_SCLK,SPI3_SIMO,SPI3_SCS[0], SPI3_SCS[1]) or USBDRVVBUS or GPIO pins.  
(5) Example 1 VDD_ISIF_18_33 power supply can be at 1.8V for VPFE pin functionality or it can be at 3.3V if other peripherals pin functionality  
is to be used like SPI3 or GPIO or CLKOUT0, or USBDRVVBUS.  
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Table 6-1. Power Supplies (continued)  
CUSTOMER  
TOLERANCE  
PACKAGE  
DEVICE PLANE  
DESCRIPTION  
BOARD SUPPLY  
PLANE  
0 V  
0 V  
VSSA  
PLL ground  
Note: For proper device operation, keep separate from digital  
ground VSS  
.
0 V  
0 V  
0 V  
0 V  
0 V  
0 V  
0 V  
0 V  
VSSA18_USB  
VSSA33_USB  
VSSA33_VC  
VSSA18_VC  
VSSA_ADC  
USB ground  
0 V  
3.3-V USB ground  
0 V  
3.3-V Voice Codec Module ground  
1.8-V Voice Codec Module ground  
Analog-to-digital converter (ADC) ground  
1.8-V DAC ground  
0 V  
0 V  
0 V  
VSSA18_DAC  
VSSA12_DAC  
0 V  
1.2-V DAC ground  
VDD18_DDR*0.5  
VDD18_DDR*0.5 DDR_VREF  
DRR reference voltage  
(VDDS divided by 2, through board resistors)  
0.5V  
±5%  
VREF  
DAC reference voltage  
VBUS  
5.25V  
USB_VBUS  
6.4 Power-Supply Sequencing  
In order to ensure device reliability, the device requires the following power supply power-on and  
power-off sequences. See Section 5.2, Recommended Operating Conditions, for a description of the  
power supplies.  
•
•
The following power sequences are recommended to prevent damage to the device.  
The PRTCSS core must always be powered-on and powered-off regardless of whether the PRTCSS  
feature is used.  
•
If the PRTCSS sequencer is to be used in any PRTCSS modes, please refer to the TMS320DM36x  
PRTCSS User's Guide (literature number SPRUFJ0) for more details on the differences to the power  
sequence.  
6.4.1 Simple Power-On and Power-Off Method  
The following steps must be followed in sequential order for the simple power-on method:  
1. Power on the PRTCSS/ Main core (1.2-V or 1.35-V).  
2. Power on the PRTCSS/Main I/O (1.8-V).  
3. Power on the Main/Analog I/O (3.3-V).  
Note for simple power-on: RESET must be low until all supplies are ramped up.  
The following steps should be followed for the simple power-off method:  
1. Power off the Main/Analog I/O (3.3-V).  
2. Power off the PRTCSS/Main I/O (1.8-V).  
3. Power off the PRTCSS/Main core (1.2-V or 1.35-V).  
Notes for simple power-off:  
–
–
If RESET is low, steps 2 and 3 may be performed simultaneously.  
If RESET is not low, these steps must be followed sequentially.  
6.4.2 Restricted Power-On and Power-Off Method  
The following steps should be followed for the restricted power-on method:  
1. Power on the PRTCSS/ Main core (1.2-V or 1.35-V).  
2. Power on the PRTCSS/Main I/O (1.8-V).  
3. Power on the Main/Analog I/O (3.3-V).  
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Notes for restricted power-on:  
–
–
RESET must be low until all supplies are ramped up.  
Steps 1, 2, and 3 may be performed simultaneously if the Main core finishes ramping up before the  
I/Os and the maximum delta voltage difference between the 1.8-V and 3.3-V I/Os is 2.0-V until the  
1.8-V I/O reaches the full voltage.  
The following steps should be followed for the restricted power-off method:  
1. Power off Main/Analog I/O (3.3-V).  
2. Power off PRTCSS/Main I/O (1.8-V).  
3. Power off PRTCSS/Main core (1.2-V or 1.35-V).  
Notes for restricted power-off:  
–
The 3.3-/1.8-V I/Os may be powered off simultaneously if the maximum delta voltage difference  
between them is 2.0V until the 1.8-V I/O is completely powered off, and the PRTCSS/Main core  
must be powered down last.  
When booting the DM365 from OneNAND, you must ensure that the OneNAND device is ready with valid  
program instructions before the DM365 attempts to read program instructions from it. In particular, before  
you release the device's reset, you must allow time for OneNAND device power to stabilize and for the  
OneNAND device to complete its internal copy routine. During the internal copy routine, the OneNAND  
device copies boot code from its internal non-volatile memory to its internal boot memory section. Board  
designers typically achieve this requirement by design of the system power and reset supervisor circuit.  
Refer to your OneNAND device datasheet for OneNAND power ramp and stabilization times and for  
OneNAND boot copy times.  
6.4.3 Power-Supply Design Considerations  
Core and I/O supply voltage regulators should be located close to the device to minimize inductance and  
resistance in the power delivery path. Additionally, when designing for high-performance applications  
utilizing the device, the PC board should include separate power planes for core, I/O, and ground, all  
bypassed with high-quality low-ESL/ESR capacitors.  
6.4.4 Power-Supply Decoupling  
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as  
possible close to the device. These caps need to be close to the power pins, no more than 1.25 cm  
maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their  
lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560  
pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a  
small package) should be next closest. TI recommends no less than 8 small and 8 medium caps per  
supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the  
corners of the "exterior".  
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order  
of 100 uF) should be furthest away, but still as close as possible. Large caps for each supply should be  
placed outside of the BGA footprint.  
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of  
any component, verification of capacitor availability over the product’s production lifetime should be  
considered. See also Section 6.6.1 for additional recommendations on power supplies for the  
oscillator/PLL supplies.  
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6.5 Reset  
6.5.1 Reset Electrical Data/Timing  
Table 6-2. Timing Requirements for Reset (1) (2) (3) (see Figure 6-4)  
DEVICE  
MIN  
NO.  
UNIT  
MAX  
1
2
3
tw(RESET)  
tsu(BOOT)  
th(BOOT)  
Active low width of the RESET pulse  
12C  
2E  
0
ns  
ns  
ns  
Setup time, boot configuration pins valid before RESET rising edge  
Hold time, boot configuration pins valid after RESET rising edge  
(1) BTSEL[2:0] and AECFG[2:0] are the boot configuration pins during device reset.  
(2) C = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use C = 41.6 ns.  
(3) E = 1/PLLC1SYSCLK4 cycle time in ns.  
1
RESET  
2
3
Boot Configuration Pins  
(BTSEL[2:0], AECFG[2:0])  
Figure 6-4. Reset Timing  
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6.6 Oscillators and Clocks  
The device has one oscillator input/output pair (MXI1/MXO1) usable with external crystals or ceramic  
resonators to provide clock inputs. The optimal frequencies for the crystals are 19.2 MHz, 24 MHz, 27  
MHz, and 36 MHz. Optionally, the oscillator inputs are configurable for use with external clock oscillators.  
If external clock oscillators are used, to minimize the clock jitter, a single clean power supply should power  
both the device and the external oscillator circuit and the minimum CLKIN rise and fall times must be  
observed. The electrical requirements and characteristics are described in this section.  
The timing parameters for CLKOUT[3:1] are also described in this section. The device has three output  
clock pins (CLKOUT[3:1]). See Section 3.3 for more information on CLKOUT[3:1].  
Note: Please ensure that the appropriate oscillator input pin (GIO81/OSCCFG) frequency range setting is  
set correctly. For more details on this pin setting, see Section 3.7.6.  
6.6.1 MXI1 Oscillator  
The MXI1 (typically 24 MHz, can also be 19.2 MHz, 27 MHz, or 36 MHz) oscillator provides the primary  
reference clock for the device. The on-chip oscillator requires an external crystal connected across the  
MXI1 and MXO1 pins, along with two load capacitors, as shown in Figure 6-5. The external crystal load  
capacitors must be connected only to the oscillator ground pin (VSS_MX1). Do not connect to board ground  
(VSS). Also, the PLL power pin (VDDA_PLL1) should be connected to the power supply through a ferrite  
bead, L1 in the example circuit shown in Figure 6-5.  
Note: If an external oscillator is to be used, the external oscillator clock signal should be connected to the  
MXI1 pin with a 1.8V amplitude. The MXO1 should be left unconnected and the VSS_MX1 signal should  
be connected to board ground (Vss).  
MXO1  
V
V
V
SSA_PLL1  
MXI1/CLKIN  
SS_MX1  
DDA_PLL1  
0.1 µF  
0.1 µF  
Crystal  
19.2 MHz  
24 MHz or  
36 MHz  
C1  
C2  
L1  
Figure 6-5. MXI1 Oscillator  
The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are  
C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete  
components used to implement the oscillator circuit should be placed as close as possible to the  
associated oscillator pins (MXI1 and MXO1) and to the VSS_MX1 pin.  
C1C2  
CL  
(C1 C2)  
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Table 6-3. Switching Characteristics Over Recommended Operating Conditions for System Oscillator  
PARAMETER  
Start-up time (from power up until oscillating at stable frequency)  
Oscillation frequency  
MIN  
TYP  
MAX  
UNIT  
ms  
2
19.2/24/2  
7/36  
MHz  
Crystal ESR  
19 - 30 MHz  
30 - 36 MHz  
60  
40  
Ω
Ω
Frequency stability  
+/-50  
ppm  
6.6.2 Clock PLL Electrical Data/Timing (Input and Output Clocks)  
Table 6-4. Timing Requirements for MXI1/CLKIN1(1) (2) (3) (see Figure 6-6)  
DEVICE  
TYP  
NO  
.
UNIT  
MIN  
27.7  
MAX  
1
2
3
4
5
tc(MXI1)  
tw(MXI1H)  
tw(MXI1L)  
tt(MXI1)  
Cycle time, MXI1/CLKIN1  
52.083 ns  
0.55C ns  
0.55C ns  
.05C ns  
.02C ns  
Pulse duration, MXI1/CLKIN1 high  
Pulse duration, MXI1/CLKIN1 low  
Transition time, MXI1/CLKIN1  
Period jitter, MXI1/CLKIN1  
0.45C  
0.45C  
tJ(MXI1)  
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.  
(2) C = MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns.  
(3) tc(MXI1) = 52.083 ns, tc(MXI1) = 41.6 ns, tc(MXI1) = 37.037 ns, and tc(MXI1) = 27.7 ns are the only supported cycle times for  
MXI1/CLKIN1.  
1
5
4
2
MXI1/CLKIN  
3
4
Figure 6-6. MXI1/CLKIN1 Timing  
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Table 6-5. Switching Characteristics Over Recommended Operating Conditions for CLKOUT0/CLKOUT1(1)  
(2) (see Figure 6-7)  
DEVICE  
NO.  
PARAMETER  
UNIT  
MIN  
27.7  
TYP  
MAX  
1
2
3
4
tC(CLKOUT0/CLKOUT1)  
tw(CLKOUT0H/CLKOUT1H)  
tw(CLKOUT0L/CLKOUT1L)  
tt(CLKOUT0/CLKOUT1)  
Cycle time, CLKOUT0/CLKOUT1  
ns  
Pulse duration, CLKOUT0/CLKOUT1 high  
Pulse duration, CLKOUT0/CLKOUT1 low  
Transition time, CLKOUT0/CLKOUT1  
.45P  
.45P  
.55P ns  
.55P ns  
3
ns  
Delay time, MXI1/CLKIN1 high to CLKOUT0/CLKOUT1  
high  
5
6
td(MXI1H-CLKOUT0H/CLKOUT1H)  
td(MXI1L-CLKOUT0L/CLKOUT1L)  
1
1
8
ns  
Delay time, MXI1/CLKIN1I low to CLKOUT0/CLKOUT1  
low  
8
ns  
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOHMIN.  
(2) P = 1/CLKOUT0/1 clock frequency in nanoseconds (ns). For example, when CLKOUT1 frequency is 24 MHz use P = 41.6 ns.  
5
6
MXI1/CLKIN  
2
4
1
CLKOUT0/1  
3
4
Figure 6-7. CLKOUT1 Timing  
Table 6-6. Switching Characteristics Over Recommended Operating Conditions for CLKOUT2(1) (2) (see  
Figure 6-8)  
DEVICE  
NO.  
PARAMETER  
UNIT  
MIN  
TYP  
MAX  
1
2
3
4
tC(CLKOUT2)  
tw(CLKOUT2H)  
tw(CLKOUT2L)  
tt(CLKOUT2)  
Cycle time, CLKOUT2  
20  
ns  
ns  
ns  
ns  
Pulse duration, CLKOUT2 high  
Pulse duration, CLKOUT2 low  
Transition time, CLKOUT2  
.45P  
.45P  
.55P  
.55P  
3
td(MXI1H-  
CLKOUT2H)  
td(MXI1L-  
5
6
Delay time, MXI1/CLKIN1 high to CLKOUT2 high  
Delay time, MXI1/CLKIN1 low to CLKOUT2 low  
1
1
8
8
ns  
ns  
CLKOUT2L)  
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.  
(2) P = 1/CLKOUT2 clock frequency in nanoseconds (ns). For example, when CLKOUT2 frequency is 8 MHz use P = 125 ns.  
MXI1/CLKIN  
5
6
2
4
1
CLKOUT2  
3
4
Figure 6-8. CLKOUT2 Timing  
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6.6.3 PRTCSS Oscillator  
The device has an PRTCSS oscillator input/output pair (RTCXI/RTCXO) usable with external crystals or  
ceramic resonators to provide clock inputs. The optimal frequency for the crystal is 32.768 kHz. The  
electrical requirements and characteristics are described in this section. Figure 6-9 shows an example  
circuit.  
RTCXO  
VSS_32k  
RTCXI  
Crystal  
32.768 kHz  
C1  
C2  
Figure 6-9. RTCXI1 Oscillator  
The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are  
C1 = C2 = 2 fF). CL in the equation below is the load specified by the crystal manufacturer. All discrete  
components used to implement the oscillator circuit should be placed as close as possible to the  
associated oscillator pins (RTCXI and RTCXO) and to the VSS_32K pin.  
C1C2  
CL  
(C1 C2)  
(1)  
6.6.4 PRTCSS Electrical Data/Timing  
Table 6-7. Timing Requirements for RTCXI(1) (2) (see Figure 6-6)  
DEVICE  
TYP  
30.5175  
UNIT  
NO.  
MIN  
MAX  
1
2
3
tc(RTCXI)  
Cycle time, RTCXI  
µs  
tw(RTCXIH)  
tw(RTCXIL)  
Pulse duration, RTCXI high  
Pulse duration, RTCXI low  
.45C  
.45C  
.55C ns  
.55C ns  
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.  
(2) C = MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns.  
1
2
RTCXI  
3
Figure 6-10. RTCXI Timing  
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Table 6-8. Switching Characteristics Over Recommended Operating Conditions for RTC Oscillator  
PARAMETER  
Start-up time (from power up until oscillating at stable frequency)  
Oscillation frequency  
MIN  
TYP  
0.85  
32.768  
MAX  
UNIT  
s
2
kHz  
kΩ  
Crystal ESR  
70  
Frequency stability  
+/- 50  
ppm  
The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are  
C1 = C2 = 2 fF). CL in the equation is the load specified by the crystal manufacturer. All discrete  
components used to implement the oscillator circuit should be placed as close as possible to the  
associated oscillator pins (RTCXI and RTCXO) and to the VSS_MX1 pin.  
6.7 Power Management and Real Time Clock Subsystem (PRTCSS)  
The Power Management and Real Time Clock Subsystem (PRTCSS) is used for calendar applications.  
The PRTCSS has an independent power supply and can remain ON while the rest of the power supply is  
turned OFF. The PRTCSS supports the following features:  
•
Real Time Clock (RTC)  
–
–
–
–
Simple day counter (Up to 89-years)  
To generate the Alarm event to check the RTC count  
16-bit simple timer  
Watch-dog timer to generate the event for RTC-Sequencer  
•
General Purpose I/O with Anti-chattering  
–
–
3-output pins (PWRCTRO[2:0])  
7-In/Output pins (PWRCTRIO[6:0])  
6.7.1 PRTCSS Peripheral Register Description(s)  
The following table lists the PRTCSS Interface registers (PRTCIF) and Table 6-10 lists the PRTCSS  
registers which can only be accessed via the PRTCIF registers, their corresponding acronyms, and device  
memory locations (offsets). For more details, see the TMS320DM36x PRTCSS User's Guide (literature  
number SPRUFJ0).  
Table 6-9. PRTC Interface (PRTCIF) Registers  
Offset  
0x0  
Acronym  
Register Description  
PID  
PRTCIF peripheral ID register  
PRTCIF control register  
0x4  
PRTCIF_CTRL  
PRTCIF_LDATA  
PRTCIF_UDATA  
PRTCIF_INTEN  
PRTCIF_INTFLG  
0x8  
PRTCIF access lower data register  
PRTCIF access upper data register  
PRTCIF interrupt enable register  
PRTCIF interrupt flag register  
0xC  
0x10  
0x14  
Table 6-10. Power Management and Real Time Clock Subsystem (PRTCSS) Registers  
Offset  
0x0  
0x1  
0x2  
0x3  
0x4  
0x5  
0x6  
Acronym  
Register Description  
GO_OUT  
Global output pin output data register  
Global input/output pin output data register  
Global input/output pin direction register  
Global input/output pin input data register  
Global input/output pin function register  
GIO rise interrupt enable register  
GIO fall interrupt enable register  
GIO_OUT  
GIO_DIR  
GIO_IN  
GIO_FUNC  
GIO_RISE_INT_EN  
GIO_FALL_INT_EN  
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Table 6-10. Power Management and Real Time Clock Subsystem (PRTCSS) Registers (continued)  
Offset  
0x7  
Acronym  
Register Description  
GIO rise interrupt flag register  
GIO fall interrupt flag register  
Reserved  
GIO_RISE_INT_FLG  
GIO_FALL_INT_FLG  
Reserved  
0x8  
0x9 - 0xA  
0xB  
INTC_EXTENA0  
INTC_EXTENA1  
INTC_FLG0  
INTC_FLG1  
RTC_CTRL  
EXT interrupt enable 0 register  
EXT interrupt enable 1 register  
Event interrupt flag 0 register  
Event interrupt flag 1 register  
RTC control register  
0xC  
0xD  
0xE  
0x10  
0x11  
0x12  
0x13  
0x14  
0x15  
0x16  
0x17  
0x18  
0x19  
0x1A  
0x1B  
0x1C  
0x1D  
0x20  
RTC_WDT  
Watchdog timer counter register  
Timer counter 0 register  
Timer counter 1 register  
Calender control register  
Seconds register  
RTC_TMR0  
RTC_TMR1  
RTC_CCTRL  
RTC_SEC  
RTC_MIN  
Minutes register  
RTC_HOUR  
RTC_DAY0  
Hours register  
Days[[7:0] register  
RTC_DAY1  
Days[14:8] register  
RTC_AMIN  
Minutes Alarm register  
Hour Alarm register  
RTC_AHOUR  
RTC_ADAY0  
RTC_ADAY1  
CLKC_CNT  
Days[7:0] Alarm register  
Days[14:8] Alarm register  
Clock control register  
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6.8 General-Purpose Input/Output (GPIO)  
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.  
When configured as an output, a write to an internal register can control the state driven on the output pin.  
When configured as an input, the state of the input is detectable by reading the state of an internal  
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different  
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.  
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]). There  
are a total of 7 GPIO banks in the device, because the device has 104 GPIOs. For additional details on  
GPIO pins voltage level and the associated power supply please see Table 6-11.  
Table 6-11. GPIO Pin Voltage Level and Power Supply Reference  
Voltage Level  
1.8 V or 3.3 V  
VDD_AEMIF2_18_33  
GIO[67]  
3.3 V  
1.8 V  
Power Supply Name  
VDD_AEMIF1_18_33  
GIO[78:68]  
VDD_ISIF18_33  
VDDS33  
VDD18_PRTCSS  
GIO[110:104]  
GIO[103:93]  
GIO[92:79]  
GIO[49:0]  
Pin Name  
GIO[66:56]  
GIO[55:52]  
GIO[51:50]  
The GPIO peripheral supports the following:  
•
•
Up to 104 GPIO pins, GPIO[103:0]  
Up to 7 GPIO pins dedicated to the PRTC Subsystem, GPIO[110:104]. These pins are labeled as  
PWRCTRIO[6:0]. For the PRTCSS module the PWRCTRIO[6:0] pins support input and output  
functionality but for the GPIO module the GPIO[110:104] pins support input functionality only. For more  
details please refer to Section 6.7.  
•
Interrupts:  
–
–
Up to 15 unique GPIO[15:0] interrupts from Bank 0.  
Up to 3 unique GPIO[106:104] interrupts from Bank 6, dedicated to the PRTC Subsystem. For  
more details please refer to Section 6.7.  
–
Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO  
signal  
•
•
DMA events:  
–
Up to 15 unique GPIO DMA events from Bank 0  
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO  
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section  
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to  
anther process during GPIO programming).  
•
•
Separate Input/Output registers  
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can  
be toggled by direct write to the output register(s).  
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting  
pin status, allows wired logic be implemented.  
For more detailed information on GPIOs, see the Documentation Support section for the General-Purpose  
Input/Output (GPIO) Reference Guide.  
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6.8.1 GPIO Peripheral Register Description(s)  
Table 6-12 lists the GPIO registers, their corresponding acronyms, and device memory locations (offsets).  
Table 6-12. General-Purpose Input/Output (GPIO) Registers  
OFFSET  
0h  
ACRONYM  
PID  
REGISTER DESCRIPTION  
Peripheral Identification Register  
8h  
BINTEN  
GPIO Interrupt Per-Bank Enable Register  
GPIO Banks 0 and 1  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
2Ch  
30h  
34h  
DIR01  
GPIO Banks 0 and 1 Direction Register  
GPIO Banks 0 and 1 Output Data Register  
GPIO Banks 0 and 1 Set Data Register  
GPIO Banks 0 and 1 Clear Data Register  
GPIO Banks 0 and 1 Input Data Register  
GPIO Set Rising Edge Interrupt Register  
GPIO Clear Rising Edge Interrupt Register  
GPIO Set Falling Edge Interrupt Register  
GPIO Clear Falling Edge Interrupt Register  
GPIO Interrupt Status Register  
OUT_DATA01  
SET_DATA01  
CLR_DATA01  
IN_DATA01  
SET_RIS_TRIG  
CLR_RIS_TRIG  
SET_FAL_TRIG  
CLR_FAL_TRIG  
INTSTAT  
GPIO Banks 2 and 3  
38h  
3Ch  
40h  
44h  
48h  
DIR23  
GPIO Banks 2 and 3 Direction Register  
GPIO Banks 2 and 3 Output Data Register  
GPIO Banks 2 and 3 Set Data Register  
GPIO Banks 2 and 3 Clear Data Register  
GPIO Banks 2 and 3 Input Data Register  
GPIO Bank 4 and 5  
OUT_DATA23  
SET_DATA23  
CLR_DATA23  
IN_DATA23  
60h  
64h  
68h  
6Ch  
70h  
DIR45  
GPIO Bank 4 and 5 Direction Register  
GPIO Bank 4 and 5 Output Data Register  
GPIO Bank 4 and 5 Set Data Register  
GPIO Bank 4 and 5 Clear Data Register  
GPIO Bank 4 and 5 Input Data Register  
GPIO Bank 6  
OUT_DATA45  
SET_DATA45  
CLR_DATA45  
IN_DATA45  
88h  
8Ch  
90h  
94h  
98h  
DIR6  
GPIO Bank 6 Direction Register  
OUT_DATA6  
SET_DATA6  
CLR_DATA6  
IN_DATA6  
GPIO Bank 6 Output Data Register  
GPIO Bank 6 Set Data Register  
GPIO Bank 6 Clear Data Register  
GPIO Bank 6 Input Data Register  
6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing  
Table 6-13. Timing Requirements for GPIO Inputs (see Figure 6-11)  
DEVICE  
NO.  
UNIT  
MIN  
12P(1)  
12P(1)  
MAX  
1
2
tw(GPIH)  
tw(GPIL)  
Pulse duration, GPIx high  
Pulse duration, GPIx low  
ns  
ns  
(1) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3 , Device Clocking.  
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Table 6-14. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs  
(see Figure 6-11)  
DEVICE  
NO.  
PARAMETER  
Pulse duration, GPOx high  
Pulse duration, GPOx low  
UNIT  
MIN  
MAX  
36P(1)  
-
3
4
tw(GPOH)  
tw(GPOL)  
ns  
ns  
8
36P(1)  
-
8
(1) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3 , Device Clocking.  
2
1
GPIx  
4
3
GPOx  
Figure 6-11. GPIO Port Timing  
6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing  
Table 6-15. Timing Requirements for External Interrupts/EDMA Events(1) (see Figure 6-12)  
DEVICE  
NO.  
UNIT  
MIN  
2P(2)  
2P(2)  
MAX  
1
2
tw(ILOW)  
tw(IHIGH)  
Width of the external interrupt pulse low  
Width of the external interrupt pulse high  
ns  
ns  
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants the device to recognize the  
GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to  
access the GPIO register through the internal bus.  
(2) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3 , Device Clocking.  
2
1
EXT_INTx  
Figure 6-12. GPIO External Interrupt Timing  
6.9 EDMA Controller  
The EDMA controller handles all data transfers between memories and the device slave peripherals on  
the device. These are summarized as follows:  
•
Transfer to/from on-chip memories  
–
–
–
ARM program/data RAM  
HDVICP Coprocessor memory  
MPEG/JPEG Coprocessor memory  
•
Transfer to/from external storage  
–
–
–
–
–
DDR2 / mDDR SDRAM  
Asynchronous EMIF  
OneNAND flash  
NAND flash, NOR flash  
Smart Media, SD, MMC, xD media storage  
•
Transfer to/from peripherals  
–
–
–
McBSP  
SPI  
I2C  
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–
–
–
–
–
–
PWM  
RTO  
GPIO  
Timer/WDT  
UART  
MMC/SD  
The EDMA Controller consists of two major blocks: the Transfer Controller (TC) and the Channel  
Controller (CC). The CC is a highly flexible Channel Controller that serves as the user interface and event  
interface for the EDMA system. The CC supports 64-event channels and 8 QDMA channels. The CC  
consists of a scalable Parameter RAM (PaRAM) that supports flexible ping-pong, circular buffering,  
channel-chaining, auto-reloading, and memory protection.  
The EDMA Channel Controller has the following features:  
•
Fully orthogonal transfer description  
–
–
–
–
–
Three transfer dimensions  
A-synchronized transfers: one dimension serviced per event  
AB- synchronized transfers: two dimensions serviced per event  
Independent indexes on source and destination  
Chaining feature allows 3-D transfer based on single event  
•
Flexible transfer definition  
–
–
–
Increment and constant addressing modes  
Linking mechanism allows automatic PaRAM set update  
Chaining allows multiple transfers to execute with one event  
•
•
•
Interrupt generation for:  
–
–
DMA completion  
Error conditions  
Debug visibility  
–
–
Queue watermarking/threshold  
Error and status recording to facilitate debug  
64 DMA channels  
–
–
–
Event synchronization  
Manual synchronization (CPU(s) write to event set register)  
Chain synchronization (completion of one transfer chains to next)  
•
•
8 QDMA channels  
–
–
QDMA channels are triggered automatically upon writing to a PaRAM set entry  
Support for programmable QDMA channel to PaRAM mapping  
256 PaRAM sets  
Each PaRAM set can be used for a DMA channel, QDMA channel, or link set (remaining)  
–
•
•
•
Four transfer controllers/event queues. The system-level priority of these queues is user programmable  
16 event entries per event queue  
External events (for example, McBSP TX Evt and RX Evt)  
The EDMA Transfer Controller has the following features:  
•
•
•
•
•
Four transfer controllers  
64-bit wide read and write ports per channel  
Up to four in-flight transfer requests (TR)  
Programmable priority level  
Supports two dimensional transfers with independent indexes on source and destination (EDMA  
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Channel Controller manages the 3rd dimension)  
•
•
Support for increment and constant addressing modes  
Interrupt and error support  
Parameter RAM: Each EDMA is specified by an eight word (32-byte) parameter table contained in  
Parameter RAM (PaRAM) within the CC. The device provides 256 PaRAM entries, one for each of the 64  
DMA channels and for 8 QDMA / Linked DMA entries.  
DMA Channels: Can be triggered by: " External events (for example, McBSP TX Evt and RX Evt), "  
Software writing a '1' to the given bit location, or channel, of the Event Set register, or, " Chaining to other  
DMAs.  
QDMA: The Quick DMA (QDMA) function is contained within the CC. The device implements 8 QDMA  
channels. Each QDMA channel has a selectable PaRAM entry used to specify the transfer. A QDMA  
transfer is submitted immediately upon writing of the "trigger" parameter (as opposed to the occurrence of  
an event as with EDMA). The QDMA parameter RAM may be written by any Config bus master through  
the Config Bus and by DMAs through the Config Bus bridge.  
QDMA Channels: Triggered by a configuration bus write to a designated 'QDMA trigger word'. QDMAs  
allow a minimum number of linear writes (optimized for GEM IDMA feature) to be issued to the CC to  
force a series of transfers to take place.  
6.9.1 EDMA Channel Synchronization Events  
The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.  
Table 6-16 lists the source of EDMA synchronization events associated with each of the programmable  
EDMA channels. For the device, the association of an event to a channel is fixed; each of the EDMA  
channels has one specific event associated with it. These specific events are captured in the EDMA event  
registers (ER, ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH).  
For more detailed information on the EDMA module and how EDMA events are enabled, captured,  
processed, linked, chained, and cleared, etc., see the Document Support section for the Enhanced Direct  
Memory Access (EDMA) Controller Reference Guide.  
Table 6-16. EDMA Channel Synchronization Events(1) (2)  
EDMA  
CHANNEL  
EVENT NAME  
EVENT DESCRIPTION  
0
1
TIMER3: TEVT6  
TIMER3 TEVT7  
Timer 3 Interrupt (TEVT6) Event  
Timer 3 Interrupt (TEVT7) Event  
McBSP: XEVT or  
VoiceCodec : VCREVT  
2
3
McBSP Transmit Event or Voice Codec Transmit Event  
McBSP Receive Event or Voice Codec Receive Event  
McBSP :REVT or  
VoiceCodec : VCREVT  
4
5
VPSS: EVT1  
VPSS: EVT2  
VPSS Event 1  
VPSS Event 2  
6
VPSS: EVT3  
VPSS Event 3  
7
VPSS: EVT4  
VPSS Event 4  
8
TIMER2: TEVT4  
TIMER2: TEVT5  
SPI2: SPI2XEVT  
SPI2: SPI2REVT  
Timer 2 interrupt (TEVT4) Event  
Timer 2 interrupt (TEVT5) Event  
SPI2 Transmit Event  
SPI2 Receive Event  
9
10  
11  
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or  
intermediate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the Document Support  
section for the Enhanced Direct Memory Access (EDMA) Controller Reference Guide.  
(2) The total number of EDMA events exceeds 64, which is the maximum value of the EDMA module. Therefore, several events are  
multiplexed and you must use the register EDMA_EVTMUX in the System Control Module to select the event source for multiplexed  
events. Refer to the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5) for more information on  
the System Control Module register EDMA_EVTMUX.  
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(1) (2)  
Table 6-16. EDMA Channel Synchronization Events  
(continued)  
EDMA  
CHANNEL  
EVENT NAME  
EVENT DESCRIPTION  
MJCP : IMX0INT or  
HDVICP :  
HDVICP_ARMINT  
MPEG/JPEG Coprocessor IMX0INT Event or High Definition Video Image Coprocessor  
HDVICP_ARMINT Event  
12  
13  
14  
15  
16  
17  
MJCP : SEQINT  
SPI1: SPI1XEVT  
SPI1: SPI1REVT  
SPI0: SPI0XEVT  
SPI0: SPI0REVT  
MPEG/JPEG Coprocessor SEQINT Event  
SPI1 Transmit Event  
SPI1 Receive Event  
SP0I Transmit Event  
SPI0 Receive Event  
UART0: URXEVT0 or SPI3:  
SPI3XEVT  
18  
19  
UART 0 Receive Event  
UART 0 Transmit Event  
UART0: UTXEVT0 or SPI3:  
SPI3REVT  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
UART1: URXEVT1  
UART1: UTXEVT1  
TIMER4 : TEVT8  
TIMER4 : TEVT9  
RTOEVT  
UART 1 Receive Event  
UART 1 Transmit Event  
Timer 4 (TEVT8) Event  
Timer 4 (TEVT9) Event  
Real Time Out Module Event  
GPIO 9 Event  
GPIO: GPINT9  
MMC0RXEVT  
MMC0TXEVT  
I2C : ICREVT  
I2C : ICXEVT  
MMC/SD0 Receive Event  
MMC/SD0 Transmit Event  
I2C Receive Event  
I2C Transmit Event  
MMC/SD1 Receive Event  
MMC/SD1 Transmit Event  
GPIO 0 Event  
MMC1RXEVT  
MMC1TXEVT  
GPIO :GPINT0  
GPIO: GPINT1  
GPIO :GPINT2  
GPIO :GPINT3  
GPIO :GPINT4  
GPIO :GPINT5  
GPIO :GPINT6  
GPIO :GPINT7  
GPIO 1 Event  
GPIO 2 Event  
GPIO 3 Event  
GPIO 4 Event  
GPIO 5 Event  
GPIO 6 Event  
GPIO 7 Event  
GPIO : GPINT10 or  
EMACRXTHREESH  
40  
41  
42  
43  
GPIO 10 Event or EMAC EMACRXTHREESH  
GPIO 11 Event or EMAC EMACRXPULSE  
GPIO 12 Event or EMAC EMACTXPULSE  
GPIO 13 Event or EMAC EMACMISCPULSE  
GPIO : GPINT11 or  
EMACRXPULSE  
GPIO : GPINT12 or  
EMACTXPULSE  
GPIO : GPINT13 or  
EMACMISCPULSE  
44  
45  
46  
47  
48  
49  
50  
51  
52  
GPIO : GPINT14  
GPIO : GPINT15  
ADC : ADINT  
GPIO 14 Event  
GPIO 15 Event  
Analog to Digital Converter Interrupt Event  
GPIO 8 Event  
GPIO : GPINT8  
TIMER0 : TEVT0  
TIMER0: TEVT1  
TIMER1: TEVT2  
TIMER1: TEVT3  
PWM0  
Timer 0 (TEVT0) Event  
Timer 1 (TEVT1) Event  
Timer 2(TEVT2) Event  
Timer 3(TEVT3) Event  
PWM 0 Event  
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(1) (2)  
Table 6-16. EDMA Channel Synchronization Events  
(continued)  
EDMA  
CHANNEL  
EVENT NAME  
EVENT DESCRIPTION  
53  
54  
PWM1 or MJCP : IMX1INT  
PWM2 or MJCP : NSFINT  
PWM 1 Event or MJCP IMX1INT interrupt  
PWM 2 Event or MJCP NSFINT interrupt  
PWM3 or HDVICP(6) :  
CP_UNDEF  
MPEG/JPEG Coprocessor PWM 3 Event or High Definition Video Image Coprocessor  
CP_UNDEF Event  
55  
56  
57  
58  
59  
60  
61  
62  
63  
MJCP : VLCDINT or  
HDVICP(5) : CP_ECDCMP  
MPEG/JPEG Coprocessor VLCDINT Event or High Definition Video Image Coprocessor  
CP_ECDCMP Event  
MJCP : BIMINT or  
HDVICP(8) : CP_ME  
MPEG/JPEG Coprocessor BIMINT Event or High Definition Video Image Coprocessor  
CP_ME Event  
MJCP : DCTINT or  
HDVICP(1) : CP_CALC  
MPEG/JPEG Coprocessor DCTINT Event or High Definition Video Image Coprocessor  
CP_CALC Event  
MJCP : QIQINT or  
HDVICP(7) : CP_IPE  
MPEG/JPEG Coprocessor QIQINT Event or High Definition Video Image Coprocessor  
CP_IPE Event  
MJCP : BPSINT or  
HDVICP(2) : CP_BS  
MPEG/JPEG Coprocessor BPSINT Event or High Definition Video Image Coprocessor  
CP_BS Event  
MJCP : VLCDERRINT or MPEG/JPEG Coprocessor VLCDERRINT Event or High Definition Video Image Coprocessor  
HDVICP(0) : CP_LPF  
CP_LPF Event  
MJCP : RCNTINT or  
HDVICP(3) : CP_MC  
MPEG/JPEG Coprocessor RCNTINT Event or High Definition Video Image Coprocessor  
CP_MC Event  
MJCP : COPCINT or  
HDVICP(4) : CP_ECDEND  
MPEG/JPEG Coprocessor COPCINT Event or High Definition Video Image Coprocessor  
CP_ECDEND Event  
6.9.2 EDMA Peripheral Register Description(s)  
Table 6-17 lists the EDMA registers, their corresponding acronyms, and device memory locations  
(offsets).  
Table 6-17. EDMA Registers  
Offset  
00h  
Acronym  
PID  
Register Description  
Peripheral Identification Register  
EDMA3CC Configuration Register  
Global Registers  
04h  
CCCFG  
0200h  
0204h  
0208h  
020Ch  
0210h  
0214h  
0218h  
021Ch  
0240h  
0244h  
0248h  
024Ch  
0250h  
0254h  
0258h  
025Ch  
0260h  
0284h  
0300h  
QCHMAP0  
QCHMAP1  
QCHMAP2  
QCHMAP3  
QCHMAP4  
QCHMAP5  
QCHMAP6  
QCHMAP7  
DMAQNUM0  
DMAQNUM1  
DMAQNUM2  
DMAQNUM3  
DMAQNUM4  
DMAQNUM5  
DMAQNUM6  
DMAQNUM7  
QDMAQNUM  
QUEPRI  
QDMA Channel 0 Mapping Register  
QDMA Channel 1 Mapping Register  
QDMA Channel 2 Mapping Register  
QDMA Channel 3 Mapping Register  
QDMA Channel 4 Mapping Register  
QDMA Channel 5 Mapping Register  
QDMA Channel 6 Mapping Register  
QDMA Channel 7 Mapping Register  
DMA Queue Number Register 0  
DMA Queue Number Register 1  
DMA Queue Number Register 2  
DMA Queue Number Register 3  
DMA Queue Number Register 4  
DMA Queue Number Register 5  
DMA Queue Number Register 6  
DMA Queue Number Register 7  
QDMA Queue Number Register  
Queue Priority Register  
EMR  
Event Missed Register  
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Table 6-17. EDMA Registers (continued)  
Offset  
Acronym  
EMRH  
Register Description  
0304h  
0308h  
030Ch  
0310h  
0314h  
0318h  
031Ch  
0320h  
0340h  
0344h  
...  
Event Missed Register High  
Event Missed Clear Register  
Event Missed Clear Register High  
QDMA Event Missed Register  
QDMA Event Missed Clear Register  
EDMA3CC Error Register  
EMCR  
EMCRH  
QEMR  
QEMCR  
CCERR  
CCERRCLR  
EEVAL  
EDMA3CC Error Clear Register  
Error Evaluate Register  
DRAE0  
DRAEH0  
DMA Region Access Enable Register for Region 0  
DMA Region Access Enable Register High for Region 0  
0350h  
0354h  
0360h  
0364h  
0368h  
036Ch  
0380h  
0388h  
0390h  
0394h  
0400h-047Ch  
0600h  
0604h  
0608h  
060Ch  
0620h  
0640h  
DRAE2  
DMA Region Access Enable Register for Region 2  
DMA Region Access Enable Register High for Region 2  
DMA Region Access Enable Register for Region 4  
DMA Region Access Enable Register High for Region 4  
DMA Region Access Enable Register for Region 5  
DMA Region Access Enable Register High for Region 5  
QDMA Region Access Enable Register for Region 0  
QDMA Region Access Enable Register for Region 2  
DRAEH2  
DRAE4  
DRAEH4  
DRAE5  
DRAEH5  
QRAE0  
QRAE2  
QRAE4  
QRAE5  
Q0E0-Q1E15  
QSTAT0  
QSTAT1  
QSTAT2  
QSTAT3  
QWMTHRA  
CCSTAT  
Event Queue Entry Registers Q0E0-Q1E15  
Queue 0 Status Register  
Queue 1 Status Register  
Queue 2 Status Register  
Queue 3 Status Register  
Queue Watermark Threshold A Register  
EDMA3CC Status Register  
Global Channel Registers  
Event Register  
1000h  
1004h  
1008h  
100Ch  
1010h  
1014h  
1018h  
101Ch  
1020h  
1024h  
1028h  
102Ch  
1030h  
1034h  
1038h  
103Ch  
1040h  
1044h  
ER  
ERH  
Event Register High  
ECR  
Event Clear Register  
ECRH  
ESR  
Event Clear Register High  
Event Set Register  
ESRH  
CER  
Event Set Register High  
Chained Event Register  
CERH  
EER  
Chained Event Register High  
Event Enable Register  
EERH  
EECR  
EECRH  
EESR  
EESRH  
SER  
Event Enable Register High  
Event Enable Clear Register  
Event Enable Clear Register High  
Event Enable Set Register  
Event Enable Set Register High  
Secondary Event Register  
Secondary Event Register High  
Secondary Event Clear Register  
Secondary Event Clear Register High  
SERH  
SECR  
SECRH  
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Table 6-17. EDMA Registers (continued)  
Offset  
1050h  
1054h  
1058h  
105Ch  
1060h  
1064h  
1068h  
106Ch  
1070h  
1074h  
1078h  
1080h  
1084h  
1088h  
108Ch  
1090h  
1094h  
Acronym  
IER  
Register Description  
Interrupt Enable Register  
IERH  
Interrupt Enable Register High  
Interrupt Enable Clear Register  
Interrupt Enable Clear Register High  
Interrupt Enable Set Register  
Interrupt Enable Set Register High  
Interrupt Pending Register  
Interrupt Pending Register High  
Interrupt Clear Register  
IECR  
IECRH  
IESR  
IESRH  
IPR  
IPRH  
ICR  
ICRH  
Interrupt Clear Register High  
Interrupt Evaluate Register  
QDMA Event Register  
IEVAL  
QER  
QEER  
QEECR  
QEESR  
QSER  
QSECR  
QDMA Event Enable Register  
QDMA Event Enable Clear Register  
QDMA Event Enable Set Register  
QDMA Secondary Event Register  
QDMA Secondary Event Clear Register  
Shadow Region 0 Channel Registers  
Event Register  
2000h  
2004h  
2008h  
200Ch  
2010h  
2014h  
2018h  
201Ch  
2020h  
2024h  
2028h  
202Ch  
2030h  
2034h  
2038h  
203Ch  
2040h  
2044h  
2050h  
2054h  
2058h  
205Ch  
2060h  
2064h  
2068h  
206Ch  
2070h  
2074h  
2078h  
ER  
ERH  
Event Register High  
ECR  
Event Clear Register  
ECRH  
ESR  
Event Clear Register High  
Event Set Register  
ESRH  
CER  
Event Set Register High  
Chained Event Register  
CERH  
EER  
Chained Event Register High  
Event Enable Register  
EERH  
EECR  
EECRH  
EESR  
EESRH  
SER  
Event Enable Register High  
Event Enable Clear Register  
Event Enable Clear Register High  
Event Enable Set Register  
Event Enable Set Register High  
Secondary Event Register  
Secondary Event Register High  
Secondary Event Clear Register  
Secondary Event Clear Register High  
Interrupt Enable Register  
SERH  
SECR  
SECRH  
IER  
IERH  
IECR  
IECRH  
IESR  
IESRH  
IPR  
Interrupt Enable Register High  
Interrupt Enable Clear Register  
Interrupt Enable Clear Register High  
Interrupt Enable Set Register  
Interrupt Enable Set Register High  
Interrupt Pending Register  
Interrupt Pending Register High  
Interrupt Clear Register  
IPRH  
ICR  
ICRH  
IEVAL  
Interrupt Clear Register High  
Interrupt Evaluate Register  
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Table 6-17. EDMA Registers (continued)  
Offset  
Acronym  
QER  
Register Description  
2080h  
2084h  
2088h  
208Ch  
2090h  
2094h  
QDMA Event Register  
QEER  
QDMA Event Enable Register  
QDMA Event Enable Clear Register  
QDMA Event Enable Set Register  
QDMA Secondary Event Register  
QDMA Secondary Event Clear Register  
Shadow Region 1 Channel Registers  
Event Register  
QEECR  
QEESR  
QSER  
QSECR  
2200h  
2204h  
ER  
ERH  
Event Register High  
2208h  
ECR  
Event Clear Register  
220Ch  
ECRH  
ESR  
Event Clear Register High  
2210h  
Event Set Register  
2214h  
ESRH  
CER  
Event Set Register High  
2218h  
Chained Event Register  
221Ch  
CERH  
EER  
Chained Event Register High  
Event Enable Register  
2220h  
2224h  
EERH  
EECR  
EECRH  
EESR  
EESRH  
SER  
Event Enable Register High  
Event Enable Clear Register  
Event Enable Clear Register High  
Event Enable Set Register  
2228h  
222Ch  
2230h  
2234h  
Event Enable Set Register High  
Secondary Event Register  
2238h  
223Ch  
SERH  
SECR  
SECRH  
IER  
Secondary Event Register High  
Secondary Event Clear Register  
Secondary Event Clear Register High  
Interrupt Enable Register  
2240h  
2244h  
2250h  
2254h  
IERH  
IECR  
IECRH  
IESR  
IESRH  
IPR  
Interrupt Enable Register High  
Interrupt Enable Clear Register  
Interrupt Enable Clear Register High  
Interrupt Enable Set Register  
Interrupt Enable Set Register High  
Interrupt Pending Register  
2258h  
225Ch  
2260h  
2264h  
2268h  
226Ch  
IPRH  
ICR  
Interrupt Pending Register High  
Interrupt Clear Register  
2270h  
2274h  
ICRH  
IEVAL  
QER  
Interrupt Clear Register High  
Interrupt Evaluate Register  
2278h  
2280h  
QDMA Event Register  
2284h  
QEER  
QEECR  
QEESR  
QSER  
QSECR  
—
QDMA Event Enable Register  
QDMA Event Enable Clear Register  
QDMA Event Enable Set Register  
QDMA Secondary Event Register  
QDMA Secondary Event Clear Register  
Shadow Region 2 Channel Registers  
Shadow Region 3 Channel Registers  
Shadow Region 4 Channel Registers  
Shadow Region 5 Channel Registers  
Shadow Region 6 Channel Registers  
2288h  
228Ch  
2290h  
2294h  
2400h-2494h  
2600h-2694h  
2800h-2894h  
2A00h-2A94h  
2C00h-2C94h  
—
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Table 6-17. EDMA Registers (continued)  
Offset  
Acronym  
Register Description  
2E00h-2E94h  
4000h-4FFFh  
Shadow Region 7 Channel Registers  
Parameter RAM (PaRAM)  
—
Table 6-18 shows an abbreviation of the set of registers which make up the parameter set for each of 512  
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-19 shows the  
parameter set entry registers with relative memory address locations within each of the parameter sets.  
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Table 6-18. EDMA Parameter Set RAM  
HEX ADDRESS RANGE  
DESCRIPTION  
0x01C0 4000 - 0x01C0 401F  
0x01C0 4020 - 0x01C0 403F  
0x01C0 4040 - 0x01C0 405F  
0x01C0 4060 - 0x01C0 407F  
0x01C0 4080 - 0x01C0 409F  
0x01C0 40A0 - 0x01C0 40BF  
...  
Parameters Set 0 (8 32-bit words)  
Parameters Set 1 (8 32-bit words)  
Parameters Set 2 (8 32-bit words)  
Parameters Set 3 (8 32-bit words)  
Parameters Set 4 (8 32-bit words)  
Parameters Set 5 (8 32-bit words)  
...  
0x01C0 7FC0 - 0x01C0 7FDF  
0x01C0 7FE0 - 0x01C0 7FFF  
Parameters Set 510 (8 32-bit words)  
Parameters Set 511 (8 32-bit words)  
Table 6-19. Parameter Set Entries  
HEX OFFSET ADDRESS  
WITHIN THE PARAMETER SET  
ACRONYM  
PARAMETER ENTRY  
0x0000  
0x0004  
0x0008  
0x000C  
0x0010  
0x0014  
0x0018  
0x001C  
OPT  
SRC  
Option  
Source Address  
A_B_CNT  
DST  
A Count, B Count  
Destination Address  
SRC_DST_BIDX  
LINK_BCNTRLD  
SRC_DST_CIDX  
CCNT  
Source B Index, Destination B Index  
Link Address, B Count Reload  
Source C Index, Destination C Index  
C Count  
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6.10 External Memory Interface (EMIF)  
The device supports several memory and external device interfaces, including:  
•
Asynchronous EMIF (AEMIF) for interfacing to SRAM.  
–
–
–
OneNAND flash memories  
NAND flash memories  
NOR flash memories  
•
DDR2/mDDR Memory Controller for interfacing to SDRAM.  
6.10.1 Asynchronous EMIF (AEMIF)  
The EMIF supports the following features:  
•
•
•
•
•
SRAM, NOR flash, etc. on up to 2 asynchronous chip selects addressable up to 16MB each  
Supports 8-bit or 16-bit data bus widths  
Programmable asynchronous cycle timings  
Supports extended wait mode  
Supports Select Strobe mode  
6.10.1.1 NAND (NAND, SmartMedia, xD)  
The NAND features of the EMIF are as follows:  
•
•
•
•
•
NAND flash on up to 2 asynchronous chip selects  
8 and 16-bit data bus widths  
Programmable cycle timings  
Performs 1-bit and 4-bit ECC calculation  
NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory  
cards  
6.10.1.2 OneNAND  
The OneNAND features supported are as follows.  
•
•
•
•
NAND flash on up to 2 asynchronous chip selects  
Only 16-bit data bus widths  
Supports asynchronous writes and reads  
Supports synchronous reads with continuous linear burst mode (Does not support synchronous reads  
with wrap burst modes)  
•
Programmable cycle timings for each chip select in asynchronous mode  
6.10.1.3 EMIF Peripheral Register Descriptions  
Table 6-20 lists the EDMA registers, their corresponding acronyms, and device memory locations  
(offsets).  
Table 6-20. External Memory Interface (EMIF) Registers  
OFFSET  
ACRONYM  
REGISTER DESCRIPTION  
04h  
AWCCR  
Asynchronous Wait Cycle Configuration  
Register  
10h  
14h  
A1CR  
A2CR  
Asynchronous 1 Configuration Register (CE0  
space)  
Asynchronous 2 Configuration Register (CE1  
space)  
40h  
44h  
EIRR  
EIMR  
EMIF Interrupt Raw Register  
EMIF Interrupt Mask Register  
100  
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Table 6-20. External Memory Interface (EMIF) Registers (continued)  
OFFSET  
48h  
ACRONYM  
EIMSR  
REGISTER DESCRIPTION  
EMIF Interrupt Mask Set Register  
EMIF Interrupt Mask Clear Register  
OneNAND Flash Control Register  
NAND Flash Control Register  
NAND Flash Status Register  
4Ch  
EIMCR  
5Ch  
ONENANDCTL  
NANDFCR  
NANDFSR  
NANDF1ECC  
60h  
64h  
70h  
NAND Flash 1-Bit ECC Register 1 (CE0  
Space)  
74h  
NANDF2ECC  
NAND Flash 1-Bit ECC Register 2 (CE1  
Space)  
BCh  
C0h  
C4h  
C8h  
CCh  
D0h  
NAND4BITECCLOAD  
NAND4BITECC1  
NAND4BITECC2  
NAND4BITECC3  
NAND3BITECC4  
NANDERRADD1  
NANDFlash 4-Bit ECC Load Register  
NAND Flash 4-Bit ECC Register 1  
NAND Flash 4-Bit ECC Register 2  
NAND Flash 4-Bit ECC Register 3  
NAND Flash 4-Bit ECC Register 4  
NAND Flash 4-Bit ECC Error Address  
Register 1  
D4h  
D8h  
DCh  
NANDERRADD2  
NANDERRVAL1  
NANDERRVAL2  
NAND Flash 4-Bit ECC Error Address  
Register 2  
NAND Flash 4-Bit ECC Error Value Register  
1
NAND Flash 4-Bit ECC Error Value Register  
2
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6.10.1.4 AEMIF Electrical Data/Timing  
Table 6-21. Timing Requirements for Asynchronous Memory Cycles for AEMIF Module(1) (see Figure 6-13  
and Figure 6-14)  
DEVICE  
NOM  
NO  
.
UNIT  
MIN  
MAX  
READS and WRITES  
Pulse duration, EM_WAIT assertion and  
deassertion  
2
tw(EM_WAIT)  
2E  
ns  
READS  
12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high  
4
3
ns  
ns  
13 th(EMOEH-EMDIV)  
Hold time, EM_D[15:0] valid after EM_OE high  
tsu  
14  
Setup time EM_WAIT asserted before EM_OE  
high(2)  
4E + 3  
ns  
(EMOEL-EMWAIT)  
READS (OneNAND Synchronous Burst Read)  
Setup time, EM_D[15:0] valid before EM_CLK  
high  
30 tsu(EMDV-EMCLKH)  
4
3
ns  
ns  
31 th(EMCLKH-EMDIV) Hold time, EM_D[15:0] valid after EM_CLK high  
WRITES  
Setup time EM_WAIT asserted before EM_WE  
high(2)  
tsu  
28  
4E + 3  
ns  
(EMWEL-EMWAIT)  
(1) E = (0.5) * PLL1C SYSCLK4 period in ns. See Section 3.3 for more information.  
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended  
wait states. Figure 6-15 and Figure 6-16 describe EMIF transactions that include extended wait states inserted during the STROBE  
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where  
the HOLD phase would begin if there were no extended wait cycles.  
Table 6-22. Switching Characteristics Over Recommended Operating Conditions for Asynchronous  
Memory Cycles for AEMIF Module(1) (2) (3) (see Figure 6-13 and Figure 6-14)  
DEVICE  
UNI  
T
NO.  
PARAMETER  
MIN  
READS and WRITES  
TYP  
MAX  
1
td(TURNAROUND)  
Turn around time  
(TA)*E  
ns  
READS  
EMIF read cycle time (EW = 0)  
EMIF read cycle time (EW = 1)  
(RS+RST+RH + 3)*E  
(RS+RST+RH+3)*E  
ns  
ns  
3
tc(EMRCYCLE)  
Output setup time, EM_CE[1:0] low to  
EM_OE low (SS = 0)  
(RS + 1)*E + 3  
(RS + 1)*E  
(RH + 1)*E  
(RH + 1)*E  
(RS + 1)*E  
(RH + 1)*E  
ns  
ns  
ns  
ns  
ns  
ns  
4
5
tsu(EMCEL-EMOEL)  
Output setup time, EM_CE[1:0] low to  
EM_OE low (SS = 1)  
Output hold time, EM_OE high to  
EM_CE[1:0] high (SS = 0)  
th(EMOEH-EMCEH)  
Output hold time, EM_OE high to  
EM_CE[1:0] high (SS = 1)  
Output setup time, EM_BA[1:0] valid to  
EM_OE low  
6
7
tsu(EMBAV-EMOEL)  
th(EMOEH-EMBAIV)  
Output hold time, EM_OE high to  
EM_BA[1:0] invalid  
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,  
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle  
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],  
WH[8-1], and MEW[1-256]. See the TMS320DM36x DMSoC Asynchronous External Memory Interface User's Guide (SPRUFI1) for  
more information.  
(2) E = (0.5) * PLLC1 SYSCLK4 period in ns. See Section 3.3 for more information.  
(3) EWC = external wait cycles determined by EM_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that  
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the  
TMS320DM36x DMSoC Asynchronous External Memory Interface User's Guide (SPRUFI1) for more information.  
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Table 6-22. Switching Characteristics Over Recommended Operating Conditions for Asynchronous  
Memory Cycles for AEMIF Module (1) (2) (3) (see Figure 6-13 and Figure 6-14 ) (continued)  
DEVICE  
UNI  
T
NO.  
PARAMETER  
MIN  
TYP  
MAX  
Output setup time, EM_A[21:0] valid to  
EM_OE low  
8
9
tsu(EMBAV-EMOEL)  
th(EMOEH-EMAIV)  
(RS + 1)*E  
(RH + 1)*E  
ns  
ns  
Output hold time, EM_OE high to  
EM_A[21:0] invalid  
EM_OE active low width (EW = 0)  
EM_OE active low width (EW = 1)  
(RST)*E  
ns  
ns  
10 tw(EMOEL)  
(RST+(EWC*16))*E  
td(EMWAITH-  
EMOEH)  
Delay time from EM_WAIT deasserted to  
EM_OE high  
11  
4E  
ns  
READS (OneNAND Synchronous Burst Read)  
MH  
z
32 fc(EM_CLK)  
Frequency, EM_CLK  
Cycle time, EM_CLK  
66  
33 tc(EM_CLK)  
tsu(EM_ADVV-  
15.15  
ns  
Output setup time, EM_ADV valid before  
EM_CLK high  
34  
35  
36  
37  
2E - 2.5  
2E + 3  
2E - 2.5  
2E + 3  
ns  
EM_CLKH)  
th(EM_CLKH-  
EM_ADVIV)  
Output hold time, EM_CLK high to EM_ADV  
invalid  
ns  
ns  
ns  
tsu(EM_AV-  
EM_CLKH)  
Output setup time, EM_A[21:0]/EM_BA[1]  
valid before EM_CLK high  
th(EM_CLKH-  
EM_AIV)  
Output hold time, EM_CLK high to  
EM_A[21:0]/EM_BA[1] invalid  
38 tw(EM_CLKH)  
Pulse duration, EM_CLK high  
Pulse duration, EM_CLK low  
5.05  
5.05  
ns  
ns  
39 tw(EM_CLKL)  
WRITES  
(WS + WST +  
WH + TA + 4) * E  
- 3  
(WS + WST +  
WH + TA + 4) * E ns  
+ 3  
EMIF write cycle time (EW = 0)  
EMIF write cycle time (EW = 1)  
15 tc(EMWCYCLE)  
(WS + WST +  
WH + TA + 4) * E  
- 3  
(WS + WST +  
WH + TA + 4) * E ns  
+ 3  
Output setup time, EM_CE[1:0] low to  
EM_WE low (SS = 0)  
(WS+1) * E - 3  
(WS+1) * E - 3  
(WH+1) * E - 3  
(WH+1) * E - 3  
(WS+1) * E - 3  
(WH+1) * E - 3  
(WS+1) * E - 3  
(WH+1) * E - 3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
16 tsu(EMCEL-EMWEL)  
Output setup time, EM_CE[1:0] low to  
EM_WE low (SS = 1)  
Output hold time, EM_WE high to  
EM_CE[1:0] high (SS = 0)  
17 th(EMWEH-EMCEH)  
Output hold time, EM_WE high to  
EM_CE[1:0] high (SS = 1)  
Output setup time, EM_BA[1:0] valid to  
EM_WE low  
20 tsu(EMBAV-EMWEL)  
21 th(EMWEH-EMBAIV)  
22 tsu(EMAV-EMWEL)  
23 th(EMWEH-EMAIV)  
Output hold time, EM_WE high to  
EM_BA[1:0] invalid  
Output setup time, EM_A[21:0] valid to  
EM_WE low  
Output hold time, EM_WE high to  
EM_A[21:0] invalid  
EM_WE active low width (EW = 0)  
EM_WE active low width (EW = 1)  
(WST+1) * E - 3  
(WST+1) * E - 3  
ns  
ns  
24 tw(EMWEL)  
td(EMWAITH-  
EMWEH)  
Delay time from EM_WAIT deasserted to  
EM_WE high  
25  
4E + 3 ns  
ns  
Output setup time, EM_D[15:0] valid to  
EM_WE low  
26 tsu(EMDV-EMWEL)  
(WS+1) * E - 3  
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Table 6-22. Switching Characteristics Over Recommended Operating Conditions for Asynchronous  
Memory Cycles for AEMIF Module (1) (2) (3) (see Figure 6-13 and Figure 6-14 ) (continued)  
DEVICE  
UNI  
T
NO.  
PARAMETER  
MIN  
TYP  
MAX  
Output hold time, EM_WE high to  
EM_D[15:0] invalid  
27 th(EMWEH-EMDIV)  
(WH+1) * E - 3  
ns  
3
1
EM_CE[1:0]  
EM_BA[1:0]  
EM_A[21:0]  
4
8
5
9
7
6
10  
EM_OE  
13  
12  
EM_D[15:0]  
EM_WE  
Figure 6-13. Asynchronous Memory Read Timing for EMIF  
15  
1
EM_CE[1:0]  
EM_BA[1:0]  
EM_A[21:0]  
16  
18  
20  
22  
17  
19  
21  
23  
24  
EM_WE  
27  
26  
EM_D[15:0]  
EM_OE  
Figure 6-14. Asynchronous Memory Write Timing for EMIF  
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STROBE HOLD  
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SETUP  
STROBE  
Extended Due to EM_WAIT  
EM_CE[1:0]  
EM_BA[1:0]  
EM_A[21:0]  
EM_D[15:0]  
11  
EM_OE  
14  
2
2
EM_WAIT  
Asserted  
Deasserted  
Figure 6-15. EM_WAIT Read Timing Requirements  
SETUP  
STROBE  
Extended Due to EM_WAIT  
STROBE HOLD  
EM_CE[1:0]  
EM_BA[1:0]  
EM_A[21:0]  
EM_D[15:0]  
28  
25  
EM_WE  
2
2
Asserted  
Deasserted  
EM_WAIT  
Figure 6-16. EM_WAIT Write Timing Requirements  
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33  
38  
EM_CE[1:0]  
EM_CLK  
39  
34  
EM_ADV  
35  
36  
31  
EM_BA0,  
EM_A[21:0],  
EM_BA1  
30  
Da  
37  
Da+n+1  
Da+n  
EM_D[15:0]  
Da+1  
Da+2  
Da+3  
Da+4  
Da+5  
EM_OE  
EM_WAIT  
Figure 6-17. Synchronous OneNAND Flash Read Timing  
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6.10.2 DDR2/mDDR Memory Controller  
The DDR2 / mDDR Memory Controller is a dedicated interface to DDR2 / mDDR SDRAM. It supports  
JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.  
DDR2 / mDDR SDRAM plays a key role in a device-based system. Such a system is expected to require  
a significant amount of high-speed external memory for all of the following functions:  
•
•
•
•
Buffering of input image data from sensors or video sources  
Intermediate buffering for processing/resizing of image data in the VPFE  
Numerous OSD display buffers  
Intermediate buffering for large raw Bayer data image files while performing image processing  
functions  
•
•
Buffering for intermediate data while performing video encode and decode functions  
Storage of executable code for the ARM  
The DDR2 / mDDR Memory Controller supports the following features:  
•
•
•
•
•
JESD79D-2A standard compliant DDR2 SDRAM  
Mobile DDR SDRAM  
256 MByte memory space  
Data bus width 16 bits  
CAS latencies:  
–
–
DDR2: 2, 3, 4, and 5  
mDDR: 2 and 3  
•
Internal banks:  
–
–
DDR2: 1, 2, 4, and 8  
mDDR: 1, 2, and 4  
•
•
Burst length: 8  
Burst type: sequential  
•
•
•
•
•
•
•
•
•
•
1 CS signal  
Page sizes: 256, 512, 1024, and 2048  
SDRAM autoinitialization  
Self-refresh mode  
Partial array self-refresh (for mDDR)  
Power down mode  
Prioritized refresh  
Programmable refresh rate and backlog counter  
Programmable timing parameters  
Little endian  
For details on the DDR2 Memory Controller, see the TMS320DM36x DMSoC DDR2/mDDR Memory  
Controller User's Guide (literature number SPRUFI2).  
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6.10.3 DDR2 Memory Controller Electrical Data/Timing  
Table 6-23. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory  
Controller(1) (2)(see )  
NO.  
PARAMETER  
MIN MAX UNIT  
1
tf(DDR_CLK)  
Frequency, DDR_CLK  
173-DDR2 (supported for 216-MHz device)  
216-DDR2 (supported for 270-MHz device)  
270-DDR2 (supported for 300-MHz device)  
mDDR (supported for all devices)  
125 173  
125 216  
MHz  
125 270  
90 168  
(1) DDR_CLK frequency = 2 x PLLC1.SYSCLK7 or 2 x PLLC2.SYSCLK3 frequency.  
(2) The PLL2 Controller must be programmed such that the resulting DDR_CLK clock frequency is within the specified range.  
1
DDR_CLK  
Figure 6-18. DDR2 Memory Controller Clock Timing  
6.10.3.1 DDR2/mDDR Interface  
This section provides the timing specification for the DDR2/mDDR interface as a PCB design and  
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal  
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR  
memory system without the need for a complex timing closure process. For more information regarding  
guidelines for using this DDR2 specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing  
Specification (SPRAAV0).  
6.10.3.1.1 DDR2/mDDR Interface Schematic  
Figure 6-19 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The  
dual-memory system shown in Figure 6-20. Pin numbers for the device can be obtained from the pin  
description section.  
6.10.3.1.2 Compatible JEDEC DDR2/mDDR Devices  
Table 6-24 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this  
interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2/mDDR devices.  
The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one  
chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control  
signals are shared just like regular dual chip memory configurations.  
Table 6-24. Compatible JEDEC DDR2/mDDR Devices  
No.  
Parameter  
Min  
Max  
Unit  
Notes  
(1)  
(1)  
(1)  
(1)  
1
JEDEC DDR2/mDDR Device Speed Grade  
DDR2-400  
(for 173MHz DDR2)  
See Notes  
,
,
,
,
(2)  
mDDR-400  
(for 168MHz mDDR)  
See Notes  
(3)  
DDR2-533  
(for 216MHz DDR2)  
See Notes  
(2)  
DDR2-667  
(for 270MHz DDR2)  
See Notes  
(2)  
2
JEDEC DDR2/mDDR Device Bit Width  
x8  
x16  
Bits  
(1) Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility.  
(2) Used for DDR2.  
(3) Used for mobile DDR.  
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Table 6-24. Compatible JEDEC DDR2/mDDR Devices (continued)  
No.  
Parameter  
JEDEC DDR2/mDDR Device Count  
Min  
Max  
Unit  
Notes  
(4)  
3
1
2
Devices  
See Note  
(4) Supported configurations are one 16-bit DDR2/mDDR memory or two 8-bit DDR2/mDDR memories.  
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6.10.3.1.3 PCB Stack Up  
The minimum stack up required for routing the device is a six layer stack as shown in Table 6-25.  
Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size  
of the PCB footprint.  
Table 6-25. Minimum PCB Stack Up  
Layer  
Type  
Signal  
Plane  
Plane  
Signal  
Plane  
Signal  
Description  
Top Routing Mostly Horizontal  
Ground  
1
2
3
4
5
6
Power  
Internal Routing  
Ground  
Bottom Routing Mostly Vertical  
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Complete stack up specifications are provided below.  
DMSoC  
DDR2/mDDR  
ODT  
DQ0  
DDR_DQ00  
T
T
DDR_DQ07  
DQ7  
DDR_DQM0  
DDR_DQS0  
DDR_DQSN0  
DDR_DQ08  
T
T
LDM  
LDQS  
T
T
LDQS  
DQ8  
DDR_DQ15  
T
DQ15  
DDR_DQM1  
DDR_DQS1  
T
T
UDM  
UDQS  
T
T
DDR_DQSN1  
DDR_BA0  
UDQS  
BA0  
DDR_BA2  
DDR_A00  
T
T
BA2  
A0  
DDR_A13  
DDR_CS  
T
T
T
T
T
T
T
T
A13(C)  
CS  
DDR_CAS  
DDR_RAS  
DDR_WE  
DDR_CKE  
DDR_CLK  
DDR_CLK  
CAS  
RAS  
WE  
CKE  
CK  
CK  
DDR_PADREF  
DDR_DQGATE0  
DDR_DQGATE1  
T
Vio 1.8(A)  
DDR_VREF(D)  
VREF(D)  
0.1 μF(B)  
0.1 μF(B)  
0.1 μF(B)  
0.1 μF  
1 K Ω 1%  
VREF(D)  
T
Terminator, if desired. See terminator comments.  
1 K Ω 1%  
0.1 μF  
A. Vio 1.8 is the power supply for the DDR2/mDDR memories and the DM36x DDR2/mDDR interface.  
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. In the  
Case of mobile DDR, these capacitors can be eliminated completely.  
C. When present, A13 signals should be connected.  
D. VREF applies in the case of DDR2 memories. For mDDR the DMSoC DDR_VREF pin still needs to be connected to  
the divider circuit.  
Figure 6-19. DDR2/mDDR Single-Memory High Level Schematic  
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DMSoC  
ODT  
DDR_DQ00-07  
T
DQ0 - DQ7  
BA0-BA2  
A0-A13(C)  
DDR_DQM0  
DDR_DQS0  
DDR_DQSN0  
T
T
DM  
DQS  
DQS  
T
CK  
CK  
CS  
CAS  
RAS  
WE  
CKE  
VREF(D)  
DDR_BA0-BA2  
DDR_A00-A13  
T
T
BA0-BA2  
A0-A13(C)  
DDR_CLK  
DDR_CLK  
DDR_CS  
T
T
T
T
T
T
T
CK  
CK  
CS  
DDR_CAS  
DDR_RAS  
DDR_WE  
DDR_CKE  
CAS  
RAS  
WE  
CKE  
DDR_DQM1  
DDR_DQS1  
DDR_DQSN1  
T
T
T
DM  
DQS  
DQS  
DDR_DQ08-15  
Vio 1.8(A)  
T
DQ0 - DQ7  
DDR_PADREF  
ODT  
DDR_DQGATE0  
DDR_DQGATE1  
T
VREF(D)  
0.1 μF  
0.1 μF  
1 K Ω 1%  
DDR_VREF(D)  
VREF(D)  
0.1 μF(B)  
0.1 μF(B)  
0.1 μF(B)  
1 K Ω 1%  
T
Terminator, if desired. See terminator comments.  
A. Vio 1.8 is the power supply for the DDR2/mDDR memories and the DM36x DDR2/mDDR interface.  
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. In the  
Case of mobile DDR, these capacitors can be eliminated completely.  
C. When present, A13 signals should be connected.  
D. VREF applies in the case of DDR2 memories. For mDDR the DMSoC DDR_VREF pin still needs to be connected to  
the divider circuit.  
Figure 6-20. DDR2/mDDR Dual-Memory High Level Schematic  
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Table 6-26. PCB Stack Up Specifications  
No. Parameter  
Min  
6
Typ  
Max Unit  
Notes  
1
2
3
4
5
PCB Routing/Plane Layers  
Signal Routing Layers  
3
Full ground layers under DDR2/mDDR routing Region  
2
1
Number of ground plane cuts allowed within DDR routing region  
0
0
Number of ground reference planes required for each DDR2/mDDR  
routing layer  
6
Number of layers between DDR2/mDDR routing layer and reference  
ground plane  
7
8
PCB Routing Feature Size  
PCB Trace Width w  
4
4
Mils  
Mils  
Mils  
Mils  
8
PCB BGA escape via pad size  
PCB BGA escape via hole size  
DMSoC Device BGA pad size  
DDR2/mDDR Device BGA pad size  
Single Ended Impedance, Zo  
Impedance Control  
18  
8
9
(1)  
(2)  
10  
11  
12  
13  
See Note  
See Note  
50  
75  
Ω
Ω
(3)  
Z-5  
Z
Z+5  
See Note  
(1) Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for DMSoC device BGA pad size.  
(2) Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size.  
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.  
6.10.3.1.4 Placement  
Figure 6-21 shows the required placement for the device as well as the DDR2/mDDR devices. The  
dimensions for Figure 6-21 are defined in Table 6-27. The placement does not restrict the side of the PCB  
that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace  
lengths and allow for proper routing space. For single-memory DDR2/mDDR systems, the second  
DDR2/mDDR device is omitted from the placement.  
X
A1  
Y
OFFSET  
DDR2/mDDR  
Y
Device  
Y
DMSoC  
OFFSET  
A1  
Recommended DDR2/mDDR  
Device Orientation  
Figure 6-21. DM365 and DDR2/mDDR Device Placement  
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Table 6-27. Placement Specifications  
No. Parameter  
Min  
Max  
1750  
1280  
650  
Unit  
Mils  
Mils  
Mils  
Notes  
(1) (2)  
1
2
3
X
See Notes  
,
(1) (2)  
Y
See Notes  
,
(1) (2)  
Y Offset  
See Notes  
.
,
(3)  
(4)  
(5)  
4
5
DDR2/mDDR Keepout Region  
See Note  
See Note  
Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout Region  
4
w
(1) See Figure 6-19 for dimension definitions.  
(2) Measurements from center of DMSoC device to center of DDR2/mDDR device.  
(3) For single memory systems it is recommended that Y Offset be as small as possible.  
(4) DDR2/mDDR Keepout region to encompass entire DDR2/mDDR routing area  
(5) Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing layers by  
a ground plane.  
6.10.3.1.5 DDR2/mDDR Keep Out Region  
The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The  
DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 6-22. The size of this  
region varies with the placement and DDR routing. Additional clearances required for the keep out region  
are shown in Table 6-27.  
A1  
DDR2/mDDR  
Device  
A1  
Region should encompass all DDR2/mDDR circuitry and varies  
depending on placement. Non-DDR2/mDDR signals should not be  
routed on the DDR signal layers within the DDR2/mDDR keep out  
region. Non-DDR2/mDDR signals may be routed in the region  
provided they are routed on layers separated from DDR2/mDDR  
signal layers by a ground layer. No breaks should be allowed in the  
reference ground layers in this region. In addition, the 1.8 V power  
plane should cover the entire keep out region.  
Figure 6-22. DDR2/mDDR Keepout Region  
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6.10.3.1.6 Bulk Bypass Capacitors  
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other  
circuitry. Table 6-28 contains the minimum numbers and capacitance required for the bulk bypass  
capacitors. Note that this table only covers the bypass needs of the DMSoC and DDR2/mDDR interfaces.  
Additional bulk bypass capacitance may be needed for other circuitry.  
Table 6-28. Bulk Bypass Capacitors  
No. Parameter  
Min  
Max  
Unit  
Notes  
1
VDD18_DDR Bulk Bypass Capacitor Count  
3
Devices See Note  
(1)  
2
3
VDD18_DDR Bulk Bypass Total Capacitance  
DDR#1 Bulk Bypass Capacitor Count  
30  
1
uF  
Devices See Note  
(1)  
4
5
DDR#1 Bulk Bypass Total Capacitance  
DDR#2 Bulk Bypass Capacitor Count  
22  
1
uF  
Devices See Notes  
(1) (2)  
,
6
DDR#2 Bulk Bypass Total Capacitance  
22  
uF  
See Note  
(2)  
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed  
(HS) bypass caps.  
(2) Only used on dual-memory systems  
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6.10.3.1.7 High-Speed Bypass Capacitors  
High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is  
particularly important to minimize the parasitic series inductance of the HS bypass cap,  
DMSoC/DDR2/mDDR power, and DMSoC/DDR2/mDDR ground connections. Table 6-29 contains the  
specification for the HS bypass capacitors as well as for the power connections on the PCB.  
6.10.3.1.8 Net Classes  
Table 6-30 lists the clock net classes for the DDR2/mDDR interface. Table 6-31 lists the signal net  
classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes  
are used for the termination and routing rules that follow.  
Table 6-29. High-Speed Bypass Capacitors  
No. Parameter  
Min  
Max  
0402  
250  
Unit  
10 Mils  
Mils  
Notes  
(1)  
(2)  
1
2
3
4
5
6
7
8
9
HS Bypass Capacitor Package Size  
See Note  
Distance from HS bypass capacitor to device being bypassed  
Number of connection vias for each HS bypass capacitor  
Trace length from bypass capacitor contact to connection via  
Number of connection vias for each DDR2/mDDR device power or ground balls  
Trace length from DDR2/mDDR device power ball to connection via  
VDD18_DDR HS Bypass Capacitor Count  
2
1
1
Vias  
See Note  
30  
35  
Mils  
Vias  
Mils  
(3)  
(3)  
10  
1.2  
8
Devices  
uF  
See Note  
See Note  
VDD18_DDR HS Bypass Capacitor Total Capacitance  
DDR#1 HS Bypass Capacitor Count  
Devices  
uF  
10 DDR#1 HS Bypass Capacitor Total Capacitance  
11 DDR#2 HS Bypass Capacitor Count  
0.4  
8
Devices  
See Notes  
(3) (4)  
,
(4)  
12 DDR#2 HS Bypass Capacitor Total Capacitance  
0.4  
uF  
See Note  
(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor  
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.  
(3) These devices should be placed as close as possible to the device being bypassed.  
(4) Only used on dual-memory systems  
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Table 6-30. Clock Net Class Definitions  
Clock Net Class  
DMSoC Pin Names  
CK  
DDR_CLK/DDR_CLK  
DQS0  
DQS1  
DDR_DQS0/DDR_DQSN0  
DDR_DQS1/DDR_DQSN1  
Table 6-31. Signal Net Class Definitions  
Associated Clock Net  
Clock Net Class  
Class  
DMSoC Pin Names  
ADDR_CTRL  
CK  
DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE,  
DDR_CKE  
DQ0  
DQ1  
DQS0  
DDR_DQ[7:0], DDR_DQM0  
DQS1  
DDR_DQ[15:8], DDR_DQM1  
DDR_DQGATE0, DDR_DQGATE1  
DQGATE  
CK, DQS0, DQS1  
6.10.3.1.9 DDR2/mDDR Signal Termination  
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.  
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only  
type permitted. Table 6-32 shows the specifications for the series terminators.  
Table 6-32. DDR2/mDDR Signal Terminations  
No. Parameter  
Min  
0
Typ  
Max  
10  
Unit  
Ω
Notes  
See Note  
See Notes  
(1)  
(1)  
1
2
CK Net Class  
ADDR_CTRL Net Class  
0
22  
22  
10  
Zo  
Ω
,
,
,
(2) (3)  
,
(1)  
3
4
Data Byte Net Classes (DQS0-DQS1, DQ0-DQ1)  
DQGATE Net Class (DQGATE)  
0
0
Zo  
Zo  
Ω
Ω
See Notes  
(2) (3) (4)  
,
,
(1)  
See Notes  
(2) (3)  
,
(1) Only series termination is permitted, parallel or SST specifically disallowed.  
(2) Terminator values larger than typical only recommended to address EMI issues.  
(3) Termination value should be uniform across net class.  
(4) When no termination is used on data lines (0 Ωs), the DDR2/mDDR devices must be programmed to operate in 60% strength mode.  
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6.10.3.1.10 VREF Routing  
VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the device.  
VREF is intended to be the DDR2/mDDR power supply voltage and should be created using a resistive  
divider as shown in Figure 6-19. Other methods of creating VREF are not recommended. Figure 6-23  
shows the layout guidelines for VREF.  
VREF Bypass Capacitor  
DDR2/mDDR Device  
A1  
VREF Nominal Minimum  
DMSoC  
Device  
Trace Width is 20 Mils  
A1  
Neck down to minimum in BGA escape  
regions is acceptable. Narrowing to  
accomodate via congestion for short  
distances is also acceptable. Best  
performance is obtained if the width  
of VREF is maximized.  
Figure 6-23. VREF Routing and Topology  
6.10.3.1.11 DDR2/mDDR CK and ADDR_CTRL Routing  
Figure 6-24 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a  
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A  
should be maximized.  
A1  
T
A
DMSoC  
A1  
Figure 6-24. CK and ADDR_CTRL Routing and Topology  
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(1)  
Table 6-33. CK and ADDR_CTRL Routing Specification  
No  
1
Parameter  
Min  
Typ  
Max  
2w  
25  
Unit  
Notes  
Center to center DQS-DQSN spacing  
(1)  
2
CK A to B/A to C Skew Length Mismatch  
CK B to C Skew Length Mismatch  
Mils  
Mils  
See Note  
3
25  
(2)  
(3)  
4
Center to center CK to other DDR2/mDDR trace spacing  
CK/ADDR_CTRL nominal trace length  
4w  
See Note  
See Note  
5
CACLM-50  
CACLM  
CACLM+50  
100  
Mils  
Mils  
Mils  
6
ADDR_CTRL to CK Skew Length Mismatch  
ADDR_CTRL to ADDR_CTRL Skew Length Mismatch  
7
100  
(2)  
(2)  
(1)  
8
Center to center ADDR_CTRL to other DDR2/mDDR  
trace spacing  
4w  
3w  
See Note  
See Note  
See Note  
9
Center to center ADDR_CTRL to other ADDR_CTRL  
trace spacing  
10  
11  
ADDR_CTRL A to B/A to C Skew Length Mismatch  
ADDR_CTRL B to C Skew Length Mismatch  
100  
100  
Mils  
Mils  
(1) Series terminator, if used, should be located closest to DMSoC.  
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.  
Figure 6-25 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.  
Skew matching across bytes is not needed nor recommended.  
T
E0  
A1  
T
E1  
DMSoC  
T
E2  
A1  
T
E3  
Figure 6-25. DQS and DQ Routing and Topology  
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Table 6-34. DQS and DQ Routing Specification  
No. Parameter  
Min  
Typ  
Max  
2w  
Unit  
Notes  
1
2
3
4
5
6
7
8
9
Center to center DQS-DQSN spacing  
DQS E Skew Length Mismatch  
25  
Mils  
(1)  
Center to center DQS to other DDR2/mDDR trace spacing  
DQS/DQ nominal trace length  
4w  
See Note  
(2) (3)  
DQLM-50  
DQLM  
DQLM+50 Mils  
See Notes  
,
(3)  
DQ to DQS Skew Length Mismatch  
100  
100  
Mils  
Mils  
See Note  
See Note  
(3)  
DQ to DQ Skew Length Mismatch  
(1) (4)  
Center to center DQ to other DDR2/mDDR trace spacing  
Center to Center DQ to other DQ trace spacing  
DQ/DQS E Skew Length Mismatch  
4w  
3w  
See Notes  
,
(5) (1)  
See Notes  
See Note  
,
(3)  
100  
Mils  
(1) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(2) Series terminator, if used, should be located closest to DDR.  
(3) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte  
1.  
(4) DQ's from other DQS domains are considered other DDR2/mDDR trace.  
(5) DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.  
Figure 6-26 shows the routing for the DQGATE net classes. Table 6-35 contains the routing specification.  
A1  
T
T
DMSoC  
A1  
Figure 6-26. DQGATE Routing  
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Table 6-35. DQGATE Routing Specification  
No. Parameter  
Min  
Typ  
Max  
Unit  
Notes  
(1)  
(2)  
1
3
4
5
DQGATE Length F  
CKB0B1  
See Note  
Center to center DQGATE to any other trace spacing  
DQS/DQ nominal trace length  
4w  
DQLM-50  
DQLM  
DQLM+50  
100  
Mils  
DQGATE Skew  
Mils See Note  
(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.  
(2) Skew from CKB0B1  
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6.11 MMC/SD  
The device includes MMC/SD Controllers which are compliant with MMC V3.31, Secure Digital Part 1  
Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.  
The device MMC/SD Controller has following features:  
•
•
•
•
•
•
•
•
MultiMediaCard (MMC)  
Secure Digital (SD) Memory Card  
MMC/SD protocol support  
SDIO protocol support  
Programmable clock frequency  
512 bit Read/Write FIFO to lower system overhead  
Slave EDMA transfer capability  
SD High Capacity support  
The device MMC/SD Controller does not support SPI mode.  
6.11.1 MMC/SD Peripheral Register Description(s)  
Table 6-36 lists the MMC/SD registers, their corresponding acronyms, and device memory locations  
(offsets).  
Table 6-36. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers  
OFFSET  
00h  
04h  
08h  
0Ch  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
2Ch  
30h  
34h  
38h  
3Ch  
40h  
44h  
48h  
50h  
64h  
68h  
6Ch  
70h  
74h  
ACRONYM  
MMCCTL  
REGISTER DESCRIPTION  
MMC Control Register  
MMCCLK  
MMC Memory Clock Control Register  
MMC Status Register 0  
MMCST0  
MMCST1  
MMC Status Register 1  
MMCIM  
MMC Interrupt Mask Register  
MMC Response Time-Out Register  
MMC Data Read Time-Out Register  
MMC Block Length Register  
MMC Number of Blocks Register  
MMC Number of Blocks Counter Register  
MMC Data Receive Register  
MMC Data Transmit Register  
MMC Command Register  
MMCTOR  
MMCTOD  
MMCBLEN  
MMCNBLK  
MMCNBLC  
MMCDRR  
MMCDXR  
MMCCMD  
MMCARGHL  
MMCRSP01  
MMCRSP23  
MMCRSP45  
MMCRSP67  
MMCDRSP  
MMCCIDX  
SDIOCTL  
MMC Argument Register  
MMC Response Register 0 and 1  
MMC Response Register 2 and 3  
MMC Response Register 4 and 5  
MMC Response Register 6 and 7  
MMC Data Response Register  
MMC Command Index Register  
SDIO Control Register  
SDIOST0  
SDIO Status Register 0  
SDIOIEN  
SDIO Interrupt Enable Register  
SDIO Interrupt Status Register  
MMC FIFO Control Register  
SDIOIST  
MMCFIFOCTL  
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6.11.2 MMC/SD Electrical Data/Timing  
Table 6-37. Timing Requirements for MMC/SD Module  
(see Figure 6-28 and Figure 6-30)  
DEVICE  
FAST MODE STANDARD MODE UNIT  
NO.  
MIN  
2.7  
2.5  
2.7  
2.5  
MAX  
MIN  
2.7  
2.5  
2.7  
2.5  
MAX  
1
2
3
4
tsu(CMDV-CLKH) Setup time, SD_CMD valid before SD_CLK high  
ns  
ns  
ns  
ns  
th(CLKH-CMDV)  
tsu(DATV-CLKH)  
th(CLKH-DATV)  
Hold time, SD_CMD valid after SD_CLK high  
Setup time, SD_DATx valid before SD_CLK high  
Hold time, SD_DATx valid after SD_CLK high  
Table 6-38. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module  
(see Figure 6-27 through Figure 6-30)  
DEVICE  
STANDARD  
NO.  
PARAMETER  
FAST MODE  
UNIT  
MODE  
MIN  
0
MAX  
MIN MAX  
7
8
9
f(CLK)  
Operating frequency, SD_CLK  
50  
0
0
25 MHz  
400 KHz  
ns  
f(CLK_ID)  
tW(CLKL)  
Identification mode frequency, SD_CLK  
Pulse width, SD_CLK low  
Pulse width, SD_CLK high  
Rise time, SD_CLK  
0
400  
6.5  
6.5  
6.5  
6.5  
10 tW(CLKH)  
11 tr(CLK)  
12 tf(CLK)  
ns  
3
3
3
3
ns  
ns  
Fall time, SD_CLK  
13 td(CLKL-CMD) Delay time, SD_CLK low to SD_CMD transition  
14 td(CLKL-DAT) Delay time, SD_CLK low to SD_DATx transition  
-4.1  
-4.1  
1.5  
1.5  
-4.1  
-4.1  
1.5 ns  
1.5 ns  
10  
9
7
SD_CLK  
SD_CMD  
13  
13  
13  
Valid  
13  
START  
XMIT  
Valid  
Valid  
END  
Figure 6-27. MMC/SD Host Command Timing  
9
10  
7
SD_CLK  
SD_CMD  
1
2
Valid  
START  
XMIT  
Valid  
Valid  
END  
Figure 6-28. MMC/SD Card Response Timing  
10  
9
7
SD_CLK  
14  
14  
14  
Dx  
14  
START  
D0  
D1  
END  
SD_DATx  
Figure 6-29. MMC/SD Host Write Timing  
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9
10  
7
SD_CLK  
4
4
3
Start  
3
SD_DATx  
D0  
D1  
Dx  
End  
Figure 6-30. MMC/SD Host Read and Card CRC Status Timing  
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6.12 Video Processing Subsystem (VPSS) Overview  
The device contains a Video Processing Subsystem (VPSS) that provides an input interface (Video  
Processing Front End or VPFE) for external imaging peripherals such as image sensors, video decoders,  
etc.; and an output interface (Video Processing Back End or VPBE) for display devices, such as analog  
SDTV/HDTV displays, digital LCD panels, etc.  
In addition to these peripherals, there is a set of common buffer memory and DMA control to ensure  
efficient use of the DDR2/mDDR burst bandwidth. The shared buffer logic/memory is a unique block that  
is tailored for seamlessly integrating the VPSS into an image/video processing system. It acts as the  
primary source or sink to all the VPFE and VPBE modules that are either requesting or transferring data  
from/to DDR2/mDDR . In order to efficiently utilize the external DDR2/mDDR bandwidth, the shared buffer  
logic/memory interfaces with the DMA system via a high bandwidth bus (64-bit wide). The shared buffer  
logic/memory also interfaces with all the VPFE and VPBE modules via a 128-bit wide bus. The shared  
buffer logic/memory (divided into the read & write buffers and arbitration logic) is capable of performing the  
following functions. It is imperative that the VPSS utilize DDR2/mDDR bandwidth efficiently due to both its  
large bandwidth requirements and the real-time requirements of the VPSS modules. Because it is possible  
to configure the VPSS modules in such a way that DDR2/mDDR bandwidth is exceeded, a set of user  
accessible registers is provided to monitor overflows or failures in data transfers.  
6.12.1 Video Processing Front-End (VPFE)  
The VPFE or Video Processing Front-End block is comprised of the Image Sensor Interface (ISIF), Image  
Pipe (IPIPE), Image Pipe Interface (IPIPEIF), Hardware 3A Statistic Generator (H3A), and a Hardware  
Face Detect Engine. These modules are described in the sections that follow.  
The VPFE sub-module register memory mapping is shown in Table 6-39.  
Table 6-39. Video Processing Front End Sub-Module Register Map  
Address:Offset  
0x01C7:0000  
0x01C7:0200  
0x01C7:0400  
0x01C7:0800  
0x01C7:1000  
0x01C7:1200  
0x01C7:1400  
Acronym  
ISP  
Register Description  
ISP System Configuration  
VPBE Clock Control  
Resizer  
VPBE_CLK_CTRL  
RSZ  
IPIPE  
Image Pipe  
ISIF  
Image Sensor Interface  
Image Pipe Interface  
Hardware 3A  
IPIPEIF  
H3A  
0x01C7:1600 -  
0x01C7:17FF  
Reserved  
Reserved  
0x01C7:1800  
0x01C7:1C00  
FDIF  
Face Detection Register Interface  
VPBE On-Screen Display  
Reserved  
OSD  
0x01C7:1D00 -  
0x01C7:1DFF  
Reserved  
0x01C7:1E00  
VENC  
VPBE Video Encoder  
Reserved  
0x01C7:2000 -  
0x01CF:FFFF  
Reserved  
6.12.1.1 Image Sensor Interface (ISIF)  
The ISIF is responsible for accepting raw (unprocessed) image/video data from a sensor (CMOS or CCD).  
In addition, the ISIF can accept YUV video data in numerous formats, typically from so-called video  
decoder devices. In case of raw inputs, the ISIF output requires additional image processing to transform  
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the raw input image to the final processed image. This processing can be done either on-the-fly in IPIPE  
or in software on the ARM and MPEG/JPEG and HD Video Image coprocessor subsystems. In parallel,  
raw data input to the ISIF can also used for computing various statistics (3A, Histogram) to eventually  
control the image/video tuning parameters. The ISIF is programmed via control and parameter registers.  
The following features are supported by the ISIF module.  
•
•
Support for conventional Bayer pattern, pixel summation mode, and RGB stripe sensor formats.  
Support for the various pixel summation mode formats is provided via a data reformatter of ISIF, which  
transforms any specific sensor formats to the Bayer format. The maximum line width supported by the  
reformatter is 4736 pixels.  
•
•
•
Image processing steps applicable to RGB stripe sensors are limited to color-dependent gain control  
and black level offset control."  
Generates HD/VD timing signals and field ID to an external timing generator, or can synchronize to the  
external timing generator.  
Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware  
support for higher number of fields, typically 3-, 4-, and 5-field sensors.  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Support for up to 32K pixels (image size) in both the horizontal and vertical direction.  
Support for up to 120 MHz sensor clock.  
Support for ITU-R BT.656/1120 standard format.  
Support for YCbCr 422 format, either 8- or 16-bit with discrete HSYNC and VSYNC signals.  
Support for up to 16-bit input.  
Support for color space conversion.  
Digital clamp with Horizontal/Vertical offset drift compensation.  
Vertical Line defect correction based on a lookup table that contains defect position.  
Support for color-dependent gain control and black level offset control.  
Ability to control output to the DDR2/mDDR via an external write enable signal.  
Support for down sampling via programmable culling patterns.  
Support for 12-bit to 8-bit DPCM compression.  
Support for 10-bit to 8-bit A-law compression.  
Support for generating output to range 16-bits, 12-bits, and 8-bits wide (8-bits wide allows for 50%  
saving in storage area).  
•
•
•
OTF DPC  
Noise Filter  
2D edge enhancement  
The ISIF register memory mapping (offsets) is shown in Table 6-40.  
Table 6-40. Image Sensor Interface (ISIF) Registers  
Offset  
0h  
Acronym  
SYNCEN  
MODESET  
HDW  
Register Description  
Synchronization Enable  
Mode Setup  
4h  
8h  
HD pulse width  
Ch  
VDW  
VD pulse width  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
PPLN  
LPFR  
Pixels per line  
Lines per frame  
SPH  
Start pixel horizontal  
Number of pixels in line  
Start line vertical - field 0  
Start line vertical - field 1  
Number of lines vertical  
LNH  
SLV0  
SLV1  
LNV  
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Table 6-40. Image Sensor Interface (ISIF) Registers (continued)  
Offset  
Acronym  
CULH  
Register Description  
2Ch  
30h  
Culling - horizontal  
CULV  
Culling - vertical  
34h  
HSIZE  
Horizontal size  
38h  
SDOFST  
CADU  
SDRAM Line Offset  
3Ch  
40h  
SDRAM Address - high  
CADL  
SDRAM Address - low  
44h - 48h  
4Ch  
50h  
Reserved  
CCOLP  
Reserved  
CCD Color Pattern  
CRGAIN  
CGRGAIN  
CGBGAIN  
CBGAIN  
CCD Gain Adjustment - R/Ye  
CCD Gain Adjustment - Gr/Cy  
CCD Gain Adjustment - Gb/G  
CCD Gain Adjustment - B/Mg  
CCD Offset Adjustment  
54h  
58h  
5Ch  
60h  
COFSTA  
FLSHCFG0  
FLSHCFG1  
FLSHCFG2  
VDINT0  
64h  
FLSHCFG0  
68h  
FLSHCFG1  
6Ch  
70h  
FLSHCFG2  
VD Interrupt #0  
74h  
VDINT1  
VD Interrupt #1  
78h  
VDINT2  
VD Interrupt #2  
7Ch  
80h  
Reserved  
CGAMMAWD  
REC656IF  
CCDCFG  
DFCCTL  
VDFSATLV  
DFCMEMCTL  
DFCMEM0  
DFCMEM1  
DFCMEM2  
DFCMEM3  
DFCMEM4  
CLAMPCFG  
CLDCOFST  
CLSV  
Reserved  
Gamma Correction settings  
CCIR 656 Control  
84h  
88h  
CCD Configuration  
8Ch  
90h  
Defect Correction - Control  
Defect Correction - Vertical Saturation Level  
Defect Correction - Memory Control  
Defect Correction - Set V Position  
Defect Correction - Set H Position  
Defect Correction - Set SUB1  
Defect Correction - Set SUB2  
Defect Correction - Set SUB3  
Black Clamp configuration  
DC offset for Black Clamp  
Black Clamp Start position  
Horizontal Black Clamp configuration  
Horizontal Black Clamp configuration  
Horizontal Black Clamp configuration  
Vertical Black Clamp configuration  
Vertical Black Clamp configuration  
Vertical Black Clamp configuration  
Vertical Black Clamp configuration  
Vertical Black Clamp configuration  
Reserved  
94h  
98h  
9Ch  
A0h  
A4h  
A8h  
ACh  
B0h  
B4h  
B8h  
CLHWIN0  
CLHWIN1  
CLHWIN2  
CLVRV  
BCh  
C0h  
C4h  
C8h  
CCh  
D0h  
D4h  
D8h - 1A2h  
1A4h  
1A8h  
1ACh  
1B0h  
CLVWIN0  
CLVWIN1  
CLVWIN2  
CLVWIN3  
Reserved  
CSCCTL  
CSCM0  
Color Space Converter Enable  
Color Space Converter - Coefficients #0  
Color Space Converter - Coefficients #1  
Color Space Converter - Coefficients #2  
CSCM1  
CSCM2  
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Table 6-40. Image Sensor Interface (ISIF) Registers (continued)  
Offset  
1B4h  
1B8h  
1BCh  
1C0h  
1C4h  
Acronym  
CSCM3  
CSCM4  
CSCM5  
CSCM6  
CSCM7  
Register Description  
Color Space Converter - Coefficients #3  
Color Space Converter - Coefficients #4  
Color Space Converter - Coefficients #5  
Color Space Converter - Coefficients #6  
Color Space Converter - Coefficients #7  
6.12.1.2 The Image Pipe Interface (IPIPEIF)  
The IPIPEIF is data and sync signals interface module for ISIF and IPIPE. Data source of this module is  
sensor parallel port, ISIF or SDRAM and the selected data is output to ISIF and IPIPE. This module also  
outputs black frame subtraction (two-way) data which is generated by subtracting SDRAM data from  
sensor parallel port or ISIF data and vice versa. Depending on the functions performed, it may also  
readjust the HD, VD, and PCLK timing to the IPIPE and/or ISIF input.  
The IPIPEIF module supports the following features:  
•
•
Up to 16-bit sensor data input  
Dark-frame subtract of raw image stored in SDRAM from image coming from sensor parallel port or  
ISIF  
•
•
•
•
•
•
•
8-10, 8-12 DPCM decompression of 10-8, 12-8 compressed data in SDRAM  
Inverse ALAW decompression of RAW data from SDRAM  
(1,2,1) average filtering before horizontal decimation  
Horizontal decimation (downsizing) of input lines to <= 2160 maximum required by the IPIPE  
Gain multiply for output data to IPIPE  
Simple defect correction to prevent a subtraction of defect pixel  
8-bit, 12-bit unpacking of 8-bit, 12-bit packed SDRAM data  
The IPIPE register memory mapping (offsets) is shown in Table 6-41.  
Table 6-41. Image Pipe Input Interface (IPIPEIF) Registers  
Address  
0h  
Acronym  
ENABLE  
CFG1  
Register Description  
IPIPE I/F Enable  
4h  
IPIPE I/F Configuration  
8h  
PPLN  
IPIPE I/F Interval of HD / Start pixel in HD  
IPIPE I/F Interval of VD / Start line in VD  
IPIPE I/F Number of valid pixels per line  
IPIPE I/F Number of valid lines per frame  
IPIPE I/F Memory Address (Upper)  
IPIPE I/F Memory Address (Lower)  
IPIPE I/F Address offset of each line  
IPIPE I/F Horizontal Resizing Parameter  
IPIPE I/F Gain Parameter  
Ch  
LPFR  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
2Ch  
30h  
34h  
38h  
3Ch  
40h  
44h  
48h  
HNUM  
VNUM  
ADDRU  
ADDRL  
ADOFS  
RSZ  
GAIN  
DPCM  
CFG2  
IPIPE I/F DPCM Configuration  
IPIPE I/F Configuration 2  
INIRSZ  
OCLIP  
DTUDF  
CLKDIV  
DPC1  
IPIPE I/F Initial position of resize  
IPIPE I/F Output clipping value  
IPIPE I/F Data underflow error status  
IPIPE I/F Clock rate configuration  
IPIPE I/F Defect pixel correction  
IPIPE I/F Defect pixel correction  
DPC2  
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Table 6-41. Image Pipe Input Interface (IPIPEIF) Registers (continued)  
Address  
Acronym  
RSZ3A  
Register Description  
54h  
58h  
IPIPE I/F Horizontal Resizing Parameter for H3A  
IPIPE I/F Initial position of resize for H3A  
INIRSZ3A  
6.12.1.3 Image Pipe – Hardware Image Signal Processor (IPIPE)  
The Image Pipe (IPIPE) is a programmable hardware image processing module that generates image  
data in YCbCr-4:2:2 or YCbCr-4:2:0 formats from raw CCD/CMOS data. An image resizer is also fully  
integrated within this module. The IPIPE can also be configured to operate in a resize-only mode, which  
allows YCbCr-4:2:2 or YCbCr-4:2:0 to be resized without processing every module in the IPIPE.  
The following features are supported by the IPIPE:  
•
•
12-bit RAW data image processing or 16-bit YCbCr resizing  
RGB Bayer pattern for input color filter array; does not support complementary color pattern, stripe  
pattern, or Foveon™ sensors.  
•
Requires at least eight pixels for horizontal blanking and four lines for vertical blanking. In one shot  
mode, 16 blanking lines after processing area are required.  
•
•
•
•
Maximum horizontal and vertical offset of IPIPE processing area from synchronous signal is 65534  
Maximum input and output widths up to 2176 pixels wide (1088 for RSZ[2]).  
Raw pass-through mode for images wider than 2176 pixels (up to 8190 pixels)  
Automatic mirroring of pixels/lines when edge processing is performed so that the width and height is  
consistent throughout.  
•
Defect pixel correction using  
–
–
Lookup table method that contains row and column position of the pixel to be corrected  
On-the-fly adaptive method  
•
•
•
•
Offset and gain control for white balancing at each color component (WB).  
CFA interpolation for good quality CFA interpolation  
Programmable RGB to RGB blending matrix (9 coefficients for the 3x3 matrix). (RGB2RGB module)  
Separate lookup tables for gamma correction on each of R, G and B components for display through  
piece-wise linear interpolation approach  
•
•
•
4:4:4 data to 4:2:2 data conversion by chroma low-pass filtering and down sampling to Cb and Cr.  
(4:4:4 to 4:2:2 module)  
Programmable look-up table for luminance edge enhancement. Adjustable brightness and contrast for  
Y component (Edge Enhancer module)  
Programmable down or up-sampling filter for both horizontal and vertical directions with range from  
1/16x to 16x, in which the filter outputs two images with different magnification simultaneously (Resizer  
module)  
•
•
4:2:2 to 4:2:0 conversion that can be done in the resizing block  
Different data formats [YCbCr (4:2:2 or 4:2:0), RGB (32bit/16bit), Raw data] are available while storing  
data in the SDRAM from IPIPE  
•
•
•
Flipping image horizontally and/or vertically  
Programmable histogram engine (4 windows, 256 bins)  
Boxcar calculation (1/8 or 1/16 size).  
The IPIPE register memory mapping (offsets) is shown in Table 6-42.  
Table 6-42. IPIPE Registers  
Offset  
Acronym  
Register Description  
0h  
SRC_EN  
IPIPE Enable  
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Table 6-42. IPIPE Registers (continued)  
Offset  
04h  
Acronym  
Register Description  
One Shot Mode  
SRC_MODE  
08h  
SRC_FMT  
Input/Output Data Paths  
Color Pattern  
Ch  
SRC_COL  
10h  
SRC_VPS  
Vertical Start Position  
14h  
SRC_VSZ  
Vertical Processing Size  
Horizontal Start Position  
Horizontal Processing Size  
Status Flags (Reserved)  
MMR Gated Clock Control  
PCLK Gated Clock Control  
Reserved  
18h  
SRC_HPS  
1Ch  
SRC_HSZ  
24h  
DMA_STA  
48h  
GCK_MMR  
2Ch  
GCK_PIX  
30h  
Reserved  
34h  
DPC_LUT_EN  
DPC_LUT_SEL  
DPC_LUT_ADR  
DPC_LUT_SIZ  
WB2_OFT_R  
WB2_OFT_GR  
WB2_OFT_GB  
WB2_OFT_B  
WB2_WGN_R  
WB2_WGN_GR  
WB2_WGN_GB  
WB2_WGN_B  
Reserved  
LUTDPC (=LUT Defect Pixel Correction): Enable  
LUTDPC: Processing Mode Selection  
LUTDPC: Start Address in LUT  
LUTDPC: Number of available entries in LUT  
WB2 (=White Balance): Offset  
WB2: Offset  
38h  
3Ch  
40h  
1D0h  
1D4h  
1D8h  
1DCh  
1E0h  
1E4h  
1E8h  
1ECh  
1F0h-228h  
22Ch  
230h  
234h  
238h  
23Ch  
240h  
244h  
248h  
24Ch  
250h  
254h  
258h  
25Ch  
294h  
298h  
29Ch  
2A0h  
2A4h  
2A8h  
2ACh  
2B0h  
2B4h  
2B8h  
WB2: Offset  
WB2: Offset  
WB2: Gain  
WB2: Gain  
WB2: Gain  
WB2: Gain  
Reserved  
RGB1_MUL_RR  
RGB1_MUL_GR  
RGB1_MUL_BR  
RGB1_MUL_RG  
RGB1_MUL_GG  
RGB1_MUL_BG  
RGB1_MUL_RB  
RGB1_MUL_GB  
RGB1_MUL_BB  
RGB1_OFT_OR  
RGB1_OFT_OG  
RGB1_OFT_OB  
GMM_CFG  
RGB1 (=1st RGB2RGB conv): Matrix Coefficient  
RGB1: Matrix Coefficient  
RGB1: Matrix Coefficient  
RGB1: Matrix Coefficient  
RGB1: Matrix Coefficient  
RGB1: Matrix Coefficient  
RGB1: Matrix Coefficient  
RGB1: Matrix Coefficient  
RGB1: Matrix Coefficient  
RGB1: Offset  
RGB1: Offset  
RGB1: Offset  
Gamma Correction Configuration  
YUV (RGB2YCbCr conv): Luminance Adjustment (contrast & brightness)  
YUV: Matrix Coefficient  
YUV: Matrix Coefficient  
YUV: Matrix Coefficient  
YUV: Matrix Coefficient  
YUV: Matrix Coefficient  
YUV: Matrix Coefficient  
YUV: Matrix Coefficient  
YUV: Matrix Coefficient  
YUV: Matrix Coefficient  
YUV_ADJ  
YUV_MUL_RY  
YUV_MUL_GY  
YUV_MUL_BY  
YUV_MUL_RCB  
YUV_MUL_GCB  
YUV_MUL_BCB  
YUV_MUL_RCR  
YUV_MUL_GCR  
YUV_MUL_BCR  
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Table 6-42. IPIPE Registers (continued)  
Offset  
2BCh  
2C0h  
2C4h  
2C8h  
2D4h  
2D8h  
2DCh  
2E0h  
2E4h  
2E8h  
2ECh  
2F0h  
2F4h  
2F8h  
2FCh  
300h  
304h  
308h  
30Ch  
310h  
314h  
318h  
380h  
384h  
388h  
38Ch  
390h  
394h  
398h  
39Ch  
3A0h  
3A4h  
3A8h  
3ACh  
3B0h  
3B4h  
3B8h  
3BCh  
3C0h  
3C4h  
3C8h  
3CCh  
3D0h  
3D4h  
3D8h  
3DCh  
3E0h  
Acronym  
Register Description  
YUV: Offset  
YUV_OFT_Y  
YUV_OFT_CB  
YUV_OFT_CR  
YUV_PHS  
YUV: Offset  
YUV: Offset  
Chrominance Position (for 422 down sampler)  
YEE (=Edge Enhancer): Enable  
YEE: Method Selection  
YEE: HPF Shift Length  
YEE: HPF Coefficient  
YEE: HPF Coefficient  
YEE: HPF Coefficient  
YEE: HPF Coefficient  
YEE: HPF Coefficient  
YEE: HPF Coefficient  
YEE: HPF Coefficient  
YEE: HPF Coefficient  
YEE: HPF Coefficient  
YEE: Lower Threshold before referring to LUT  
YEE: Edge Sharpener Gain  
YEE_EN  
YEE_TYP  
YEE_SHF  
YEE_MUL_00  
YEE_MUL_01  
YEE_MUL_02  
YEE_MUL_10  
YEE_MUL_11  
YEE_MUL_12  
YEE_MUL_20  
YEE_MUL_21  
YEE_MUL_22  
YEE_THR  
YEE_E_GAN  
YEE_E_THR_1  
YEE_E_THR_2  
YEE_G_GAN  
YEE_G_OFT  
BOX_EN  
YEE: Edge Sharpener HP Value Lower Threshold  
YEE: Edge Sharpener HP Value Upper Limit  
YEE: Edge Sharpener Gain on Gradient  
YEE: Edge Sharpener Offset on Gradient  
BOX (=Boxcar) Enable  
BOX_MODE  
BOX_TYP  
BOX: One Shot Mode  
BOX: Block Size (16x16 or 8x8)  
BOX: Down shift value of input  
BOX: SDRAM Address MSB  
BOX: SDRAM Address LSB  
Reserved  
BOX_SHF  
BOX_SDR_SAD_H  
BOX_SDR_SAD_L  
Reserved  
HST_EN  
HST (=Histogram): Enable  
HST: One Shot Mode  
HST_MODE  
HST_SEL  
HST: Source Select  
HST_PARA  
HST_0_VPS  
HST_0_VSZ  
HST_0_HPS  
HST_0_HSZ  
HST_1_VPS  
HST_1_VSZ  
HST_1_HPS  
HST_1_HSZ  
HST_2_VPS  
HST_2_VSZ  
HST_2_HPS  
HST_2_HSZ  
HST_3_VPS  
HST_3_VSZ  
HST: Parameters Select  
HST: Vertical Start Position  
HST: Vertical Size  
HST: Horizontal Start Position  
HST: Horizontal Size  
HST: Vertical Start Position  
HST: Vertical Size  
HST: Horizontal Start Position  
HST: Horizontal Size  
HST: Vertical Start Position  
HST: Vertical Size  
HST: Horizontal Start Position  
HST: Horizontal Size  
HST: Vertical Start Position  
HST: Vertical Size  
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Table 6-42. IPIPE Registers (continued)  
Offset  
3E4h  
3E8h  
3ECh  
3F0h  
3F4h  
3F8h  
3FCh  
Acronym  
Register Description  
HST: Horizontal Start Position  
HST: Horizontal Size  
HST: Table Select  
HST_3_HPS  
HST_3_HSZ  
HST_TBL  
HST_MUL_R  
HST_MUL_GR  
HST_MUL_GB  
HST_MUL_B  
HST: Matrix Coefficient  
HST: Matrix Coefficient  
HST: Matrix Coefficient  
HST: Matrix Coefficient  
6.12.1.4 Hardware 3A (H3A)  
The H3A module is designed to support the control loops for Auto Focus, Auto White Balance and Auto  
Exposure by collecting metrics about the imaging/video data. The metrics are to adjust the various  
parameters for processing the imaging/video data. There are 2 main blocks in the H3A module:  
•
•
Auto Focus (AF) engine  
Auto Exposure (AE) Auto White Balance (AWB) engine  
The AF engine extracts and filters the red, green, and blue data from the input image/video data and  
provides either the accumulation or peaks of the data in a specified region. The specified region is a  
two-dimensional block of data and is referred to as a "paxel" for the case of AF.  
The AE/AWB Engine accumulates the values and checks for saturated values in a sub sampling of the  
video data. In the case of the AE/AWB, the two-dimensional block of data is referred to as a "window".  
Thus, other than referring them by different names, a paxel and a window are essentially the same thing.  
However, the number, dimensions, and starting position of the AF paxels and the AE/AWB windows are  
separately programmable.  
The following features are supported by the AF engine:  
•
•
•
•
•
•
Support for input from DDR2 / mDDR SDRAM (in addition to the ISIF port)  
Support for a Peak Mode in a Paxel (a Paxel is defined as a two dimensional block of pixels).  
Accumulate the maximum Focus Value of each line in a Paxel  
Support for an Accumulation/Sum Mode (instead of Peak mode).  
Accumulate Focus Value in a Paxel.  
Support for up to 36 Paxels in the horizontal direction and up to 128 Paxels in the vertical direction.  
The number of horizontal paxels is limited by the memory size (and cost), while the vertical number of  
paxels is not. Therefore, the number of paxels in horizontal direction is smaller than the number of  
paxels in vertical direction.  
•
•
•
•
•
Programmable width and height for the Paxel. All paxels in the frame will be of same size.  
Programmable red, green, and blue position within a 2x2 matrix.  
Separate horizontal start for paxel and filtering.  
Programmable vertical line increments within a paxel.  
Parallel IIR filters configured in a dual-biquad configuration with individual coefficients (2 filters with 11  
coefficients each). The filters are intended to compute the sharpness/peaks in the frame to focus on.  
The following features are supported by the AE/AWB engine:  
•
•
•
•
•
•
Support for input from DDR2 / mDDR SDRAM (in addition to the ISIF port)  
Accumulate clipped pixels along with all non-saturated pixels  
Support for up to 36 horizontal windows.  
Support for up to 128 vertical windows.  
Programmable width and height for the windows. All windows in the frame will be of same size.  
Separate vertical start co-ordinate and height for a black row of paxels that is different than the  
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remaining color paxels.  
•
•
Programmable Horizontal Sampling Points in a window  
Programmable Vertical Sampling Points in a window  
The Hardware 3A (H3A) register memory mapping (offsets) is shown in Table 6-43.  
Table 6-43. Hardware 3A Statistics Generation (AE, AF, AWB) (H3A) Registers  
Offset  
0h  
Acronym  
Register Description  
PID  
Peripheral Revision and Class Information  
Peripheral Control Register  
4h  
PCR  
8h  
AFPAX1  
Setup for the AF Engine Paxel Configuration  
Setup for the AF Engine Paxel Configuration  
Start Position for AF Engine Paxels  
Ch  
AFPAX2  
10h  
18h  
4Ch  
50h  
54h  
58h  
5Ch  
60h  
64h  
68h  
6Ch  
70h  
74h  
78h  
AFPAXSTART  
AFBUFST  
AEWWIN1  
AEWINSTART  
AEWINBLK  
AEWSUBWIN  
AEWBUFST  
RSDR_ADDR  
LINE_START  
VFV_CFG1  
VFV_CFG2  
VFV_CFG3  
VFV_CFG4  
HFV_THR  
SDRAM/DDRAM Start address for AF Engine  
Configuration for AE/AWB Windows  
Start position for AE/AWB Windows  
Start position and height for black line of AE/AWB Windows  
Configuration for subsample data in AE/AWB window  
SDRAM/DDRAM Start address for AE/AWB Engine Output Data  
AE/AWB Engine Configuration  
Line start position for ISIF interface  
AF Vertical Focus Configuration 1 Register  
AF Vertical Focus Configuration 2 Register  
AF Vertical Focus Configuration 3 Register  
AF Vertical Focus Configuration 4 Register  
Configures the Horizontal Thresholds for the AF IIR filters  
6.12.1.5 Face Detection Module  
The following features are supported on the Face Detection module:  
•
•
•
•
High detection rate of close to 100% under most conditions  
Allows detection in different directions - up, left, and right  
Allows detection with rotation in plane (RIP) - ±45°, @ 0°/+90°/-90°  
Allows detection for rotation out of plane (ROP)  
–
–
Horizontal (left/right) pan: ±60°  
Vertical (up/down) tilt: ±30°  
•
•
•
•
•
Configurable minimum face size of 20 - 40 pixels  
Configurable region of interest in the input frame  
Configurable start position in the input frame  
Supports up to 35 face detections in a single frame  
Interrupt generation to ARM using the Video Processing Subsystem (VPSS) multiplexed interrupt  
mechanism  
•
Robust performance in low light conditions, night vision, monochromatic, and false color sensing as  
skin tone not used for face detection  
•
•
Supported input size is (256X192)  
Input format is 8-bit gray scale data  
The Face Detection Module register memory mapping (offsets) is shown in Table 6-44.  
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Table 6-44. Face Detection Module Registers  
Offset  
0x000  
0x008  
0x00C  
0x010  
0x020  
0x024  
0x028  
0x02C  
0x030  
0x034  
0x038  
0x03C  
0x100  
0x104  
0x108  
0x10C  
0x110  
0x114  
0x118  
0x11C  
0x120  
0x124  
0x128  
0x12C  
0x130  
0x134  
0x138  
0x13C  
0x140  
0x144  
0x148  
0x14C  
0x150  
0x154  
0x158  
0x15C  
0x160  
0x164  
0x168  
0x16C  
0x170  
0x174  
0x178  
0x17C  
0x180  
0x184  
0x188  
Acronym  
Register Description  
FDIF_PID  
FDIF PID  
FDIF_INTEN  
FDIF Interrupt enable  
FDIF_PICADDR  
FDIF_WKADDR  
FD_CTRL  
FDIF Picture Data address  
FDIF Work Area address  
FD Core Control Register  
Detect number  
FD_DNUM  
FD_DCOND  
Detect Condition set register  
X Start address  
FD_STARTX  
FD_STARTY  
Y Start address  
FD_SIZEX  
X Size for detection  
FD_SIZEY  
Y Size for detection  
FD_LHIT  
Detect process threshold  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX1  
FD_CENTERY1  
FD_CONFSIZE1  
FD_ANGLE1  
FD_CENTERX2  
FD_CENTERY2  
FD_CONFSIZE2  
FD_ANGLE2  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX3  
FD_CENTERY3  
FD_CONFSIZE3  
FD_ANGLE3  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX4  
FD_CENTERY4  
FD_CONFSIZE4  
FD_ANGLE4  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX5  
FD_CENTERY5  
FD_CONFSIZE5  
FD_ANGLE5  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX6  
FD_CENTERY6  
FD_CONFSIZE6  
FD_ANGLE6  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX7  
FD_CENTERY7  
FD_CONFSIZE7  
FD_ANGLE7  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX8  
FD_CENTERY8  
FD_CONFSIZE8  
FD_ANGLE8  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX9  
FD_CENTERY9  
FD_CONFSIZE9  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
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Table 6-44. Face Detection Module Registers (continued)  
Offset  
0x18C  
0x190  
0x194  
0x198  
0x19C  
0x1A0  
0x1A4  
0x1A8  
0x1AC  
0x1B0  
0x1B4  
0x1B8  
0x1BC  
0x1C0  
0x1C4  
0x1C8  
0x1CC  
0x1D0  
0x1D4  
0x1D8  
0x1DC  
0x1E0  
0x1E4  
0x1E8  
0x1EC  
0x1F0  
0x1F4  
0x1F8  
0x1FC  
0x200  
0x204  
0x208  
0x20C  
0x210  
0x214  
0x218  
0x21C  
0x220  
0x224  
0x228  
0x22C  
0x230  
0x234  
0x238  
0x23C  
0x240  
0x244  
Acronym  
Register Description  
FD_ANGLE9  
Detect Angle  
FD_CENTERX10  
FD_CENTERY10  
FD_CONFSIZE10  
FD_ANGLE10  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX11  
FD_CENTERY11  
FD_CONFSIZE11  
FD_ANGLE11  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX12  
FD_CENTERY12  
FD_CONFSIZE12  
FD_ANGLE12  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX13  
FD_CENTERY13  
FD_CONFSIZE13  
FD_ANGLE13  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX14  
FD_CENTERY14  
FD_CONFSIZE14  
FD_ANGLE14  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX15  
FD_CENTERY15  
FD_CONFSIZE15  
FD_ANGLE15  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX16  
FD_CENTERY16  
FD_CONFSIZE16  
FD_ANGLE16  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX17  
FD_CENTERY17  
FD_CONFSIZE17  
FD_ANGLE17  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX18  
FD_CENTERY18  
FD_CONFSIZE18  
FD_ANGLE18  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX19  
FD_CENTERY19  
FD_CONFSIZE19  
FD_ANGLE19  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX20  
FD_CENTERY20  
FD_CONFSIZE20  
FD_ANGLE20  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX21  
FD_CENTERY21  
Detect Result Center X Address  
Detect Result Center Y Address  
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Table 6-44. Face Detection Module Registers (continued)  
Offset  
0x248  
0x24C  
0x250  
0x254  
0x258  
0x25C  
0x260  
0x264  
0x268  
0x26C  
0x270  
0x274  
0x278  
0x27C  
0x280  
0x284  
0x288  
0x28C  
0x290  
0x294  
0x298  
0x29C  
0x2A0  
0x2A4  
0x2A8  
0x2AC  
0x2B0  
0x2B4  
0x2B8  
0x2BC  
0x2C0  
0x2C4  
0x2C8  
0x2CC  
0x2D0  
0x2D4  
0x2D8  
0x2DC  
0x2E0  
0x2E4  
0x2E8  
0x2EC  
0x2F0  
0x2F4  
0x2F8  
0x2FC  
0x300  
Acronym  
Register Description  
FD_CONFSIZE21  
FD_ANGLE21  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX22  
FD_CENTERY22  
FD_CONFSIZE22  
FD_ANGLE22  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX23  
FD_CENTERY23  
FD_CONFSIZE23  
FD_ANGLE23  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX24  
FD_CENTERY24  
FD_CONFSIZE24  
FD_ANGLE24  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX25  
FD_CENTERY25  
FD_CONFSIZE25  
FD_ANGLE25  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX26  
FD_CENTERY26  
FD_CONFSIZE26  
FD_ANGLE26  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX27  
FD_CENTERY27  
FD_CONFSIZE27  
FD_ANGLE27  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX28  
FD_CENTERY28  
FD_CONFSIZE28  
FD_ANGLE28  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX29  
FD_CENTERY29  
FD_CONFSIZE29  
FD_ANGLE29  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX30  
FD_CENTERY30  
FD_CONFSIZE30  
FD_ANGLE30  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX31  
FD_CENTERY31  
FD_CONFSIZE31  
FD_ANGLE31  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX32  
FD_CENTERY32  
FD_CONFSIZE32  
FD_ANGLE32  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX33  
Detect Result Center X Address  
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Table 6-44. Face Detection Module Registers (continued)  
Offset  
0x304  
0x308  
0x30C  
0x310  
0x314  
0x318  
0x31C  
0x320  
0x324  
0x328  
0x32C  
Acronym  
Register Description  
FD_CENTERY33  
FD_CONFSIZE33  
FD_ANGLE33  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX34  
FD_CENTERY34  
FD_CONFSIZE34  
FD_ANGLE34  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
FD_CENTERX35  
FD_CENTERY35  
FD_CONFSIZE35  
FD_ANGLE35  
Detect Result Center X Address  
Detect Result Center Y Address  
Detect Result Confidence/Size  
Detect Angle  
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6.12.1.6 VPFE Electrical Data/Timing  
Table 6-45. Timing Requirements for VPFE PCLK Master/Slave Mode(1) (see Figure 6-31)  
NO.  
MIN  
8.33  
MAX  
120  
UNIT  
ns  
Slave Mode  
1
tc(PCLK)  
Cycle time, PCLK  
Master Mode  
13.33  
120  
ns  
2
3
4
tw(PCLKH)  
tw(PCLKL)  
tt(PCLK)  
Pulse duration, PCLK high  
Pulse duration, PCLK low  
Transition time, PCLK  
tc(PCLK)* 0.35 tc(PCLK)* 0.65  
ns  
ns  
ns  
tc(PCLK)* 0.35 tc(PCLK)* 0.65  
2
(1) P = 1/SYSCLK4 in nanoseconds (ns). For example, if the SYSCLK4 frequency is 135 MHz, use P = 7.41 ns. See Section 3.3 , Device  
Clocking, for more information on the supported clock configurations of the device.  
2
3
1
PCLK  
4
4
Figure 6-31. VPFE PCLK Timing  
Table 6-46. Timing Requirements for VPFE (ISIF) Slave Mode (see Figure 6-32)  
DEVICE  
MAX  
UNI  
T
NO.  
5
MIN  
2.5  
1.5  
1.5  
2.5  
2.5  
1.5  
1.5  
2.5  
2.5  
1.5  
1.5  
2.5  
2.5  
1.5  
1.5  
2.5  
2.5  
1.5  
1.5  
2.5  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
tsu(DATAV-  
PCLK)  
Setup time, ISIF DATA valid before PCLK edge  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
6
th(PCLK-DATAV) Hold time, ISIF DATA valid after PCLK edge  
7
tsu(HDV-PCLK)  
th(PCLK-HDV)  
tsu(VDV-PCLK)  
th(PCLK-VDV)  
Setup time, HD valid before PCLK edge  
Hold time, HD valid after PCLK edge  
Setup time, VD valid before PCLK edge  
Hold time, VD valid after PCLK edge  
Setup time, C_WE valid before PCLK edge  
8
9
10  
11  
12  
13  
14  
tsu(C_WEV-  
PCLK)  
th(PCLK-C_WEV) Hold time, C_WE valid after PCLK edge  
tsu(C_FIELDV-  
PCLK)  
Setup time, C_FIELD valid before PCLK edge  
th(PCLK-  
C_FIELDV)  
Hold time, C_FIELD valid after PCLK edge  
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PCLK  
(Positive Edge Clocking)  
PCLK  
(Negative Edge Clocking)  
8, 10  
7, 9  
HD/VD  
11, 13  
12, 14  
C_WE/C_FIELD  
5
6
CIN[7:0]/YIN[7:0]/  
CCD[15:0]  
Figure 6-32. VPFE (ISIF) Slave Mode Input Data Timing  
Table 6-47. Timing Requirements for VPFE (ISIF) Master Mode(1) (see Figure 6-33)  
DEVICE  
UNI  
T
NO.  
15  
MIN  
2.5  
1.5  
1.5  
2.5  
2.5  
1.5  
1.5  
2.5  
MAX  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
tsu(DATAV-  
PCLK)  
Setup time, ISIF DATA valid before PCLK edge  
ns  
ns  
ns  
ns  
16  
th(PCLK-DATAV) Hold time, ISIF DATA valid after PCLK edge  
tsu(CWEV-PCLK) Setup time, C_WE valid before PCLK edge  
th(PCLK-CWEV) Hold time, C_WE valid after PCLK edge  
23  
24  
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the  
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.  
PCLK  
(Positive Edge Clocking)  
PCLK  
(Positive Edge Clocking)  
15  
16  
CIN[7:0]/YIN[7:0]/  
CCD[15:0]  
23  
24  
C_WE/C_FIELD  
Figure 6-33. VPFE (ISIF) Master Mode Input Data Timing  
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Table 6-48. Switching Characteristics Over Recommended Operating Conditions for VPFE (ISIF) Master  
Mode (see Figure 6-34)  
DEVICE  
NO.  
PARAMETER  
UNIT  
MIN  
1.5  
MAX  
11  
18  
20  
td(PCLKL-HDIV)  
td(PCLKL-VDIV)  
Delay time, PCLK edge to HD valid  
Delay time, PCLK edge to VD valid  
ns  
ns  
1.5  
11  
PCLK  
(Negative Edge Clocking)  
PCLK  
(Positive Edge Clocking)  
18  
20  
HD  
VD  
Figure 6-34. VPFE (ISIF) Master Mode Control Output Data Timing  
6.12.2 Video Processing Back-End (VPBE)  
The Video Processing Back-End of VPBE module is comprised of the On Screen Display (OSD) module  
and the Video Encoder / Digital LCD Controller (VENC/DLCD).  
Table 6-49 lists the Video Processing Back-End (VPBE) module registers, their corresponding acronyms,  
and the device memory locations (offsets).  
Note: HD display mode resolutions are not supported on ARM 216Mhz clock rate devices.  
Table 6-49. VPBE Module Register Map  
Address  
Peripheral  
VPBE_CLK_CTRL  
OSD  
Description  
0x01C7:0200  
0x01C7:1C00  
0x01C7:1E00  
VPBE Clock Control  
VPBE On-Screen Display  
VPBE Video Encoder  
VENC  
6.12.2.1 On-Screen Display (OSD)  
The primary function of the OSD module is to gather and blend video data and display/bitmap data and  
then pass it to the Video Encoder (VENC) in YCbCr format. The video and display data is read from  
external DDR2/mDDR memory. The OSD is programmed via control and parameter registers. The  
following are the primary features that are supported by the OSD.  
•
Support for two video windows and two OSD bitmapped windows that can be displayed simultaneously  
(VIDWIN0/VIDWIN1 and OSDWIN0/OSDWIN1).  
•
Video windows support YCbCr data in 422 and 420 formats from external memory, with the ability to  
interchange the order of the CbCr component in the 32-bit word  
•
•
OSD bitmap windows support ＝/4/8 bit width index data of color palette  
In addition one OSD bitmap window at a time can be configured to one of the following:  
–
–
–
YUV422 (same as video data)  
RGB format data in 16-bit mode (R=5bit, G=6bit, B=5bit)  
24-bit mode (each R/G/B=8bit) with pixel level blending with video windows  
•
Programmable color palette with the ability to select between a RAM/ROM table with support for 256  
colors.  
•
•
Support for 2 ROM tables, one of which can be selected at a given time  
Separate enable/disable control for each window  
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•
•
•
•
Programmable width, height, and base starting coordinates for each window  
External memory address and offset registers for each window  
Support for x2 and x4 zoom in both the horizontal and vertical direction  
Pixel-level blending/transparency/blinking attributes can be defined for OSDWIN0 when OSDWIN1 is  
configured as an attribute window for OSDWIN0.  
•
•
•
•
Support for blinking intervals to the attribute window  
Ability to select either field/frame mode for the windows (interlaced/progressive)  
An eight step blending process between the bitmap and video windows  
Transparency support for the bitmap and video data (when a bitmap pixel is zero, there will be no  
blending for that corresponding video pixel)  
•
•
•
•
•
Ability to resize from VGA to NTSC/PAL (640x480 to 720x576) for both the OSD and video windows  
Horizontal rescaling x1.5 is supported  
Support for a rectangular cursor window and a programmable background color selection.  
The width, height, and color of the cursor is selectable  
The display priority is: Rectangular-Cursor > OSDWIN1 > OSDWIN0 > VIDWIN1 > VIDWIN0 >  
background color  
•
Support for attenuation of the YCbCr values for the REC601 standard.  
The following restrictions exist in the OSD module.  
•
If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window  
dimension cannot be greater than 1024 currently. This is due to the limitation in the size of the line  
memory.  
•
It is not possible to use both of the CLUT ROMs at the same time. However, a window can use RAM  
while another uses ROM.  
Table 6-50 lists the On-Screen Display (OSD) registers, their corresponding acronyms, and the device  
memory locations (offsets).  
Table 6-50. On-Screen Display (OSD) Registers  
Offset  
0h  
Acronym  
Register Description  
MODE  
OSD Mode Setup  
4h  
VIDWINMD  
OSDWIN0MD  
OSDWIN1MD  
Video Window Mode Setup  
Bitmap Window 0 Mode Setup  
8h  
Ch  
OSD Window 1 Mode Setup  
(when used as a second OSD window)  
Ch  
OSDATRMD  
OSD Attribute Window Mode Setup  
(when used as an attribute window)  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
2Ch  
30h  
34h  
38h  
3Ch  
40h  
RECTCUR  
Rectangular Cursor Setup  
Reserved  
RSV0  
VIDWIN0OFST  
VIDWIN1OFST  
OSDWIN0OFST  
OSDWIN1OFST  
VIDWINADH  
VIDWIN0ADL  
VIDWIN1ADL  
OSDWINADH  
OSDWIN0ADL  
OSDWIN1ADL  
BASEPX  
Video Window 0 Offset  
Video Window 1 Offset  
Bitmap Window 0 Offset  
Bitmap Window 1/Attribute Window Offset  
Video Window 0/1 Address - High  
Video Window 0 Address - Low  
Video Window 1 Address - Low  
BMP Window 0/1 Address - High  
BMP Window 0 Address - Low  
Bitmap Window 1/Attribute Address - Low  
Base Pixel X  
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Table 6-50. On-Screen Display (OSD) Registers (continued)  
Offset  
44h  
48h  
4Ch  
50h  
54h  
58h  
5Ch  
60h  
64h  
68h  
6Ch  
70h  
74h  
78h  
7Ch  
80h  
84h  
88h  
8Ch  
90h  
94h  
98h  
9Ch  
A0h  
A4h  
A8h  
ACh  
B0h  
B4h  
B8h  
BCh  
C0h  
C4h  
C8h  
CCh  
D0h  
D4h  
D8h  
DCh  
E0h  
E4h  
E8h  
ECh  
F0h  
F4h  
F8h  
FCh  
Acronym  
Register Description  
BASEPY  
Base Pixel Y  
VIDWIN0XP  
VIDWIN0YP  
VIDWIN0XL  
VIDWIN0YL  
VIDWIN1XP  
VIDWIN1YP  
VIDWIN1XL  
VIDWIN1YL  
OSDWIN0XP  
OSDWIN0YP  
OSDWIN0XL  
OSDWIN0YL  
OSDWIN1XP  
OSDWIN1YP  
OSDWIN1XL  
OSDWIN1YL  
CURXP  
Video Window 0 X-Position  
Video Window 0 Y-Position  
Video Window 0 X-Size  
Video Window 0 Y-Size  
Video Window 1 X-Position  
Video Window 1 Y-Position  
Video Window 1 X-Size  
Video Window 1 Y-Size  
Bitmap Window 0 X-Position  
Bitmap Window 0 Y-Position  
Bitmap Window 0 X-Size  
Bitmap Window 0 Y-Size  
Bitmap Window 1 X-Position  
Bitmap Window 1 Y-Position  
Bitmap Window 1 X-Size  
Bitmap Window 1 Y-Size  
Rectangular Cursor Window X-Position  
Rectangular Cursor Window Y-Position  
Rectangular Cursor Window X-Size  
Rectangular Cursor Window Y-Size  
Reserved  
CURYP  
CURXL  
CURYL  
RSV1  
RSV2  
Reserved  
W0BMP01  
W0BMP23  
W0BMP45  
W0BMP67  
W0BMP89  
W0BMPAB  
W0BMPCD  
W0BMPEF  
W1BMP01  
W1BMP23  
W1BMP45  
W1BMP67  
W1BMP89  
W1BMPAB  
W1BMPCD  
W1BMPEF  
VBNDRY  
Window 0 Bitmap Value to Palette Map 0/1  
Window 0 Bitmap Value to Palette Map 2/3  
Window 0 Bitmap Value to Palette Map 4/5  
Window 0 Bitmap Value to Palette Map 6/7  
Window 0 Bitmap Value to Palette Map 8/9  
Window 0 Bitmap Value to Palette Map A/B  
Window 0 Bitmap Value to Palette Map C/D  
Window 0 Bitmap Value to Palette Map E/F  
Window 1 Bitmap Value to Palette Map 0/1  
Window 1 Bitmap Value to Palette Map 2/3  
Window 1 Bitmap Value to Palette Map 4/5  
Window 1 Bitmap Value to Palette Map 6/7  
Window 1 Bitmap Value to Palette Map 8/9  
Window 1 Bitmap Value to Palette Map A/B  
Window 1 Bitmap Value to Palette Map C/D  
Window 1 Bitmap Value to Palette Map E/F  
Test Mode  
EXTMODE  
MISCCTL  
Extended Mode  
Miscellaneous Control  
CLUTRAMYCB  
CLUTRAMCR  
TRANSPVALL  
TRANSPVALU  
TRANSPBMPIDX  
CLUT RAM Y/Cb Setup  
CLUT RAM Cr/Mapping Setup  
Transparent Color Code - Lower  
Transparent Color Code - Upper  
Transparent Index Code for Bitmaps  
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6.12.2.2 Video Encoder / Digital LCD Controller (VENC/DLCD)  
The VENC/DLCD consists of three major blocks:  
•
•
•
Video encoder to generate analog video output  
Digital LCD controller to generate digital RGB/YCbCr data output and timing signals  
Timing generator  
The video encoder for analog video supports the following features:  
•
•
Master Clock Input - 27 MHz or 74.25 MHz  
SDTV Support  
–
–
–
–
–
–
Composite NTSC-M, PAL-B/D/G/H/I  
S-Video (Y/C)  
Component YPbPr  
RGB  
CGMS/WSS  
Closed Caption  
•
HDTV Support  
–
–
–
–
525p/625p/720p/1080i  
Component YPbPr  
RGB  
CGMS/WSS  
•
•
Master/Slave Operation  
Three 10-bit D/A Converters  
The digital LCD controller supports the following features:  
•
•
Programmable Timing Generator  
Various Output Formats  
–
–
–
–
YCbCr 4:2:2 16-bit  
YCbCr 4:2:2 8-bit  
Parallel RGB 16/18/24-bit  
Serial RGB 8-bit  
•
•
EAV/SAV insertion  
Master/Slave Operation  
Table 6-51 lists the Video Encoder / Digital LCD Controller (VENC/DLCD) registers, their corresponding  
acronyms, and the device memory locations (offsets).  
Table 6-51. Video Encoder (VENC) Registers  
Offset  
0h  
Acronym  
VMOD  
Register Description  
Video Mode  
4h  
VIOCTL  
VDPRO  
SYNCCTL  
HSPLS  
Video Interface I/O Control  
Video Data Processing  
Sync Control  
8h  
Ch  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
Horizontal Sync Pulse Width  
Vertical Sync Pulse Width  
Horizontal Interval  
VSPLS  
HINTVL  
HSTART  
HVALID  
VINTVL  
VSTART  
Horizontal Valid Data Start Position  
Horizontal Data Valid Range  
Vertical Interval  
Vertical Valid Data Start Position  
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Table 6-51. Video Encoder (VENC) Registers (continued)  
Offset  
2Ch  
30h  
34h  
38h  
3Ch  
40h  
44h  
48h  
4Ch  
50h  
54h  
58h  
5Ch  
60h  
64h  
68h  
6Ch  
70h  
74h  
78h  
7Ch  
80h  
84h  
88h  
8Ch  
90h  
94h  
98h  
9Ch  
A0h  
A4h  
A8h  
ACh  
B0h  
B4h  
B8h  
BCh  
C0h  
C4h  
C8h  
CCh  
D0h  
D4h  
D8h  
DCh  
E0h  
E4h  
Acronym  
VVALID  
Register Description  
Vertical Data Valid Range  
Horizontal Sync Delay  
Vertical Sync Delay  
HSDLY  
VSDLY  
YCCCTL  
RGBCTL  
RGBCLP  
LINECTL  
CULLLINE  
LCDOUT  
BRT0  
YCbCr Control  
RGB Control  
RGB Level Clipping  
Line ID Control  
Culling Line Control  
LCD Output Signal Control  
Brightness Start Position Signal Control  
Brightness Width Signal Control  
LCD_AC Signal Control  
PWM Output Period  
BRT1  
ACCTL  
PWM0  
PWM1  
PWM Output Pulse Width  
DCLK Control  
DCLKCTL  
DCLKPTN0  
DCLKPTN1  
DCLKPTN2  
DCLKPTN3  
DCLKPTN0A  
DCLKPTN1A  
DCLKPTN2A  
DCLKPTN3A  
DCLKHSTT  
DCLKHSTTA  
DCLKHVLD  
DCLKVSTT  
DCLKVVLD  
CAPCTL  
CAPDO  
DCLK Pattern 0  
DCLK Pattern 1  
DCLK Pattern 2  
DCLK Pattern 3  
DCLK Auxiliary Pattern 0  
DCLK Auxiliary Pattern 1  
DCLK Auxiliary Pattern 2  
DCLK Auxiliary Pattern 3  
Horizontal DCLK Mask Start Position  
Horizontal Auxiliary DCLK Mask Start Position  
Horizontal DCLK Mask Range  
Vertical DCLK Mask Start Position  
Vertical DCLK Mask Range  
Closed Caption Control  
Closed Caption Odd Field Data  
Closed Caption Even Field Data  
Video Attribute Data 0  
Video Attribute Data 1  
Video Attribute Data 2  
Reserved 0  
CAPDE  
ATR0  
ATR1  
ATR2  
RSV0  
VSTAT  
Video Status  
RAMADR  
RAMPORT  
DACTST  
YCOLVL  
SCPROG  
RSV1  
GCP/FRC Table RAM Address  
GCP/FRC Table RAM Data Port  
DAC Test  
YOUT and COUT Levels  
Sub-Carrier Programming  
Reserved 1  
RSV2  
Reserved 2  
RSV3  
Reserved 3  
CVBS  
Composite Mode  
CMPNT  
Component Mode  
ETMG0  
CVBS Timing Control 0  
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Table 6-51. Video Encoder (VENC) Registers (continued)  
Offset  
Acronym  
ETMG1  
Register Description  
E8h  
ECh  
CVBS Timing Control 1  
ETMG2  
CVBS Timing Control 2  
F0h  
ETMG3  
CVBS Timing Control 3  
F4h  
DACSEL  
ARGBX0  
ARGBX1  
ARGBX2  
ARGBX3  
ARGBX4  
DRGBX0  
DRGBX1  
DRGBX2  
DRGBX3  
DRGBX4  
VSTARTA  
OSDCLK0  
OSDCLK1  
HVLDCL0  
HVLDCL1  
OSDHADV  
CLKCTL  
GAMCTL  
VVALIDA  
BATR0  
DAC Output Select  
100h  
104h  
108h  
10Ch  
110h  
114h  
118h  
11Ch  
120h  
124h  
128h  
12Ch  
130h  
134h  
138h  
13Ch  
140h  
144h  
148h  
14Ch  
150h  
154h  
158h  
15Ch  
160h  
164h  
168h  
16Ch  
170h  
Analog RGB Matrix 0  
Analog RGB Matrix 1  
Analog RGB Matrix 2  
Analog RGB Matrix 3  
Analog RGB Matrix 4  
Digital RGB Matrix 0  
Digital RGB Matrix 1  
Digital RGB Matrix 2  
Digital RGB Matrix 3  
Digital RGB Matrix 4  
Vertical Data Valid Start Position For Even Field  
OSD Clock Control 0  
OSD Clock Control 1  
Horizontal Valid Culling Control 0  
Horizontal Valid Culling Control 1  
OSD Horizontal Sync Advance  
Clock Control  
Enable Gamma Correction  
Vertical Data Valid Area For Even Field  
Video Attribute 0 For Type B Packet  
Video Attribute 1 For Type B Packet  
Video Attribute 2 For Type B Packet  
Video Attribute 3 For Type B Packet  
Video Attribute 4 For Type B Packet  
Video Attribute 5 For Type B Packet  
Video Attribute 6 For Type B Packet  
Video Attribute 7 For Type B Packet  
Video Attribute 8 For Type B Packet  
Gain and Offset  
BATR1  
BATR2  
BATR3  
BATR4  
BATR5  
BATR6  
BATR7  
BATR8  
DACAMP  
6.12.2.3 VPBE Electrical Data/Timing  
Table 6-52. Timing Requirements for VPBE CLK Inputs (see Figure 6-35)  
DEVICE  
MIN  
NO.  
UNIT  
MAX  
1
2
3
4
5
6
7
tc(PCLK)  
Cycle time, PCLK(1)  
13.33  
5.7  
160  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tw(PCLKH)  
tw(PCLKL)  
tt(PCLK)  
Pulse duration, PCLK high  
Pulse duration, PCLK low  
Transition time, PCLK  
5.7  
3
tc(EXTCLK)  
tw(EXTCLKH)  
tw(EXTCLKL)  
Cycle time, EXTCLK  
13.33  
5.7  
160  
Pulse duration, EXTCLK high  
Pulse duration, EXTCLK low  
5.7  
(1) For timing specifications relating to PCLK see Table 6-45 , Timing Requirements for VPFE PCLK Master/Slave Mode.  
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Table 6-52. Timing Requirements for VPBE CLK Inputs (see Figure 6-35 ) (continued)  
DEVICE  
MIN  
NO.  
UNIT  
MAX  
8
tt(EXTCLK)  
Transition time, EXTCLK  
3
ns  
3
7
1
2
6
PCLK  
4
4
5
EXTCLK  
8
8
Figure 6-35. VPBE PCLK and EXTCLK Timing  
Table 6-53. Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK(1) (2) (3) (see  
Figure 6-36)  
DEVICE  
UNI  
T
NO.  
9
MIN  
4
MAX  
Positive Edge  
Negative Edge  
Positive Edge  
Negative Edge  
tsu(VCTLV-  
VCLKIN)  
Setup time, VCTL valid before VCLKIN  
edge  
ns  
ns  
3
1
th(VCLKIN-  
VCTLV)  
10  
Hold time, VCTL valid after VCLKIN edge  
2
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the  
rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.  
(2) VCTL = HSYNC, VSYNC, and FIELD  
(3) VCLKIN = PCLK or EXTCLK. Positive and Negative Edge apply to PCLK only; EXTCLK does not support Negative Edge clocking.  
(A)  
VCLKIN  
(Positive Edge Clocking)  
(A)  
VCLKIN  
(Negative Edge Clocking)  
10  
9
(B)  
VCTL  
A. VCLKIN = PCLK or EXTCLK. Note Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking.  
B.  
VCTL = HSYNC, VSYNC, and FIELD  
Figure 6-36. VPBE Input Timing With Respect to PCLK and EXTCLK  
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Table 6-54. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and  
Data Output With Respect to PCLK and EXTCLK(1) (2) (3) (see Figure 6-37)  
DEVICE  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
15  
Positive Edge  
Negative Edge  
td(VCLKIN-  
VCTLV)  
11  
12  
13  
14  
Delay time, VCLKIN edge to VCTL valid  
Delay time, VCLKIN edge to VCTL invalid  
Delay time, VCLKIN edge to VDATA valid  
Delay time, VCLKIN edge to VDATA invalid  
ns  
ns  
ns  
ns  
16  
td(VCLKIN-  
VCTLIV)  
2
VCLKIN = EXTCLK  
VCLKIN = PCLK  
15  
td(VCLKIN-  
VDATAV)  
17.5  
td(VCLKIN-  
VDATAIV)  
2
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the  
rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.  
(2) VCLKIN = PCLK or EXTCLK. Positive and Negative Edge apply to PCLK only; EXTCLK does not support Negative Edge clocking.  
(3) VCTL = HSYNC, VSYNC, FIELD, and LCD_OE.  
(A)  
VCLKIN  
(Positive Edge Clocking)  
(A)  
VCLKIN  
(Negative Edge Clocking)  
11  
13  
12  
14  
(B)  
(C)  
VCTL  
VDATA  
A. VCLKIN = PCLK or EXTCLK. Note Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking.  
B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE  
C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]  
Figure 6-37. VPBE Control and Data Output With Respect to PCLK and EXTCLK  
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Table 6-55. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and  
Data Output With Respect to VCLK(1) (2) (3)(see Figure 6-38)  
DEVICE  
NO.  
PARAMETER  
UNIT  
MIN  
13.33  
5.7  
MAX  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
tc(VCLK)  
Cycle time, VCLK  
160  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tw(VCLKH)  
Pulse duration, VCLK high  
tw(VCLKL)  
Pulse duration, VCLK low  
5.7  
tt(VCLK)  
Transition time, VCLK  
3
16  
td(VCLKINH-VCLKH)  
td(VCLKINL-VCLKL)  
td(VCLK-VCTLV)  
td(VCLK-VCTLIV)  
td(VCLK-VDATAV)  
td(VCLK-VDATAIV)  
Delay time, VCLKIN high to VCLK high  
Delay time, VCLKIN low to VCLK low  
Delay time, VCLK edge to VCTL valid  
Delay time, VCLK edge to VCTL invalid  
Delay time, VCLK edge to VDATA valid  
Delay time, VCLK edge to VDATA invalid  
3
3
16  
1.5  
-1.5  
1.5  
-1.5  
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the  
rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.  
(2) VCLKIN = PCLK or EXTCLK. Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking. For  
timing specifications relating to PCLK, see Table 6-45 , Timing Requirements for VPFE PCLK Master/Slave Mode.  
(3) VCTL= HSYNC, VSYNC, FIELD and LCD_OE.  
(A)  
VCLKIN  
19  
21  
17  
22  
18  
VCLK  
(Positive Edge  
Clocking)  
VCLK  
(Negative Edge  
Clocking)  
20  
23  
25  
20  
24  
26  
(B)  
VCTL  
(C)  
VDATA  
A.  
VCLKIN = PCLK or EXTCLK. Note Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking.  
B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE  
C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]  
Figure 6-38. VPBE Control and Data Output Timing With Respect to VCLK  
6.12.2.4 High-Definition (HD) DACs and Video Buffer Electrical Data/Timing  
Three DACs and a video buffer are available on the device.  
6.12.2.4.1 HD DACs-Only Option  
In the HD DACs-only configuration, the internal video buffer is not used and an external video buffer is  
attached to the DACs. Another solution is to use a Video Amplifier, such as the Texas Instruments'  
THS7303 which provides a complete solution to the typical output circuit shown in Figure 6-39.  
Note: HD display mode resolutions are not supported on ARM 216Mhz clock rate devices.  
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TV Monitor  
75 Ω  
DAC  
CH-A  
Low-Pass Filter  
~RLOAD = 75 Ω  
COMPY  
COMPPB  
COMPPR  
Amplifier  
Gain = 5.6 V/V  
75 Ω  
75 Ω  
75 Ω  
75 Ω  
75 Ω  
DAC  
CH-B  
Low-Pass Filter  
~RLOAD = 75 Ω  
Amplifier  
Gain = 5.6 V/V  
DAC  
CH-C  
Low-Pass Filter  
~RLOAD = 75 Ω  
Amplifier  
Gain = 5.6 V/V  
IREF  
RBIAS  
VREF  
CBG  
IDACOUT  
VFB  
DC = 0.5 V  
0.1 µF  
TVOUT  
A. RBIAS = 2400Ω.  
B. VREF = 0.5V (from external supply).  
C. IDACOUT must be connected to Vss or left open for proper device configuration.  
D. VFB must be connected to Vss or left open for proper device configuration.  
E. TVOUT must be connected to Vss or left open for proper device configuration.  
Figure 6-39. HD Video DAC Application Example  
6.12.2.4.2 DAC With Video Buffer Option  
In a DAC plus video buffer configuration, one of the DACs may be used along with the video buffer for  
standard definition TVOUT mode. In the DAC plus video buffer configuration, the DAC and internal video  
buffer are both used, and a TV cable may be attached directly to the output of the video buffer.Figure 6-40  
shows an example of the DAC Plus Video Buffer Option circuit configuration.  
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COMPY  
COMPPB  
COMPPR  
DAC CHC  
IREF  
VREF  
RBIAS  
CBG  
DC = 0.5 V  
IDACOUT  
0.1 µF  
R1  
R2  
Video  
Buffer  
VFB  
TV monitor  
TVOUT  
RL  
Figure 6-40. SD Video Buffer Application Example  
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6.13 USB 2.0  
The USB2.0 peripheral supports the following features:  
•
•
•
•
•
USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)  
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)  
All transfer modes (control, bulk, interrupt, and isochronous)  
Four Transmit (TX) and four Receive (RX) endpoints in addition to endpoint 0  
FIFO RAM  
–
–
4K bytes shared by all endpoints.  
Programmable FIFO size  
•
•
•
Includes a DMA sub-module that supports four TX and four RX channels of CPPI 3.0 DMAs  
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB  
USB OTG extensions, i.e. session request protocol (SRP) and host negotiation protocol (HNP)  
The USB2.0 peripheral does not support the following features:  
•
•
•
•
On-chip charge pump  
High bandwidth ISO mode is not supported (triple buffering)  
RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes  
Endpoint max USB packet sizes that do not conform to the USB 2.0 spec (for FS/LS: 8, 16, 32, 64,  
and 1023 are defined; for HS: 64, 128, 512, and 1024 are defined)  
6.13.1 USB Peripheral Register Description(s)  
Table 6-56 lists the USB registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-56. Universal Serial Bus (USB) Registers  
Offset  
4h  
Acronym  
Register Description  
CTRLR  
Control Register  
8h  
STATR  
Status Register  
10h  
14h  
20h  
24h  
28h  
2Ch  
30h  
34h  
38h  
3Ch  
40h  
80h  
84h  
88h  
8Ch  
90h  
94h  
98h  
9Ch  
C0h  
RNDISR  
RNDIS Register  
AUTOREQ  
INTSRCR  
Autorequest Register  
USB Interrupt Source Register  
USB Interrupt Source Set Register  
USB Interrupt Source Clear Register  
USB Interrupt Mask Register  
USB Interrupt Mask Set Register  
USB Interrupt Mask Clear Register  
USB Interrupt Source Masked Register  
USB End of Interrupt Register  
USB Interrupt Vector Register  
Transmit CPPI Control Register  
Transmit CPPI Teardown Register  
Transmit CPPI DMA Controller End of Interrupt Register  
-
INTSETR  
INTCLRR  
INTMSKR  
INTMSKSETR  
INTMSKCLRR  
INTMASKEDR  
EOIR  
INTVECTR  
TCPPICR  
TCPPITDR  
TCPPIEOIR  
Reserved  
TCPPIMSKSR  
TCPPIRAWSR  
TCPPIIENSETR  
TCPPIIENCLRR  
RCPPICR  
Transmit CPPI Masked Status Register  
Transmit CPPI Raw Status Register  
Transmit CPPI Interrupt Enable Set Register  
Transmit CPPI Interrupt Enable Clear Register  
Receive CPPI Control Register  
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Table 6-56. Universal Serial Bus (USB) Registers (continued)  
Offset  
D0h  
D4h  
D8h  
DCh  
E0h  
Acronym  
Register Description  
Receive CPPI Masked Status Register  
Receive CPPI Raw Status Register  
Receive CPPI Interrupt Enable Set Register  
Receive CPPI Interrupt Enable Clear Register  
Receive Buffer Count 0 Register  
Receive Buffer Count 1 Register  
Receive Buffer Count 2 Register  
Receive Buffer Count 3 Register  
Transmit/Receive CPPI Channel 0 State Block  
Transmit CPPI DMA State Word 0  
Transmit CPPI DMA State Word 1  
Transmit CPPI DMA State Word 2  
Transmit CPPI DMA State Word 3  
Transmit CPPI DMA State Word 4  
Transmit CPPI DMA State Word 5  
Transmit CPPI Completion Pointer  
Receive CPPI DMA State Word 0  
Receive CPPI DMA State Word 1  
Receive CPPI DMA State Word 2  
Receive CPPI DMA State Word 3  
Receive CPPI DMA State Word 4  
Receive CPPI DMA State Word 5  
Receive CPPI DMA State Word 6  
Receive CPPI Completion Pointer  
Transmit/Receive CPPI Channel 1 State Block  
Transmit CPPI DMA State Word 0  
Transmit CPPI DMA State Word 1  
Transmit CPPI DMA State Word 2  
Transmit CPPI DMA State Word 3  
Transmit CPPI DMA State Word 4  
Transmit CPPI DMA State Word 5  
Transmit CPPI Completion Pointer  
Receive CPPI DMA State Word 0  
Receive CPPI DMA State Word 1  
Receive CPPI DMA State Word 2  
Receive CPPI DMA State Word 3  
Receive CPPI DMA State Word 4  
Receive CPPI DMA State Word 5  
Receive CPPI DMA State Word 6  
Receive CPPI Completion Pointer  
Transmit/Receive CPPI Channel 2 State Block  
Transmit CPPI DMA State Word 0  
Transmit CPPI DMA State Word 1  
Transmit CPPI DMA State Word 2  
Transmit CPPI DMA State Word 3  
Transmit CPPI DMA State Word 4  
Transmit CPPI DMA State Word 5  
RCPPIMSKSR  
RCPPIRAWSR  
RCPPIENSETR  
RCPPIIENCLRR  
RBUFCNT0  
E4h  
RBUFCNT1  
E8h  
RBUFCNT2  
ECh  
RBUFCNT3  
100h  
104h  
108h  
10Ch  
110h  
114h  
11Ch  
120h  
124h  
128h  
12Ch  
130h  
134h  
138h  
13Ch  
TCPPIDMASTATEW0  
TCPPIDMASTATEW1  
TCPPIDMASTATEW2  
TCPPIDMASTATEW3  
TCPPIDMASTATEW4  
TCPPIDMASTATEW5  
TCPPICOMPPTR  
RCPPIDMASTATEW0  
RCPPIDMASTATEW1  
RCPPIDMASTATEW2  
RCPPIDMASTATEW3  
RCPPIDMASTATEW4  
RCPPIDMASTATEW5  
RCPPIDMASTATEW6  
RCPPICOMPPTR  
140h  
144h  
148h  
14Ch  
150h  
154h  
15Ch  
160h  
164h  
168h  
16Ch  
170h  
174h  
178h  
17Ch  
TCPPIDMASTATEW0  
TCPPIDMASTATEW1  
TCPPIDMASTATEW2  
TCPPIDMASTATEW3  
TCPPIDMASTATEW4  
TCPPIDMASTATEW5  
TCPPICOMPPTR  
RCPPIDMASTATEW0  
RCPPIDMASTATEW1  
RCPPIDMASTATEW2  
RCPPIDMASTATEW3  
RCPPIDMASTATEW4  
RCPPIDMASTATEW5  
RCPPIDMASTATEW6  
RCPPICOMPPTR  
180h  
184h  
188h  
18Ch  
190h  
194h  
TCPPIDMASTATEW0  
TCPPIDMASTATEW1  
TCPPIDMASTATEW2  
TCPPIDMASTATEW3  
TCPPIDMASTATEW4  
TCPPIDMASTATEW5  
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Table 6-56. Universal Serial Bus (USB) Registers (continued)  
Offset  
19Ch  
1A0h  
1A4h  
1A8h  
1ACh  
1B0h  
1B4h  
1B8h  
1BCh  
Acronym  
Register Description  
Transmit CPPI Completion Pointer  
Receive CPPI DMA State Word 0  
Receive CPPI DMA State Word 1  
Receive CPPI DMA State Word 2  
Receive CPPI DMA State Word 3  
Receive CPPI DMA State Word 4  
Receive CPPI DMA State Word 5  
Receive CPPI DMA State Word 6  
Receive CPPI Completion Pointer  
Transmit/Receive CPPI Channel 3 State Block  
Transmit CPPI DMA State Word 0  
Transmit CPPI DMA State Word 1  
Transmit CPPI DMA State Word 2  
Transmit CPPI DMA State Word 3  
Transmit CPPI DMA State Word 4  
Transmit CPPI DMA State Word 5  
Transmit CPPI Completion Pointer  
Receive CPPI DMA State Word 0  
Receive CPPI DMA State Word 1  
Receive CPPI DMA State Word 2  
Receive CPPI DMA State Word 3  
Receive CPPI DMA State Word 4  
Receive CPPI DMA State Word 5  
Receive CPPI DMA State Word 6  
Receive CPPI Completion Pointer  
Common USB Registers  
TCPPICOMPPTR  
RCPPIDMASTATEW0  
RCPPIDMASTATEW1  
RCPPIDMASTATEW2  
RCPPIDMASTATEW3  
RCPPIDMASTATEW4  
RCPPIDMASTATEW5  
RCPPIDMASTATEW6  
RCPPICOMPPTR  
1C0h  
1C4h  
1C8h  
1CCh  
1D0h  
1D4h  
1DCh  
1E0h  
1E4h  
1E8h  
1ECh  
1F0h  
1F4h  
1F8h  
1FCh  
TCPPIDMASTATEW0  
TCPPIDMASTATEW1  
TCPPIDMASTATEW2  
TCPPIDMASTATEW3  
TCPPIDMASTATEW4  
TCPPIDMASTATEW5  
TCPPICOMPPTR  
RCPPIDMASTATEW0  
RCPPIDMASTATEW1  
RCPPIDMASTATEW2  
RCPPIDMASTATEW3  
RCPPIDMASTATEW4  
RCPPIDMASTATEW5  
RCPPIDMASTATEW6  
RCPPICOMPPTR  
400h  
401h  
402h  
404h  
406h  
408h  
40Ah  
40Bh  
40Ch  
40Eh  
40Fh  
FADDR  
Function Address Register  
POWER  
INTRTX  
Power Management Register  
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4  
Interrupt Register for Receive Endpoints 1 to 4  
Interrupt enable register for INTRTX  
Interrupt Enable Register for INTRRX  
Interrupt Register for Common USB Interrupts  
Interrupt Enable Register for INTRUSB  
Frame Number Register  
INTRRX  
INTRTXE  
INTRRXE  
INTRUSB  
INTRUSBE  
FRAME  
INDEX  
Index Register for Selecting the Endpoint Status and Control Registers  
Register to Enable the USB 2.0 Test Modes  
Indexed Registers  
TESTMODE  
These registers operate on the endpoint selected by the INDEX register  
410h  
412h  
TXMAXP  
Maximum Packet Size for Peripheral/Host Transmit Endpoint.  
(Index register set to select Endpoints 1-4)  
PERI_CSR0  
HOST_CSR0  
PERI_TXCSR  
HOST_TXCSR  
Control Status Register for Endpoint 0 in Peripheral Mode.  
(Index register set to select Endpoint 0)  
Control Status Register for Endpoint 0 in Host Mode.  
(Index register set to select Endpoint 0)  
Control Status Register for Peripheral Transmit Endpoint.  
(Index register set to select Endpoints 1-4)  
Control Status Register for Host Transmit Endpoint.  
(Index register set to select Endpoints 1-4)  
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Table 6-56. Universal Serial Bus (USB) Registers (continued)  
Offset  
Acronym  
Register Description  
414h  
RXMAXP  
Maximum Packet Size for Peripheral/Host Receive Endpoint.  
(Index register set to select Endpoints 1-4)  
416h  
418h  
41Ah  
41Bh  
PERI_RXCSR  
HOST_RXCSR  
COUNT0  
Control Status Register for Peripheral Receive Endpoint.  
(Index register set to select Endpoints 1-4)  
Control Status Register for Host Receive Endpoint.  
(Index register set to select Endpoints 1-4)  
Number of Received Bytes in Endpoint 0 FIFO.  
(Index register set to select Endpoint 0)  
RXCOUNT  
Number of Bytes in Host Receive Endpoint FIFO.  
(Index register set to select Endpoints 1- 4)  
HOST_TYPE0  
Defines the speed of Endpoint 0  
HOST_TXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Transmit endpoint.  
(Index register set to select Endpoints 1-4)  
HOST_NAKLIMIT0  
Sets the NAK response timeout on Endpoint 0.  
(Index register set to select Endpoint 0)  
HOST_TXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Transmit endpoint. (Index register set to  
select Endpoints 1-4)  
41Ch  
41Dh  
41Fh  
HOST_RXTYPE  
HOST_RXINTERVAL  
CONFIGDATA  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Receive endpoint.  
(Index register set to select Endpoints 1-4)  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Receive endpoint. (Index register set to select  
Endpoints 1-4)  
Returns details of core configuration. (Index register set to select Endpoint 0)  
FIFOn  
420h  
424h  
428h  
42Ch  
430h  
FIFO0  
FIFO1  
FIFO2  
FIFO3  
FIFO4  
Transmit and Receive FIFO Register for Endpoint 0  
Transmit and Receive FIFO Register for Endpoint 1  
Transmit and Receive FIFO Register for Endpoint 2  
Transmit and Receive FIFO Register for Endpoint 3  
Transmit and Receive FIFO Register for Endpoint 4  
OTG Device Control  
460h  
DEVCTL  
OTG Device Control Register  
Dynamic FIFO Control  
462h  
463h  
464h  
466h  
TXFIFOSZ  
Transmit Endpoint FIFO Size  
(Index register set to select Endpoints 1-4)  
RXFIFOSZ  
Receive Endpoint FIFO Size  
(Index register set to select Endpoints 1-4)  
TXFIFOADDR  
RXFIFOADDR  
Transmit Endpoint FIFO Address  
(Index register set to select Endpoints 1-4)  
Receive Endpoint FIFO Address  
(Index register set to select Endpoints 1-4)  
Target Endpoint 0 Control Registers, Valid Only in Host Mode  
480h  
482h  
TXFUNCADDR  
TXHUBADDR  
Address of the target function that has to be accessed through the associated  
Transmit Endpoint.  
Address of the hub that has to be accessed through the associated Transmit  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
483h  
484h  
TXHUBPORT  
Port of the hub that has to be accessed through the associated Transmit Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
RXFUNCADDR  
Address of the target function that has to be accessed through the associated  
Receive Endpoint.  
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Table 6-56. Universal Serial Bus (USB) Registers (continued)  
Offset  
Acronym  
Register Description  
486h  
RXHUBADDR  
Address of the hub that has to be accessed through the associated Receive  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
487h  
RXHUBPORT  
Port of the hub that has to be accessed through the associated Receive Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
Target Endpoint 1 Control Registers, Valid Only in Host Mode  
488h  
48Ah  
TXFUNCADDR  
TXHUBADDR  
Address of the target function that has to be accessed through the associated  
Transmit Endpoint.  
Address of the hub that has to be accessed through the associated Transmit  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
48Bh  
TXHUBPORT  
Port of the hub that has to be accessed through the associated Transmit Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
48Ch  
48Eh  
RXFUNCADDR  
RXHUBADDR  
Address of the target function that has to be accessed through the associated  
Receive Endpoint.  
Address of the hub that has to be accessed through the associated Receive  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
48Fh  
RXHUBPORT  
Port of the hub that has to be accessed through the associated Receive Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
Target Endpoint 2 Control Registers, Valid Only in Host Mode  
490h  
492h  
TXFUNCADDR  
TXHUBADDR  
Address of the target function that has to be accessed through the associated  
Transmit Endpoint.  
Address of the hub that has to be accessed through the associated Transmit  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
493h  
TXHUBPORT  
Port of the hub that has to be accessed through the associated Transmit Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
494h  
496h  
RXFUNCADDR  
RXHUBADDR  
Address of the target function that has to be accessed through the associated  
Receive Endpoint.  
Address of the hub that has to be accessed through the associated Receive  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
497h  
RXHUBPORT  
Port of the hub that has to be accessed through the associated Receive Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
Target Endpoint 3 Control Registers, Valid Only in Host Mode  
498h  
49Ah  
TXFUNCADDR  
TXHUBADDR  
Address of the target function that has to be accessed through the associated  
Transmit Endpoint.  
Address of the hub that has to be accessed through the associated Transmit  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
49Bh  
TXHUBPORT  
Port of the hub that has to be accessed through the associated Transmit Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
49Ch  
49Eh  
RXFUNCADDR  
RXHUBADDR  
Address of the target function that has to be accessed through the associated  
Receive Endpoint.  
Address of the hub that has to be accessed through the associated Receive  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
49Fh  
RXHUBPORT  
Port of the hub that has to be accessed through the associated Receive Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
Target Endpoint 4 Control Registers, Valid Only in Host Mode  
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Table 6-56. Universal Serial Bus (USB) Registers (continued)  
Offset  
Acronym  
Register Description  
4A0h  
TXFUNCADDR  
Address of the target function that has to be accessed through the associated  
Transmit Endpoint.  
4A2h  
4A3h  
TXHUBADDR  
TXHUBPORT  
Address of the hub that has to be accessed through the associated Transmit  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
Port of the hub that has to be accessed through the associated Transmit Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
4A4h  
4A6h  
RXFUNCADDR  
RXHUBADDR  
Address of the target function that has to be accessed through the associated  
Receive Endpoint.  
Address of the hub that has to be accessed through the associated Receive  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
4A7h  
RXHUBPORT  
Port of the hub that has to be accessed through the associated Receive Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
Control and Status Register for Endpoint 0  
Control Status Register for Endpoint 0 in Peripheral Mode  
Control Status Register for Endpoint 0 in Host Mode  
Number of Received Bytes in Endpoint 0 FIFO  
Defines the Speed of Endpoint 0  
502h  
PERI_CSR0  
HOST_CSR0  
COUNT0  
508h  
50Ah  
50Bh  
50Fh  
HOST_TYPE0  
HOST_NAKLIMIT0  
CONFIGDATA  
Sets the NAK Response Timeout on Endpoint 0  
Returns details of core configuration.  
Control and Status Register for Endpoint 1  
Maximum Packet Size for Peripheral/Host Transmit Endpoint  
510h  
512h  
TXMAXP  
PERI_TXCSR  
Control Status Register for Peripheral Transmit Endpoint  
(peripheral mode)  
HOST_TXCSR  
Control Status Register for Host Transmit Endpoint  
(host mode)  
514h  
516h  
RXMAXP  
Maximum Packet Size for Peripheral/Host Receive Endpoint  
PERI_RXCSR  
Control Status Register for Peripheral Receive Endpoint  
(peripheral mode)  
HOST_RXCSR  
Control Status Register for Host Receive Endpoint  
(host mode)  
518h  
51Ah  
RXCOUNT  
Number of Bytes in Host Receive endpoint FIFO  
HOST_TXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Transmit endpoint.  
51Bh  
51Ch  
51Dh  
HOST_TXINTERVAL  
HOST_RXTYPE  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Transmit endpoint.  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Receive endpoint.  
HOST_RXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Receive endpoint.  
Control and Status Register for Endpoint 2  
520h  
522h  
TXMAXP  
Maximum Packet Size for Peripheral/Host Transmit Endpoint  
PERI_TXCSR  
Control Status Register for Peripheral Transmit Endpoint  
(peripheral mode)  
HOST_TXCSR  
Control Status Register for Host Transmit Endpoint  
(host mode)  
524h  
526h  
RXMAXP  
Maximum Packet Size for Peripheral/Host Receive Endpoint  
PERI_RXCSR  
Control Status Register for Peripheral Receive Endpoint  
(peripheral mode)  
HOST_RXCSR  
Control Status Register for Host Receive Endpoint  
(host mode)  
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Table 6-56. Universal Serial Bus (USB) Registers (continued)  
Offset  
528h  
Acronym  
Register Description  
RXCOUNT  
Number of Bytes in Host Receive endpoint FIFO  
52Ah  
HOST_TXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Transmit endpoint.  
52Bh  
52Ch  
52Dh  
HOST_TXINTERVAL  
HOST_RXTYPE  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Transmit endpoint.  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Receive endpoint.  
HOST_RXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Receive endpoint.  
Control and Status Register for Endpoint 3  
530h  
532h  
TXMAXP  
Maximum Packet Size for Peripheral/Host Transmit Endpoint  
PERI_TXCSR  
Control Status Register for Peripheral Transmit Endpoint  
(peripheral mode)  
HOST_TXCSR  
Control Status Register for Host Transmit Endpoint  
(host mode)  
534h  
536h  
RXMAXP  
Maximum Packet Size for Peripheral/Host Receive Endpoint  
PERI_RXCSR  
Control Status Register for Peripheral Receive Endpoint  
(peripheral mode)  
HOST_RXCSR  
Control Status Register for Host Receive Endpoint  
(host mode)  
538h  
53Ah  
RXCOUNT  
Number of Bytes in Host Receive endpoint FIFO  
HOST_TXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Transmit endpoint.  
53Bh  
53Ch  
53Dh  
HOST_TXINTERVAL  
HOST_RXTYPE  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Transmit endpoint.  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Receive endpoint.  
HOST_RXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Receive endpoint.  
Control and Status Register for Endpoint 4  
540h  
542h  
TXMAXP  
Maximum Packet Size for Peripheral/Host Transmit Endpoint  
PERI_TXCSR  
Control Status Register for Peripheral Transmit Endpoint  
(peripheral mode)  
HOST_TXCSR  
Control Status Register for Host Transmit Endpoint  
(host mode)  
544h  
546h  
RXMAXP  
Maximum Packet Size for Peripheral/Host Receive Endpoint  
PERI_RXCSR  
Control Status Register for Peripheral Receive Endpoint  
(peripheral mode)  
HOST_RXCSR  
Control Status Register for Host Receive Endpoint  
(host mode)  
548h  
54Ah  
RXCOUNT  
Number of Bytes in Host Receive endpoint FIFO  
HOST_TXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Transmit endpoint.  
54Bh  
54Ch  
54Dh  
HOST_TXINTERVAL  
HOST_RXTYPE  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Transmit endpoint.  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Receive endpoint.  
HOST_RXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Receive endpoint.  
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6.13.2 USB2.0 Electrical Data/Timing  
Table 6-57. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see  
Figure 6-41)  
DEVICE  
LOW SPEED  
1.5 Mbps  
FULL SPEED  
12 Mbps  
HIGH SPEED(1)  
480 Mbps  
NO.  
PARAMETER  
UNIT  
MIN  
75  
MAX  
MIN  
4
MAX  
MIN  
0.5  
0.5  
-
MAX  
1
2
3
4
5
tr(D)  
Rise time, USB_DP and USB_DM signals(2)  
Fall time, USB_DP and USB_DM signals(2)  
Rise/Fall time, matching(3)  
Output signal cross-over voltage(2)  
Source (Host) Driver jitter, next transition  
Function Driver jitter, next transition  
Source (Host) Driver jitter, paired transition(4)  
Function Driver jitter, paired transition  
Pulse duration, EOP transmitter  
Pulse duration, EOP receiver  
300  
300  
125  
2
20  
20  
20  
20  
-
ns  
ns  
%
tf(D)  
75  
4
tfrfm  
80  
90 111.11  
VCRS  
1.3  
1.3  
2
2
-
-
V
tjr(source)NT  
tjr(FUNC)NT  
tjr(source)PT  
tjr(FUNC)PT  
tw(EOPT)  
tw(EOPR)  
t(DRATE)  
2
ns  
ns  
ns  
ns  
ns  
ns  
25  
2
6
1
1
10  
1
7
8
9
1250  
670  
1500  
160  
82  
175  
-
-
-
Data Rate  
1.5  
-
12  
480 Mb/s  
49.5  
10 ZDRV  
Driver Output Resistance  
-
28  
49.5  
40.5  
Ω
(1) For more detailed specification information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7.  
(2) Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF  
(3) tfrfm = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]  
(4) tjr = tpx(1) - tpx(0)  
t
t
per − jr  
USB_DM  
V
90% V  
OH  
CRS  
10% V  
OL  
USB_DP  
t
f
t
r
Figure 6-41. USB2.0 Integrated Transceiver Interface Timing  
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6.14 Universal Asynchronous Receiver/Transmitter (UART)  
The UART module performs serial-to-parallel conversion on data received from a peripheral device or  
modem, and parallel-to-serial conversion on data received from the CPU. Each UART also includes a  
programmable baud rate generator capable of dividing the module's reference clock by divisors from 1 to  
65,535 to produce a 16 x clock driving the internal logic. The UART modules support the following  
features:  
•
•
•
•
•
•
•
Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates  
16-byte storage space for both the transmitter and receiver FIFOs  
Unique interrupts, one for each UART  
Unique EDMA events, both received and transmitted data for each UART  
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA  
Programmable auto-rts and auto-cts for autoflow control (supported on UART1)  
Programmable serial data formats  
–
–
–
5, 6, 7, or 8-bit characters  
Even, odd, or no parity bit generation and detection  
1, 1.5, or 2 stop bit generation  
•
•
•
False start bit detection  
Line break generation and detection  
Internal diagnostic capabilities  
–
–
Loopback controls for communications link fault isolation  
Break, parity, overrun, and framing error simulation  
•
Modem control functions: CTS, RTS (supported on UART1)  
6.14.1 UART Peripheral Register Description(s)  
Table 6-58 lists the UART registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-58. UART Registers  
OFFSET  
0h  
ACRONYM  
REGISTER DESCRIPTION  
Receiver Buffer Register (read only)  
Transmitter Holding Register (write only)  
Interrupt Enable Register  
RBR  
0h  
THR  
4h  
IER  
8h  
IIR  
Interrupt Identification Register (read only)  
FIFO Control Register (write only)  
Line Control Register  
8h  
FCR  
Ch  
LCR  
10h  
14h  
20h  
24h  
28h  
30h  
34h  
MCR  
Modem Control Register  
LSR  
Line Status Register  
DLL  
Divisor LSB Latch  
DLH  
Divisor MSB Latch  
PID  
Peripheral Identification Register  
Power and Emulation Management Register  
Mode Definition Register  
PWREMU_MGMT  
MDR  
6.14.2 UART Electrical Data/Timing  
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UNIT  
Table 6-59. Timing Requirements for UARTx Receive (see Figure 6-42)(1)  
DEVICE  
MIN  
NO.  
MAX  
4
5
tw(URXDB)  
tw(URXSB)  
Pulse duration, receive data bit (RXDn)  
Pulse duration, receive start bit  
.96U  
1.05U  
1.05U  
ns  
ns  
.96U  
(1) U = UART baud time = 1/programmed baud rate.  
Table 6-60. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit  
(see Figure 6-42)(1)  
DEVICE  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
5
UART0 Maximum programmable baud rate  
UART1 Maximum programmable baud rate  
Pulse duration, transmit data bit (TXDn)  
Pulse duration, transmit start bit  
1
f(baud)  
MHz  
5
2
3
tw(UTXDB)  
tw(UTXSB)  
U - 2  
U - 2  
U + 2  
U + 2  
ns  
ns  
(1) U = UART baud time = 1/programmed baud rate.  
3
2
Start  
Bit  
UART_TXDn  
Data Bits  
5
4
Start  
Bit  
UART_RXDn  
Data Bits  
Figure 6-42. UART Transmit/Receive Timing  
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6.15 Serial Port Interface (SPI)  
The SPI module provides a programmable length shift register which allows serial communication with  
other SPI devices through a 3 or 4 wire interface (Clock, Data In, Data Out, and Chip-select). The SPI  
supports the following features:  
•
Master and Slave mode operation is supported on all SPI ports (master mode means that the device  
provides the serial clock)  
•
•
•
•
•
•
•
•
•
•
•
2 chip selects for interfacing to multiple slave SPI devices.  
3 or 4 wire interface (Clock, Data In, Data Out, and Enable)  
Unique interrupt for each SPI port (except SPI4)  
Separate EDMA events for SPI Receive and Transmit for each SPI port (except SPI4)  
16-bit shift register  
Receive buffer register  
Programmable character length (2 to 16 bits)  
Programmable SPI clock frequency range  
8-bit clock prescaler  
Programmable clock phase (delay or no delay)  
Programmable clock polarity  
Note: SPI4 slave mode does not support Chip-select input, only supports 3-wire interface.  
The SPI modules do not support the following features:  
•
GPIO mode. GPIO functionality is supported by the GIO modules for those SPI pins that are  
multiplexed with GPIO signals.  
6.15.1 SPI Peripheral Register Description(s)  
Table 6-61 lists the SPI registers, their corresponding acronyms, and the device memory locations  
(offsets). These offsets apply to all device SPI modules.  
Table 6-61. SPI Registers  
OFFSET  
00h  
ACRONYM  
SPIGCR0  
SPIGCR1  
SPIINT  
REGISTER DESCRIPTION  
SPI global control register 0  
SPI global control register 1  
SPI interrupt register  
SPI interrupt level register  
SPI flag register  
04h  
08h  
0Ch  
SPILVL  
SPIFLG  
SPIPC0  
-
10h  
14h  
SPI pin control register  
Reserved  
18h  
1Ch  
SPIPC2  
-
SPI pin control register 2  
Reserved  
20h - 38h  
3Ch  
SPIDAT1  
SPIBUF  
SPIEMU  
SPIDELAY  
SPIDEF  
SPIFMT0  
INTVECT0  
INTVECT1  
SPI shift register  
40h  
SPI buffer register  
44h  
SPI emulation register  
SPI delay register  
48h  
4Ch  
SPI default chip select register  
SPI data format register 0  
SPI interrupt vector register 0  
SPI interrupt vector register 1  
50h-5Ch  
60h  
64h  
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6.15.2 SPI Electrical Data/Timing  
Master Mode — General  
Table 6-62. General Switching Characteristics in Master Mode(1)  
NO.  
PARAMETER  
MIN  
MAX UNIT  
greater of 2P  
or 25  
1
tc(CLK)  
Cycle time, SPI_SCLK  
256P  
ns  
ns  
ns  
.5(tc(CLK)) -  
1.25  
2
3
tw(CLKH)  
tw(CLKL)  
Pulse width, SPI_SCLK high  
Pulse width, SPI_SCLK low  
.5(tc(CLK)) -  
1.25  
Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK  
rising edge, 3-/4-pin mode,  
polarity = 0, phase = 0  
6.5  
.5tc(CLK) + 6.5  
6.5  
Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK  
rising edge, 3-/4-pin mode,  
polarity = 0, phase = 1  
4
5
6
tosu(SIMO-CLK)  
td(CLK-SIMO)  
toh(CLK-SIMO)  
ns  
ns  
ns  
Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK  
falling edge, 3-/4-pin mode,  
polarity = 1, phase = 0  
Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK  
falling edge, 3-/4-pin mode,  
polarity = 1, phase = 1  
.5tc(CLK) + 6.5  
Delay time, SPI_SCLK transmit rising edge to SPI_SIMO output  
valid (subsequent bit driven), 3-/4-pin mode, polarity = 0, phase = 0  
-3  
-3  
-3  
-3  
6
6
6
6
Delay time, SPI_SCLK transmit falling edge to SPI_SIMO output  
valid (subsequent bit driven), 3-/4-pin mode, polarity = 0, phase = 1  
Delay time, SPI_SCLK transmit falling edge to SPI_SIMO output  
valid (subsequent bit driven), 3-/4-pin mode, polarity = 1, phase = 0  
Delay time, SPI_SCLK transmit rising edge to SPI_SIMO output  
valid (subsequent bit driven), 3-/4-pin mode, polarity = 1, phase = 1  
Output hold time, SPI_SIMO valid (except final bit) after receive  
falling edge of SPI_SCLK,  
3-/4-pin mode, polarity = 0, phase = 0  
9.5  
9.5  
9.5  
9.5  
Output hold time, SPI_SIMO valid (except final bit) after receive  
rising edge of SPI_SCLK,  
3-/4-pin mode, polarity = 0, phase = 1  
Output hold time, SPI_SIMO valid (except final bit) after receive  
rising edge of SPI_SCLK,  
3-/4-pin mode, polarity = 1, phase = 0  
Output hold time, SPI_SIMO valid (except final bit) after receive  
falling edge of SPI_SCLK,  
3-/4-pin mode, polarity = 1, phase = 1  
(1) T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI  
core clock (OSCIN).  
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Table 6-63. General Input Timing Requirements in Master Mode  
MIN  
MAX UNIT  
Setup time, SPI_SOMI valid before receive falling edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 0, phase = 0  
4
4
4
4
Setup time, SPI_SOMI valid before receive rising edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 0, phase = 1  
7
tsu(SOMI-CLK)  
ns  
Setup time, SPI_SOMI valid before receive rising edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 1, phase = 0  
Setup time, SPI_SOMI valid before receive falling edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 1, phase = 1  
Hold time, SPI_SOMI valid after receive falling edge of SPI_SCLK,  
3-/4-pin mode, polarity = 0, phase = 0  
4
4
4
4
Hold time, SPI_SOMI valid after receive rising edge of SPI_SCLK,  
3-/4-pin mode, polarity = 0, phase = 1  
8
th(CLK-SOMI)  
ns  
Hold time, SPI_SOMI valid after receive rising edge of SPI_SCLK,  
3-/4-pin mode, polarity = 1, phase = 0  
Hold time, SPI_SOMI valid after receive falling edge of SPI_SCLK,  
3-/4-pin mode, polarity = 1, phase = 1  
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Slave Mode — General  
Table 6-64. General Switching Characteristics in Slave Mode (For 3-/4-Pin Modes)(1)  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, transmit rising edge of SPI_SCLK to SPI_SOMI output  
valid, 3-/4-pin mode, polarity = 0, phase = 0  
2
16.5  
Delay time, transmit falling edge of SPI_SCLK to SPI_SOMI output  
valid, 3-/4-pin mode, polarity = 0, phase = 1  
2
2
2
4
4
4
4
16.5  
ns  
13  
td(CLK-SOMI)  
Delay time, transmit falling edge of SPI_SCLK to SPI_SOMI output  
valid, 3-/4-pin mode, polarity = 1, phase = 0  
16.5  
Delay time, transmit rising edge of SPI_SCLK to SPI_SOMI output  
valid, 3-/4-pin mode, polarity = 1, phase = 1  
16.5  
Output hold time, SPI_SOMI valid (except final bit) after receive  
falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 0  
Output hold time, SPI_SOMI valid (except final bit) after receive  
rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 1  
14  
toh(CLK-SOMI)  
ns  
Output hold time, SPI_SOMI valid (except final bit) after receive  
rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 0  
Output hold time, SPI_SOMI valid (except final bit) after receive  
falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 1  
(1) T = period of SPI_SCLK  
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Table 6-65. General Input Timing Requirements in Slave Mode(1)  
NO.  
MIN  
MAX UNIT  
greater of 2P  
or 25  
9
tc(CLK)  
Cycle time, SPI_SCLK  
256P  
ns  
ns  
ns  
.5(tc(CLK)) -  
1.25  
10  
11  
tw(CLKH)  
tw(CLKL)  
Pulse width, SPI_SCLK high  
Pulse width, SPI_SCLK low  
.5(tc(CLK)) -  
1.25  
Setup time, SPI_SIMO data valid before receive falling edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 0, phase = 0  
4
4
4
4
4
4
4
4
Setup time, SPI_SIMO data valid before receive rising edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 0, phase = 1  
15  
tsu(SIMO-CLK)  
ns  
Setup time, SPI_SIMO data valid before receive rising edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 1, phase = 0  
Setup time, SPI_SIMO data valid before receive falling edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 1, phase = 1  
Hold time, SPI_SIMO data valid after receive falling edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 0, phase = 0  
Hold time, SPI_SIMO data valid after receive rising edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 0, phase = 1  
16  
th(CLK-SIMO)  
ns  
Hold time, SPI_SIMO data valid after receive rising edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 1, phase = 0  
Hold time, SPI_SIMO data valid after receive falling edge of  
SPI_SCLK, 3-/4-pin mode,  
polarity = 1, phase = 1  
(1) T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI  
core clock (OSCIN).  
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Master Mode — Additional  
Table 6-66. Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Master Mode  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Output setup time, SPI_SCS[n] active before first  
SPI_SCLK rising edge, polarity = 0, phase = 0,  
SPIDELAY.C2TDELAY = 0  
(C2TDELAY+2)*P+6  
.5  
Output setup time, SPI_SCS[n] active before first  
SPI_SCLK rising edge, polarity = 0, phase = 1,  
SPIDELAY.C2TDELAY = 0  
(C2TDELAY+2)*P +  
.5tc + 6.5  
(1)  
19  
tosu(CS-CLK)  
ns  
Output setup time, SPI_SCS[n] active before first  
SPI_SCLK falling edge, polarity = 1, phase = 0,  
SPIDELAY.C2TDELAY = 0  
(C2TDELAY+2)*P +  
6.5  
Output setup time, SPI_SCS[n] active before first  
SPI_SCLK falling edge, polarity = 1, phase = 1,  
SPIDELAY.C2TDELAY = 0  
(C2TDELAY+2)*P +  
.5tc + 6.5  
Delay time, final SPI_SCLK falling edge to master  
deasserting SPI_SCS[n], polarity = 0, phase = 0,  
SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD  
not enabled  
(T2CDELAY+1)*P -  
3
Delay time, final SPI_SCLK falling edge to master  
deasserting SPI_SCS[n], polarity = 0, phase = 1,  
SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD  
not enabled  
(T2CDELAY+1)*P -  
3
20  
td(CLK-CS)  
ns  
Delay time, final SPI_SCLK rising edge to master  
deasserting SPI_SCS[n], polarity = 1, phase = 0,  
SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD  
not enabled  
(T2CDELAY+1)*P -  
3
Delay time, final SPI_SCLK rising edge to master  
deasserting SPI_SCS[n], polarity = 1, phase = 1,  
SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD  
not enabled  
(T2CDELAY+1)*P -  
3
(1) The Master SPI is ready with new data before SPI_SCS[n] assertion.  
Slave Mode — Additional  
Table 6-67. Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Slave Mode(1)  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, master asserting SPI_SCS[n] to slave driving  
SPI_SOMI data valid  
27  
td(CSL-SOMI)  
2P + 16.5  
2P + 16.5  
ns  
ns  
Disable time, master deasserting SPI_SCS[n] to slave driving  
SPI_SOMI high impedance  
28  
tdis(CSH-SOMI)  
(1) T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI  
core clock (OSCIN).  
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Table 6-68. Additional Input Timing Requirements of 4-Pin Chip-Select Option in Slave Mode(1)  
NO.  
MIN  
MAX UNIT  
Setup time, SPI_SCS[n] asserted at slave to first SPI_SCLK edge  
(rising or falling) at slave  
25  
tsu(CSL-CLK)  
2P + 25  
ns  
Delay time, final falling edge SPI_SCLK to SPI_SCS[n]  
deasserted, polarity = 0, phase = 0  
.5(tc(CLK)) + 2P - 4  
2P - 4  
Delay time, final falling edge SPI_SCLK to SPI_SCS[n]  
deasserted, polarity = 0, phase = 1  
26  
td(CLK-CSH)  
ns  
Delay time, final rising edge SPI_SCLK to SPI_SCS[n] deasserted,  
polarity = 1, phase = 0  
.5(tc(CLK)) + 2P - 4  
2P - 4  
Delay time, final rising edge SPI_SCLK to SPI_SCS[n] deasserted,  
polarity = 1, phase = 1  
(1) T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI  
core clock (OSCIN).  
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MASTER MODE  
POLARITY = 0 PHASE = 0  
1
2
3
SPI_CLK  
SPI_SIMO  
SPI_SOMI  
5
4
6
MO(0)  
MO(1)  
MO(n-1)  
MI(n-1)  
MO(n)  
MI(n)  
7
8
MI(0)  
MI(1)  
MASTER MODE  
POLARITY = 0 PHASE = 1  
4
SPI_CLK  
SPI_SIMO  
SPI_SOMI  
5
6
MO(0)  
MO(1)  
MI(1)  
MO(n-1)  
MI(n-1)  
MO(n)  
MI(n)  
7
8
MI(0)  
MASTER MODE  
POLARITY = 1 PHASE = 0  
4
SPI_CLK  
SPI_SIMO  
SPI_SOMI  
5
6
MO(0)  
MO(1)  
MI(1)  
MO(n-1)  
MI(n-1)  
MO(n)  
MI(n)  
7
8
MI(0)  
MASTER MODE  
POLARITY = 1 PHASE = 1  
SPI_CLK  
SPI_SIMO  
SPI_SOMI  
6
4
5
MO(0)  
MO(1)  
MI(1)  
MO(n-1)  
MI(n-1)  
MO(n)  
MI(n)  
7
8
MI(0)  
Figure 6-43. SPI Timings—Master Mode  
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SLAVE MODE  
POLARITY = 0 PHASE = 0  
9
10  
11  
16  
SPI_CLK  
SPI_SIMO  
SPI_SOMI  
15  
SI(0)  
SI(1)  
SI(n-1)  
SI(n)  
13  
SO(1)  
14  
SO(0)  
SO(n-1)  
SO(n)  
SLAVE MODE  
POLARITY = 0 PHASE = 1  
SPI_CLK  
SPI_SIMO  
SPI_SOMI  
15  
16  
SI(0)  
SI(n-1)  
SI(n)  
SI(1)  
13  
14  
SO(0)  
SO(1)  
SO(n-1)  
SO(n)  
SLAVE MODE  
POLARITY = 1 PHASE = 0  
SPI_CLK  
SPI_SIMO  
SPI_SOMI  
15  
16  
SI(0)  
SI(1)  
SI(n-1)  
SI(n)  
13  
SO(1)  
14  
SO(0)  
SO(n-1)  
SO(n)  
SLAVE MODE  
POLARITY = 1 PHASE = 1  
SPI_CLK  
SPI_SIMO  
SPI_SOMI  
15  
16  
SI(0)  
SI(n-1)  
SI(n)  
SI(1)  
13  
14  
SO(0)  
SO(1)  
SO(n-1)  
SO(n)  
A. The first bit of transmit data becomes valid on the SPI_SOMI pin when software writes to the SPIDAT1 register. For  
more details, see the TMS320DM36x DMSoC Serial Peripheral Interface User's Guide (literature number SPRUFH1).  
Figure 6-44. SPI Timings—Slave Mode  
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MASTER MODE 4 PIN WITH CHIP SELECT  
19  
20  
SPI_CLK  
MO(0)  
MO(1)  
MI(1)  
MO(n-1)  
MI(n-1)  
MO(n)  
MI(n)  
SPI_SIMO  
MI(0)  
SPI_SOMI  
SPI_SCS[n]  
Figure 6-45. SPI Timings—Master Mode (4-Pin)  
SLAVE MODE 4 PIN WITH CHIP SELECT  
25  
26  
SPI_CLK  
28  
27  
SO(n-1)  
SI(n-1)  
SPI_SOMI  
SPI_SIMO  
SPI_SCS[n]  
SO(0)  
SI(0)  
SO(1)  
SI(1)  
SO(n)  
SI(n)  
Figure 6-46. SPI Timings—Slave Mode (4-Pin)  
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6.16 Inter-Integrated Circuit (I2C)  
The inter-integrated circuit (I2C) module provides an interface between the DM365 and other devices  
compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by  
way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit  
data to/from the device through the I2C module.  
The I2C port supports:  
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)  
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)  
Noise Filter to Remove Noise 50 ns or less  
Seven- and Ten-Bit Device Addressing Modes  
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality  
Events: DMA, Interrupt, or Polling  
For more detailed information on the I2C peripheral, see the Documentation Support section for the device  
Inter-Integrated Circuit (I2C) Module Reference Guide.  
6.16.1 I2C Peripheral Register Description(s)  
Table 6-69 lists the I2C registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-69. Inter-Integrated Circuit (I2C) Registers  
Offset  
0h  
Acronym  
ICOAR  
Register Description  
I2C Own Address Register  
I2C Interrupt Mask Register  
I2C Interrupt Status Register  
I2C Clock Low-Time Divider Register  
I2C Clock High-Time Divider Register  
I2C Data Count Register  
I2C Data Receive Register  
I2C Slave Address Register  
I2C Data Transmit Register  
I2C Mode Register  
4h  
ICIMR  
8h  
ICSTR  
Ch  
ICCLKL  
ICCLKH  
ICCNT  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
2Ch  
30h  
34h  
38h  
48h  
4ch  
50h  
54h  
58h  
5ch  
ICDRR  
ICSAR  
ICDXR  
ICMDR  
ICIVR  
I2C Interrupt Vector Register  
I2C Extended Mode Register  
I2C Prescaler Register  
ICEMDR  
ICPSC  
REVID1  
REVID2  
ICPFUNC  
ICPDIR  
ICPDIN  
ICPDOUT  
ICPDSET  
ICPDCLR  
I2C Revision ID Register 1  
I2C Revision ID Register 2  
I2C Pin Function Register  
I2C Pin Direction Register  
I2C Pin Data In Register  
I2C Pin Data Out Register  
I2C Pin Data Set Register  
I2C Pin Data Clear register  
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6.16.2 I2C Electrical Data/Timing  
6.16.2.1 Inter-Integrated Circuits (I2C) Timing  
Table 6-70. Timing Requirements for I2C Timings(1) (see Figure 6-47)  
DEVICE  
STANDARD  
MODE  
FAST  
MODE  
NO.  
UNIT  
MIN MAX MIN MAX  
1
2
tc(SCL)  
Cycle time, SCL  
10  
2.5  
0.6  
ms  
ms  
tsu(SCLH-SDAL)  
Setup time, SCL high before SDA low (for a repeated START condition)  
4.7  
Hold time, SCL low after SDA low (for a START and a repeated START  
condition)  
3
th(SCLL-SDAL)  
4
0.6  
ms  
4
5
6
7
8
tw(SCLL)  
Pulse duration, SCL low  
4.7  
4
1.3  
0.6  
100  
0
ms  
ms  
ns  
ms  
ms  
tw(SCLH)  
Pulse duration, SCL high  
tsu(SDAV-SCLH)  
th(SDA-SCLL)  
tw(SDAH)  
Setup time, SDA valid before SCL high  
Hold time, SDA valid after SCL low (For I2C bus™ devices)  
Pulse duration, SDA high between STOP and START conditions  
250  
0
3.45  
0.9  
4.7  
1.3  
20 +  
9
tr(SDA)  
tr(SCL)  
tf(SDA)  
tf(SCL)  
Rise time, SDA  
Rise time, SCL  
Fall time, SDA  
Fall time, SCL  
1000 0.1C  
300  
300  
300  
300  
ns  
ns  
ns  
ns  
(1)  
b
20 +  
10  
11  
12  
1000 0.1C  
(1)  
b
20 +  
300 0.1C  
(1)  
b
20 +  
300 0.1C  
(1)  
b
13  
14  
15  
tsu(SCLH-SDAH)  
tw(SP)  
Setup time, SCL high before SDA high (for STOP condition)  
Pulse duration, spike (must be suppressed)  
Capacitive load for each bus line  
4
0.6  
ms  
ns  
pF  
50  
(2)  
Cb  
400  
400  
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered  
down.  
(2) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.  
11  
9
SDA  
SCL  
6
8
14  
4
13  
5
10  
1
12  
3
2
7
3
Stop  
Start  
Repeated  
Start  
Stop  
Figure 6-47. I2C Receive Timings  
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Table 6-71. Switching Characteristics for I2C Timings(1) (see Figure 6-48)  
DEVICE  
STANDARD  
MODE  
MIN MAX MIN  
NO.  
PARAMETER  
FAST MODE UNIT  
MAX  
16  
17  
tc(SCL)  
Cycle time, SCL  
10  
2.5  
0.6  
ms  
ms  
td(SCLH-SDAL)  
Delay time, SCL high to SDA low (for a repeated START condition)  
4.7  
Delay time, SDA low to SCL low (for a START and a repeated  
START condition)  
18  
td(SDAL-SCLL)  
4
0.6  
ms  
19  
20  
21  
22  
23  
28  
29  
tw(SCLL)  
Pulse duration, SCL low  
4.7  
4
1.3  
0.6  
100  
0
ms  
ms  
ns  
ms  
ms  
ms  
pF  
tw(SCLH)  
Pulse duration, SCL high  
td(SDAV-SCLH)  
tv(SCLL-SDAV)  
tw(SDAH)  
Delay time, SDA valid to SCL high  
250  
0
Valid time, SDA valid after SCL low (For I2C devices)  
Pulse duration, SDA high between STOP and START conditions  
Delay time, SCL high to SDA high (for STOP condition)  
Capacitance for each I2C pin  
0.9  
10  
4.7  
4
1.3  
0.6  
td(SCLH-SDAH)  
Cp  
10  
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.  
CAUTION  
The I2C pins use a standard ±4-mA LVCMOS buffer, not the slow I/OP buffer defined in  
the I2C specification. Series resistors may be necessary to reduce noise at the system  
level.  
SDA  
SCL  
21  
23  
19  
28  
20  
16  
18  
17  
22  
18  
Stop  
Start  
Repeated  
Start  
Stop  
Figure 6-48. I2C Transmit Timings  
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6.17 Multi-Channel Buffered Serial Port (McBSP)  
The primary use for the Multi-Channel Buffered Serial Port (McBSP) is for audio interface purposes. The  
primary audio modes that are supported by the McBSP are the AC97 and IIS modes. In addition to the  
primary audio modes, the McBSP supports general serial port receive and transmit operation, but is not  
intended to be used as a high-speed interface. The McBSP supports the following features:  
•
•
•
•
•
•
•
Full-duplex communication  
Double-buffered data registers, which allow a continuous data stream  
Independent framing and clocking for receive and transmit  
External shift clock generation or an internal programmable frequency shift clock  
Double-buffered data registers, which allow a continuous data stream  
Independent framing and clocking for receive and transmit  
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially  
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices  
•
Direct interface to AC97 compliant devices (the necessary multiphase frame synchronization capability  
is provided)  
•
•
•
•
•
•
•
•
•
Direct interface to IIS compliant devices  
Direct interface to SPI protocol in master mode only  
A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits  
m-Law and A-Law companding  
8-bit data transfers with the option of LSB or MSB first  
Programmable polarity for both frame synchronization and data clocks  
Highly programmable internal clock and frame generation  
Direct interface to T1/E1 Framers  
Multi-channel transmit and receive of up to 128 channels  
For more detailed information on the McBSP peripheral, see the Documentation Support section for the  
Multi-Channel Buffered Serial Port (McBSP) Reference Guide.  
6.17.1 McBSP Peripheral Register Description(s)  
Table 6-72 lists the McBSP registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-72. McBSP Registers  
Offset  
-
Acronym  
RBR(1)  
RSR(1)  
XSR(1)  
DRR(2) (3)  
DXR(3)  
SPCR  
RCR  
Register Name  
Receive buffer register  
Receive shift register  
-
-
Transmit shift register  
Data receive register  
00h  
04h  
08h  
0Ch  
10h  
14h  
18h  
Data transmit register  
Serial port control register  
Receive control register  
Transmit control register  
Sample rate generator register  
Multichannel Control Register  
XCR  
SRGR  
MCR  
Enhanced Receive Channel Enable Register  
0 Partition A/B  
1Ch  
RCERE0  
(1) The RBR, RSR, and XSR are not directly accessible via the CPUs or the EDMA controller.  
(2) The CPUs and EDMA controller can only read this register; they cannot write to it.  
(3) The DRR and DXR are accessible via the CPUs or the EDMA controller.  
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Table 6-72. McBSP Registers (continued)  
Offset  
20h  
Acronym  
XCERE0  
PCR  
Register Name  
Enhanced Transmit Channel Enable Register  
0 Partition A/B  
24h  
Pin control register  
Enhanced Receive Channel Enable Register  
1 Partition C/D  
28h  
RCERE1  
Enhanced Transmit Channel Enable Register  
1 Partition C/D  
2Ch  
30h  
34h  
38h  
3Ch  
XCERE1  
RCERE2  
XCERE2  
RCERE3  
XCERE3  
Enhanced Receive Channel Enable Register  
2 Partition E/F  
Enhanced Transmit Channel Enable Register  
2 Partition E/F  
Enhanced Receive Channel Enable Register  
3 Partition G/H  
Enhanced Transmit Channel Enable Register  
3 Partition G/H  
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6.17.2 McBSP Electrical Data/Timing  
6.17.2.1 Multi-Channel Buffered Serial Port (McBSP) Timing  
Table 6-73. Timing Requirements for McBSP(1) (2) (see Figure 6-49)  
DEVICE  
NO.  
UNIT  
MIN  
MAX  
15(3) tc(CLKS)  
16(4) tw(CLKS)  
Cycle time, CLKS  
CLKS ext  
CLKS ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
38.5 or 2P  
ns  
ns  
Pulse duration, CLKR/X high or CLKR/X low  
19.25 or P  
21  
6
5
6
tsu(FRH-CKRL)  
th(CKRL-FRH)  
tsu(DRV-CKRL)  
th(CKRL-DRV)  
tsu(FXH-CKXL)  
th(CKXL-FXH)  
Setup time, external FSR high before CLKR low  
Hold time, external FSR high after CLKR low  
Setup time, DR valid before CLKR low  
ns  
ns  
ns  
ns  
ns  
ns  
0
6
21  
6
7
0
8
Hold time, DR valid after CLKR low  
6
21  
6
10  
11  
Setup time, external FSX high before CLKX low  
Hold time, external FSX high after CLKX low  
0
10  
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also  
inverted.  
(2) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3 ) .  
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock  
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA  
limitations and AC timing requirements.  
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.  
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Table 6-74. Switching Characteristics Over Recommended Operating Conditions for McBSP(1) (2) (3)  
(see Figure 6-49)  
DEVICE  
NO.  
2(4) (5) tc(CKRX)  
PARAMETER  
UNIT  
MIN  
MAX  
CLKR/X int  
CLKR/X ext  
CLKR/X int  
CLKR/X int  
CLKR/X ext  
CLKR int  
CLKR ext  
CLKX int  
Cycle time, CLKR/X  
38.5 or 2P  
ns  
17  
td(CLKS-CLKRX) Delay time, CLKS high to internal CLKR/X  
1
24  
19.25 - 1 or P - 1  
3(6) tw(CKRX)  
Pulse duration, CLKR/X high or CLKR/X low  
Delay time, CLKR high to internal FSR valid  
Delay time, CLKX high to internal FSX valid  
ns  
ns  
ns  
19.25 or P  
-4  
3
8
4
9
td(CKRH-FRV)  
25  
-4  
3
8
25  
td(CKXH-FXV)  
CLKX ext  
CLKX int  
12  
ns  
ns  
ns  
ns  
tdis(CKXH-  
DXHZ)  
Disable time, DX high impedance following last data  
bit from CLKX high  
12  
13  
CLKX ext  
CLKX int  
25  
-5 + D1(7)  
3 + D1(7)  
0 + D1(8)  
12 + D2(7)  
25 + D2(7)  
14 + D2(8)  
td(CKXH-DXV)  
Delay time, CLKX high to DX valid  
CLKX ext  
FSX int  
Delay time, FSX high to DX valid  
ONLY applies when in data  
delay 0 (XDATDLY = 00b) mode  
14  
td(FXH-DXV)  
ns  
FSX ext  
0 + D1(8)  
25 + D2(8)  
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also  
inverted.  
(2) Minimum delay times also represent minimum output hold times.  
(3) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3 ) .  
(4) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock  
source.  
(5) The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations  
and AC timing requirements. Use whichever value is greater.  
(6) C = H or L  
S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK3 period)  
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
H = (CLKGDV + 1)/2 * S if CLKGDV is odd  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
L = (CLKGDV + 1)/2 * S if CLKGDV is odd  
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit.  
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
If DXENA = 0, then D1 = D2 = 0  
If DXENA = 1, then D1 = 6P, D2 = 12P  
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
If DXENA = 0, then D1 = D2 = 0  
If DXENA = 1, then D1 = 6P, D2 = 12P  
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16  
15  
16  
CLKS  
2
17  
3
3
CLKR  
4
4
FSR (int)  
FSR (ext)  
5
6
7
8
Bit(n-1)  
(n-2)  
(n-3)  
DR  
2
17  
3
3
CLKX  
9
FSX (int)  
FSX (ext)  
11  
10  
FSX  
(XDATDLY=00b)  
(A)  
13  
14  
(A)  
13  
Bit(n-1)  
12  
DX  
Bit 0  
(n-2)  
(n-3)  
A. Parameter No. 13 applies to the first data bitonly when XDATDLY ≠ 0.  
Figure 6-49. McBSP Timing  
Table 6-75. McBSP as SPI Timing Requirements  
CLKSTP = 10b, CLKXP = 0 (see Figure 6-50)  
MASTER  
NO.  
UNIT  
MIN  
16  
0
MAX  
M30  
M31  
tsu(DRV-CKXL)  
th(CKXL-DRV)  
Setup time, DR valid before CLKX low  
Hold time, DR valid after CLKX low  
ns  
ns  
Table 6-76. McBSP as SPI Switching Characteristics(1) (2)  
CLKSTP = 10b, CLKXP = 0 (see Figure 6-50)  
MASTER  
MIN  
NO.  
PARAMETER  
Cycle time, CLKX  
UNIT  
MAX  
38.5 or  
2P  
M33  
M24  
tc(CKX)  
ns  
ns  
CLKXP - CLKXP +  
td(CKXL-FXH)  
Delay time, CLKX low to FSX high(2)  
2
4
CLKXL - CLKXL +  
M25  
M26  
M27  
td(FXL-CKXH)  
td(CKXH-DXV)  
tdis(CKXL-DXHZ)  
Delay time, FSX low to CLKX high(3)  
ns  
ns  
ns  
2
2
Delay time, CLKX high to DX valid  
-2  
6
CLKXL - CLKXL +  
Disable time, DX high impedance following last data bit from CLKX low  
3
8
(1) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3 ) .  
(2) T = CLKX period = (1 + CLKGDV) × 2P  
L1 = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even.  
(3) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master  
clock (CLKX).  
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CLKX  
M33  
M24  
M25  
FSX  
M27  
M26  
(n-2)  
DX  
DR  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-3)  
(n-3)  
(n-4)  
M30  
M31  
(n-2)  
Bit 0  
(n-4)  
Figure 6-50. McBSP as SPI: CLKSTP = 10b, CLKXP = 0  
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Table 6-77. McBSP as SPI Timing Requirements  
CLKSTP = 11b, CLKXP = 0  
MASTER  
NO.  
UNIT  
MIN  
16  
1
MAX  
M39  
M40  
tsu(DRV-CKXH)  
th(CKXH-DRV)  
Setup time, DR valid before CLKX high  
Hold time, DR valid after CLKX high  
ns  
ns  
Table 6-78. McBSP as SPI Switching Characteristics(1) (2)  
CLKSTP = 11b, CLKXP = 0 (see Figure 6-51)  
MASTER  
NO.  
PARAMETER  
UNIT  
MIN  
38.5 or 2P  
CLKXP - 2  
CLKXP - 2  
-2  
MAX  
M42  
M34  
M35  
M36  
tc(CKX)  
Cycle time, CLKX  
ns  
ns  
ns  
ns  
td(CKXL-FXH)  
td(FXL-CKXH)  
td(CKXL-DXV)  
Delay time, CLKX low to FSX high(3)  
Delay time, FSX low to CLKX high(4)  
Delay time, CLKX low to DX valid  
CLKXP + 4  
CLKXP + 2  
6
Disable time, DX high impedance following last data bit from  
CLKX low  
M37  
M38  
tdis(CKXL-DXHZ)  
td(FXL-DXV)  
-3  
8
ns  
ns  
Delay time, FSX low to DX valid  
CLKXH - 2 CLKXH + 10  
(1) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3 ).  
(2) T = CLKX period = (1 + CLKGDV) × 2P  
L1 = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even  
H1 = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even  
(3) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
(4) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master  
clock (CLKX).  
CLKX  
M42  
M35  
M34  
FSX  
DX  
M37  
M38  
M39  
M36  
(n-2)  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-3)  
(n-3)  
(n-4)  
M40  
(n-2)  
DR  
Bit 0  
(n-4)  
Figure 6-51. McBSP as SPI: CLKSTP = 11b, CLKXP = 0  
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Table 6-79. McBSP as SPI Timing Requirements  
CLKSTP = 10b, CLKXP = 1 (see Figure 6-52)  
MASTER  
UNIT  
NO.  
MIN  
16  
0
MAX  
M49  
M50  
tsu(DRV-CKXH)  
th(CKXH-DRV)  
Setup time, DR valid before CLKX high  
Hold time, DR valid after CLKX high  
ns  
ns  
Table 6-80. McBSP as SPI Switching Characteristics(1) (2)  
CLKSTP = 10b, CLKXP = 1 (see Figure 6-52)  
MASTER  
MIN  
NO.  
PARAMETER  
UNIT  
MAX  
M52  
M43  
M44  
M45  
tc(CKX)  
Cycle time, CLKX  
38.5 or 2P  
CLKXP - 2  
CLKXH - 2  
-2  
ns  
ns  
ns  
ns  
td(CKXH-FXH)  
td(FXL-CKXL)  
td(CKXL-DXV)  
Delay time, CLKX high to FSX high(3)  
Delay time, FSX low to CLKX low(4)  
Delay time, CLKX low to DX valid  
CLKXP + 4  
CLKXH + 2  
6
Disable time, DX high impedance following last data bit from  
CLKX high  
M46  
tdis(CKXH-DXHZ)  
CLKXH - 3  
CLKXL + 8  
ns  
(1) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3 ).  
(2) T = CLKX period = (1 + CLKGDV) × 2P  
H1 = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even  
(3) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
(4) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master  
clock (CLKX).  
CLKX  
M43  
FSX  
M44  
M52  
M46  
M45  
(n-2)  
DX  
DR  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-3)  
(n-4)  
M49  
M50  
(n-2)  
Bit 0  
(n-3)  
(n-4)  
Figure 6-52. McBSP as SPI: CLKSTP = 10b, CLKXP = 1  
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Table 6-81. McBSP as SPI Timing Requirements  
CLKSTP = 11b, CLKXP = 1 (see Figure 6-53)  
MASTER  
NO.  
UNIT  
MIN  
16  
0
MAX  
M58  
M59  
tsu(DRV-CKXL)  
th(CKXL-DRV)  
Setup time, DR valid before CLKX low  
Hold time, DR valid after CLKX low  
ns  
ns  
Table 6-82. McBSP as SPI Switching Characteristics(1) (2)  
CLKSTP = 11b, CLKXP = 1 (see Figure 6-53)  
MASTER  
NO.  
PARAMETER  
UNIT  
MIN  
38.5 or 2P  
CLKXP - 2  
CLKXP - 2  
-2  
MAX  
M62  
M53  
M54  
M55  
tc(CKX)  
Cycle time, CLKX  
ns  
ns  
ns  
ns  
td(CKXH-FXH)  
td(FXL-CKXL)  
td(CKXL-DXV)  
Delay time, CLKX high to FSX high(3)  
Delay time, FSX low to CLKX low(4)  
Delay time, CLKX high to DX valid  
CLKXP + 4  
CLKXP + 2  
6
Disable time, DX high impedance following last data bit from  
CLKX high  
M56  
M57  
tdis(CKXH-DXHZ)  
td(FXL-DXV)  
-3  
8
ns  
ns  
Delay time, FSX low to DX valid  
CLKXL - 1  
CLKXL + 10  
(1) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3 ).  
(2) T = CLKX period = (1 + CLKGDV) × 2P  
L1 = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even  
H1 = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even  
(3) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
(4) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master  
clock (CLKX).  
CLKX  
M62  
M53  
M54  
FSX  
DX  
M57  
M56  
M55  
(n-2)  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-3)  
(n-4)  
M58  
M59  
(n-2)  
DR  
Bit 0  
(n-3)  
(n-4)  
Figure 6-53. McBSP as SPI: CLKSTP = 11b, CLKXP = 1  
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6.18 Timer  
The device contains four software-programmable timers. Timer 0, Timer 1, Timer 3, and Timer 4  
(general-purpose timers) can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit  
chained mode. Timer 3 supports additional features over the other timers: external clock/event input,  
period reload, output event tied to Real Time Out (RTO) module, external event capture, and timer counter  
register read reset. Timer 2 is used only as a watchdog timer. Timer 2 is tied to device reset.  
•
•
64-bit count-up counter  
Timer modes:  
–
–
–
64-bit general-purpose timer mode (Timer 0, 1, 3, 4)  
Dual 32-bit general-purpose timer mode (Timer 0, 1, 3, 4)  
Watchdog timer mode (Timer 2)  
•
•
Two possible clock sources:  
–
–
Internal clock  
External clock/event input via timer input pins (Timer 3)  
Three possible operation modes:  
–
–
–
One-time operation (timer runs for one period then stops)  
Continuous operation (timer automatically resets after each period)  
Continuous operation with period reload (Timer 3)  
•
•
•
•
•
Generates interrupts to the ARM CPU  
Generates sync event to EDMA  
Generates output event to device reset (Timer 2)  
Generates output event to Real Timer Out (RTO) module (Timer 3)  
External event capture via timer input pins (Timer 3)  
For more detailed information, see the TMS320DM36x DMSoC Timer/Watchdog Timer User's Guide  
(SPRUFH0).  
6.18.1 Timer Peripheral Register Description(s)  
Table 6-83 lists the Timer registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-83. Timer Global Registers  
Offset  
00h  
04h  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
34h  
38h  
3Ch  
40h  
44h  
Acronym  
PID12  
Register Description  
Peripheral Identification Register 12  
Emulation Management Register  
Timer Counter Register 12  
Timer Counter Register 34  
Timer Period Register 12  
EMUMGT  
TIM12  
TIM34  
PRD12  
PRD34  
TCR  
Timer Period Register 34  
Timer Control Register  
TGCR  
Timer Global Control Register  
Watchdog Timer Control Register  
Timer Reload Register 12  
WDTCR  
REL12  
REL34  
Timer Reload Register 34  
CAP12  
Timer Capture Register 12  
Timer Capture Register 34  
Timer Interrupt Control and Status Register  
CAP34  
INTCTL_STAT  
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6.18.2 Timer Electrical Data/Timing  
Table 6-84. Timing Requirements for Timer Input(1) (2) (see Figure 6-54)  
DEVICE  
MIN  
NO.  
UNIT  
MAX  
1
2
3
4
tc(TIN)  
Cycle time, TIM_IN  
4P  
ns  
ns  
ns  
ns  
tw(TINPH)  
tw(TINPL)  
tt(TIN)  
Pulse duration, TIM_IN high  
Pulse duration, TIM_IN low  
Transition time, TIM_IN  
0.45C  
0.45C  
0.55C  
0.55C  
5
(1) GPIO001, GPIO002, GPIO003, and GPIO004 can be used as external clock inputs for Timer 3. See the TMS320DM36x DMSoC  
Timer/Watchdog Timer User's Guide for more information (SPRUFH0).  
(2) P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.  
1
2
3
4
4
TIM_IN  
Figure 6-54. Timer Input Timing  
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6.19 Pulse Width Modulator (PWM)  
The pulse width modulator (PWM) feature is very common in embedded systems. It provides a way to  
generate a pulse periodic waveform for motor control or can act as a digital-to-analog converter with some  
external components. This PWM peripheral is basically a timer with a period counter and a first-phase  
duration comparator, where bit width of the period and first-phase duration are both programmable. The  
Pulse Width Modulator (PWM) modules support the following features:  
•
•
•
32-bit period counter  
32-bit first-phase duration counter  
8-bit repeat count for one-shot operation. One-shot operation will produce N + 1 periods of the  
waveform, where N is the repeat counter value.  
•
•
•
Configurable to operate in either one-shot or continuous mode  
Buffered period and first-phase duration registers  
One-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or  
high-to-low).  
•
One-shot operation triggerable by the ISIF VSYNC output of the video processing subsystem (VPSS),  
which allows any of the PWM instantiations to be used as a ISIF timer. This allows the device module  
to support the functions provided by the ISIF timer feature (generating strobe and shutter signals).  
•
•
•
One-shot operation generates N+1 periods of waveform, N being the repeat count register value  
Configurable PWM output pin inactive state  
Interrupt and EDMA synchronization events  
6.19.1 PWM Peripheral Register Description(s)  
Table 6-85 lists the PWM registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-85. Pulse Width Modulator (PWM) Registers  
Offset  
00h  
Acronym  
PID  
Register Description  
PWM Peripheral Identification Register  
PWM Peripheral Control Register  
PWM Configuration Register  
PWM Start Register  
04h  
PCR  
08h  
CFG  
0Ch  
10h  
START  
RPT  
PWM Repeat Count Register  
PWM Period Register  
14h  
PER  
18h  
PH1D  
PWM First-Phase Duration Register  
6.19.2 PWM0/1/2/3 Electrical/Timing Data  
Table 6-86. Switching Characteristics Over Recommended Operating Conditions for PWM0/1/2/3  
Outputs(1) (see Figure 6-55 and Figure 6-56)  
DEVICE  
NO.  
PARAMETER  
UNIT  
MIN  
37  
MAX  
1
2
3
4
tw(PWMH)  
tw(PWML)  
tt(PWM)  
Pulse duration, PWMx high  
ns  
ns  
ns  
ns  
Pulse duration, PWMx low  
37  
Transition time, PWMx  
5
td(ISIF-PWMV)  
Delay time, ISIF(VD) trigger event to PWMx valid  
0
10  
(1) P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.  
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1
2
PWM0/1/2/3  
3
3
Figure 6-55. PWM Output Timing  
VD(CCDC)  
4
INVALID  
VALID  
PWM0  
PWM1  
4
4
INVALID  
VALID  
INVALID  
VALID  
PWM2  
PWM3  
4
INVALID  
VALID  
Figure 6-56. PWM Output Delay Timing  
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6.20 Real Time Out (RTO)  
The device uses the Real Time Out (RTO) peripheral to provide appropriate input control signals to  
external devices such as motor controllers. This peripheral supports the following features:  
•
•
Four separate outputs  
Trigger on Timer3 event  
6.20.1 Real Time Out (RTO) Peripheral Register Description(s)  
Table 6-87 lists the RTO registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-87. Real Time Out (RTO) Registers  
Offset  
0h  
Acronym  
Register Description  
REVID  
RTO Controller Revision ID Register  
RTO Controller Control and Status Register  
04h  
CTRL_STATUS  
6.20.2 RTO Electrical/Timing Data  
Table 6-88. Switching Characteristics Over Recommended Operating Conditions for RTO Outputs (see  
Figure 6-57 and Figure 6-58)(1)  
DEVICE  
NO.  
PARAMETER  
Pulse duration, RTOx high  
UNIT  
MIN  
MAX  
52.08  
3
1
tw(RTOH)  
27.7  
ns  
2
3
4
tw(RTOL)  
Pulse duration, RTOx low  
.45C  
.45C  
.55C  
.55C  
10  
ns  
ns  
ns  
tt(RTO)  
Transition time, RTOx  
td(TIMER3-RTOV)  
Delay time, Timer 3 (TINT12 or TINT34) trigger event to RTOx valid  
(1) C = MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns.  
1
2
RTO0/1/2/3  
3
3
Figure 6-57. RTO Output Timing  
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TINT12/TINT34  
(Timer3)  
4
RTO0  
RTO1  
INVALID  
VALID  
4
INVALID  
VALID  
4
INVALID  
VALID  
RTO2  
RTO3  
4
INVALID  
VALID  
Figure 6-58. RTO Output Delay Timing  
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6.21 Ethernet Media Access Controller (EMAC)  
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the  
network. The EMAC supports both 10Base-T (10 Mbits/second [Mbps]) and 100Base-TX (100 Mbps) in  
either half- or full-duplex mode. The EMAC module also supports hardware flow control and quality of  
service (QOS) support.  
The frequencies supported for transmit and receive clocks are fixed by the IEEE 802.3 standard as:  
•
•
2.5 MHz for 10Mbps  
25 MHz for 100Mbps  
The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY  
configuration and status monitoring.  
The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple  
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE  
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).  
Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER.  
Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will  
intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame  
will be detected as an error by the network  
Both the EMAC and the MDIO modules interface to the device through a custom interface that allows  
efficient data transmission and reception. This custom interface is referred to as the EMAC control  
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to  
multiplex and control interrupts.  
For more information on the TMS320DM36x DMSoC Ethernet Media Access Controller User's Guide  
(literature number SPRUFI5).  
6.21.1 EMAC Peripheral Register Description(s)  
Table 6-89 lists the EMAC registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-89. Ethernet Media Access Controller (EMAC) Control Module Registers  
Slave VBUS  
Acronym  
Register Description  
Address Offset  
0h  
04h  
08h  
Ch  
CMIDVER  
Identification and Version Register  
Software Reset Register  
CMSOFTRESET  
CMEMCONTROL  
CMINTCTRL  
Emulation Control Register  
Interrupt Control Register  
10h  
14h  
18h  
1Ch  
40h  
44h  
48h  
4Ch  
70Ch  
74h  
CMRXTHRESHINTEN  
CMRXINTEN  
Receive Threshold Interrupt Enable Register  
Receive Interrupt Enable Register  
Transmit Interrupt Enable Register  
Miscellaneous Interrupt Enable Register  
CMTXINTEN  
CMMISCINTEN  
CMRXTHRESHINTSTAT Receive Threshold Interrupt Status Register  
CMRXINTSTAT  
CMTXINTSTAT  
CMMISCINTSTAT  
CMRXINTMAX  
CMTXINTMAX  
Receive Interrupt Status Register  
Transmit Interrupt Status Register  
Miscellaneous Interrupt Status Register  
Receive Interrupts Per Millisecond Register  
Transmit Interrupts Per Millisecond Register  
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Table 6-90. Ethernet Media Access Controller (EMAC) Registers  
Offset  
0h  
Acronym  
Register Description  
TXIDVER  
Transmit Identification and Version Register  
Transmit Control Register  
4h  
TXCONTROL  
8h  
TXTEARDOWN  
Transmit Teardown Register  
10h  
RXIDVER  
Receive Identification and Version Register  
Receive Control Register  
14h  
RXCONTROL  
18h  
RXTEARDOWN  
Receive Teardown Register  
80h  
TXINTSTATRAW  
TXINTSTATMASKED  
TXINTMASKSET  
TXINTMASKCLEAR  
MACINVECTOR  
MACEOIVECTOR  
RXINTSTATRAW  
RXINTSTATMASKED  
RXINTMASKSET  
RXINTMASKCLEAR  
MACINTSTATRAW  
MACINTSTATMASKED  
MACINTMASKSET  
MACINTMASKCLEAR  
RXMBPENABLE  
RXUNICASTSET  
RXUNICASTCLEAR  
RXMAXLEN  
Transmit Interrupt Status (Unmasked) Register  
Transmit Interrupt Status (Masked) Register  
Transmit Interrupt Mask Set Register  
Transmit Interrupt Clear Register  
84h  
88h  
8Ch  
90h  
MAC Input Vector Register  
94h  
MAC End of Interrupt Vector Register  
Receive Interrupt Status (Unmasked) Register  
Receive Interrupt Status (Masked) Register  
Receive Interrupt Mask Set Register  
A0h  
A4h  
A8h  
ACh  
B0h  
Receive Interrupt Mask Clear Register  
MAC Interrupt Status (Unmasked) Register  
MAC Interrupt Status (Masked) Register  
MAC Interrupt Mask Set Register  
B4h  
B8h  
BCh  
100h  
104h  
108h  
10Ch  
110h  
114h  
120h  
124h  
128h  
12Ch  
130h  
134h  
138h  
13Ch  
140h  
144h  
148h  
14Ch  
150h  
154h  
158h  
15Ch  
160h  
164h  
168h  
16Ch  
170h  
MAC Interrupt Mask Clear Register  
Receive Multicast/Broadcast/Promiscuous Channel Enable Register  
Receive Unicast Enable Set Register  
Receive Unicast Clear Register  
Receive Maximum Length Register  
RXBUFFEROFFSET  
RXFILTERLOWTHRESH  
RX0FLOWTHRESH  
RX1FLOWTHRESH  
RX2FLOWTHRESH  
RX3FLOWTHRESH  
RX4FLOWTHRESH  
RX5FLOWTHRESH  
RX6FLOWTHRESH  
RX7FLOWTHRESH  
RX0FREEBUFFER  
RX1FREEBUFFER  
RX2FREEBUFFER  
RX3FREEBUFFER  
RX4FREEBUFFER  
RX5FREEBUFFER  
RX6FREEBUFFER  
RX7FREEBUFFER  
MACCONTROL  
Receive Buffer Offset Register  
Receive Filter Low Priority Frame Threshold Register  
Receive Channel 0 Flow Control Threshold Register  
Receive Channel 1 Flow Control Threshold Register  
Receive Channel 2 Flow Control Threshold Register  
Receive Channel 3 Flow Control Threshold Register  
Receive Channel 4 Flow Control Threshold Register  
Receive Channel 5 Flow Control Threshold Register  
Receive Channel 6 Flow Control Threshold Register  
Receive Channel 7 Flow Control Threshold Register  
Receive Channel 0 Free Buffer Count Register  
Receive Channel 1 Free Buffer Count Register  
Receive Channel 2 Free Buffer Count Register  
Receive Channel 3 Free Buffer Count Register  
Receive Channel 4 Free Buffer Count Register  
Receive Channel 5 Free Buffer Count Register  
Receive Channel 6 Free Buffer Count Register  
Receive Channel 7 Free Buffer Count Register  
MAC Control Register  
MACSTATUS  
MAC Status Register  
EMCONTROL  
Emulation Control Register  
FIFOCONTROL  
FIFO Control Register  
MACCONFIG  
MAC Configuration Register  
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Table 6-90. Ethernet Media Access Controller (EMAC) Registers (continued)  
Offset  
174h  
1D0h  
1D4h  
1D8h  
1DCh  
1E0h  
1E4h  
1E8h  
1ECh  
500h  
504h  
508h  
600h  
604h  
608h  
60Ch  
610h  
614h  
618h  
61Ch  
620h  
624h  
628h  
62Ch  
630h  
634h  
638h  
63Ch  
640h  
644h  
648h  
64Ch  
650h  
654h  
658h  
65Ch  
660h  
664h  
668h  
66Ch  
670h  
674h  
678h  
67Ch  
Acronym  
SOFTRESET  
MACSRCADDRLO  
MACSRCADDRHI  
MACHASH1  
MACHASH2  
BOFFTEST  
TPACETEST  
RXPAUSE  
TXPAUSE  
MACADDRLO  
MACADDRHI  
MACINDEX  
TX0HDP  
TX1HDP  
TX2HDP  
TX3HDP  
TX4HDP  
TX5HDP  
TX6HDP  
TX7HDP  
RX0HDP  
RX1HDP  
RX2HDP  
RX3HDP  
RX4HDP  
RX5HDP  
RX6HDP  
RX7HDP  
TX0CP  
Register Description  
Soft Reset Register  
MAC Source Address Low Bytes Register  
MAC Source Address High Bytes Register  
MAC Hash Address Register 1  
MAC Hash Address Register 2  
Back Off Test Register  
Transmit Pacing Algorithm Test Register  
Receive Pause Timer Register  
Transmit Pause Timer Register  
MAC Address Low Bytes Register, Used in Receive Address Matching  
MAC Address High Bytes Register, Used in Receive Address Matching  
MAC Index Register  
Transmit Channel 0 DMA Head Descriptor Pointer Register  
Transmit Channel 1 DMA Head Descriptor Pointer Register  
Transmit Channel 2 DMA Head Descriptor Pointer Register  
Transmit Channel 3 DMA Head Descriptor Pointer Register  
Transmit Channel 4 DMA Head Descriptor Pointer Register  
Transmit Channel 5 DMA Head Descriptor Pointer Register  
Transmit Channel 6 DMA Head Descriptor Pointer Register  
Transmit Channel 7 DMA Head Descriptor Pointer Register  
Receive Channel 0 DMA Head Descriptor Pointer Register  
Receive Channel 1 DMA Head Descriptor Pointer Register  
Receive Channel 2 DMA Head Descriptor Pointer Register  
Receive Channel 3 DMA Head Descriptor Pointer Register  
Receive Channel 4 DMA Head Descriptor Pointer Register  
Receive Channel 5 DMA Head Descriptor Pointer Register  
Receive Channel 6 DMA Head Descriptor Pointer Register  
Receive Channel 7 DMA Head Descriptor Pointer Register  
Transmit Channel 0 Completion Pointer Register  
Transmit Channel 1 Completion Pointer Register  
Transmit Channel 2 Completion Pointer Register  
Transmit Channel 3 Completion Pointer Register  
Transmit Channel 4 Completion Pointer Register  
Transmit Channel 5 Completion Pointer Register  
Transmit Channel 6 Completion Pointer Register  
Transmit Channel 7 Completion Pointer Register  
Receive Channel 0 Completion Pointer Register  
Receive Channel 1 Completion Pointer Register  
Receive Channel 2 Completion Pointer Register  
Receive Channel 3 Completion Pointer Register  
Receive Channel 4 Completion Pointer Register  
Receive Channel 5 Completion Pointer Register  
Receive Channel 6 Completion Pointer Register  
Receive Channel 7 Completion Pointer Register  
Network Statistics Registers  
TX1CP  
TX2CP  
TX3CP  
TX4CP  
TX5CP  
TX6CP  
TX7CP  
RX0CP  
RX1CP  
RX2CP  
RX3CP  
RX4CP  
RX5CP  
RX6CP  
RX7CP  
200h  
204h  
RXGOODFRAMES  
RXBCASTFRAMES  
Good Receive Frames Register  
Broadcast Receive Frames Register  
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Table 6-90. Ethernet Media Access Controller (EMAC) Registers (continued)  
Offset  
208h  
20Ch  
210h  
214h  
218h  
21Ch  
220h  
224h  
228h  
22Ch  
230h  
234h  
238h  
23Ch  
240h  
244h  
248h  
24Ch  
250h  
254h  
258h  
25Ch  
260h  
264h  
268h  
26Ch  
270h  
274h  
278h  
27Ch  
280h  
284h  
288h  
28Ch  
Acronym  
Register Description  
RXMCASTFRAMES  
RXPAUSEFRAMES  
RXCRCERRORS  
RXALIGNCODEERRORS  
RXOVERSIZED  
RXJABBER  
Multicast Receive Frames Register  
Pause Receive Frames Register  
Receive CRC Errors Register  
Receive Alignment/Code Errors Register  
Receive Oversized Frames Register  
Receive Jabber Frames Register  
RXUNDERSIZED  
RXFRAGMENTS  
RXFILTERED  
Receive Undersized Frames Register  
Receive Frame Fragments Register  
Filtered Receive Frames Register  
RXQOSFILTERED  
RXOCTETS  
Receive QOS Filtered Frames Register  
Receive Octet Frames Register  
TXGOODFRAMES  
TXBCASTFRAMES  
TXMCASTFRAMES  
TXPAUSEFRAMES  
TXDEFERRED  
Good Transmit Frames Register  
Broadcast Transmit Frames Register  
Multicast Transmit Frames Register  
Pause Transmit Frames Register  
Deferred Transmit Frames Register  
TXCOLLISION  
Transmit Collision Frames Register  
TXSINGLECOLL  
TXMULTICOLL  
Transmit Single Collision Frames Register  
Transmit Multiple Collision Frames Register  
Transmit Excessive Collision Frames Register  
Transmit Late Collision Frames Register  
Transmit Underrun Error Register  
TXEXCESSIVECOLL  
TXLATECOLL  
TXUNDERRUN  
TXCARRIERSENSE  
TXOCTETS  
Transmit Carrier Sense Errors Register  
Transmit Octet Frames Register  
FRAME64  
Transmit and Receive 64 Octet Frames Register  
Transmit and Receive 65 to 127 Octet Frames Register  
Transmit and Receive 128 to 255 Octet Frames Register  
Transmit and Receive 256 to 511 Octet Frames Register  
Transmit and Receive 512 to 1023 Octet Frames Register  
Transmit and Receive 1024 to RXMAXLEN Octet Frames Register  
Network Octet Frames Register  
FRAME65T127  
FRAME128T255  
FRAME256T511  
FRAME512T1023  
FRAME1024TUP  
NETOCTETS  
RXSOFOVERRUNS  
RXMOFOVERRUNS  
RXDMAOVERRUNS  
Receive FIFO or DMA Start of Frame Overruns Register  
Receive FIFO or DMA Middle of Frame Overruns Register  
Receive DMA Overruns Register  
Table 6-91. EMAC Descriptor Memory  
HEX ADDRESS RANGE  
ACRONYM  
DESCRIPTION  
EMAC Control Module Descriptor Memory  
0x01D0 8000 - 0x01D0 9FFF  
–
192  
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6.21.2 Ethernet Media Access Controller (EMAC) Electrical Data/Timing  
Table 6-92. Timing Requirements for MRCLK (see Figure 6-59)  
10 Mbps  
100 Mbps  
NO.  
UNIT  
MIN MAX MIN MAX  
1
2
3
tc(MRCLK)  
Cycle time, MRCLK  
400  
140  
140  
40  
14  
14  
ns  
ns  
ns  
tw(MRCLKH) Pulse duration, MRCLK high  
tw(MRCLKL) Pulse duration, MRCLK low  
1
2
3
MRCLK  
Figure 6-59. MRCLK Timing (EMAC - Receive)  
Table 6-93. Timing Requirements for MTCLK (see Figure 6-59)  
10 Mbps  
100 Mbps  
NO.  
UNIT  
MIN MAX MIN MAX  
1
2
3
tc(MTCLK)  
Cycle time, MTCLK  
400  
140  
140  
40  
14  
14  
ns  
ns  
ns  
tw(MTCLKH) Pulse duration, MTCLK high  
tw(MTCLKL)  
Pulse duration, MTCLK low  
1
2
3
MTCLK  
Figure 6-60. MTCLK Timing (EMAC - Transmit)  
Table 6-94. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 6-61)  
NO.  
UNIT  
MIN  
8
MAX  
1
2
tsu(MRXD-MRCLKH)  
th(MRCLKH-MRXD)  
Setup time, receive selected signals valid before MRCLK high  
Hold time, receive selected signals valid after MRCLK high  
ns  
ns  
8
(1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.  
1
2
MRCLK (Input)  
MRXD3−MRXD0,  
MRXDV, MRXER (Inputs)  
Figure 6-61. EMAC Receive Interface Timing  
Table 6-95. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit  
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Table 6-95. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit  
10/100 Mbit/s (1) (see Figure 6-62 ) (continued)  
10/100 Mbit/s(1) (see Figure 6-62)  
NO.  
UNIT  
MIN  
MAX  
1
td(MTCLKH-MTXD)  
Delay time, MTCLK high to transmit selected signals valid  
5
25  
ns  
(1) Transmit selected signals include: MTXD3-MTXD0, and MTXEN.  
1
MTCLK (Input)  
MTXD3−MTXD0,  
MTXEN (Outputs)  
Figure 6-62. EMAC Transmit Interface Timing  
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6.22 Management Data Input/Output (MDIO)  
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to  
enumerate all PHY devices in the system.  
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to  
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO  
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the  
negotiation results, and configure required parameters in the EMAC module for correct operation. The  
module is designed to allow almost transparent operation of the MDIO interface, with very little  
maintenance from the core processor. Only one PHY may be connected at any given time.  
For more detailed information on the MDIO peripheral, see the TMS320DM36x DMSoC Ethernet Media  
Access Controller User's Guide (literature number SPRUFI5).  
6.22.1 MDIO Peripheral Register Description(s)  
Table 6-96 lists the MDIO registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-96. Management Data Input/Output (MDIO) Registers  
Offset  
0h  
Acronym  
VERSION  
CONTROL  
ALIVE  
Register Description  
Identification and Version Register  
MDIO Control Register  
04h  
08h  
Ch  
PHY Alive Status register  
PHY Link Status Register  
LINK  
10h  
LINKINTRAW  
MDIO Link Status Change Interrupt  
(Unmasked) Register  
14h  
20h  
24h  
28h  
2Ch  
LINKINTMASKED  
USERINTRAW  
MDIO Link Status Change Interrupt (Masked)  
Register  
MDIO User Command Complete Interrupt  
(Unmasked) Register  
USERINTMASKED  
USERINTMASKSET  
USERINTMASKCLEAR  
MDIO User Command Complete Interrupt  
(Masked) Register  
MDIO User Command Complete Interrupt  
Mask Set Register  
MDIO User Command Complete Interrupt  
Mask Clear Register  
80h  
84h  
88h  
8Ch  
USERACCESS0  
USERPHYSEL0  
USERACCESS1  
USERPHYSEL1  
MDIO User Access Register 0  
MDIO User PHY Select Register 0  
MDIO User Access Register 1  
MDIO User PHY Select Register 1  
6.22.2 Management Data Input/Output (MDIO) Electrical Data/Timing  
Table 6-97. Timing Requirements for MDIO Input (see Figure 6-63 and Figure 6-64)  
DEVICE  
NO.  
UNIT  
MIN  
400  
180  
MAX  
1
2
3
4
5
tc(MDCLK)  
Cycle time, MDCLK  
ns  
ns  
ns  
ns  
ns  
tw(MDCLK)  
Pulse duration, MDCLK high/low  
tt(MDCLK)  
Transition time, MDCLK  
5
tsu(MDIO-MDCLKH)  
th(MDCLKH-MDIO)  
Setup time, MDIO data input valid before MDCLK high  
Hold time, MDIO data input valid after MDCLK high  
10  
10  
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1
3
3
MDCLK  
4
5
MDIO  
(input)  
Figure 6-63. MDIO Input Timing  
Table 6-98. Switching Characteristics Over Recommended Operating Conditions for MDIO Output  
(see Figure 6-64)  
DEVICE  
NO.  
UNIT  
MIN  
MAX  
7
td(MDCLKL-MDIO)  
Delay time, MDCLK low to MDIO data output valid  
100  
ns  
1
MDCLK  
7
MDIO  
(output)  
Figure 6-64. MDIO Output Timing  
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6.23 Host-Port Interface (HPI) Peripheral  
Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot  
mode selected is HPI boot mode. In this configuration, the device will always act as a slave.  
6.23.1 HPI Device-Specific Information  
The device includes a user-configurable 16-bit Host-port interface (HPI16).  
•
•
•
•
•
•
•
•
•
Multiplexed (address/data) operation  
Configurable single full-word cycle and dual half-word cycle access modes  
Bursting available utilizing 8-word read and write FIFOs  
HPIA register supports auto-incrementing  
HPID register/FIFOs providing data-path between external host interface and system bus  
Multiple strobes and control signals to allow flexible host connection  
Software control of data prefetching to the HPID/FIFOs  
DMSoC-to-Host interrupt output signal controlled by HPIC accesses  
Host-to-DMSoC interrupt controlled by HPIC accesses  
NOTE: The device HPI does not support the HAS feature. For proper HPI operation if the HAS pin is  
routed out, the HAS pin must be pulled up via an external resistor.  
The device HPICTL register (0x01C4 0024) is part of the System Module Registers. The HPICTL register  
controls write access to the HPI peripheral control and address registers as well as determines the host  
time-out value.  
6.23.2 HPI Bus Master  
The HPI peripheral includes a bus master interface that allows external device initiated transfers to access  
the DM365 system bus. See the Master Peripheral Mem Map column in Table 2-3, the device Memory  
Map.  
6.23.3 HPI Peripheral Register Description(s)  
Table 6-99 lists the HPI registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-99. HPI Registers  
Offset  
0h  
Acronym  
PID  
Register Description  
Peripheral Identification Register  
4h  
PWREMU_MGMT  
HPIC  
Power and Emulation Management Register  
Host Port Interface Control Register  
Host Port Interface Write Address Register  
Host Port Interface Read Address Register  
30h  
34h  
38h  
HPIAW  
HPIAR  
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6.23.4 HPI Electrical Data/Timing  
Table 6-100. Timing Requirements for Host-Port Interface Cycles(1) (2) (see Figure 6-65 and Figure 6-66)  
DEVICE  
NO.  
UNIT  
MIN  
6
MAX  
1
2
tsu(SELV-HSTBL)  
th(HSTBL-SELV)  
tw(HSTBL)  
Setup time, select signals(3) valid before HSTROBE low  
Hold time, select signals(3) valid after HSTROBE low  
Pulse duration, HSTROBE active low  
ns  
ns  
ns  
ns  
ns  
ns  
2
3
15  
2P  
5
4
tw(HSTBH)  
Pulse duration, HSTROBE inactive high between consecutive accesses  
Setup time, host data valid before HSTROBE high  
Hold time, host data valid after HSTROBE high  
11  
12  
tsu(HDV-HSTBH)  
th(HSTBH-HDV)  
2
Hold time, HSTROBE high after HRDY low. HSTROBE should not be  
inactivated until HRDY is active (low); otherwise, HPI writes will not  
complete properly.  
13  
th(HRDYL-HSTBL)  
2
ns  
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
(2) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3 , Device Clocking  
(3) Select signals include: HCNTLA, HCNTLB, HR/W and HHWIL.  
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Table 6-101. Switching Characteristics for Host-Port Interface Cycles(1) (2) (3)  
(see Figure 6-65 and Figure 6-66)  
DEVICE  
MIN MAX  
NO.  
PARAMETER  
UNIT  
For HPI Write, HRDY can go high (not  
ready) for these HPI Write conditions;  
otherwise, HRDY stays low (ready):  
Case 1: Back-to-back HPIA writes (can  
be either first or second half-word)  
Case 2: HPIA write following a  
PREFETCH command (can be either  
first or second half-word)  
Case 3: HPID write when FIFO is full  
or flushing (can be either first or  
second half-word)  
Case 4: HPIA write and Write FIFO not  
empty  
For HPI Read, HRDY can go high (not  
ready) for these HPI Read conditions:  
Case 1: HPID read (with  
Delay time, HSTROBE low to  
HRDY valid  
5
td(HSTBL-HRDYV)  
17  
ns  
auto-increment) and data not in Read  
FIFO (can only happen to first  
half-word of HPID access)  
Case 2: First half-word access of HPID  
Read without auto-increment  
For HPI Read, HRDY stays low (ready)  
for these HPI Read conditions:  
Case 1: HPID read with auto-increment  
and data is already in Read FIFO  
(applies to either half-word of HPID  
access)  
Case 2: HPID read without  
auto-increment and data is already in  
Read FIFO (always applies to second  
half-word of HPID access)  
Case 3: HPIC or HPIA read (applies to  
either half-word access)  
6
7
ten(HSTBL-HDLZ)  
td(HRDYL-HDV)  
toh(HSTBH-HDV)  
tdis(HSTBH-HDV)  
Enable time, HD driven from HSTROBE low  
Delay time, HRDY low to HD valid  
2
ns  
ns  
ns  
ns  
0
8
Output hold time, HD valid after HSTROBE high  
Disable time, HD high-impedance from HSTROBE high  
1.5  
14  
15  
For HPI Read. Applies to conditions  
where data is already residing in  
HPID/FIFO:  
Case 1: HPIC or HPIA read  
Case 2: First half-word of HPID read  
with auto-increment and data is  
already in Read FIFO  
Delay time, HSTROBE low to  
HD valid  
15  
td(HSTBL-HDV)  
18  
ns  
Case 3: Second half-word of HPID  
read with or without auto-increment  
(1) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3, Device Clocking.  
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).  
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HCS  
HAS(D)  
2
2
2
1
1
HCNTL[B:A]  
2
1
1
HR/W  
2
2
1
1
HHWIL  
4
3
3
HSTROBE(A)(C)  
15  
15  
6
14  
14  
6
8
8
HD[15:0]  
(output)  
1st Half-Word  
5
13  
7
2nd Half-Word  
HRDY(B)  
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] or HCS.  
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and  
the state of the FIFO, transitions on HRDY may or may not occur.  
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by  
parameters for HSTROBE.  
D. For proper HPI operation, HAS must be pulled up via an external resistor.  
Figure 6-65. HPI16 Read Timing (HAS Not Used, Tied High)  
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HCS  
HAS(D)  
2
2
2
2
1
1
1
HCNTL[B:A]  
HR/W  
2
1
2
1
1
HHWIL  
4
3
3
HSTROBE(A)(C)  
11  
11  
12  
12  
2nd Half-Word  
1st Half-Word  
HD[15:0]  
(input)  
18  
18  
5
13  
13  
5
HRDY(B)  
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with  
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur.  
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing  
requirements are reflected by parameters for HSTROBE.  
D. For proper HPI operation, HAS must be pulled up via an external resistor.  
Figure 6-66. HPI16 Write Timing (HAS Not Used, Tied High)  
6.24 Key Scan  
The device contains Key Scan module that supports two types of Key Matrices - 4x4 and 5x3. It also  
supports the following features :  
•
•
•
•
Supports the following two scan modes  
–
–
Channel Interval mode  
Scan Interval mode  
Programmable key scan time  
–
–
Strobe time  
Interval time  
Two input detection modes  
–
–
Direct mode  
3-Data check mode  
Supports one interrupt to detect the following:  
–
–
Key input changes  
Periodic time intervals after a key is pressed  
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6.24.1 Key Scan Peripheral Register Description(s)  
Table 6-102 lists the Key Scan registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-102. Key Scan Registers  
Offset  
0x0  
Register  
Description  
KEYCTRL  
Module Control register  
Interrupt Enable control  
Interrupt Flag control  
Interrupt Clear control  
Strobe width  
0x4  
INTCENA  
0x8  
INTFLG  
0xC  
INTCLR  
0x10  
0x14  
0x18  
0x1C  
0x20  
0x24  
STRBWIDTH  
INTERVALTIME  
CONTITIME  
CURRENTST  
PREVIOUSST  
EMUCTRL  
Interval Time  
Continuous timer  
Keyscan current status  
Keyscan previous status  
Emulation control  
6.24.2 Key Scan Electrical Data/Timing  
Table 6-103. Timing Requirements for Keyscan (see Figure 6-63 and Figure 6-64)  
DEVICE  
NO  
.
UNIT  
MIN MAX  
(STWIDTH + 1)*CLK_P-1(1)  
1
2
tw(KEYOUTV)  
tw(KEYOUTL)  
tsu(KEYOUT-KEYIN)  
Pulse duration, Keyscan out (active low mode)  
Pulse duration, Keyscan out (always out mode)  
ns  
ns  
(2)  
(STWIDTH + 1)*CLK_P-1(1)  
(2)  
Setup time, Keyscan input (always out mode)  
Setup time, Keyscan input (active low mode)  
Hold time, Keyscan input (always out mode)  
Hold time, Keyscan input (active low mode)  
3
4
20  
0
ns  
ns  
th(KEYOUT-KEYIN)  
(1) STWIDTH = the value programmed into the STRBWIDTH register.  
(2) CLK_P = 1/(PLLC1.AUXCLK/(DIV3+1)) or 1/(RTCXI), where RTCXI is the PRTCSS oscillator input pin frequency of 32.768kHz.  
1
KEY_OUT[3:0]  
Hi -Z  
Hi -Z  
(Active Low)  
2
KEY_OUT[3:0]  
(Always Out)  
3
4
KEY_ IN[4:0]  
Figure 6-67. Key Scan Timing  
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6.25 Analog-to-Digital Converter (ADC)  
The device has a 6-channel 10-bit Analog-to-Digital Converter (ADC) interface. The analog-to-digital  
converter (ADC) feature is very common in embedded systems. The following features are supported on  
the Analog-to-Digital Converter (ADC):  
•
•
•
•
•
•
•
Six configurable analog input selects  
Successive Approximation type 10 bit A-D converter  
Programmable Sampling / Conversion Time (base clock is AUXCLK)  
Channel select by Auto Scan conversion  
Mode select by One-shot mode or Free-run mode  
Programmable setup (idle) period to secure A/D sampling start time  
Supports the clock stop signals to connect the PSC  
For Analog-to-Digital Converter characteristics, see Section 5.2 and Section 5.3.  
6.25.1 Analog-to-Digital Converter (ADC) Peripheral Register Description(s)  
Table 6-104 lists the ADC registers, their corresponding acronyms, and the device memory locations  
(offsets).  
Table 6-104. Analog-to-Digital Converter (ADC) Interface Registers  
Offset  
0x0  
Register  
ADCTL  
Description  
Control register  
0x4  
CMPTGT  
CMPLDAT  
CMPUDAT  
SETDIV  
Comparator target channel  
Comparison A/D Lower data  
Comparison A/D Upper data  
SETUP divide value for start A/D conversion  
Analog Input channel select  
A/D conversion data 0  
A/D conversion data 1  
A/D conversion data 2  
A/D conversion data 3  
A/D conversion data 4  
A/D conversion data 5  
Emulation Control  
0x8  
0xC  
0x10  
0x14  
0x18  
0x1C  
0x20  
0x24  
0x28  
0x2C  
0x30  
CHSEL  
AD0DAT  
AD1DAT  
AD2DAT  
AD3DAT  
AD4DAT  
AD5DAT  
EMUCTRL  
6.26 Voice Codec  
The device has Voice Codec with FIFO (Read FIFO/Write FIFO). The following features are supported on  
the Voice Codec module.  
•
•
•
•
•
•
•
•
•
•
16bit x 16 word FIFO for Recording/Playback data transfer  
Full differential Microphone Amplifier  
Monaural single ended Line output  
Monaural Speaker Amplifier (BTL)  
Dynamic Range: 70dB(DAC)  
Dynamic Range: 70dB(ADC)  
200-300mW Speaker output at RL = 8Ω  
Sampling frequency: 8 KHz or 16 KHz  
Automatic Level Control for Recording  
Programmable Function by Register Control  
–
Digital Attenuator of DAC: 0 dB to -62 dB  
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–
–
–
–
Digital gain control for Recording (0/ +6/ +12/ +18dB)  
Power Up/Down Control for each module  
20 dB/26 dB Boost Selectable for Microphone Input  
Two Stage Notch filter  
For Voice Codec characteristics, see Section 5.2 and Section 5.3.  
6.26.1 Voice Codec Register Description(s)  
Table 6-105 lists the Voice Codec registers, their corresponding acronyms, and the device memory  
locations (offsets).  
Table 6-105. Voice Codec Registers  
Offset  
0x00  
0x04  
0x08  
0x0C  
0x10  
0x14  
0x20  
0x24  
0x28  
0x80  
0x84  
0x88  
0x8C  
0x90  
0x94  
0x98  
0xA4  
0xA8  
0xB0  
Register  
VC_PID  
Description  
VCIF PID  
VC_CTRL  
VCIF Control Register  
VCIF Interrupt enable  
VCIF Interrupt status  
VC_INTEN  
VC_INTSTATUS  
VC_INTCLR  
VC_EMUL_CTRL  
RFIFO  
VCIF Interrupt status clear  
VCIF emulator Control  
VCIF Read FIFO access register  
VCIF Write FIFO access register  
FIFO Status  
WFIFO  
FIFOSTAT  
VC_REG00  
VC_REG01  
VC_REG02  
VC_REG03  
VC_REG04  
VC_REG05  
VC_REG06  
VC_REG09  
VC_REG10  
VC_REG12  
Notch filter parameter 1  
Notch filter parameter 1  
Notch filter parameter 2  
Notch filter parameter 2  
Recording side mode control  
PGM & MIC gain  
ALC  
Digital soft mute/attention  
Digital soft mute/attention  
Power up/down control  
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6.27 IEEE 1149.1 JTAG  
The JTAG(1) interface is used for BSDL testing and emulation of the device.  
The device requires that both TRST and RESET be asserted upon power up to be properly initialized.  
While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required  
for proper operation.  
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for  
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG  
port interface and device's emulation logic in the reset state.  
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or  
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by  
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.  
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE  
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.  
For maximum reliability, the device includes an internal pulldown (PD) on the TRST pin to ensure that  
TRST will always be asserted upon power up and the device's internal emulation logic will always be  
properly initialized.  
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG  
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.  
When using this type of JTAG controller, assert TRST to initialize the device after power up and externally  
drive TRST high before attempting any emulation or boundary scan operations. Following the release of  
RESET, the low-to-high transition of TRST must be "seen" to latch the state of EMU1 and EMU0. The  
EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed  
information, see the terminal functions section of this data sheet.  
6.27.1 JTAG Register Description(s)  
Table 6-105 shows the DEVICE ID register (which includes the JTAG ID related information), its  
corresponding acronym, and the device memory location. For more details on the DEVICE ID register bit  
fields, see the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).  
Table 6-106. DEVICE ID Register  
HEX ADDRESS RANGE  
ACRONYM  
REGISTER NAME  
JTAG Identification Register  
COMMENTS  
Read-only. Provides 32-bit  
JTAG ID of the device.  
0x01C4 0028  
DEVICEID  
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
The DEVICE ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the  
device, the DEVICE ID register resides at address location 0x01C4 0028. The register hex value for the  
device is: 0xXB70 002F where 'X' denotes the silicon revision of the device. For more details on the silicon  
revision, see the TMS320DM365 DMSoC Silicon Errata (literature number SPRZ294).  
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6.27.2 JTAG Test-Port Electrical Data/Timing  
Table 6-107. Timing Requirements for JTAG Test Port (see Figure 6-68)  
DEVICE  
NO.  
UNIT  
MIN  
50  
20  
20  
5
MAX  
1
2
3
4
5
6
7
tc(TCK)  
Cycle time, TCK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tw(TCKH)  
Pulse duration, TCK high  
tw(TCKL)  
Pulse duration, TCK low  
tsu(TDIV-RTCKH)  
th(RTCKH-TDIIV)  
tsu(TMSV-RTCKH)  
th(RTCKH-TMSV)  
Setup time, TDI valid before RTCK high  
Hold time, TDI valid after RTCK high  
Setup time, TMS valid before RTCK high  
Hold time, TMS valid after RTCK high  
10  
5
10  
1
2
3
TCK  
RTCK  
TDO  
TDI  
5
7
4
6
TMS  
Figure 6-68. JTAG Input Timing  
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Table 6-108. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port  
(see Figure 6-68)  
DEVICE  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
8
9
tc(RTCK)  
Cycle time, RTCK  
50  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
tw(RTCKH)  
Pulse duration, RTCK high  
Pulse duration, RTCK low  
10 tw(RTCKL)  
11 tr(all JTAG outputs) Rise time, all JTAG outputs  
12 tf(all JTAG outputs) Fall time, all JTAG outputs  
5
5
13 td(RTCKL-TDOV)  
Delay time, TCK low to TDO valid  
0
23  
8
9
10  
RTCK  
TDO  
13  
Figure 6-69. JTAG Output Timing  
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7 Mechanical Data  
The following table(s) show the thermal resistance characteristics for the PBGA − ZCE mechanical  
package. Note that micro-vias are not required.  
7.1 Thermal Data for ZCE  
The following table shows the thermal resistance characteristics for the PBGA − ZCE mechanical  
package.  
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZCE]  
NO.  
1
°C/W(1)  
7.2  
RΘJC  
RΘJB  
RΘJA  
PsiJT  
PsiJB  
Junction-to-case  
2
Junction-to-board  
Junction-to-free air  
Junction-to-package top  
Junction-to-board  
11.4  
27.0  
0.1  
3
4
5
11.3  
(1) The junction-to-case measurement was conducted in a JEDEC defined 2S2P system and will change based on environment as well as  
application. For more information, see these three EIA/JEDEC standards:  
•
•
•
EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)  
EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
7.2 Packaging Information  
The following packaging information reflects the most current data available for the designated device(s).  
This data is subject to change without notice and without revision of this document. Note that micro-vias  
are not required for this package.  
208  
Mechanical Data  
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PACKAGE OPTION ADDENDUM  
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8-May-2010  
PACKAGING INFORMATION  
Orderable Device  
TMS320DM365ZCE21  
TMS320DM365ZCE27  
TMS320DM365ZCE30  
TMS320DM365ZCED30  
TMS320DM365ZCEF  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
NFBGA  
ZCE  
338  
338  
338  
338  
338  
160 Green (RoHS &  
no Sb/Br)  
SNAGCU  
SNAGCU  
SNAGCU  
SNAGCU  
SNAGCU  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
NFBGA  
NFBGA  
NFBGA  
NFBGA  
ZCE  
ZCE  
ZCE  
ZCE  
160 Green (RoHS &  
no Sb/Br)  
1
Green (RoHS &  
no Sb/Br)  
160 Green (RoHS &  
no Sb/Br)  
160 Green (RoHS &  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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VS36VUA1VWMTF

 VS36VUA1VWMTF是一款用于浪涌保护、电压控制和电压限制的TVS二极管，是符合AEC-Q101标准的高可靠性车规级产品。该产品用更小型的PMDE封装实现了与ROHM以往产品同等的电气特性。PMDE是可靠性高、散热性能优异的封装形式。
ROHM

VS3AN5XLP

 VS3 Series Retroreflective Mode Sensors
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VS3AN5XLPQ

 VS3 Series Retroreflective Mode Sensors
BANNER

VS3AN5XLV

 VS3 Series Retroreflective Mode Sensors
BANNER

VS3AN5XLVQ

 VS3 Series Retroreflective Mode Sensors
BANNER

VS3AP5XLP

 VS3 Series Retroreflective Mode Sensors
BANNER

VS3AP5XLPQ

 VS3 Series Retroreflective Mode Sensors
BANNER

VS3AP5XLV

 VS3 Series Retroreflective Mode Sensors
BANNER

VS3AP5XLVQ

 VS3 Series Retroreflective Mode Sensors
BANNER

VS3RN5XLP

 VS3 Series Retroreflective Mode Sensors
BANNER
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