WL1805MOD [TI]
WiLink™ 8 单频带、2x2 MIMO Wi-Fi® 模块;
| 型号： | WL1805MOD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | WiLink™ 8 单频带、2x2 MIMO Wi-Fi® 模块 |
| 文件： | 总46页 (文件大小：2449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
WL18xxMOD WiLink™ 8 单频段 Combo模块 –
Wi-Fi®， Bluetooth®，和 Bluetooth 低功耗 (BLE)
1 器件概述
1.1 特性
1
• 常规说明
• Bluetooth 和 BLE（仅适用于 WL183xMOD）
– 集成了射频 (RF)、功率放大器 (PA)、时钟、RF
开关、滤波器、无源器件和电源管理单元
– 支持 Bluetooth 4.1 和 CSA2
– 主机控制器接口 (HCI) 传输，用于通过通用异步
收发器 (UART) 进行的 Bluetooth 传输
– 支持子带 (SBC) 编码 + 高级音频传输协议
(A2DP) 的专用音频处理器
– 可利用 TI 模块配套资料和参考设计实现快速硬件
设计
– 工作温度：–20°C 至 70°C
– 小封装尺寸：13.3mm x 13.4mm x 2mm
– 100 引脚 MOC 封装
– 经 FCC，IC，ETSI/CE 和 TELEC 认证的芯片天
线
– 双模 Bluetooth 和 BLE
– Bluetopia + LE 认证堆栈（由 TI 提供）
• 主要优势
– 减少设计开销
• Wi-Fi
– 通过在两极（STA 和 AP）上同时配置 WiLink
8，可将差别化的使用案例直接连接至不同 RF 通
道（Wi-Fi 网络）上的其它 Wi-Fi 器件
– 支持 IEEE 标准 802.11a、802.11b、802.11g 和
802.11n 的 WLAN 基带处理器和 RF 收发器
– 2.4GHz 20MHz 和 40MHz 单输入单输出 (SISO)
以及 2.4GHz 20MHz 2 x 2 多输入多输出
(MIMO)，针对高数据吞吐量：80Mbps
(TCP)，100Mbps (UDP)
– 用于高性能音频和视频流参考应用的一流 Wi-
Fi，覆盖范围高达单根天线的 1.4 倍
– 提供多种配置方法，可一步将室内设备连接至
Wi-Fi
– 2.4GHz 最大比合并 (MRC)，支持扩展范围
– 完全校准：无需生产校准
– 4 位 SDIO 主机接口支持
– 连接空闲时最低 Wi-Fi 功耗 (< 800µA)
– WLAN 滤波器上只将系统唤醒的可配置唤醒
– Wi-Fi-Bluetooth 单天线共存
– Wi-Fi 直接并发运行（多通道、多用途）
1.2 应用范围
•
•
•
•
物联网
•
•
•
•
工业和家庭自动化
智能网关和仪表计量
视频会议
多媒体
家用电子产品
家用电器和大型家电
视频摄像机和安防器材
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SWRS152
WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
www.ti.com.cn
1.3 说明
TI 经认证的 WiLink 8 模块采用功率优化设计，可提供高数据吞吐量和扩展范围，并且支持 Wi-Fi 和
Bluetooth 共存（只适用于 WL1835MOD）。 WL18x5MOD 器件是一套 2.4GHz 模块双天线解决方案。 该
器件经 FCC、IC、ETSI/CE 和 TELEC 认证，适用于接入点 (AP) 和客户端。 TI 为 Linux®、
Android™、WinCE 和 RTOS 等高级操作系统提供了驱动程序。
器件信息
封装
订货编号
封装尺寸
WL1801MOD
WL1805MOD
WL1831MOD
WL1835MOD
MOC (100)
MOC (100)
MOC (100)
MOC (100)
13.3mm × 13.4mm × 2mm
13.3mm × 13.4mm × 2mm
13.3mm × 13.4mm × 2mm
13.3mm × 13.4mm × 2mm
空白
1.4 功能方框图
图 1-1 显示了 WL1835 变型的功能方框图。
OSC
32kHz
RFTST
:
BT UART
WRF2
WRF1
WLAN: SDIO
F
F
bg1
bg2
VIO
BT
26M XTAL
PM
VBAT
COEX I/F
图 1-1. WL1835 功能方框图
空白
2
器件概述
版权 © 2013–2014, Texas Instruments Incorporated
WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
www.ti.com.cn
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
内容
1
器件概述.................................................... 1
5.12 Timing and Switching Characteristics ............... 18
1.1 特性 ................................................... 1
1.2 应用范围 .............................................. 1
1.3 说明 ................................................... 2
1.4 功能方框图............................................ 2
修订历史记录............................................... 3
Device Comparison ..................................... 4
Terminal Configuration and Functions.............. 5
4.1 Pin Description ....................................... 7
Specifications .......................................... 10
5.1 Absolute Maximum Ratings......................... 10
5.2 Handling Ratings.................................... 10
5.3 Power-On Hours (POH)............................. 10
5.4 Recommended Operating Conditions............... 10
6
Detailed Description ................................... 26
6.1 WLAN ............................................... 27
6.2 Bluetooth ............................................ 27
6.3 BLE.................................................. 28
6.4 WiLink 8 Module Markings .......................... 28
6.5 Test Grades ......................................... 29
Applications and Implementation................... 30
7.1 Application Information .............................. 30
Device and Documentation Support ............... 35
8.1 Device Support ...................................... 35
8.2 Related Links........................................ 35
8.3 社区资源............................................. 35
8.4 商标.................................................. 35
8.5 静电放电警告 ........................................ 36
8.6 术语表 ............................................... 36
2
3
4
7
8
5
5.5
External Digital Slow Clock Requirements.......... 11
5.6 Thermal Characteristics............................. 11
5.7 WLAN Performance ................................. 12
5.8 Bluetooth Performance.............................. 14
5.9 Bluetooth LE Performance .......................... 16
5.10 Bluetooth-BLE Dynamic Currents................... 17
5.11 Bluetooth LE Currents .............................. 18
9
Mechanical Packaging and Orderable
Information .............................................. 37
9.1 TI Module Mechanical Outline ...................... 37
9.2 Packaging Information .............................. 38
2 修订历史记录
Changes from Revision I (August 2014) to Revision J
Page
•
•
•
Changed 节 1.1，特性 ............................................................................................................... 1
Changed 节 1.2，应用 ............................................................................................................... 1
Changed organization of 节 9, Mechanical Packaging and Orderable Information ........................................ 37
Copyright © 2013–2014, Texas Instruments Incorporated
修订历史记录
3
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Product Folder Links: WL1801MOD WL1805MOD WL1831MOD WL1835MOD
WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
www.ti.com.cn
3 Device Comparison
The TI WiLink 8 module offers four footprint-compatible 2.4-GHz variants providing stand-alone and
Bluetooth combo connectivity. Table 3-1 compares the features of the module variants.
Table 3-1. TI WiLink 8 Module Variants
DEVICE
WLAN 2.4-GHZ SISO(1)
WLAN 2.4-GHZ MIMO(1)
WLAN 2.4-GHZ MRC(1)
BLUETOOTH
WL1835MOD
WL1831MOD
WL1805MOD
WL1801MOD
√
√
√
√
√
√
√
√
√
√
(1) SISO: single input, single output; MIMO: multiple input, multiple output; MRC: maximum ratio combining.
4
Device Comparison
Copyright © 2013–2014, Texas Instruments Incorporated
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WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
www.ti.com.cn
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
4 Terminal Configuration and Functions
Figure 4-1 shows the pin assignments for the 100-pin MOC package.
PIN 49 - GND
BT_HCI_RTS
2G4_ANT1_WB
GND
GND
BT_HCI_CTS
BT_HCI_TX
BT_HCI_RX
GND
GND GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GPIO1
GPIO2
GPIO4
GND
GND
GND
BT_AUD_IN
BT_AUD_OUT
BT_AUD_FSYNC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RESERVED2
RESERVED1
BT_AUD_CLK
GND
GND GND GND
GND GND
RESERVED3
GND
GND
GND
GND
GND
GND
GND
GND
RESERVED
2G4_ANT2_W
PIN 17 - GND
Figure 4-1. 100-Pin MOC Package (Bottom View)
Copyright © 2013–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
5
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WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
www.ti.com.cn
Figure 4-2 shows the outline of the 100-pin MOC package.
NOTE: 1. Module size: 13.4 x 13.3 mm
NOTE: 2. Pad size: 0.75 x 0.40 mm
NOTE: 3. Pitch: 0.7 mm
Figure 4-2. Outline of 100-Pin MOC Package
Figure 4-3 shows the outline of the recommended PCB pattern for the 100-pin MOC package.
Figure 4-3. Outline of Recommended PCB Pattern for 100-Pin MOC Package
6
Terminal Configuration and Functions
Copyright © 2013–2014, Texas Instruments Incorporated
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WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
www.ti.com.cn
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
4.1 Pin Description
Table 4-1 describes the module pins.
Table 4-1. Pin Description
PIN NAME
PIN
TYPE/ SHUTDOWN
AFTER
POWER
UP(1)
VOLTAG
E LEVEL
CONNECTIVITY(2)
DESCRIPTION
DIR
STATE
1801 1805 1831 1835
Clocks and Reset SIgnals
WL_SDIO_CLK_1V8
8
I
Hi-Z
Hi-Z
1.8 V
v
v
v
v
WLAN SDIO clock.
Must be driven by the
host.
EXT_32K
WLAN_EN
BT_EN
36
40
41
ANA
–
v
v
x
v
v
x
v
v
v
v
v
v
Input sleep clock:
32.768 kHz
I
I
PD
PD
PD
PD
1.8 V
1.8 V
Mode setting: high =
enable
Mode setting: high =
enable
Power-Management Signals
VIO_IN
38
46
47
POW
POW
POW
PD
PD
1.8 V
VBAT
VBAT
v
v
v
v
v
v
v
v
v
v
v
v
Connect to 1.8-V
external VIO
VBAT_IN
VBAT_IN
Power supply input,
2.9 to 4.8 V
Power supply input,
2.9 to 4.8 V
TI Reserved
GPIO11
2
3
I/O
I/O
I/O
I/O
I
PD
PD
PU
PU
PD
PD
PD
PD
PD
PD
PU
PU
PD
PD
PD
PD
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
–
v
v
v
v
x
x
v
x
v
v
v
v
v
x
x
v
x
v
v
v
v
v
x
x
v
x
v
v
v
v
v
x
x
v
x
v
Reserved for future
use. NC if not used.
GPIO9
Reserved for future
use. NC if not used.
GPIO10
4
Reserved for future
use. NC if not used.
GPIO12
5
Reserved for future
use. NC if not used.
RESERVED1
RESERVED2
GPIO4
21
22
25
62
64
Reserved for future
use. NC if not used.
I
Reserved for future
use. NC if not used.
I/O
O
Reserved for future
use. NC if not used.
RESERVED3
RESERVED
Reserved for future
use. NC if not used.
GND
Reserved for future
use. NC if not used.
WLAN Functional Block: Int Signals
WL_SDIO_CMD_1V8
WL_SDIO_D0_1V8
WL_SDIO_D1_1V8
WL_SDIO_D2_1V8
6
I/O
I/O
I/O
IO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1.8 V
1.8 V
1.8 V
1.8 V
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
WLAN SDIO
command in(3)
10
11
12
WLAN SDIO data bit
0(3)
WLAN SDIO data bit
1(3)
WLAN SDIO data bit
2(3)
(1) PU = pullup; PD = pulldown.
(2) v = connect; x = no connect.
(3) Host must provide PU using a 10-K resistor for all non-CLK SDIO signals.
Copyright © 2013–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
7
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ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
www.ti.com.cn
Table 4-1. Pin Description (continued)
PIN NAME
PIN
TYPE/ SHUTDOWN
AFTER
POWER
UP(1)
VOLTAG
E LEVEL
CONNECTIVITY(2)
DESCRIPTION
DIR
STATE
1801 1805 1831 1835
WL_SDIO_D3_1V8
13
I/O
Hi-Z
PU
1.8 V
v
v
v
v
WLAN SDIO data bit
3. Changes state to
PU at WL_EN or
BT_EN assertion for
card detects. Later
disabled by software
during initialization.
(1)
WL_IRQ_1V8
14
O
PD
0
1.8 V
v
v
v
v
SDIO available,
interrupt out. Active
high. (For
WL_RS232_TX/RX
pullup is at power
up.) Set to rising
edge (active high) on
power up. The Wi-Fi
interrupt line can be
configured by the
driver according to
the IRQ configuration
(polarity/level/edge).
GPIO2
26
I/O
PD
PD
PU
PD
PD
PU
1.8 V
v
v
v
v
WL_RS232_RX
(when WLAN_IRQ =
1 at power up)
2G4_ANT2_W
GPIO1
18
27
ANA
I/O
–
x
v
v
v
x
v
v
v
2.4G ant2 TX, RX
1.8 V
WL_RS232_TX
(when WLAN_IRQ =
1 at power up)
2G4_ANT1_WB
WL_UART_DBG
32
42
ANA
O
–
v
v
v
v
v
v
v
v
2.4G ant1 TX, RX
1.8 V
Option: WLAN logger
Bluetooth Functional Block: Int Signals
BT_UART_DBG
BT_HCI_RTS_1V8
BT_HCI_CTS_1V8
BT_HCI_TX_1V8
BT_HCI_RX_1V8
BT_AUD_IN
43
50
51
52
53
56
O
O
I
PU
PU
PU
PU
PU
PD
PU
PU
PU
PU
PU
PD
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
x
x
x
x
x
x
x
x
x
x
x
x
v
v
v
v
v
v
v
v
v
v
v
v
Option: Bluetooth
logger
UART RTS to host.
NC if not used.
UART CTS from
host. NC if not used.
O
I
UART TX to host. NC
if not used.
UART RX from host.
NC if not used.
I
Bluetooth PCM/I2S
bus. Data in. NC if
not used.
BT_AUD_OUT
BT_AUD_FSYNC
BT_AUD_CLK
57
58
60
O
PD
PD
PD
PD
PD
PD
1.8 V
1.8 V
1.8 V
x
x
x
x
x
x
v
v
v
v
v
v
Bluetooth PCM/I2S
bus. Data out. NC if
not used.
I/O
I/O
Bluetooth PCM/I2S
bus. Frame sync. NC
if not used.
Bluetooth PCM/I2S
bus. NC if not used.
8
Terminal Configuration and Functions
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PIN NAME
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
Table 4-1. Pin Description (continued)
PIN
TYPE/ SHUTDOWN
AFTER
POWER
UP(1)
VOLTAG
E LEVEL
CONNECTIVITY(2)
DESCRIPTION
DIR
STATE
1801 1805 1831 1835
Ground Pins
GND
1, 7, 9,
15, 16,
17, 19,
20, 23,
24, 28,
29, 30,
31, 33,
34, 35,
37, 39,
44, 45,
48, 49,
54, 55,
59, 61,
63, G1-
G36
GND
–
v
v
v
v
Copyright © 2013–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
9
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ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
www.ti.com.cn
5 Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VALUE
4.8(2)
UNIT
V
VBAT
VIO
–0.5 to 2.1
V
Input voltage to analog pins
Input voltage limits (CLK_IN)
Input voltage to all other pins
Operating ambient temperature range
–0.5 to 2.1
V
–0.5 to VDD_IO
–0.5 to (VDD_IO + 0.5 V)
–20 to +70(3)
V
V
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) 4.8 V cumulative to 2.33 years, including charging dips and peaks
(3) Operating free-air temperature range at which the device can operate reliably for 15K cumulative active TX power-on hours (assuming a
maximum junction temperature of (Tj) of 125°C). Section 5.3, Power-On Hours (POH), describes the correlation between Tj and PoH. In
the WL18xx system, a control mechanism automatically ensures Tj < 125°C. Whenever Tj approaches the threshold, this mechanism
controls the transmitter patterns.
5.2 Handling Ratings
MIN
–40
MAX
+85
UNIT
Tstg
Storage temperature range
Human body model (HBM)(2)
Charged device model (CDM)(3)
°C
ESD stress voltage(1)
–1000
–250
+1000
+250
V
(1) ESD measures device sensitivity and immunity to damage caused by electrostatic discharges into the device.
(2) The level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible, if necessary precautions
are taken. Pins listed as 1000 V can actually have higher performance.
(3) The level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 250-V CDM is possible, if necessary precautions
are taken. Pins listed as 250 V can actually have higher performance.
5.3 Power-On Hours (POH)
OPERATING JUNCTION TEMPERATURE (°C)
POH
125
120
115
110
105
15,000
20,000
27,000
37,000
50,000
5.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.9
NOM
MAX
4.8
UNIT
V
VBAT(1)
DC supply range for all modes
1.8-V I/O ring power supply
voltage
1.62
1.95
V
VIH
I/O high-level input voltage
0.65 x
VDD_IO
VDD_IO
V
V
V
VIL
I/O low-level input voltage
0
0.35 ×
VDD_IO
VIH_EN
Enable inputs high-level input
voltage
1.365
VDD_IO
(1) 4.8 V is applicable only for 2.3 years (30% of the time). Otherwise, maximum VBAT must not exceed 4.3 V.
10 Specifications
Copyright © 2013–2014, Texas Instruments Incorporated
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ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIL_EN
VOH
Enable inputs low-level input
voltage
0
0.4
V
High-level output voltage
@ 4 mA
@ 4 mA
VDD_IO
–0.45
VDD_IO
V
VOL
Low-level output voltage
0
1
0.45
10
V
Tr,Tf
Input transitions time Tr,Tf from
10% to 90% (digital I/O)(2)
ns
Tr
Tf
Output rise time from 10% to
90% (digital pins)(2)
CL < 25 pF
CL < 25 pF
5.3
4.9
ns
ns
Output fall time from 10% to
90% (digital pins)(2)
Ambient operating temperature
WLAN operation
–20
70
2.8
0.2
ºC
W
Maximum power dissipation
Bluetooth operation
(2) Applies to all digital lines except SDIO, UART, I2C, PCM and slow clock lines
5.5 External Digital Slow Clock Requirements
The supported digital slow clock is 32.768 kHz digital (square wave). All core functions share a single input.
PARAMETER
CONDITION
SYMBOL
MIN
TYP
MAX
UNIT
Input slow clock frequency
32768
Hz
Input slow clock accuracy (Initial + WLAN, Bluetooth
temp + aging)
±250
200
ppm
Input transition time Tr,Tf (10% to
90%)
Tr,Tf
ns
Frequency input duty cycle
15
50
85
%
Input voltage limits
Square wave, DC-
coupled
Vih
Vil
0.65 x VDD_IO
VDD_IO
Vpeak
0
1
0.35 x VDD_IO
Input impedance
Input capacitance
MΩ
5
pF
5.6 Thermal Characteristics
AIR FLOW
NAME
DESCRIPTION
FCBGA (°C/W)(1)
θJC
θJB
θJA
φJB
Junction to case
12.7
13.6
20.5
8.7
Junction to board
Junction to free air(2)
Junction to board
(1) °C/W = degrees Celsius per watt
(2) According to the JEDEC EIA/JESD 51 document
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5.7 WLAN Performance
All RF and performance numbers are aligned to the module pin.
5.7.1 WLAN 2.4-GHz Receiver Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
MHz
dBm
Operation frequency range
2400 to 2480
2400
2480
Sensitivity: 20-MHz bandwidth. At < 10%
PER limit
1 Mbps DSSS
2 Mbps DSSS
5.5 Mbps CCK
11 Mbps CCK
6 Mbps OFDM
9 Mbps OFDM
12 Mbps OFDM
18 Mbps OFDM
24 Mbps OFDM
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
MCS0 MM 4K
MCS1 MM 4K
MCS2 MM 4K
MCS3 MM 4K
MCS4 MM 4K
MCS5 MM 4K
MCS6 MM 4K
MCS7 MM 4K
MCS0 MM 4K 40 MHz
MCS7 MM 4K 40 MHz
MCS0 MM 4K MRC
MCS7 MM 4K MRC
MCS13 MM 4K
MCS14 MM 4K
MCS15 MM 4K
OFDM (11g/n)
DSSS
–96.3
–93.2
–90.6
–87.9
–92.0
–90.4
–89.5
–87.2
–84.1
–80.7
–76.5
–74.9
–90.4
–87.6
–85.9
–82.8
–79.4
–75.2
–73.5
–72.4
–86.7
–67.0
–92.7
–75.2
–73.7
–72.3
–71.0
–9
Max Input Level At < 10% PER limit
–19
–4
dBm
dBm
dB
–0
Adjacent channel rejection: Sensitivity level
+3 dB for OFDM; Sensitivity level +6 dB for
11b
2 Mbps DSSS
11 Mbps CCK
54 Mbps OFDM
42.7
37.9
2.0
dB
dB
12
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5.7.2 WLAN 2.4-GHz Transmitter Power
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
RF_IO2_BG_WL pin 2.4-GHz SISO
Output Power:
Maximum RMS
output power
measured at 1 dB
from IEEE spectral
mask or EVM(1)
1 Mbps DSSS
2 Mbps DSSS
5.5 Mbps CCK
11 Mbps CCK
6 Mbps OFDM
9 Mbps OFDM
12 Mbps OFDM
18 Mbps OFDM
24 Mbps OFDM
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
MCS0 MM
17.3
17.3
17.3
17.3
17.1
17.1
17.1
17.1
16.2
15.3
14.6
13.8
16.1
16.1
16.1
16.1
15.3
14.6
13.8
12.6
14.8
11.3
dBm
MCS1 MM
MCS2 MM
MCS3 MM
MCS4 MM
MCS5 MM
MCS6 MM
MCS7 MM(2)
MCS0 MM 40 MHz
MCS7 MM 40 MHz
2G4_ANT2_W + 2G4_ANT1_WB 2.4-GHz MIMO
MCS12 (WL18x5)
MCS13 (WL18x5)
MCS14 (WL18x5)
MCS15 (WL18x5)
18.5
17.4
dBm
MHz
14.5
13.4
2G4_ANT2_W + 2G4_ANT1_WB Pins
Operation frequency
range
2412
2484
Return loss
–10.0
50.0
dB
Reference input
impedance
Ω
(1) Regulatory constraints limit TI module output power to the following:
•
•
•
•
Channels 1, 11, 13 @ OFDM legacy and HT 20-MHz rates: 14 dBm
Channels 1, 11, 13 @ HT 40-MHz lower primary rates: 12 dBm
Channel 7 @ HT 40-MHz lower primary rates: 12 dBm
Channel 5 @ HT 40-MHz upper primary rates: 12 dBm
(2) To ensure compliance with the EVM conditions specified in the PHY chapter of IEEE Std 802.11™ – 2012:
•
•
MCS7 20 MHz channel 12 output power is 2 dB lower than the typical value.
MCS7 20 MHz channel 8 output power is 1 dB lower than the typical value.
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Specifications
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5.7.3 WLAN Currents
SPECIFICATION ITEMS
TYP (AVG) – 25°C
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Receiver
Low-power mode (LPM) 2.4-GHz RX SISO20 single chain
2.4 GHz RX search SISO20
49
54
2.4-GHz RX search MIMO20
74
2.4-GHz RX search SISO40
59
2.4-GHz RX 20 M SISO 11 CCK
56
2.4-GHz RX 20 M SISO 6 OFDM
61
2.4-GHz RX 20 M SISO MCS7
65
2.4-GHz RX 20 M MRC 1 DSSS
74
2.4-GHz RX 20 M MRC 6 OFDM
81
2.4-GHz RX 20 M MRC 54 OFDM
2.4-GHz RX 40 MHz MCS7
85
77
Transmitter
2.4-GHz TX 20 M SISO 6 OFDM 15.4 dBm
2.4-GHz TX 20 M SISO 11 CCK 15.4 dBm
2.4-GHz TX 20 M SISO 54 OFDM 12.7 dBm
2.4-GHz TX 20 M SISO MCS7 11.2 dBm
2.4-GHz TX 20 M MIMO MCS15 11.2 dBm
2.4-GHz TX 40 M SISO MCS7 8.2 dBm
285
273
247
238
420
243
space
5.8 Bluetooth Performance
All RF and performance numbers are aligned to the module pin.
5.8.1 Bluetooth BR, EDR Receiver Characteristics—In-Band Signals
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Bluetooth BR, EDR operation
2402
2480
MHz
frequency range
Bluetooth BR, EDR channel
1
MHz
spacing
Bluetooth BR, EDR input
50
Ω
impedance
Bluetooth BR, EDR
sensitivity(1)
dirty TX on
BR, BER = 0.1%
–92.2
–91.7
–84.7
dBm
dBm
dBm
EDR2, BER = 0.01%
EDR3, BER = 0.01%
EDR2
Bluetooth EDR BER floor at
sensitivity + 10 dB
Dirty TX off (for 1,600,000
bits)
1e-6
1e-6
EDR3
Bluetooth BR, EDR maximum BR, BER = 0.1%
–5.0
–15.0
–15.0
–36.0
dBm
dBm
dBm
dBm
usable input power
EDR2, BER = 0.1%
EDR3, BER = 0.1%
Bluetooth BR intermodulation Level of interferers for n = 3, 4, and 5
–30.0
(1) Sensitivity degradation up to –3 dB may occur due to fast clock harmonics with dirty TX on.
14 Specifications
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PARAMETER
CONDITION
MIN
TYP
MAX
10
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bluetooth BR, EDR C/I
performance
Numbers show wanted
signal-to-interfering-signal
ratio. Smaller numbers
indicate better C/I
BR, co-channel
EDR, co-channel
EDR2
EDR3
12
20
BR, adjacent ±1 MHz
–3.0
–3.0
2.0
EDR, adjacent ±1 MHz,
(image)
EDR2
EDR3
performances (Image
frequency = –1 MHz)
BR, adjacent +2 MHz
EDR, adjacent +2 MHz
–33.0
–33.0
–28.0
–20.0
–20.0
–13.0
–42.0
–42.0
–36.0
EDR2
EDR3
BR, adjacent –2 MHz
EDR, adjacent –2 MHz
EDR2
EDR3
BR, adjacent ≥Ι±3Ι MHz
EDR, adjacent ≥Ι±3Ι MHz
EDR2
EDR3
Bluetooth BR, EDR RF return
–10.0
loss
5.8.2 Bluetooth Transmitter, BR
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
12.7
7.2
MAX
UNIT
BR RF output power(1)
VBAT ≥ 3 V
dBm
dBm
dB
VBAT < 3 V
BR gain control range
BR power control step
30.0
5.0
dB
BR adjacent channel power |M-N| = 2
BR adjacent channel power |M-N| > 2
–43.0
–48.0
dBm
dBm
(1) Values reflect maximum power. Reduced power is available using a vendor-specific (VS) command.
5.8.3 Bluetooth Transmitter, EDR
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
7.2
MAX
UNIT
EDR output power(1)
VBAT ≥ 3 V
dBm
VBAT < 3 V
5.2
EDR relative power
dB
dB
EDR gain control range
EDR power control step
30
5
dB
EDR adjacent channel power |M-N| = 1
EDR adjacent channel power |M-N| = 2
EDR adjacent channel power |M-N| > 2
–36
–30
–42
dBc
dBm
dBm
(1) Values reflect default maximum power. Max power can be changed using a VS command.
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5.8.4 Bluetooth Modulation, BR
over operating free-air temperature range (unless otherwise noted)
CHARACTERISTICS
BR –20 dB bandwidth
BR modulation characteristics
CONDITION(1)
MIN
TYP
925
160
MAX
995
UNIT
kHz
∆f1avg
Mod data = 4 1s, 4
145
170
kHz
0s:
111100001111...
∆f2max ≥ limit for
at least 99.9% of
all Δf2max
Mod data =
1010101...
120
130
88
kHz
∆f2avg, ∆f1avg
85
%
BR carrier frequency drift
One slot packet
–25
–35
25
35
kHz
kHz
Three and five slot
packet
BR drift rate
lfk+5 – fkl , k =
0 …. max
15
kHz/50 µs
kHz
BR initial carrier frequency tolerance(2)
f0–fTX
±75
±75
(1) Performance values reflect maximum power.
(2) Numbers include XTAL frequency drift over temperature and aging.
5.8.5 Bluetooth Modulation, EDR
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
EDR carrier frequency stability
EDR initial carrier frequency tolerance(2)
EDR RMS DEVM
CONDITION
MIN
–5
TYP
MAX
UNIT
kHz
kHz
%
5
±75
15
10
30
20
25
18
±75
EDR2
EDR3
EDR2
EDR3
EDR2
EDR3
4
4
%
EDR 99% DEVM
EDR peak DEVM
%
%
9
9
%
%
(1) Performance values reflect maximum power.
(2) Numbers include XTAL frequency drift over temperature and aging.
5.9 Bluetooth LE Performance
All RF and performance numbers are aligned to the module pin.
5.9.1 Bluetooth LE Receiver Characteristics – In-Band Signals
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Bluetooth LE operation frequency range
Bluetooth LE channel spacing
Bluetooth LE input impedance
CONDITION(1)
MIN
TYP
MAX
UNIT
MHz
MHz
Ω
2402
2480
2
50
Bluetooth LE sensitivity(2)
–92.2
dBm
Dirty TX on
Bluetooth LE maximum usable input power
–5
dBm
dBm
Bluetooth LE intermodulation characteristics Level of interferers.
–36
–30
For n = 3, 4, 5
(1) BER of 0.1% corresponds to PER of 30.8% for a minimum of 1500 transmitted packets, according to the Bluetooth LE test specification.
(2) Sensitivity degradation of up to –3 dB can occur due to fast clock harmonics.
16
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PARAMETER
CONDITION(1)
LE, co-channel
MIN
TYP
MAX
12
UNIT
Bluetooth LE C/I performance.
dB
Note: Numbers show wanted signal-to-
interfering-signal ratio. Smaller numbers
indicate better C/I performance.
LE, adjacent ±1 MHz
LE, adjacent +2 MHz
LE, adjacent –2 MHz
LE, adjacent ≥ |±3|MHz
0
–38
–15
–40
Image = –1 MHz
5.9.2 Bluetooth LE Transmitter Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Bluetooth LE RF output power(1)
MIN
TYP
MAX
UNIT
dBm
dBm
dBm
dBm
VBAT ≥ 3 V
10.0
7.2
VBAT < 3 V
Bluetooth LE adjacent channel power |M-N| = 2
Bluetooth LE adjacent channel power |M-N| > 2
–51.0
–54.0
(1) To reduce the maximum BLE power, use a VS command. The optional extra margin is offered to compensate for design losses, such as
trace and filter losses, and to achieve the maximum allowed output power at system level.
5.9.3 Bluetooth LE Modulation Characteristics
over operating free-air temperature range (unless otherwise noted)
CHARACTERISTICS
CONDITION(1)
MIN
TYP
MAX
UNIT
Bluetooth LE modulation
∆f1avg
Mod data = 4 1s, 4 0s:
240
250
260
kHz
characteristics
111100001111...
∆f2max ≥ limit for at
least 99.9% of all
Δf2max
Mod data = 1010101...
195
215
90
kHz
∆f2avg, ∆f1avg
85
%
Bluetooth LE carrier frequency lf0 – fnl , n = 2,3 …. K
–25
25
kHz
drift
Bluetooth LE drift rate
lf1 – f0l and lfn – fn-5l ,n = 6,7…. K
fn – fTX
15
kHz/50 µs
kHz
LE initial carrier frequency
tolerance(2)
±75
±75
(1) Performance values reflect maximum power.
(2) Numbers include XTAL frequency drift over temperature and aging.
5.10 Bluetooth-BLE Dynamic Currents
Current is measured at output power as follows:
•
•
BR at 12.7 dBm
EDR at 7.2 dBm
space
USE CASE(1) (2)
TYP
11.6
5.9
UNIT
BR voice HV3 + sniff
mA
mA
µA
EDR voice 2-EV3 no retransmission + sniff
Sniff 1 attempt 1.28 s
178.0
10.4
7.5
EDR A2DP EDR2 (master). SBC high quality – 345 Kbs
EDR A2DP EDR2 (master). MP3 high quality – 192 Kbs
Full throughput ACL RX: RX-2DH5(3)(4)
Full throughput BR ACL TX: TX-DH5(4)
Full throughput EDR ACL TX: TX-2DH5(4)
mA
mA
mA
mA
mA
18.0
50.0
33.0
(1) The role of Bluetooth in all scenarios except A2DP is slave.
(2) CL1P5 PA is connected to VBAT, 3.7 V.
(3) ACL RX has the same current in all modulations.
(4) Full throughput assumes data transfer in one direction.
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USE CASE(1) (2)
TYP
253.0
332.0
UNIT
Page scan or inquiry scan (scan interval is 1.28 s or 11.25 ms, respectively)
Page scan and inquiry scan (scan interval is 1.28 s and 2.56 s, respectively)
µA
µA
5.11 Bluetooth LE Currents
All current measured at output power of 7.2 dBm
USE CASE(1)
Advertising, not connectable(2)
Advertising, discoverable(2)
TYP
131
143
266
124
132
UNIT
µA
µA
Scanning(3)
µA
Connected, master role, 1.28-s connect interval(4)
µA
(4)
Connected, slave role, 1.28-s connect interval
µA
(1) CL1p% PA is connected to VBAT, 3.7 V.
(2) Advertising in all three channels, 1.28-s advertising interval, 15 bytes advertise data
(3) Listening to a single frequency per window, 1.28-s scan interval, 11.25-ms scan window
(4) Zero slave connection latency, empty TX and RX LL packets
5.12 Timing and Switching Characteristics
5.12.1 Power Management
5.12.1.1 Block Diagram – Internal DC2DCs
The device incorporates three internal DC2DCs (switched-mode power supplies) to provide efficient internal
supplies, derived from VBAT
.
WL18xx TOP LEVEL
VIO_IN
VIO
VBAT
VBAT_IN_MAIN_DC2DC
VBAT_IN_PA_DC2DC
VBAT
VBAT
PA_DC2DC_OUT
FB_IN_PA_DC2DC
MAIN_DC2DC_OUT
LDO_IN_DIG
SW
FB
SW
PA
DC2DC
Main DC2DC
FB
2.2–2.7 V
1.8V
DIG_DC2DC_OUT
VDD_DIG
SW
FB
Digital DC2DC
1V
Figure 5-1. Internal DC2DCs
5.12.2 Power-Up and Shut-Down States
The correct power-up and shut-down sequences must be followed to avoid damage to the device.
While VBAT or VIO or both are deasserted, no signals should be driven to the device. The only exception is the
slow clock that is a fail-safe I/O.
While VBAT, VIO, and slow clock are fed to the device, but WL_EN is deasserted (low), the device is in
SHUTDOWN state. In SHUTDOWN state all functional blocks, internal DC2DCs, clocks, and LDOs are disabled.
To perform the correct power-up sequence, assert (high) WL_EN. The internal DC2DCs, LDOs, and clock start
to ramp and stabilize. Stable slow clock, VIO, and VBAT are prerequisites to the assertion of one of the enable
signals.
18
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To perform the correct shut-down sequence, deassert (low) WL_EN while all the supplies to the device (VBAT
,
VIO, and slow clock) are still stable and available. The supplies to the chip (VBAT and VIO) can be deasserted only
after both enable signals are deasserted (low).
Figure 5-2 shows the general power scheme for the module, including the powerdown sequence.
VBAT
1
VIO
5
5
SCLK (32 KHz)
>10 µs
2
>10 µs
4
3
WL EN
t60 µst
NOTE: 1. Either VBAT or VIO can come up first.
NOTE: 2. VBAT and VIO supplies and slow clock (SCLK), must be stable prior to EN being asserted and at all times
NOTE: when the EN is active.
NOTE: 3. At least 60 µs is required between two successive device enables. The device is assumed to be in
NOTE: shutdown state during that period, meaning all enables to the device are LOW for that minimum duration.
NOTE: 4. EN must be deasserted at least 10 µs before VBAT or VIO supply can be lowered. (Order of supply turn off
NOTE: after EN shutdown is immaterial)
NOTE: 5. SCLK - Fail safe I/O
Figure 5-2. Power-Up System
5.12.3 Chip Top-level Power-Up Sequence
VBAT / VIO
input
SLOWCLK
input
WL_EN
input
4.5msec delay
Main 1V8 DC2DC
DIG DC2DC
SRAM LDO
Top RESETZ
TCXO_CLK_REQ
output
Internal power stable = 5mS
Figure 5-3. Chip Top-Level Power-Up Sequence
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5.12.4 WLAN Power-Up Sequence
VBAT / VIO
input
SLOWCLK
input
WL_EN
input
TCXO_CLK_REQ
output
TXCO_LDO
output
TCXO
input
SDIO_CLK
input
Indicates completion of FW download
and Internal initialization
NLCP: trigger at rising edge
WLAN_IRQ
output
NLCP
Wake-up time
Indicates completion of FW download
and Internal initialization
WLAN_IRQ
output
MCP
Wake-up time
MCP: trigger at low level
Host configures device to
reverse WLAN_IRQ polarity
Figure 5-4. WLAN Power-Up Sequence
5.12.5 Bluetooth-BLE Power-Up Sequence
Figure 5-5 shows the Bluetooth-BLE power-up sequence.
Figure 5-5. Bluetooth/BLE Power-Up Sequence
20
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5.12.6 WLAN SDIO Transport Layer
The SDIO is the host interface for WLAN. The interface between the host and the WL18xx module uses an SDIO
interface and supports a maximum clock rate of 50 MHz.
The device SDIO also supports the following features of the SDIO V3 specification:
•
•
•
•
4-bit data bus
Synchronous and asynchronous in-band interrupt
Default and high-speed (HS, 50 MHz) timing
Sleep and wake commands
5.12.6.1 SDIO Timing Specifications
Figure 5-6 and Figure 5-7 show the SDIO switching characteristics over recommended operating conditions and
with the default rate for input and output.
tWH
tWL
VDD
VIH
VIH
VIH
Clock Input
VSS
VIL
VIL
tTHL
tTLH
tIH
tISU
VDD
VIH
VIH
Data Input
Not Valid
Valid
Not Valid
VIL
VIL
VSS
Figure 5-6. SDIO Default Input Timing
tTHL
VIH
tWL
tWH
VDD
VIH
VIH
Clock Input
VSS
VIL
VIL
tTLH
tODLY(max)
tODLY(min)
VDD
VOH
VOL
VOH
VOL
Data Output
VSS
Valid
Not Valid
Not Valid
Figure 5-7. SDIO Default Output Timing
Table 5-1 lists the SDIO default timing characteristics.
Table 5-1. SDIO Default Timing Characteristics(1)
PARAMETER(2)
MIN
0.0
MAX
26.0
60.0
10.0
10.0
UNIT
MHz
%
fclock
DC
tTLH
tTHL
tISU
tIH
Clock frequency, CLK
Low, high duty cycle
40.0
Rise time, CLK
ns
Fall time, CLK
ns
Setup time, input valid before CLK ↑
Hold time, input valid after CLK ↑
Delay time, CLK ↓ to output valid
Capacitive load on outputs
3.0
2.0
7.0
ns
ns
tODLY
Cl
10.0
15.0
ns
pF
(1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit.
(2) Parameter values reflect maximum clock frequency.
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5.12.6.2 SDIO Switching Characteristics – High Rate
Figure 5-8 and Figure 5-9 show the parameters for maximum clock frequency.
tWH
tWL
VDD
VIH
VIH
50% VDD
VIH
Clock Input
VSS
VIL
VIL
tTHL
tTLH
tISU
tIH
VDD
VIH
VIH
VIL
Data Input
Not Valid
Valid
Not Valid
VIL
VSS
Figure 5-8. SDIO HS Input Timing
tWL
tWH
tTHL
VIH
VDD
VIH
50% VDD
VIH
Clock Input
VSS
50% VDD
VIL
VIL
tTLH
tODLY(max)
tOH(min)
VDD
Data Output
VSS
VOH
VOH
Not Valid
Valid
Not Valid
VOL
VOL
Figure 5-9. SDIO HS Output Timing
Table 5-2 lists the SDIO high-rate timing characteristics.
Table 5-2. SDIO HS Timing Characteristics
PARAMETER
MIN
0.0
MAX
52.0
60.0
3.0
UNIT
MHz
%
fclock
DC
tTLH
tTHL
tISU
tIH
Clock frequency, CLK
Low, high duty cycle
40.0
Rise time, CLK
ns
Fall time, CLK
3.0
ns
Setup time, input valid before CLK ↑
Hold time, input valid after CLK ↑
Delay time, CLK ↑ to output valid
Capacitive load on outputs
3.0
2.0
7.0
ns
ns
tODLY
Cl
10.0
10.0
ns
pF
5.12.7 HCI UART Shared Transport Layers for All Functional Blocks (Except WLAN)
The device incorporates a UART module dedicated to the Bluetooth shared-transport, host controller interface
(HCI) transport layer. The HCI interface transports commands, events, and ACL between the Bluetooth device
and its host using HCI data packets acting as a shared transport for all functional blocks except WLAN.
space
WLAN
SHARED HCI FOR ALL FUNCTIONAL BLOCKS EXCEPT WLAN
BLUETOOTH VOICE-AUDIO
Bluetooth PCM
WLAN HS SDIO
Over UART
22
Specifications
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The HCI UART supports most baud rates (including all PC rates) for all fast-clock frequencies up to a maximum
of 4 Mbps. After power up, the baud rate is set for 115.2 kbps, regardless of the fast-clock frequency. The baud
rate can then be changed using a VS command. The device responds with a Command Complete Event (still at
115.2 kbps), after which the baud rate change occurs.
HCI hardware includes the following features:
•
•
•
•
Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions
Receiver-transmitter underflow detection
CTS, RTS hardware flow control
4 wire (H4)
Table 5-3 lists the UART default settings.
Table 5-3. UART Default Setting
PARAMETER
VALUE
Bit rate
115.2 kbps
8 bits
1
Data length
Stop bit
Parity
None
5.12.7.1 UART 4-Wire Interface – H4
The interface includes four signals:
•
•
•
•
TXD
RXD
CTS
RTS
Flow control between the host and the device is byte-wise by hardware.
When the UART RX buffer of the device passes the flow-control threshold, the buffer sets the UART_RTS signal
high to stop transmission from the host. When the UART_CTS signal is set high, the device stops transmitting on
the interface. If HCI_CTS is set high in the middle of transmitting a byte, the device finishes transmitting the byte
and stops the transmission.
Figure 5-10 shows the UART timing.
Figure 5-10. UART Timing Diagram
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Table 5-4 lists the UART timing characteristics.
Table 5-4. UART Timing Characteristics
PARAMETER
CONDITION
SYMBOL
MIN
37.5
–2.5
–12.5
0.0
TYP
MAX
4364
+1.5
UNIT
Kbps
%
Baud rate
Baud rate accuracy per byte
Baud rate accuracy per bit
CTS low to TX_DATA on
CTS high to TX_DATA off
CTS high pulse width
Receive-transmit
Receive-transmit
+12.5
%
t3
t4
t6
t1
t2
2.0
2.0
µs
Hardware flow control
1.0
Byte
Bit
1.0
0.0
RTS low to RX_DATA on
RTS high to RX_DATA off
µs
Interrupt set to 1/4 FIFO
16.0
Bytes
Figure 5-11 shows the UART data frame.
tb
TX
STR
STR-Start bit;
D0
D1
D2
Dn
PAR
STP
D0..Dn - Data bits (LSB first);
PAR - Parity bit (if used); STP - Stop bit
Figure 5-11. UART Data Frame
5.12.8 Bluetooth Codec-PCM (Audio) Timing Specifications
Figure 5-12 shows the Bluetooth codec-PCM (audio) timing diagram.
Figure 5-12. Bluetooth Codec-PCM (Audio) Master Timing Diagram
24
Specifications
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Table 5-5 lists the Bluetooth codec-PCM master timing characteristics.
Table 5-5. Bluetooth Codec-PCM Master Timing Characteristics
PARAMETER
SYMBOL
MIN
MAX
UNIT
Cycle time
Tclk
Ts
tis
162.76 (6.144 MHz)
15625 (64 kHz)
ns
High or low pulse width
AUD_IN setup time
35% of Tclk min
10.6
AUD_IN hold time
tih
0
0
0
AUD_OUT propagation time
FSYNC_OUT propagation time
Capacitive loading on outputs
top
top
Cl
15
15
40
pF
Table 5-6 lists the Bluetooth codec-PCM slave timing characteristics.
Table 5-6. Bluetooth Codec-PCM Slave Timing Characteristics
PARAMETER
SYMBOL
MIN
MAX
UNIT
Cycle time
Tclk
Tw
tis
81.38 (12.266 MHz)
ns
High or low pulse width
AUD_IN setup time
35% of Tclk min
5
0
5
0
0
AUD_IN hold time
tih
AUD_FSYNC setup time
AUD_FSYNC hold time
AUD_OUT propagation time
Capacitive loading on outputs
tis
tih
top
Cl
19
40
pF
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Specifications
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6 Detailed Description
The WiLink 8 module is a self-contained connectivity solution based on WiLink 8 connectivity. As the
eighth-generation connectivity combo chip from TI, the WiLink 8 module is based on proven technology.
Table 6-1 through Table 6-3 list performance parameters along with shutdown and sleep currents.
Table 6-1. WLAN Performance Parameters
WLAN(1)
SPECIFICATION (TYP)
17.3 dBm
–96.3 dBm
160 µA
CONDITIONS
1 Mbps DSSS
Maximum TX power
Minimum sensitivity
Sleep current
1 Mbps DSSS
Leakage, firmware retained
No traffic IDLE connect
Search (SISO20)
Connected IDLE
RX search
750 µA
54 mA
RX current (SISO20)
TX current (SISO20)(2)
65 mA
MCS7, 2.4 GHz
238 mA
MCS7, 2.4 GHz, +11.2 dBm
Maximum peak current consumption during calibration(3)
850 mA
(1) System design power scheme must comply with both peak and average TX bursts.
(2) WLAN maximum VBAT current draw of 725 mA with MIMO continues burst configuration.
(3) Peak current VBAT can hit 850 mA during device calibration.
•
•
•
At wakeup, the WiLink 8 module performs the entire calibration sequence at the center of the 2.4-GHz band.
Once a link is established, calibration is performed periodically (every 5 minutes) on the specific channel tuned.
The maximum VBAT value is based on peak calibration consumption with a 30% margin.
Table 6-2. Bluetooth Performance Parameters
BLUETOOTH
SPECIFICATION (TYP)
12.7 dBm
CONDITIONS
Maximum TX power
Minimum sensitivity
Sniff
GFSK
GFSK
–92.2 dBm
178 µA
1 attempt, 1.28 s (+4 dBm)
Page or inquiry
A2DP
253 µA
1.28-s interrupt, 11.25-ms scan window (+4 dBm)
MP3 high quality 192 kbps (+4 dBm)
7.5 mA
Table 6-3. Shutdown and Sleep Currents
PARAMETER
POWER SUPPLY CURRENT
TYP
10
UNIT
µA
Shutdown mode
VBAT
VIO
All functions shut down
2
µA
WLAN sleep mode
VBAT
VBAT
160
110
µA
Bluetooth sleep mode
µA
26
Detailed Description
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Figure 6-1 shows a high-level view of the WL1835MOD variant.
Figure 6-1. WL1835MOD High-Level System Diagram
6.1 WLAN
The device supports the following WLAN features:
•
•
Integrated 2.4-GHz power amplifiers (PAs) for a complete WLAN solution
Baseband processor: IEEE Std 802.11b/g and IEEE Std 802.11n data rates with 20- or 40-MHz SISO
and 20-MHz MIMO
•
•
Fully calibrated system (production calibration not required)
Medium access controller (MAC)
–
–
–
Embedded ARM® central processing unit (CPU)
Hardware-based encryption-decryption using 64-, 128-, and 256-bit WEP, TKIP, or AES keys
Requirements for Wi-Fi-protected access (WPA and WPA2.0) and IEEE Std 802.11i (includes
hardware-accelerated Advanced Encryption Standard [AES])
•
•
New advanced coexistence scheme with Bluetooth and BLE
2.4-GHz radio
–
–
Internal LNA and PA
IEEE Std 802.11b, 802.11g, and 802.11n
•
4-bit SDIO host interface, including high speed (HS) and V3 modes
6.2 Bluetooth
The device supports the following Bluetooth features:
•
•
Bluetooth 4.0 as well as CSA2
Concurrent operation and built-in coexisting and prioritization handling of Bluetooth, BLE, audio
processing, and WLAN
•
Dedicated audio processor supporting on-chip SBC encoding + A2DP
–
–
Assisted A2DP (A3DP): SBC encoding implemented internally
Assisted WB-speech (AWBS): modified SBC codec implemented internally
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6.3 BLE
The device supports the following BLE features:
•
•
•
•
Bluetooth 4.0 BLE dual-mode standard
All roles and role combinations, mandatory as well as optional
Up to 10 BLE connections
Independent LE buffering allowing many multiple connections with no affect on BR-EDR performance
6.4 WiLink 8 Module Markings
Figure 6-2 shows the markings for the TI WiLink 8 module.
Model: WL18 MODGB
Test Grade:&&
FCC ID: Z64-WL18SBMOD
-
IC: 451I WL18SBMOD
LTC: YYWW SSF
R 201-135370
Figure 6-2. WiLink 8 Module Markings
Table 6-4 describes the WiLink 8 module markings.
Table 6-4. Description of WiLink 8 Module Markings
MARKING
WL18 MODGB
&&
DESCRIPTION
Model
Test grade (for more information, see Section 6.5, Test Grades)
FCC ID: single modular FCC grant ID
IC: single modular IC grant ID
Z64-WL18SBMOD
451I-WL18SBMOD
LTC (lot trace code):
•
•
•
•
YY = year (for example, 12 = 2012)
WW = week
YYWWSSF
201-135370
SS = serial number (01 to 99) matching manufacturer lot number
F = Reserved for internal use
R: single modular TELEC grant ID
TELEC compliance mark
CE compliance mark
CE
28
Detailed Description
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6.5 Test Grades
To minimize delivery time, TI may ship the device ordered or an equivalent device currently available that
contains at least the functions of the part ordered. From all aspects, this device will behave exactly the
same as the part ordered. For example, if a customer orders device WL1801MOD, the part shipped can
be marked with a test grade of 37, 07 (see Table 6-5).
Table 6-5. Test Grade Markings
MARK 1
0&
WLAN
Tested
BLUETOOTH
–
Tested
3&
Tested
MARK 2
&1
WLAN 2.4 GHz
Tested
MIMO 2.4 GHz
–
&5
Tested
Tested
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7 Applications and Implementation
7.1 Application Information
7.1.1 Typical Application – WL1835MOD Reference Design
Figure 7-1 shows the TI WL1835MOD reference design.
WLAN/BT Enable Control.
Connect to Host GPIO.
BT_EN
WLAN_EN
Reserved for DBG
TP1 TP2
VBAT_IN
VIO_IN
EXT_32K
ANT1
ANT016008LCD2442MA1
ANT-N3-1.6X0.8MM
C15
8pF
CAP1005
C4
10pF
CAP1005
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
GND
2G4_ANT1_WB
GND
FEED
BT_HCI_RTS_1V8
BT_HCI_CTS_1V8
BT_HCI_TX_1V8
BT_HCI_RX_1V8
2.4G
5G
BT_HCI_RTS
BT_HCI_CTS
BT_HCI_TX
BT_HCI_RX
GND
L1
1.1nH
IND1005
GND
C6
2pF
CAP1005
C7
NU_2.4pF
CAP1005
GND
GND
WL_RS232_TX_1V8
WL_RS232_RX_1V8
TP5
TP3
TP4
GPIO_1
GPIO_2
GPIO_4
GND
Connect to Host HCI Interface.
The value of antenna matching components
is for TMDXWL1835COM8T
GND
BT_AUD_IN
BT_AUD_IN
BT_AUD_OUT
BT_AUD_FSYNC
GND
U1
For Debug only
BT_AUD_OUT
BT_AUD_FSYNC
(X)WL1835MOD
E-13.4X13.3-N100_0.75-TOP
GND
TP6
TP7
RESERVED2
RESERVED1
GND
BT_AUD_CLK
BT_AUD_CLK
GND
ANT2
ANT016008LCD2442MA1
ANT-N3-1.6X0.8MM
C17
8pF
CAP1005
TP8
C8
10pF
CAP1005
Connect to Host BT PCM Bus.
RESERVED3
GND
GND
A
2G4_ANT2_W
GND
FEED
2.4G
5G
GND
L2
1.1nH
IND1005
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G1
G2
G3
G4
G5
G6
G7
G8
C10
2pF
CAP1005
C11
NU_3pF
CAP1005
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
The value of antenna matching components
is for TMDXWL1835COM8T
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
For Debug only
VIO_IN
R13
NU
RES1005
TP10TP11TP12TP13
WL_IRQ_1V8
WL_SDIO_D3_1V8
WL_SDIO_D2_1V8
WL_SDIO_D1_1V8
WL_SDIO_D0_1V8
WL_SDIO_CLK_1V8
WL_SDIO_CMD_1V8
Connect to Host SDIO Interface.
Figure 7-1. TI Module Reference Schematics
Table 7-1 lists the bill materials (BOM).
Table 7-1. Bill of Materials
DESCRIPTION
PART NUMBER
(X)WL1835MOD
PACKAGE
REFERENCE
QTY
MFR
TI WL 1835 WiFi/BT Module
13.4 x 13.3 x 2.0mm
1.6 mm x 0.8 mm
U1
1
2
TI
ANT/Chip/2.4, 5 GHz/Peak Gain >
5 dBi
ANT016008LCD2442MA1
ANT1, ANT2
TDK
IND 0402/1.2 nH/±0.3/0.12 Ω/300 mA
CAP 0402/2.0 pF/50 V/C0G/±0.25 pF
CAP 0402/8.2 pF/50 V/NPO/±0.5 pF
CAP 0402/10 pF/50 V/NPO/±5%
RES 0402/10K/±5% (debug only)
Hl1005-1C1N2SMT
C1005C0G1H020C
0402N8R2D500
0402
0402
0402
0402
0402
L1, L2
C8, C10
C15, C17
C4, C6
R13
2
2
2
2
1
ACX
Walsin
Walsin
Walsin
Walsin
0402N100J500LT
WR04X103 JTL
30
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7.1.2 Design Recommendations
This section describes the layout recommendations for the (X)WL1835 module, RF trace, and antenna.
Table 7-2 summarizes the layout recommendations.
Table 7-2. Layout Recommendations Summary
ITEM
DESCRIPTION
Thermal
1
2
3
4
5
6
The proximity of ground vias must be close to the pad.
Signal traces must not be run underneath the module on the layer where the module is mounted.
Have a complete ground pour in layer 2 for thermal dissipation.
Have a solid ground plane and ground vias under the module for stable system and thermal dissipation.
Increase the ground pour in the first layer and have all of the traces from the first layer on the inner layers, if possible.
Signal traces can be run on a third layer under the solid ground layer, which is below the module mounting layer.
RF Trace and Antenna Routing
7
8
The RF trace antenna feed must be as short as possible beyond the ground reference. At this point, the trace starts to radiate.
The RF trace bends must be gradual with an approximate maximum bend of 45 degrees with trace mitered. RF traces must not
have sharp corners.
9
RF traces must have via stitching on the ground plane beside the RF trace on both sides.
RF traces must have constant impedance (microstrip transmission line).
10
11
For best results, the RF trace ground layer must be the ground layer immediately below the RF trace. The ground layer must be
solid.
12
13
There must be no traces or ground under the antenna section.
RF traces must be as short as possible. The antenna, RF traces, and modules must be on the edge of the PCB product. The
proximity of the antenna to the enclosure and the enclosure material must also be considered.
Supply and IF
14
15
16
17
18
The power trace for VBAT must be at least 40-mil wide.
The 1.8-V trace must be at least 18-mil wide.
Make VBAT traces as wide as possible to ensure reduced inductance and trace resistance.
If possible, shield VBAT traces with ground above, below, and beside the traces.
SDIO signals traces (CLK, CMD, D0, D1, D2, and D3) must be routed in parallel to each other and as short as possible (less than
12 cm). In addition, every trace length must be the same as the others. There should be enough space between traces – greater
than 1.5 times the trace width or ground – to ensure signal quality, especially for the SDIO_CLK trace. Remember to keep these
traces away from the other digital or analog signal traces. TI recommends adding ground shielding around these buses.
19
SDIO and digital clock signals are a source of noise. Keep the traces of these signals as short as possible. If possible, maintain a
clearance around them.
7.1.3 RF Trace and Antenna Layout Recommendations
Figure 7-2 shows the location of the antenna on the WL1835MODCOM8 board as well as the RF trace
routing from the (X)WL1835 module (TI reference design). The TDK chip multilayer antennas are mounted
on the board with a specific layout and matching circuit for the radiation test conducted in FCC, CE, and
IC certifications.
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Antennas distance is Higher than
half wavelength.
Antennas are orthogonal
to each other.
76.00mm
Antenna placement on
the edge of the board.
Constant 50 OHM control
impedance RF Trace.
No sharp corners.
Figure 7-2. Location of Antenna and RF Trace Routing on the TMDXWL1835MODCOM8T Board
Follow these RF trace routing recommendations:
•
•
•
•
RF traces must have 50-Ω impedance.
RF traces must not have sharp corners.
RF traces must have via stitching on the ground plane beside the RF trace on both sides.
RF traces must be as short as possible. The antenna, RF traces, and module must be on the edge of
the PCB product in consideration of the product enclosure material and proximity.
7.1.4 Module Layout Recommendations
Figure 7-3 shows layer 1 and layer 2 of the TI module layout:
Layer 1
Layer 2 (Solid GND)
Figure 7-3. TI Module Layout
Follow these module layout recommendations:
•
Ensure a solid ground plane and ground vias under the module for stable system and thermal
dissipation.
32
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•
•
Do not run signal traces underneath the module on a layer where the module is mounted.
Signal traces can be run on a third layer under the solid ground layer and beneath the module
mounting.
•
•
Run the host interfaces with ground on the adjacent layer to improve the return path.
TI recommends routing the signals as short as possible to the host.
7.1.5 Thermal Board Recommendations
The TI module uses µvias for layers 1 through 6 with full copper filling, providing heat flow all the way
to the module ground pads.
TI recommends using one big ground pad under the module with vias all the way to connect the pad to
all ground layers (see Figure 7-4).
Module
COM8 Board
Figure 7-4. Block of Ground Pads on Bottom Side of Package
Figure 7-5 shows via array patterns, which are applied wherever possible to connect all of the layers to
the TI module central or main ground pads.
Figure 7-5. Via Array Patterns
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7.1.6 Baking and SMT Recommendations
7.1.6.1 Baking Recommendations
Follow these baking guidelines for the WiLink 8 module:
•
•
Follow MSL level 3 to perform the baking process.
After the bag is open, devices subjected to reflow solder or other high temperature processes must be
mounted within 168 hours of factory conditions (< 30°C/60% RH) or stored at <10% RH.
•
•
if the Humidity Indicator Card reads >10%, devices require baking before being mounted.
If baking is required, bake devices for 8 hours at 125 °C.
7.1.6.2 SMT Recommendations
Figure 7-6 shows the recommended reflow profile for the WiLink 8 module.
Temp
(degC)
D3
D2
T3
D1
T1
T2
Meating
Soldering
Cooling
Preheat
Time
(SeC)
Figure 7-6. Reflow Profile for the WiLink 8 Module
Table 7-3 lists the temperature values for the profile shown in Figure 7-6.
Table 7-3. Temperature Values for Reflow Profile
ITEM
TEMPERATURE (°C)
TIME (s)
Preheat
D1 to approximately D2: 140 to 200
D2: 220
T1: 80 to approximately 120
T2: 60 ±10
Soldering
Peak temperature
D3: 250 max
T3: 10
34
Applications and Implementation
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8 Device and Documentation Support
8.1 Device Support
8.1.1 Development Support
For a complete listing of development-support tools, visit the Texas Instruments WL18xx Wiki. For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
8.1.2 Device Support Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These
prefixes represent evolutionary stages of product development from engineering prototypes through fully
qualified production devices.
X
Experimental, preproduction, sample or prototype device. Device may not meet all product qualification conditions and
may not fully comply with TI specifications. Experimental/Prototype devices are shipped against the following disclaimer:
“This product is still in development and is intended for internal evaluation purposes.” Notwithstanding any provision to the
contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of
fitness for a specific purpose, of this device.
null Device is qualified and released to production. TI’s standard warranty applies to production devices.
8.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表 8-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
WL1801MOD
WL1805MOD
WL1831MOD
WL1835MOD
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
8.3 社区资源
下列链接提供到 TI 社区资源的连接。 链接的内容由各个分销商“按照原样”提供。 这些内容并不构成 TI 技术
规范和标准且不一定反映 TI 的观点；请见 TI 的使用条款。
TI E2E™ 在线社区 TI 工程师对工程师 (E2E) 社区。 此社区的创建目的是为了促进工程师之间协作。 在
e2e.ti.com 中，您可以咨询问题、共享知识、探索思路，在同领域工程师的帮助下解决问题。
德州仪器 (TI) 嵌入式处理器维基网站 德州仪器 (TI) 嵌入式处理器维基网站。 此网站的建立是为了帮助开发
人员从德州仪器 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体
知识的创新和增长。
8.4 商标
WiLink, E2E are trademarks of Texas Instruments.
ARM is a registered trademark of ARM Physical IP, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc..
Android is a trademark of Google Inc.
IEEE Std 802.11 is a trademark of IEEE.
Linux is a registered trademark of Linus Torvalds.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
All other trademarks are the property of their respective owners.
版权 © 2013–2014, Texas Instruments Incorporated
Device and Documentation Support
35
提交文档反馈意见
产品主页链接: WL1801MOD WL1805MOD WL1831MOD WL1835MOD
WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
www.ti.com.cn
8.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
36
Device and Documentation Support
版权 © 2013–2014, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: WL1801MOD WL1805MOD WL1831MOD WL1835MOD
WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
www.ti.com.cn
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
9 Mechanical Packaging and Orderable Information
9.1 TI Module Mechanical Outline
图 9-1 shows the mechanical outline for the device.
图 9-1. TI Module Mechanical Outline
表 9-1 lists the dimensions for the mechanical outline of the device.
表 9-1. Dimensions for TI Module Mechanical Outline
MARKING
MIN (mm) NOM (mm) MAX (mm)
MARKING
MIN (mm) NOM (mm) MAX (mm)
L (body size)
13.20
13.30
1.90
0.30
0.60
0.65
0.20
0.65
1.20
0.20
13.30
13.40
13.40
13.50
2.00
0.50
0.80
0.85
0.40
0.85
1.40
0.40
c2
c3
d1
d2
e1
e2
e3
e4
e5
e6
0.65
1.15
0.90
0.90
1.30
1.30
1.15
1.20
1.00
1.00
0.75
1.25
1.00
1.00
1.40
1.40
1.25
1.30
1.10
1.10
0.85
1.35
1.10
1.10
1.50
1.50
1.35
1.40
1.20
1.20
W (body size)
T (thickness)
a1
a2
a3
b1
b2
b3
c1
0.40
0.70
0.75
0.30
0.75
1.30
0.30
版权 © 2013–2014, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
37
提交文档反馈意见
产品主页链接: WL1801MOD WL1805MOD WL1831MOD WL1835MOD
WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
ZHCSC42J –JULY 2013–REVISED OCTOBER 2014
www.ti.com.cn
9.2 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
Mechanical Packaging and Orderable Information
版权 © 2013–2014, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: WL1801MOD WL1805MOD WL1831MOD WL1835MOD
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
WL1801MODGBMOCR
ACTIVE
QFM
QFM
QFM
QFM
QFM
QFM
QFM
MOC
100
100
100
100
100
100
100
1200
RoHS &
Non-Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-20 to 70
WL18MODGB
01
Z64-WL18SBMOD
451I-WL18SBMOD
201-135370
Samples
WL1801MODGBMOCT
WL1805MODGBMOCR
WL1805MODGBMOCT
WL1831MODGBMOCR
WL1831MODGBMOCT
WL1835MODGBMOCR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MOC
MOC
MOC
MOC
MOC
MOC
250
1200
250
RoHS &
Non-Green
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
WL18MODGB
01
Z64-WL18SBMOD
451I-WL18SBMOD
201-135370
Samples
Samples
Samples
Samples
Samples
Samples
RoHS &
Non-Green
WL18MODGB
05
Z64-WL18SBMOD
451I-WL18SBMOD
201-135370
RoHS &
Non-Green
WL18MODGB
05
Z64-WL18SBMOD
451I-WL18SBMOD
201-135370
1200
250
RoHS &
Non-Green
WL18MODGB
31
Z64-WL18SBMOD
451I-WL18SBMOD
201-135370
RoHS &
Non-Green
WL18MODGB
31
Z64-WL18SBMOD
451I-WL18SBMOD
201-135370
1200
RoHS &
Non-Green
WL18MODGB
35
Z64-WL18SBMOD
451I-WL18SBMOD
201-135370
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
WL1835MODGBMOCT
ACTIVE
QFM
MOC
100
250
RoHS (In
Work) & Green
(In Work)
Call TI
Level-3-260C-168 HR
-20 to 70
WL18MODGB
35
Z64-WL18SBMOD
451I-WL18SBMOD
201-135370
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
WL1801MODGBMOCR
WL1801MODGBMOCT
WL1805MODGBMOCR
WL1805MODGBMOCT
WL1831MODGBMOCR
WL1831MODGBMOCT
WL1835MODGBMOCR
WL1835MODGBMOCT
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
MOC
MOC
MOC
MOC
MOC
MOC
MOC
MOC
100
100
100
100
100
100
100
100
1200
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
13.8
13.8
13.8
13.8
13.8
13.8
13.8
13.8
13.8
13.8
13.8
13.8
13.8
13.8
13.8
13.8
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
1200
250
1200
250
1200
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
WL1801MODGBMOCR
WL1801MODGBMOCT
WL1805MODGBMOCR
WL1805MODGBMOCT
WL1831MODGBMOCR
WL1831MODGBMOCT
WL1835MODGBMOCR
WL1835MODGBMOCT
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
MOC
MOC
MOC
MOC
MOC
MOC
MOC
MOC
100
100
100
100
100
100
100
100
1200
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
55.0
55.0
55.0
55.0
55.0
55.0
55.0
55.0
1200
250
1200
250
1200
250
Pack Materials-Page 2
PACKAGE OUTLINE
QFM - 2.0 mm max height
QUAD FLAT MODULE
MOC0100A
13.4
13.2
A
B
1
PIN 1
INDEX AREA
13.5
13.3
C
2 MAX
0.08 C
2X 11.95
2X 9.8
7.7
TYP
17
56X
0.7
33
G36
G6
7.7
TYP
(1.4) TYP
SYMM
2X 9.8
G3
0.8
0.7
60X
2X 12.05
0.45
60X
G1
64
0.35
G7
G31
G19
0.1
C A B
C
0.05
1
49
PIN 2
ID
0.8
4X
SYMM
0.7
(1.4) TYP
1.05
0.95
36X
4221006/B 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
QFM - 2.0 mm max height
QUAD FLAT MODULE
MOC0100A
2X (11.95)
64
1
49
G7
G19
G25
G1
G13
G31
2X
(12.05)
SYMM
56X (0.7)
(1.05) TYP
(1.4) TYP
60X (0.75)
60X (0.4)
G12
G24
G30
G6
G18
G36
(1.4) TYP
(1.05) TYP
33
17
4X (0.75)
36X (1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 8X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK DETAILS
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
(R0.05) TYP
4221006/B 10/2016
NOTES: (continued)
4. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271)
.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, it is recommended
that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
QFM - 2.0 mm max height
QUAD FLAT MODULE
MOC0100A
2X (11.95)
64
1
49
G7
G19
G25
G31
G1
G13
60X (0.4)
60X (0.75)
2X
(12.05)
SYMM
56X (0.7)
(1.05) TYP
(1.4) TYP
SEE DETAIL B
G12
G24
G30
G6
G18
G36
(1.4) TYP
(1.05) TYP
33
17
SYMM
SEE DETAIL A
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PADS 1, 17, 33, 49, G1-G36
90% PRINTED COVERAGE BY AREA
SCALE: 8X
SOLDER
PASTE
SOLDER
PASTE
METAL UNDER
SOLDER MASK
METAL UNDER
SOLDER MASK
SOLDER
MASK
EDGE
SOLDER
MASK
4X (0.713)
36X (0.95)
DETAIL A
SCALE 20X
EDGE
DETAIL B
SCALE 20X
4221006/B 10/2016
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
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