XA2944BGALT [TI]
AWR2944 Single-Chip 76- and 81-GHz FMCW Radar Sensor;
| 型号： | XA2944BGALT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AWR2944 Single-Chip 76- and 81-GHz FMCW Radar Sensor |
| 文件： | 总93页 (文件大小：2256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AWR2944
SWRS273 – NOVEMBER 2021
AWR2944 Single-Chip 76- and 81-GHz FMCW Radar Sensor
•
On Chip RAM
– 3.5 – 4 MBytes (AWR2943 with 3.5MB &
AWR2944 with 4MB)
1 Features
•
FMCW transceiver
– Integrated PLL, Transmitter, Receiver,
Baseband and ADC
– Memory space split between DSP, MCU, and
shared L3
– 76-81 GHz coverage with 5GHz available
Bandwidth
•
Device Security (on select part numbers)
– Programmable embedded Hardware security
module (HSM)
– Secure authenticated and encrypted boot
support
– Customer programmable root keys, symmetric
keys (256 bit), Asymmetric keys (up to RSA-4K
or ECC-512) with Key revocation capability
– Crypto hardware accelerators - PKA with ECC,
AES (up to 256 bit), SHA (up to 512 bit), TRNG/
DRGB
Functional Safety-Compliant targeted
– Developed for functional safety applications
– Documentation will be available to aid ISO
26262 functional safety system design
– Hardware integrity up to ASIL B targeted
AEC-Q100 qualified
Advanced Features
– Embedded self-monitoring with no external
processor involvement
– Embedded interference detection capability
Power Management
– On die LDO network for enhanced PSRR
– LVCMOS IO supports dual voltage 3.3V/1.8V
Clock source
– 4 Receive and 3 – 4 Transmit channels
(AWR2943 with 3 channels & AWR2944 with
4 channels) for PCB interface to antennas
– Per Transmit phase shifter
– Ultra-Accurate Chirp engine based on
fractional-N PLL
– TX power
•
12 dBm
– RX noise Figure
13 dB
– Phase Noise @ 1MHz
•
•
•
•
-96 dBc/Hz [76 to 77 GHz]
-95 dBc/Hz [76 to 81 GHz]
•
•
Built in calibration and Self-Test
•
•
– Built in Firmware (ROM)
– Self-calibrating system across process and
temperature
Processing Elements
– ARM R5F ® Core [Supports lock step
operation]
– TI Digital Signal Processor C66x
– TI Radar Hardware Accelerator (HWA2.0) for
operations like FFT, Log Magnitude, memory
compression etc..
– Multiple EDMA Instances for Data Movement
Host Interface
•
•
– 40 MHz crystal with internal oscillator
– Supports external oscillator at 40 MHz
– Supports externally driven clock (Square/Sine)
at 40 MHz
Cost Reduced Hardware Design
– 0.65mm pitch, 12 mm × 12 mm flip chip BGA
package for easy assembly and low cost PCB
design
– Small solution size
Supports Automotive Temperature Operating
•
– 2x CAN-FD
•
•
– 10/100 Mbps RGMII/RMII/MII Ethernet
Supports a Serial Flash Memory Interface (loading
user application from QSPI flash memory)
Other Interfaces Available to User Application
– Up to 9 ADC Channels
– 2 SPIs
– 4 UARTs
– I2C
– GPIOs
•
•
Range
– Operating junction temperature range: –40°C to
140°C
– 3 EPWMs
– 4-Lane Aurora LVDS Interface for Raw ADC
Data and Debug Instrumentation
– CSI2 Rx interface to enable playback of the
captured data
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
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SWRS273 – NOVEMBER 2021
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2 Applications
•
•
•
•
•
Lane Change Assist
Blind Spot detection
Automatic Emergency Braking
Adaptive Cruise Control
Cross Traffic Alert
40-MHz
Crystal
Serial
Flash
Power Management
QSPI
Integrated MCU
ARM Cortex-R5F
Ethernet
PHY
Automotive
Network
Ethernet
Antenna
RX1
Structure
RX2
MCAN
PHY
Automotive
Network
CAN FD (2)
RX3
RX4
Radar
Front End
TX1
TX2
TX3
TX4
Integrated DSP
TI C66x
mmWave Sensor
Figure 2-1. Autonomous Radar Sensor For Automotive Applications
3 Description
The AWR294x is a single chip mmWave Sensor composed of a FMCW transceiver, capable of operation in the
76-81 GHz band, radar data processing elements, and peripherals for in-vehicle networking. It is built with TI’s
low power, 45 nm RFCMOS process and enables unprecedented levels of integration in a small form factor and
minimal BOM. AWR294x is an ideal solution for low power, self-monitored, ultra-accurate radar systems in the
automotive space.
TI’s low-power, 45-nm RFCMOS process enables a monolithic implementation of a 3-4 TX, 4 RX system
with integrated PLL, VCO, mixer, and baseband ADC. Integrated in the DSP Subsystem (DSS), is TI's high-
performance C66x DSP for radar signal processing. The device includes a Radio Processor Subsystem (RSS),
which is responsible for radar front-end configuration, control, and calibration. Within the Main Subsystem
(MSS), the device implements a user programmable ARM R5F allowing for custom control and automotive
interface applications. The Hardware Accelerator block (HWA 2.0) supplements the DSS and MSS by offloading
comon radar processing such as FFT, Constant False Alarm rate (CFAR), scaling, and compression. This saves
MIPS on the DSS and MSS, opening up resources for custom applications and higher level algorithms.
A Hardware Security Module (HSM) is also provisioned in the device (available for only Secure Part variants).
The HSM consists of a programmable ARM Cortex M4 core and the necessary infrastructure to provide a secure
zone of operation within the device.
Simple programming model changes can enable a wide variety of sensor implementation (Short, Mid, Long) with
the possibility of dynamic reconfiguration for implementing a multimode sensor.
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Additionally, the AWR294x device is provided as a complete platform solution including TI hardware and
software reference designs, software drivers, sample configurations, API guides, and user documentation.
Device Information
PART NUMBER
XA2943BGALT
XA2944BGALT
XA2944BDALT
XA2944BSALT
PACKAGE(1)
FCBGA (266)
FCBGA (266)
FCBGA (266)
FCBGA (266)
BODY SIZE (NOM)
12 mm × 12 mm
12 mm × 12 mm
12 mm × 12 mm
12 mm × 12 mm
(1) For more information, see Section 14, Mechanical, Packaging, and Orderable Information.
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3.1 Functional Block Diagram
Figure 3-1 represents the functional block diagram for the device.
9
GPADC
QSPI
Main Sub-System
(Customer Programmed)
Serial Flash Interface
LNA
LNA
LNA
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
Optional External
MCU Interface
SPI
ARM Cortex-R5F
(Lock Step)
@ 300 MHz
PMIC Control
Digital
Front-end
SPI / I2C
CAN-FD
Primary Communication
Interfaces (Automotive)
(Decimation
Filter Chain)
Prog
Cache
16KB
Data
Cache
16KB
L1 Data
RAM
128KB(A)
L2 RAM
960KB(A)
Debug
UARTs
For Debug
Test/
Debug
JTAG for Debug/
Development
DMA
Hardware Security
Module (B)
100Mbps Alternate Data
Communication Interface
PA
û-
û-
û-
û-
Ethernet
ADC
Buffer
Mailbox
PA
PA
PA
DSP Sub-System
(Customer Programmed)
Synth
(20 GHz)
Ramp
Generator
x4
C66x DSP Core
@ 360 MHz
Radio (BIST)
Processor
Aurora
LVDS
High-Speed ADC Output
Interface (for Recording)
High-Speed Interface to
enable playback of the
captured data
(For RF Calibration
& Self-Test œ TI
Programmed)
CSI2 RX
L1P L1D
(32KB) (32KB)
L2
(384KB)
Prog RAM
& ROM
Data
RAM
DMA
CRC
Radar Data Memory(A)
AWR2943 - 2.0MB /
AWR2944 - 2.5MB
Osc.
GPADC
VMON
Temp
Radio Processor
Sub-System
(TI Programmed)
Radar Hardware Accelerator
(FFT, Log mag, and others)
RF/Analog Sub-System
A. Configurable memory can be switched from Radar Data memory to the Main R5F program and Data RAMs per application usecase
needs.
B. This feature is only available in select part variants as indicated by the Device Type identifier in the Section 3, Device Information table.
Figure 3-1. Functional Block Diagram
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
3.1 Functional Block Diagram...........................................4
4 Revision History.............................................................. 5
5 Device Comparison.........................................................6
6 Related Products.............................................................8
7 Pin Configurations and Functions.................................9
7.1 Pin Diagram................................................................ 9
7.2 Pin Attributes.............................................................14
7.3 Signal Descriptions - Digital......................................26
7.4 Signal Descriptions - Analog.....................................33
8 Specifications................................................................ 35
8.1 Absolute Maximum Ratings...................................... 35
8.2 ESD Ratings............................................................. 35
8.3 Power-On Hours (POH) ...........................................36
8.4 Recommended Operating Conditions.......................36
8.5 VPP Specifications for One-Time Programmable
8.12 Peripheral Information.............................................43
8.13 Emulation and Debug............................................. 66
9 Detailed Description......................................................69
9.1 Overview...................................................................69
9.2 Functional Block Diagram.........................................69
9.3 Subsytems................................................................ 70
9.4 Other Subsystems.................................................... 74
10 Monitoring and Diagnostics....................................... 76
10.1 Monitoring and Diagnostic Mechanisms................. 76
11 Applications, Implementation, and Layout............... 81
11.1 Application Information............................................81
11.2 Short and Medium Range Radar............................ 81
11.3 Reference Schematic..............................................81
12 Device and Documentation Support..........................82
12.1 Device Support....................................................... 82
13 Device Nomenclature..................................................82
13.1 Tools and Software................................................. 83
13.2 Documentation support...........................................83
13.3 Support Resources................................................. 83
13.4 Trademarks.............................................................83
13.5 Electrostatic Discharge Caution..............................83
13.6 Glossary..................................................................83
14 Mechanical, Packaging, and Orderable
(OTP) eFuses..............................................................37
8.6 Power Supply Specifications.....................................38
8.7 Power Consumption Summary................................. 38
8.8 RF Specifications......................................................39
8.9 Thermal Resistance Characteristics ........................ 40
8.10 Power Supply Sequencing and Reset Timing.........41
8.11 Input Clocks and Oscillators....................................42
Information.................................................................... 84
4 Revision History
DATE
REVISION
NOTES
November 2021
*
APL Release
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5 Device Comparison
Table 5-1. Device Features Comparison
FUNCTION
AWR2943
AWR2944
AWR2243P
AWR1843
Number of receivers
Number of transmitters
On-chip memory
4
3
4
4
4
3(1)
—
4
3(1)
2MB
10
3.5MB
15
4MB
15
Max I/F (Intermediate Frequency) (MHz)
Max real/complex 2x sampling rate (Msps)
Max complex 1x sampling rate (Msps)
Safety and Security (3)
Device Security(4)
20
37.5 (2)
37.5 (2)
45
25
(2)
(2)
—
—
22.5
12.5
Yes
Yes
Yes
Yes
—
Yes
Yes
AEC-Q100 Qualified
Processor
Yes
MCU (RxF)
Yes(5)
Yes(6)
Yes(7)
Yes
Yes(5)
Yes(6)
Yes(7)
Yes
—
—
—
—
—
Yes
Yes
Yes
—
DSP (C6xx)
Hardware accelerator
Hardware Security Module (HSM) (8)
Security Accelerators (8)
Peripherals
Yes
Yes
Yes
Serial Peripheral Interface (SPI) ports
Quad Serial Peripheral Interface (QSPI)
LVDS/Debug
2
Yes
Yes
Yes
Yes
1
2
Yes
Yes
Yes
Yes
1
1
—
2
Yes
Yes
—
Yes
—
Aurora LVDS
Ethernet Interface
—
—
Inter-Integrated Circuit (I2C) interface
Controller Area Network (DCAN) interface
CAN FD
1
1
—
—
—
Yes
1
2
2
—
Trace
Yes
Yes
Yes
Yes(9)
—
Yes
Yes
Yes
Yes(9)
—
—
Yes
Yes
Yes
Yes
—
ePWM
—
DMM Interface
—
GPADC
Yes
Yes
—
CSI2 TX
CSI2 RX (10)
Yes
—
Yes
—
—
Cascade (20-GHz sync)
JTAG
Yes
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Per chirp configurable Tx phase shifter
Yes
PRODUCT PREVIEW (PP),
ADVANCE INFORMATION (AI),
or PRODUCTION DATA (PD)
Product
AI
AI
PD
PD
status(11)
(1) 3 Tx Simultaneous operation in AWR1843 and AWR2243P is supported only with 1V LDO bypass and PA LDO disable mode. In this
mode 1V supply needs to be fed on the VOUT PA pin. Please refer to the respective datasheets for more information.
(2) AWR294x supports a real only receiver.
(3) Developed for Functional Safety applications, the AWR294x device is targeted to support hardware integrity upto ASIL-B. For other
devices, refer to the respective Datasheets.
(4) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as
indicated by the Device Type identifier in the Section 3, Device Information table.
(5) In AWR294x, Main-Subsytem Processing core is changed from ARM CR4F in AWR1843 to ARM CR5F.
(6) The DSP processing core in AWR294x is upgraded from C67x in AWR1843 to C66x.
(7) The hardware accelerator in AWR294x is upgraded to HWA2.0 with additional features as compared to AWR1843.
(8) Only applicable for AWR294x Secure Part Variant
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(9) AWR294x has a dedicated GPADC for external voltage monitoring.
(10) AWR294x support CSI2 Rx based playback functionality .
(11) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of allparameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
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6 Related Products
For information about other devices in this family of products or related products see the links that follow.
mmWave Sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less
power using the smallest footprint mmWave sensor portfolio for automotive applications.
Automotive
TI’s automotive mmWave sensor portfolio offers high-performance radar front end to ultra-
mmWave Sensors high resolution, small and low-power single-chip radar solutions. TI’s scalable sensor
portfolio enables design and development of ADAS system solution for every performance,
application and sensor configuration ranging from comfort functions to safety functions in
all vehicles.
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7 Pin Configurations and Functions
7.1 Pin Diagram
Figure 7-1 shows the pin locations for the 12 x12 mm FCBGA package. Figure 7-2, Figure 7-3, Figure 7-4and
Figure 7-5 show the same pins, but split into four quadrants.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
MSS_UARTB DSS_UARTA
MSS_MCANB
_RX
A
B
C
D
E
F
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
OSC_CLKOUT
VSS
VIOIN
MSS_GPIO_1
VSS
_TX
_TX
DSS_UARTA
_RX
MSS_UARTA MSS_MCANB
CLKM
VSSA
CLKP
VSSA
VSSA
VSSA
VSSA
VSSA
RX4
TX1
VSSA
VSSA
TX2
VSSA
VSSA
TX3
VSSA
VSSA
TX4
VSSA
VSSA
VSSA
VSSA
NERROR_OUT
XREF_CLK1
VSS
WARM_RESET XREF_CLK0
MSS_GPIO_0
VIOIN
_RX
_TX
MSS_UARTA
MSS_EPWMB0MSS_EPWMA1
_TX
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
ADC1
ADC3
ADC5
VPP
VSSA
VSSA
TCK
TMS
MSS_MCANA MSS_MCANA
VDDA_10RF2 VDDA_10RF2
VDDA_18CLK
TDI
TDO
VIOIN_18
_RX
_TX
MSS_RS232
_TX
VDDA_18VCO
VDD
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VSS
VDD
VDD
VDD
VDD
VSS
VDD
VDD
MSS_EPWMA0
VSS
MSS_RS232
_RX
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VDD
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
LVDS_TXP0 LVDS_TXM0
LVDS_TXP2 LVDS_TXM2
VOUT
_14SYNTH
G
H
J
VSSA
VSSA
VSSA
VSSA
RX3
VSS
VSS
MSS_GPIO_2
_CLKP
_CLKM
VOUT
_14APLL
LVDS_TXP3 LVDS_TXM3
_FRCLKP _FRCLKM
VSS
VSS
NRESET
MSS_GPIO
_11
VSSA
RX2
VSS
VSS
LVDS_TXP1 LVDS_TXM1
VIOIN
_18LVDS
VIOIN
_18CSI
K
L
VBGAP
VSS
VSS
VSS
CSI2
_RX0CLKP
CSI2
_RX0CLKM
VSSA
RX1
VSS
VSS
MSS_GPIO_4
MSS_GPIO_9
MCU_CLKOUT
VIDDA
_10RF1
BSS_UARTA
_TX
M
N
P
R
T
VSS
VSS
CSI2_RX0P1 CSI2_RX0M1
CSI2_RX0P0 CSI2_RX0M0
VSSA
VDDA_18BB
VDDA_18PM
ADC7
VSSA
ADC2
ADC4
ADC8
ADC6
VSS
VSS
VSS
MSS_GPIO
VSS
VDD
VDD
VSS
MSS_GPIO_3
_30
MSS_MDIO
_CLK
MSS_RGMII
_TCTL
MSS_I2CA
_SDA
MSS_QSPI
_CLK
MSS_MIBSPIB
_CS2
MSS_GPIO
VIOIN
MSS_QSPI_3
_28
MSS_MDIO
_DATA
MSS_RGMII
_RCTL
MSS_RGMII
_RCLK
MSS_MIBSPIB
_CLK
MSS_MIBSPIA MSS_MIBSPIA
_CS0 _CLK
PMIC
MSS_QSPI_2
MSS_QSPI_0
MSS_QSPI_1
MSS_GPIO_8
_CLKOUT
MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII
_TD3
MSS_GPIO
_17
MSS_I2CA
_SCL
MSS_RGMII
_RD3
MSS_QSPI MSS_MIBSPIB MSS_MIBSPIB MSS_MIBSPIA MSS_MIBSPIA MSS_GPIO
U
V
ADC9
VIOIN_18
_TD1
_TD2
_TD0
_CS
_MISO
_CS0
_MOSI
_MISO
_31
MSS
_MIBSPIA
_HOSTIRQ
MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII
_TCLK _RD1 _RD2 _RD0
MSS_MIBSPIB
_MOSI
MSS_MIBSPIB
_CS1
VSSA
VDD_SRAM
VIOIN
VSS
VIOIN_18
VNWA
VSS
VIOIN
VSS
Not to scale
Figure 7-1. Pin Diagram
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1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VSSA
CLKM
VSSA
CLKP
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
RX4
TX1
VSSA
VSSA
TX2
VSSA
VSSA
TX3
VSSA
VSSA
TX4
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VDDA_10RF2 VDDA_10RF2
VDDA_18CLK
VDDA_18VCO
VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VOUT
_14SYNTH
G
H
VSSA
VSSA
RX3
VOUT
_14APLL
VSS
VSS
Not to scale
1
3
2
4
Figure 7-2. Top Left Quadrant
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10
11
12
13
14
15
16
17
18
MSS_UARTB DSS_UARTA
MSS_MCANB
_RX
A
B
C
D
E
F
VSSA
OSC_CLKOUT
VSS
VIOIN
MSS_GPIO_1
VSS
_TX
_TX
DSS_UARTA
_RX
MSS_UARTA MSS_MCANB
VSSA
VSSA
VSSA
NERROR_OUT
XREF_CLK1
VSS
WARM_RESET XREF_CLK0
MSS_GPIO_0
VIOIN
_RX
_TX
MSS_UARTA
_TX
TCK
TMS
MSS_EPWMB0MSS_EPWMA1
MSS_MCANA MSS_MCANA
TDI
TDO
VIOIN_18
_RX
_TX
MSS_RS232
_TX
VDD
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
VDD
MSS_EPWMA0
VSS
MSS_RS232
_RX
VSS
VSS
VSS
VSS
LVDS_TXP0 LVDS_TXM0
LVDS_TXP2 LVDS_TXM2
G
H
VSS
MSS_GPIO_2
_CLKP
_CLKM
LVDS_TXP3 LVDS_TXM3
_FRCLKP
VSS
NRESET
_FRCLKM
Not to scale
1
3
2
4
Figure 7-3. Top Right Quadrant
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1
2
3
4
5
6
7
8
9
J
VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
K
L
RX2
VSSA
RX1
VSSA
VSSA
VSSA
VSSA
ADC1
ADC3
ADC5
VPP
VBGAP
VSSA
VSSA
VSSA
VDD
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSSA
VIDDA
_10RF1
M
N
P
R
T
U
V
VSSA
VDDA_18BB
VDDA_18PM
ADC7
VSSA
ADC2
ADC4
ADC8
ADC6
VSS
VDD
MSS_MDIO
_CLK
MSS_RGMII
_TCTL
MSS_I2CA
_SDA
MSS_MDIO
_DATA
MSS_RGMII
_RCTL
MSS_RGMII
_RCLK
MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII
MSS_GPIO
_17
MSS_I2CA
_SCL
ADC9
_TD3
_TD1
_TD2
_TD0
MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII
_TCLK _RD1 _RD2 _RD0
VSSA
VDD_SRAM
VIOIN
VSS
Not to scale
1
3
2
4
Figure 7-4. Bottom Left Quadrant
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10
11
12
13
14
15
16
17
18
MSS_GPIO
_11
J
VSS
VSS
VSS
VSS
VDD
LVDS_TXP1 LVDS_TXM1
VIOIN
_18LVDS
VIOIN
_18CSI
K
L
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VSS
VDD
VDD
VSS
CSI2
_RX0CLKP
CSI2
_RX0CLKM
MSS_GPIO_4
MSS_GPIO_9
MCU_CLKOUT
BSS_UARTA
_TX
M
N
P
R
T
U
V
VSS
CSI2_RX0P1 CSI2_RX0M1
CSI2_RX0P0 CSI2_RX0M0
VSS
MSS_GPIO
VSS
VSS
MSS_GPIO_3
_30
MSS_QSPI
_CLK
MSS_MIBSPIB
_CS2
MSS_GPIO
VIOIN
MSS_QSPI_3
_28
MSS_MIBSPIB
_CLK
MSS_MIBSPIA MSS_MIBSPIA
_CS0 _CLK
PMIC
MSS_QSPI_2
MSS_QSPI_0
MSS_QSPI_1
MSS_GPIO_8
_CLKOUT
MSS_RGMII
_RD3
MSS_QSPI MSS_MIBSPIB MSS_MIBSPIB MSS_MIBSPIA MSS_MIBSPIA MSS_GPIO
VIOIN_18
_CS
_MISO
_CS0
_MOSI
_MISO
_31
MSS
_MIBSPIA
_HOSTIRQ
MSS_MIBSPIB
_MOSI
MSS_MIBSPIB
_CS1
VIOIN_18
VNWA
VSS
VIOIN
VSS
Not to scale
1
2
4
3
Figure 7-5. Bottom Right Quadrant
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7.2 Pin Attributes
PULL UP/DOWN
TYPE 7
BALL NUMBER 1
V16
PAD NAME
BALL NAME 2
MSS_MIBSPIB_CS1
SIGNAL NAME 3
MODE 4,8
TYPE 5
BALL RESET STATE 6
PAD_AA
MSS_GPIO_12
0
1
IO
O
O
IO
IO
IO
O
I
Output Disabled
Pull Down
MSS_MIBSPIA_HOSTIRQ
ADC_VALID
2
MSS_MIBSPIB_CS1
MSS_GPIO_13
6
B15
PAD_AB
MSS_GPIO_0
0
Output Disabled
Pull Down
MSS_GPIO_0
1
PMIC_CLKOUT
MSS_EPWM_TZ2
MSS_EPWMA1
MSS_EPWMB0
MSS_GPIO_16
2
3
10
11
0
O
O
IO
IO
O
I
A16
PAD_AC
MSS_GPIO_1
Output Disabled
Pull Down
MSS_GPIO_1
1
SYNC_OUT
2
MSS_EPWM_TZ1
BSS_UARTA_TX
READY_INT
3
7
O
O
O
I
8
LVDS_VALID
9
DMM_MUX_IN
12
13
14
15
0
MSS_MIBSPIB_CS1
MSS_MIBSPIB_CS2
MSS_EPWMA_SYNCI
MSS_GPIO_21
IO
IO
I
V12
U13
PAD_AH
PAD_AI
MSS_MIBSPIB_MOSI
MSS_MIBSPIB_MISO
IO
IO
IO
O
I
Output Disabled
Pull Up
MSS_MIBSPIB_MOSI
MSS_I2CA_SDA
MSS_EPWMA0
MSS_MCANB_RX
MSS_GPIO_22
1
2
3
7
0
IO
IO
IO
O
IO
O
Output Disabled
Pull Up
MSS_MIBSPIB_MISO
MSS_I2CA_SCL
MSS_EPWMB0
DSS_UARTA_TX
MSS_MCANB_TX
1
2
3
6
7
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PULL UP/DOWN
BALL NUMBER 1
T13
PAD NAME
BALL NAME 2
MSS_MIBSPIB_CLK
SIGNAL NAME 3
MODE 4,8
TYPE 5
BALL RESET STATE 6
TYPE 7
PAD_AJ
MSS_GPIO_5
0
1
2
3
6
7
8
0
1
2
6
7
9
0
1
2
0
1
2
8
0
1
2
8
0
1
2
8
0
1
2
6
0
1
2
0
0
IO
IO
IO
O
Output Disabled Pull Up
MSS_MIBSPIB_CLK
MSS_UARTA_RX
MSS_EPWMC0
MSS_UARTB_TX
BSS_UARTA_TX
MSS_MCANA_RX
MSS_GPIO_4
IO
O
I
U14
PAD_AK
MSS_MIBSPIB_CS0
IO
IO
IO
IO
O
Output Disabled
Pull Up
MSS_MIBSPIB_CS0
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UARTA_TX
MSS_MCANA_TX
MSS_GPIO_8
O
U11
V11
PAD_AL
PAD_AM
MSS_QSPI_0
MSS_QSPI_1
IO
IO
IO
IO
I
Output Disabled
Output Disabled
Pull Down
Pull Down
MSS_QSPI_0
MSS_MIBSPIB_MISO
MSS_GPIO_9
MSS_QSPI_1
MSS_MIBSPIB_MOSI
MSS_MIBSPIB_CS2
MSS_GPIO_10
MSS_QSPI_2
IO
IO
IO
I
T11
R12
R10
U12
PAD_AN
PAD_AO
PAD_AP
PAD_AQ
MSS_QSPI_2
MSS_QSPI_3
MSS_QSPI_CLK
MSS_QSPI_CS
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Pull Up
Pull Up
Pull Down
Pull Up
ADC_VALID
O
MSS_MCANA_TX
MSS_GPIO_11
O
IO
I
MSS_QSPI_3
ADC_VALID
O
MSS_MCANA_RX
MSS_GPIO_7
I
IO
IO
IO
IO
IO
O
MSS_QSPI_CLK
MSS_MIBSPIB_CLK
DSS_UARTA_TX
MSS_GPIO_6
MSS_QSPI_CS
MSS_MIBSPIB_CS0
WARM_RESET
NERROR_OUT
IO
IO
O
B12
C11
PAD_AS
PAD_AT
WARM_RESET
NERROR_OUT
HiZ Input (Open drain)
HiZ (Open drain)
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PULL UP/DOWN
TYPE 7
BALL NUMBER 1
C12
PAD NAME
BALL NAME 2
SIGNAL NAME 3
MODE 4,8
TYPE 5
BALL RESET STATE 6
PAD_AU
TCK
MSS_GPIO_17
TCK
0
IO
I
Output Disabled
Pull Down
1
MSS_UARTB_TX
BSS_UARTA_RX
MSS_MCANA_TX
MSS_GPIO_18
TMS
2
IO
I
6
8
O
IO
IO
O
I
C14
D13
D15
PAD_AV
PAD_AW
PAD_AX
TMS
TDI
0
Output Disabled
Output Disabled
Output Enabled
Pull Up
Pull Up
1
BSS_UARTA_TX
MSS_MCANA_RX
MSS_GPIO_23
TDI
2
6
0
IO
I
1
MSS_UARTA_RX
DSS_UARTA_RX
SOP[0]
2
IO
IO
I
7
TDO
During Power-up
MSS_GPIO_24
TDO
0
1
IO
O
IO
IO
O
O
IO
O
O
O
O
O
I
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UARTA_TX
NDMM_EN
2
6
7
9
R15
PAD_AY
MCU_CLKOUT
MSS_GPIO_25
MCU_CLKOUT
TRACE_CLK
FRAME_START
READY_INT
0
Output Disabled
Pull Down
1
2
7
8
LVDS_VALID
BSS_UARTA_RX
MSS_EPWMA0
DMM_CLK
9
10
12
14
15
O
I
OBS_CLKOUT
O
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PULL UP/DOWN
BALL NUMBER 1
G15
PAD NAME
BALL NAME 2
MSS_GPIO_2
SIGNAL NAME 3
MODE 4,8
TYPE 5
BALL RESET STATE 6
TYPE 7
PAD_AZ
MSS_GPIO_26
MSS_GPIO_2
0
IO
IO
IO
IO
O
O
O
O
O
I
Output Disabled
Pull Down
1
MSS_UARTB_TX
MSS_GPIO_2
SYNC_OUT
7
1
9
PMIC_CLKOUT
CHIRP_START
CHIRP_END
10
11
12
FRAME_START
MSS_EPWM_TZ0
LVDS_VALID
SOP[2]
13
14
15
O
I
T17
PAD_BA
PMIC_CLKOUT
During Power-up
Output Disabled
No Pull
MSS_GPIO_27
PMIC_CLKOUT
OBS_CLKOUT
TRACE_CTL
0
1
IO
O
O
O
O
O
O
O
O
O
O
I
2
3
CHIRP_START
CHIRP_END
6
7
FRAME_START
READY_INT
8
9
LVDS_VALID
MSS_EPWMA1
MSS_EPWMB0
DMM_SYNC
10
11
12
13
0
R17
PAD_BB
MSS_GPIO_28
MSS_GPIO_28
SYNC_IN
IO
I
Output Disabled
Pull Down
1
ADC_VALID
2
O
IO
I
MSS_UARTB_RX
DMM_MUX_IN
DSS_UARTA_RX
SYNC_OUT
6
7
8
IO
O
9
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PULL UP/DOWN
TYPE 7
BALL NUMBER 1
R14
PAD NAME
BALL NAME 2
MSS_MIBSPIB_CS2
SIGNAL NAME 3
MODE 4,8
TYPE 5
BALL RESET STATE 6
PAD_BC
SOP[1]
During Power-up
I
Output Disabled
MSS_GPIO_29
SYNC_OUT
RCOSC_CLK
READY_INT
LVDS_VALID
DMM_MUX_IN
0
1
IO
O
O
O
O
I
2
6
7
9
MSS_MIBSPIB_CS1
MSS_MIBSPIB_CS2
MSS_EPWMB0
MSS_EPWMB1
MSS_GPIO_15
MSS_RS232_RX
MSS_UARTA_RX
TRACE_CLK
10
11
12
13
0
IO
IO
O
O
IO
IO
IO
O
O
IO
I
F16
PAD_BD
MSS_RS232_RX
Output Disabled
Pull Up
1
2
3
BSS_UARTA_TX
MSS_UARTB_RX
MSS_MCANA_RX
MSS_I2CA_SCL
MSS_EPWMB0
MSS_EPWMB1
MSS_EPWMC0
MSS_GPIO_14
MSS_RS232_TX
TRACE_CTL
6
7
8
9
IO
O
O
O
IO
IO
O
IO
IO
O
O
O
O
IO
O
O
O
O
10
11
12
0
E17
PAD_BE
MSS_RS232_TX
Output Enabled
Pull Up
1
2
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UARTA_TX
READY_INT
5
6
7
8
LVDS_VALID
9
MSS_MCANA_TX
MSS_I2CA_SDA
MSS_EPWMA0
MSS_EPWMA1
NDMM_EN
10
11
12
13
14
15
MSS_EPWMB0
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PULL UP/DOWN
BALL NUMBER 1
PAD NAME
BALL NAME 2
MSS_GPIO_31
SIGNAL NAME 3
TRACE_DATA_0
MODE 4,8
TYPE 5
BALL RESET STATE 6
TYPE 7
U17
PAD_BF
0
1
2
4
10
0
1
2
3
4
6
10
0
1
2
3
6
7
0
1
2
4
6
7
0
1
2
4
6
0
1
2
4
5
6
O
IO
I
Output Disabled
Pull Down
MSS_GPIO_31
DMM0
MSS_UARTA_TX
MSS_I2CA_SDA
TRACE_DATA_1
MSS_GPIO_30
DMM1
IO
IO
O
IO
I
P17
PAD_BG
MSS_GPIO_30
Output Disabled
Pull Down
MSS_EPWMC_SYNCI
MSS_UARTA_RX
MSS_GPIO_0
MSS_I2CA_SCL
TRACE_DATA_2
MSS_GPIO_29
DMM2
I
IO
IO
IO
O
IO
I
T18
PAD_BH
MSS_GPIO_8
Output Disabled
Pull Down
MSS_EPWMB_SYNCI
MSS_GPIO_1
MSS_GPIO_8
TRACE_DATA_3
MSS_GPIO_28
DMM3
I
IO
IO
O
IO
I
N15
PAD_BI
MSS_GPIO_9
Output Disabled
Pull Down
MSS_EPWMC_SYNCO
MSS_GPIO_2
MSS_GPIO_9
TRACE_DATA_4
MSS_GPIO_3
DMM4
O
IO
IO
O
IO
I
P16
L15
PAD_BJ
PAD_BK
MSS_GPIO_3
MSS_GPIO_4
Output Disabled
Pull Down
MSS_EPWMB_SYNCO
MSS_GPIO_27
TRACE_DATA_5
MSS_GPIO_4
DMM5
O
IO
O
IO
I
Output Disabled
Pull Down
MSS_EPWM_TZ2
MSS_UARTB_TX
MSS_GPIO_26
I
IO
IO
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PULL UP/DOWN
TYPE 7
BALL NUMBER 1
M16
PAD NAME
BALL NAME 2
BSS_UARTA_TX
SIGNAL NAME 3
TRACE_DATA_6
MODE 4,8
TYPE 5
BALL RESET STATE 6
PAD_BL
0
1
2
4
5
6
7
0
1
2
4
5
6
7
0
1
2
4
5
6
0
1
2
4
5
6
0
1
2
3
4
6
0
1
2
3
4
6
O
IO
I
Output Disabled
Pull Down
MSS_GPIO_5
DMM6
MSS_EPWM_TZ1
BSS_UARTA_TX
MSS_GPIO_25
MSS_GPIO_10
TRACE_DATA_7
MSS_GPIO_6
DMM7
I
O
IO
IO
O
IO
I
J15
PAD_BM
MSS_GPIO_11
Output Disabled
Pull Down
MSS_EPWM_TZ0
DSS_UARTA_TX
MSS_GPIO_24
MSS_GPIO_11
TRACE_DATA_8
MSS_GPIO_7
DMM8
I
IO
IO
IO
O
IO
I
D17
D16
E15
C18
PAD_BN
PAD_BO
PAD_BP
PAD_BQ
MSS_MCANA_TX
MSS_MCANA_RX
MSS_EPWMA0
MSS_EPWMA1
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
Pull Down
MSS_MCANA_TX
MSS_EPWMA_SYNCI
MSS_GPIO_23
TRACE_DATA_9
MSS_GPIO_8
DMM9
O
I
IO
O
IO
I
MSS_MCANA_RX
MSS_EPWMA_SYNCO
MSS_GPIO_22
TRACE_DATA_10
MSS_GPIO_9
DMM10
I
O
IO
O
IO
I
MSS_EPWMA0
MSS_EPWMC0
MSS_GPIO_21
TRACE_DATA_11
MSS_GPIO_10
DMM11
O
O
IO
O
IO
I
MSS_EPWMA1
MSS_EPWMC1
MSS_GPIO_20
O
O
IO
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PULL UP/DOWN
BALL NUMBER 1
PAD NAME
BALL NAME 2
MSS_MCANB_TX
SIGNAL NAME 3
TRACE_DATA_12
MODE 4,8
TYPE 5
BALL RESET STATE 6
TYPE 7
B17
A17
C17
PAD_BR
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
6
0
1
2
6
0
1
2
3
6
0
1
2
3
6
0
1
2
3
6
O
IO
I
Output Disabled
Output Disabled
Output Disabled
Pull Down
MSS_GPIO_11
DMM12
MSS_EPWMB0
MSS_EPWMA0
MSS_MCANB_TX
MSS_GPIO_19
TRACE_DATA_13
MSS_GPIO_12
DMM13
O
O
O
IO
O
IO
I
PAD_BS
MSS_MCANB_RX
Pull Down
MSS_EPWMB1
MSS_EPWMA1
MSS_MCANB_RX
MSS_GPIO_18
TRACE_DATA_14
MSS_GPIO_13
DMM14
O
O
I
IO
O
IO
I
PAD_BT
MSS_EPWMB0
Pull Down
MSS_EPWMC0
MSS_EPWMB0
MSS_GPIO_17
MSS_GPIO_17
MSS_MII_COL
MSS_RMII_REFCLK
MSS_EPWMA1
MSS_GPIO_18
MSS_MII_CRS
MSS_RMII_CRS_DV
MSS_I2CA_SDA
MSS_EPWMB1
MSS_GPIO_19
MSS_MII_RXER
MSS_RMII_RXER
MSS_I2CA_SCL
MSS_EPWMC1
MSS_GPIO_20
MSS_MII_TXEN
MSS_RMII_TXEN
MSS_RGMII_TCTL
MSS_EPWMA0
O
O
IO
IO
I
U8
R8
PAD_BX
PAD_BY
MSS_GPIO_17
MSS_I2CA_SDA
Output Disabled
Output Disabled
Pull Down
IO
O
IO
I
HiZ (Open drain)
I
IO
O
IO
I
U9
R6
PAD_BZ
PAD_CA
MSS_I2CA_SCL
Output Disabled
HiZ (Open drain)
I
IO
O
IO
O
O
O
O
MSS_RGMII_TCTL
Output Disabled
Pull Down
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PULL UP/DOWN
TYPE 7
BALL NUMBER 1
PAD NAME
BALL NAME 2
MSS_RGMII_RCTL
SIGNAL NAME 3
MODE 4,8
TYPE 5
BALL RESET STATE 6
T7
PAD_CB
MSS_GPIO_21
0
1
3
4
5
6
0
1
3
5
6
0
1
3
0
1
2
3
0
1
2
3
0
1
3
0
1
3
4
0
1
3
0
1
3
0
1
2
3
IO
I
Output Disabled
MSS_MII_RXDV
MSS_RGMII_RCTL
MSS_RMII_CRS_DV
MSS_UARTB_RX
MSS_EPWMB0
MSS_GPIO_22
I
I
IO
O
IO
O
O
IO
O
IO
O
O
IO
O
O
O
IO
O
O
O
IO
I
U4
PAD_CC
MSS_RGMII_TD3
Output Disabled
Pull Down
MSS_MII_TXD3
MSS_RGMII_TD3
MSS_UARTB_TX
MSS_EPWMC0
MSS_GPIO_23
U6
U5
PAD_CD
PAD_CE
MSS_RGMII_TD2
MSS_RGMII_TD1
Output Disabled
Output Disabled
Pull Down
Pull Down
MSS_MII_TXD2
MSS_RGMII_TD2
MSS_GPIO_24
MSS_MII_TXD1
MSS_RMII_TXD1
MSS_RGMII_TD1
MSS_GPIO_25
U7
PAD_CF
MSS_RGMII_TD0
Output Disabled
Pull Down
MSS_MII_TXD0
MSS_RMII_TXD0
MSS_RGMII_TD0
MSS_GPIO_26
V3
T9
PAD_CG
PAD_CH
MSS_RGMII_TCLK
MSS_RGMII_RCLK
Output Disabled
Output Disabled
Pull Down
Pull Down
MSS_MII_TXCLK
MSS_RGMII_TCLK
MSS_GPIO_27
O
IO
I
MSS_MII_RXCLK
MSS_RGMII_RCLK
MSS_RMII_REFCLK
MSS_GPIO_28
I
IO
IO
I
U10
V5
PAD_CI
PAD_CJ
PAD_CK
MSS_RGMII_RD3
MSS_RGMII_RD2
MSS_RGMII_RD1
Output Disabled
Output Disabled
Output Disabled
MSS_MII_RXD3
MSS_RGMII_RD3
MSS_GPIO_29
I
IO
I
MSS_MII_RXD2
MSS_RGMII_RD2
MSS_GPIO_30
I
V4
IO
I
MSS_MII_RXD1
MSS_RMII_RXD1
MSS_RGMII_RD1
I
I
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PULL UP/DOWN
BALL NUMBER 1
PAD NAME
BALL NAME 2
MSS_RGMII_RD0
SIGNAL NAME 3
MODE 4,8
TYPE 5
BALL RESET STATE 6
TYPE 7
V6
PAD_CL
MSS_GPIO_31
MSS_MII_RXD0
0
IO
I
Output Disabled
1
MSS_RMII_RXD0
MSS_RGMII_RD0
MSS_GPIO_30
2
I
3
I
T5
PAD_CM
PAD_CN
PAD_CO
PAD_CP
PAD_CQ
PAD_CR
PAD_CS
MSS_MDIO_DATA
0
IO
IO
IO
O
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Pull Up
Pull Up
Pull Up
Pull Up
Pull Up
Pull Up
MSS_MDIO_DATA
MSS_GPIO_31
1
R4
MSS_MDIO_CLK
0
MSS_MDIO_CLK
MSS_GPIO_0
1
U15
U16
T16
T15
V17
MSS_MIBSPIA_MOSI
MSS_MIBSPIA_MISO
MSS_MIBSPIA_CLK
MSS_MIBSPIA_CS0
MSS_MIBSPIA_HOSTIRQ
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
MSS_MIBSPIA_MOSI
MSS_GPIO_1
5
0
MSS_MIBSPIA_MISO
MSS_GPIO_2
5
0
MSS_MIBSPIA_CLK
MSS_GPIO_3
5
0
MSS_MIBSPIA_CS0
MSS_GPIO_4
5
0
Pull Down
MSS_GPIO_2
2
MSS_GPIO_8
3
MSS_MIBSPIA_HOSTIRQ
MSS_MIBSPIB_CS2
MSS_GPIO_2
5
6
IO
IO
IO
IO
O
7
MSS_GPIO_8
10
B16
PAD_DA
MSS_UARTA_RX
MSS_GPIO_12
0
Output Disabled
Pull Up
MSS_CPTS0_TS_SYNC
MSS_GPIO_8
1
3
IO
IO
IO
IO
I
MSS_UARTB_TX
MSS_UARTA_RX
DSS_UARTA_TX
SOP[4]
4
5
6
C16
PAD_DB
MSS_UARTA_TX
During Power-up
Output Disabled
MSS_GPIO_13
0
1
3
4
5
6
IO
I
MSS_CPTS0_HW2TSPUSH
MSS_GPIO_9
IO
IO
IO
IO
MSS_UARTB_RX
MSS_UARTA_TX
DSS_UARTA_RX
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PULL UP/DOWN
TYPE 7
BALL NUMBER 1
A15
PAD NAME
BALL NAME 2
DSS_UARTA_TX
SIGNAL NAME 3
MODE 4,8
TYPE 5
BALL RESET STATE 6
PAD_DC
MSS_GPIO_14
0
IO
I
Output Disabled
Pull Up
MSS_CPTS0_HW1TSPUSH
MSS_GPIO_10
DSS_UARTA_TX
MSS_UARTA_RX
MSS_GPIO_15
DSS_UARTA_RX
MSS_GPIO_11
MSS_UARTA_TX
SOP[3]
1
3
IO
IO
IO
IO
IO
IO
IO
I
4
6
B14
A14
PAD_DD
PAD_DE
DSS_UARTA_RX
MSS_UARTB_TX
0
Output Disabled
Output Disabled
Pull Up
1
3
6
During Power-up
MSS_GPIO_0
0
1
IO
IO
I
DSS_UARTA_TX
MSS_EPWMB_SYNCI
MSS_UARTA_TX
MSS_UARTB_TX
LVDS_VALID
3
5
IO
IO
O
6
8
MSS_GPIO_31
MSS_GPIO_1
12
0
IO
IO
I
B13
D11
PAD_DF
PAD_DG
XREF_CLK0
XREF_CLK1
Output Disabled
Pull Down
XREF_CLK0
1
MSS_GPIO_8
3
IO
O
MCU_CLKOUT
MSS_GPIO_30
MSS_GPIO_2
6
12
0
IO
IO
I
Output Disabled
Pull Down
XREF_CLK1
1
MSS_GPIO_9
3
IO
O
PMIC_CLKOUT
MSS_GPIO_29
7
12
IO
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The following list describes the table column headers:
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken based on an example implementation).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
4. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit
range value.
5. TYPE: Signal type and direction:
•
•
•
I = Input
O = Output
IO = Input or Output
6. BALL RESET STATE: The state of the terminal at power-on reset
7. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled
via software.
•
•
•
Pull Up: Internal pullup
Pull Down: Internal pulldown
HiZ
8. Pin Mux Control Value maps to lower 4 bits of register.
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7.3 Signal Descriptions - Digital
Note
All digital IO pins of the device (except NERROR_OUT and WARM_RESET) are non-failsafe; hence,
care needs to be taken that they are not driven externally without the VIO supply being present to the
device.
Note
The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the
application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer
should be used to isolate the GPIO output from the radar device and a pull resister used to define the
required state in the application. The NRESET signal to the radar device could be used to control the
output enable (OE) of the tri-state buffer.
Table 7-1. Signal Descriptions - Digital
FUNCTION
SIGNAL NAME
PIN TYPE DESCRIPTION
PIN NUMBER
T16
MSS_MIBSPIA_CLK
MSS_MIBSPIA_MOSI
MSS_MIBSPIA_MISO
MSS_MIBSPIA_CS0
MSS_MIBSPIA_HOSTIRQ
IO
IO
IO
IO
O
SPI Channel A - Clock
SPI Channel A - Master Out Slave In
SPI Channel A - Master In Slave Out
SPI Channel A Chip Select
U15
U16
T15
Out of Band Interrupt to an external host
communicating over SPI
V16,V17
SPI Interface
MSS_MIBSPIB_CLK
MSS_MIBSPIB_MOSI
MSS_MIBSPIB_MISO
MSS_MIBSPIB_CS0
MSS_MIBSPIB_CS1
MSS_MIBSPIB_CS2
MSS_MCANA_RX
MSS_MCANA_TX
MSS_MCANB_RX
MSS_MCANB_TX
MSS_UARTA_RX
IO
IO
IO
IO
IO
IO
I
SPI Channel B - Clock
T13,R10
V12,V11
SPI Channel B - Master Out Slave In
SPI Channel B - Master In Slave Out
SPI Channel B Chip Select (Instance ID 0)
SPI Channel B Chip Select (Instance ID 1)
SPI Channel B Chip Select (Instance ID 2)
CAN-FD A (MCAN) Receive Signal
CAN-FD A (MCAN) Transmit Signal
CAN-FD B (MCAN) Receive Signal
CAN-FD B (MCAN) Transmit Signal
U13,U11
U14,U12
V16,A16,R14
A16,V11,R14,V17
T13,R12,C14,F16,D16
U14,T11,C12,E17,D17
V12,A17
O
CAN-FD
I
O
U13,B17
IO
Main Subsystem - UART A Receive
(For Flash programming)
T13,D13,F16,P17,B16,A15
MSS_UARTA_TX
MSS_UARTB_TX
IO
IO
Main Subsystem - UART A Transmit (For
Flash programming)
U14,D15,E17,U17,C16,B14,
A14
UART (MSS)
Main Subsystem - UART B Receive
T13,U14,C12,D15,G15,E17,
L15,U4,B16,A14
MSS_UARTB_RX
MSS_QSPI_0
IO
IO
Main Subsystem - UART B Transmit
R17,F16,T7,C16
U11
QSPI Data Line #0 (Used with Serial Data
Flash)
MSS_QSPI_1
MSS_QSPI_2
MSS_QSPI_3
I
I
I
QSPI Data Line #1 (Used with Serial Data
Flash)
V11
T11
R12
QSPI Data Line #2 (Used with Serial Data
Flash)
QSPI for Serial
Flash
QSPI Data Line #3 (Used with Serial Data
Flash)
MSS_QSPI_CLK
MSS_QSPI_CS
IO
O
QSPI clock (Used with Serial Data Flash)
R10
U12
QSPI chip select (Used with Serial Data
Flash)
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Table 7-1. Signal Descriptions - Digital (continued)
FUNCTION
SIGNAL NAME
PIN TYPE DESCRIPTION
PIN NUMBER
V12,E17,U17,R8
U13,F16,P17,U9
F16
MSS_I2CA_SDA
MSS_I2CA_SCL
MSS_RS232_RX
IO
IO
IO
I2C Clock
I2C Data
I2C interface
Debug UART (Operates as Bus controller) -
Receive Signal
RS232 UART
MSS_RS232_TX
IO
Debug UART (Operates as Bus controller) -
Transmit Signal
E17
MSS_EPWMA0
O
O
I
PWM Module 1 - Output A0
PWM Module 1 - Output A1
PWM Module 1 - Sync Input
PWM Module 1 - Sync Output
PWM Module 2 - Output B0
V12,R15,E17,E15,B17,R6
B15,T17,E17,C18,A17,U8
A16,D17
MSS_EPWMA1
MSS_EPWMA_SYNCI
MSS_EPWMA_SYNCO
MSS_EPWMB0
O
O
D16
B15,U13,T17,R14,F16,E17,
B17,C17,T7
MSS_EPWMB1
O
I
PWM Module 2 - Output B1
PWM Module 2 - Sync Input
PWM Module 2 - Sync Output
PWM Module 3 - Output C0
PWM Module 3 - Output C1
PWM Module 3 - Sync Input
PWM Module 3 - Sync Output
PWM module Trip Signal 0
PWM module Trip Signal 1
PWM module Trip Signal 2
R14,F16,A17,R8
T18,A14
MSS_EPWMB_SYNCI
MSS_EPWMB_SYNCO
MSS_EPWMC0
PWM Module
O
O
O
I
P16
T13,F16,E15,C17,U4
C18,U9
MSS_EPWMC1
MSS_EPWMC_SYNCI
MSS_EPWMC_SYNCO
MSS_EPWM_TZ0
MSS_EPWM_TZ1
MSS_EPWM_TZ2
P17
O
I
N15
G15,J15
I
A16,M16
B15,L15
I
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Table 7-1. Signal Descriptions - Digital (continued)
FUNCTION
SIGNAL NAME
PIN TYPE DESCRIPTION
PIN NUMBER
MSS_MII_COL
MSS_MII_CRS
I
I
U8
R8
MSS Ethernet MII Collision Detect
MSS Ethernet MII Carrier Sense
MSS Ethernet MII Receive Error
MSS Ethernet MII Transmit Enable
MSS_MII_RXER
MSS_MII_TXEN
MSS_MII_RXDV
I
O
I
U9
R6
T7
MSS Ethernet MII Receive Data Valid
MSS_MII_TXD3
MSS_MII_TXD2
MSS_MII_TXD1
MSS_MII_TXD0
MSS_MII_TXCLK
MSS_MII_RXCLK
MSS_MII_RXD3
MSS_MII_RXD2
MSS_MII_RXD1
MSS_MII_RXD0
MSS_RMII_REFCLK
MSS_RMII_CRS_DV
O
O
O
O
I
MSS Ethernet MII Transmit Data 3
MSS Ethernet MII Transmit Data 2
MSS Ethernet MII Transmit Data 1
MSS Ethernet MII Transmit Data 0
MSS Ethernet MII Transmit Clock
MSS Ethernet MII Receive Clock
MSS Ethernet MII Receive Data 0
MSS Ethernet MII Receive Data 1
MSS Ethernet MII Receive Data 2
MSS Ethernet MII Receive Data 3
MSS Ethernet RMII Clock Input
U4
U6
U5
U7
V3
I
T9
I
U10
V5
I
I
V4
I
V6
IO
I
U8,T9
R8,T7
MSS Ethernet RMII Carrier Sense/Receive
Data Valid
MSS_RMII_RXER
MSS_RMII_TXEN
MSS_RMII_TXD1
MSS_RMII_TXD0
MSS_RMII_RXD1
MSS_RMII_RXD0
MSS_RGMII_TCTL
MSS_RGMII_RCTL
MSS_RGMII_TD3
MSS_RGMII_TD2
MSS_RGMII_TD1
MSS_RGMII_TD0
MSS_RGMII_TCLK
MSS_RGMII_RCLK
MSS_RGMII_RD3
MSS_RGMII_RD2
MSS_RGMII_RD1
MSS_RGMII_RD0
MSS_MDIO_DATA
I
O
O
O
I
MSS Ethernet RMII Receive Error
MSS Ethernet RMII Transmit Enable
MSS Ethernet RMII Transmit Data 1
MSS Ethernet RMII Transmit Data 0
MSS Ethernet MII Receive Data 1
MSS Ethernet MII Receive Data 0
MSS Ethernet RGMII Transmit Control
MSS Ethernet RGMII Receive Control
MSS Ethernet RGMII Transmit Data 3
MSS Ethernet RGMII Transmit Data 2
MSS Ethernet RGMII Transmit Data 1
MSS Ethernet RGMII Transmit Data 0
MSS Ethernet RGMII Transmit Clock
MSS Ethernet RGMII Receive Clock
MSS Ethernet RGMII Receive Data 0
MSS Ethernet RGMII Receive Data 1
MSS Ethernet RGMII Receive Data 2
MSS Ethernet RGMII Receive Data 3
U9
R6
U5
U7
V4
V6
R6
T7
RGMII/RMII/MII
Ethernet
I
O
I
O
O
O
O
O
I
U4
U6
U5
U7
V3
T9
I
U10
V5
V4
V6
T5
I
I
I
IO
MSS Ethernet Manage Data Input/Output
data
MSS_MDIO_CLK
O
MSS Ethernet Manage Data Input/Output
Clock
R4
MSS_CPTS0_TS_SYNC
O
I
Ethernet Timestamp SYNC output
B16
C16
MSS_CPTS0_HW2TSPUS
H
Ethernet hardware Timestamp Inputs Pins
MSS_CPTS0_HW1TSPUS
H
I
A15
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Table 7-1. Signal Descriptions - Digital (continued)
FUNCTION
SIGNAL NAME
PIN TYPE DESCRIPTION
PIN NUMBER
U17
TRACE_DATA_0
TRACE_DATA_1
TRACE_DATA_2
TRACE_DATA_3
TRACE_DATA_4
TRACE_DATA_5
TRACE_DATA_6
TRACE_DATA_7
TRACE_DATA_8
TRACE_DATA_9
TRACE_DATA_10
TRACE_DATA_11
TRACE_DATA_12
TRACE_DATA_13
TRACE_DATA_14
TRACE_CLK
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Clock
P17
T18
N15
P16
L15
M16
J15
Trace Signal
D17
D16
E15
C18
B17
A17
C17
R15,F16
T17,E17
TRACE_CTL
Debug Trace Output - Control
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Table 7-1. Signal Descriptions - Digital (continued)
FUNCTION
SIGNAL NAME
PIN TYPE DESCRIPTION
PIN NUMBER
DMM0
DMM1
DMM2
DMM3
DMM4
DMM5
DMM6
DMM7
DMM8
DMM9
DMM10
DMM11
DMM12
DMM13
DMM14
DMM_CLK
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Debug Interface (Hardware In Loop) - Data
Line
U17
P17
T18
N15
P16
L15
M16
J15
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
D17
D16
E15
C18
B17
A17
C17
R15
Debug Interface (Hardware In Loop) - Data
Line
DMM Interface
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) - Data
Line
Debug Interface (Hardware In Loop) -
Clock
DMM_SYNC
I
I
Debug Interface (Hardware In Loop) - Sync
T17
DMM_MUX_IN
Debug Interface (Hardware In Loop) Mux
Select between DMM1 and DMM2 (Two
Instances)
A16,R17,R14
NDMM_EN
O
Debug Interface (Hardware In Loop)
Enable - Active Low Signal
D15,E17
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Table 7-1. Signal Descriptions - Digital (continued)
FUNCTION
SIGNAL NAME
PIN TYPE DESCRIPTION
PIN NUMBER
B15,P17,U15,A14
A16,T18,U16,B13
G15,N15,T16,V17,D11
P16,T15
MSS_GPIO_0
MSS_GPIO_1
MSS_GPIO_2
MSS_GPIO_3
MSS_GPIO_4
MSS_GPIO_5
MSS_GPIO_6
MSS_GPIO_7
MSS_GPIO_8
MSS_GPIO_9
MSS_GPIO_10
MSS_GPIO_11
MSS_GPIO_12
MSS_GPIO_13
MSS_GPIO_14
MSS_GPIO_15
MSS_GPIO_16
MSS_GPIO_17
MSS_GPIO_18
MSS_GPIO_19
MSS_GPIO_20
MSS_GPIO_21
MSS_GPIO_22
MSS_GPIO_23
MSS_GPIO_24
MSS_GPIO_25
MSS_GPIO_26
MSS_GPIO_27
MSS_GPIO_28
MSS_GPIO_29
MSS_GPIO_30
MSS_GPIO_31
DSS_UARTA_TX
DSS_UARTA_RX
ADC_VALID
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
Debug UART Transmit [DSP]
Debug UART Receive [DSP]
When high, indicating valid ADC samples
U14,L15,V17
T13,M16
U12,J15
R10,D17
U11,T18,D16,V17,B16,B13
V11,N15,E15,C16,D11
T11,M16,C18,A15
R12,J15,B17,B14
V16,A17,B16
B15,C17,C16
E17,A15
F16,B14
General-purpose
I/Os
A16
C12,C17,U8
C14,A17,R8
B17,U9
C18,R6
V12,E15,T7
U13,D16,U4
D13,D17,U6
D15,J15,U5
R15,M16,U7
G15,L15,V3
T17,P16,T9
R17,N15,U10
R14,T18,V5,D11
P17,V4,T5,B13
U17,V6,R4,A14
U13,R10,J15,B16,A15,A14
D13,R17,C16,B14
V16,T11,R12,R17
G15,T17
UART (DSS)
CHIRP_START
O
Pulse signal indicating the start of each
chirp
Chirp/Frame signals
CHIRP_END
O
O
O
O
O
Pulse signal indicating the end of each
chirp
G15,T17
FRAME_START
LVDS_VALID
Pulse signal indicating the start of each
frame
R15,G15,T17
When high, indicating valid LVDS data
A16,R15,G15,T17,R14,E17,
A14
LVDS_VALID
MCU_CLKOUT
PMIC_CLKOUT
Programmable clock given out to external
MCU or the processor
R15,B13
External clock out
Output Clock from the device for PMIC
B15,G15,T17,D11
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Table 7-1. Signal Descriptions - Digital (continued)
FUNCTION
System
SIGNAL NAME
PIN TYPE DESCRIPTION
PIN NUMBER
SYNC_IN
I
Low frequency Synchronization signal input
R17
SYNC_OUT
O
Low Frequency Synchronization Signal
output
A16,G15,R17,R14
Synchronization
OBS_CLKOUT
RCOSC_CLK
XREF_CLK0
XREF_CLK1
TCK
O
O
I
Observation Clock Output
Internal RCOSC Clock Output
External reference input clock 0
External reference input clock 1
JTAG Test Clock
R15,T17
R14
Clock Output
B13
Reference Clock
I
D11
I
C12
TMS
IO
I
JTAG Test Mode Signal
C14
JTAG
TDI
JTAG Test Data Input
D13
TDO
O
O
JTAG Test Data Output
D15
BSS_UARTA_TX
Debug UART Transmit [Radar Block]
A16,T13,U14,C14,D15,F16,
E17,M16
UART (BSS)
Reset
BSS_UARTA_RX
WARM_RESET
I
Debug UART Receive [Radar Block]
C12,R15
B12
IO
Open drain fail safe warm reset signal. Can
be driven from PMIC for diagnostic or can
be used as status signal that the device is
going through reset.
NERROR_OUT
O
Open drain fail safe output signal.
Connected to PMIC/Processor/MCU to
indicate that some severe criticality fault
has happened. Recovery would be through
reset.
C11
Safety
SOP[0]
SOP[1]
SOP[2]
SOP[3]
SOP[4]
I
I
I
I
I
The SOP pins are driven externally (weak
drive) and the mmWave device senses the
state of these pins during bootup to decide
the bootup mode. After boot the same pins
have other functionality.
D15
R14
T17
A14
C16
•
•
•
[SOP2 SOP1 SOP0] = [0 0 1] ->
Functional QSPI load mode
[SOP2 SOP1 SOP0] = [1 0 1] -> UART
load mode
Sense On power
[SOP2 SOP1 SOP0] = [0 1 1] -> debug
and development mode
The following configuration of SOP pins
help decide the reference crystal frequency
•
[SOP4 SOP3] = [0 0] -> 40 MHz
CSI2_RX0M0
CSI2_RX0P0
CSI2_RX0CLKM
CSI2_RX0CLKP
CSI2_RX0M1
CSI2_RX0P1
I
I
I
I
I
I
CSI2.0 Receiver #1, Negative Polarity,
Lane 0
N18
N17
L18
L17
M18
M17
CSI2.0 Receiver #1, Positive Polarity, Lane
0
CSI2.0 Receiver #1, Clock Input, Negative
Polarity
CSI2 RX
CSI2.0 Receiver #1, Clock Input, Positive
Polarity
CSI2.0 Receiver #1, Negative Polarity Lane
1
CSI2.0 Receiver #1, Positive Polarity Lane
1
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Table 7-1. Signal Descriptions - Digital (continued)
FUNCTION
SIGNAL NAME
PIN TYPE DESCRIPTION
PIN NUMBER
F18
LVDS_TXM0
O
O
O
O
O
O
O
O
LVDS/Aurora Transmitter, Data Output,
Lane 0
LVDS_TXP0
F17
LVDS_TXM2_CLKM
LVDS_TXP2_CLKP
LVDS_TXM3_FRCLKM
LVDS_TXP3_FRCLKP
LVDS_TXM1
G18
LVDS Clock, Aurora Data output - Lane 2
G17
Aurora LVDS
H18
LVDS Frame Clock, Aurora Data Output -
Lane 3
H17
J18
LVDS/Aurora Transmitter, Data Output,
Lane 1
LVDS_TXP1
J17
7.4 Signal Descriptions - Analog
PIN
TYPE
INTERFACE
SIGNAL NAME
DESCRIPTION
BALL NO.
TX1
TX2
TX3
TX4
RX1
RX2
RX3
RX4
O
O
O
O
I
Single ended transmitter 1 O/P
Single ended transmitter 2 O/P
Single ended transmitter 3 O/P
Single ended transmitter 4 O/P
Single ended receiver 1 I/P
Single ended receiver 2 I/P
Single ended receiver 3 I/P
Single ended receiver 4 I/P
Power on reset for chip. Active low
B3
B5
B7
B9
M2
K2
H2
F2
Transmitters
I
Receivers
Reset
I
I
NRESET
I
H16
In XTAL mode: Input for the reference crystal
In External clock mode: Single ended input
reference clock port
CLKP
I
I
D1
B1
Reference
Oscillator
In XTAL mode: Feedback drive for the reference
crystal
CLKM
In External clock mode: Connect this port to ground
Reference clock output from clocking subsystem
after cleanup PLL
Reference clock
Bandgap voltage
OSC_CLKOUT
VBGAP
O
O
A11
K4
Device's Band Gap Reference Output
E12,E13,E14,F14,H
14,J14,K14,L14,N6,
N14,P6,P7,P9,P10,
P11,P13,P14
VDD
Power 1.2V digital power supply
VDD_SRAM
VNWA
Power 1.2V power rail for internal SRAM
V7
Power 1.2V power rail for SRAM array back bias
V13
I/O Supply (3.3V or 1.8V): All CMOS I/Os would
operate on this supply
A13,B18,R18,V8,V1
5
VIOIN
Power
Power supply
VIOIN_18
Power 1.8V supply for CMOS IO
Power 1.8V supply for clock module
Power 1.8V supply for PM module
Power 1.8V supply for LVDS port
Power 1.8V supply for CSI port
Power Voltage supply for fuse chain
D18,U18,V10
VDDA_18CLK
VDDA_18PM
VIOIN_18LVDS
VIOIN_18CSI
VPP
D9
R1
K17
K18
U3
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PIN
TYPE
INTERFACE
SIGNAL NAME
VIDDA_10RF1
DESCRIPTION
1V Analog and RF supply,VDDA_10RF1 and
VDDA_10RF2 could be shorted on the board
Power
M4
VDDA_10RF2
VDDA_18BB
VDDA_18VCO
Power 1V Analog and RF supply
Power 1.8V Analog base band power supply
Power 1.8V RF VCO supply
D6, D7
P1
E4
A12,A18,E11,E18,F
8,F9,F10,F11,F12,F
13,G7,G8,G9,G10,
G11,G12,G13,G14,
H7,H8,H9,H10,H11,
H12,H13,J7,J8,J9,J
10,J11,J12,J13,K7,
K8,K9,K10,K11,K12
,K13,K16,L7,L8,L9,
L10,L11,L12,L13,M
7,M8,M9,M10,M11,
M12,M13,M14,N7,N
8,N9,N10,N11,N12,
N13,P8,P12,P18,V2
,V9,V14,V18
VSS(2)
Ground Digital ground
Power supply
A1,A2,A4,A6,A8,A1
0,B2,B4,B6,B8,B10,
B11,C1,C2,C3,C4,C
5,C6,C7,C8,C9,C10
,D2,D3,E1,E2,E3,F
3,F6,F7,G1,G2,G3,
G6,H3,H6,J1,J2,J3,
J6,K3,K6,L1,L2,L3,
L6,M3,M6,N1,N2,N
3,V1
VSSA(3)
Ground Analog ground
VOUT_14APLL
VOUT_14SYNTH
ADC1
O
Internal LDO output
Internal LDO output
ADC Channel 1
ADC Channel 2
ADC Channel 3
ADC Channel 4
ADC Channel 5
ADC Channel 6
ADC Channel 7
ADC Channel 8
ADC Channel 9
H4
G4
P3
P2
R3
R2
T3
U2
T1
T2
U1
Internal LDO output/
inputs
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
ADC2
ADC3
General purpose
ADC inputs for
external voltage
monitoring(1)
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
(1) For details, see Section 9.4.3
(2) Corner BGAs are VSS and redundant, meaning if they fail the device will still function.
(3) The VSSA BGAs around the launches are not redundant and are required for functionality.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
PARAMETERS
MIN
–0.5
–0.5
–0.5
MAX
1.4
UNIT
VDD
1.2 V digital power supply
V
V
V
VDD_SRAM
VNWA
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
1.4
1.4
I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this
supply.
VIOIN
–0.5
3.8
V
VIOIN_18
1.8 V supply for CMOS IO
–0.5
–0.5
2
2
V
V
VDDA_18CLK
1.8 V supply for clock module
VDDA_18PM
VIOIN_18CSI
VIOIN_18LVDS
1.8 V supply for the PM Module
1.8 V supply for CSI2 port
1.8 V supply for LVDS port
-0.5
–0.5
–0.5
2
2
2
V
V
V
VDDA_10RF1
VDDA_10RF2
VDDA_18BB
1 V Analog and RF supply, VDDA_10RF1 and VDDA_10RF2
could be shorted on the board.
–0.5
1.4
V
1.8-V Analog baseband power supply
–0.5
–0.5
2
V
VDDA_18VCO supply 1.8-V RF VCO supply
2
V
RX1-4
TX1-4
Externally applied power on RF inputs
10
10
dBm
dBm
Externally applied power on RF outputs(3)
Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)
–0.3V
VIOIN + 0.3
Input and output
voltage range
V
Dual-voltage LVCMOS inputs, operatedat 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input
VIOIN + 20% up to
20% of signal period
CLKP, CLKM
Clamp current
Input ports for reference crystal
–0.5
2
V
Input or Output Voltages 0.3 V above or below their respective
power rails. Limit clamp current that flows through the internal
diode protection cells of the I/O.
–20
20
mA
TJ
Operating junction temperature range
–40
–55
140
150
°C
°C
TSTG
Storage temperature range after soldered onto PC board
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma= 1 can be applied on
the TX output.
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
All pins
V(ESD) Electrostatic discharge
All pins
V
Corner pins
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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8.3 Power-On Hours (POH)
JUNCTION
OPERATING
TEMPERATURE (Tj)
NOMINAL CVDD VOLTAGE (V)
POWER-ON HOURS [POH] (HOURS)
CONDITION
(1) (2)
–40°C
75°C
1440 (6%)
4800 (20%)
15600 (65%)
1920 (8%)
240 (1%)
95°C
130°C
140°C
50% duty cycle
1.2
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would
not be applicable, if the Tx gain table is overwritten using an API.
8.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.14
1.14
1.14
3.135
1.71
1.71
1.71
NOM
1.2
1.2
1.2
3.3
1.8
1.8
1.8
MAX
1.32
1.32
1.32
3.465
1.89
1.9
UNIT
VDD
1.2 V digital power supply
V
V
V
VDD_SRAM
VNWA
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
I/O supply (3.3 V or 1.8 V):
All CMOS I/Os would operate on this supply.
VIOIN
V
VIOIN_18
1.8 V supply for CMOS IO
V
V
V
VDDA_18CLK
VDDA_18PM
1.8 V supply for clock module
1.8 V supply for the PM module
1.9
1.71
1.71
1.71
1.8
1.8
1.8
1.9
1.9
1.9
VIOIN_18CSI
1.8 V supply for CSI2 port
1.8 V supply for LVDS port
V
V
VIOIN_18LVDS
VDDA_10RF1
VDDA_10RF2
VDDA_18BB
VDDA_18VCO
1 V Analog and RF supply. VDDA_10RF1 and VDDA_10RF2
could be shorted on the board
0.95
1
1.05
V
1.8-V Analog baseband power supply
1.8V RF VCO supply
1.71
1.71
1.8
1.8
1.9
1.9
V
V
Voltage Input High (1.8 V mode)
Voltage Input High (3.3 V mode)
Voltage Input Low (1.8 V mode)
Voltage Input Low (3.3 V mode)
High-level output threshold (IOH = 6 mA)
Low-level output threshold (IOL = 6 mA)
VIL (1.8V Mode)
1.17
0.3 + VIOIN
0.3 + VIOIN
0.3*VIOIN
0.62
VIH
VIL
V
V
2.25
-0.3
-0.3
VOH
VOL
VIOIN – 450
mV
mV
450
0.45
VIH (1.8V Mode)
0.96
NRESET
SOP[4:0]
V
VIL (3.3V Mode)
0.65
140
VIH (3.3V Mode)
1.57
-40
TJ
Operating junction temperature range
℃
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8.5 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses and is applicable only
for high-security (AWR294x HS) devices. During the process of writing the customer specific keys or other fields
like Software version etc. in the efuse , the user needs to provide the VPP supply.
8.5.1 Recommended Operating Conditions for OTP eFuse Programming
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
Supply voltage range for the eFuse ROM domain during
normal operation
NC
VPP
Supply voltage range for the eFuse ROM domain during OTP
programming(1)
1.65
1.7
1.75
50
V
I(VPP)
mA
(1) During normal operation, no voltage should be applied to VPP. This can be typically achieved by disabling the external regulator
attached to the VPP terminal.
8.5.2 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
•
The VPP power supply must be disabled when not programming OTP registers.
8.5.3 Impact to Your Hardware Warranty
You recognize and accept at your own risk that your use of eFuse permanently alters the TI device. You
acknowledge that eFuse can fail due to incorrect operating conditions or programming sequence. Such a failure
may render the TI device inoperable and TI will be unable to confirm the TI device conformed to TI device
specifications prior to the attempted eFuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY FOR ANY TI
DEVICES THAT HAVE BEEN eFUSED.
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8.6 Power Supply Specifications
Table 8-1 describes the four required power rails which must be provided to the AWR294x from an external
power supply. In the case when 1.8V LVCMOS IO is utilized, VIOIN will be powered from a 1.8V rail and the
3.3V rail can be ommited, so only three rails must be provided. Also, depending on the power topology utilized,
additional power supply filtering may be required for the RF 1.0V and baseband, clock and VCO 1.8V supplies
to meet the required ripple specifications. This additional filtering will result in separate supply power nets being
generated from these four basic rails.
Table 8-1. Power Supply Rails Characteristics
SUPPLY VOLTAGE
DEVICE BLOCKS POWERED FROM THE SUPPLY
DEVICE POWER NETS
Input: VDDA_18VCO, VDDA_18CLK, VDDA_18PM,
VDDA_18BB, VIOIN_18CSI, VIOIN_18LVDS,
VIOIN_18
Synthesizer and APLL VCOs, crystal oscillator, IF
Amplifier stages, ADC, CSI2, LVDS, LVCMOS IO
1.8 V
LDO Output: VOUT_14SYNTH, VOUT_14APLL
Power Amplifier, Low Noise Amplifier, Mixers and LO
Distribution
1.0 V
Input: VDDA_10RF2, VDDA_10RF1
VIOIN
3.3 V (or 1.8 V for 1.8 V
I/O mode)
LVCMOS IO
1.2 V
1.7 V
Core Digital and SRAM
VDD, VDD_SRAM, VNWA
VPP
Programming OTP eFuse (For secure devices)
The 1.0 V and 1.8 V power supply ripple specifications are mentioned in Table 8-2 The spur and ripple levels
have a dB to dB relationship, for example, a 1dB increase in supply ripple leads to a ~1dB increase in spur level.
Values quoted are rms levels for a sinusoidal input applied at the specified frequency.
Table 8-2. Ripple Specifications (TBD)
RF RAIL
1V (µVRMS
TBD
VCO/IF RAIL
FREQUENCY (kHz)
)
1.8 V (µVRMS)
TBD
TBD
8.7 Power Consumption Summary
Table 8-3 and Table 8-4 summarize the power consumption at the power terminals.
Table 8-3. Maximum Current Ratings at Power Terminals
PARAMETER(1)
SUPPLY NAME
DESCRIPTION
MIN
TYP
MAX(1)
UNIT
Total current drawn by all
nodes driven by 1.2V rail
VDD, VDD_SRAM, VNWA
2100
Total current drawn by all
nodes driven by 1V rail
when all 4 transmitters
are used
VDDA_10RF1, VDDA_10RF2
2300
Current consumption
mA
VIOIN_18, VDDA_18CLK,
VDDA_18PM, VIOIN_18CSI,
VIOIN_18LVDS, VDDA_18BB,
VDDA_18VCO
Total current drawn by all
nodes driven by 1.8V rail
600
Total current drawn by all
nodes driven by 3.3V rail
VIOIN
50(2)
(1) The specified current values are at Max supply voltage level (Recommended operating conditions).
(2) The exact value will depend on the system use case and design.
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Table 8-4. Average Power Consumption at Power Terminals
PARAMETER
CONDITION(2)
DESCRIPTION
MIN
TYP(1)
MAX UNIT
25% duty
cycle
Use Case: Regular mode, 37.5
Msps sampling rate, 25.6 ms frame
periodicity, 256 chirps, 256 samples/
chirp, 2-µs idle time, 7us ADC start
time and excess ramp time
1.47
3TX, 4RX
50% duty
cycle
2.09
1.54
25% duty
cycle
Activity of cores :
Average power consumption
in single chip mode.
W
•
•
•
70% MSS R5F
70% C66x DSP and HWA
50% ARM M4F
4TX, 4RX
50% duty
cycle
2.25
Ethernet and CAN-FD interface is
enabled for data transfer
(1) The Power consumption numbers are for a typical usecase i.e. for a Nominal device at 25C ambient temperature and nominal voltage
conditions.
(2) Frame duty cycle represents the ratio of Frame Active and Interframe time.
8.8 RF Specifications
over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)
PARAMETER
MIN
TYP
13
-11
44
20
2
MAX
UNIT
dB
Noise figure
1-dB compression point (Out Of Band)(1)
dBm
dB
Maximum gain
Gain range
dB
Gain step size
dB
IF bandwidth(2)
15
MHz
Msps
Bits
dB
Receiver
ADC sampling rate
37.5
ADC resolution
12
-10
±0.5
±3
Return loss (S11)
Gain mismatch variation (over temperature)
Phase mismatch variation (over temperature)
Idle Channel Spurs
dB
°
-90
12
dBFS
dBm
°
Output power
Phase shifter accuracy
Temperature sensor accuracy
Amplitude noise
±5
Transmitter
±5
℃
-145
dBc/Hz
GHz
MHz/μs
dBc/Hz
Frequency range
76
81
Ramp rate
250(3)
Clock subsystem
Phase noise at 1- 76 to 77 GHz (VCO1)
MHz offset
-96
-95
76 to 81 GHz (VCO2)
(1) 1-dB Compression Point (Out Of Band) is measured by feeding a continuous wave tone at 5% of the programmed HPF cut-off
frequency (i.e. blocker tone) along with a second in-band tone. The compression point is determined by the blocker power that results
in a 1dB compression of the in-band tone at the RX ADC.
(2) The analog IF stages include a second order high pass filter that can be configured to the following -6dB corner frequencies:
Available HPF Corner Frequencies (kHz)
HPF
300, 350, 700, 1400,
The filtering performed by the digital baseband chain is targeted to provide:
•
•
Less than ±0.5 dB pass-band ripple/droop, and
Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
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(3) The max ramp rate depends on the PLL bandwidth configuration set using the"AWR_APLL_SYNTH_BW_CONTROL_SB" API. For
more details, refer to the mmWave Radar Interface Control document.
Figure 8-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain
programmed
16.0
15.5
15.0
14.5
14.0
13.5
13.0
-21
-24
-27
-30
-33
-36
-39
NF (dB)
In-band P1dB (dBm)
30
32
34
36
38
40
42
44
RX Gain (dB)
Figure 8-1. Noise Figure, In-band P1dB vs Receiver Gain
8.9 Thermal Resistance Characteristics
THERMAL METRICS(1) (4)
°C/W(2) (3)
3.3
RΘJC
RΘJB
RΘJA
PsiJC
Junction-to-case
Junction-to-board
Junction-to-free air
Junction-to-case
2.9
14.9
0.1
PsiJB
Junction-to-board
2.8
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
A junction temperature of 140°C is assumed.
(4) Air flow = 1 m/s
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8.10 Power Supply Sequencing and Reset Timing
The AWR294x device expects all external 1.2V, 1.8V and 3.3V voltage rails as well as all SOP[4:0] lines to be
stable before NRESET is deasserted for a successful device bootup. IO state is not guaranteed until the VIOIN
and VIOIN_18 supplies are available. Figure 8-2 describes the device wake-up sequence.
Note
Hardware platform must support supplying 1.7V on the VPP pin only during OTP eFuse programming.
SOP
Setup
Time
SOP
Hold time to
nRESET
DC power
Stable before
nRESET
MSS
BOOT
START
nRESET
ASSERT
tPGDEL
DC
Power
notOK
DC
Power
OK
QSPI
READ
release
VDD,
VDD_SRAM
VNWA
VIOIN_18
VDDA_18CLK
VIOIN_18CSI
VIOIN_18LVDS
VDDA_18BB
VDDA_10RF1
VDDA_10RF2
VIOIN
SOP IO
Reuse
SOP[4.3.2.1.0]
SOP IO‘s can be used as functional IO‘s
nRESET
WARMRESET
OUTPUT
VBGAP
OUTPUT
CLKP, CLKM
Using Crystal
QSPI_CS
OUTPUT
8 ms (XTAL Mode)
Figure 8-2. Device Wake-up Sequence
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8.11 Input Clocks and Oscillators
8.11.1 Clock Specifications
An external crystal is connected to the device pins. Figure 8-3 shows the crystal implementation.
Cf1
CLKP
Cp
40 MHz
CLKM
Cf2
Figure 8-3. Crystal Implementation
Note
The load capacitors, Cf1 and Cf2 in Figure 8-3, should be chosen such that Equation 1 is satisfied.
CL in the equation is the load specified by the crystal manufacturer. All discrete components used
to implement the oscillator circuit should be placed as close as possible to the associated oscillator
CLKP and CLKM pins.Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.
Note
The board routing parasitics between CLKP/CLKM pins also need to be included in the estimates of
CP
C f2
CL = C f1
´
+CP
C
f1 +C f2
(1)
Table 8-5 lists the electrical characteristics of the clock crystal.
Table 8-5. Crystal Electrical Characteristics (Oscillator Mode)
NAME
DESCRIPTION
Parallel resonance crystal frequency
Crystal load capacitance
MIN
TYP
40
8
MAX
UNIT
MHz
pF
fp
CL
ESR
5
12
50
Crystal ESR
Ω
Temperature range
Expected temperature range of operation
Crystal frequency tolerance(1) (2)
-40
125
℃
Frequency
tolererance
ppm
-100
100(3)
200
Drive level
50
μW
(1) The crystal manufacturer's specification must satisfy this requirement.
(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.
(3) For Ethernet operation, tighter specifications of less than 100 PPM frequency error is required. If the Ethernet interface is not used , a
PPM error up to 200 PPM can be tolerated.
In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM
is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 8-6
lists the electrical characteristics of the external clock signal.
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Table 8-6. External Clock Mode Specifications
SPECIFICATION
PARAMETER
UNIT
MAX
MIN
TYP
Frequency
40
MHz
AC-Amplitude
700
1200
10
mV (pp)
ns
DC-trise/fall
Input Clock: External AC-
Phase Noise at 1 kHz
Phase Noise at 10 kHz
Phase Noise at 100 kHz
Phase Noise at 1 MHz
Duty Cycle
-132
–143
–152
–153
65
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
%
coupled sine wave or DC-
coupled square wave Phase
Noise referred to 40 MHz
35
Freq Tolerance
-100
100
ppm
8.12 Peripheral Information
Initial peripheral descriptions and features are provided in the following sections. Additional peripheral details
and interface timing information shall be provided in a later product preview or datasheet release.
8.12.1 QSPI Flash Memory Peripheral
The device includes a Quad-Serial Peripheral Interface for external flash memory access. Flash memory can
be utilized for many purposes including: Secondary boot-loader memory, application program memory, security
keys storage, and long-term data logs for security and error conditions.
Following features are supported by the QSPI Interface on the device:
•
•
•
Loopback skew cancellation for clock signal to supported faster flash interface clock rates
Two chip-select signals to connect two external flash devices
Memory mapped 'direct' mode and software triggered 'indirect' mode of operation for performing flash data
transfers
8.12.1.1 QSPI Timing Conditions
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
15
pF
8.12.1.2 QSPI Timing Requirements(1) (2)
SPECIFICATION
NUMBER
PARAMETER
MIN
TYP
MAX
UNIT
Q12
tsu(D-SCLK)
Setup time, D[3:0] valid before falling SCLK edge
(Q12)
ns
13.2
1
Q13
Q14
th(SCLK-D)
tsu(D-SCLK)
Hold time, D[3:0] valid after falling SCLK edge (Q13)
ns
ns
Setup time, final D[3:0] bit valid before final falling
SCLK edge
13.2-P(3)
Q15
th(SCLK-D)
Hold time, final D[3:0] bit valid after final falling SCLK
edge
ns
1+P(3)
(1) Clock Mode 0 (clock polarity = 0 ; clock phase = 0) is the mode of operation.
(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although
nonstandard, The falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Mode 0.
(3) P = SCLK period in ns.
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8.12.1.3 QSPI Switching Characteristics(1) (2)
SPECIFICATION
NUMBER
PARAMETER
MIN
TYP
MAX UNIT
Q1
Q2
Q3
Q4
Q5
Q6
Q7
tc(SCLK)
Cycle time, sclk
15
0.5*P – 1.5
0.5*P – 1.5
–M*P – 1
N*P – 1
ns
ns
ns
ns
ns
ns
ns
ns
tw(SCLKL)
Pulse duration, sclk low
tw(SCLKH)
td(CS-SCLK)
td(SCLK-CS)
td(SCLK-D1)
tena(CS-D1LZ)
tdis(CS-D1Z)
Pulse duration, sclk high
Delay time, sclk falling edge to cs active edge
Delay time, sclk falling edge to cs inactive edge
Delay time, sclk falling edge to d[0] transition
Enable time, cs active edge to d[0] driven (lo-z)
–M*P + 2.5
N*P + 2.5
5.5
–2.5
–P – 4
–P +1
Disable time, cs active edge to d[0] tri-stated
(hi-z)
Q8
Q9
–P – 4
–3– P
–P +1
td(SCLK-D1)
Delay time, sclk first falling edge to first d[1]
transition (for PHA = 0 only)
ns
3.5 – P
(1) P = SCLK period in ns.
(2) M = QSPI_SPI_DC_REG.DDx + 1, N = 2
Figure 8-4. QSPI Read (Clock Mode 0)
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PHA=0
cs
Q5
Q4
Q1
Q2
Q3
POL=0
sclk
Q8
Q6
Q6
Q7
Q9
Command
Bit n-1
Q6
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS85v_TIMING_OSPI1_04
Figure 8-5. QSPI Write (Clock Mode 0)
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8.12.2 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
8.12.2.1 MibSPI Peripheral Description
The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
The device includes two, Multi-Buffered Serial Peripheral Interface (MIBSPI) in the Main Sub-System (MSS).
These are intended for external MCU, PMIC, EEPROM and Watchdog communication.
Standard and MibSPI modules have the following features:
•
•
•
•
16-bit shift register
Receive buffer register
8-bit baud clock generator
SPICLK can be internally-generated (Controller mode) or received from an external clock source
(Peripheral mode)
•
•
•
Maximum clock rate supported over each MIBSPI module shall be 40MHz.
Each word transferred can have a unique format.
SPI I/Os not used in the communication can be used as digital input/output signals
8.12.2.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit
transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be
partitioned into multiple transfer group with variable number of buffers each.
Section 8.12.2.2.2 and Section 8.12.2.2.3 assume the operating conditions stated in Section 8.12.2.2.1.
8.12.2.2.1 SPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD Output load capacitance
2
15
pF
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8.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1) (2) (3)
NO.
PARAMETER
MIN
40
TYP
MAX
256tc(VCLK)
UNIT
1
tc(SPC)M
Cycle time, SPICLK(4)
ns
tw(SPCH)M
tw(SPCL)M
tw(SPCL)M
tw(SPCH)M
td(SPCH-SIMO)M
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
2(4)
ns
ns
3(4)
0.5tc(SPC)M
–
14
4(4)
ns
ns
td(SPCL-SIMO)M
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
0.5tc(SPC)M
–
14
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
0.5tc(SPC)M – 18
0.5tc(SPC)M – 18
5(4)
CSHOLD = 0
(C2TDELAY+2)*tc(VCLK
) – 7.5
(C2TDELAY+2) *
tc(VCLK) + 7
Setup time CS active until SPICLK high
(clock polarity = 0)
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
6(5)
tC2TDELAY
ns
ns
(C2TDELAY+2)*tc(VCLK
) – 7.5
(C2TDELAY+2) *
tc(VCLK) + 7
Setup time CS active until SPICLK low
(clock polarity = 1)
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
Hold time, SPICLK low until CS inactive (clock polarity = 0)
Hold time, SPICLK high until CS inactive (clock polarity = 1)
0.5*tc(SPC)M
(T2CDELAY + 1)
*tc(VCLK) – 7
+
0.5*tc(SPC)M +
(T2CDELAY + 1) *
tc(VCLK) + 7.5
7(5)
tT2CDELAY
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(T2CDELAY + 1)
*tc(VCLK) – 7
(T2CDELAY + 1) *
tc(VCLK) + 7.5
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
th(SPCL-SOMI)M
th(SPCH-SOMI)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
5
5
3
3
8(4)
ns
ns
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
9(4)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
(1) The Controller bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).
(2) tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, refer to the device Technical Reference Manual.
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(3) When the SPI is in controller mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25ns, where PS is the prescale value set in the
SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
11
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1
4
5
Master Out Data Is Valid
SPISIMO
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 8-6. SPI Controller Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
6
7
Figure 8-7. SPI Controller Mode Chip Select Timing (CLOCK PHASE = 0)
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8.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1) (2) (3)
NO.
PARAMETER
MIN
40
TYP
MAX
256tc(VCLK)
UNIT
1
tc(SPC)M
Cycle time, SPICLK(4)
ns
tw(SPCH)M
tw(SPCL)M
tw(SPCL)M
tw(SPCH)M
td(SPCH-SIMO)M
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
2(4)
ns
ns
3(4)
0.5tc(SPC)M
–
14
4(4)
ns
ns
td(SPCL-SIMO)M
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
0.5tc(SPC)M
–
14
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
tC2TDELAY
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
0.5tc(SPC)M – 18
0.5tc(SPC)M – 18
5(4)
Setup time CS active until SPICLK high
(clock polarity = 0)
CSHOLD = 0
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
(C2TDELAY +
2)*tc(VCLK) – 7
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
(C2TDELAY +
2)*tc(VCLK) – 7
6(5)
ns
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
(C2TDELAY+2)*tc(V
CLK) – 7
Setup time CS active until SPICLK low
(clock polarity = 1)
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+3)*tc(V
CLK) – 7
(C2TDELAY+3) *
tc(VCLK) + 7.5
Hold time, SPICLK low until CS inactive (clock polarity = 0)
Hold time, SPICLK high until CS inactive (clock polarity = 1)
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
7(5)
8(4)
9(4)
tT2CDELAY
ns
ns
ns
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
5
5
3
3
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
th(SPCL-SOMI)M
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
th(SPCH-SOMI)M
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
(1) The Controller bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).
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(2) tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, refer to the device Technical Reference Manual.
(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the
SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Master Out Data Is Valid
Data Valid
SPISIMO
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 8-8. SPI Controller Mode External Timing (CLOCK PHASE = 1)
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Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
6
7
Figure 8-9. SPI Controller Mode Chip Select Timing (CLOCK PHASE = 1)
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8.12.2.3 SPI Peripheral Mode I/O Timings
8.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output)(1) (2) (3)
SPECIFICATIO
N NUMBER
PARAMETER(5)
MIN
TYP
MAX
UNIT
1
tc(SPC)S
Cycle time, SPICLK (4)
50
20
20
20
20
ns
ns
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
td(SPCH-SOMI)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
2
3
4
ns
ns
Delay time, SPISOMI valid after SPICLK high
(clock polarity = 0)
10
10
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
td(SPCH-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
2
2
5
4
ns
ns
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
Delay time, SPISOMI valid after SPICLK high
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
14
14
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1; clock phase = 0) OR (clock polarity =
0; clock phase = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
2
2
6
6
1
1
5
6
7
ns
ns
ns
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1; clock phase = 0) OR (clock
polarity = 0; clock phase = 1)
Setup time, SPISIMO before SPICLK low (clock
polarity = 0; clock phase = 0) OR (clock polarity =
1; clock phase = 1)
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK high (clock
tsu(SIMO-SPCH)S polarity = 1; clock phase = 0) OR (clock polarity =
0; clock phase = 1)
Hold time, SPISIMO data valid after SPICLK low
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK high
(clock polarity = 1; clock phase = 0) OR (clock
polarity = 0; clock phase = 1)
th(SPCL-SIMO)S
(1) The Controller bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).
(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.
(3) tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, refer to the device Technical Reference Manual.
(4) When the SPI is in Peripheral mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns,
where PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: tc(SPC)S = 2tc(MSS_VCLK) ≥ 25 ns.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 8-10. SPI Peripheral Mode External Timing (CLOCK PHASE = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 8-11. SPI Peripheral Mode External Timing (CLOCK PHASE = 1)
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8.12.3 Ethernet Switch (RGMII/RMII/MII) Peripheral
The device integrates a two port Ethernet with one external RGMII/RMII/MII port and another port servicing the
Main Sub-System (MSS). This interface is intended to operate primarily as a 100Mbps ECU interface. It can also
be used as an instrumentation interface.
•
•
•
•
Full Duplex 10/100Mbps wire rate interface to Ethernet PHY over RGMII, RMII, or MII parallel interface
MDIO Clause 22 and 45 PHY management interface
IEEE 1588 Synchronous Ethernet support
AWR synchronous trigger output allowing Ethernet to trigger radar frames
8.12.3.1 RGMII/GMII/MII Timing Conditions
SPECIFIC
ATION
PARAMETER
MIN
TYP
MAX
UNIT
NUMBER
Input Conditions
1
2
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD Output load capacitance
3
2
20
pF
8.12.3.2 RGMII Transmit Clock Switching Characteristics
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
MAX
440
44
UNIT
1
tc(TXC)
Cycle time, rgmiin_txc
360
36
ns
ns
ns
ns
ns
ns
ns
ns
2
3
4
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, rgmiin_txc high
Pulse duration, rgmiin_txc low
Transition time, rgmiin_txc
160
16
240
24
160
16
240
24
0.75
0.75
8.12.3.3 RGMII Transmit Data and Control Switching Characteristics
NO.(1) PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
5
tosu(TXD-TXC)
Output Setup time, transmit selected signals valid to
MSS_RGMII_TCLK high/low
RGMII, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
6
toh(TXC-TXD)
Output Hold time, transmit selected signals valid
after MSS_RGMII_TCLK high/low
RGMII, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
(1) For RGMII, transmit selected signals include: MSS_RGMII_TXD[3:0] and MSS_RGMII_TCTL.
1
4
2
4
3
rgmiin_txc(A)
[internal delay enabled]
5
rgmiin_txd[3:0](B)
rgmiin_txctl(B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
6
A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
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B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the rising edge of
rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on rising edge of rgmiin_txc and
TXERR of falling edge of rgmiin_txc.
Figure 8-12. RGMII Transmit Interface Switching Characteristics
8.12.3.4 RGMII Recieve Clock Timing Requirements
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
360
36
MAX
440
44
UNIT
ns
1
tc(RXC)
Cycle time, rgmiin_rxc
ns
2
3
4
tw(RXCH)
tw(RXCL)
tt(RXC)
Pulse duration, rgmiin_rxc high
Pulse duration, rgmiin_rxc low
Transition time, rgmiin_rxc
160
16
240
24
ns
ns
160
16
240
24
ns
ns
0.75
0.75
ns
ns
8.12.3.5 RGMII Recieve Data and Control Timing Requirements
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
5
tsu(RXD-RXCH)
Setup time, receive selected signals valid before MSS_RGMII_RCLK
high/low
1
ns
6
th(RXCH-RXD)
Hold time, receive selected signals valid after MSS_RGMII_RCLK
high/low
4.5
ns
1
4
2
4
3
rgmiin_rxc(A)
5
1st Half-byte
6
2nd Half-byte
rgmiin_rxd[3:0](B)
rgmiin_rxctl(B)
RGRXD[3:0]
RXDV
RGRXD[7:4]
RXERR
A. rgmiin_rxc must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. MSS_RGMII_RXD[3:0] carries data bits 3-0 on the rising edge
of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on rising edge of rgmiin_rxc and
RXERR on falling edge of rgmiin_rxc.
Figure 8-13. MAC Receive Interface Timing, RGMIIn operation
8.12.3.6 RMII Transmit Clock Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
20
7
MAX
UNIT
ns
RMII7 tc(REF_CLK)
RMII8 tw(REF_CLKH)
RMII9 tw(REF_CLKL)
RMII10 tt(REF_CLK)
Cycle time, REF_CLK
Pulse duration, REF_CLK high
Pulse duration, REF_CLK low
Transistion time, REF_CLK
13
13
3
ns
7
ns
ns
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8.12.3.7 RMII Transmit Data and Control Switching Characteristics
NO.
RMII11 td(REF_CLK-TXD)
tdd(REF_CLK-TXEN)
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
Delay time, REF_CLK high to selected transmit signals valid
3
14.2
ns
RMII7
RMII8
RMII9
RMII10
RMII11
REF_CLK (PRCM)
rmiin_txd1−rmiin_txd0,
rmiin_txen (Outputs)
SPRS8xx_GMAC_RMIITX_06
Figure 8-14. MAC Transmit Interface Timing, RMIIn Operation
8.12.3.8 RMII Receive Clock Timing Requirements
NO.
PARAMETER
DESCRIPTION
MIN
20
7
MAX
UNIT
ns
RMII1 tc(REF_CLK)
RMII2 tw(REF_CLKH)
RMII3 tw(REF_CLKL)
RMII4 ttt(REF_CLK)
Cycle time, REF_CLK
Pulse duration, REF_CLK high
Pulse duration, REF_CLK low
Transistion time, REF_CLK
13
13
3
ns
7
ns
ns
8.12.3.9 RMII Receive Data and Control Timing Requirements
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII5
tsu(RXD-REF_CLK)
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
Setup time, receive selected signals valid before REF_CLK
4
ns
RMII6
Hold time, receive selected signals valid after REF_CLK
2
ns
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
RMII1
RMII3
RMII2
RMII4
RMII6
RMII5
REF_CLK (PRCM)
rmiin_rxd1−rmiin_rxd0,
rmiin_crs, rmin_rxer (inputs)
SPRS8xx_GMAC_RMIIRX_05
Figure 8-15. MAC Receive Interface Timing, RMIIn operation
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8.12.3.10 MII Transmit Switching Characteristics
NO.
PARAMETER
td(TX_CLK-TXD)
td(TX_CLK-TX_EN)
td(TX_CLK-TX_ER)
DESCRIPTION
MIN
MAX
UNIT
1
Delay time, miin_txclk to transmit selected signals valid
3
25
ns
1
miin_txclk (input)
miin_txd3 − miin_txd0,
miin_txen, miin_txer (outputs)
Figure 8-16. MAC Transmit Interface Timing, MIIn operation
8.12.3.11 MII Receive Clock Timing Requirements
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
400
40
MAX
UNIT
ns
1
tc(RX_CLK)
Cycle time, miin_rxclk
ns
2
3
4
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Pulse duration, miin_rxclk high
Pulse duration, miin_rxclk low
Transition time, miin_rxclk
140
14
260
26
260
26
3
ns
ns
140
14
ns
ns
ns
3
ns
1
4
2
3
miin_rxclk
4
Figure 8-17. Clock Timing (MAC Receive) - MIIn operation
8.12.3.12 MII Receive Timing Requirements
NO.
PARAMETER
tsu(RXD-RX_CLK)
DESCRIPTION
MIN
MAX
UNIT
1
Setup time, receive selected signals valid before miin_rxclk
8
ns
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
th(RX_CLK-RXD)
2
Hold time, receive selected signals valid after miin_rxclk
8
ns
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
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1
2
miin_rxclk (Input)
miin_rxd3−miin_rxd0,
miin_rxdv, miin_rxer (Inputs)
Figure 8-18. MAC Receive Interface Timing, MIIn operation
8.12.3.13 MII Transmit Clock Timing Requirements
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
400
40
MAX
UNIT
ns
1
tc(TX_CLK)
Cycle time, miin_txclk
ns
2
3
4
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Pulse duration, miin_txclk high
Pulse duration, miin_txclk low
Transition time, miin_txclk
140
14
260
26
260
26
3
ns
ns
140
14
ns
ns
ns
3
ns
1
4
2
3
miin_txclk
4
Figure 8-19. Clock Timing (MAC Transmit) - MIIn operation
8.12.3.14 MDIO Interface Timings
CAUTION
The IO Timings provided in this section are only valid for some MAC usage modes when the
corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables
found in this section.
Table 8-7, Table 8-8 and Figure 8-20 present switching characteristics and timing requirements for the MDIO
interface.
Table 8-7. Timing Requirements for MDIO Input
No
PARAMETER
tc(MDC)
DESCRIPTION
MIN
400
160
160
90
MAX
UNIT
ns
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
Cycle time, MDC
tw(MDCH)
Pulse Duration, MDC High
ns
tw(MDCL)
Pulse Duration, MDC Low
ns
tsu(MDIO-MDC)
th(MDIO_MDC)
Setup time, MDIO valid before MDC High
Hold time, MDIO valid from MDC High
ns
0
ns
Table 8-8. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MDIO6
tt(MDC)
Transition time, MDC
5
ns
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Table 8-8. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(continued)
NO
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MDIO7
td(MDC-MDIO)
Delay time, MDC low to MDIO valid
10
(P * 0.5) - 10
ns
1
MDIO2
MDIO3
MDCLK
MDIO6
MDIO6
MDIO4
MDIO5
MDIO
(input)
MDIO7
MDIO
(output)
Figure 8-20. MAC MDIO diagrams
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8.12.4 LVDS/Aurora Instrumentation and Measurement Peripheral
The device supports a set of LVDS interfaces in two different modes.
•
•
Legacy LVDS mode
STM-TWP Aurora interface
The LVDS IO are shared between the above two measurement interface options.
Following features are supported :
•
•
2-data lane LVDS interface (two additional lanes for Data Clock and Frame Clock)
4-Lane STM-TWP-Aurora-LVDS interface mode. It has the following features:
– Configurable 4/2/1 lane of operation.
– Transmit data compliant to Aurora 8B/10B Serial Simplex Operation
– Transmit data compliant to Aurora 64B/66B Serial Simplex Operation
Please see the device TRM for information regarding programming options for both LVDS interfaces.
8.12.4.1 LVDS Interface Configuration
The supported LVDS lane configuration is four Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M)
and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface supports the following data rates:
•
•
•
•
•
•
•
900 Mbps (450 MHz DDR Clock)
600 Mbps (300 MHz DDR Clock)
450 Mbps (225 MHz DDR Clock)
400 Mbps (200 MHz DDR Clock)
300 Mbps (150 MHz DDR Clock)
225 Mbps (112.5 MHz DDR Clock)
150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the number of toggles in the clock is equivalent to data.
LVDS_TXP/M
LVDS_FRCLKP/M
Data bitwidth
LVDS_CLKP/M
Figure 8-21. LVDS Interface Lane Configuration And Relative Timings
8.12.4.2 LVDS Interface Timings
Trise
LVDS_CLK
Clock Jitter = 6sigma
LVDS_TXP/M
LVDS_FRCLKP/M
1100 ps
Figure 8-22. Timing Parameters
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Table 8-9. LVDS Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Duty Cycle Requirements
max 1 pF lumped capacitive load on
LVDS lanes
48%
52%
Output Differential Voltage
peak-to-peak single-ended with 100 Ω
resistive load between differential pairs
250
450
mV
Output Offset Voltage
Trise and Tfall
1125
1275
mV
ps
20%-80%, 900 Mbps
900 Mbps
330
80
Jitter (pk-pk)
ps
8.12.5 UART Peripheral
The device includes four UART interfaces. One UART is intended as a secondary boot loader source, one is
intended for use as a register debug interface (with XDS110 emulator) and the remaining two are meant for
general UART communication support.
•
•
Maximum baud-rate supported shall be at least 1536K baud in all the different clock frequency modes
UART interfaces multiplexed with other I/O to allow for widest peripheral use flexibility
8.12.5.1 SCI Timing Requirements
MIN
TYP
MAX
UNIT
f(baud)
Supported baud rate at 20 pF
921.6
kHz
8.12.6 Inter-Integrated Circuit Interface (I2C)
The device supports one Controller/Target Inter-integrated Circuit interface and is intended to be connected to an
external PMIC or EEPROM device (alternative control SPI).
The I2C has the following features:
•
Standard/fast mode I2C interface compliant with Philips I2C bus specification, v2.1 (The I2C Specification,
Philips document number 9398 393 40011)
– Bit/Byte format transfer
– 7-bit and 10-bit device addressing modes
– General call
– START byte
– Multi-controller transmitter/ target receiver mode
– Multi-controller receiver/ target transmitter mode
– Combined controller transmit/receive and receive/transmit mode
– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)
Free data format
Two DMA events (transmit and receive)
DMA event enable/disable capability
Module enable/disable capability
The SDA and SCL are optionally configurable as general purpose I/O
Slew rate control of the outputs
Open drain control of the outputs
Programmable pullup/pulldown capability on the inputs
Supports Ignore NACK mode
•
•
•
•
•
•
•
•
•
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Note
This I2C module does not support:
•
•
•
High-speed (HS) mode
C-bus compatibility mode
The combined format in 10-bit address mode (the I2C sends the target address second byte every
time it sends the target address first byte)
8.12.6.1 I2C Timing Requirements(1)
STANDARD MODE
FAST MODE
UNIT
MIN
10
MAX
MIN
2.5
MAX
tc(SCL)
Cycle time, SCL
μs
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low
(for a repeated START condition)
4.7
0.6
th(SCLL-SDAL)
Hold time, SCL low after SDA low
4
0.6
μs
(for a START and a repeated START condition)
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
μs
μs
μs
μs
μs
tw(SCLH)
Pulse duration, SCL high
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0
(1)
th(SCLL-SDA)
3.45
0.9
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
4.7
1.3
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high
(for STOP condition)
4
0.6
0
μs
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(2) (3)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the
SCL signal.
(3) Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SP)
tw(SCLL)
tr(SCL)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
tf(SCL)
th(SCLL-SDAL)
tsu(SCLH-SDAL)
th(SDA-SCLL)
Stop
Start
Repeated Start
Stop
Figure 8-23. I2C Timing Diagram
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Note
•
•
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW
period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-
mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line tr max + tsu(SDA-SCLH)
.
8.12.7 Controller Area Network - Flexible Data-rate (CAN-FD)
The device integrates two CAN-FD interfaces, MSS_MCANA and MSS_MCANB. This enables support of a
typical use case where one CAN-FD interface is used as ECU network interface while the other interface is used
as a local network interface, providing communication with the neighboring sensors.
•
•
•
Support CAN-FD according to ISO 11898-7 protocol with data rate up to 8Mbps
Multiplexed GPIO can be used for CAN-FD external driver control
AWRx synchronous trigger output allows CAN-FD to trigger radar frames
8.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
PARAMETER(1)
MIN
TYP
MAX
UNIT
td(MSS_CANA_TX)
td(MSS_CANB_TX)
td(MSS_MCANA_RX)
td(MSS_MCANB_RX)
Delay time, transmit shift register to
MSS_CANA_TX pin
15
ns
Delay time, transmit shift register to
MSS_CANB_TX pin
15
10
10
ns
ns
ns
Delay time, MSS_MCANA_RX pin to receive
shift register
Delay time, MSS_MCANB_RX pin to receive
shift register
(1) These values do not include rise/fall times of the output buffer.
8.12.8 CSI2 Receiver Peripheral
The device integrates one 3-lane MIPI CSI2, D-PHY receiver peripheral in the Radio processing subsystem.
The CSI2 interface is primarily functional of operating as a hardware-in-the-loop (HIL) interface, allowing for the
playback of recorded radar data for development purposes.
•
•
•
•
•
Interface is compliant with the MIPI CSI-2 D-PHY standard revision 1.2
1x 3-lane (2 data lanes, 1 clock lane) CSI2 receiver interface, working simultaneously at 600 Mbps/lane
2-lane, or 1-lane CSI2 configurations
Support for 4 simultanoeus virtual channels and data types
Support for 8/10/12/14/16-bit RAW data mode with capability of sign extension or zero padding to align with
16-bit memory addressing for RAW 10/12/14 modes
•
Support for user defined data types
Please refer to the device Technical Reference Manual for a complete description of all the programmable
options.
8.12.8.1 CSI2 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
Low Power Receiver (LP-RX)
(1)
VIL
Logic 0 input threshold
Logic 1 input threshold
Input Hysteresis
550
mV
mV
mV
(2)
VIH
880
25
VHYST
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
High Speed Receiver (HS-RX)
VIDTH
Differential input high threshold
70
mV
mV
VIDTL
Differential input low threshold
-70
VIDMAX
VILHS
Maximum differential input voltage
Single-ended input low voltage
270
mV
-40
70
mV
VIHHS
Single-ended input high voltage
Common-mode voltage
460
330
200
50
mV
VCMRXDC
ΔVCMRX(HF)
ΔVCMRX(LF)
mV
Common-mode interference beyond 450 MHz
mVPP
mVPP
Common mode interference 50MHz – 450MHz
-50
HS DATA-CLOCK Timing Specification (3) (5)
UIINST
TSETUP
THOLD
TR, , TF
Data/Clock Unit Interval
1.11
166
166
166
ns
ps
ps
ps
Data to Clock setup time
Clock to Data hold time
Rise/Fall Times
(4)
0.4*UIINST
(1) The input low-level voltage, VIL, is the voltage at which the receiver is required to detect a low state in the input signal. VIL is larger
than the maximum single-ended line voltage during HS transmission. Therefore, both LP receivers will detect low during HS signaling
(2) The input high-level voltage, VIH, is the voltage at which the receiver is required to detect a high state in the input signal.
(3) TSKEW in the figure is the skew between the clock and data HS signals that can be tolerated at the receiver input. It is only a
descriptive parameter. Rx timing is specified by TSETUP/THOLD only.
(4) Rise/Fall from VIDTL to VIDTH
.
(5) Setup/hold specification is assuming identical common mode and rise/fall time for both data and clock lane at receiver input. i.e.
VCMRXDC and TR, TF must be same for clock lane and data lane while measuring TSETUP and THOLD
Figure 8-24. Clock and Data Timing in HS Transmission
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8.12.9 Enhanced Pulse-Width Modulator (ePWM)
The device includes three Enhanced Pulse-Width Modulation (ePWM) modules. These modules can be used
to generate duty-cycled controlled waveforms for a power regulator, or a power management systems, or more
complex waveforms for motor control applications.
The module supports the following features:
•
•
Dedicated 16-bit time-base counter with period and frequency control for each PWM module
Each module contains two PWM outputs (EPWMxA and EPWMxB) that shall be usable in the following
configurations:
– Two independent PWM outputs with single-edge operation
– Two independent PWM outputs with dual-edge symmetric operation
– One independent PWM output with dual-edge asymmetric operation
8.12.10 General-Purpose Input/Output
Section 8.12.10.1 lists the switching characteristics of output timing relative to load capacitance.
8.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)(1) (2)
PARAMETER
TEST CONDITIONS
CL = 20 pF
VIOIN = 1.8V
VIOIN = 3.3V
UNIT
2.8
6.4
9.4
2.8
6.4
9.4
3.3
6.7
9.6
3.1
6.6
9.6
3.0
6.9
10.2
2.8
6.6
9.8
3.3
7.2
10.5
3.1
6.6
9.6
tr
tf
tr
tf
Max rise time
CL = 50 pF
ns
CL = 75 pF
Slew control = 0
CL = 20 pF
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
Max fall time
Max rise time
Max fall time
ns
ns
ns
Slew control = 1
(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).
(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.
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8.13 Emulation and Debug
8.13.1 Emulation and Debug Description
8.13.2 JTAG Interface
The JTAG interface implements the IEEE1149.1 standard interface for processor debug and boundary scan
testing.
Section 8.13.2.1 and Section 8.13.2.2 assume the operating conditions stated in Figure 8-25.
8.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
Table 8-10. JTAG Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
15
pF
Table 8-11. JTAG Timing Requirements
NO.
1
MIN
TYP
MAX
UNIT
ns
tc(TCK)
Cycle time TCK
33.33
13.33
1a
tw(TCKH)
Pulse duration
TCK high (40% of
tc)
ns
1b
3
tw(TCKL)
Pulse duration
TCK low (40% of
tc)
13.33
2.5
2.5
18
ns
ns
ns
ns
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
Input setup time
TDI valid to TCK
high
3
Input setup time
TMS valid to TCK
high
4
Input hold time
TDI valid from
TCK high
4
Input hold time
TMS valid from
TCK high
18
8.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
NO.
PARAMETER
MIN
TYP
MAX
UNIT
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
27.1
ns
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1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
SPRS91v_JTAG_01
Figure 8-25. JTAG Timing
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8.13.3 ETM Trace Interface
The ETM Trace interface provides a means of exporting real time processor debug information to a host PC
through a compatible emulator toolset.
Section 8.13.3.1 and Section 8.13.3.2 describe the operating conditions shown in Figure 8-26 and Figure 8-27.
8.13.3.1 ETM TRACE Timing Requirements
MIN
TYP
MAX
UNIT
Output Conditions
CLOAD
Output load capacitance
2
20
pF
8.13.3.2 ETM TRACE Switching Characteristics
NO.
PARAMETER
MIN
TYP
MAX
UNIT
tcyc(ETM)
th(ETM)
tl(ETM)
Cycle time, TRACECLK
period
16
ns
1
Pulse Duration, TRACECLK
High
7
7
ns
ns
2
3
Pulse Duration, TRACECLK
Low
4
5
tr(ETM)
Clock and data rise time
Clock and data fall time
3.3
3.3
ns
ns
ns
tf(ETM)
td(ETMTRACECLKH-ETMDATAV)
Delay time, ETM trace clock
high to ETM data valid
1
1
14.5
6
7
td(ETMTRACECLKl-ETMDATAV)
Delay time, ETM trace clock
low to ETM data valid
ns
14.5
tl(ETM)
th(ETM)
tr(ETM)
tf(ETM)
tcyc(ETM)
Figure 8-26. ETMTRACECLKOUT Timing
Figure 8-27. ETMDATA Timing
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9 Detailed Description
9.1 Overview
The AWR294x device includes the entire Millimeter Wave blocks, and analog baseband signal chain, for three
or four transmitters and four receivers, as well as a customer-programmable MCU and DSP. This device is
applicable as a radar-on-a-chip in use-cases with modest requirements for memory, processing capacity, and
application code size. These could be cost-sensitive automotive applications that are evolving from 24 GHz
narrowband implementation and some emerging, ultra-short-range radar applications.
To support additional scalability, the device can also be paired with an external host MCU, to provide additional
control and processing platform so as to address more complex applications. To interface to external host MCU,
the device provides SPI, CAN-FD and I2C for host control.
9.2 Functional Block Diagram
Figure 9-1 represents the functional block diagram for the device.
9
GPADC
Main Sub-System
(Customer Programmed)
Serial Flash Interface
QSPI
SPI
LNA
LNA
LNA
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
Optional External
MCU Interface
ARM Cortex-R5F
(Lock Step)
@ 300 MHz
PMIC Control
Digital
Front-end
SPI / I2C
CAN-FD
Primary Communication
Interfaces (Automotive)
(Decimation
Filter Chain)
Prog
Cache
16KB
Data
Cache
16KB
L1 Data
RAM
128KB(A)
L2 RAM
960KB(A)
Debug
UARTs
For Debug
Test/
Debug
JTAG for Debug/
Development
DMA
Hardware Security
Module (B)
100Mbps Alternate Data
Communication Interface
PA
û-
û-
û-
û-
Ethernet
ADC
Buffer
Mailbox
PA
PA
PA
DSP Sub-System
(Customer Programmed)
Synth
(20 GHz)
Ramp
Generator
x4
C66x DSP Core
@ 360 MHz
Radio (BIST)
Processor
Aurora
LVDS
High-Speed ADC Output
Interface (for Recording)
High-Speed Interface to
enable playback of the
captured data
(For RF Calibration
& Self-Test œ TI
Programmed)
CSI2 RX
L1P L1D
(32KB) (32KB)
L2
(384KB)
Prog RAM
& ROM
Data
RAM
DMA
CRC
Radar Data Memory(A)
AWR2943 - 2.0MB /
AWR2944 - 2.5MB
Osc.
GPADC
VMON
Temp
Radio Processor
Sub-System
(TI Programmed)
Radar Hardware Accelerator
(FFT, Log mag, and others)
RF/Analog Sub-System
A. Configurable memory can be switched from Radar Data memory to the Main R5F program and Data RAMs per application usecase
needs.
B. This feature is only available in select part variants as indicated by the Device Type identifier in the Section 3, Device Information table.
Figure 9-1. Functional Block Diagram
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9.3 Subsytems
9.3.1 RF and Analog Subsystem
The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,
IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The four transmit and
the receive channels can all be operated simultaneously for transmit beamforming purpose and receiving data
as required.
9.3.1.1 RF Clock Subsystem
The device clock subsystem generates 76 to 81 GHz from an input reference of 40 MHz crystal. It has a built-in
oscillator circuit followed by an Analog PLL and a RF synthesizer circuit. The output of the RF synthesizer is
then processed by an x4 multiplier to create the required frequency in the 76 to 81 GHz spectrum. The RF
synthesizer output can be modulated by the timing engine block to create the required waveforms for effective
sensor operation or it can input a fixed signal of 1GHz directly from APLL.
The Analog PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the
quality of the generated clock.
Figure 9-2 describes the clock subsystem.
Self Test
RX LO
Timing
Engine
SYNC_OUT
SYNCIN
x4
MULT
TX LO
RF SYNTH
~1 GHz
(Fixed Clock Domain)
APLL
XO/
Slicer
40 MHz
Figure 9-2. RF Clock Subsystem
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9.3.1.2 Transmit Subsystem
The device Transmit subsystem consists of four parallel transmit chains, each with independent phase and
amplitude control. All four transmitters can be used simultaneously or in time-multiplexed fashion. The device
supports binary phase modulation and a 6 bit programmable phase shifter for beamforming control on a per
chirp basis for each channel as indicated in the figure below.
Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit chains also
support programmable backoff for system optimization.
Figure 9-3 describes the transmit subsystem.
Self Test
LO Loopback
Path
Beamforming
Control
PA Loopback
Path
6 bits
PCB
12dBm
@ 50 Ω
û-
LO
0/180°
(from Timing Engine)
Figure 9-3. Transmit Subsystem (Per Channel)
9.3.1.3 Receive Subsystem
The device Receive subsystem consists of four parallel channels. A single receive channel consists of an LNA,
mixer, IF filtering, ADC conversion, and decimation. All four receive channels can be operational at the same
time. An individual power-down option is also available for system optimization.
The device supports a real-only receiver. The band-pass IF chain has configurable cutoff frequencies above 350
kHz and can support bandwidths up to 15 MHz.
Figure 9-4 describes the receive subsystem.
Self Test
RSSI
Loopback
Path
Saturation Detect
DAC
PCB
50 Ω
GSG
LNA
IFA
DSM
LORX
Figure 9-4. Receive Subsystem (Per Channel)
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9.3.2 Processor Subsystem
Figure 9-5 shows the block diagram for customer programmable processor subsystems in the device. At a
high level there are two customer programmable subsystems. Left hand side shows the DSP Subsystem
which contains TI's high performance C66x DSP, HWA 2.0, a high-bandwidth interconnect for high performance
(128-bit, 150MHz), and associated peripherals – six EDMAs for data transfer,Aurora and LVDS interface for
Measurement data output, L3 Radar data cube memory, ADC buffers, CRC engine, and data handshake
memory (additional memory provided on interconnect).
For more information, see the TMS320C66x DSP CorePac User Guide
The right side of the diagram shows the Main subsystem (MSS). Main subsystem as the name suggests is the
primary controller of the device and controls all the device peripherals and house-keeping activities of the device.
Main subsystem contains Cortex-R5F (MSS R5F) processor and associated peripherals and housekeeping
components such as EDMAs, CRC and Peripherals (I2C, UART, SPIs, CAN-FD, EPWM, and others) connected
to the primary Interconnect through Peripheral Central Resource (PCR interconnect).
The Radio Processing Subsytem or the BIST Subsystem (RSS) is responsible for initializing and calibrating the
Analog/RF modules. It periodically monitors the Analog/RF functionality such that all the Analog/RF modules
work in their defined limits.
General Purpose ADC (GPADC), Fast Fourier Transformation engine (FFT engine) and other modules are
provided to monitor the signal from different points in the transmitter and receiver chains. Digital front-end filters
(DFE), Ramp Generation module and Analog/DFE registers, which are mainly under the control of BSS, can be
indirectly controlled through the API calls from the Main Subsytem.
The device also integrates one two-lane CSI2 receiver interfaces in the Radio processing subsystem. The prime
functionality of this interface is the Hardware in loop (HIL) functionality, that can be used to perform the radar
operations feeding the captured data from outside into the device without involving the RF subsystem.
Please refer to the Device TRM (Technical Reference Manual) for MSS R5F and DSP C66x memory map.
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DSP SS
Main SS
Uart#2
L2
384 KB
L3 Memory
Bank
UART
Cache/RAM
I2C
L1P
32 KB
2/2.5 MB
MPU
CAN FD #2
C66x
JTAG
L1D
32 KB
DSPSS L2
Interconnect
SPI #2
RS232
EPWM #3
Development Interfaces
CPSW
DSPSS L1 Interconnect (ECC)
MCU Interfaces
EDMA
TC
DSPSS L2 Interconnect
EDMA
#3
CRC
TC
HWA 2.0
(CPUSS, FFT,
CFAR, Histogram etc)
(TPCC #2)
#6
(TPCC #3)
QSPI
HSM
MCU Cortex 32 KB
R5F
Cache
FUSA
CRYPTO
ACCELERATORS
MSS R5F TCM (128 KB)
MSS R5F L2 (960 KB)
BSS
EDMA
TC
#1
Mailbox
Interrupts/
SW Triggers
(Complete SS including ARM
CR4F (Lockstep), DFE,
RF/Analog Control,
(TPCC #1)
Monitoring, Calibration)
ESM Signals
RSS L1 Interconnect (ECC)
Reset
Watch
Dog
VIM
#2
Clocks
RCSS L2 Interconnect
LBIST,
PBIST
RTI
#3
Interrupts/
SW Triggers
DCC
GPIO/
MUX
#4
2L
CSI2
FUSE
ROM
ESM
CRC
RSS Radar Subsystem
DBG/
TRACE
GPADC
FUSA
DPLL
CNTRL
RF/ANALOG
FRONT END
77 GHz
WAKEUP SS
Figure 9-5. Processor Subsystem
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9.3.3 Automotive Interfaces
The device communicates with the automotive network over the following main interfaces:
•
•
CAN-FD
Ethernet
9.4 Other Subsystems
9.4.1 Hardware Accelerator Subsystem
In addition to the DSP core, the device incorporates Radar Hardware Accelerators (HWA2.0) to offload the DSP
from pre-processing computations.
To understand the capabilities offered by the Radar Hardware Accelerator 2.0 so as to achieve the desired
functionality, please refer to Radar Hardware Accelerator User's Guide.
9.4.2 Security - Hardware Security Module
A Hardware Security Module (HSM), which performs a secure zone operation is provisioned in the device
(operational only in select part variants). A programmable core, ARM Cortex M4 core is deployed to realize the
crypto-agility requirements.
The cryptographic algorithms can be accelerated using the Hardware modules provisioned within the HSM. They
include acceleration of AES, SHA, Public Key Accelerator (PKA) to perform big math operation for Asymmetric
key crypto requirements and True Random Number Generation.
The Main subsystem (MSS) Cortex R5F interfaces with the HSM subsystem to perform the crypto operations
required for the secure boot and secure runtime communications.
Further details on Security can be found in the concerned collaterals. Please reach out to your local TI sales
representative for more information.
9.4.3 ADC Channels (Service) for User Application
The device includes provision for an ADC service for user application, where the GPADC engine present inside
the device can be used to measure up to nine external and internal voltages. The ADC1, ADC2, ADC3, ADC4,
ADC5, ADC6, ADC7, ADC8 and ADC9 pins are used for this purpose.
Note
GPADC structures are also used for measuring the output of internal temperature sensors.
GPADC Specifications:
•
•
•
625 Ksps SAR ADC
0 to 1.8V input range
10-bit resolution
Table 9-1. GP-ADC Parameter
PARAMETER
TYP
1.8
UNIT
V
ADC supply
ADC unbuffered input voltage range
ADC buffered input voltage range(1)
ADC resolution
0 – 1.8
0.4 – 1.3
10
V
V
bits
LSB
LSB
LSB
LSB
Ksps
ns
ADC offset error
±5
ADC gain error
±5
ADC DNL
–1/+2.5
±2.5
625
ADC INL
ADC sample rate
ADC sampling time
400
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Table 9-1. GP-ADC Parameter (continued)
PARAMETER
TYP
UNIT
pF
ADC internal cap
10
2
ADC buffer input capacitance
ADC input leakage current
pF
3
uA
(1) Outside of given range, the buffer output will become nonlinear.
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10 Monitoring and Diagnostics
10.1 Monitoring and Diagnostic Mechanisms
Table 10-1 is a list of the main monitoring and diagnostic mechanisms available in the device.
Table 10-1. Monitoring and Diagnostic Mechanisms for AWR294x
NO
FEATURE
DESCRIPTION
MAIN SUB-SYSTEM
1
2
Lockstep operation of MSS R5F
Core
Device architecture supports lockstep operation of the MSS R5F core that is the operating
core in the Main subsystem that is provisioned as the safety island in the device.
Boot time LBIST For MSS R5F
Core and associated VIM
Device architecture supports hardware logic BIST (LBIST) engine self-test Controller
(STC). This logic is used to provide a very high diagnostic coverage (>90%) on the MSS
R5F CPU core and Vectored Interrupt Module (VIM) at a transistor level.
LBIST for the CPU and VIM need to be triggered by application code before starting
the functional safety application. A reset of the CPU is initiated at the end of the STC
operation and the reset cause register would capture the status of reset. The STC
registers may then be read out to identify the status of the STC execution to determine if
there were any errors. CPU stays there in while loop and does not proceed further if a fault
is identified.
There can be a fault injection test also performed which would also lead to a reset of the
CPU with the error status signaled in the STC registers.
3
Boot time PBIST for MSS R5F
Memories
MSS R5F has Tightly coupled Memories (TCM) Level 1 (L1) memories TCMA, TCMB0
and TCMB1 as well as the Level 2 (L2) Memories. Device architecture supports a
hardware programmable memory BIST (PBIST) engine. This logic is used to provide a
very high diagnostic coverage (March-13n) on the implemented MSS R5F TCMs at a
transistor level.
PBIST for L1 and L2 memories is triggered by Bootloader at the boot time before starting
download of application from Flash or peripheral interface. CPU stays there in while loop
and does not proceed further if a fault is identified.
4
End to End ECC for MSS R5F
Memories
TCMs and L2 Memory diagnostic is supported by Single error correction double error
detection (SECDED) ECC diagnostic. For L2 Memory, an 8-bit code word is used to store
the ECC data as calculated over the 64-bit data bus, whereas for TCMs, a 7-bit code word
is used to store the ECC data for a 32-bit data bus. ECC evaluation for TCMs is done by
the ECC control logic inside the CPU. This scheme provides end-to-end diagnostics on
the transmissions between CPU and TCM. CPU can be configured to have predetermined
response (Ignore or Abort generation) to single and double bit error conditions.
5
MSS R5F bit multiplexing
Logical TCM and L2 Memory word and its associated ECC code is split and stored in
two physical SRAM banks. This scheme provides an inherent diagnostic mechanism for
address decode failures in the physical SRAM banks. Faults in the bank addressing are
detected by the CPU as an ECC fault.
Further, bit multiplexing scheme implemented such that the bits accessed to generate
a logical (CPU) word are not physically adjacent. This scheme helps to reduce the
probability of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest
as multiple single bit faults. As the SECDED TCM ECC can correct a single bit fault in a
logical word, this scheme improves the usefulness of the TCM ECC diagnostic.
Both these features are hardware features and cannot be enabled or disabled by
application software.
6
Clock Monitor
Device architecture supports Four Digital Clock Comparators (EDCCs) and an internal
RCOSC. Dual functionality is provided by these modules – Clock detection and Clock
Monitoring.
EDCCA is dedicated for ADPLL/APLL lock detection monitoring, comparing the ADPLL/
APLL output divided version with the Reference input clock of the device. Failure detection
for EDCCA could be programmed to cause the device to go into limp mode.
Additionally, there is a provision to feed an external reference clock to monitor the internal
clock using the EDCCA.
EDCCB, EDCCC, EDCCD module is one which is available for user software. From the
list of clock options given in detailed spec, any two clocks can be compared. One example
usage is to compare the CPU clock with the Reference or internal RCOSC clock source.
Failure detection is indicated to the MSS R5F CPU via Error Signaling Module (ESM).
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Table 10-1. Monitoring and Diagnostic Mechanisms for AWR294x (continued)
NO
FEATURE
DESCRIPTION
7
RTI/WDT for MSS R5F
Device architecture supports the use of an internal watchdog that is implemented in the
real-time interrupt (RTI) module. The internal watchdog has two modes of operation: digital
watchdog (DWD) and digital windowed watchdog (DWWD). The modes of operation are
mutually exclusive; the designer can elect to use one mode or the other but not both at the
same time.
Watchdog can issue either an internal (warm) system reset or a CPU non-mask able
interrupt upon detection of a failure.
The Watchdog is enabled by the bootloader in DWD mode at boot time to track the boot
process. Once the application code takes up the control, Watchdog can be configured
again for mode and timings based on specific customer requirements.
8
9
MPU for MSS R5F
Cortex-R5F CPU includes an MPU. The MPU logic can be used to provide spatial
separation of software tasks in the device memory. Cortex-R4F MPU supports 16 regions.
It is expected that the operating system controls the MPU and changes the MPU settings
based on the needs of each task. A violation of a configured memory protection policy
results in a CPU abort.
PBIST for Peripheral interface
SRAMs - SPIs,CANs, Ethernet,
EDMA, Mailbox
Device architecture supports a hardware programmable memory BIST (PBIST) engine for
Peripheral SRAMs as well.
PBIST for peripheral SRAM memories can be triggered by the application. User can
elect to run the PBIST on one SRAM or on groups of SRAMs based on the execution
time, which can be allocated to the PBIST diagnostic. The PBIST tests are destructive to
memory contents, and as such are typically run only at boot time. However, the user has
the freedom to initiate the tests at any time if peripheral communication can be hindered.
Any fault detected by the PBIST results in an error indicated in PBIST status registers.
10
11
ECC for Peripheral interface
SRAMs – SPIs, CANs, Ethernet,
EDMA, Mailbox
Peripheral interface SRAMs diagnostic is supported by Single error correction double error
detection (SECDED) ECC diagnostic. When a single or double bit error is detected, the
MSS R5F is notified via ESM (Error Signaling Module). This feature is disabled after reset.
Software must configure and enable this feature in the peripheral and ESM module. ECC
failure (both single bit corrected and double bit uncorrectable error conditions) is reported
to the MSS R5F as an interrupt via ESM module.
Configuration registers protection
for Main SS peripherals
All the Main SS peripherals (SPIs, CANs, Ethernet, I2C, DMAs, RTI/WD, DCCs, EDMA,
IOMUX etc.) are connected to interconnect via Peripheral Central resource (PCR). This
provides two diagnostic mechanisms that can limit access to peripherals. Peripherals can
be clock gated per peripheral chip select in the PCR. This can be utilized to disable
unused features such that they cannot interfere. In addition, each peripheral chip select
can be programmed to limit access based on privilege level of transaction. This feature
can be used to limit access to entire peripherals to privileged operating system code only.
These diagnostic mechanisms are disabled after reset. Software must configure and
enable these mechanisms. Protection violation also generates an ‘aerror’ that result in
abort to MSS R5F or error response to other hosts such as DMAs.
12
Cyclic Redundancy Check–Main
SS
Device architecture supports hardware CRC engine on Main SS implementing the below
polynomials.
•
•
•
•
•
•
•
CRC16 CCITT – 0x10
CRC32 Ethernet – 0x04C11DB7
CRC64
CRC 32C – CASTAGNOLI – 0x1EDC6F4
CRC32P4 – E2E Profile4 – 0xF4ACFB1
CRC-8 – H2F Autosar – 0x2F
CRC-8 – VDA CAN – 0x1D
The read operation of the SRAM contents to the CRC can be done by CPU or by DMA.
The comparison of results, indication of fault, and fault response are the responsibility of
the software managing the test.
13
14
MPU
Device architecture supports MPUs on certain slave ports in the Main SS that include L2
Memory, PCR peripheral access, QSPI access, R5F AXI-Slave access. This would allow
configuring access permissions to these key regions in the Main SS.
By default, this control would reside with the HSM.
MPU for DMAs
Device architecture supports MPUs on Main SS EDMAs. EDMAs also includes MPUs on
both read and writes host ports. EDMA MPUs supports 8 regions. Failure detection by
MPU is reported to the core as an interrupt via local ESM.
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Table 10-1. Monitoring and Diagnostic Mechanisms for AWR294x (continued)
NO
FEATURE
DESCRIPTION
15
16
Interconnect ECC
Device architecture supports hardware based ECC protection mechanisms for transfers
over the system interconnect. Since code execution includes instruction fetches from
memories hosted on the interconnect, the transfers over the interconnect are ensured
to be safe by a combination of ECC and redundancy based mechanisms. Any failures
detected in the transfers are reported over the ESM interface. This mechanism is enabled
by default in HW.
Error Signaling Error Output
When a diagnostic detects a fault, the error must be indicated. The Device architecture
provides aggregation of fault indication from internal monitoring/diagnostic mechanisms
using a peripheral logic known as the Error Signaling Module (ESM). The ESM provides
mechanisms to classify errors by severity and to provide programmable error response.
ESM module is configured by customer application code and specific error signals can be
enabled or masked to generate an interrupt (Low/High priority) for the MSS R5F CPU.
Device supports Nerror output signal (IO) which can be monitored externally to identify any
kind of high severity faults in the design which could not be handled by the R5F.
17
18
Temperature Sensor
Voltage Monitors
Device architecture supports various temperature sensors at temperature hotspots in
digital across the device that can be monitored by the application using an internal GPADC
channel.
Device architecture supports monitoring the supply rails connected to the chip, in
conjunction with external voltage monitors.
HSM SUB-SYSTEM
1
2
Boot time LBIST For HSM M4 Core Device architecture supports hardware logic BIST (LBIST) even for HSM Cortex M4 core.
This logic provides very high diagnostic coverage (>90%) on the BIST R4F CPU core and
VIM.
This needs to be triggered by HSM Runtime Firmware before starting the security and
functional safety application.
Boot time PBIST for HSM
Memories (SRAM, Secure RAM,
Mailbox)
Device architecture supports a hardware programmable memory BIST (PBIST) engine for
HSM Memories which provide a very high diagnostic coverage (March-13n).
PBIST for HSM memories is triggered by Bootloader at the boot time before starting
download of application from Flash or peripheral interface. CPU stays there in while loop
and does not proceed further if a fault is identified.
3
4
5
End to End ECC for HSM Memories HSM memories diagnostic is supported by Single error correction double error detection
(SECDED) ECC diagnostic. Single bit error is communicated to the HSM CM4 while
double bit error is communicated to MSS R5F as an interrupt so that application code
becomes aware of this and takes appropriate action.
HSM Memory bit multiplexing
Logical memory word and its associated ECC code is split and stored in two physical
SRAM banks. This scheme provides an inherent diagnostic mechanism for address
decode failures in the physical SRAM banks and helps to reduce the probability of physical
multi-bit faults resulting in logical multi-bit faults.
Clock Monitor
Device architecture supports One Digital Clock Comparators (DCC) and an internal 32
KHz RCOSC. Dual functionality is provided by these modules – Clock detection and Clock
Monitoring.
From the list of clock options given in detailed spec, any two clocks can be compared. One
example usage is to compare the CPU clock with the Reference or internal RCOSC clock
source. Failure detection is indicated to the HSM M4 CPU via Error Signaling Module
(ESM).
6
7
RTI/WDT for HSM CM4
MPU/Firewall
Device architecture supports an internal watchdog for HSM M4. Timeout condition is
reported via an interrupt to MSS R5F and rest is left to application code to take the device
to a safe state.
Device architecture supports Firewalls/MPUs on the HSM and crypto engine access both
for safety and security reasons. This would allow configuring access permissions to these
key regions in the HSM.
By default, this control would reside with the HSM.
DSP SUB-SYSTEM
1
Boot time LBIST for DSP core
Device supports boot time LBIST for the DSP Core. LBIST can be triggered by the
MSS R5F secondary bootloader/application code before starting the functional safety
application.
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Table 10-1. Monitoring and Diagnostic Mechanisms for AWR294x (continued)
NO
FEATURE
DESCRIPTION
2
Boot time PBIST for L1P, L1D, L2
Device architecture supports a hardware programmable memory BIST (PBIST) engine for
and L3 Memories, HWA memories, DSPSS and RSS memories which provide a very high diagnostic coverage (March-13n).
RSS Memories (ADCBUF, CQ
Memory), Mailbox
PBIST is triggered by MSS R5F secondary bootloader/application code before starting the
functional safety application.
3
4
Parity on L1P, ECC on L1D
ECC on DSP’s L2 Memory
Device architecture supports Parity diagnostic on DSP’s L1P memory. Parity error is
reported to the CPU as an interrupt.
L1D memory is covered by SECDED ECC.
Device architecture supports both Parity Single error correction double error detection
(SECDED) ECC diagnostic on DSP’s L1D and L2 memory. L2 Memory is a unified 384KB
of memory used to store program and Data sections for the DSP. A 12-bit code word is
used to store the ECC data as calculated over the 256-bit data bus (logical instruction
fetch size). The ECC logic for the L2 access is located in the DSP and evaluation is done
by the ECC control logic inside the DSP. This scheme provides end-to-end diagnostics on
the transmissions between DSP and L2. Byte aligned Parity mechanism is also available
on L2 to take care of data section.
5
6
ECC on Radar Data Cube (L3)
Memory, HWA Memories, RSS
Memory (ADCBUF), Mailbox
L3 memory is used as Radar data section in the device. The architecture supports Single
error correction double error detection (SECDED) ECC diagnostic on L3 memory. A 12-bit
code word is used to store the ECC data as calculated over the 256-bit data bus.
The RSS memory (ADCBUF) too supports the SECDED ECC diagnostics.
Failure detection by ECC logic is reported to the DSP core as an interrupt via ESM.
RTI/WDT for DSP Core
Device architecture supports the use of an internal watchdog for BIST R4F that is
implemented in the real-time interrupt (RTI) module – replication of same module as used
in Main SS. This module supports same features as that of RTI/WD for MSS/BIST R4F.
This watchdog is enabled by customer application code and Timeout condition is reported
via an interrupt to MSS R5F and rest is left to application code in MSS R5F to take the
device to a safe state.
7
CRC for DSP Sub-System
Device architecture supports hardware CRC engine on DSPSS implementing the below
polynomials.
•
•
•
•
•
•
•
CRC16 CCITT – 0x10
CRC32 Ethernet – 0x04C11DB7
CRC64
CRC 32C – CASTAGNOLI – 0x1EDC6F4
CRC32P4 – E2E Profile4 – 0xF4ACFB1
CRC-8 – H2F Autosar – 0x2F
CRC-8 – VDA CAN – 0x1D
The read operation of the SRAM contents to the CRC can be done by CPU or by DMA.
The comparison of results, indication of fault, and fault response are the responsibility of
the software managing the test.
8
MPU for DSP
Device architecture supports MPUs for DSP memory accesses (L1D, L1P, and L2). L2
memory supports 64 regions and 16 regions for L1P and L1D each. Failure detection by
MPU is reported to the DSP core as an abort.
BIST (Within RADAR SUB-SYSTEM)
1
2
Lockstep operation of BIST R4F
Core
Device architecture supports lockstep operation of the BIST R4F core.
Boot time LBIST For BIST R4F
Core and associated VIM
Device architecture supports hardware logic BIST (LBIST) even for BIST R4F core and
associated VIM module. This logic provides very high diagnostic coverage (>90%) on the
BIST R4F CPU core and VIM.
This needs to be triggered by MSS R5F secondary bootloader/application code before
starting the functional safety application.
3
Boot time PBIST for BIST R4F TCM Device architecture supports a hardware programmable memory BIST (PBIST) engine for
Memories, Mailbox
BIST R4F TCMs, Mailbox which provide a very high diagnostic coverage (March-13n) on
the BIST R4F TCMs.
PBIST is triggered by MSS R5F secondary bootloader/application code before starting the
functional safety application.
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Table 10-1. Monitoring and Diagnostic Mechanisms for AWR294x (continued)
NO
FEATURE
DESCRIPTION
4
5
6
End to End ECC for BIST R4F TCM BIST R4F TCMs, Mailbox diagnostic is supported by Single error correction double
Memories, Mailbox
error detection (SECDED) ECC diagnostic. Single bit error is communicated to the BIST
R4FCPU while double bit error is communicated to MSS R5F as an interrupt so that
application code becomes aware of this and takes appropriate action.
BIST R4F TCM bit multiplexing
Logical TCM word and its associated ECC code is split and stored in two physical SRAM
banks. This scheme provides an inherent diagnostic mechanism for address decode
failures in the physical SRAM banks and helps to reduce the probability of physical multi-
bit faults resulting in logical multi-bit faults.
Temperature Sensors
Tx Power Monitors
Device architecture supports various temperature sensors all across the device (next
to power hungry modules such as PAs, etc) which is monitored during the inter-frame
period(1)
.
7
8
Device architecture supports power detectors at the Tx output(2)
.
Synthesizer (Chirp) frequency
monitor
Monitors Synthesizer’s frequency ramp by counting (divided-down) clock cycles and
comparing to ideal frequency ramp. Excess frequency errors above a certain threshold,
if any, are detected and reported.
9
Ball break detection for TX ports
(TX Ball break monitor)
Device architecture supports a ball break detection mechanism based on Impedance
measurement at the TX output(s) to detect and report any large deviations that can
indicate a ball break.
Monitoring is done by TIs code running on BIST R4F and failure is reported to the MSS
R5F via Mailbox.
It is completely up to customer SW to decide on the appropriate action based on the
message from BIST R4F
10
11
12
RX loopback test
IF loopback test
Built-in TX to RX loopback to enable detection of failures in the RX path(s), including Gain,
inter-RX balance, etc. This monitor also covers ball breaks on the RX pins.
Built-in IF (square wave) test tone input to monitor IF filter’s frequency response and
detect failure.
RX saturation detect
Provision to detect ADC saturation due to excessive incoming signal level and/or
interference.
(1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the
temperature sensed via API by customer application.
a. Report the temperature sensed after every N frames
b. Report the condition once the temperature crosses programmed threshold.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.
(2) Monitoring is done by the TI's code running on BIST R4F.
There are two modes in which it could be configured to report the detected output power via API by customer application.
a. Report the power detected after every N frames
b. Report the condition once the output power degrades by more than configured threshold from the configured.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.
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11 Applications, Implementation, and Layout
Note
Information in the following Applications section is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI's customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
11.1 Application Information
Key device features driving the following applications are:
•
•
•
•
Integration of Radar Front End and Programmable MCU
Flexible boot modes: Autonomous application boot using a serial flash or external boot over SPI
Hardware Security Module
High speed 100Mbps Fast Ethernet Support
11.2 Short and Medium Range Radar
40-MHz
Crystal
Serial
Flash
Power Management
QSPI
Integrated MCU
ARM Cortex-R5F
Ethernet
PHY
Automotive
Network
Ethernet
Antenna
RX1
Structure
RX2
RX3
MCAN
PHY
Automotive
Network
CAN FD (2)
RX4
Radar
Front End
TX1
TX2
TX3
TX4
Integrated DSP
TI C66x
mmWave Sensor
Figure 11-1. Short- and Medium-Range Radar
11.3 Reference Schematic
The reference schematic and power supply information can be found in the AWR2944 EVM Documentation.
Listed for convenience are: Design Files, Schematics, Layouts, and Stack up details for PCB at the AWR2944
EVM Product page.
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Device Support
13 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, XA2943BGALT). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, your package), the temperature range (for example, blank is the default commercial temperature
range), and the device speed range, in megahertz (for example, your device speed range). Figure x provides a
legend for reading the complete device name for any your device device.
For orderable part numbers of your device devices in the your package package types, see the Package Option
Addendum of this document, ti.com, or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the AWR2944 Errata
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2
9
44
B
XA
G
ALT
Q1
Qualification
Prefix
Q1 = AEC-Q100
Blank = no special Qual
XA = Pre-production Automotive
AWR = Production Automotive
Tray or Tape & Reel
Generation
T = Small Reel
R = Big Reel
1, 2 = 76 - 81 GHz
Blank = Tray
Variant
Package
ALT = BGA
Security
2 = FE
4 = FE + FFT + MCU
6 = FE + MCU + DSP
8 = FE + FFT + MCU + DSP
9 = FE + FFT + MCU + DSP
G = General
S = Secure
D = Development Secure
Num RX/TX Channels
Safety
RX = 1,2,3,4
TX = 1,2,3,4
Q = Quality Manage
A = ASIL A Targeted
B = ASIL B Targeted
Silicon PG Revision
Blank = Rev 1.0
A = Rev 2.0 / Rev 3.0
Features
Blank = Baseline
N = Narrow Band (76-77 GHz)
Figure 13-1. Device Nomenclature
13.1 Tools and Software
The contents in this section will be updated in subsequent versions.
13.2 Documentation support
The contents in this section will be updated in subsequent versions.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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PACKAGE OUTLINE
ALT0266A
FCBGA - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
BALL GRID ARRAY
12.1
11.9
B
A
BALL A1
CORNER
12.1
11.9
0.15 C
0.2 C
1.2 MAX
C
SEATING PLANE
0.1 C
0.462
0.216
11.05 TYP
SYMM
(0.475)
(0.475)
V
U
T
R
P
N
M
L
SYMM
K
11.05 TYP
J
H
G
F
E
D
C
0.46
266X
0.36
0.15
0.08
C A B
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
0.65 TYP
0.65 TYP
4226546/A 02/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ALT0266A
FCBGA - 1.2 mm max height
BALL GRID ARRAY
(0.65) TYP
266X ( 0.35)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
A
B
C
D
E
F
(0.65) TYP
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED METAL
(
0.35)
(
0.35)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
METAL EDGE
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4226546/A 02/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ALT0266A
FCBGA - 1.2 mm max height
BALL GRID ARRAY
(0.65) TYP
266X ( 0.35)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
A
B
C
D
E
F
(0.65) TYP
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
4226546/A 02/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
13-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
XA2943BGALT
XA2944BGALT
ACTIVE
ACTIVE
FCCSP
FCCSP
ALT
ALT
266
266
1
1
TBD
TBD
Call TI
Call TI
Call TI
-40 to 140
-40 to 140
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Nov-2021
Addendum-Page 2
PACKAGE OUTLINE
ALT0266A
FCBGA - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
BALL GRID ARRAY
12.1
11.9
B
A
BALL A1
CORNER
12.1
11.9
0.15 C
0.2 C
1.2 MAX
C
SEATING PLANE
0.1 C
0.462
0.216
11.05 TYP
SYMM
(0.475)
(0.475)
V
U
T
R
P
N
M
L
SYMM
K
11.05 TYP
J
H
G
F
E
D
C
0.46
266X
0.36
0.15
0.08
C A B
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
0.65 TYP
0.65 TYP
4226546/A 02/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ALT0266A
FCBGA - 1.2 mm max height
BALL GRID ARRAY
(0.65) TYP
266X ( 0.35)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
A
B
C
D
E
F
(0.65) TYP
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED METAL
(
0.35)
(
0.35)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
METAL EDGE
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4226546/A 02/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ALT0266A
FCBGA - 1.2 mm max height
BALL GRID ARRAY
(0.65) TYP
266X ( 0.35)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
A
B
C
D
E
F
(0.65) TYP
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
4226546/A 02/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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