XDLP462SAFQXQ1_技术文档

DLP4620S-Q1

ZHCSRC7A –DECEMBER 2022 –REVISED FEBRUARY 2023

DLP4620S-Q1 适用于汽车显示应用的DLP 数字微镜器件(DMD)

1 特性

3 说明

• 符合汽车应用要求

DLP^®DLP4620S-Q1 汽车数字微镜器件 (DMD) 与

DLPC230S-Q1 DMD 控制器和 TPS99000S-Q1 系统

管理和照明控制器结合使用，能够实现具有高性能、高

分辨率的增强现实抬头显示 (HUD)。采用 2:1 宽高

比，支持超宽宽高比设计；具有 90 万像素分辨率，可

在 HUD 应用实现视网膜级受限显示。DLP4620S-Q1

在光通量和分辨率之间实现了良好的平衡，能够获得宽

视野和较大的驾驶员眼动范围，增强用户体验。该芯片

组耦合了 LED 或激光和光学系统，能够获得更饱满的

125% NTSC 色彩、超过 15,000cd/m2 的超高亮度、

超过 5000:1 的高动态调光比以及太阳能高负载容差。

DLP4620S-Q1 汽车 DMD 微镜阵列针对底部照明而配

置，可实现高效及更紧凑的光学引擎设计，以支持左舵

和右舵驾驶员配置。DLP4620S-Q1 器件采用面板封

装，可优化系统成本。该封装针对 DMD 阵列而言具有

低热阻的特点，可实现高效的散热解决方案。

– DMD 阵列工作温度范围-40°C 至105°C

• 功能安全质量管理型

– 有助于使ISO 2626 功能安全系统设计满足

ASIL-B 要求的文档

• DLP4620S-Q1 汽车芯片组包括：

– DLP4620S-Q1 DMD

– DLPC230S-Q1 DMD 控制器

– TPS99000S-Q1 系统管理和照明控制器

• 0.46 英寸对角线微镜阵列

– 7.6 μm 微镜间距

– ±12° 微镜倾斜角（相对于平面）

– Bottom 照明可实现高效率和更小的发动机尺寸

– 高达1920 × 960 分辨率，外部基于GPU 的梅

花形预处理

– 1358 × 566 或1220 × 610 分辨率模式

– 与LED 或激光照明兼容

器件信息

封装⁽¹⁾

• 600MHz subLVDS DMD 接口，可实现低功耗和低

排放

封装尺寸（标称值）

器件型号

DLP4620S-Q1

FQX

25.2 mm × 11.0 mm

• 温度极值下DMD 刷新率为10 kHz

• DMD 存储器单元的内置自检(BIST)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 宽视场和增强现实抬头显示(HUD)

• 数字仪表组、导航和信息娱乐系统挡风玻璃显示

Voltage

Monitor and

Enables

Power

1.1 V

Regulation

1.8 V

3.3 V

6.5 V

TPS99000S-Q1

V_OFFSET

V_BIAS

SPI

V_RESET

Video

DLPC230S-Q1

SubLVDS

DLP4620S-Q1 DMD

TMP411

Temperature

Sensor

I²C

LED

ENABLE

Flash

SPI

DLP4620S-Q1 DLP^®芯片组系统方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS230

DLP4620S-Q1

ZHCSRC7A –DECEMBER 2022 –REVISED FEBRUARY 2023

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Table of Contents

7.4 System Optical Considerations.................................21

7.5 DMD Image Performance Specification....................22

7.6 Micromirror Array Temperature Calculation.............. 23

7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 25

8 Application and Implementation..................................26

8.1 Application Information............................................. 26

8.2 Typical Application.................................................... 26

9 Power Supply Recommendations................................29

9.1 Power Supply Power-Up Procedure......................... 29

9.2 Power Supply Power-Down Procedure.....................29

9.3 Power Supply Sequencing Requirements................ 30

10 Layout...........................................................................31

10.1 Layout Guidelines................................................... 31

11 Device and Documentation Support..........................32

11.1 第三方产品免责声明................................................32

11.2 Device Support........................................................32

11.3 Trademarks............................................................. 32

11.4 静电放电警告...........................................................32

11.5 DMD Handling.........................................................33

11.6 术语表..................................................................... 33

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 8

6.1 Absolute Maximum Ratings........................................ 8

6.2 Storage Conditions..................................................... 8

6.3 ESD Ratings .............................................................. 9

6.4 Recommended Operating Conditions.........................9

6.5 Thermal Information .................................................10

6.6 Electrical Characteristics...........................................10

6.7 Timing Requirements................................................ 11

6.8 Switching Characteristics .........................................14

6.9 System Mounting Interface Loads............................ 15

6.10 Physical Characteristics of the Micromirror Array ..15

6.11 Micromirror Array Optical Characteristics .............. 17

6.12 Window Characteristics.......................................... 17

6.13 Chipset Component Usage Specification............... 17

7 Detailed Description......................................................18

7.1 Overview...................................................................18

7.2 Functional Block Diagram.........................................19

7.3 Feature Description...................................................20

Information.................................................................... 33

4 Revision History

Changes from Revision * (December 2022) to Revision A (February 2023)

Page

• 更新了该数据表标题........................................................................................................................................... 1

2

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5 Pin Configuration and Functions

1

3

5

17 19 21 23

16 18 20 22 24

2

4

6

A

B

C

D

E

F

G

H

J

K

图5-1. FQX Package 120-Pin LGA Bottom View

表5-1. Pin Functions—Connector Pins

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

NO.

DATA INPUTS

D_AN(0)

A3

B1

C2

F2

H2

K1

K4

I

SubLVDS

Double

Data, Negative

D_AN(1)

D_AN(2)

D_AN(3)

D_AN(4)

D_AN(5)

D_AN(6)

D_AN(7)

D_AP(0)

D_AP(1)

D_AP(2)

D_AP(3)

D_AP(4)

D_AP(5)

D_AP(6)

D_AP(7)

D_BN(0)

D_BN(1)

D_BN(2)

D_BN(3)

D_BN(4)

I

Double

K6

A2

C1

SubLVDS

Data, Negative

Data, Positive

D2

E2

SubLVDS

Data, Positive

Data, Negative

G2

K2

K3

K5

A22

B24

D23

F23

H23

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表5-1. Pin Functions—Connector Pins (continued)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

NO.

D_BN(5)

K24

I

SubLVDS

Double

Single

Data, Negative

Data, Positive

Clock, Negative

Clock, Positive

Clock, Negative

Clock, Positive

D_BN(6)

K21

K19

A23

C24

C23

E23

G23

K23

K22

K20

J1

D_BN(7)

D_BP(0)

D_BP(1)

D_BP(2)

D_BP(3)

D_BP(4)

D_BP(5)

D_BP(6)

D_BP(7)

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

LS_CLKN

LS_CLKP

LS_WDATAN

LS_WDATAP

H1

J24

H24

C3

Clock for Low Speed Interface, Negative

Clock for Low Speed Interface, Positive

Write Data for Low Speed Interface, Negative

Write Data for Low Speed Interface, Positive

C4

Single

C5

Single

C6

Single

CONTROL INPUTS

Asynchronous Reset Active Low. Logic High

Enables DMD

DMD_DEN_ARSTZ

E6

I

LPSDR

LS_RDATA_A

LS_RDATA_B

E19

F19

O

LPSDR

Single

Read Data for Low Speed Interface

TEMPERATURE SENSE DIODE

TEMP_N

TEMP_P

F6

O

I

Calibrated temperature diode used to assist

accurate temperature measurements of DMD die

G6

4

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表5-1. Pin Functions—Connector Pins (continued)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

POWER

VBIAS

NO.

A4

A21

B3

Power

Supply voltage for positive bias level at

micromirrors

VBIAS

VOFFSET

VRESET

B4

B21

B22

J4

Supply voltage for high-voltage CMOS core logic.

Supply voltage for offset level at micromirrors

J21

B6

Supply voltage for negative reset level at

micromirrors

B19

VDD

A5

Power

A20

C20

VDD

VDDI

D4

D19

D21

E3

Power

Supply voltage for Low Voltage CMOS core logic;

for LPSDR inputs; for normal high level at

micromirror address electrodes

E22

F4

G3

G21

H22

J3

J6

J19

E5

E20

F5

F20

G5

Supply voltage for SubLVDS receivers

G20

H5

H20

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表5-1. Pin Functions—Connector Pins (continued)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

NO.

VSS

A1

Ground

VSS

A6

A19

A24

B2

Ground

VSS

B5

Ground

VSS

B20

B23

C19

C21

C22

D3

Ground

D5

VSS

D6

D20

D22

E4

Ground

E21

F3

Common return. Ground for all power

F21

F22

G4

G19

G22

H3

H4

H6

H19

H21

J2

J5

J20

J22

J23

6

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表5-2. Pin Functions—Test Pads

NUMBER

TP0

SYSTEM BOARD

Do not connect.

TP1

TP2

MBRST(0)

Do not connect.

MBRST(1)

MBRST(6)

MBRST(7)

Do not connect.

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6 Specifications

6.1 Absolute Maximum Ratings

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not

imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating

Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not

be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

MIN

MAX

UNIT

SUPPLY VOLTAGE

Supply voltage for LVCMOS core logic⁽¹⁾

Supply voltage for LPSDR low speed interface

V_DD

2.3

V

–0.5

V_DDI

Supply voltage for subLVDS receivers⁽¹⁾

Supply voltage for HVCMOS and micromirror

electrode^{(1) (2)}

V_OFFSET

8.75

V_BIAS

Supply voltage for micromirror electrode⁽¹⁾

Supply voltage delta (absolute value)⁽³⁾

Supply voltage delta (absolute value)⁽⁴⁾

Supply voltage delta (absolute value)⁽⁵⁾

17

0.5

V

–0.5

–11

V_RESET

|V_DDI- V_DD

|V_BIAS-V_OFFSET

|V_BIAS- V_RESET

INPUT VOLTAGE

|

0.3

|

8.75

28

|

Input voltage for LVCMOS inputs⁽¹⁾

Input voltage for other inputs subLVDS^{(1) (6)}

INPUT PINS

V_DD+ 0.5

V_DDI+ 0.5

V

–0.5

|V_ID|

SubLVDS input differential voltage (absolute value)⁽⁶⁾

810

10

mV

mA

|I_ID|

SubLVDS input differential current

CLOCK FREQUENCY

F_{max_LS}

Clock frequency for low speed interface LS_CLK

Max current source into temperature diode

Operating DMD array temperature

100

130

120

105

MHz

µA

TEMPERATURE DIODE

I_{TEMP_DIODE}

ENVIRONMENTAL

T_ARRAY

°C

–40

(1) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:

VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.

(2) VOFFSET supply transients must fall within specified voltages.

(3) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw and

permanent damage to the device.

(4) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current

draw and permanent damage to the device.

(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw

and permanent damage to the device.

(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. SubLVDS differential

inputs must not exceed the specified limit or damage to the internal termination resistors may result.

6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system.

MIN

MAX

UNIT

T_stg

DMD storage temperature

125

°C

–40

8

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6.3 ESD Ratings

VALUE

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Charged device model (CDM), per AEC Q100-011

±2000

±750

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGE

Supply voltage for LVCMOS core logic

Supply voltage for LPSDR low-speed interface

V_DD

1.65

1.8

1.95

V

V_DDI

Supply voltage for SubLVDS receivers

Supply voltage for HVCMOS and micromirror electrode⁽³⁾

Supply voltage for mirror electrode

1.65

8.25

1.8

8.5

1.95

8.75

16.5

–10.5

0.3

V

V_OFFSET

V_BIAS

15.5

16

V_RESET

Supply voltage for micromirror electrode

Supply voltage delta (absolute value)⁽⁴⁾

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

–9.5

–10

|V_DDI- V_DD

|V_BIAS-V_OFFSET

|V_BIAS- V_RESET

LOW-SPEED LPDSR INTERFACE

|

8.75

28

|

f_{clock_LS}

Clock frequency for low speed interface LS_CLK

108

44

120

56

MHz

%

DCD_IN

LSIF duty cycle distortion (LS_CLK)

SUBLVDS INTERFACE

f_{clock_HS}

DCD_IN

|V_ID|

Clock frequency for high-speed interface DCLK

LVDS duty cycle distortion (DCLK)

LVDS differential input voltage magnitude⁽⁷⁾

Common mode voltage⁽⁷⁾

300

44

540

56

MHz

%

150

700

525

90

250

900

350

mV

V_CM

1100

1275

110

V_SUBLVDS

Z_LINE

SubLVDS voltage⁽⁷⁾

Line differential impedance (PWB/trace)

Internal differential termination resistance⁽⁸⁾

100-Ωdifferential PCD trace

100

Ω

Z_IN

80

120

6.35

152.4

mm

ENVIRONMENTAL

T_ARRAY

Array Temperature^{(9) (11)}

-40

105

2

°C

Illumination

ILL_UV

Illumination, wavelength < 395 nm⁽¹⁰⁾

mW/cm²

Illumination overfill maximum heat load in area shown in

Figure 6-1

ILL_OVERFILL

90 mW/mm²

(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(2) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections

are also required.

(3) VOFFSET supply transients must fall within specified min/max voltages.

(4) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than the specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than the specified limit.

(6) To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than the specified limit.

(7) See Figure 6-6 and Figure 6-7.

(8) See Figure 6-8.

(9) DMD Active Array temperature can be calculated as shown in the Micromirror Array Temperature Calculation.

(10) The maximum operation conditions for operating temperature and UV illumination must not be implemented simultaneously.

(11) The operating profile information for the device micromirror landed duty-cycle and temperature is provided upon request.

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6.4.1 Illumination Overfill Diagram

Limited illumination area on

window aperture

Window

Array

Window

Aperture

Window

0.5 mm

Window Aperture

0.5 mm

图6-1. Illumination Overfill Diagram

6.5 Thermal Information

DLP4620S-Q1

THERMAL METRIC

UNIT

FQX

1.3

Thermal resistance

Active area-to-test point 1 (TP1) ⁽¹⁾

Active area-to-temperature sense diode⁽¹⁾

°C/W

0.1

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the Recommended Operating Conditions . The total heat load on

the DMD is largely driven by the incident light absorbed by the active area, although other contributions include light energy absorbed

by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy

falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the

device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT

I_DD

Supply current: VDD⁽²⁾

Supply current: VDDI⁽²⁾

Supply current: VOFFSET

Supply current: VBIAS

Supply current: VRESET

VDD = 1.95 V

220

55

mA

I_DDI

VDDI = 1.95 V

I_OFFSET

I_BIAS

VOFFSET = 8.75 V

VBIAS = 16.5 V

35

1.5

16

I_RESET

VRESET = –10.5 V

POWER

P_DD

Supply power dissipation: VDD⁽²⁾

Supply power dissipation: VDDI⁽²⁾

Supply power dissipation: VOFFSET

Supply power dissipation: VBIAS

Supply power dissipation: VRESET

Supply power dissipation: total

VDD = 1.95 V

430

108

307

25

mW

P_DDI

VDDI = 1.95 V

P_OFFSET

P_BIAS

VOFFSET = 8.75 V

VBIAS = 16.5 V

VRESET = –10.5 V

P_RESET

P_TOTAL

LVCMOS INPUT

168

1038

10

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6.6 Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.7 ×

V_DD

VDD +

0.3

V_IH

High-level input voltage⁽³⁾

V

0.3 ×

V_DD

V_IL

Low-level input voltage⁽³⁾

AC input high voltage⁽³⁾

AC input low voltage⁽³⁾

Input hysteresis⁽³⁾

V

–0.3

0.8 ×

V_DD

V_DD+

0.3

V_IH(AC)

V_IL(AC)

V_Hyst

0.2 ×

V_DD

–0.3

0.1 ×

V_DD

0.4 ×

V_DD

See Figure 6-9

I_IL

Low-level input current⁽³⁾

High-level input current⁽³⁾

VDD = 1.95 V; V_I= 0 V

nA

–100

I_IH

VDD = 1.95 V; V_I= 1.95 V

135

μA

LVCMOS OUTPUT

0.8 ×

V_DD

V_OH

V_OL

DC output high voltage⁽⁴⁾

V

I_OH= –2 mA

0.2 ×

V_DD

DC output low voltage⁽⁴⁾

I_OL= 2 mA

V

I_OZ

High impedance output current

VDD = 1.95 V

10

µA

CAPACITANCE

Input capacitance LVCMOS

Input capacitance subLVDS

Output capacitance

F = 1 MHz

10

20

10

20

pF

C_IN

C_OUT

C_TEMP

Input capacitance subLVDS

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

(2) Supply power dissipation based on non-compressed commands and data.

(3) LPSDR input specifications are for pin DMD_DEN_ARSTZ.

(4) LPSDR output specification is for pins LS_RDATA_A and LS_RDATA_B.

6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted

MIN NOM MAX UNIT

Low-Speed Interface

t_r

Rise slew rate ^{(1) (2)}

(20% to 80%) × VDD

(80% to 20%) × VDD

0.25

7.7

3.1

1.5

3

V/ns

ns

t_f

Fall slew rate ^{(1) (2)}

t_c

Cycle time LS_CLK

8.3

t_W(H)

t_W(L)

t_su

Pulse duration LS_CLK high⁽³⁾50% to 50% reference points

Pulse duration LS_CLK low⁽³⁾50% to 50% reference points

Setup time⁽³⁾

ns

LS_WDATA valid before LS_CLK↑or LS_CLK↓

t_h

Hold time⁽³⁾

ns

LS_WDATA valid after LS_CLK↑or LS_CLK↓

t_WINDOW

Window time

Setup time + hold time

ns

For each 0.25 V/ns reduction in slew rate below 1

V/ns

t_DERATING

Window time derating

0.35

ns

High-Speed Interface

t_r

Rise slew rate⁽²⁾

20% to 80% reference points

80% to 20% reference points

0.7

1

V/ns

ns

t_f

Fall slew rate⁽²⁾

t_c

Cycle time DCLK ⁽³⁾

Pulse duration DCLK high⁽³⁾

1.79

0.79

1.85

t_W(H)

50% to 50% reference points

ns

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6.7 Timing Requirements (continued)

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted

MIN NOM MAX UNIT

t_W(L)

Pulse duration DCLK low⁽³⁾

Window time^{(3) (4)}

50% to 50% reference points

Setup time + Hold time

0.79

0.3

ns

t_WINDOW

t_{LVDS-EN+REFGEN}

Power-up receiver ⁽⁵⁾

2000

(1) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-2.

(2) See Figure 6-3.

(3) See Figure 6-4.

(4) See Figure 6-5.

(5) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

Electrical and Timing Diagrams

图6-2. LPSDR Input Rise and Fall Slew Rate

图6-3. SubLVDS Input Rise and Fall Slew Rate

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图6-4. SubLVDS Switching Parameters

图6-5. High-Speed Training Scan Window

图6-6. SubLVDS Voltage Parameters

图6-7. SubLVDS Waveform Parameters

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DCLK_AP

DCLK_BP

D_AP(7:0)

D_BP(7:0)

ESD

Internal

Termination

DCLK_AN

DCLK_BN

D_AN(7:0)

D_BN(7:0)

SubLVDS

Receiver

图6-8. SubLVDS Equivalent Input Circuit

图6-9. LPSDR Input Hysteresis

6.8 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ns

Output propagation, clock to Q, rising edge of LS_CLK

(differential clock signal) input to LS_RDATA output⁽²⁾

t_PD

C_L= 45 pF

15

Slew rate, LS_RDATA

0.5

V/ns

Output duty cycle distortion, LS_RDATA_A and LS_RDATA_B

40%

60%

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

(2) See 图6-10 and 图6-11.

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6.8.1 LPSDR and Test Load Circuit Diagrams

图6-10. LPSDR Read Out

图6-11. Test Load Circuit for Output Propagation Measurement

6.9 System Mounting Interface Loads

PARAMETER

Thermal interface area

Electrical interface area

Condition

MIN

NOM

MAX

90

UNIT

Maximum load uniformly distributed within each area⁽¹⁾

N

135

(1) See Figure 6-12.

System Interface Loads Diagram

Thermal Interface Area

Electrical Interface Area

图6-12. System Interface Loads

6.10 Physical Characteristics of the Micromirror Array

PARAMETER

VALUE

UNIT

M

N

Number of active columns⁽¹⁾

960

7.6

micromirrors

µm

Number of active rows⁽¹⁾

Micromirror (pixel) pitch—diagonal⁽¹⁾

Micromirror (pixel) pitch—horizontal and vertical⁽¹⁾

ε

P

10.8

µm

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6.10 Physical Characteristics of the Micromirror Array (continued)

PARAMETER

VALUE

10.373

5.189

10

UNIT

mm

Micromirror active array width

Micromirror active array height

Micromirror active border

(P × M) + (P / 2)

(P x N) / 2 + (P / 2)

mm

Pond of micromirrors (POM) ⁽²⁾

micromirrors/side

(1) See 图6-13.

(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

6.10.1 Array Physical Characteristics Diagram

Off State

Light Path

Row 959

Row 958

Row 957

Row 956

Row 955

Row 954

Row 953

Row 952

Off-State

Tilt Direction

On-State

Tilt Direction

DMD Active Mirror Array

Row 7

Row 6

Row 5

Row 4

Row 3

Row 2

Row 1

Row 0

Array Width

Pond of Micromirrors (POM) are Omitted for Clarity

Details omitted for clarify

Not to Scale

Incoming

Illumination

Light Path

P (um)

图6-13. Micromirror Array Physical Characteristics

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6.11 Micromirror Array Optical Characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

degree

Micromirror tilt angle

DMD landed state⁽¹⁾

12

Micromirror tilt angle tolerance⁽²⁾

DMD efficiency⁽³⁾

1

–1

66%

420 nm –700 nm

(1) Measured relative to the plane formed by the overall micromirror array at 25°C.

(2) For some applications, it is critical to account for the micromirror tilt angle variation in the overall optical system design. With some

optical system designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some optical system designs, the micromirror tilt angle variation between devices may result

in colorimetry variations, system efficiency variations, or system contrast variations.

(3) DMD efficiency is measured photopically under the following conditions: 24° illumination angle, F/2.4 illumination and collection

apertures, uniform source spectrum (halogen), uniform pupil illumination, the optical system is telecentric at the DMD, and the

efficiency numbers are measured with 100% electronic micromirror landed duty-cycle and do not include system optical efficiency or

overfill loss. This number is measured under conditions described above and deviations from these specified conditions could result in

a different efficiency value in a different optical system. The factors that can influence the DMD efficiency related to system application

include: light source spectral distribution and diffraction efficiency at those wavelengths (especially with discrete light sources such as

LEDs or lasers), and illumination and collection apertures (F/#) and diffraction efficiency. The interaction of these system factors as well

as the DMD efficiency factors that are not system dependent are described in detail in DMD Optical Efficiency for Visible Wavelengths

Application Note.

6.12 Window Characteristics

PARAMETER

MIN

NOM

Corning Eagle XG

1.5119

MAX

UNIT

Window material designation

Window refractive index

Window aperture⁽¹⁾

Illumination overfill

At wavelength 546.1 nm

See ⁽¹⁾

.

(1) See the mechanical package ICD for details regarding the size and location of the window aperture.

6.13 Chipset Component Usage Specification

The DLP4620S-Q1 is a component of a chipset. Reliable function and operation of the DLP4620S-Q1 requires

that it be used in conjunction with the TPS99000S-Q1 and DLPC230S-Q1, and includes components that

contain or implement TI DMD control technology. TI DMD control technology consists of the TI technology and

devices used for operating or controlling a DLP DMD.

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

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7 Detailed Description

7.1 Overview

The DLP4620S-Q1 automotive DMD consists of 921600 highly reflective, digitally switchable, micrometer-sized

mirrors organized in a two-dimensional array. As shown in Figure 6-13, the micromirror array consists of 960

micromirror columns × 960 micromirror rows in a diamond pixel configuration with a 2:1 aspect ratio.

Around the perimeter of the 960 × 960 array of micromirrors is a uniform band of border micromirrors called the

Pond of Micromirrors (POM). The border micromirrors are not user-addressable. The border micromirrors land in

the –12° position once power has been applied to the device. There are 10 border micromirrors on each side of

the 960 × 960 active array.

Due to the diamond pixel configuration, the columns of each odd row are offset by half a pixel from the columns

of the even row. Each mirror is switchable between two discrete angular positions: –12° and +12°. The mirrors

are illuminated from the bottom which allows for compact and efficient system optical design.

Although the native resolution of the DLP4620S-Q1 is 960 × 960 with an aspect ratio of 2:1, when paired with

the DLPC230S-Q1 controller, the DLP4620S-Q1 can be driven with different resolutions. For example, a Head-

Up Display system can use a resolution of 960 × 480 or 1920 × 960 with external quincunx processing before

the DLPC230S-Q1. The DLPC230S-Q1 can also support resolutions of 1220x610 and 1358 × 566 which are

displayed as 864 × 864 and 960 × 800 sub-images on the 960 × 960 DLP4620S-Q1, respectively. The table

below summarizes the resolution options.

表7-1. DLP4620S-Q1 Resolution Options

INPUT MANHATTAN RESOLUTION

EXTERNAL VIDEO PROCESSING

REQUIRED

DMD DIAMOND MIRRORS USED

960 × 480

1220 × 610

1358 × 566

1920 × 960

No

960 × 960

864 × 864 (sub-image)

960 × 800 (sub-image)

960 × 960

No

Yes: Quincunx

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7.2 Functional Block Diagram

High Speed Data Path &

Training: Bus A

High Speed Data Path &

Training: Bus B

(960, 960)

TEMP_P

TEMP_N

0.9 Mega Pixel 2:1 Aspect ratio

SRAM & Micromirror Array

(1,1)

DMD Mirror & SRAM Voltage Control

Low Speed Bus Interface & DMD Mirror

Voltage control

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7.3 Feature Description

The DLP4620S-Q1 consists of a two-dimensional array of 1-bit CMOS memory cells driven by a subLVDS bus

from the DLPC230S-Q1 and powered by the TPS99000S-Q1. The temperature sensing diode is used to

continuously monitor the DMD array temperature.

To ensure reliable operation, the DLP4620S-Q1 must be used with the DLPC230S-Q1 DMD display controller

and the TPS99000S-Q1 system management and illumination controller.

7.3.1 SubLVDS Data Interface

The subLVDS signaling protocol was designed to enable very fast DMD data refresh rates while simultaneously

maintaining low power and low emission.

Data is loaded into the SRAM under each micromirror using the subLVDS interface from the DLPC230S-Q1.

This interface consists of 16 pairs of differential data signals plus two clock pairs into two separate buses A and

B loading the left and right half of the SRAM array. The data is latched on both transitions creating a double data

rate (DDR) interface. The subLVDS interface also implements a continuous training algorithm to optimize the

data and clock timing to allow for a more robust interface.

The entire DMD array of 0.9 million pixels can be updated at a rate of less than 100 µs as a result of the high

speed subLVDS interface.

7.3.2 Low Speed Interface for Control

The purpose of the low speed interface is to configure the DMD at power up and power down and to control the

micromirror reset voltage levels that are synchronized with the data loading. The micromirror reset voltage

controls the time when the mirrors are mechanically switched. The low speed differential interface includes two

pairs of signals for write data and clock, and two single-ended signals for output (A and B).

7.3.3 DMD Voltage Supplies

The micromirrors require unique voltage levels to control the mechanical switching from –12° to +12°. These

voltage levels are nominally 16 V, 8.5 V, and –10 V (VBIAS, VOFFSET, and VRESET), and are generated by

the TPS99000S-Q1.

7.3.4 Asynchronous Reset

Reset of the DMD is required and controlled by the DLPC230S-Q1 via the signal DMD_DEN_ARSTZ.

7.3.5 Temperature Sensing Diode

The DMD includes a temperature sensing diode designed to be used with the TMP411 temperature monitoring

device. The DLPC230S-Q1 monitors the temperature sense diode via the TMP411. The DLPC230S-Q1

operation of the DMD timing can be adjusted based on the DMD array temperature, therefore this connection is

essential to ensure reliable operation of the DMD.

图7-1 shows the typical connection between the DLPC230S-Q1, TMP411, and the DMD.

图7-1. Temperature Sense Diode Typical Circuit Configuration

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7.3.5.1 Temperature Sense Diode Theory

A temperature sensing diode is based on the fundamental current and temperature characteristics of a transistor.

The diode is formed by connecting the transistor base to the collector. Three different known currents flow

through the diode and the resulting diode voltage is measured in each case. The difference in their base–

emitter voltages is proportional to the absolute temperature of the transistor.

Refer to the TMP411-Q1 data sheet for detailed information about temperature diode theory and measurement.

图7-2 and 图7-3 illustrate the relationships between the current and voltage through the diode.

IE1

IE2

TEMP_N

+

VBE 1,2

-

TEMP_P

图7-2. Temperature Measurement Theory

100uA

10uA

1uA

Temperature (°C)

图7-3. Example of Delta VBE Versus Temperature

7.4 System Optical Considerations

Optimizing system optical performance and image performance strongly relates to optical system design

parameter trades. Although it is not possible to anticipate every conceivable application, projector image and

optical performance is contingent on compliance to the optical system operating conditions described in the

following sections.

7.4.1 Numerical Aperture and Stray Light Control

The numerical aperture of the illumination and projection optics at the DMD optical area should be the same.

This cone angle defined by the numerical aperture should not exceed the nominal device mirror tilt angle unless

appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light

from the projection lens. The mirror tilt angle defines the DMD's capability to separate the "On" optical path from

any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces.

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7.4.2 Pupil Match

TI’s optical and image performance specifications assume that the exit pupil of the illumination optics is

nominally centered and located at the entrance pupil position of the projection optics. Misalignment of pupils

between the illumination and projection optics can degrade screen image uniformity and cause objectionable

artifacts in the display’s border and/or active area. These artifacts may require additional system apertures to

control, especially if the numerical aperture of the system exceeds the pixel tilt angle.

7.4.3 Illumination Overfill

Overfill light illuminating the area outside the active array can create artifacts from the mechanical features and

other surfaces that surround the active array. These artifacts may be visible in the projected image. The

illumination optical system should be designed to minimize light flux incident outside the active array and on the

window aperture. Depending on the particular system’s optical architecture and assembly tolerances, this

amount of overfill light on the area outside of the active array may still cause artifacts to be visible.

Illumination light and overfill can also induce undesirable thermal conditions on the DMD, especially if

illumination light impinges directly on the DMD window aperture or near the edge of the DMD window. Heat load

on the aperture in the areas shown in 图 6-1 should not exceed the values listed in Recommended Operating

Conditions. This area is a 0.5-mm wide area and length of the aperture opening. The values listed in

Recommended Operating Conditions assume a uniform distribution. For a non-uniform distribution please

contact TI for additional information.

备注

TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD FAILURES

CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING LIMITS DESCRIBED

PREVIOUSLY.

7.5 DMD Image Performance Specification

表7-2. DMD Image Performance

PARAMETER^{(1) (2)}

Dark Blemishes—Viewed on a linear blue 60 screen⁽³⁾

Light Blemishes—Viewed on a linear gray 10 screen.

Bright Pixels—Viewed on a linear gray 10 screen.

Dark Pixels—Viewed on a white screen

MIN

NOM

MAX

UNIT

4

0

4

micromirrors

(1) See the System Optical Considerations section.

(2) Blemish counts do not include reflections or shadows of the same artifact. Any artifact that is not specifically called out in this table is

acceptable. Viewing distance must be > 60 in. Screen size should be similar to application image size. All values referenced are in

linear gamma. Non-linear gamma curves may be running by default, and it should be ensured with a TI applications engineer that the

equivalent linear gamma value as specified is used to judge artifacts.

(3) Linear gray 5 may be substituted in monochrome applications.

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7.6 Micromirror Array Temperature Calculation

Array

TP1

1.10

15.40

TP1

图7-4. DMD Thermal Test Points

The active array temperature can be computed analytically from the thermal measurement point on the outside

of the package, the package thermal resistance, the electrical power, and the illumination heat load. The

relationship between array temperature and the reference ceramic temperature (TP1) in Figure 7-4 is provided

by the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY–TO–CERAMIC}

)

(1)

(2)

(3)

Q_ILLUMINATION= (Q_INCIDENT× DMD Absorption Constant)

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

where

• T_ARRAY= computed array temperature (°C)

• T_CERAMIC= measured ceramic temperature at the TP1 location in DMD Thermal Test Points (°C)

• R_{ARRAY–TO–CERAMIC}= DMD package thermal resistance from array to thermal test point TP1 (°C/W),

• Q_ARRAY= total power (electrical plus absorbed) on the DMD array (W)

• Q_ELECTRICAL= nominal electrical power dissipation by the DMD (W)

• Q_ILLUMINATION= absorbed illumination heat load (W)

• Q_INCIDENT= incident power on the DMD (W)

The DMD absorption constant is a function of illumination distribution on the active array and the array border,

angle of incidence (AOI), f number of the system, and operating state of the mirrors. The absorption constant is

higher in the OFF state than in the ON state. Equations to calculate the absorption constant are provided for

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both ON and OFF mirror states. They assume an AOI of 34 degrees, an f/1.7 system, and they account for the

distribution of light on the active array, POM, and array border.

DMD Absorption Constant (OFF state) = 0.895 –0.004783 × (% of light on ActiveArray + POM)

(4)

DMD Absorption Constant (ON state) = 0.895 –0.007208 × (% of light on ActiveArray + POM)

(5)

Electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating

frequencies.

The following sample calculations assume 10% of the total incident light falls outside of the active array and

POM, and the mirrors are in the OFF state.

1. T_CERAMIC= 50°C (measured)

2. Q_INCIDENT= 10 W (measured)

3. DMD Absorption Constant = 0.895 –0.004783 × 90 = 0.46

4. Q_ELECTRICAL= 0.4 W

5. R_{ARRAY–TO–CERAMIC}= 1.3°C/W

6. Q_ARRAY= 0.4 W + (0.46 x 10 W) = 5 W

7. T_ARRAY= 50°C x (5 W x 1.3°C/W) = 56.5°C

When designing the DMD heatsink solution, the package thermal resistance from array to reference ceramic

temperature (thermocouple location TP1 can be used to determine the temperature rise through the package as

given by the following equations:

T_{ARRAY-TO-CERAMIC}= Q_ARRAY× R_{ARRAY–TO–CERAMIC}

(6)

7.6.1 Monitoring Array Temperature Using the Temperature Sense Diode

The active array temperature can be computed analytically from the temperature sense diode measurement, the

thermal resistance from array to diode, the electrical power, and the illumination heat load. The relationship

between array temperature and the temperature sense diode is provided by the following equations:

T_ARRAY= T_DIODE+ (Q_ARRAY× R_{ARRAY–TO–DIODE}

)

(7)

(8)

(9)

Q_ILLUMINATION= (Q_INCIDENT× DMD Absorption Constant)

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

where

• T_ARRAY= computed array temperature (°C)

• T_DIODE= measured temperature sense diode temperature (°C)

• R_{ARRAY–TO–DIODE}= package thermal resistance from array to diode (°C/W)

• Q_ARRAY= total power, electrical plus absorbed, on the DMD array (W)

Refer to Section 7.6 for details.

• Q_ELECTRICAL= nominal electrical power dissipation by the DMD (W)

• Q_ILLUMINATION= absorbed illumination heat load (W)

• Q_INCIDENT= incident power on the DMD (W)

The temperature sense diode to array thermal resistance (R_{ARRAY–TO–DIODE}) assumes a uniform illumination

distribution on the DMD.

The following sample calculations assume 10% of the total incident light falls outside of the active array and

POM, and the mirrors are in the OFF state.

1. T_DIODE= 55°C/W

2. Q_INCIDENT= 10 W (measured)

3. DMD Absorption Constant = 0.895 –0.004783 × 90 = 0.46

4. Q_ELECTRICAL= 0.4 W

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5. R_{ARRAY–TO–DIODE}= 0.1°C/W

6. Q_ARRAY= 0.4 W + (0.46 × 10 W) = 5 W

7. T_ARRAY= 55°C + (5 W × 0.1°C/W) = 55.5°C

7.7 Micromirror Landed-On/Landed-Off Duty Cycle

7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the ON state versus the amount of time the same

micromirror is landed in the OFF state.

As an example, a landed duty cycle of 90/10 indicates that the referenced pixel is in the ON state 90% of the

time (and in the OFF state 10% of the time), whereas 10/90 would indicate that the pixel is in the OFF state 90%

of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

always add to 100.

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The DLP4620S-Q1 chipset is designed to support projection-based automotive applications such as s head-up

display systems.

8.2 Typical Application

The chipset consists of three components—the DLP4620S-Q1 automotive DMD, the DLPC230S-Q1, and the

TPS99000S-Q1. The DMD is a light modulator consisting of tiny mirrors that are used to form and project

images. The DLPC230S-Q1 is a controller for the DMD; it formats incoming video and controls the timing of the

DMD illumination sources and the DMD in order to display the incoming video. The TPS99000S-Q1 is a high

performance voltage regulator for the DMD, a controller for the illumination sources (e.g. LEDs or lasers) and a

management IC for the entire chipset. In conjunction, the DLPC230S-Q1 and the TPS99000S-Q1 can be used

for system-level monitoring, diagnostics, and failure detection features. 图 8-1 is a system level block diagram

with these devices in the DLP head-up display configuration and displays the primary features and functions of

each device.

VLED

6.5 V

Pre-

Supplies for

DLPC230 and

DMD

6.5 V

3.3 V

1.1 V

1.8 V

3.3 V

Regulator

VBATT

reg

Reg

LDO

(Optional)

Power Sequencing

and Monitoring

High-side Current

Limiting

PROJ_ON

Optional SPI Monitor

12-bit

ADC

External ADC Inputs

for General Usage

LM3409

LED drive

AC3

ADC_CTRL(2)

SPI(4)

F

SPI_2

Shunt (2

)

E

T

s

RED

GREEN

BLUE

MPU

ECC

WD(2)

LED_SEL(4)

SEQ_START

S_EN

Ultra Wide Dimming

LED Controller

SPI_1

Low-side Current

Measurement

HOST_IRQ

TPS99000S-Q1

OpenLDI

D_EN

DLPC230S-Q1

Illumination

Optics

Host

Photo Diode

External Watchdogs /

Over Brightness / and

Other Monitors

CTRL

4

DATA

24

COMPOUT

SEQ_CLK

Parallel

28

eSRAM

Frame Buffer

General

Purpose

PARKZ

RESETZ

INTZ

Photo Diode

Meas. System

PD Neg

LDO

I2C(2)

SPI(4)

I2C_0

BIAS, RST, OFS

(3)

SPI_0

Spare

GPIO

GPIOx

I2C_1

Sys Clock

Monitor

DMD Bias

Regulator

VCC_FLASH

VCC_INTF

3.3 V

EEPROM

1.8 V

1.1 V

VIO

TMP411

(2)

DMD Die Temperature

VCORE

DLP4620S-Q1

DMD

Sub-LVDS

Interface

Sub-LVDS DATA

Control

图8-1. HUD System Block Diagram

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8.2.1 Application Overview

图 8-1 shows the system block diagram for a DLP HUD module. The system uses the DLPC230S-Q1,

TPS99000S-Q1, and the DLP4620S-Q1 automotive DMD to enable a head-up display with high brightness, high

efficiency, and a large virtual image distance. The combination of the DLPC230S-Q1 and TPS99000S-Q1

removes the need for external SDRAM and a dedicated microprocessor. The chipset manages the illumination

control of LED sources, power sequencing functions, and system management functions. Additionally, the

chipset supports numerous system diagnostic and built-in self test (BIST) features. The following paragraphs

describe the functionality of the chipset used for a HUD system in more detail.

The DLPC230S-Q1 is a controller for the DMD and the light sources in the DLP Headlight, HUD or Projector

module. It receives input video from the host and synchronizes DMD and light source timing in order to achieve

the desired video. The DLPC230S-Q1 formats input video data that is displayed on the DMD. It synchronizes

these video segments with light source timing in order to create a video with grayscale shading and multiple

colors, if applicable.

The DLPC230S-Q1 receives inputs from a host processor in the vehicle. The host provides commands and input

video data. Host commands can be sent using either the I²C bus or SPI bus. The bus that is not being used for

host commands can be used as a read-only bus for diagnostic purposes. Input video can be sent over an

OpenLDI bus or a parallel 24-bit bus. The 24-bit bus can be limited to only 8-bits or 16-bits of data for single light

source or dual light source systems depending on the system design. The SPI flash memory provides the

embedded software for the DLPC230S-Q1’s ARM core, any calibration data, and default settings. The

TPS99000S-Q1 provides diagnostic and monitoring information to the DLPC230S-Q1 using an SPI bus and

several other control signals such as PARKZ, INTZ, and RESETZ to manage power-up and power-down

sequencing. The TMP411 uses an I²C interface to provide the DMD array temperature to the DLPC230S-Q1.

The outputs of the DLPC230S-Q1 are configuration and monitoring commands to the TPS99000S-Q1, timing

controls to the LED or laser driver, control and data signals to the DMD, and monitoring and diagnostics

information to the host processor. The DLPC230S-Q1 communicates with the TPS99000S-Q1 over an SPI bus.

It uses this to configure the TPS99000S-Q1 and to read monitoring and diagnostics information from the

TPS99000S-Q1. The DLPC230S-Q1 sends drive enable signals to the LED or laser driver, and synchronizes this

with the DMD mirror timing. The control signals to the DMD are sent using a subLVDS interface.

The TPS99000S-Q1 is a highly integrated mixed-signal IC that controls DMD power and provides monitoring and

diagnostics information for the DLP HUD system. The power sequencing and monitoring blocks of the

TPS99000S-Q1 properly power up the DMD and provide accurate DMD voltage rails (–16 V, 8.5 V, and 10 V),

and then monitor the system’s power rails during operation. The integration of these functions into one IC

significantly reduces design time and complexity. The TPS99000S-Q1 also has several output signals that can

be used to control a variety of LED or laser driver topologies. The TPS99000S-Q1 has several general-purpose

ADCs that designers can use for system level monitoring, such as over-brightness detection.

The TPS99000S-Q1 receives inputs from the DLPC230S-Q1, the power rails it monitors, the host processor, and

potentially several other ADC ports. The DLPC230S-Q1 sends configuration and control commands to the

TPS99000S-Q1 over an SPI bus and several other control signals. The DLPC230S-Q1’s clocks are also

monitored by the watchdogs in the TPS99000S-Q1 to detect any errors. The power rails are monitored by the

TPS99000S-Q1 in order to detect power failures or glitches and request a proper power down of the DMD in

case of an error. The host processor can read diagnostics information from the TPS99000S-Q1 using a

dedicated SPI bus, which enables independent monitoring. Additionally, the host can request the image to be

turned on or off using a PROJ_ON signal. Lastly, the TPS99000S-Q1 has several general-purpose ADCs that

can be used to implement system level monitoring functions.

The outputs of the TPS99000S-Q1 are diagnostic information and error alerts to the DLPC230S-Q1, and control

signals to the LED or laser driver. The TPS99000S-Q1 can output diagnostic information to the host and the

DLPC230S-Q1 over two SPI buses. In case of critical system errors, such as power loss, it outputs signals to the

DLPC230S-Q1 that trigger power down or reset sequences. It also has output signals that can be used to

implement various LED or laser driver topologies.

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The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video

data), and produces a mechanical output (mirror position). The electrical interface to the DMD is a subLVDS

interface with the DLPC230S-Q1. The mechanical output is the state of more than 0.9 million mirrors in the DMD

array that can be tilted ±12°. In a projection system the mirrors are used as pixels in order to display an image.

8.2.2 Reference Design

For information about connecting together the DLP4620S-Q1 DMD, DLPC230S-Q1 controller, and TPS99000S-

Q1, please contact the TI Application Team for additional information about the DLP4620S-Q1 evaluation

module (EVM). TI has optical-mechanical reference designs available, see the TI Application team for more

information.

8.2.3 Application Mission Profile Consideration

Each application is anticipated to have different mission profiles, or number of operating hours at different

temperatures. To assist in evaluation an Application Report may be provided in the future. See the TI Application

team for more information.

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET.

All VSS connections are also required. DMD power-up and power-down sequencing is strictly controlled by the

TPS99000S-Q1 device.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to the prescribed power-up and power-down procedures may affect

device reliability.

VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-

up and power-down operations. Failure to meet any of the below requirements will result in a

significant reduction in the DMD’s reliability and lifetime. VSS must also be connected.

9.1 Power Supply Power-Up Procedure

• During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET

voltages are applied to the DMD.

• During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the

specified limit shown in the Recommended Operating Conditions.

• During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have

settled at operating voltage.

• During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow

the requirements listed previously and in 图9-1.

9.2 Power Supply Power-Down Procedure

• The power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be

supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.

• During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement

that the delta between VBIAS and VOFFSET must be within the specified limit shown in the Recommended

Operating Conditions (refer to Note 2 in 节9.3).

• During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in the

Recommended Operating Conditions.

• During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS.

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements listed previously and in 节9.3.

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9.3 Power Supply Sequencing Requirements

TPS9900x initiates DMD power-

down sequence. DLPC231

executes critical commands.

DLPC231 and TPS9900x

control start of DMD

operation

DLPC231 and TPS9900x

disables VBIAS, VOFFSET, and

VRESET

Mirror Park Sequence⁽⁴⁾

Power off

VSS

VDD / VDDI

VSS

VBIAS

VBIAS < 4 V

V < Specification⁽¹⁾⁽²⁾

V < Specification⁽³⁾

VSS

V < Specification⁽²⁾

VOFFSET

VSS

VOFFSET < 4 V

VSS

VRESET < 0.5 V

VRESET > - 4 V

VSS

VRESET

VDD

DMD_DEN_ARSTZ

VSS

Initialization

LS_CLK_P

LS_CLK_N

VSS

LS_WDATA_P

LS_WDATA_N

D_AP(7:0) , D_AN(7:0)

D_BP(7:0) , D_BN(7:0) VSS

DCLK_AP , DCLK_AN

DCLK_BP , DCLK_BN

VSS

A. To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified in the Recommended Operating

Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to

remove VBIAS prior to VOFFSET during power-down. Also, the TPS99000S-Q1 is capable of managing the timing between VBIAS and

VOFFSET.

B. To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified than the limit shown in the

Recommended Operating Conditions.

C. When system power is interrupted, the TPS99000S-Q1 initiates hardware power-down that disables VBIAS, VRESET, and VOFFSET

after the Micromirror Park Sequence.

D. The drawing is not to scale and details are omitted for clarity.

图9-1. Power Supply Sequencing Requirements (Power Up and Power Down)

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10 Layout

10.1 Layout Guidelines

Please refer to the DLPC230S-Q1 and TPS99000S-Q1 data sheets for specific PCB layout and routing

guidelines. For specific DMD PCB guidelines, use the following:

• Match lengths for the LS_WDATA and LS_CLK signals

• Minimize vias, layer changes, and turns for the HS bus signals

• Minimum of two 220-nF decoupling capacitors close to VBIAS

• Minimum of two 220-nF decoupling capacitors close to VRESET

• Minimum of two 220-nF decoupling capacitors close to VOFFSET

• Minimum of four 100-nF decoupling capacitors close to VDDI and VDD

• Temperature diode pins

The DMD has an internal diode (PN junction) that is intended to be used with an external TI TMP411

temperature sensing IC. PCB traces from the DMD’s temperature diode pins to the TMP411 are sensitive to

noise. See the TMP411 ±1°C Remote and Local Temperature Sensor with N-Factor and Series Resistance

Correction Data Sheet for specific routing recommendations.

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11 Device and Documentation Support

11.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.2 Device Support

11.2.1 Device Nomenclature

DLP4620S A FQX Q1

Automotive Qualified

Package Type

Temperature Range (-40 to 105ºC)

Device Descriptor

图11-1. Part Number Description

11.2.2 Device Markings

The device marking includes the legible character string GHJJJJK DLP4620SAFQXQ1. GHJJJJK is the lot trace

code. DLP4620SAFQXQ1 is the part number.

Lot Trace Code

Two-Dimensional Matrix Code

(DMD part number and lot trace code)

Part Marking

图11-2. DMD Marking

11.3 Trademarks

DLP^®is a registered trademark of Texas Instruments.

is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.4 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

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11.5 DMD Handling

The DMD is an optical device so precautions should be taken to avoid damaging the glass window. Please see

the application note DLPA019 DMD Handling for instructions on how to properly handle the DMD.

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	XDLP462SAFQXQ1
厂家：	TEXAS INSTRUMENTS
描述：	适用于内部显示应用的汽车类 0.46 英寸 DLP® 数字微镜器件 (DMD) \| FQX \| 120 \| -40 to 105
文件：	总36页 (文件大小：1516K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XDLP462SAFQXQ1 [TI]

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