XIO2000AZAY [TI]
XIO2000A/XIO2000AI PCI Express to PCI Bus Translation Bridge;
| 型号： | XIO2000AZAY |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | XIO2000A/XIO2000AI PCI Express to PCI Bus Translation Bridge PC |
| 文件： | 总165页 (文件大小：2177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XIO2000A/XIO2000AI PCI Express
to PCI Bus Translation Bridge
Data Manual
Literature Number: SCPS155C
April 2007 Revised October 2008
Printed on Recycled Paper
Contents
Section
Page
1
2
XIO2000A Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
2
3
3
3
4
13
20
20
20
21
22
23
23
24
24
24
24
25
25
25
26
26
27
28
28
29
30
31
32
33
34
35
36
37
38
38
40
42
42
42
43
43
43
3
Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Power-Up/-Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
3.1.2
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
3.3
Bridge Reset Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
External Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Beacon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initial Flow Control Credits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Message Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
3.5
PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clamping Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Bus Clock Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Bus External Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MSI Messages Generated from the Serial IRQ Interface . . . . . . . . . . . . . . . . . . . . . .
PCI Bus Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quality of Service and Isochronous Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
3.5.2
3.5.3
3.5.4
PCI Port Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Isochronous Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Extended VC With VC Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128-Phase, WRR PCI Port Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
3.7
3.8
3.9
3.10
Configuration Register Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interrupt Conversion to PCI Express Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PME Conversion to PCI Express Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express To PCI Bus Lock Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-Wire Serial-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.1
3.10.2
3.10.3
3.10.4
Serial-Bus Interface Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accessing Serial-Bus Devices Through Software . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11
3.12
3.13
3.14
3.15
Advanced Error Reporting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Error Forwarding Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Slot Power Limit Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express and PCI Bus Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
April 2007 Revised October 2008
SCPS155C
Contents
4
Classic PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
46
46
47
48
49
49
49
49
50
50
50
51
51
51
51
52
53
54
54
54
55
55
55
56
56
56
57
57
57
59
59
60
61
61
62
62
62
63
63
64
64
64
65
65
65
65
66
66
4.1
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Control Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prefetchable Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prefetchable Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prefetchable Base Upper 32-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prefetchable Limit Upper 32-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Base Upper 16-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Limit Upper 16-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Bridge Support Extension Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MSI Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MSI Message Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MSI Message Lower Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MSI Message Upper Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MSI Message Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
4.22
4.23
4.24
4.25
4.26
4.27
4.28
4.29
4.30
4.31
4.32
4.33
4.34
4.35
4.36
4.37
4.38
4.39
4.40
4.41
4.42
4.43
4.44
4.45
4.46
4.47
4.48
iv
SCPS155C
April 2007 Revised October 2008
4.49
4.50
4.51
4.52
4.53
4.54
4.55
4.56
4.57
4.58
4.59
4.60
4.61
4.62
4.63
4.64
4.65
4.66
4.67
4.68
4.69
4.70
4.71
4.72
4.73
4.74
Device Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Word Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Diagnostic Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Diagnostic Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Diagnostic Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Run Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbiter Request Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbiter Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Edge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
68
69
70
71
72
72
72
73
74
75
76
77
78
79
79
80
82
83
84
85
86
87
88
89
90
5
PCI Express Extended Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Advanced Error Reporting Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next Capability Offset/Capability Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Uncorrectable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Uncorrectable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Uncorrectable Error Severity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Correctable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Correctable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Error Capabilities and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Header Log Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Uncorrectable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Uncorrectable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Uncorrectable Error Severity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Error Capabilities and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Header Log Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual Channel Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next Capability Offset/Capability Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port VC Capability Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port VC Capability Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port VC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port VC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Resource Capability Register (VC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Resource Control Register (VC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93
93
94
95
96
97
98
99
5.9
99
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
100
101
102
103
104
104
105
105
106
107
107
108
109
v
April 2007 Revised October 2008
SCPS155C
Contents
5.23
5.24
5.25
5.26
5.27
5.28
VC Resource Status Register (VC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Resource Capability Register (VC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Resource Control Register (VC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Resource Status Register (VC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Arbitration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Arbitration Table (VC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
110
111
112
112
113
114
114
115
115
116
117
117
117
118
118
118
119
119
119
120
120
120
121
122
122
123
123
124
125
126
127
129
129
129
130
131
132
135
136
136
137
137
138
139
140
141
6
Memory-Mapped TI Proprietary Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
6.2
6.3
6.4
Device Control Map ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochrony Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochrony Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 0 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 0 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 0 Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 1 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 1 Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 2 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 2 Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 3 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 3 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 3 Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Word Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Edge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
6.25
7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
Absolute Maximum Ratings Over Operating Temperature Ranges † . . . . . . . . . . . . . . . . . . . . .
Recommended Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nominal Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Differential Transmitter Output Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Differential Receiver Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Differential Reference Clock Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Over Recommended Operating Conditions (PCI Bus) . . . . . . . . . . .
Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O) . . . . . . . . . . .
PCI Clock Timing Requirements Over Recommended Operating Conditions . . . . . . . . . . . . . .
PCI Bus Timing Requirements Over Recommended Operating Conditions . . . . . . . . . . . . . . . .
PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
9
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
SCPS155C
April 2007 Revised October 2008
List of Figures
Figure
Page
TM
2−1
2−2
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
XIO2000A GZZ/ZZZ MicroStar BGA
Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
8
XIO2000A ZHH Microstar BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XIO2000A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Type 0 Configuration Transaction Address Phase Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Type 1 Configuration Transaction Address Phase Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Assert_INTx Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Deassert_INTx Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
21
22
25
33
33
34
35
35
35
36
37
37
38
39
39
39
40
40
137
139
139
139
3−10 PCI Express PME Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Starting A Locked Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 Continuing A Locked Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 Terminating A Locked Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 Serial EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 Serial-Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 Serial-Bus Protocol Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 Serial-Bus Protocol—Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18 Serial-Bus Protocol—Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−19 Serial-Bus Protocol—Multibyte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1
7−2
7−3
7−4
Load Circuit And Voltage Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRST Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shared Signals Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
April 2007 Revised October 2008
SCPS155C
Tables
Table
List of Tables
Page
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
XIO2000A GZZ/ZZZ Terminals Sorted Alphanumerically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XIO2000A ZHH Terminals Sorted Alphanumerically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XIO2000A Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combined Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bridge Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initial Flow Control Credit Advertisements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Messages Supported by the Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Interrupt to MSI Message Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Classic PCI Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Number to PCI Bus Device Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128-Phase, WRR Time-Based Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Isochronous Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware-Fixed, Round-Robin Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-phase, WRR Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Type 0 Configuration Transaction IDSEL Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Mapping In The Code Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Register Loading Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Used To Program Serial-Bus Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking In Low Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Classic PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Control Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Base Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Limit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Base Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Limit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prefetchable Memory Base Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prefetchable Memory Limit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prefetchable Base Upper 32-Bit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prefetchable Limit Upper 32-Bit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Base Upper 16-Bit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Limit Upper 16-Bit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Bridge Support Extension Register Description . . . . . . . . . . . . . . . . . . . . . . . .
MSI Message Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
9
11
14
14
14
15
15
16
17
18
23
24
25
27
29
29
30
30
31
32
34
35
41
42
44
45
47
48
49
50
51
52
53
54
54
54
55
55
55
56
56
57
60
61
61
63
2−9
2−10
2−11
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
3−10
3−11
3−12
3−13
3−14
3−15
4−1
4−2
4−3
4−4
4−5
4−6
4−7
4−8
4−9
4−10
4−11
4−12
4−13
4−14
4−15
4−16
4−17
4−18
4−19
4−20
4−21
viii
SCPS155C
April 2007 Revised October 2008
Table
Page
4−22
4−23
4−24
4−25
4−26
4−27
4−28
4−29
4−30
4−31
4−32
4−33
4−34
4−35
4−36
4−37
4−38
4−39
4−40
4−41
4−42
4−43
4−44
4−45
4−46
4−47
4−48
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
5−10
5−11
5−12
5−13
5−14
5−15
5−16
5−17
5−18
5−19
5−20
5−21
MSI Message Lower Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MSI Message Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Control and Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Diagnostic Register 0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Diagnostic Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Diagnostic Register 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Run Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbiter Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbiter Request Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbiter Time-Out Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Mode Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Edge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Extended Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Uncorrectable Error Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Uncorrectable Error Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Uncorrectable Error Severity Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Correctable Error Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Correctable Error Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Error Capabilities and Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Uncorrectable Error Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Uncorrectable Error Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Uncorrectable Error Severity Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Error Capabilities and Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Header Log Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port VC Capability Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port VC Capability Register 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port VC Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port VC Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Resource Capability Register (VC0) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Resource Control Register (VC0) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Resource Status Register (VC0) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Resource Capability Register (VC1) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Resource Control Register (VC1) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
64
66
67
68
69
70
71
72
73
74
75
76
77
78
79
79
80
82
83
84
85
86
87
88
89
90
92
94
95
96
97
98
99
100
101
102
103
104
105
106
107
107
108
109
110
110
111
ix
April 2007 Revised October 2008
SCPS155C
Tables
Table
Page
5−22
5−23
5−24
5−25
5−26
6−1
6−2
6−3
6−4
6−5
6−6
6−7
6−8
6−9
6−10
6−11
6−12
6−13
6−14
VC Resource Status Register (VC1) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Arbitration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VC Arbitration Table Entry Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Arbitration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Arbitration Table Entry Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Control Memory Window Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochrony Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 0 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 1 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 2 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Isochronous Window 3 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Control and Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Mode Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Edge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial IRQ Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112
112
112
113
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
x
SCPS155C
April 2007 Revised October 2008
Features
1
XIO2000A Features
D
D
Full x1 PCI Express Throughput
D
D
D
Two Package Options: 15 mm x 15 mm and
12 mm x 12 mm
Fully Compliant with PCI Express to
PCI/PCI-X Bridge Specification,
Revision 1.0
Internal PCI Arbiter Supporting Up to 6
External PCI Masters
D
D
D
Fully Compliant with PCI Express Base
Specification, Revision 1.0a
Advanced VC Arbitration Options Include
VC1 Strict Priority, Hardware-Fixed
Round-Robin, and 32-Phase, Weighted
Round-Robin
Fully Compliant with PCI Local Bus
Specification, Revision 2.3
D
Advanced PCI Bus Port Arbitration Options
Include 128-phase, Weighted Round-Robin
Time-Based and 128-phase, Weighted
Round-Robin Aggressive Time-Based
Extended Virtual Channel (VC) Support
Includes a Second VC for
Quality-of-Service and Isochronous
Applications
D
D
Advanced PCI Isochronous Windows for
Memory Space Mapping to a Specified
Traffic Class
D
PCI Express Advanced Error Reporting
Capability Including ECRC Support
D
Support for D1, D2, D3 , and D3
hot
cold
Advanced PCI Express Message Signaled
Interrupt Generation for Serial IRQ
Interrupts from CardBus Applications
D
Active State Link Power Management
Saves Power When Packet Activity on the
PCI Express Link is Idle, Using Both L0s
and L1 States
D
D
D
D
D
D
D
D
External PCI Bus Arbiter Option
PCI Bus LOCK Support
D
D
D
Wake Event and Beacon Support
Clock Run and Power Override Support
Error Forwarding Including PCI Express
Data Poisoning and PCI Bus Parity Errors
Six Buffered PCI Clock Outputs (33 MHz or
66 MHz)
Utilizes 100-MHz Differential PCI Express
Common Reference Clock or 125-MHz
Single-Ended, Reference Clock
PCI Bus Interface 3.3-V and 5.0-V (33 MHz
only at 5.0 V) Tolerance Options
D
D
D
Robust Pipeline Architecture To Minimize
Transaction Latency
Integrated AUX Power Switch Drains V
AUX
Power Only When Main Power Is Off
Full PCI Local Bus 66-MHz/32-Bit
Throughput
Eight 3.3-V, Multifunction, General-Purpose
I/O Terminals
Support for Six Subordinate PCI Bus
Masters with Internal Configurable, 2-Level
Prioritization Scheme
Memory-Mapped EEPROM Serial-Bus
Controller Supporting PCI Express Power
Budget/Limit Extensions for Add-In Cards
D
D
Low Power Design (<350 mW) Ensures
Ease of Implementation
D
Compact Footprint, 201-Ball, GZZ
TM
MicroStar
BGA (XIO2000A only),
TM
Lead-Free 201-Ball, ZZZ MicroStar
175-Ball ZHC MicroStar BGA; or 175-Ball
ZHH MicroStar BGA
BGA;
XIO2000AI Supports Industrial
Temperatures at 33-MHz Bus Speeds
Table 1−1.
Figure 1−1.
MicroStar BGA is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
1
April 2007 Revised October 2008
SCPS155C
Introduction
2
Introduction
The Texas Instruments XIO2000A is a PCI Express to PCI local bus translation bridge that provides full PCI
Express and PCI local bus functionality and performance.
2.1 Description
The XIO2000A is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI
Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously
supports up to eight posted and four nonposted transactions for each enabled virtual channel (VC). For
upstream traffic, up to six posted and four nonposted transactions are simultaneously supported for each VC.
The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 1.0a.
The PCI Express interface supports a x1 link operating at full 250 MB/s packet throughput in each direction
simultaneously. Two independent VCs are supported. The second VC is optimized for isochronous traffic
types and quality-of-service (QoS) applications. Also, the bridge supports the advanced error reporting
capability including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental
firmware or software is required to fully utilize both of these features.
Robust pipeline architecture is implemented to minimize system latency across the bridge. If parity errors are
detected, then packet poisoning is supported for both upstream and downstream operations.
The PCI local bus is fully compliant with the PCI Local Bus Specification (Revision 2.3) and associated
programming model. Also, the bridge supports the standard PCI-to-PCI bridge programming model.
The PCI bus interface is 32-bit and can operate at either 33 MHz or 66 MHz. Also, the PCI interface provides
fair arbitration and buffered clock outputs for up to 6 subordinate devices. The bridge has advanced VC
arbitration and PCI port arbitration features for upstream traffic. When these arbitration features are fully
utilized, bridge throughput performance may be tuned for a variety of complex applications.
Power management (PM) features include active state link PM, PME mechanisms, the beacon and wake
protocols, and all conventional PCI D-states. If the active state link PM is enabled, then the link automatically
saves power when idle using the L0s and L1 states. PM active state NAK, PM PME, and PME-to-ACK
messages are supported. Standard PCI bus power management features provide several low power modes,
which enable the host system to further reduce power consumption.
The bridge has additional capabilities including, but not limited to, serial IRQ with MSI messages, serial
EEPROM, power override, clock run, and PCI bus LOCK. Also, eight general-purpose inputs and outputs
(GPIOs) are provided for further system control and customization.
2.2 Related Documents
•
•
•
•
•
•
•
•
•
PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
PCI Express Base Specification, Revision 1.0a
PCI Express Card Electromechanical Specification, Revision 1.0a
PCI Local Bus Specification, Revision 2.3
PCI-to-PCI Bridge Architecture Specification, Revision 1.2
PCI Bus Power Management Interface Specification, Revision 1.1 or 1.2
PCI Mobile Design Guide, Revision 1.1
Serialized IRQ Support for PCI Systems, Revision 6.0
PCI Express Jitter and BER White Paper
2.3 Trademarks
•
•
•
PCI Express is a trademark of PCI-SIG
TI and MicroStar BGA are trademarks of Texas Instruments
Other trademarks are the property of their respective owners
2
SCPS155C
April 2007 Revised October 2008
Introduction
2.4 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are
listed below:
1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary
field.
2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a
12-bit hexadecimal field.
3. All other numbers that appear in this document that do not have either a b or h following the number are
assumed to be decimal format.
4. If the signal or terminal name has a bar above the name (for example, GRST), then this indicates the
logical NOT function. When asserted, this signal is a logic low, 0, or 0b.
5. Differential signal names end with P, N, +, or − designators. The P or + designators signify the positive
signal associated with the differential pair. The N or − designators signify the negative signal associated
with the differential pair.
6. RSVD indicates that the referenced item is reserved.
7. The power and ground signals in Figure 2−1 are not subscripted to aid in readability.
8. In Sections 4 through 6, the configuration space for the bridge is defined. For each register bit, the software
access method is identified in an access column. The legend for this access column includes the following
entries:
r – read access by software
u – updates by the bridge internal hardware
w – write access by software
c – clear an asserted status bit with a write-back of 1b by software
2.5 Document History
REVISION REVISION
REVISION COMMENTS
DATE
NUMBER
05/2004
08/2005
−
Product preview
Initial release
A
2.6 Ordering Information
ORDERING NUMBER
NAME
VOLTAGE
PACKAGE
XIO2000A
XIO2000A
XIO2000A
XIO2000A
XIO2000AI
XIO2000AI
XIO2000AI
PCI-Express to PCI Bridge
PCI-Express to PCI Bridge
PCI-Express to PCI Bridge
PCI-Express to PCI Bridge
PCI-Express to PCI Bridge
PCI-Express to PCI Bridge
PCI-Express to PCI Bridge
3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
201-terminal GZZ MicroStar
PBGA
3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
201-terminal ZZZ (Lead-Free)
MicroStar PBGA
3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
175-terminal ZHH (Lead-Free)
MicroStar PBGA
3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
175-terminal ZHC (Lead-Free)
MicroStar PBGA
3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
201-terminal ZZZ (Lead-Free)
MicroStar PBGA
3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
175-terminal ZHH (Lead-Free)
MicroStar PBGA
3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
175-terminal ZHC (Lead-Free)
MicroStar PBGA
3
April 2007 Revised October 2008
SCPS155C
Introduction
2.7 Terminal Assignments
TM
The XIO2000A is available in either a 201-ball GZZ/ZZZ MicroStar
BGA or a 175−ball ZHH/ZHC Microstar
package. The XIO2000AI is available in a 201-ball ZZZ MicroStar BGA or a 175-ball ZHH MicroStar package.
Figure 2−1 shows a terminal diagram of the GZZ/ZZZ package, and Table 2−1 lists the GZZ/ZZZ terminals
sorted alphanumerically.
Figure 2−2 shows a terminal diagram of the ZHH package, and Table 2−2 lists the ZHH package terminals
sorted alphanumerically.
Figure 2−3 shows a terminal diagram of the ZHC package, and Table 2−3 lists the ZHC package terminals
sorted alphanumerically.
Table 2−4 shows the terminals by the alphabetically sorted signal names for both packages.
4
SCPS155C
April 2007 Revised October 2008
Introduction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GPIO1 //
PWR_
U
T
INTC
PRST
LOCK
GPIO3
GPIO6
GPIO7
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
OVRD
GPIO0 //
CLKRUN
GPIO5 //
SDA
INTB
M66EN
AD30
INTD
SERIRQ
VSS
GPIO2
VSS
RSVD
RSVD
VSS
RSVD
RSVD
RSVD
VSS
RSVD
VSS
RSVD
VSS
VDD_33
VSS
RSVD
RSVD
RSVD
VSS
GPIO4 //
SCL
R
P
N
M
L
INTA
AD31
AD29
AD27
C/BE[3]
AD21
AD19
AD17
IRDY
STOP
PAR
VDD_33
VDD_33
RSVD
RSVD
RSVD
WAKE
CLK
VSS
VDD_15
VDD_33
VDD_33
VDD_33
VDD_15
RSVD
PME
RSVD
GRST
AD28
VDD_15
_COMB
AD26
VDD_33
AD24
AD22
AD18
AD16
TRDY
PERR
VDD_33
VSS
VDD_33
_COMB
IO
REF0_
PCIE
REF1_
PCIE
AD23
AD25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
VDD_33
_AUX
VDDA_
33
VDD_33
_COMB
K
J
AD20
VSS
PERST
TXP
VDDA_
15
VDDA_
15
VCCP
C/BE[2]
FRAME
DEVSEL
SERR
C/BE[1]
AD14
VDD_15
VDD_33
VSS
VSSA
TXN
VDD_
15
H
G
F
VSSA
VDDA_
15
VSSA
VSSA
VSSA
RXN
VSS
VDDA_
15
VSSA
VSSA
E
D
C
B
A
RXP
VDDA_
33
AD15
AD13
AD3
AD2
AD1
VSS
VDD_15
REQ1
VDD_33
REQ2
VSS
GNT3
REQ3
RSVD
RSVD
CLK
REF
REF
AD8
VSS
AD7
VDD_33
AD5
GNT4
REQ4
VDD_33
REQ5
VSS
OUT0
CLK−
CLK+
CLK
CLK
CLK
CLKRUN
_EN
AD12
AD10
C/BE[0]
REQ0
VSSA
OUT1
OUT2
OUT6
CLK
CLK
CLK
EXT_
REFCLK
_SEL
AD11
AD9
VCCP
AD6
AD4
AD0
GNT0
GNT1
GNT2
GNT5
OUT3
OUT4
OUT5
ARB_EN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Figure 2−1. XIO2000A GZZ MicroStar BGA Package,
XIO2000A/XIO2000AI ZZZ MicroStar BGA Package(Bottom View)
5
April 2007 Revised October 2008
SCPS155C
Introduction
Table 2−1. GZZ/ZZZ Terminals Sorted Alphanumerically
BGA BALL #
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
SIGNAL NAME
BGA BALL #
C17
D01
D02
D03
D07
D08
D09
D10
D11
D15
D16
D17
E01
E02
E03
E15
E16
E17
F01
SIGNAL NAME
REFCLK+
BGA BALL #
H10
H11
H14
H15
H16
H17
J01
SIGNAL NAME
AD11
AD9
V
V
V
V
SS
C/BE[1]
AD15
SS
V
CCP
DD_15
SSA
AD6
AD4
AD0
V
SS
AD3
TXN
TXP
V
V
V
V
V
SS
GNT0
V
CCP
DD_15
DD_33
SS
GNT1
J02
AD19
AD18
GNT2
J03
CLKOUT3
CLKOUT4
CLKOUT5
GNT5
J04
V
V
V
V
V
V
V
V
V
DDA_33
DD_15
A12
A13
A14
A15
A16
B01
B03
B04
B05
B06
B07
B08
B09
B10
B11
RSVD
RSVD
SERR
PAR
J07
SS
J08
SS
J09
SS
EXT_ARB_EN
REFCLK_SEL
AD12
J10
SS
V
V
J11
DD_33
SS
J14
SSA
DDA_15
DDA_15
SSA
AD10
RXN
J15
C/BE[0]
AD7
RXP
J16
DEVSEL
STOP
PERR
J17
PERST
AD20
AD21
AD22
AD5
F02
K01
K02
K03
K04
K07
K08
K09
K10
K11
K14
K15
K16
K17
L01
L02
L03
L04
L07
L08
L09
L10
L11
AD1
F03
REQ0
F15
V
V
V
SSA
CLKOUT1
CLKOUT2
REQ3
F16
V
V
V
V
V
V
V
V
V
V
SSA
SS
F17
DDA_15
SS
G01
G02
G03
G04
G07
G08
G09
G10
G11
G14
G15
G16
G17
H01
H02
H03
H04
H07
H08
H09
FRAME
IRDY
SS
B12
B13
B14
B15
B17
C01
C02
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C16
REQ4
SS
REQ5
TRDY
SS
CLKOUT6
CLKRUN_EN
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
DD_33_AUX
DDA_33
DD_33_COMB
SS
V
SSA
SS
AD14
AD13
AD8
SS
SS
AD23
C/BE[3]
AD24
AD25
SS
V
V
SS
SSA
DDA_15
SSA
SS
DD_33
AD2
CLKOUT0
REQ1
REQ2
GNT3
GNT4
V
V
V
V
V
V
V
SS
C/BE[2]
AD17
SS
SS
AD16
SS
V
V
V
V
DD_33
SS
V
V
L14
L15
L16
DD_33
SS
DD_33_COMBIO
SSA
SS
SS
REFCLK−
REF0_PCIE
SS
6
SCPS155C
April 2007 Revised October 2008
Introduction
Table 2−1. GZZ/ZZZ Terminals Sorted Alphanumerically (Continued)
BGA BALL #
L17
SIGNAL NAME
REF1_PCIE
BGA BALL #
P17
SIGNAL NAME
RSVD
BGA BALL #
T09
SIGNAL NAME
RSVD
M01
M02
M03
M15
M16
M17
N01
N02
N03
N15
N16
N17
P01
AD26
AD27
R01
R02
R04
R05
R06
R07
R08
R09
R10
R11
M66EN
INTA
T10
RSVD
RSVD
RSVD
T11
V
V
V
V
T12
DD_33
SS
PME
T13
V
DD_33
DD_33
SS
WAKE
T14
RSVD
RSVD
RSVD
INTC
V
GPIO4 // SCL
RSVD
T15
DD_15_COMB
AD28
AD29
T17
RSVD
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
V
SS
V
V
V
V
V
PRST
LOCK
SS
RSVD
RSVD
GRST
AD30
AD31
CLK
SS
R12
R13
R14
R16
R17
T01
GPIO1 // PWR_OVRD
GPIO3
SS
SS
GPIO6
DD_33
P02
RSVD
GPIO7
P03
V
SS
RSVD
P07
V
V
V
V
V
V
INTB
RSVD
DD_15
P08
T03
INTD
RSVD
SS
P09
T04
SERIRQ
GPIO0 // CLKRUN
GPIO2
U12
U13
U14
U15
U16
RSVD
DD_33
DD_33
DD_33
DD_15
P10
T05
RSVD
P11
T06
RSVD
P15
T07
GPIO5 // SDA
RSVD
RSVD
P16
RSVD
T08
RSVD
7
April 2007 Revised October 2008
SCPS155C
Introduction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GPIO0//
GPIO1//
PRST
LOCK
GPIO4 // SCL
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VSSA
RSVD
P
P
N
M
L
CLKRUN
PWR_OVER
INTB
INTC
INTA
SERIRQ
INTD
GPGIO2
GPGIO3
AD29
GPIO5 // SDA
GPIO6
RSVD
RSVD
GPIO7
RSVD
RSVD
RSVD
RSVD
VSS
RSVD
VDD_33
VSS
RSVD
VDD_33
RSVD
RSVD
VDD_33
VSS
VDD_15
RSVD
PME
VSS
RSVD
GRST
RSVD
RSVD
RSVD
WAKE
N
M66EN
M
AD31
AD30
AD27
C/BE[3]
AD21
AD17
C/BE[2]
CCLK
VDD_15
VDD_33
L
VDD_33_
COMBIO
VDD_15_
COMB
AD26
AD28
AD24
AD20
AD18
AD16
VDD_33
AD25
VSSA
K
K
J
AD23
VDD_33
VSS
VDD_33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDA_33
VDDA_15
VSVSA
VDD_33_
AUX
REF1_PCIE REF0_PCIE
VDD_33_
J
AD19
AD22
PERST
VSSA
VDDA_15
COMB
H
H
G
F
VCCP
VDD_15
VDD_33
VSS
VSS
VSS
TXN
VSS
TXP
G
FRAME
VSS
VSS
VDD_33
VSSA
VDDA_15
VDD_15
F
TRDY
DEVSEL
PAR
STOP
PERR
IRDY
VDDA_15
GNT4
VSSA
VSSA
RXN
RRXP
E
E
D
C
B
A
SERR
VDD_33
VDD_33
AD1
CLKOUT0
VDD_15
VDD_33
CLKOUT3
RSVD
RSVD
D
C/BE[1]
AD15
AD12
AD14
AD10
AD8
AD7
AD6
AD3
AD4
GNT0
REQ0
GNT1
REQ2
GNT3
GNT3
GNT5
VDDA_33
REFCLK+
REFCLK−
VSSA
C
AD13
C/BE[0]
CLKOUT1
CLKOUT4
CLKOUT5 EXT_ARB_EN CLKRUN_EN
B
AD11
AD9
VCCP
AD5
AD2
AD0
REQ1
CLKOUT2
REQ3
REQ4
REQ5
CLKOUT6 REFCLK_SEL
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 2−2. XIO2000A/XIO2000AI ZHH Microstar BGA Package (Bottom View)
8
SCPS155C
April 2007 Revised October 2008
Introduction
Table 2−2. ZHH Terminals Sorted Alphanumerically
BGA BALL #
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
SIGNAL NAME
BGA BALL #
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
E01
E02
E03
E04
E11
SIGNAL NAME
DD_33
DD_33
BGA BALL #
H02
H03
H04
H06
H07
H08
H09
H11
H12
H13
H14
J01
SIGNAL NAME
AD11
AD9
V
V
AD21
AD20
AD22
V
AD1
CCP
AD5
AD2
AD0
CLKOUT0
V
V
V
V
V
SS
SS
SS
SS
V
V
DD_15
DD_33
REQ1
CLKOUT3
GNT4
CLKOUT2
REQ3
DDA_15
V
SSA
PERST
REQ4
RSVD
RSVD
TRDY
DEVSEL
STOP
IRDY
V
V
DDA_15
A12
A13
A14
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
REQ5
DD_33_COMB
CLKOUT6
REFCLK_SEL
AD13
AD23
C/BE[3]
AD24
AD25
J02
J03
AD12
J04
AD10
V
V
_
J06
V
V
V
V
V
V
DDA 15
DD_33
DD_33
SS
C/BE[0]
AD6
E12
E13
E14
F01
J07
SSA
RXN
J08
AD4
RXP
J09
SS
REQ0
FRAME
C/BE[2]
AD16
J11
DDA_33
DD_33_AUX
CLKOUT1
GNT2
F02
J12
F03
J13
REF1_PCIE
REF0_PCIE
AD26
CLKOUT4
CLKOUT5
EXT_ARB_EN
CLKRUN_EN
F04
V
V
V
V
V
V
V
V
V
V
J14
DD_33
F06
K01
K02
K03
K04
K11
K12
K13
K14
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
SS
B12
B13
B14
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
D01
D02
D03
F07
AD27
SS
F08
AD28
SS
V
F09
V
V
V
V
SSA
DD_33
SSA
DD_33
C/BE[1]
AD15
AD14
AD8
F11
SSA
F12
DDA_15
SS
DD_33_COMBIO
DD_15_COMB
F13
F14
WAKE
AD31
AD30
CLK
DD_15
CCP
AD7
G01
G02
G03
G04
G06
G07
G08
G09
G11
G12
G13
G14
H01
AD3
AD17
AD18
GNT0
GNT1
REQ2
GNT3
GNT5
V
V
V
V
V
V
V
AD29
DD_15
V
SS
DD_15
GPIO7
RSVD
SS
SS
V
V
V
DDA_33
SS
DD_33
REFCLK+
REFCLK−
SERR
SSA
SSA
SS
RSVD
TXN
TXP
V
SS
PAR
L12
L13
PME
PERR
AD19
GRST
9
April 2007 Revised October 2008
SCPS155C
Introduction
Table 2−2. ZHH Terminals Sorted Alphanumerically (Continued)
BGA BALL #
L14
SIGNAL NAME
RSVD
BGA BALL #
N01
SIGNAL NAME
BGA BALL #
P02
SIGNAL NAME
LOCK
INTB
INTC
M01
M66EN
INTA
N02
P03
GPIO0 // CLKRUN
GPIO1 // PWR_OVER
GPIO4 // SCL
RSVD
M02
N03
SERIRQ
GPIO2
GPIO5 // SDA
RSVD
P04
M03
INTD
N04
P05
M04
GPIO3
GPIO6
RSVD
RSVD
N05
P06
M05
N06
P07
RSVD
M06
N07
RSVD
P08
RSVD
M07
N08
RSVD
P09
RSVD
M08
V
V
V
V
N09
RSVD
P10
RSVD
SS
M09
N10
RSVD
P11
RSVD
DD_33
DD_33
DD_33
M10
N11
RSVD
P12
RSVD
M11
N12
V
V
P13
V
DD_15
SSA
RSVD
M12
RSVD
RSVD
RSVD
N13
P14
SS
M13
N14
RSVD
PRST
M14
P01
10
SCPS155C
April 2007 Revised October 2008
Introduction
A
B
C
D
E
F
G
H
J
K
L
M
N
P
REFCLK+
RSVD
VSSA
REFCLK–
RXN
VDD_15
TXP
PERST
VDD_33_AUX REF0_PCIE
WAKE
PME
RSVD
RSVD
14
14
13
12
VDD_15_
GNT5
GNT4
CLKRUN_EN VDDA_33
VDDA_15
RSVD
RXP
VSSA
VSS
VSSA
VSSA
TXN
VSSA
VSSA
VDDA_15
REF1_PCIE
COMB
GRST
RSVD
VSS
VDD_15
RSVD
13
VDD_33_
COM_IO
VDD_33_
COMB
RSVD
VSSA
VDD_33
REQ5
REQ4
EXT_ARB_EN
RSVD
RSVD
RSVD
12
VSSA
VSS
VDDA_15
RSVD
RSVD
CLKOUT4
GNT2
CLKOUT6 REFCLK_SEL
VDDA_15
VDDA_33
11
11
RSVD
RSVD
RSVD
CLKOUT5
REQ3
VDD_33
CLKOUT3
VDD_15
VDD_33
VDD_33
VDD_33
10
9
10
GNT3
REQ2
VSS
CLKOUT2
CLKOUT1
AD0
VDD_33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD
9
8
7
6
5
4
3
2
1
GNT1
RSVD
RSVD
RSVD
REQ1
REQ0
AD2
VSS
8
RSVD
RSVD
GNT0
AD3
CLKOUT0
VSS
VDD_33
VDD_33
RSVD
7
GPIO7
RSVD
GPIO6
GPIO2
RSVD
VSS
AD1
AD4
AD7
AD9
AD11
VDD_33
AD8
6
VDD_15
GPIO5 // SDA
RSVD
AD5
AD6
5
GPIO0
/CLKRUN
AD22
C/BE(1)
VDD_33
CLK
VCCP
AD24
AD28
C/BE(0)
VDD_33
VDD_15
GPIO3
SERIRQ
INTC
GPIO4/SCL
VDD_33
4
GPIO1/
PWR_OVER
INTD
INTA
AD29
AD25
AD10
AD12
AD14
AD15
AD20
AD21
SERR
IRDY
PAR
TRDY
AD17
3
VCCP
C/BE(3)
AD27
AD30
LOCK
STOP
C/BE(2)
2
PRST
AD26
M66EN
AD13
FRAME
AD18
PERR
DEVSEL
AD19
AD23
AD31
INTB
AD16
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 2−3. XIO2000A/XIO2000AI ZHC Microstar BGA Package (Bottom View)
11
April 2007 Revised October 2008
SCPS155C
Introduction
Table 2−3. ZHC Terminal Names Sorted Alphanumerically
BGA BALL #
SIGNAL NAME
AD11
BGA BALL #
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
E01
E02
E03
E04
E11
SIGNAL NAME
VDD_33
BGA BALL #
H02
H03
H04
H06
H07
H08
H09
H11
H12
H13
H14
J01
SIGNAL NAME
AD21
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
D01
D02
D03
AD9
AD8
AD20
AD7
VDD_33
CLKOUT0
VDD_15
CLKOUT3
VDD_33
REFCLK_SEL
RSVD
VDDA_15
RSVD
FRAME
IRDY
AD22
AD4
VSS
AD1
VSS
AD0
VSS
CLKOUT1
CLKOUT2
GNT2
VSS
VDDA_15
VDD_33_COMB
VDDA_15
PERST
AD23
CLKOUT4
GNT4
GNT5
VSSA
J02
C/BE(3)
AD25
AD13
SERR
C/BE[1]
VDDA_15
VSSA
J03
AD12
J04
AD24
AD10
J06
VDD_33
VDD_33
VSS
VCCP
E12
E13
E14
F01
J07
AD5
RXP
J08
AD2
RXN
J09
VSS
REQ0
AD16
J11
VDDA_33
VDD_33_COMB_IO
REF1_PCIE
VDD_33_AUX
AD26
REQ1
F02
C/BE[2]
TRDY
VDD_33
VSS
J12
REQ2
F03
J13
GNT3
F04
J14
REQ4
F06
K01
K02
K03
K04
K11
K12
K13
K14
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
REQ5
F07
VSS
AD27
CLKRUN_EN
REFCLK−
PERR
F08
VSS
AD29
F09
VDD_33
VSSA
AD28
F11
VSSA
AD15
F12
VSSA
RSVD
AD14
F13
VSS
VDD_15_COMB
REF0_PCIE
AD31
C/BE[0]
AD6
F14
VDD_15
AD18
G01
G02
G03
G04
G06
G07
G08
G09
G11
G12
G13
G14
H01
AD3
VCCP
AD17
AD30
GNT0
CLK
GNT1
VDD_15
VSS
VDD_33
VDD_15
GPIO7
REQ3
CLKOUT5
CLKOUT6
EXT_ARB_EN
VDDA_33
REFCLK+
DEVSEL
STOP
VSS
VSS
RSVD
VSS
VDD_33
VDD_33
VDD_33
VSSA
VSSA
VSSA
TXN
TXP
L12
L13
RSVD
PAR
AD19
GRST
12
SCPS155C
April 2007 Revised October 2008
Introduction
Figure 2−3. ZHC Terminal Names Sorted Alphanumarically (Continued)
BGA BALL #
L14
SIGNAL NAME
WAKE
BGA BALL #
N01
SIGNAL NAME
INTB
BGA BALL #
P02
SIGNAL NAME
LOCK
M01
M66EN
INTA
N02
INTC
P03
GPIO1 // PWR_OVER
GPIO4 // SCL
RSVD
M02
N03
SERIRQ
GPIO3
GPIO5 // SDA
RSVD
P04
M03
INTD
N04
P05
M04
GPIO0 // CLKRUN
GPIO2
GPIO6
RSVD
VSS
N05
P06
RSVD
M05
N06
P07
RSVD
M06
N07
RSVD
P08
RSVD
M07
N08
RSVD
P09
RSVD
M08
N09
RSVD
P10
RSVD
M09
VSS
N10
RSVD
P11
VSS
M10
RSVD
RSVD
VSS
N11
RSVD
P12
VDD_33
RSVD
M11
N12
RSVD
P13
M12
N13
VDD_15
RSVD
P14
RSVD
M13
RSVD
PME
N14
M14
P01
PRST
13
April 2007 Revised October 2008
SCPS155C
Introduction
Table 2−4. XIO2000A/XIO2000AI Signal Names Sorted Alphabetically
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
SIGNAL NAME
AD0
SIGNAL NAME
CLKOUT5
A07
B07
C07
D07
A06
B06
A05
B05
C04
A03
B03
A02
B01
C02
C01
D02
H03
H02
J03
A07
A06
B06
C06
A05
B05
C05
A04
D05
A03
B03
A02
B02
B01
C03
C02
F01
G03
G01
H01
H03
H02
H04
J01
J04
J03
K01
K02
K04
K03
L02
L01
C04
E04
F02
J02
L03
D07
A08
A09
D09
A11
A07
D06
A06
C06
B06
A05
B05
C05
C04
A03
B03
A02
B02
B01
C03
C02
F03
G02
G03
H01
H03
H02
H04
J01
A13
B14
B15
F01
A15
G01
A08
A09
A10
C11
C12
A14
T05
U05
T06
U06
R07
T07
U07
U08
N17
R02
T01
U02
T03
G02
U04
R01
E02
F03
J17
C10
C11
B13
D01
C12
E01
C07
C08
A10
B10
A12
A13
M04
P03
M05
N04
P04
N05
M06
L06
L13
M02
N01
N02
M03
E02
P02
M01
D03
C01
H14
M14
P01
K14
J13
B11
A13
B13
E02
B12
F01
C07
C08
B09
C10
D11
C11
P03
P04
N04
M04
P05
N05
M05
L06
L13
M02
N01
N02
M03
E04
P02
M01
D02
D03
H12
L12
P01
J14
AD1
CLKOUT6
CLKRUN_EN
DEVSEL
EXT_ARB_EN
FRAME
GNT0
AD2
AD3
AD4
AD5
AD6
AD7
GNT1
AD8
GNT2
AD9
GNT3
AD10
GNT4
AD11
GNT5
AD12
GPIO0 // CLKRUN
GPIO1 // PWR_OVRD
GPIO2
AD13
AD14
AD15
GPIO3
AD16
GPIO4 // SCL
GPIO5 // SDA
GPIO6
AD17
AD18
AD19
J02
GPIO7
AD20
K01
K02
K03
L01
L03
L04
M01
M02
N01
N02
P01
P02
B04
D01
H01
L02
P03
C08
B09
B10
A11
A12
GRST
AD21
INTA
AD22
INTB
AD23
INTC
AD24
J03
INTD
AD25
J04
IRDY
AD26
K01
K02
K03
L04
L02
L01
B04
C01
F02
J02
LOCK
AD27
M66EN
AD28
PAR
AD29
PERR
AD30
PERST
AD31
PME
M15
U03
L16
L17
A16
C16
C17
B08
C09
C10
B11
C/BE[0]
C/BE[1]
C/BE[2]
C/BE[3]
CLK
PRST
REF0_PCIE
REF1_PCIE
REFCLK_SEL
REFCLK−
REFCLK+
REQ0
J13
D11
B14
C14
B07
B08
B09
C09
A14
C14
C13
B07
A08
C09
A10
L03
D07
B08
A09
D10
B10
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
REQ1
REQ2
REQ3
14
SCPS155C
April 2007 Revised October 2008
Introduction
Table 2−4. XIO2000A/XIO2000AI Signal Names Sorted Alphabetically (Continued)
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
SIGNAL NAME
REQ4
SIGNAL NAME
B12
B13
D16
D17
N15
N16
P16
P17
R08
R09
R16
T08
T09
T10
T11
T12
T14
T15
T17
U09
U10
U11
U12
U13
U14
U15
U16
E16
E17
T04
E01
F02
G03
H16
H17
A04
J01
B11
B12
D12
D14
K12
L07
L12
M07
M10
M11
M13
N06
N07
N08
N09
N10
N11
N12
N14
P05
P06
P07
P08
P09
P10
P13
P14
E14
E13
N03
E03
D02
F03
G13
G14
B04
G02
D08
F14
G04
L05
N13
A11
A12
D13
D14
L07
L10
L14
M14
M06
P07
N14
M12
M07
M13
N06
N08
N09
N10
N11
P06
N07
P08
P09
P10
P11
P12
P14
E13
E14
N03
D01
E03
E01
G13
G14
A04
G01
D08
F14
G04
L05
N12
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
M17
C06
C13
D10
E03
H04
M03
P09
P10
P11
R05
R14
T13
K14
K16
L14
F17
G15
J14
K13
D04
D06
D10
F04
F09
J06
J07
L04
L08
L09
L10
P12
J14
H12
J12
D13
E11
H11
H13
C13
J11
K13
D04
D05
D09
F04
F09
J06
J07
K04
L08
M09
M10
M11
J12
H14
K12
E11
F12
H11
H13
C12
J11
DD_15_COMB
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33_AUX
DD_33_COMB
DD_33_COMBIO
DDA_15
DDA_15
DDA_15
DDA_15
DDA_33
DDA_33
SS
REQ5
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXN
J15
D15
K15
C05
C14
D03
D08
D11
G04
G17
K04
K17
N03
P08
R04
R06
R10
R11
R12
R13
R17
G07
G08
F06
F07
F08
F13
G06
G07
G08
G09
H06
H07
H08
H09
J08
J09
M08
M09
M12
P11
F06
F07
F08
F13
G06
G07
G08
G09
H06
H07
H08
H09
J08
J09
L09
L11
SS
SS
SS
SS
SS
RXP
SS
SERIRQ
SERR
STOP
TRDY
TXN
SS
SS
SS
SS
SS
TXP
SS
V
V
V
V
V
V
V
CCP
SS
CCP
SS
D09
H14
J04
DD_15
DD_15
DD_15
DD_15
DD_15
SS
M08
N13
SS
SS
P07
P15
SS
SS
15
April 2007 Revised October 2008
SCPS155C
Introduction
Table 2−4. XIO2000A/XIO2000AI Signal Names Sorted Alphabetically (Continued)
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
SIGNAL NAME
SIGNAL NAME
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
G09
G10
G11
H07
H08
H09
H10
H11
J07
J08
J09
J10
J11
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
K11
L07
L08
L09
L10
L11
B17
E15
F15
F16
G14
G16
H15
J16
L15
M16
SS
SS
SS
SS
SS
SS
A14
E12
F11
F12
G11
G12
K11
L11
B14
D12
E12
F11
G11
G12
K11
P13
SSA
SSA
SSA
SSA
SSA
SSA
SSA
SSA
SSA
K07
K08
K09
K10
WAKE
L14
K14
2.8 Terminal Descriptions
Table 2−5 through Table 2−12 give a description of the terminals. These terminals are grouped in tables by
functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.
The following list describes the different input/output cell types that appear in the terminal description tables:
•
•
•
•
•
•
HS DIFF IN = High speed differential input.
HS DIFF OUT = High speed differential output.
PCI BUS = PCI bus 3-state bidirectional buffer with 3.3-V or 5.0-V clamp rail.
LV CMOS = 3.3-V low voltage CMOS input or output with 3.3-V clamp rail.
BIAS = Input/output terminals that generate a bias voltage to determine a driver’s operating current.
Feed through = these terminals connect directly to macros within the part and not through an input or
output cell.
•
•
PWR = Power terminal
GND = Ground terminal
16
SCPS155C
April 2007 Revised October 2008
Introduction
Table 2−5. Power Supply Terminals
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
I/O
TYPE
EXTERNAL
PARTS
SIGNAL
DESCRIPTION
5.0-V or 3.3-V PCI bus clamp voltage
to set maximum I/O voltage tolerance
of the secondary PCI bus signals
Bypass
capacitors
V
CCP
A04, J01
B04, G02
A04, G01
PWR
D09, H14, J04,
P07, P15
D08, F14, G04,
L05, N13
D08, F14, G04,
L05, N12
Bypass
capacitors
V
V
PWR
PWR
1.5-V digital core power terminals
1.5-V analog power terminal
DD_15
F17, J14, J15,
G15
D13, E11, H11,
H13
E11, F12, H11,
H13
Pi filter
DDA_15
C06, C13, D10,
E03, H04, M03,
P09, P10, P11,
R05, R14, T13
D04, D06, D10,
F04, F09, J06,
J07, L04, L08,
L09, L10, P12
D04, D05, D09,
F04, F09, J06,
J07, K04, L08,
M09, M10, M11
Bypass
capacitors
V
PWR
3.3-V digital I/O power terminals
DD_33
3.3-V auxiliary power terminal
Bypass
capacitors
Note: This terminal is connected to
V
K14
J14
J12
PWR
PWR
DD_33_AUX
V
through a pulldown resistor if no
SS
auxiliary supply is present.
V
D15, K15
C13, J11
C12, J11
Pi filter
3.3-V analog power terminal
DDA_33
Table 2−6. Ground Terminals
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
I/O
TYPE
SIGNAL
DESCRIPTION
C05, C14, D03, D08, D11, F06, F07, F08, F13, G06,
F06, F07, F08, F13, G06,
G04, G17, K04, K17, N03, G07, G08, G09, H06, H07, G07, G08, G09, H06, H07,
V
SS
GND
Digital ground terminals
P08, R04, R06, R10, R11, H08, H09, J08, J09, M08,
H08, H09, J08, J09, L09,
L11, M08, N13
R12, R13, R17
M09, M12, P11
G07, G08, G09, G10, G11,
H07, H08, H09, H10, H11,
J07, J08, J09, J10, J11,
K07, K08, K09, K10, K11,
L07, L08, L09, L10, L11
Ground terminals for
thermally-enhanced
package
V
V
GND
GND
SS
B17, E15, F15, F16, G14,
G16, H15, J16, L15
A14, E12, F11, F12, G11,
G12, K11, L11
B14, D12, E12, F11, G11,
G12, K11, P13
Analog ground terminal
SSA
Table 2−7. Combined Power Outputs
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
I/O
TYPE
EXTERNAL
PARTS
SIGNAL
DESCRIPTION
Internally-combined 1.5-V main and V
power output for
AUX
external bypass capacitor filtering. Supplies all internal
1.5-V circuitry powered by V
Feed
through
Bypass
capacitors
.
V
V
V
M17
K16
L14
K13
H12
J12
K13
H14
K12
AUX
DD_15_COMB
Caution: Do not use this terminal to supply external power
to other devices.
Internally-combined 3.3-V main and V
AUX
power output for
external bypass capacitor filtering. Supplies all internal
3.3-V circuitry powered by V
Feed
through
Bypass
capacitors
.
AUX
DD_33_COMB
Caution: Do not use this terminal to supply external power
to other devices.
Internally-combined 3.3-V main and V
AUX
power output for
external bypass capacitor filtering. Supplies all internal
3.3-V input/output circuitry powered by V
Feed
through
Bypass
capacitors
.
AUX
DD_33_COMBIO
Caution: Do not use this terminal to supply external power
to other devices.
17
April 2007 Revised October 2008
SCPS155C
Introduction
SIGNAL
Table 2−8. PCI Express Terminals
GZZ/
ZZZ
BALL #
ZHC
ZHH
I/O
CELL
TYPE
CLAMP
RAIL
EXTERNAL
PARTS
DESCRIPTION
BALL # BALL #
TYPE
PCI Express reset input. The PERST
signal identifies when the system power is
stable and generates an internal power on
reset.
LV
CMOS
V
DD_33_
COMBIO
PERST
J17
H14
H12
I
−
Note: The PERST input buffer has
hysteresis.
External reference resistor + and −
terminals for setting TX driver current. An
external resistor is connected between
terminals L16 and L17.
REF0_PCIE
REF1_PCIE
L16
L17
K14
J13
J14
J13
External
resistor
I/O
BIAS
−
High-speed receive pair. RXP and RXN
comprise the differential receive pair for the
single PCI Express lane supported.
RXP
RXN
E17
E16
E13
E14
E14
E13
HS
DIFF IN
DI
V
SS
−
HS
DIFF
OUT
High-speed transmit pair. TXP and TXN
comprise the differential transmit pair for
the single PCI Express lane supported.
TXP
TXN
H17
H16
G14
G13
G14
G13
Series
capacitors
DO
V
DD_15
Wake is an active low signal that is driven
low to reactivate the PCI Express link
hierarchy’s main power rails and reference
clocks.
LV
CMOS
V
DD_33_
COMBIO
WAKE
M16
L14
K14
O
−
Note: Since WAKE is an open-drain output
buffer, a system side pullup resistor is
required.
18
SCPS155C
April 2007 Revised October 2008
Introduction
Table 2−9. Clock Terminals
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
I/O
TYPE
CELL
TYPE
CLAMP EXTERNAL
SIGNAL
DESCRIPTION
RAIL
PARTS
Reference clock select. This
terminal selects the reference
clock input.
Pullup or
pulldown
resistor
LV
CMOS
0 = 100-MHz differential
common reference clock
used.
REFCLK_SEL
A16
D11
C14
A14
I
V
DD_33
1 = 125-MHz single-ended,
reference clock used.
Reference clock. REFCLK+ and
REFCLK− comprise the
differential input pair for the
100-MHz system reference
clock. For a single-ended,
125-MHz system reference
clock, use the REFCLK+ input.
HS
DIFF
IN
REFCLK+
C17
C13
DI
DI
V
−
DD_33
DD_33
Reference clock. REFCLK+ and
REFCLK− comprise the
differential input pair for the
100-MHz system reference
clock. For a single-ended,
125-MHz system reference
clock, attach a capacitor from
Capacitor to
HS
DIFF
IN
V
SS
for
REFCLK−
CLK
C16
P03
B14
L03
C14
L03
V
single-ended
mode
REFCLK− to V
.
SS
PCI
Bus
PCI clock input. This is the clock
input to the PCI bus core.
I
V
−
−
CCP
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLKOUT6
C08
B09
B10
A11
A12
A13
B14
D07
A08
A09
D09
A11
C10
C11
D07
B08
A09
D10
B10
B11
A13
PCI clock outputs. These clock
outputs are used to clock the
PCI bus. If the bridge PCI bus
clock outputs are used, then
CLKOUT6 must be connected to
the CLK input.
PCI
Bus
O
V
CCP
19
April 2007 Revised October 2008
SCPS155C
Introduction
Table 2−10. PCI System Terminals
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
I/O
CELL
TYPE
CLAMP EXTERNAL
SIGNAL
DESCRIPTION
PARTS
TYPE
RAIL
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
P02
P01
N02
N01
M02
M01
L04
L03
L01
K03
K02
K01
J02
L01
L02
K03
K04
K02
K01
J03
L01
L02
L04
K03
K02
K01
J04
J04
J01
J03
J01
H04
H02
H03
H01
G01
G03
F01
C02
C03
B01
B02
A02
B03
A03
D05
A04
C05
B05
A05
C06
B06
A06
A07
H04
H02
H03
H01
G03
G02
F03
C02
C03
B01
B02
A02
B03
A03
C04
C05
B05
A05
B06
C06
A06
D06
A07
J03
H02
H03
D02
C01
C02
B01
A02
B03
A03
C04
B05
A05
B06
A06
D07
C07
B07
A07
PCI
Bus
I/O
V
CCP
−
PCI address data lines
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE[3]
C/BE[2]
C/BE[1]
C/BE[0]
L02
H01
D01
B04
J02
F02
E04
C04
J02
F02
C01
B04
PCI
Bus
I/O
V
CCP
−
PCI command byte enables
Pullup
PCI
Bus
DEVSEL
FRAME
F01
G01
D01
E01
E02
F01
I/O
I/O
V
V
resistor per PCI device select
PCI spec
CCP
Pullup
resistor per PCI frame
PCI spec
PCI
Bus
CCP
PCI grant outputs. These signals
GNT5
GNT4
GNT3
GNT2
GNT1
GNT0
A14
C12
C11
A10
A09
A08
A13
A12
B10
A10
C08
C07
C11
D11
C10
B09
C08
C07
are used for arbitration when the
PCI bus is the secondary bus and
an external arbiter is not used.
GNT0 is used as the REQ for the
bridge when an external arbiter is
used.
PCI
Bus
O
V
CCP
−
INTA
INTB
INTC
INTD
R02
T01
U02
T03
M02
N01
N02
M03
M02
N01
N02
M03
Pullup
PCI interrupts A−D. These signals
PCI
Bus
I
V
V
resistor per are interrupt inputs to the bridge on
PCI spec
CCP
the secondary PCI bus.
Pullup
PCI
Bus
IRDY
G02
E02
E04
I/O
resistor per PCI initiator ready
PCI spec
CCP
20
SCPS155C
April 2007 Revised October 2008
Introduction
Table 2−10. PCI System Terminals (Continued)
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
I/O
CELL
TYPE
CLAMP
RAIL
EXTERNAL
PARTS
SIGNAL
DESCRIPTION
TYPE
PCI
Bus
PAR
E02
F03
D03
C01
D02
D03
I/O
I/O
V
−
PCI bus parity
CCP
CCP
Pullup
PCI
Bus
PERR
V
resistor per PCI parity error
PCI spec
PCI power management event. This
terminal may be used to detect PME
events from a PCI device on the
secondary bus.
Pullup
resistor per
PCI spec
LV
CMOS
V
DD_33_
COMBIO
PME
M15
M14
L12
I
I
Note: The PME input buffer has
hysteresis.
REQ5
REQ4
REQ3
REQ2
REQ1
REQ0
B13
B12
B11
C10
C09
B08
B12
B11
C09
B09
B08
B07
A12
A11
A10
C09
A08
B07
PCI request inputs. These signals are
used for arbitration on the secondary PCI
bus when an external arbiter is not used.
REQ0 is used as the GNT for the bridge
when an external arbiter is used.
If unused, a
weak pullup
resistor per
PCI spec
PCI
Bus
V
CCP
PCI
Bus
PCI reset. This terminal is an output to
the secondary PCI bus.
PRST
SERR
U03
E01
P01
E03
P01
D01
O
V
V
−
CCP
Pullup
PCI
Bus
I/O
resistor per PCI system error
PCI spec
CCP
Pullup
resistor per PCI stop
PCI spec
PCI
Bus
STOP
TRDY
F02
G03
D02
F03
E03
E01
I/O
I/O
V
V
CCP
Pullup
PCI
Bus
resistor per PCI target ready
PCI spec
CCP
Table 2−11. Reserved Terminals
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
I/O
TYPE
SIGNAL
DESCRIPTION
N15, N16,
P16, R08,
T08, T10, T11,
T12, T14,
T15, T17,
U09, U11,
U12, U13,
U14, U15,
U16
K12, L07, L12, L07, L10, L14,
M10, M11,
M13, N06,
N08, N09,
N10, N11,
P05, P06,
P08, P09,
M06, M12,
M13, N06,
N08, N09,
N10, N11,
P06, P08,
P09, P10,
RSVD
O
Reserved, do not connect to external signals.
P10, P13, P14 P11, P12, P14
RSVD
RSVD
R16
N12
N14
I
I
Must be connected to V
.
DD_33
D16, D17,
P17, R09,
T09, U10
D12, D14,
M07, N07,
N14, P07
D13, D14,
M14, P07,
M07, N07
Must be connected to V
.
SS
21
April 2007 Revised October 2008
SCPS155C
Introduction
Table 2−12. Miscellaneous Terminals
GZZ/
ZZZ
BALL
ZHC
ZHH
I/O
CELL CLAMP EXTERNAL
SIGNAL
DESCRIPTION
BALL BALL TYPE TYPE
RAIL
PARTS
Clock run enable
Optional
pullup
resistor
0 = Clock run support disabled
1 = Clock run support enabled
LV
CMOS
CLKRUN_EN
B15
A15
B13
C12
B13
B12
I
I
V
DD_33
Note: The CLKRUN_EN input buffer has an internal
active pulldown.
External arbiter enable
Optional
pullup
resistor
0 = Internal arbiter enabled
1 = External arbiter enabled
LV
CMOS
EXT_ARB_EN
V
DD_33
Note: The EXT_ARB_EN input buffer has an internal
active pulldown.
General-purpose I/O 0/clock run. This terminal
functions as a GPIO controlled by bit 0 (GPIO0_DIR)
in the GPIO control register (see Section 4.59) or the
clock run terminal. This terminal is used as clock run
input when the bridge is placed in clock run mode.
Optional
pullup
resistor
GPIO0 //
CLKRUN
LV
CMOS
T05
M04
P03
I/O
V
DD_33
Note: In clock run mode, an external pullup resistor
is required to prevent the CLKRUN signal from
floating.
Note: This terminal has an internal active pullup
resistor.
General-purpose I/O 1/power override. This terminal
functions as a GPIO controlled by bit 1 (GPIO1_DIR)
in the GPIO control register (see Section 4.59) or the
power override output terminal. GPIO1 becomes
PWR_OVRD when bits 22:20 (POWER_OVRD) in
the general control register are set to 001b or 011b
(see Section 4.65).
GPIO1 //
PWR_OVRD
LV
CMOS
U05
P03
P04
I/O
V
−
DD_33
Note: This terminal has an internal active pullup
resistor.
General-purpose I/O 2. This terminal functions as a
GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO
control register (see Section 4.59).
LV
CMOS
Note: When PERST is deasserted, this terminal must
be a 1b to enable the PCI Express 1.0a compatibility
mode.
GPIO2
T06
U06
R07
M05
N04
P04
N04
M04
P05
I/O
I/O
I/O
V
−
−
DD_33
Note: This terminal has an internal active pullup
resistor.
General-purpose I/O 3. This terminal functions as a
GPIO controlled by bit 3 (GPIO3_DIR) in the GPIO
control register (see Section 4.59).
LV
CMOS
GPIO3
V
DD_33
Note: This terminal has an internal active pullup
resistor.
GPIO4 or serial-bus clock. This terminal functions as
serial-bus clock if a pullup resistor is detected on
SDA. If a pulldown resistor is detected on SDA, this
terminal functions as GPIO4.
Optional
pullup
resistor
LV
CMOS
GPIO4 // SCL
V
DD_33
Note: In serial-bus mode, an external pullup resistor
is required to prevent the SCL signal from floating.
Note: This terminal has an internal active pullup
resistor.
22
SCPS155C
April 2007 Revised October 2008
Introduction
Table 2−12. Miscellaneous Terminals (Continued)
GZZ
ZZZ
BALL
ZHC
BALL
ZHH
BALL
I/O
TYPE
CELL
TYPE
CLAMP
RAIL
EXTERNAL
PARTS
SIGNAL
DESCRIPTION
GPIO5 or serial-bus data. This terminal
functions as serial-bus data if a pullup
resistor is detected on SDA. If a pulldown
resistor is detected on SDA, this terminal
functions as GPIO5.
Pullup or
Pulldown
resistor
GPIO5 //
SDA
LV
CMOS
T07
U07
N05
M06
N05
M05
I/O
I/O
V
DD_33
Note: In serial-bus mode, an external
pullup resistor is required to prevent the
SDA signal from floating.
General-purpose I/O 6. This terminal
functions as a GPIO controlled by bit 6
(GPIO6_DIR) in the GPIO control register
(see Section 4.59).
LV
CMOS
GPIO6
V
V
−
DD_33
Note: This terminal has an internal active
pullup resistor.
General-purpose I/O 7. This terminal
functions as a GPIO controlled by bit 7
(GPIO7_DIR) in the GPIO control register
(see Section 4.59).
LV
CMOS
GPIO7
GRST
LOCK
U08
N17
U04
L06
L13
P02
L06
L13
P02
I/O
−
−
DD_33
Note: This terminal has an internal active
pullup resistor.
Global reset input. Asynchronously resets
all logic in device, including sticky bits and
power management state machines.
LV
CMOS
V
DD_33_
COMBIO
I
Note: The GRST input buffer has both
hysteresis and an internal active pullup.
This terminal functions as PCI LOCK when
bit 12 (LOCK_EN) is set in the general
control register (see Section 4.65).
Pullup
resistor per
PCI spec
PCI
Bus
I/O
V
CCP
Note: In lock mode, an external pullup
resistor is required to prevent the LOCK
signal from floating.
66-MHz mode enable
0 = Secondary PCI bus and clock outputs
operate at 33 MHz
1 = Secondary PCI bus and clock outputs
operate at 66 MHz
Pullup
resistor per
PCI spec
PCI
Bus
Note: If the PCI bus clock is always 33
MHz, then this terminal is connected to
M66EN
R01
M01
M01
I
V
CCP
V
SS
.
Note: The XIO2000AI industrial
temperature device does not support 66
MHz operation so for the XIO2000AI, this
pin must be grounded for proper operation.
Serial IRQ interface. This terminal
functions as a serial IRQ interface if a
pullup is detected when PERST is
deasserted. If a pulldown is detected, then
the serial IRQ interface is disabled.
Pullup or
pulldown
resistor
PCI
Bus
SERIRQ
T04
N03
N03
I/O
V
CCP
23
April 2007 Revised October 2008
SCPS155C
Feature/Protocol Descriptions
3
Feature/Protocol Descriptions
This chapter provides a high-level overview of all significant device features. Figure 3−1 shows a simplified
block diagram of the basic architecture of the PCI-Express to PCI Bridge. The top of the diagram is the PCI
Express interface and the PCI bus interface is located at the bottom of the diagram.
PCI Express
Transmitter
PCI Express
Receiver
Power
Mgmt
GPIO
Serial
Configuration and
Memory Register
Clock
EEPROM
Generator
Reset
Serial IRQ
Controller
PCI Bus Interface
Figure 3−1. XIO2000A Block Diagram
3.1 Power-Up/-Down Sequencing
The bridge contains both 1.5-V and 3.3-V power terminals. In addition, a V
supply exists to support the
AUX
D3
state. The clamping voltage (V
) can be either 3.3-V or 5.0-V, depending on the PCI bus interface
CCP
cold
requirements. The following power-up and power-down sequences describe how power is applied to these
terminals.
In addition, the bridge has three resets: PERST, GRST, and an internal power-on reset. These resets are fully
described in Section 3.2. The following power-up and power-down sequences describe how PERST is applied
to the bridge.
The application of the PCI Express reference clock (REFCLK) is important to the power-up/-down sequence
and is included in the following power-up and power-down descriptions.
3.1.1 Power-Up Sequence
1. Assert PERST to the device.
2. Apply 1.5-V and 3.3-V voltages.
3. Apply V
clamp voltage.
CCP
4. Apply a stable PCI Express reference clock.
5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two
delay requirements are satisfied:
−
Wait a minimum of 100 µs after applying a stable PCI Express reference clock. The 100-µs limit
satisfies the requirement for stable device clocks by the deassertion of PERST.
−
Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable
power by the deassertion of PERST.
24
SCPS155C
April 2007 Revised October 2008
Feature/Protocol Descriptions
See the power-up sequencing diagram in Figure 3−2.
V and
DD_15
V
DDA_15
V
V
and
DD_33
DDA_33
V
CCP
REFCLK
PERST
100 µs
100 ms
Figure 3−2. Power-Up Sequence
3.1.2 Power-Down Sequence
1. Assert PERST to the device.
2. Remove the reference clock.
3. Remove V
clamp voltage.
CCP
4. Remove 3.3-V and 1.5-V voltages.
Please see the power-down sequencing diagram in Figure 3−3. If the V
terminal is to remain
DD_33_AUX
powered after a system shutdown, then the bridge power-down sequence is exactly the same as shown in
Figure 3−3.
25
April 2007 Revised October 2008
SCPS155C
Feature/Protocol Descriptions
V and
DD_15
V
DDA_15
V
V
and
DD_33
DDA_33
V
CCP
REFCLK
PERST
Figure 3−3. Power-Down Sequence
3.2 Bridge Reset Features
There are five bridge reset options that include internally-generated power-on reset, resets generated by
asserting input terminals, and software-initiated resets that are controlled by sending a PCI Express hot reset
or setting a configuration register bit. Table 3−1 identifies these reset sources and describes how the bridge
responds to each reset.
26
SCPS155C
April 2007 Revised October 2008
Feature/Protocol Descriptions
Table 3−1. Bridge Reset Options
RESET OPTION
XIO2000A FEATURE
RESET RESPONSE
Bridge
internally-generated
power-on reset
During a power-on cycle, the bridge asserts an internal When the internal power-on reset is asserted, all
reset and monitors the V (M17) terminal. control registers, state machines, sticky register bits,
DD_15_COMB
When this terminal reaches 90% of the nominal input
voltage specification, power is considered stable. After
stable power, the bridge monitors the PCI Express
reference clock (REFCLK) and waits 10 µs after active
clocks are detected. Then, internal power-on reset is
deasserted.
and power management state machines are initialized
to their default state.
In addition, the bridge asserts PCI bus reset (PRST).
Global reset input
GRST (N17)
When GRST is asserted low, an internal power-on
reset occurs. This reset is asynchronous and functions machines, sticky register bits, and power management
When GRST is asserted low, all control registers, state
during both normal power states and V
states.
power
state machines are initialized to their default state.
AUX
In addition, the bridge asserts PCI bus reset (PRST).
When the rising edge of GRST occurs, the bridge
samples the state of all static control inputs and latches
the information internally. If an external serial EEPROM
is detected, then a download cycle is initiated. Also, the
process to configure and initialize the PCI Express link
is started. The bridge starts link training within 80 ms
after GRST is deasserted.
PCI Express reset input This bridge input terminal is used by an upstream PCI
When PERST is asserted low, all control register bits
PERST (J17)
Express device to generate a PCI Express reset and to that are not sticky are reset. Within the configuration
k
signal a system power good condition.
register maps, the sticky bits are indicated by the
symbol. Also, all state machines that are not
When PERST is asserted low, the bridge generates an
internal PCI Express reset as defined in the PCI
Express specification.
associated with sticky functionality or V
management are reset.
power
AUX
In addition, the bridge asserts PCI bus reset (PRST).
When PERST transitions from low to high, a system
power good condition is assumed by the bridge.
When the rising edge of PERST occurs, the bridge
samples the state of all static control inputs and latches
the information internally. If an external serial EEPROM
is detected, then a download cycle is initiated. Also, the
process to configure and initialize the PCI Express link
is started. The bridge starts link training within 80 ms
after PERST is deasserted.
Note: The system must assert PERST before power is
removed, before REFCLK is removed, or before
REFCLK becomes unstable.
PCI Express training
control hot reset
The bridge responds to a training control hot reset
received on the PCI Express interface. After a training
control hot reset, the PCI Express interface enters the
DL_DOWN state.
In the DL_DOWN state, all remaining configuration
register bits and state machines are reset. All
remaining bits exclude sticky bits and EEPROM
loadable bits. All remaining state machines exclude
sticky functionality, EEPROM functionality, and V
power management.
AUX
Within the configuration register maps, the sticky bits
k
are indicated by the symbol and the EEPROM
loadable bits are indicated by the † symbol.
In addition, the bridge asserts PCI bus reset (PRST).
PCI bus reset
PRST (U03)
System software has the ability to assert and deassert
the PRST terminal on the secondary PCI bus interface. offset 3Eh (see Section 4.29) is asserted, the bridge
When bit 6 (SRST) in the bridge control register at
This terminal is the PCI bus reset.
asserts the PRST terminal. A 0 in the SRST bit
deasserts the PRST terminal.
3.3 PCI Express Interface
3.3.1 External Reference Clock
The bridge requires either a differential, 100-MHz common clock reference or a single-ended, 125-MHz clock
reference. The selected clock reference must meet all PCI Express Electrical Specification requirements for
frequency tolerance, spread spectrum clocking, and signal electrical characteristics.
27
April 2007 Revised October 2008
SCPS155C
Feature/Protocol Descriptions
If the REFCLK_SEL (A16) input is connected to V , then a differential, 100-MHz common clock reference
SS
is expected by the bridge. If the A16 terminal is connected to V
reference is expected by the bridge.
, then a single-ended, 125-MHz clock
DD_33
When the single-ended, 125-MHz clock reference option is enabled, the single-ended clock signal is
connected to the REFCLK+ (C17) terminal. The REFCLK− (C16) terminal is connected to one side of an
external capacitor with the other side of the capacitor connected to V
.
SS
When using a single-ended reference clock, care must be taken to ensure interoperability from a system jitter
standpoint. The PCI Express Base Specification does not ensure interoperability when using a differential
reference clock commonly used in PC applications along with a single-ended clock in a noncommon clock
architecture. System jitter budgets will have to be verified to ensure interoperability. See the PCI Express Jitter
and BER White Paper from the PCI-SIG.
3.3.2 Beacon
The bridge supports the PCI Express in-band beacon feature. Beacon is driven on the upstream PCI Express
link by the bridge to request the reapplication of main power when in the L2 link state. To enable the beacon
feature, bit 10 (BEACON_ENABLE) in the general control register at offset D4h is asserted. See Section 4.65,
General Control Register, for details.
If the bridge is in the L2 link state and beacon is enabled, when a secondary PCI bus device asserts PME,
then the bridge outputs the beacon signal on the upstream PCI Express link. The beacon signal frequency
is approximately 500 kHz 50% with a differential peak-to-peak amplitude of 500 mV and no de-emphasis.
Once the beacon is activated, the bridge continues to send the beacon signal until main power is restored as
indicated by PERST going inactive. At this time, the beacon signal is deactivated.
3.3.3 Wake
The bridge supports the PCI Express sideband WAKE feature. WAKE is an active low signal driven by the
bridge to request the reapplication of main power when in the L2 link state. Since WAKE is an open-collector
output, a system-side pullup resistor is required to prevent the signal from floating.
When the bridge is in the L2 link state and PME is received from a device on the secondary PCI bus, the WAKE
signal is asserted low as a wakeup mechanism. Once WAKE is asserted, the bridge drives the signal low until
main power is restored as indicated by PERST going inactive. At this time, WAKE is deasserted.
3.3.4 Initial Flow Control Credits
The bridge flow control credits are initialized using the rules defined in the PCI Express Base Specification.
Table 3−2 identifies the initial flow control credit advertisement for the bridge. The initial advertisement is
exactly the same when a second virtual channel (VC) is enabled.
Table 3−2. Initial Flow Control Credit Advertisements
CREDIT TYPE
INITIAL ADVERTISEMENT
Posted request headers (PH)
Posted request data (PD)
Nonposted header (NPH)
Nonposted data (NPD)
8
128
4
4
Completion header (CPLH)
Completion data (CPLD)
0 (infinite)
0 (infinite)
3.3.5 PCI Express Message Transactions
PCI Express messages are both initiated and received by the bridge. Table 3−3 outlines message support
within the bridge.
28
SCPS155C
April 2007 Revised October 2008
Feature/Protocol Descriptions
Table 3−3. Messages Supported by the Bridge
MESSAGE
Assert_INTx
SUPPORTED
Yes
BRIDGE ACTION
Transmitted upstream
Transmitted upstream
Received and processed
Transmitted upstream
Received and processed
Transmitted upstream
Transmitted upstream
Transmitted upstream
Transmitted upstream
Received and processed
Received and processed
Discarded
Deassert_INTx
Yes
PM_Active_State_Nak
PM_PME
Yes
Yes
PME_Turn_Off
Yes
PME_TO_Ack
Yes
ERR_COR
Yes
ERR_NONFATAL
ERR_FATAL
Yes
Yes
Unlock
Yes
Set_Slot_Power_Limit
Hot plug messages
Advanced switching messages
Vendor defined type 0
Vendor defined type 1
Yes
No
No
Discarded
No
Unsupported request
Discarded
No
All supported message transactions are processed per the PCI Express Base Specification.
3.4 PCI Bus Interface
3.4.1 I/O Characteristics
Figure 3−4 shows a 3-state bi-directional buffer that represents the I/O cell design for the PCI bus. Section
7.7, Electrical Characteristics over Recommended Operating Conditions, provides the electrical
characteristics of the PCI bus I/O cell.
NOTE: The PCI bus interface on the bridge meets the ac specifications of the PCI Local Bus
Specification. Additionally, PCI bus terminals (input or I/O) must be held high or low to prevent
them from floating.
V
CCP
Tied for Open Drain
OE
Pad
Figure 3−4. 3-State Bidirectional Buffer
3.4.2 Clamping Voltage
In the bridge, the PCI bus I/O drivers are powered from the V
to input signals with 5.0-V peak-to-peak amplitudes.
power rail. Plus, the I/O driver cell is tolerant
DD_33
For PCI bus interfaces operating at 66 MHz, all devices are required to output only 3.3-V peak-to-peak signal
amplitudes. For PCI bus interfaces operating at 33-MHz, devices may output either 3.3-V or 5.0-V
peak-to-peak signal amplitudes. The bridge accommodates both signal amplitudes.
Each PCI bus I/O driver cell has a clamping diode connected to the V
voltage rail that protects the cell
CCP
from excessive input voltage. If the PCI signaling is 3.3-V, then V
(A04, J01) is connected to a 3.3-V power
CCP
supply. If the PCI signaling is 5.0 V, then V
(A04, J01) is connected to a 5.0-V power supply.
CCP
29
April 2007 Revised October 2008
SCPS155C
Feature/Protocol Descriptions
The PCI bus signals attached to the V
clamping voltage are identified in the following list:
CCP
•
•
•
In Table 2−9, Clock Terminals, the terminal names include CLK and CLKOUT6:0.
In Table 2−10, PCI System Terminals, all terminal names except for PME
In Table 2−12, Miscellaneous Terminals, the terminal names include SERIRQ, M66EN, and LOCK.
3.4.3 PCI Bus Clock Run
The bridge supports the clock run protocol as specified in the PCI Mobile Design Guide. When the clock run
protocol is enabled, the bridge assumes the role of the central resource master.
To enable the clock run function, terminal B15 (CLKRUN_EN) is asserted high. Then, terminal T05 (GPIO0)
is enabled as the CLKRUN signal. An external pullup resistor must be provided to prevent the CLKRUN signal
from floating. To verify the operational status of the PCI bus clocks, bit 0 (SEC_CLK_STATUS) in the clock
run status register at offset DAh (see Section 4.68) is read.
Since the bridge has several unique features associated with the PCI bus interface, the system designer must
consider the following interdependencies between these features and the CLKRUN feature:
1. If the system designer chooses to generate the PCI bus clock externally, then the CLKRUN mode of the
bridge must be disabled. The central resource function within the bridge only operates as a CLKRUN
master and does not support the CLKRUN slave mode.
2. If the central resource function has stopped the PCI bus clocks, then the bridge still detects INTx state
changes and will generate and send PCI Express messages upstream.
3. If the serial IRQ interface is enabled and the central resource function has stopped the PCI bus clocks,
then any PCI bus device that needs to report an IRQ interrupt asserts CLKRUN to start the bus clocks.
4. When a PCI bus device asserts CLKRUN, the central resource function turns on PCI bus clocks for a
minimum of 512 cycles.
5. If the serial IRQ function detects an IRQ interrupt, then the central resource function keeps the PCI bus
clocks running until the IRQ interrupt is cleared by software.
6. If the central resource function has stopped the PCI bus clocks and the bridge receives a downstream
transaction that is forwarded to the PCI bus interface, then the bridge asserts CLKRUN to start the bus
clocks.
7. The central resource function is reset by PCI bus reset (PRST) assuring that clocks are present during
PCI bus resets.
3.4.4 PCI Bus External Arbiter
The bridge supports an external arbiter for the PCI bus. Terminal A15 (EXT_ARB_EN), when asserted high,
enables the use of an external arbiter.
When an external arbiter is enabled, GNT0 is connected to the external arbiter as the REQ for the bridge.
Likewise, REQ0 is connected to the external arbiter as the GNT for the bridge.
All internal port arbitration features are disabled when an external arbiter is enabled. 128-phase, weighted
round-robin (WRR) time-based arbitration, bus parking, arbiter time-out, tier select, and request masking
modes have no effect if an external arbiter is enabled.
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3.4.5 MSI Messages Generated from the Serial IRQ Interface
When properly configured, the bridge converts PCI bus serial IRQ interrupts into PCI Express message
signaled interrupts (MSI). classic PCI configuration register space is provided to enable this feature. The
following list identifies the involved configuration registers:
1. Command register at offset 04h, bit 2 (MASTER_ENB) is asserted (see Section 4.3).
2. MSI message control register at offset 62h, bits 0 (MSI_EN) and 6:4 (MM_EN) enable single and multiple
MSI messages, respectively (see Section 4.38).
3. MSI message address register at offsets 64h and 68h specifies the message memory address. A nonzero
address value in offset 68h initiates 64-bit addressing (see Section 4.40).
4. MSI message data register at offset 6Ch specifies the system interrupt message (see Section 4.41).
5. Serial IRQ mode control register at offset E0h specifies the serial IRQ bus format (see Section 4.72).
6. Serial IRQ edge control register at offset E2h selects either level or edge mode interrupts (see
Section 4.73).
7. Serial IRQ status register at offset E4h reports level mode interrupt status (see Section 4.74).
A PCI Express MSI is generated based on the settings in the serial IRQ edge control register. If the system
is configured for edge mode, then an MSI message is sent when the corresponding serial IRQ interface
sample phase transitions from low to high. If the system is configured for level mode, then an MSI message
is sent when the corresponding IRQ status bit in the serial IRQ status register changes from low to high.
The bridge has a dedicated SERIRQ terminal (T04) for all PCI bus devices that support serialized interrupts.
This SERIRQ interface is synchronous to the PCI bus clock input (CLK) frequency. The bridge always
generates a 17-phase serial IRQ stream. Internally, the bridge detects only 16 IRQ interrupts, IRQ0 frame
through IRQ15 frame. The IOCHCK frame is not monitored by the serial IRQ state machine and never
generates an IRQ interrupt or MSI message.
The multiple message enable (MM_EN) field determines the number of unique MSI messages that are sent
upstream on the PCI Express link. From 1 message to 16 messages, in powers of 2, are selectable. If fewer
than 16 messages are selected, then the mapping from IRQ interrupts to MSI messages is aliased. Table 3−4
illustrates the IRQ interrupt to MSI message mapping based on the number of enabling messages.
Table 3−4. IRQ Interrupt to MSI Message Mapping
1 MESSAGE
ENABLED
2 MESSAGES
ENABLED
4 MESSAGES
ENABLED
8 MESSAGES
ENABLED
16 MESSAGES
ENABLED
IRQ INTERRUPT
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #4
MSI MSG #5
MSI MSG #6
MSI MSG #7
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #4
MSI MSG #5
MSI MSG #6
MSI MSG #7
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #4
MSI MSG #5
MSI MSG #6
MSI MSG #7
MSI MSG #8
MSI MSG #9
MSI MSG #10
MSI MSG #11
MSI MSG #12
MSI MSG #13
MSI MSG #14
MSI MSG #15
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The MSI message format is compatible with the PCI Express request header format for 32-bit and 64-bit
memory write transactions. The system message and message number fields are included in bytes 0 and 1
of the data payload.
3.4.6 PCI Bus Clocks
The bridge has seven PCI bus clock outputs and one PCI bus clock input. Up to six PCI bus devices are
supported by the bridge.
Terminal R01 (M66EN) selects the operating frequency of the PCI bus clock outputs. When this input is
asserted high, the PCI bus clocks operate at 66-MHz. When this input is deasserted low, the PCI bus clocks
operate at 33-MHz. The clock control register at offset D8h provides 7 control bits to individually enable or
disable each PCI bus clock output (see Section 4.66). The register default is enabled for all 7 outputs.
The PCI bus clock (CLK) input provides the clock to the internal PCI bus core and serial IRQ core. When the
internal PCI bus clock source is selected, PCI bus clock output 6 (CLKOUT6) is connected to the PCI bus clock
input (CLK). When an external PCI bus clock source is selected, the external clock source is connected to the
PCI bus clock input (CLK). For external clock mode, all seven CLKOUT6:0 terminals must be disabled using
the clock control register at offset D8h (see Section 4.66).
3.5 Quality of Service and Isochronous Features
The bridge has standard and advanced features that provide a robust solution for quality-of-service (QoS) and
isochronous applications. These features are best described by divided them into the following three
categories:
•
PCI port arbitration. PCI port arbitration determines which bus master is granted the next transaction cycle
on the PCI bus. The three PCI port arbitration options are the classic PCI arbiter, the 128-phase, WRR
time-based arbiter, and the 128-phase, WRR aggressive time-based arbiter. The power-up register
default is the classic PCI arbiter. The advanced time-based arbiter features are provided to support
isochronous applications.
•
•
PCI isochronous windows. There are four separate windows that allow PCI bus-initiated memory
transactions to be labeled with a PCI Express traffic class (TC) beyond the default TC0. Each window
designates a range of PCI memory space that is mapped to a specified TC label. The power-up register
default is all four windows disabled.
PCI Express extended VC with VC arbitration. With an extended VC, system software can map a particular
TC to a specific VC. The differentiated traffic on the second VC then uses dedicated system resources
to support a QoS environment. VC arbitration is provided to gate traffic to the upstream PCI Express link.
The three VC arbitration options include strict priority, hardware-fixed round-robin, and 32-phase WRR.
The power-up register default is strict priority with the second VC disabled.
When configuring these standard and advanced features, the following rules must be followed:
1. The default mode is classic PCI arbiter with the PCI isochronous windows disabled and the second VC
disabled. The bridge performs default PCI bus arbitration without any arbiter-related configuration register
setup.
2. If a second VC is enabled, then at least one PCI isochronous window must be configured to map upstream
transactions to the second VC.
3. If a second VC is enabled, then any VC arbiter option interacts with any PCI port arbiter option.
4. To enable the PCI isochronous windows it is not required to enable a second VC. The memory space to
traffic mapping always uses VC0 for all upstream traffic.
5. When programming the upstream isochronous window base and limit registers, the 32-bit base/limit
address must be DWORD aligned and the limit address must be greater than the base address.
The following sections describe in detail the standard and advanced bridge features for QoS and isochronous
applications.
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3.5.1 PCI Port Arbitration
The internal PCI port arbitration logic supports up to six external PCI bus devices plus the bridge. Three options
exist when configuring the bridge arbiter for these seven bus devices: classic PCI arbiter, 128-phase, WRR
time-based arbiter, and 128-phase, WRR aggressive time-based arbiter.
3.5.1.1 Classic PCI Arbiter
The classic PCI arbiter is configured through the classic PCI configuration space at offset DCh. Table 3−5
identifies and describes the registers associated with classic PCI arbitration mode.
Table 3−5. Classic PCI Arbiter Registers
PCI OFFSET
Classic PCI configuration Arbiter control
register DCh (see Section 4.69)
REGISTER NAME
DESCRIPTION
Contains a two-tier priority scheme for the bridge and six PCI bus devices. The bridge
defaults to the high priority tier. The six PCI bus devices default to the low priority tier. A
bus parking control bit (bit 7, PARK) is provided.
Classic PCI configuration Arbiter request mask
register DDh (see Section 4.70)
Six mask bits provide individual control to block each PCI Bus REQ input. Bit 7
(ARB_TIMEOUT) in the arbiter request mask register enables generating timeout
status if a PCI device does not respond within 16 PCI bus clocks. Bit 6 (AUTO_MASK)
in the arbiter request mask register automatically masks a PCI bus REQ if the device
does not respond after GNT is issued. The AUTO_MASK bit is cleared to disable any
automatically generated mask.
Classic PCI configuration Arbiter time-out status When bit 7 (ARB_TIMEOUT) in the arbiter request mask register (see Section 4.70) is
register DEh (see Section 4.71) asserted, timeout status for each PCI bus device is reported in this register.
3.5.1.2 128-Phase, WRR Time-Based Arbiter
The 128-phase, WRR time-based arbiter is configured through the PCI express VC extended configuration
space at offset 150h and the device control memory window register map.
The 128-phase, WRR time-based arbiter periodically asserts GNT to a PCI master device based on entries
within a port arbitration table. There are actually two port arbitration tables within the bridge. The first table
is accessed through the PCI Express VC extended configuration register space using configuration read/write
transactions. The second table is internal and is used by the PCI bus arbiter to make GNT decisions. A
configuration register load function exists to transfer the contents of the configuration register table to the
internal table.
The port arbitration table uses a 4-bit field to identify the secondary bus master that receives GNT during each
phase of the time-based WRR arbitration. For the arbiter to recognize a bus master REQ and to generate GNT,
software must allocate at least three consecutive phases to the same port number.
Table 3−6 defines the mapping relationship of the PCI bus devices to a port number in the port arbitration table.
Table 3−6. Port Number to PCI Bus Device Mapping
PORT NUMBER
0000b
GNT
Internal GNT for PCI master state machine
External GNT0
PCI DEVICE
Internal REQ from PCI master state machine
External REQ0
0001b
0010b
External GNT1
External REQ1
0011b
External GNT2
External REQ2
0100b
External GNT3
External REQ3
0101b
External GNT4
External REQ4
0110b
External GNT5
External REQ5
0111b−1111b
Reserved
−
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To enable the 128-phase, WRR time-based arbiter, two configuration registers must be written. Bit 1
(PORTARB_LEVEL_1_EN) in the upstream isochrony control register at offset 04h (see Section 6.4) within
the device control memory window register map must be asserted. The VC1 resource control register at offset
170h within the PCI Express VC extended configuration space has a PORT_ARB_SELECT field that must
be set to 100b (see Section 5.22).
Table 3−7 identifies and describes the registers associated with 128-phase, WWR time-based arbitration
mode.
Table 3−7. 128-Phase, WRR Time-Based Arbiter Registers
REGISTER OFFSET
REGISTER NAME
DESCRIPTION
PCI Express VC extended Port arbitration table
16-doubleword sized configuration registers that are the registered version of the
128-phase, WRR port arbitration table. Each port arbitration table entry is a 4-bit
field.
configuration registers
1C0h to 1FCh
(see Section 5.28)
PCI Express VC extended VC1 resource control
configuration register 170h (see Section 5.25)
Bits 19:17 (PORT_ARB_SELECT) equal to 100b define the port arbitration
mechanism as 128-phase WRR.
Bit 16 (LOAD_PORT_TABLE), when written with a 1b, transfers the port arbitration
table configuration register values to the internal registers used by the PCI bus
arbiter.
PCI Express VC extended VC1 resource status
configuration register 176h (see Section 5.26)
Bit 0 (PORT_TABLE_STATUS) equal to 1b indicates that the port arbitration table
configuration registers were updated but not loaded into the internal arbitration
table.
Device control memory
window register 04h
Upstream isochrony
control (see Section 6.4) time-based arbiter.
Bit 1 (PORTARB_LEVEL_1_EN) must be asserted to enable the 128-phase, WRR
3.5.1.3 128-Phase, WRR Aggressive Time-Based Arbiter
The last option for PCI port arbitration is 128-phase, WRR aggressive time-based arbitration mode. This
arbitration mode performs the same as isochronous mode arbitration, but with one difference. When an
isochronous timing event occurs, the PCI bus arbiter deliberately stops a secondary bus master in the middle
of the transaction to assure that isochrony is preserved. The register setup for this arbitration option is the
same as the 128-phase, WRR time-based arbiter option with the following addition. Bit 2
(PORTARB_LEVEL_2_EN) in the device control memory window upstream isochrony control register at offset
04h must be asserted (see Section 6.4).
3.5.2 PCI Isochronous Windows
The bridge has four separate windows that allow PCI bus-initiated memory transactions to be labeled with a
PCI Express traffic class (TC) beyond the default TC0. Each window designates a range of PCI memory space
that is mapped to a specified TC label. This advance feature is configured through the device control memory
window register map.
Table 3−8 identifies and describes the registers associated with isochronous arbitration mode.
Table 3−8. PCI Isochronous Windows
REGISTER OFFSET
REGISTER NAME
DESCRIPTION
Device control memory
window register 08h
Upstream isochronous window 0 Bits 3:1 (ISOC_WINDOW_EN) indicate that memory addresses within the
control (see Section 6.5)
base and limit addresses are mapped to a specific traffic class ID.
Bit 0 (TC_ID) identifies the specific traffic class ID.
Note: Memory-mapped register space exists for four upstream windows.
Only window 0 is included in this table.
Device control memory
window register 0Ch
Upstream isochronous window 0 Window 0 base address
base address (see Section 6.6)
Device control memory
window register 10h
Upstream isochronous window 0 Window 0 limit address
limit address (see Section 6.7)
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3.5.3 PCI Express Extended VC With VC Arbitration
When a second VC is enabled, the bridge has three arbitration options that determine which VC is granted
access to the upstream PCI Express link. These three arbitration modes include strict priority, hardware-fixed
round-robin, and 32-phase WRR. The default mode is strict priority. For all three arbitration modes, if the
second VC is disabled, then VC0 is always granted.
To map upstream transactions to the extended VC, the following registers must be programmed:
1. Bit 0 (ISOC_ENABLE) is asserted in the upstream isochrony control register at device control memory
window register offset 04h (see Section 6.4).
2. At least one PCI isochronous window register set must be programmed. Please see Section 3.5.2 for a
description on how to program this advanced feature.
3. The traffic class ID selected for the PCI isochronous window(s) must be assigned to the extended VC.
This is accomplished by asserting the corresponding bit in the TC_VC_MAP field in the VC resource
control register (VC1) at PCI Express extended register offset 170h (see Section 5.25).
4. The extended VC must be enabled. This is accomplished by asserting bit 31 (VC_EN) and programming
bits 26:24 (VC_ID) in the VC resource control register (VC1) at PCI Express extended register offset 170h.
3.5.3.1 Strict Priority Arbitration Mode
Strict priority arbitration always grants VC1 traffic over VC0 traffic. If the traffic on VC1 uses 100% of the
upstream link bandwidth, then VC0 traffic is blocked. This mode is enabled when bit 25
(STRICT_PRIORITY_EN) in the general control register at offset D4h equals 1b (see Section 4.65).
For applications that require QoS or isochronous operation, this arbitration mode is recommended. In this
mode, all traffic on VC1 is assured access to the upstream link and VC0 traffic is best effort with a lower priority.
3.5.3.2 Hardware-Fixed, Round-Robin Arbitration
Hardware-fixed, round-robin arbitration alternates between VC0 and the second VC. Over an extended period
of time, if both VCs are heavily loaded with equal data payloads, each VC is granted approximately 50% of
the upstream link bandwidth. The PCI configuration registers described in Table 3−9 configure the
hardware-fixed, round-robin arbitration mode.
Table 3−9. Hardware-Fixed, Round-Robin Arbiter Registers
PCI OFFSET
REGISTER NAME
DESCRIPTION
Classic PCI configuration
register D4h
General control
(see Section 4.65)
Bit 25 (STRICT_PRIORITY_EN) equal to 0b enables either hardware-fixed,
round-robin or 32-phase, WRR arbitration mode.
Classic PCI configuration
register 15Ch
Port VC control
(see Section 5.19)
Bits 3:1 (VC_ARB_SELECT) equal to 000b enables hardware-fixed,
round-robin arbitration mode.
3.5.3.3 32-Phase, WRR Arbitration Mode
When the second upstream VC is enabled, the VC arbiter selects the next PCI Express upstream link
transaction based on entries within a VC arbitration table. There are actually two VC arbitration tables within
the bridge. The first table is accessed through the extended PCI Express configuration register space using
configuration read/write transactions. The second table is internal and is used by the VC arbiter to make
selection decisions. A configuration register load function exists to transfer the contents of the configuration
register table to the internal table.
The VC arbitration table uses a 4-bit field to identify the VC that is selected during each arbiter cycle. Bits 2:0
of this 4-bit field are loaded with the VC_ID assigned to each VC. For the arbiter to recognize a VC request,
the software must allocate only 1 phase to the same VC_ID.
The PCI configuration registers described in Table 3−10 configure the 32-phase, WRR arbitration mode.
35
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Table 3−10. 32-phase, WRR Arbiter Registers
PCI OFFSET
REGISTER NAME
DESCRIPTION
Classic PCI configuration
register D4h
General control
(see Section 4.65)
Bit 25 (STRICT_PRIORITY_EN) equal to 0b enables either hardware-fixed,
round-robin or 32-phase, WRR arbitration mode.
PCI Express VC extended
configuration register 15Ch
Port VC control
(see Section 5.19)
Bit 0 (LOAD_VC_TABLE) when written with a 1b transfers the VC arbitration table
configuration register values to the internal registers used by the VC arbiter.
Bits 3:1 (VC_ARB_SELECT) equal to 001b enables 32-phase, WRR arbitration
mode.
PCI Express VC extended
configuration register 15Eh
Port VC status
(see Section 5.20)
Bit 0 (VC_TABLE_STATUS) equal to 1b indicates that the VC arbitration table
configuration registers were updated but not loaded into the internal arbitration
table.
PCI Express VC extended
configuration registers 180h
to 18Ch
VC arbitration table
(see Section 5.27)
4-doubleword sized configuration registers that are the registered version of the
32-phase, WRR VC arbitration table. Each VC arbitration table entry is a 4-bit field.
3.5.4 128-Phase, WRR PCI Port Arbitration Timing
This section includes a timing diagram that illustrates the 128-phase, WRR time-based arbiter timing for the
bridge and three PCI bus devices. This timing diagram assumes aggressive mode since the transfer
associated with device #1 is stopped to start a device #0 transfer. The PCI bus cycle where device #1 is
stopped is indicated by the ‡ symbol. Device #1 then waits until its next port arbitration table cycle to finish
the transfer.
The signal waveforms associated with bridge REQ, bridge GNT, ISOC reference clock, and port arbitration
table entry are internal to the bridge. These internal bridge signals are included here to help clarify the
operation of the PCI port arbiter in 128-phase, WRR time-based arbitration mode. The remaining REQ, GNT,
and PCI bus signals are all external to the bridge.
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Feature/Protocol Descriptions
Bridge
REQ
REQ0
REQ1
REQ2
Bridge
GNT
GNT0
GNT1
GNT2
Isoc Ref
Clock
Port Arb
Table
3
3
0
0
0
2
2
2
2
‡
1
1
1
1
3
3
3
0
0
0
2
2
2
2
1
Bridge
Bridge
Device 1
PCI Bus
Device 1
Device 0
Device 2
Figure 3−5. PCI Bus Timing
3.6 Configuration Register Translation
PCI Express configuration register transactions received by the bridge are decoded based on the transaction’s
destination ID. These configuration transactions can be broken into three subcategories: type 0 transactions,
type 1 transactions that target the secondary bus, and type 1 transactions that target a downstream bus other
than the secondary bus.
PCI Express type 0 configuration register transactions always target the configuration space and are never
passed on to the secondary interface.
Type 1 configuration register transactions that target a device on the secondary bus are converted to type 0
configuration register transactions on the PCI bus. Figure 3−6 shows the address phase of a type 0
configuration transaction on the PCI bus as defined by the PCI specification.
31
16
15
11 10
Function
Number
8
7
2
1
0
0
0
IDSEL
Reserved
Register Number
Figure 3−6. Type 0 Configuration Transaction Address Phase Encoding
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Feature/Protocol Descriptions
In addition, the bridge converts the destination ID device number to one of the AD[31:16] lines as the IDSEL
signal. The implemented IDSEL signal mapping is shown in Table 3−11.
Table 3−11. Type 0 Configuration Transaction IDSEL Mapping
DEVICE
AD[31:16]
NUMBER
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
1xxxx
0000 0000 0000 0001
0000 0000 0000 0010
0000 0000 0000 0100
0000 0000 0000 1000
0000 0000 0001 0000
0000 0000 0010 0000
0000 0000 0100 0000
0000 0000 1000 0000
0000 0001 0000 0000
0000 0010 0000 0000
0000 0100 0000 0000
0000 1000 0000 0000
0001 0000 0000 0000
0010 0000 0000 0000
0100 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
Type 1 configuration registers transactions that target a downstream bus other then the secondary bus are
output on the PCI bus as type 1 PCI configuration transactions. Figure 3−7 shows the address phase of a type
1 configuration transaction on the PCI bus as defined by the PCI specification.
31
24
23
16
15
11
10
8
7
2
1
0
0
1
Function
Number
Reserved
Bus Number
Device Number
Register Number
Figure 3−7. Type 1 Configuration Transaction Address Phase Encoding
3.7 PCI Interrupt Conversion to PCI Express Messages
The bridge converts interrupts from the PCI bus sideband interrupt signals to PCI Express interrupt messages.
PCI Express Assert_INTx messages are generated when one of the PCI bus INT[A:D] input terminals
transitions low. The requester ID portion of the Assert_INTx message uses the value stored in the primary bus
number register (see Section 4.11) as the bus number, 0 as the device number, and 0 as the function number.
The tag field for each Assert_INTx message is 00h. The lower two bits in the code field indicate the asserted
interrupt signal.
PCI Express Deassert_INTx messages are generated when one of the PCI bus INT[A:D] input terminals
transitions high. The requester ID portion of the Deassert_INTx message uses the value stored in the primary
bus number register as the bus number, 0 as the device number, and 0 as the function number. The Tag field
for each Deassert_INTx message is 00h. The lower two bits in the code field indicate the deasserted interrupt
signal.
Table 3−12, Figure 3−8, and Figure 3−9 illustrate the format for both the assert and deassert INTx messages.
38
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Feature/Protocol Descriptions
Table 3−12. Interrupt Mapping In The Code Field
INTERRUPT CODE FIELD
INTA
INTB
INTC
INTD
00
01
10
11
+0
+1
+2
+3
7
6
5
1
4
1
3
0
2
Type
1
1
0
0
0
7
6
0
5
TC
0
4
0
3
2
1
0
7
T
D
6
E
P
5
4
0
3
2
1
0
0
0
7
0
0
6
0
0
5
4
3
0
2
0
0
1
0
x
0
0
x
Fmt
Attr
Length
Byte 0>
Byte 4>
R
R
Reserved
R
0
0
0
1
0
Code
Requester ID
Tag
0
0
Byte 8>
Reserved
Byte 12>
Figure 3−8. PCI Express ASSERT_INTX Message
+0
+1
+2
+3
7
6
0
5
4
1
3
0
2
Type
1
1
0
0
0
7
6
0
5
TC
0
4
0
3
2
1
0
7
T
D
6
E
P
5
4
0
3
2
1
0
0
0
7
0
0
6
0
0
5
4
3
0
2
0
1
1
0
x
0
0
x
Fmt
Attr
Length
Byte 0>
Byte 4>
R
R
Reserved
R
1
0
0
0
Code
Requester ID
Tag
1
0
0
Byte 8>
Reserved
Byte 12>
Figure 3−9. PCI Express DEASSERT_INTX Message
3.8 PME Conversion to PCI Express Messages
When the PCI bus PME input transitions low, the bridge generates and sends a PCI Express PME message
upstream. The requester ID portion of the PME message uses the stored value in the secondary bus number
register as the bus number, 0 as the device number, and 0 as the function number. The Tag field for each PME
message is 00h. A PME message is sent periodically until the PME signal transitions high.
Figure 3−10 illustrates the format for a PCI Express PME message.
+0
+1
+2
+3
7
6
5
1
4
1
3
0
2
Type
0
1
0
0
0
7
6
0
5
TC
0
4
0
3
2
1
0
7
T
D
6
E
P
5
4
0
3
2
1
0
0
0
7
0
0
6
0
0
5
4
3
0
2
0
0
1
0
0
0
0
0
Fmt
Attr
Length
Byte 0>
Byte 4>
R
R
Reserved
R
0
0
0
0
0
Code
Requester ID
Tag
1
1
Byte 8>
Reserved
Byte 12>
Figure 3−10. PCI Express PME Message
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3.9 PCI Express To PCI Bus Lock Conversion
The bus-locking protocol defined in the PCI Express Base Specification and PCI Local Bus Specification is
provided on the bridge as an additional compatibility feature. The PCI bus LOCK signal is a dedicated output
that is enabled by setting bit 12 in the general control register at offset D4h. See Section 4.65, General Control
Register, for details.
NOTE:The use of LOCK is only supported by PCI-Express to PCI Bridges in the downstream
direction (away from the root complex).
PCI Express locked-memory read request transactions are treated the same as PCI Express memory read
transactions except that the bridge returns a completion for a locked-memory read. Also, the bridge uses the
PCI LOCK protocol when initiating the memory read transaction on the PCI bus.
When a PCI Express locked-memory read request transaction is received and the bridge is not already locked,
the bridge arbitrates for use of the LOCK terminal by asserting REQ. If the bridge receives GNT and the LOCK
terminal is high, then the bridge drives the LOCK terminal low after the address phase of the first
locked-memory read transaction to take ownership of LOCK. The bridge continues to assert LOCK except
during the address phase of locked transactions. If the bridge receives GNT and the LOCK terminal is low,
then the bridge deasserts its REQ and waits until LOCK is high and the bus is idle before re-arbitrating for the
use of LOCK.
CLK
FRAME
LOCK
AD
IRDY
Address
Data
TRDY
DEVSEL
Figure 3−11. Starting A Locked Sequence
Once the bridge has ownership of LOCK, the bridge initiates the lock read as a memory read transaction on
the PCI bus. When the target of the locked-memory read returns data, the bridge is considered locked and
all transactions not associated with the locked sequence are blocked by the bridge.
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CLK
FRAME
LOCK
AD
Address
Data
IRDY
TRDY
DEVSEL
Figure 3−12. Continuing A Locked Sequence
Because PCI Express does not have a unique locked-memory write request packet, all PCI Express memory
write requests that are received while the bridge is locked are considered part of the locked sequence and
are transmitted to PCI as locked-memory write transactions. In addition, all traffic mapped to VC1 is allowed
to pass.
The bridge terminates the locked sequence when an unlock message is received from PCI Express and all
previous locked transactions have been completed.
CLK
FRAME
LOCK
IRDY
Figure 3−13. Terminating A Locked Sequence
In the erroneous case that a normal downstream memory read request is received during a locked sequence,
the bridge responds with an unsupported request completion status. Please note that this condition must
never occur, because the PCI Express specification requires the root complex to block normal memory read
requests at the source. All locked sequences that end successfully or with an error condition must be
immediately followed by an unlock message. This unlock message is required to return the bridge to a known
unlocked state.
3.10 Two-Wire Serial-Bus Interface
The bridge provides a two-wire serial-bus interface to load subsystem identification information and specific
register defaults from an external EEPROM. The serial-bus interface signals (SCL and SDA) are shared with
two of the GPIO terminals (4 and 5). If the serial bus interface is enabled, then the GPIO4 and GPIO5 terminals
are disabled. If the serial bus interface is disabled, then the GPIO terminals operate as described in
Section 3.13.
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3.10.1 Serial-Bus Interface Implementation
To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal. At the rising edge
of PERST or GRST, whichever occurs later in time, the SDA terminal is checked for a pullup resistor. If one
is detected, then bit 3 (SBDETECT) in the serial-bus control and status register (see Section 4.58) is set.
Software may disable the serial-bus interface at any time by writing a 0b to the SBDETECT bit. If no external
EEPROM is required, then the serial-bus interface is permanently disabled by attaching a pulldown resistor
to the SDA signal.
The bridge implements a two-terminal serial interface with 1 clock signal (SCL) and 1 data signal (SDA). The
SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both are open-drain
signals and require pullup resistors. The bridge is a bus master device and drives SCL at approximately
60 kHz during data transfers and places SCL in a high-impedance state (0 frequency) during bus idle states.
The serial EEPROM is a bus slave device and must acknowledge a slave address equal to A0h. Figure 3−14
illustrates an example application implementing the two-wire serial bus.
V
DD_33
Serial
EEPROM
XIO2000A
A0
GPIO4 // SCL
GPIO5 // SDA
A1 SCL
A2 SDA
Figure 3−14. Serial EEPROM Application
3.10.2 Serial-Bus Interface Protocol
All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a start
condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as
illustrated in Figure 3−15. The end of a requested data transfer is indicated by a stop condition, which is
signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3−15. Data on
SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high
state of SCL are interpreted as control signals, that is, a start or stop condition.
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Feature/Protocol Descriptions
SDA
SCL
Start
Stop
Change of
Condition
Condition
Data Allowed
Data Line Stable,
Data Valid
Figure 3−15. Serial-Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. During a data transfer operation, the exact number of bytes that are
transmitted is unlimited. However, each byte must be followed by an acknowledge bit to continue the data
transfer operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA signal low,
so that it remains low during the high state of the SCL signal. Figure 3−16 illustrates the acknowledge protocol.
SCL From
1
2
3
7
8
9
Master
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3−16. Serial-Bus Protocol Acknowledge
The bridge performs three basic serial-bus operations: single byte reads, single byte writes, and multibyte
reads. The single byte operations occur under software control. The multibyte read operations are performed
by the serial EEPROM initialization circuitry immediately after a PCI Express reset. See Section 3.10.3,
Serial-Bus EEPROM Application, for details on how the bridge automatically loads the subsystem
identification and other register defaults from the serial-bus EEPROM.
Figure 3−17 illustrates a single byte write. The bridge issues a start condition and sends the 7-bit slave device
address and the R/W command bit is equal to 0b. A 0b in the R/W command bit indicates that the data transfer
is a write. The slave device acknowledges if it recognizes the slave address. If no acknowledgment is received
by the bridge, then bit 1 (SB_ERR) is set in the serial-bus control and status register (PCI offset B3h, see
Section 4.58). Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment
is expected. Then the bridge delivers the data byte MSB first and expects a final acknowledgment before
issuing the stop condition.
Slave Address
Word Address
Data Byte
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
P
R/W
A = Slave Acknowledgement
S/P = Start/Stop Condition
Figure 3−17. Serial-Bus Protocol—Byte Write
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Feature/Protocol Descriptions
Figure 3−18 illustrates a single byte read. The bridge issues a start condition and sends the 7-bit slave device
address and the R/W command bit is equal to 0b (write). The slave device acknowledges if it recognizes the
slave address. Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment
is expected. Then, the bridge issues a restart condition followed by the 7-bit slave address and the R/W
command bit is equal to 1b (read). Once again, the slave device responds with an acknowledge. Next, the
slave device sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the bridge responds with no
acknowledge (logic high) indicating the last data byte. Finally, the bridge issues a stop condition.
Slave Address
Word Address
Slave Address
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
S
b6 b5 b4 b3 b2 b1 b0
1
A
Start
R/W
Restart
R/W
Data Byte
b7 b6 b5 b4 b3 b2 b1 b0
M
P
Stop
A = Slave Acknowledgement
M = Master Acknowledgement
S/P = Start/Stop Condition
Figure 3−18. Serial-Bus Protocol—Byte Read
Figure 3−19 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The
serial-bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes
are transferred. The number of transferred data bytes is controlled by the bridge master. After each data byte,
the bridge master issues acknowledge (logic low) if more data bytes are requested. The transfer ends after
a bridge master no acknowledge (logic high) followed by a stop condition.
Slave Address
Word Address
Slave Address
S
1
0
1
0
0
0
0
0
A
0
0
0
0
0
0
0
0
A
S
1
0
1
0
0
0
0
1
A
Start
R/W
Restart
R/W
Data Byte 0
M
Data Byte 1
M
Data Byte 2
M
Data Byte 3
M
P
A = Slave Acknowledgement
M = Master Acknowledgement
S/P = Start/Stop Condition
Figure 3−19. Serial-Bus Protocol—Multibyte Read
Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the
three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this control
bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol.
This feature allows the system designer a second serial-bus protocol option when selecting external EEPROM
devices.
3.10.3 Serial-Bus EEPROM Application
The registers and corresponding bits that are loaded through the EEPROM are provided in Table 3−13.
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Feature/Protocol Descriptions
Table 3−13. EEPROM Register Loading Map
SERIAL EEPROM
WORD ADDRESS
BYTE DESCRIPTION
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
PCI-Express to PCI bridge function indicator (00h)
Number of bytes to download (1Eh)
PCI 84h, subsystem vendor ID, byte 0
PCI 85h, subsystem vendor ID, byte 1
PCI 86h, subsystem ID, byte 0
PCI 87h, subsystem ID, byte 1
PCI D4h, general control, byte 0
PCI D5h, general control, byte 1
PCI D6h, general control, byte 2
PCI D7h, general control, byte 3
PCI D8h, clock control
PCI D9h, clock mask
Reserved—no bits loaded
PCI DCh, arbiter control
PCI DDh, arbiter request mask
PCI C0h, control and diagnostic register 0 byte 0
PCI C1h, control and diagnostic register 0 byte 1
PCI C2h, control and diagnostic register 0 byte 2
PCI C3h, control and diagnostic register 0 byte 3
PCI C4h, control and diagnostic register 1 byte 0
PCI C5h, control and diagnostic register 1 byte 1
PCI C6h, control and diagnostic register 1 byte 2
PCI C7h, control and diagnostic register 1 byte 3
PCI C8h, control and diagnostic register 2 byte 0
PCI C9h, control and diagnostic register 2 byte 1
PCI CAh, control and diagnostic register 2 byte 2
PCI CBh, control and diagnostic register 2 byte 3
Reserved—no bits loaded
Reserved—no bits loaded
PCI E0h, serial IRQ mode control
PCI E2h, serial IRQ edge control, byte 0
PCI E3h, serial IRQ edge control, byte 1
End-of-list indicator (80h)
This format must be explicitly followed for the bridge to correctly load initialization values from a serial
EEPROM. All byte locations must be considered when programming the EEPROM.
The serial EEPROM is addressed by the bridge at slave address 1010 000b. This slave address is internally
hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the
EEPROM are tied to V
to achieve this address. The serial EEPROM in the sample application circuit
SS
(Figure 3−14) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to
the chip, and the sample application shows these terminal inputs tied to V
.
SS
During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is
asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may
be monitored to verify a successful download.
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3.10.4 Accessing Serial-Bus Devices Through Software
The bridge provides a programming mechanism to control serial-bus devices through system software. The
programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−14 lists
the registers that program a serial-bus device through software.
Table 3−14. Registers Used To Program Serial-Bus Devices
PCI OFFSET
REGISTER NAME
Serial-bus data
DESCRIPTION
B0h
Contains the data byte to send on write commands or the received data byte on read
commands.
(see Section 4.55)
B1h
Serial-bus word address
(see Section 4.56)
The content of this register is sent as the word address on byte writes or reads. When bit 7
(PROT_SEL) in the serial-bus control and status register (offset B3h, see Section 4.58) is set
to 1b and the quick command protocol is selected, this word address is ignored.
B2h
B3h
Serial-bus slave address
(see Section 4.57)
Write transactions to this register initiate a serial-bus transaction. The slave device address
and the R/W command selector are programmed through this register.
Serial-bus control and status Serial interface enable, busy, and error status are communicated through this register. In
(see Section 4.58)
addition, the protocol-select (PROT_SEL) bit and serial-bus test (SBTEST) bit are
programmed through this register.
To access the serial EEPROM through the software interface, the following steps are performed:
1. The control and status byte is read to verify the EEPROM interface is enabled (SBDETECT asserted) and
not busy (REQBUSY and ROMBUSY deasserted).
2. The serial-bus word address is loaded. If the access is a write, then the data byte is also loaded.
3. The serial-bus slave address and R/W command selector byte is written.
4. REQBUSY is monitored until this bit is deasserted.
5. SB_ERR is checked to verify that the serial-bus operation completed without error. If the operation is a
read, then the serial-bus data byte is now valid.
3.11 Advanced Error Reporting Registers
In the extended PCI Express configuration space, the bridge supports the advanced error reporting
capabilities structure. For the PCI Express interface, both correctable and uncorrectable error status is
provided. For the PCI bus interface, secondary uncorrectable error status is provided. All uncorrectable status
bits have corresponding mask and severity control bits. For correctable status bits, only mask bits are
provided.
Both the primary and secondary interfaces include first error pointer and header log registers. When the first
error is detected, the corresponding bit position within the uncorrectable status register is loaded into the first
error pointer register. Likewise, the header information associated with the first failing transaction is loaded
into the header log. To reset this first error control logic, the corresponding status bit in the uncorrectable status
register is cleared by a writeback of 1b.
For systems that require high data reliability, ECRC is fully supported on the PCI Express interface. The
primary side advanced error capabilities and control register has both ECRC generation and checking enable
control bits. When the checking bit is asserted, all received TLPs are checked for a valid ECRC field. If the
generation bit is asserted, then all transmitted TLPs contain a valid ECRC field.
3.12 Data Error Forwarding Capability
The bridge supports the transfer of data errors in both directions.
If a downstream PCI Express transaction with a data payload is received that targets the PCI bus and the EP
bit is set indicating poisoned data, then the bridge must ensure that this information is transferred to the PCI
bus. To do this, the bridge forces a parity error on each PCI bus data phase by inverting the parity bit calculated
for each double-word of data.
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If the bridge is the target of a PCI transaction that is forwarded to the PCI Express interface and a data parity
error is detected, then this information is passed to the PCI Express interface. To do this, the bridge sets the
EP bit in the upstream PCI Express header.
3.13 General-Purpose I/O Interface
Up to eight general-purpose input/output (GPIO) terminals are provided for system customization. These
GPIO terminals are 3.3-V tolerant.
The exact number of GPIO terminals varies based on implementing the clock run, power override, and serial
EEPROM interface features. These features share four of the eight GPIO terminals. When any of the three
shared functions are enabled, the associated GPIO terminal is disabled.
All eight GPIO terminals are individually configurable as either inputs or outputs by writing the corresponding
bit in the GPIO control register at offset B4h. A GPIO data register at offset B6h exists to either read the logic
state of each GPIO input or to set the logic state of each GPIO output. The power-up default state for the GPIO
control register is input mode.
3.14 Set Slot Power Limit Functionality
The PCI Express Specification provides a method for devices to limit internal functionality and save power
based on the value programmed into the captured slot power limit scale (CSPLS) and capture slot power limit
value (CSPLV) fields of the PCI Express device capabilities register at offset 94h. See Section 4.49, Device
Capabilities Register, for details. The bridge writes these fields when a set slot power limit message is received
on the PCI Express interface.
After the deassertion of PERST, the bridge compares the information in the CSPLS and CSPLV fields of the
device capabilities register with the minimum power scale (MIN_POWER_SCALE) and minimum power value
(MIN_POWER_VALUE) fields in the general control register at offset D4h. See Section 4.65, General Control
Register, for details. If the CSPLS and CSPLV fields are less than the MIN_POWER_SCALE and
MIN_POWER_VALUE fields, respectively, then the bridge takes the appropriate action that is defined below.
The power usage action is programmable within the bridge. The general control register includes a 3-bit
PWR_OVRD field. This field is programmable to the following five options:
1. Ignore slot power limit fields
2. Assert the PWR_OVRD terminal (U05)
3. Disable secondary clocks as specified by the clock mask register at offset D9h.
4. Disable secondary clocks as specified by the clock mask register and assert the PWR_OVRD terminal
5. Respond with unsupported request to all transactions except type 0/1 configuration transactions and set
slot power limit messages
3.15 PCI Express and PCI Bus Power Management
The bridge supports both software-directed power management and active state power management through
standard PCI configuration space. Software-directed registers are located in the power management
capabilities structure located at offset 50h. Active state power management control registers are located in
the PCI Express capabilities structure located at offset 90h.
During software-directed power management state changes, the bridge initiates link state transitions to L1 or
L2/L3 after a configuration write transaction places the device in a low power state. The power management
state machine is also responsible for gating internal clocks based on the power state. Table 3−15 identifies
the relationship between the D-states and bridge clock operation.
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Table 3−15. Clocking In Low Power States
CLOCK SOURCE
D0/L0
On
D1/L1
On
D2/L1
On
D3/L2/L3
On/Off
Off
PCI express reference clock input (REFCLK)
PCI clock input (CLK)
On
Off
Off
Secondary PCI bus clock outputs (CLKOUT6:0)
On
On
On
On/Off
The link power management (LPM) state machine manages active state power by monitoring the PCI Express
transaction activity. If no transactions are pending and the transmitter has been idle for at least the minimum
time required by the PCI Express Specification, then the LPM state machine transitions the link to either the
L0s or L1 state. By reading the bridge’s L0s and L1 exit latency in the link capabilities register, the system
software may make an informed decision relating to system performance versus power savings. The ASLPMC
field in the link control register provides an L0s-only option, L1-only option, or both L0s and L1 option.
Finally, the bridge generates the PM_Active_State_Nak Message if a PM_Active_State_Request_L1 DLLP
is received on the PCI Express interface and the link cannot be transitioned to L1.
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Classic PCI Configuration Space
4
Classic PCI Configuration Space
The programming model of the XIO2000A PCI-Express to PCI bridge is compliant to the classic PCI-to-PCI
bridge programming model. The PCI configuration map uses the type 1 PCI bridge header.
k
All bits marked with a are sticky bits and are reset by a global reset (GRST) or the internally-generated
power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST), a GRST, or the
internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST,
GRST, or the internally-generated power-on reset.
Table 4−1. Classic PCI Configuration Register Map
REGISTER NAME
OFFSET
000h
Device ID
Status
Vendor ID
Command
004h
Class code
Header type
Device control base address
Reserved
Subordinate bus number Secondary bus number
Secondary status I/O limit
Revision ID
008h
BIST
Latency timer
Cache line size
00Ch
010h
014h
Secondary latency timer
Primary bus number
I/O base
018h
01Ch
Memory limit
Memory base
020h
Prefetchable memory limit
Prefetchable memory base
024h
Prefetchable base upper 32 bits
Prefetchable limit upper 32 bits
028h
02Ch
I/O limit upper 16 bits
I/O base upper 16 bits
030h
Reserved
Capabilities pointer
034h
Reserved
Reserved
038h
Bridge control
Interrupt pin
Interrupt line
PM CAP ID
03Ch
040h−04Ch
050h
Power management capabilities
Next item pointer
PM data
PMCSR_BSE
Power management CSR
054h
Reserved
058h−05Ch
060h
MSI message control
Reserved
Next item pointer
MSI CAP ID
MSI message address
064h
MSI upper message address
068h
MSI message data
06Ch
Reserved
070h−07Ch
080h
Reserved
Next item pointer
SSID/SSVID CAP ID
Subsystem ID†
Subsystem vendor ID†
084h
Reserved
088h−08Ch
090h
PCI Express capabilities register
Device status
Next item pointer
PCI Express capability ID
Device capabilities
Link capabilities
Reserved
094h
Device control
098h
09Ch
Link status
Link control
0A0h
0A4h−0ACh
0B0h
Serial-bus control and
status†
Serial-bus slave address† Serial-bus word address†
Serial-bus data†
†
One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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Classic PCI Configuration Space
Table 4−1. PCI Express Configuration Register Map (Continued)
REGISTER NAME
OFFSET
0B4h
GPIO data†
GPIO control†
Reserved
0B8h−0BCh
0C0h
Control and diagnotic register 0†
Control and diagnotic register 1†
Control and diagnotic register 2†
Reserved
0C4h
0C8h
0CCh
Subsystem access†
0D0h
General control†
0D4h
Reserved
Reserved
Clock run status†
Arbiter time-out status
Clock mask†
Clock control†
Arbiter control†
0D8h
Arbiter request mask†
Reserved
0DCh
Serial IRQ edge control†
Reserved
Serial IRQ mode control†
0E0h
Serial IRQ status
0E4h
Reserved
0E8h−0FCh
†
One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
4.1 Vendor ID Register
This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to Texas Instruments.
PCI register offset:
Register type:
Default value:
00h
Read-only
104Ch
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
4.2 Device ID Register
This 16-bit read-only register contains the value 8231h, which is the device ID assigned by TI for the bridge.
PCI register offset:
Register type:
Default value:
02h
Read-only
8231h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
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Classic PCI Configuration Space
4.3 Command Register
The command register controls how the bridge behaves on the PCI Express interface. See Table 4−2 for a
complete description of the register contents.
PCI register offset:
Register type:
Default value:
04h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−2. Command Register Description
DESCRIPTION
BIT
FIELD NAME
ACCESS
15:11
RSVD
R
Reserved. Returns 00000b when read.
INTx disable. This bit enables device specific interrupts. Since the bridge does not generate any
internal interrupts, this bit is read-only 0b.
10
9
INT_DISABLE
FBB_ENB
R
R
Fast back-to-back enable. The bridge does not generate fast back-to-back transactions;
therefore, this bit returns 0b when read.
SERR enable bit. When this bit is set, the bridge can signal fatal and nonfatal errors on the PCI
Express interface on behalf of SERR assertions detected on the PCI bus.
8
7
SERR_ENB
STEP_ENB
RW
R
0 = Disable the reporting of nonfatal errors and fatal errors (default)
1 = Enable the reporting of nonfatal errors and fatal errors
Address/data stepping control. The bridge does not support address/data stepping, and this bit is
hardwired to 0b.
Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see Section 4.4) in
response to a received poisoned TLP from PCI Express. A received poisoned TLP is forwarded
with bad parity to conventional PCI regardless of the setting of this bit.
6
PERR_ENB
RW
0 = Disables the setting of the master data parity error bit (default)
1 = Enables the setting of the master data parity error bit
VGA palette snoop enable. The bridge does not support VGA palette snooping; therefore, this bit
returns 0b when read.
5
4
3
VGA_ENB
MWI_ENB
SPECIAL
R
RW
R
Memory write and invalidate enable. When this bit is set, the bridge translates PCI Express
memory write requests into memory write and invalidate transactions on the PCI interface.
0 = Disable the promotion to memory write and invalidate (default)
1 = Enable the promotion to memory write and invalidate
Special cycle enable. The bridge does not respond to special cycle transactions; therefore, this
bit returns 0b when read.
Bus master enable. When this bit is set, the bridge is enabled to initiate transactions on the PCI
Express interface.
0 = PCI Express interface cannot initiate transactions. The bridge must disable the response
to memory and I/O transactions on the PCI interface (default).
1 = PCI Express interface can initiate transactions. The bridge can forward memory and I/O
transactions from PCI secondary interface to the PCI Express interface.
2
1
0
MASTER_ENB
MEMORY_ENB
IO_ENB
RW
RW
RW
Memory space enable. Setting this bit enables the bridge to respond to memory transactions on
the PCI Express interface.
0 = PCI Express receiver cannot process downstream memory transactions and must
respond with an unsupported request (default)
1 = PCI Express receiver can process downstream memory transactions. The bridge can
forward memory transactions to the PCI interface.
I/O space enable. Setting this bit enables the bridge to respond to I/O transactions on the PCI
Express interface.
0 = PCI Express receiver cannot process downstream I/O transactions and must respond
with an unsupported request (default)
1 = PCI Express receiver can process downstream I/O transactions. The bridge can forward
I/O transactions to the PCI interface.
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4.4 Status Register
The status register provides information about the PCI Express interface to the system. See Table 4−3 for a
complete description of the register contents.
PCI register offset:
Register type:
Default value:
06h
Read-only, Read/Clear
0010h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Table 4−3. Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP. This
bit is set regardless of the state of bit 6 (PERR_ENB) in the command register (offset 04h, see
Section 4.3).
15
PAR_ERR
RCU
0 = No parity error detected
1 = Parity error detected
Signaled system error. This bit is set when the bridge sends an ERR_FATAL or ERR_NONFATAL
message and bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set.
14
13
12
SYS_ERR
MABORT
RCU
RCU
RCU
0 = No error signaled
1 = ERR_FATAL or ERR_NONFATAL signaled
Received master abort. This bit is set when the PCI Express interface of the bridge receives a
completion-with-unsupported-request status.
0 = Unsupported request not received on the PCI Express interface
1 = Unsupported request received on the PCI Express interface
Received target abort. This bit is set when the PCI Express interface of the bridge receives a
completion-with-completer-abort status.
TABORT_REC
0 = Completer abort not received on the PCI Express interface
1 = Completer abort received on the PCI Express interface
Signaled target abort. This bit is set when the PCI Express interface completes a request with
completer abort status.
11
TABORT_SIG
PCI_SPEED
RCU
R
0 = Completer abort not signaled on the PCI Express interface
1 = Completer abort signaled on the PCI Express interface
10:9
DEVSEL timing. These bits are read-only 00b, because they do not apply to PCI Express.
Master data parity error. This bit is set if bit 6 (PERR_ENB) in the command register (offset 04h,
see Section 4.3) is set and the bridge receives a completion with data marked as poisoned on the
PCI Express interface or poisons a write request received on the PCI Express interface.
8
DATAPAR
RCU
0 = No uncorrectable data error detected on the primary interface
1 = Uncorrectable data error detected on the primary interface
Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express device
and is hardwired to 0b.
7
6
5
FBB_CAP
RSVD
R
R
R
Reserved. Returns 0b when read.
66-MHz capable. This bit does not have a meaningful context for a PCI Express device and is
hardwired to 0b.
66MHZ
Capabilities list. This bit returns 1b when read, indicating that the bridge supports additional PCI
capabilities.
4
CAPLIST
R
Interrupt status. This bit reflects the interrupt status of the function. This bit is read-only 0b since
the bridge does not generate any interrupts internally.
3
INT_STATUS
RSVD
R
R
2:0
Reserved. Returns 000b when read.
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4.5 Class Code and Revision ID Register
This read-only register categorizes the base class, subclass, and programming interface of the bridge. The
base class is 06h, identifying the device as a bridge. The subclass is 04h, identifying the function as a
PCI-to-PCI bridge, and the programming interface is 00h. Furthermore, the TI device revision is indicated in
the lower byte (03h). See Table 4−4 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
08h
Read-only
0604 0003
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Table 4−4. Class Code and Revision ID Register Description
BIT
31:24
23:16
15:8
7:0
FIELD NAME
BASECLASS
SUBCLASS
PGMIF
ACCESS
DESCRIPTION
Base class. This field returns 06h when read, which classifies the function as a bridge device.
R
R
R
R
Subclass. This field returns 04h when read, which classifies the function as a PCI-to-PCI bridge.
Programming interface. This field returns 00h when read.
CHIPREV
Silicon revision. This field returns the silicon revision of the function.
4.6 Cache Line Size Register
This read/write cache line size register is used by the bridge to determine how much data to prefetch when
handling delayed read transactions. The value in this register must be programmed to a power of 2. Any written
odd value (bit 0 = 1b) or value greater than 32 DWORDs is treated as 0 DWORDs.
PCI register offset:
Register type:
Default value:
0Ch
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.7 Primary Latency Timer Register
This read-only register has no meaningful context for a PCI Express device and returns the value 00h when
read.
PCI register offset:
Register type:
Default value:
0Dh
Read-only
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.8 Header Type Register
This read-only register indicates that this function has a type one PCI header. Bit 7 of this register is 0b
indicating that the bridge is a single-function device.
PCI register offset:
Register type:
Default value:
0Eh
Read-only
01h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
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4.9 BIST Register
Since the bridge does not support a built-in self test (BIST), this read-only register returns the value of 00h
when read.
PCI register offset:
Register type:
Default value:
0Fh
Read-only
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.10 Device Control Base Address Register
This register programs the memory base address that acesses the device control registers. By default, this
register is read only. If bit 5 of the Control and Diagnostic Register 2 (offset C8h) is set, then the bits 31:12
of this register become read/write. See Table 4−5 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
10h
Read-only, Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−5. Device Control Base Address Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Memory base address. The memory address field for the bridge uses 20 read/write bits indicating
that 4096 bytes is the amount of memory space that is reserved. These bits are read only if
Register C8h bit 5 is clear. If bit 5 is set, then these bits become Read/Write.
31:12
ADDRESS
R,R/W
11:4
3
RSVD
R
R
Reserved. These bits are read-only and return 00h when read.
PRE_FETCH
Prefetchable. This bit is read-only 0b indicating that this memory window is not prefetchable.
Memory type. This field is read-only 00b indicating that this window can be located anywhere in the
32-bit address space.
2:1
0
MEM_TYPE
MEM_IND
R
R
Memory space indicator. This field returns 0b indicating that memory space is used.
4.11 Primary Bus Number Register
This read/write register specifies the bus number of the PCI bus segment that the PCI Express interface is
connected to.
PCI register offset:
Register type:
Default value:
18h
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
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4.12 Secondary Bus Number Register
This read/write register specifies the bus number of the PCI bus segment that the PCI interface is connected
to. The bridge uses this register to determine how to respond to a type 1 configuration transaction.
PCI register offset:
Register type:
Default value:
19h
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.13 Subordinate Bus Number Register
This read/write register specifies the bus number of the highest number PCI bus segment that is downstream
of the bridge. The bridge uses this register to determine how to respond to a type 1 configuration transaction.
PCI register offset:
Register type:
Default value:
1Ah
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.14 Secondary Latency Timer Register
This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock cycles.
PCI register offset:
Register type:
Default value:
1Bh
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.15 I/O Base Register
This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream.
See Table 4−6 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
1Ch
Read-only, Read/Write
01h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Table 4−6. I/O Base Register Description
BIT
7:4
3:0
FIELD NAME
IOBASE
ACCESS
DESCRIPTION
I/O base. Defines the bottom address of the I/O address range that determines when to forward I/O
transactions from one interface to the other. These bits correspond to address bits [15:12] in the
I/O address. The lower 12 bits are assumed to be 000h. The 16 bits corresponding to address bits
[31:16] of the I/O address are defined in the I/O base upper 16 bits register (offset 30h, see
Section 4.24).
RW
R
IOTYPE
I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.
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4.16 I/O Limit Register
This read/write register specifies the upper limit of the I/O addresses that the bridge forwards downstream.
See Table 4−7 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
1Dh
Read-only, Read/Write
01h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Table 4−7. I/O Limit Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
I/O limit. Defines the top address of the I/O address range that determines when to forward I/O
transactions from one interface to the other. These bits correspond to address bits [15:12] in the
I/O address. The lower 12 bits are assumed to be FFFh. The 16 bits corresponding to address bits
[31:16] of the I/O address are defined in the I/O limit upper 16 bits register (offset 32h, see
Section 4.25).
7:4
IOLIMIT
RW
3:0
IOTYPE
R
I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.
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4.17 Secondary Status Register
The secondary status register provides information about the PCI bus interface. See Table 4−8 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
1Eh
Read-only, Read/Clear
02X0h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
1
0
x
0
0
0
0
0
Table 4−8. Secondary Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15
PAR_ERR
RCU
Detected parity error. This bit reports the detection of an uncorrectable address, attribute, or data
error by the bridge on its secondary interface. This bit must be set when any of the following three
conditions are true:
•
•
•
The bridge detects an uncorrectable address or attribute error as a potential target.
The bridge detects an uncorrectable data error when it is the target of a write transaction.
The bridge detects an uncorrectable data error when it is the master of a read transaction
(immediate read data).
The bit is set irrespective of the state of bit 0 (PERR_EN) in the bridge control register at offset 3Eh
(see Section 4.29).
0 = Uncorrectable address, attribute, or data error not detected on secondary interface
1 = Uncorrectable address, attribute, or data error detected on secondary interface
14
13
SYS_ERR
MABORT
RCU
RCU
Received system error. This bit is set when the bridge detects an SERR assertion.
0 = No error asserted on the PCI interface
1 = SERR asserted on the PCI interface
Received master abort. This bit is set when the PCI interface of the bridge reports the detection of
a master abort termination by the bridge when it is the master of a transaction on its secondary
interface.
0 = Master abort not received on the PCI interface
1 = Master abort received on the PCI interface
12
11
TABORT_REC
TABORT_SIG
RCU
RCU
Received target abort. This bit is set when the PCI interface of the bridge receives a target abort.
0 = Target abort not received on the PCI interface
1 = Target abort received on the PCI interface
Signaled target abort. This bit reports the signaling of a target abort termination by the bridge when
it responds as the target of a transaction on its secondary interface.
0 = Target abort not signaled on the PCI interface
1 = Target abort signaled on the PCI interface
10:9
8
PCI_SPEED
DATAPAR
R
DEVSEL timing. These bits are 01b indicating that this is a medium speed decoding device.
RCU
Master data parity error. This bit is set if the bridge is the bus master of the transaction on the PCI
bus, bit 0 (PERR_EN) in the bridge control register (offset 3Eh see Section 4.29) is set, and the
bridge either asserts PERR on a read transaction or detects PERR asserted on a write transaction.
0 = No data parity error detected on the PCI interface
1 = Data parity error detected on the PCI interface
7
FBB_CAP
R
Fast back-to-back capable. This bit returns a 1b when read indicating that the secondary PCI
interface of bridge supports fast back-to-back transactions.
6
5
RSVD
R
R
Reserved. Returns 0b when read.
66MHZ
66-MHz capable. The bridge can operate at a maximum CLK frequency of 66 MHz; therefore, this
bit reflects the state of the M66EN terminal.
4:0
RSVD
R
Reserved. Returns 00000b when read.
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4.18 Memory Base Register
This read/write register specifies the lower limit of the memory addresses that the bridge forwards
downstream. See Table 4−9 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
20h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−9. Memory Base Register Description
BIT
15:4
3:0
FIELD NAME
MEMBASE
RSVD
ACCESS
DESCRIPTION
Memory base. Defines the lowest address of the memory address range that determines when to
forward memory transactions from one interface to the other. These bits correspond to address bits
[31:20] in the memory address. The lower 20 bits are assumed to be 00000h.
RW
R
Reserved. Returns 0h when read.
4.19 Memory Limit Register
This read/write register specifies the upper limit of the memory addresses that the bridge forwards
downstream. See Table 4−10 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
22h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−10. Memory Limit Register Description
BIT
15:4
3:0
FIELD NAME
MEMLIMIT
RSVD
ACCESS
DESCRIPTION
Memory limit. Defines the highest address of the memory address range that determines when to
forward memory transactions from one interface to the other. These bits correspond to address bits
[31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh.
RW
R
Reserved. Returns 0h when read.
4.20 Prefetchable Memory Base Register
This read/write register specifies the lower limit of the prefetchable memory addresses that the bridge forwards
downstream. See Table 4−11 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
24h
Read-only, Read/Write
0001h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 4−11. Prefetchable Memory Base Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Prefetchable memory base. Defines the lowest address of the prefetchable memory address range
that determines when to forward memory transactions from one interface to the other. These bits
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be
00000h. The prefetchable base upper 32 bits register (offset 28h, see Section 4.22) specifies
bits [63:32] of the 64-bit prefetchable memory address.
15:4
PREBASE
RW
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
3:0
64BIT
R
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4.21 Prefetchable Memory Limit Register
This read/write register specifies the upper limit of the prefetchable memory addresses that the bridge
forwards downstream. See Table 4−12 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
26h
Read-only, Read/Write
0001h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 4−12. Prefetchable Memory Limit Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Prefetchable memory limit. Defines the highest address of the prefetchable memory address range
that determines when to forward memory transactions from one interface to the other. These bits
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be
FFFFFh. The prefetchable limit upper 32 bits register (offset 2Ch, see Section 4.23) specifies bits
[63:32] of the 64-bit prefetchable memory address.
15:4
PRELIMIT
RW
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
3:0
64BIT
R
4.22 Prefetchable Base Upper 32-Bit Register
This read/write register specifies the upper 32 bits of the prefetchable memory base register. See Table 4−13
for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
28h
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−13. Prefetchable Base Upper 32-Bit Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Prefetchable memory base upper 32 bits. Defines the upper 32 bits of the lowest address of the
prefetchable memory address range that determines when to forward memory transactions
downstream.
31:0
PREBASE
RW
4.23 Prefetchable Limit Upper 32-Bit Register
This read/write register specifies the upper 32 bits of the prefetchable memory limit register. See Table 4−14
for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
2Ch
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−14. Prefetchable Limit Upper 32-Bit Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Prefetchable memory limit upper 32 bits. Defines the upper 32 bits of the highest address of the
prefetchable memory address range that determines when to forward memory transactions
downstream.
31:0
PRELIMIT
RW
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4.24 I/O Base Upper 16-Bit Register
This read/write register specifies the upper 16 bits of the I/O base register. See Table 4−15 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
30h
Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−15. I/O Base Upper 16-Bit Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
I/O base upper 16 bits. Defines the upper 16 bits of the lowest address of the I/O address range
15:0
IOBASE
RW
that determines when to forward I/O transactions downstream. These bits correspond to address
bits [31:20] in the I/O address. The lower 20 bits are assumed to be 00000h.
4.25 I/O Limit Upper 16-Bit Register
This read/write register specifies the upper 16 bits of the I/O limit register. See Table 4−16 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
32h
Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−16. I/O Limit Upper 16-Bit Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
I/O limit upper 16 bits. Defines the upper 16 bits of the top address of the I/O address range that
determines when to forward I/O transactions downstream. These bits correspond to address
bits [31:20] in the I/O address. The lower 20 bits are assumed to be FFFFFh.
15:0
IOLIMIT
RW
4.26 Capabilities Pointer Register
This read-only register provides a pointer into the PCI configuration header where the PCI power management
block resides. Since the PCI power management registers begin at 50h, this register is hardwired to 50h.
PCI register offset:
Register type:
Default value:
34h
Read-only
50h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
0
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Classic PCI Configuration Space
4.27 Interrupt Line Register
This read/write register is programmed by the system and indicates to the software which interrupt line the
bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet
been assigned to the function. Since the bridge does not generate interrupts internally, this register is a scratch
pad register.
PCI register offset:
Register type:
Default value:
3Ch
Read/Write
FFh
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
4.28 Interrupt Pin Register
The interrupt pin register is read-only 00h indicating that the bridge does not generate internal interrupts. While
the bridge does not generate internal interrupts, it does forward interrupts from the secondary interface to the
primary interface.
PCI register offset:
Register type:
Default value:
3Dh
Read-only
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.29 Bridge Control Register
The bridge control register provides extensions to the command register that are specific to a bridge. See
Table 4−17 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
3Eh
Read-only, Read/Write, Read/Clear
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−17. Bridge Control Register Description
BIT
15:12
11
FIELD NAME
RSVD
ACCESS
DESCRIPTION
R
Reserved. Returns 0h when read.
DTSERR
RW
Discard timer SERR enable. Applies only in conventional PCI mode. This bit enables the bridge to
generate either an ERR_NONFATAL (by default) or ERR_FATAL transaction on the primary
interface when the secondary discard timer expires and a delayed transaction is discarded from a
queue in the bridge. The severity is selectable only if advanced error reporting is supported.
0 = Do not generate ERR_NONFATAL or ERR_FATAL on the primary interface as a result of
the expiration of the secondary discard timer. Note that an error message can still be sent if
advanced error reporting is supported and bit 10 (DISCARD_TIMER_MASK) in the
secondary uncorrectable error mask register (offset 130h, see Section 5.11) is clear
(default).
1 = Generate ERR_NONFATAL or ERR_FATAL on the primary interface if the secondary
discard timer expires and a delayed transaction is discarded from a queue in the bridge
10
DTSTATUS
RCU
Discard timer status. This bit indicates if a discard timer expires and a delayed transaction is
discarded.
0 = No discard timer error
1 = Discard timer error
61
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Table 4−17. Bridge Control Register Description (Continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
9
SEC_DT
RW
Selects the number of PCI clocks that the bridge waits for a master on the secondary interface to
repeat a delayed transaction request. The counter starts once the delayed completion (the
completion of the delayed transaction on the primary interface) has reached the head of the
downstream queue of the bridge (i.e., all ordering requirements have been satisfied and the bridge
is ready to complete the delayed transaction with the initiating master on the secondary bus). If the
master does not repeat the transaction before the counter expires, then the bridge deletes the
delayed transaction from its queue and sets the discard timer status bit.
15
0 = The secondary discard timer counts 2 PCI clock cycles (default)
10
1 = The secondary discard timer counts 2 PCI clock cycles
8
7
PRI_DEC
FBB_EN
R
Primary discard timer. This bit has no meaning in PCI Express and is hardwired to 0b.
RW
Fast back-to-back enable. This bit allows software to enable fast back-to-back transactions on the
secondary PCI interface.
0 = Fast back-to-back transactions are disabled (default)
1 = Secondary interface fast back-to-back transactions are enabled
6
5
SRST
MAM
RW
RW
Secondary bus reset. This bit is set when software wishes to reset all devices downstream of the
bridge. Setting this bit causes the PRST terminal on the secondary interface to be asserted.
0 = Secondary interface is not in reset state (default)
1 = Secondary interface is in the reset state
Master abort mode. This bit controls the behavior of the bridge when it receives a master abort or
an unsupported request.
0 = Do not report master aborts. Returns FFFF FFFFh on reads and discards data on writes
(default).
1 = Respond with an unsupported request on PCI Express when a master abort is received on
PCI. Respond with target abort on PCI when an unsupported request completion on PCI
Express is received. This bit also enables error signaling on master abort conditions on
posted writes.
4
3
VGA16
VGA
RW
RW
VGA 16-bit decode. This bit enables the bridge to provide full 16-bit decoding for VGA I/O
addresses. This bit only has meaning if the VGA enable bit is set.
0 = Ignore address bits [15:10] when decoding VGA I/O addresses (default)
1 = Decode address bits [15:10] when decoding VGA I/O addresses
VGA enable. This bit modifies the response by the bridge to VGA compatible addresses. If this bit
is set, then the bridge decodes and forwards the following accesses on the primary interface to the
secondary interface (and, conversely, block the forwarding of these addresses from the secondary
to primary interface):
•
•
Memory accesses in the range 000A 0000h to 000B FFFFh
I/O addresses in the first 64 KB of the I/O address space (address bits [31:16] are 0000h) and
where address bits [9:0] are in the range of 3B0h to 3BBh or 3C0h to 3DFh (inclusive of ISA
address aliases – address bits [15:10] may possess any value and are not used in the decoding)
If this bit is set, then forwarding of VGA addresses is independent of the value of bit 2 (ISA), the I/O
address and memory address ranges defined by the I/O base and limit registers, the memory base
and limit registers, and the prefetchable memory base and limit registers of the bridge. The
forwarding of VGA addresses is qualified by bits 0 (IO_ENB) and 1 (MEMORY_ENB) in the
command register (offset 04h, see Section 4.3).
0 = Do not forward VGA compatible memory and I/O addresses from the primary to secondary
interface (addresses defined above) unless they are enabled for forwarding by the defined
I/O and memory address ranges (default)
1 = Forward VGA compatible memory and I/O addresses (addresses defined above) from the
primary interface to the secondary interface (if the I/O enable and memory enable bits are
set) independent of the I/O and memory address ranges and independent of the ISA enable
bit
62
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Classic PCI Configuration Space
Table 4−17. Bridge Control Register Description (Continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
2
ISA
RW
ISA enable. This bit modifies the response by the bridge to ISA I/O addresses. This applies only to
I/O addresses that are enabled by the I/O base and I/O limit registers and are in the first 64 KB of
PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, then the bridge blocks any
forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each
1 KB block. In the opposite direction (secondary to primary), I/O transactions are forwarded if they
address the last 768 bytes in each 1K block.
0 = Forward downstream all I/O addresses in the address range defined by the I/O base and
I/O limit registers (default)
1 = Forward upstream ISA I/O addresses in the address range defined by the I/O base and I/O
limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each
1-KB block)
1
SERR_EN
RW
SERR enable. This bit controls forwarding of system error events from the secondary interface to
the primary interface. The bridge forwards system error events when:
•
•
•
This bit is set
Bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set
SERR is asserted on the secondary interface
0 = Disable the forwarding of system error events (default)
1 = Enable the forwarding of system error events
0
PERR_EN
RW
Parity error response enable. Controls the bridge’s response to data, uncorrectable address, and
attribute errors on the secondary interface. Also, the bridge always forwards data with poisoning,
from conventional PCI to PCI Express on an uncorrectable conventional PCI data error, regardless
of the setting of this bit.
0 = Ignore uncorrectable address, attribute, and data errors on the secondary interface
(default)
1 = Enable uncorrectable address, attribute, and data error detection and reporting on the
secondary interface
4.30 Capability ID Register
This read-only register identifies the linked list item as the register for PCI power management. The register
returns 01h when read.
PCI register offset:
Register type:
Default value:
50h
Read-only
01h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
4.31 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 60h pointing to the MSI capabilities registers.
PCI register offset:
Register type:
Default value:
51h
Read-only
60h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
1
1
0
0
0
0
0
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4.32 Power Management Capabilities Register
This read-only register indicates the capabilities of the bridge related to PCI power management. See
Table 4−18 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
52h
Read-only
0602h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
Table 4−18. Power Management Capabilities Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
PME support. This 5-bit field indicates the power states from which the bridge may assert PME.
Because the bridge never generates a PME except on a behalf of a secondary device, this field
is read-only and returns 00000b.
15:11
PME_SUPPORT
R
10
9
D2_SUPPORT
D1_SUPPORT
R
R
This bit returns a 1b when read, indicating that the function supports the D2 device power state.
This bit returns a 1b when read, indicating that the function supports the D1 device power state.
3.3 V
AUX
auxiliary current requirements. This field returns 000b since the bridge does not
8:6
AUX_CURRENT
R
generate PME from D3
.
cold
Device specific initialization. This bit returns 0b when read, indicating that the bridge does not
require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
5
DSI
R
4
3
RSVD
R
R
Reserved. Returns 0b when read.
PME_CLK
PME clock. This bit returns 0b indicating that the PCI clock is not needed to generate PME.
Power management version. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register
(offset D4h, see Section 4.65) is 0b, then this field returns 010b indicating revision 1.1
compatibility. If PCI_PM_VERSION_CTRL is 1b, then this field returns 011b indicating revision
1.2 compatibility.
2:0
PM_VERSION
R
64
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4.33 Power Management Control/Status Register
This register determines and changes the current power state of the bridge. No internal reset is generated
when transitioning from the D3
register contents.
state to the D0 state. See Table 4−19 for a complete description of the
hot
PCI register offset:
Register type:
Default value:
54h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−19. Power Management Control/Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15
PME_STAT
R
PME status. This bit is read-only and returns 0b when read.
Data scale. This 2-bit field returns 00b when read since the bridge does not use the data
register.
14:13
12:9
DATA_SCALE
DATA_SEL
R
R
Data select. This 4-bit field returns 0h when read since the bridge does not use the data
register.
PME enable. This bit has no function and acts as scratchpad space. The default value for this
bit is 0b.
8
PME_EN
RSVD
RW
R
7:4
Reserved. Returns 0h when read.
No soft reset. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register (offset D4h,
see Section 4.65) is 0b, then this bit returns 0b for compatibility with version 1.1 of the PCI
Power Management Specification. If PCI_PM_VERSION_CTRL is 1b, then this bit returns 1b
indicating that no internal reset is generated and the device retains its configuration context
3
2
NO_SOFT_RESET
RSVD
R
R
when transitioning from the D3
hot
state to the D0 state.
Reserved. Returns 0b when read.
Power state. This 2-bit field determines the current power state of the function and sets the
function into a new power state. This field is encoded as follows:
00 = D0 (default)
01 = D1
1:0
PWR_STATE
RW
10 = D2
11 = D3
hot
4.34 Power Management Bridge Support Extension Register
This read-only register indicates to host software what the state of the secondary bus will be when the bridge
is placed in D3. See Table 4−20 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
56h
Read-only
40h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
Table 4−20. Power Management Bridge Support Extension Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Bus power/clock control enable. This bit indicates to the host software if the bus secondary clocks
are stopped when the bridge is placed in D3. The state of the BPCC bit is controlled by bit 11
(BPCC_E) in the general control register (offset D4h, see Section 4.65).
7
BPCC
R
0 = The secondary bus clocks are not stopped in D3
1 = The secondary bus clocks are stopped in D3
6
BSTATE
RSVD
R
R
B2/B3 support. This bit is read-only 1b indicating that the bus state in D3 is B2.
Reserved. Returns 00 0000b when read.
5:0
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4.35 Power Management Data Register
The read-only register is not applicable to the bridge and returns 00h when read.
PCI register offset:
Register type:
Default value:
57h
Read-only
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.36 MSI Capability ID Register
This read-only register identifies the linked list item as the register for message signaled interrupts capabilities.
The register returns 05h when read.
PCI register offset:
Register type:
Default value:
60h
Read-only
05h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
1
4.37 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 80h pointing to the subsystem ID capabilities registers.
PCI register offset:
Register type:
Default value:
61h
Read-only
80h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
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4.38 MSI Message Control Register
This register controls the sending of MSI messages. See Table 4−21 for a complete description of the register
contents.
PCI register offset:
Register type:
Default value:
62h
Read-only, Read/Write
0088h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
Table 4−21. MSI Message Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:8
RSVD
R
Reserved. Returns 00h when read.
64-bit message capability. This bit is read-only 1b indicating that the bridge supports 64-bit MSI
message addressing.
7
64CAP
R
Multiple message enable. This bit indicates the number of distinct messages that the bridge is
allowed to generate.
000 = 1 message (default)
001 = 2 messages
010 = 4 messages
011 = 8 messages
100 = 16 messages
101 = Reserved
6:4
MM_EN
RW
110 = Reserved
111 = Reserved
Multiple message capabilities. This field indicates the number of distinct messages that bridge is
3:1
0
MM_CAP
MSI_EN
R
capable of generating. This field is read-only 100b indicating that the bridge can signal 1 interrupt
for each IRQ supported on the serial IRQ stream up to a maximum of 16 unique interrupts.
MSI enable. This bit enables MSI interrupt signaling. MSI signaling must be enabled by software
for the bridge to signal that a serial IRQ has been detected.
RW
0 = MSI signaling is prohibited (default)
1 = MSI signaling is enabled
4.39 MSI Message Lower Address Register
This register contains the lower 32 bits of the address that a MSI message writes to when a serial IRQ is
detected. See Table 4−22 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
64h
Read-only, Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−22. MSI Message Lower Address Register Description
BIT
31:2
1:0
FIELD NAME
ADDRESS
RSVD
ACCESS
DESCRIPTION
RW
R
System specified message address
Reserved. Returns 00b when read.
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4.40 MSI Message Upper Address Register
This register contains the upper 32 bits of the address that a MSI message writes to when a serial IRQ is
detected. If this register contains 0000 0000h, then 32-bit addressing is used; otherwise, 64-bit addressing
is used.
PCI register offset:
Register type:
Default value:
68h
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.41 MSI Message Data Register
This register contains the data that software programmed the bridge to send when it send a MSI message.
See Table 4−23 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
6Ch
Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−23. MSI Message Data Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
System specific message. This field contains the portion of the message that the bridge forwards
unmodified.
15:4
MSG
RW
Message number. This portion of the message field may be modified to contain the message
number is multiple messages are enable. The number of bits that are modifiable depends on the
number of messages enabled in the message control register.
1 message = No message data bits can be modified (default)
2 messages = Bit 0 can be modified
3:0
MSG_NUM
RW
4 messages = Bits 1:0 can be modified
8 messages = Bits 2:0 can be modified
16 messages = Bits 3:0 can be modified
4.42 Capability ID Register
This read-only register identifies the linked list item as the register for subsystem ID and subsystem vendor
ID capabilities. The register returns 0Dh when read.
PCI register offset:
Register type:
Default value:
80h
Read-only
0Dh
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
1
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4.43 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 90h pointing to the PCI Express capabilities registers.
PCI register offset:
Register type:
Default value:
81h
Read-only
90h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
4.44 Subsystem Vendor ID Register
This register, used for system and option card identification purposes, may be required for certain operating
systems. This read-only register is initialized through the EEPROM and can be written through the subsystem
alias register. This register is reset by a PCI Express reset (PERST), a GRST, or the internally-generated
power-on reset.
PCI register offset:
Register type:
Default value:
84h
Read-only
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.45 Subsystem ID Register
This register, used for system and option card identification purposes, may be required for certain operating
systems. This read-only register is initialized through the EEPROM and can be written through the subsystem
alias register. This register is reset by a PCI Express reset (PERST), a GRST, or the internally-generated
power-on reset.
PCI register offset:
Register type:
Default value:
86h
Read-only
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.46 PCI Express Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express capabilities. The register
returns 10h when read.
PCI register offset:
Register type:
Default value:
90h
Read-only
10h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
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4.47 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 00h indicating no additional capabilities are supported.
PCI register offset:
Register type:
Default value:
91h
Read-only
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.48 PCI Express Capabilities Register
This read-only register indicates the capabilities of the bridge related to PCI Express. See Table 4−24 for a
complete description of the register contents.
PCI register offset:
Register type:
Default value:
92h
Read-only
0071h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
Table 4−24. PCI Express Capabilities Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:14
RSVD
R
Reserved. Returns 00b when read.
Interrupt message number. This field is used for MSI support and is implemented as read-only
00000b in the bridge.
13:9
8
INT_NUM
SLOT
R
R
R
R
Slot implemented. This bit is not valid for the bridge and is read-only 0b.
Device/port type. This read-only field returns 7h indicating that the device is a PCI Express-to-PCI
bridge.
7:4
3:0
DEV_TYPE
VERSION
Capability version. This field returns 1h indicating revision 1 of the PCI Express capability.
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4.49 Device Capabilities Register
The device capabilities register indicates the device specific capabilities of the bridge. See Table 4−25 for a
complete description of the register contents.
PCI register offset:
Register type:
Default value:
94h
Read-only
0000 0D82
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
0
Table 4−25. Device Capabilities Register Description
BIT
FIELD NAME
RSVD
ACCESS
DESCRIPTION
31:28
27:26
R
Reserved. Returns 0h when read.
Captured slot power limit scale. The value in this field is programmed by the host by issuing a
CSPLS
RU
Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 9:8 are
written to this field. The value in this field specifies the scale used for the slot power limit.
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x
25:18
CSPLV
RU
Captured slot power limit value. The value in this field is programmed by the host by issuing a
Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 7:0 are
written to this field. The value in this field in combination with the slot power limit scale value
(bits 27:26) specifies the upper limit of power supplied to the slot. The power limit is calculated by
multiplying the value in this field by the value in the slot power limit scale field.
17:15
14
RSVD
PIP
R
R
Reserved. Returns 000b when read.
Power indicator present. This bit is hardwired to 0b indicating that a power indicator is not
implemented.
13
12
AIP
ABP
R
R
Attention indicator present. This bit is hardwired to 0b indicating that an attention indicator is not
implemented.
Attention button present. This bit is hardwired to 0b indicating that an attention button is not
implemented.
11:9
EP_L1_LAT
RU
Endpoint L1 acceptable latency. This field indicates the maximum acceptable latency for a
transition from L1 to L0 state. This field can be programmed by writing to the L1_LATENCY field
(bits 15:13) in the general control register (offset D4h, see Section 4.65). The default value for this
field is 110b which indicates a range from 32 µs to 64 µs. This field cannot be programmed to be
less than the latency for the PHY to exit the L1 state.
8:6
EP_L0S_LAT
RU
Endpoint L0s acceptable latency. This field indicates the maximum acceptable latency for a
transition from L0s to L0 state. This field can be programmed by writing to the L0s_LATENCY field
(bits 18:16) in the general control register (offset D4h, see Section 4.65). The default value for this
field is 110b which indicates a range from 2 µs to 4 µs. This field cannot be programmed to be less
than the latency for the PHY to exit the L0s state.
5
ETFS
PFS
R
R
Extended tag field supported. This field indicates the size of the tag field not supported.
4:3
Phantom functions supported. This field is read-only 00b indicating that function numbers are not
used for phantom functions.
2:0
MPSS
R
Maximum payload size supported. This field indicates the maximum payload size that the device
can support for TLPs. This field is encoded as 010b indicating the maximum payload size for a TLP
is 512 bytes.
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4.50 Device Control Register
The device control register controls PCI Express device specific parameters. See Table 4−26 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
98h
Read-only, Read/Write
2800h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
Table 4−26. Device Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Configuration retry status enable. When this read/write bit is set to 1b, the bridge returns a
completion with completion retry status on PCI Express if a configuration transaction forwarded
to the secondary interface did not complete within the implementation specific time-out period.
When this bit is set to 0b, the bridge does not generate completions with completion retry status
on behalf of configuration transactions. The default value of this bit is 0b.
15
CFG_RTRY_ENB
RW
Maximum read request size. This field is programmed by host software to set the maximum size
of a read request that the bridge can generate. The bridge uses this field in conjunction with the
cache line size register (offset 0Ch, see Section 4.6) to determine how much data to fetch on a
read request. This field is encoded as:
000 = 128B
001 = 256B
010 = 512B (default)
011 = 1024B
14:12
MRRS
RW
100 = 2048B
101 = 4096B
110 = Reserved
111 = Reserved
Enable no snoop. Controls the setting of the no snoop flag within the TLP header for upstream
memory transactions mapped to any traffic class mapped to a virtual channel (VC) other than
VC0 through the upstream decode windows.
11
ENS
RW
RW
0 = No snoop field is 0b
1 = No snoop field is 1b (default)
Auxiliary power PM enable. This bit has no effect in the bridge.
k
10
APPE
0 = AUX power is disabled (default)
1 = AUX power is enabled
Phantom function enable. Since the bridge does not support phantom functions, this bit is
read-only 0b.
9
8
PFE
R
R
Extended tag field enable. Since the bridge does not support extended tags, this bit is read-only
0b.
ETFE
Maximum payload size. This field is programmed by host software to set the maximum size of
posted writes or read completions that the bridge can initiate. This field is encoded as:
000 = 128B (default)
001 = 256B
010 = 512B
011 = 1024B
7:5
MPS
RW
100 = 2048B
101 = 4096B
110 = Reserved
111 = Reserved
Enable relaxed ordering. Since the bridge does not support relaxed ordering, this bit is read-only
0b.
4
ERO
R
kThis bit is sticky and must retain its value when the bridge is powered by V
.
AUX
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Table 4−26. Device Control Register Description (Continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Unsupported request reporting enable. If this bit is set, then the bridge sends an ERR_NONFATAL
message to the root complex when an unsupported request is received.
3
URRE
RW
0 = Do not report unsupported requests to the root complex (default)
1 = Report unsupported requests to the root complex
Fatal error reporting enable. If this bit is set, then the bridge is enabled to send ERR_FATAL
messages to the root complex when a system error event occurs.
2
1
0
FERE
NFERE
CERE
RW
RW
RW
0 = Do not report fatal errors to the root complex (default)
1 = Report fatal errors to the root complex
Nonfatal error reporting enable. If this bit is set, then the bridge is enabled to send
ERR_NONFATAL messages to the root complex when a system error event occurs.
0 = Do not report nonfatal errors to the root complex (default)
1 = Report nonfatal errors to the root complex
Correctable error reporting enable. If this bit is set, then the bridge is enabled to send ERR_COR
messages to the root complex when a system error event occurs.
0 = Do not report correctable errors to the root complex (default)
1 = Report correctable errors to the root complex
4.51 Device Status Register
The device status register provides PCI Express device specific information to the system. See Table 4−27
for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
9Ah
Read-only
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−27. Device Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:6
RSVD
R
Reserved. Returns 00 0000 0000b when read.
Transaction pending. This bit is set when the bridge has issued a nonposted transaction that has
not been completed.
5
4
3
PEND
RU
AUX power detected. This bit indicates that AUX power is present.
APD
RU
0 = No AUX power detected
1 = AUX power detected
Unsupported request detected. This bit is set by the bridge when an unsupported request is
received.
URD
RCU
2
1
0
FED
NFED
CED
RCU
RCU
RCU
Fatal error detected. This bit is set by the bridge when a fatal error is detected.
Nonfatal error detected. This bit is set by the bridge when a nonfatal error is detected.
Correctable error detected. This bit is set by the bridge when a correctable error is detected.
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4.52 Link Capabilities Register
The link capabilities register indicates the link specific capabilities of the bridge. See Table 4−28 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
9Ch
Read-only
0002 XC11h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
x
x
x
1
1
0
0
0
0
0
1
0
0
0
1
Table 4−28. Link Capabilities Register Description
BIT
FIELD NAME
PORT_NUM
RSVD
ACCESS
DESCRIPTION
Port number. This field indicates port number for the PCI Express link. This field is read-only 00h
indicating that the link is associated with port 0.
31:24
23:18
R
R
Reserved. Returns 00 0000b when read.
L1 exit latency. This field indicates the time that it takes to transition from the L1 state to the L0
state. Bit 6 (CCC) in the link control register (offset A0h, see Section 4.53) equals 1b for a common
clock and equals 0b for an asynchronous clock.
For a common reference clock, the value of this field is determined by bits 20:18
17:15
L1_LATENCY
R
(L1_EXIT_LAT_ASYNC) of the control and diagnostic register 1 (offset C4h, see Section 4.62).
For an asynchronous reference clock, the value of this field is determined by bits 17:15
(L1_EXIT_LAT_COMMON) of the control and diagnostic register 1 (offset C4h, see Section 4.62).
L0s exit latency. This field indicates the time that it takes to transition from the L0s state to the L0
state. Bit 6 (CCC) in the link control register (offset A0h, see Section 4.53) equals 1b for a common
clock and equals 0b for an asynchronous clock.
For a common reference clock, the value of 011b indicates that the L1 exit latency falls between
256 ns to less than 512 ns.
14:12
11:10
L0S_LATENCY
ASLPMS
R
R
For an asynchronous reference clock, the value of 100b indicates that the L1 exit latency falls
between 512 ns to less than 1 µs.
Active state link PM support. This field indicates the level of active state power management that
the bridge supports. The value 11b indicates support for both L0s and L1 through active state
power management.
Maximum link width. This field is encoded 00 0001b to indicate that the bridge only supports a 1x
PCI Express link.
9:4
3:0
MLW
MLS
R
R
Maximum link speed. This field is encoded 1h to indicate that the bridge supports a maximum link
speed of 2.5 Gb/s.
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4.53 Link Control Register
The link control register controls link specific behavior. See Table 4−29 for a complete description of the
register contents.
PCI register offset:
Register type:
Default value:
A0h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−29. Link Control Register Description
DESCRIPTION
BIT
FIELD NAME
ACCESS
15:8
RSVD
R
Reserved. Returns 00h when read.
Extended synch. This bit forces the bridge to extend the transmission of FTS ordered sets and an
extra TS2 when exiting from L1 prior to entering to L0.
7
6
ES
RW
RW
0 = Normal synch (default)
1 = Extended synch
Common clock configuration. When this bit is set, it indicates that the bridge and the device at the
opposite end of the link are operating with a common clock source. A value of 0b indicates that the
bridge and the device at the opposite end of the link are operating with separate reference clock
sources. The bridge uses this common clock configuration information to report the L0s and L1 exit
latencies.
CCC
0 = Reference clock is asynchronous (default)
1 = Reference clock is common
5
4
RL
LD
R
R
Retrain link. This bit has no function and is read-only 0b.
Link disable. This bit has no function and is read-only 0b.
Read completion boundary. This bit is an indication of the RCB of the root complex. The state of
this bit has no affect on the bridge, since the RCB of the bridge is fixed at 128 bytes.
3
2
RCB
RW
R
0 = 64 bytes (default)
1 = 128 bytes
RSVD
Reserved. Returns 0b when read.
Active state link PM control. This field enables and disables the active state PM.
00 = Active state PM disabled (default)
01 = L0s entry enabled
1:0
ASLPMC
RW
10 = L1 entry enabled
11 = L0s and L1 entry enabled
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4.54 Link Status Register
The link status register indicates the current state of the PCI Express link. See Table 4−30 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
A2h
Read-only
X011h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
x
0
0
0
0
0
0
0
1
0
0
0
1
Table 4−30. Link Status Register Description
DESCRIPTION
BIT
FIELD NAME
ACCESS
15:13
RSVD
R
Reserved. Returns 000b when read.
Slot clock configuration. This bit indicates that the bridge uses the same physical reference clock
that the platform provides on the connector. If the bridge uses an independent clock irrespective of
the presence of a reference on the connector, then this bit must be cleared.
12
SCC
R
0 = Independent 125-MHz reference clock is used
1 = Common 100-MHz reference clock is used
11
10
LT
TE
R
R
R
R
Link training. This bit has no function and is read-only 0b.
Retrain link. This bit has no function and is read-only 0b.
9:4
3:0
NLW
LS
Negotiated link width. This field is read-only 00 0001b indicating the lane width is 1x.
Link speed. This field is read-only 1h indicating the link speed is 2.5 Gb/s.
4.55 Serial-Bus Data Register
The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this
register prior to writing the serial-bus slave address register (offset B2h, see Section 4.57) that initiates the
bus cycle. When reading data from the serial bus, this register contains the data read after bit 5 (REQBUSY)
of the serial-bus control and status register (offset B3h, see Section 4.58) is cleared. This register is reset by
a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
PCI register offset:
Register type:
Default value:
B0h
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.56 Serial-Bus Word Address Register
The value written to the serial-bus word address register represents the word address of the byte being read
from or written to the serial-bus device. The word address is loaded into this register prior to writing the
serial-bus slave address register (offset B2h, see Section 4.57) that initiates the bus cycle. This register is reset
by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
PCI register offset:
Register type:
Default value:
B1h
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
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4.57 Serial-Bus Slave Address Register
The serial-bus slave address register indicates the slave address of the device being targeted by the serial-bus
cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this register initiates the cycle
on the serial interface. See Table 4−31 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
B2h
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4−31. Serial-Bus Slave Address Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write
transaction. The default value for this field is 000 0000b.
7:1†
SLAVE_ADDR
RW
Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.
0†
RW_CMD
RW
0 = A single byte write is requested (default)
1 = A single byte read is requested
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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4.58 Serial-Bus Control and Status Register
The serial-bus control and status register controls the behavior of the serial-bus interface. This register also
provides status information about the state of the serial bus. See Table 4−32 for a complete description of the
register contents.
PCI register offset:
Register type:
Default value:
B3h
Read-only, Read/Write, Read/Clear
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4−32. Serial-Bus Control and Status Register Description
BIT
7†
6
FIELD NAME
PROT_SEL
RSVD
ACCESS
DESCRIPTION
Protocol select. This bit selects the serial-bus address mode used.
RW
R
0 = Slave address and word address are sent on the serial-bus (default)
1 = Only the slave address is sent on the serial-bus
Reserved. Returns 0b when read.
Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle is in
progress.
5†
4†
REQBUSY
ROMBUSY
RU
RU
0 = No serial-bus cycle
1 = Serial-bus cycle in progress
Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the bridge is
downloading register defaults from a serial EEPROM.
0 = No EEPROM activity
1 = EEPROM download in progress
Serial EEPROM detected. This bit enables the serial-bus interface. The value of this bit controls
whether the GPIO4//SCL and GPIO5//SDA terminals are configured as GPIO signals or as
serial-bus signals. This bit is automatically set to 1b when a serial EEPROM is detected.
Note: A serial EEPROM is only detected once following PERST.
3†
SBDETECT
RWU
0 = No EEPROM present, EEPROM load process does not happen. GPIO4//SCL and
GPIO5//SDA terminals are configured as GPIO signals.
1 = EEPROM present, EEPROM load process takes place. GPIO4//SCL and GPIO5//SDA
terminals are configured as serial-bus signals.
Serial-bus test. This bit is used for internal test purposes. This bit controls the clock source for the
serial interface clock.
2†
1†
0†
SBTEST
SB_ERR
RW
RCU
RCU
0 = Serial-bus clock at normal operating frequency ~ 60 kHz (default)
1 = Serial-bus clock frequency increased for test purposes ~ 4 MHz
Serial-bus error. This bit is set when an error occurs during a software-initiated serial-bus cycle.
0 = No error
1 = Serial-bus error
Serial EEPROM load error. This bit is set when an error occurs while downloading registers from a
serial EEPROM.
ROM_ERR
0 = No error
1 = EEPROM load error
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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4.59 GPIO Control Register
This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of
GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO0
(CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). See Table 4−33 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
B4h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−33. GPIO Control Register Description
DESCRIPTION
BIT
FIELD NAME
ACCESS
15:8
RSVD
R
Reserved. Returns 00h when read.
GPIO 7 data direction. This bit selects whether GPIO7 is in input or output mode.
7†
6†
5†
4†
3†
2†
1†
0†
GPIO7_DIR
GPIO6_DIR
GPIO5_DIR
GPIO4_DIR
GPIO3_DIR
GPIO2_DIR
GPIO1_DIR
GPIO0_DIR
RW
RW
RW
RW
RW
RW
RW
RW
0 = Input (default)
1 = Output
GPIO 6 data direction. This bit selects whether GPIO6 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 5 data direction. This bit selects whether GPIO5 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.
0 = Input (default)
1 = Output
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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Classic PCI Configuration Space
4.60 GPIO Data Register
This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO
terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary
functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). The default
value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs. See
Table 4−34 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
B6h
Read-only, Read/Write
00XXh
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
Table 4−34. GPIO Data Register Description
DESCRIPTION
BIT
FIELD NAME
ACCESS
15:8
RSVD
R
Reserved. Returns 00h when read.
GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of GPIO7
when in output mode.
7†
6†
5†
4†
3†
2†
1†
0†
GPIO7_DATA
GPIO6_DATA
GPIO5_DATA
GPIO4_DATA
GPIO3_DATA
GPIO2_DATA
GPIO1_DATA
GPIO0_DATA
RW
RW
RW
RW
RW
RW
RW
RW
GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of GPIO6
when in output mode.
GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of GPIO5
when in output mode.
GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of GPIO4
when in output mode.
GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of GPIO3
when in output mode.
GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of GPIO2
when in output mode.
GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of GPIO1
when in output mode.
GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of GPIO0
when in output mode.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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4.61 Control and Diagnostic Register 0
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−35 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
PCI register offset:
Register type:
Default value:
C0h
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−35. Control and Diagnostic Register 0 Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
This field contains the captured primary bus number
31:24† PRI_BUS_NUM
R
PRI_DEVICE_
23:19†
NUM
R
This field contains the captured primary device number
18:16
15:14†
13:12
11:8†
7
RSVD
RSVD
RSVD
RSVD
RSVD
R
Reserved. Returns 000b when read.
Reserved. Bits 15:14 default to 00b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 00b.
RW
R
Reserved. Returns 00b when read.
Reserved. Bits 11:8 default to 0000b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 0000b.
RW
R
Reserved. Returns 0b when read.
Prefetch 4X enable. This bit sets the prefetch behavior for upstream memory read multiple
transactions. If bit 24 (FORCE_MRM) in the general control register (offset D4h, see Section 4.65)
is set, then all upstream memory read transactions will prefetch the indicated number of cache lines.
If bit 19 (READ_PREFETCH_DIS) in the general control register (offset D4h, see Section 4.65) is
set, then this bit has no effect and only 1 DWORD will be fetched.
6†
PREFETCH_4X
RW
0 = The bridge will prefetch up to 2 cache lines, as defined in the cache line size register (offset
0Ch, see Section 4.6) for upstream memory read multiple (MRM) transactions (default)
1 = The bridge device will prefetch up to 4 cache lines, as defined in the cache line size register
(offset 0Ch, see Section 4.6) for upstream memory read multiple (MRM) transactions.
PCI upstream req−res buffer threshold value. The value in this field controls the buffer space that
must be available for the bridge to accept a PCI bus transaction. If the cache line size is not valid,
then the bridge will use 8 DW for calculating the threshold value
00 = 1 Cacheline + 4 DW (default)
UP_REQ_BUF
_VALUE
5:4†
RW
01 = 1 Cacheline + 8 DW
10 = 1 Cacheline + 12 DW
11 = 2 Cachelines + 4 DW
PCI upstream req-res buffer threshold control. This bit enables the PCI upstream req-res buffer
threshold control mode of the bridge.
UP_REQ_BUF
_CTRL
3†
2†
RW
RW
0 = PCI upstream req-res buffer threshold control mode disabled (default)
1 = PCI upstream req-res buffer threshold control mode enabled
CFG_ACCESS
_MEM_REG
Configuration access to memory-mapped registers. When this bit is set, the bridge allows
configuration access to memory-mapped configuration registers.
Reserved. Bit 1 defaults to 0b. If this register is programmed via EEPROM or another mechanism,
the value written into this field must be 0b.
1†
0
RSVD
RSVD
RW
R
Reserved. Returns 0b when read.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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4.62 Control and Diagnostic Register 1
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−36 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
PCI register offset:
Register type:
Default value:
C4h
Read/Write
0012 0108h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
Table 4−36. Control and Diagnostic Register 1 Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
32:21
RSVD
R
Reserved. Returns 000h when read.
L1 exit latency for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h,
see Section 4.53) is set, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the
link capabilities register (offset 9Ch, see Section 4.52). This field defaults to 100b.
L1_EXIT_LAT_
ASYNC
20:18†
17:15†
RW
RW
L1 exit latency for common clock. When bit 6 (CCC) of the link control register (offset A0h, see
Section 4.53) is clear, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the link
capabilities register (offset 9Ch, see Section 4.52). This field defaults to 100b.
L1_EXIT_LAT_
COMMON
Reserved. Bits 14:11 default to 0000b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 0000b.
14:11†
10†
RSVD
RW
RW
RW
RW
RW
SBUS_RESET
_MASK
Secondary bus reset bit mask. When this bit is set, the bridge masks the reset caused by bit 6
(SRST) of the bridge control register (offset 3Eh, see Section 4.29). This bit defaults to 0b.
L1ASPM_
TIMER
L1ASPM entry timer. This field specifies the value (in 512-ns ticks) of the L1ASPM entry timer. This
field defaults to 0100b.
9:6†
5:2†
1:0†
L0s entry timer. This field specifies the value (in 62.5-MHz clock ticks) of the L0s entry timer. This
field defaults to 0010b.
L0s_TIMER
RSVD
Reserved. Bits 1:0 default to 00b. If this register is programmed via EEPROM or another
mechanism, then the value written into this field must be 00b.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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4.63 Control and Diagnostic Register 2
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−37 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
PCI register offset:
Register type:
Default value:
C8h
Read/Write
3214 6000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−37. Control and Diagnostic Register 2 Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
N_FTS for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h, see
Section 4.53) is clear, the value in this field is the number of FTS that are sent on a transition from
L0s to L0. This field shall default to 32h.
N_FTS_
ASYNC_CLK
31:24†
RW
N_FTS_
COMMON_
CLK
N_FTS for common clock. When bit 6 (CCC) of the link control register (offset A0h, see Section
4.53) is set, the value in this field is the number of FTS that are sent on a transition from L0s to L0.
This field defaults to 14h.
23:16†
RW
15:13
12:8†
7:6
PHY_REV
LINK_NUM
RSVD
R
RW
R
PHY revision number
Link number
Reserved. Returns 00b when read.
BAR 0 Write Enable. When this bit is clear (default), the Base Address at offset 10h is read only
and writes to that register will have no effect. When this bit is set, then bits 31:12 of the Base
Address Register becomes writeable allowing the address of the 4K window to the Memory
Mapped TI Proprietary Registers to be changed.
5:0
BAROWE
RSVD
RW
RW
Reserved. Bits 4:0 default to 00000b. If this register is programmed via EEPROM or another
mechanism, then the value written into this field must be 00000b.
4:0†
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
4.64 Subsystem Access Register
The contents of this read/write register are aliased to the subsystem vendor ID and subsystem ID registers
at PCI offsets 84h and 86h. See Table 4−38 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
D0h
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−38. Subsystem Access Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Subsystem ID. The value written to this field is aliased to the subsystem ID register at PCI
offset 86h (see Section 4.45).
31:16†
SubsystemID
RW
Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 84h (see Section 4.44).
15:0†
SubsystemVendorID
RW
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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4.65 General Control Register
This read/write register controls various functions of the bridge. See Table 4−39 for a complete description
of the register contents.
PCI register offset:
Register type:
Default value:
D4h
Read-only, Read/Write
8206 C000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−39. General Control Register Description
BIT
FIELD NAME ACCESS
DESCRIPTION
Configuration retry counter. Configures the amount of time that a configuration request must be retried
on the secondary PCI bus before it may be completed with configuration retry status on the PCI
Express side.
CFG_RETRY
RW
00 = 25 µs
01 = 1 ms
31:30†
_CNTR
10 = 25 ms (default)
11 = 50 ms
29:28
27†
RSVD
R
Reserved. Returns 00b when read.
LOW_POWER
_EN
Low-power enable. When this bit is set, the half-ampitude, no preemphasis mode for the PCI Express
TX drivers is enabled. The default for this bit is 0b.
RW
PCI power management version control. This bit controls the value reported in bits 2:0 (PM_VERSION)
in the power management capabilities register (offset 52h, see Section 4.32). It also controls the value
of bit 3 (NO_SOFT_RESET) in the power management control/status register (offset 54h, see Section
4.33).
PCI_PM_
VERSION_
CTRL
26†
RW
0 = Version fields reports 010b and NO_SOFT_RESET reports 0b for Power Management 1.1
compliance (default)
1 = Version fields reports 011b and NO_SOFT_RESET reports 1b for Power Management 1.2
compliance
Strict priority enable. When this bit is set and bits 6:4 (LOW_PRIORITY_COUNT) in the port VC
capability register 1 (offset 154h, see Section 5.17) are 000b, meaning that strict priority VC arbitration
is used, the extended VC always receives priority over VC0 at the PCI Express port.
0 = The default LOW_PRIORITY_COUNT is 001b
STRICT_
PRIORITY_EN
25†
24†
23†
RW
RW
RW
1 = The default LOW_PRIORITY_COUNT is 000b (default)
Force memory read multiple
0 = Memory read multiple transactions are disabled (default)
1 = All upstream memory read transactions initiated on the PCI bus are treated as though they
are memory read multiple transactions where prefetching is supported
FORCE_MRM
Active state power management control default override. This bit determines the power-up default for
bits 1:0 (ASLPMC) of the link control register (offset A0h, see Section 4.53) in the PCI Express
capability structure.
ASPM_CTRL_
DEF_OVRD
0 = Power-on default indicates that active state power management is disabled (00b) (default)
1 = Power-on default indicates that active state power management is enabled for L0s and L1 (11b)
Power override. This bit field determines how the bridge responds when the slot power limit is less
than the amount of power required by the bridge and the devices behind the bridge.
000 = Ignore slot power limit (default)
001 = Assert the PWR_OVRD terminal
POWER_
OVRD
010 = Disable secondary clocks selected by the clock mask register
011 = Disable secondary clocks selected by the clock mask register and assert the PWR_OVRD
terminal
22:20†
RW
100 = Respond with unsupported request to all transactions except for configuration transactions
(type 0 or type 1) and set slot power limit messages
101, 110, 111 = Reserved
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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Table 4−39. General Control Register Description (Continued)
BIT
FIELD NAME ACCESS
DESCRIPTION
Read prefetch disable. This bit controls the prefetch functionality on PCI memory read transactions.
READ_
19†
PREFETCH_
DIS
RW
0 = Prefetch to the next cache line boundary on a burst read (default)
1 = Fetch only a single DWORD on a burst read
L0s maximum exit latency. This field programs the maximum acceptable latency when exiting the L0s
state. This sets bits 8:6 (EP_L0S_LAT) in the device capabilities register (offset 94h, see Section
4.49).
000 = Less than 64 ns
001 = 64 ns up to less than 128 ns
010 = 128 ns up to less than 256 ns
011 = 256 ns up to less than 512 ns
100 = 512 ns up to less than 1 µs
101 = 1 µs up to less than 2 µs
110 = 2 µs to 4 µs (default)
18:16† L0s_LATENCY
RW
111 = More than 4 µs
L1 maximum exit latency. This field programs the maximum acceptable latency when exiting the L1
state. This sets bits 11:9 (EP_L1_LAT) in the device capabilities register (offset 94h, see
Section 4.49).
000 = Less than 1 µs
001 = 1 µs up to less than 2 µs
010 = 2 µs up to less than 4 µs
011 = 4 µs up to less than 8 µs
100 = 8 µs up to less than 16 µs
101 = 16 µs up to less than 32 µs
110 = 32 µs to 64 µs (default)
111 = More than 64 µs
15:13† L1_LATENCY
RW
VC capability structure enable. This bit enables the VC capability structure by changing the next
offset field of the advanced error reporting capability register at offset 102h.
12†
VC_CAP_EN
BPCC_E
RW
RW
RW
0 = VC capability structure disabled (offset field = 000h)
1 = VC capability structure enabled (offset field = 150h)
Bus power clock control enable. This bit controls whether the secondary bus PCI clocks are stopped
when the bridge is placed in the D3 state. It is assumed that if the secondary bus clocks are required
to be active, that a reference clock continues to be provided on the PCI Express interface.
k
11
0 = Secondary bus clocks are not stopped in D3 (default)
1 = Secondary bus clocks are stopped on D3
Beacon enable. This bit controls the mechanism for waking up the physical PCI Express link when in
L2.
BEACON_
ENABLE
k
10
0 = WAKE mechanism is used exclusively. Beacon is not used (default).
1 = Beacon and WAKE mechanisms are used
Minimum power scale. This value is programmed to indicate the scale of bits 7:0
(MIN_POWER_VALUE).
MIN_POWER_
SCALE
00 = 1.0x (default)
01 = 0.1x
10 = 0.01x
9:8†
7:0†
RW
RW
11 = 0.001x
Minimum power value. This value is programmed to indicate the minimum power requirements. This
value is multiplied by the minimum power scale field (bits 9:8) to determine the minimum power
requirements for the bridge. The default is 00h, because this feature is only usable when the system
implementer adds the PCI devices’ power consumption to the bridge power consumption and
reprograms this field with an EEPROM or the system BIOS.
MIN_POWER_
VALUE
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
kThese bits are sticky and must retain their value when the bridge is powered by V
.
AUX
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4.66 Clock Control Register
This register enables and disables the PCI clock outputs (CLKOUT). See Table 4−40 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
D8h
Read-only, Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4−40. Clock Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7
RSVD
R
Reserved. Returns 0b when read.
Clock output 6 disable. This bit disables secondary CLKOUT6.
6†
5†
4†
3†
2†
1†
0†
CLOCK6_DISABLE
CLOCK5_DISABLE
CLOCK4_DISABLE
CLOCK3_DISABLE
CLOCK2_DISABLE
CLOCK1_DISABLE
CLOCK0_DISABLE
RW
0 = Clock enabled (default)
1 = Clock disabled
Clock output 5 disable. This bit disables secondary CLKOUT5.
RW
RW
RW
RW
RW
RW
0 = Clock enabled (default)
1 = Clock disabled
Clock output 4 disable. This bit disables secondary CLKOUT4.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 3 disable. This bit disables secondary CLKOUT3.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 2 disable. This bit disables secondary CLKOUT2.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 1 disable. This bit disables secondary CLKOUT1.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 0 disable. This bit disables secondary CLKOUT0.
0 = Clock enabled (default)
1 = Clock disabled
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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4.67 Clock Mask Register
This register selects which PCI bus clocks are disabled when bits 22:20 (POWER_OVRD) in the general
control register (offset D4h, see Section 4.65) are set to 010h or 011h. This register has no effect on the clock
outputs if the POWER_OVRD bits are not set to 010h or 011h or if the slot power limit is greater than the power
required. See Table 4−41 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
D9h
Read-only, Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4−41. Clock Mask Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7
RSVD
R
Reserved. Returns 0b when read.
Clock output 6 mask. This bit disables PCI bus CLKOUT6 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
6†
5†
4†
3†
2†
1†
0†
CLOCK6_MASK
CLOCK5_MASK
CLOCK4_MASK
CLOCK3_MASK
CLOCK2_MASK
CLOCK1_MASK
CLOCK0_MASK
RW
RW
RW
RW
RW
RW
RW
0 = Clock enabled (default)
1 = Clock disabled
Clock output 5 mask. This bit disables PCI bus CLKOUT5 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 4 mask. This bit disables PCI bus CLKOUT4 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 3 mask. This bit disables PCI bus CLKOUT3 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 2 mask. This bit disables PCI bus CLKOUT2 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 1 mask. This bit disables PCI bus CLKOUT1 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 0 mask. This bit disables PCI bus CLKOUT0 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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4.68 Clock Run Status Register
The clock run status register indicates the state of the PCI clock-run features in the bridge. See Table 4−42
for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
DAh
Read-only
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4−42. Clock Run Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Returns 000 0000b when read.
7:1
RSVD
R
Secondary clock status. This bit indicates the status of the PCI bus secondary clock outputs.
0†
SEC_CLK_STATUS
RU
0 = Secondary clock running
1 = Secondary clock stopped
†
This bit is reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
88
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4.69 Arbiter Control Register
The arbiter control register controls the bridge internal arbiter. The arbitration scheme used is a two-tier
rotational arbitration. The bridge is the only secondary bus master that defaults to the higher priority arbitration
tier. See Table 4−43 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
DCh
Read/Write
40h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
Table 4−43. Arbiter Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Bus parking mode. This bit determines where the internal arbiter parks the secondary bus.
When this bit is set, the arbiter parks the secondary bus on the bridge. When this bit is
cleared, the arbiter parks the bus on the last device mastering the secondary bus.
7†
PARK
RW
RW
0 = Park the secondary bus on the last secondary bus master (default)
1 = Park the secondary bus on the bridge
Bridge tier select. This bit determines in which tier the bridge is placed in the arbitration
scheme.
6†
BRIDGE_TIER_SEL
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT5 tier select. This bit determines in which tier GNT5 is placed in the arbitration scheme.
5†
4†
3†
2†
1†
0†
TIER_SEL5
TIER_SEL4
TIER_SEL3
TIER_SEL2
TIER_SEL1
TIER_SEL0
RW
RW
RW
RW
RW
RW
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT4 tier select. This bit determines in which tier GNT4 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT3 tier select. This bit determines in which tier GNT3 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT2 tier select. This bit determines in which tier GNT2 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT1 tier select. This bit determines in which tier GNT1 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT0 tier select. This bit determines in which tier GNT0 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
†
Thes bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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4.70 Arbiter Request Mask Register
The arbiter request mask register enables and disables support for requests from specific masters on the
secondary bus. The arbiter request mask register also controls if a request input is automatically masked on
an arbiter time-out. See Table 4−44 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
DDh
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4−44. Arbiter Request Mask Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Arbiter time-out. This bit enables the arbiter time-out feature. The arbiter time-out is defined as
the number of PCI clocks after the PCI bus has gone idle for a device to assert FRAME before
the arbiter assumes the device will not respond.
7†
ARB_TIMEOUT
RW
0 = Arbiter time disabled (default)
1 = Arbiter time-out set to 16 PCI clocks
Automatic request mask. This bit enables automatic request masking when an arbiter time-out
occurs.
6†
5†
4†
3†
2†
1†
0†
AUTO_MASK
REQ5_MASK
REQ4_MASK
REQ3_MASK
REQ2_MASK
REQ1_MASK
REQ0_MASK
RW
RW
RW
RW
RW
RW
RW
0 = Automatic request masking disabled (default)
1 = Automatic request masking enabled
Request 5 (REQ5) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 5.
0 = Use request 5 (default)
1 = Ignore request 5
Request 4 (REQ4) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 4.
0 = Use request 4 (default)
1 = Ignore request 4
Request 3 (REQ3) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 3.
0 = Use request 3 (default)
1 = Ignore request 3
Request 2 (REQ2) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 2.
0 = Use request 2 (default)
1 = Ignore request 2
Request 1 (REQ1) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 1.
0 = Use request 1 (default)
1 = Ignore request 1
Request 0 (REQ0) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 0.
0 = Use request 0 (default)
1 = Ignore request 0
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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Classic PCI Configuration Space
4.71 Arbiter Time-Out Status Register
The arbiter time-out status register contains the status of each request (request 5–0) time-out. The time-out
status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out value.
See Table 4−45 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
DEh
Read/Clear
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4−45. Arbiter Time-Out Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:6
RSVD
R
Reserved. Returns 00b when read.
Request 5 time-out status
5
4
3
2
1
0
REQ5_TO
REQ4_TO
REQ3_TO
REQ2_TO
REQ1_TO
REQ0_TO
RCU
0 = No time-out
1 = Time-out has occurred
Request 4 time-out status
RCU
RCU
RCU
RCU
RCU
0 = No time-out
1 = Time-out has occurred
Request 3 time-out status
0 = No time-out
1 = Time-out has occurred
Request 2 time-out status
0 = No time-out
1 = Time-out has occurred
Request 1 time-out status
0 = No time-out
1 = Time-out has occurred
Request 0 time-out status
0 = No time-out
1 = Time-out has occurred
NOTE:If bit 6 (AUTO_MASK) in the arbiter request mask register (offset DDh, see
Section 4.70) is asserted and a PCI bus request time-out is detected, then the request time-out
status bits require a special reset sequence. First, the AUTO_MASK bit must be cleared to
0b. Then, the REQ[5:0]_TO bit will clear after a write-back of 1b.
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4.72 Serial IRQ Mode Control Register
This register controls the behavior of the serial IRQ controller. See Table 4−46 for a complete description of
the register contents.
PCI register offset:
Register type:
Default value:
E0h
Read-only, Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4−46. Serial IRQ Mode Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:4
RSVD
R
Reserved. Returns 0h when read.
Start frame pulse width. Sets the width of the start frame for a SERIRQ stream.
00 = 4 clocks (default)
01 = 6 clocks
3:2†
START_WIDTH
RW
10 = 8 clocks
11 = Reserved
Poll mode. This bit selects between continuous and quiet mode.
1†
0†
POLLMODE
DRIVEMODE
RW
RW
0 = Continuous mode (default)
1 = Quiet mode
Drive mode. This bit selects the behavior of the serial IRQ controller during the recovery cycle.
0 = Drive high (default)
1 = 3-state
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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4.73 Serial IRQ Edge Control Register
This register controls the edge mode or level mode for each IRQ in the serial IRQ stream. See Table 4−47 for
a complete description of the register contents.
PCI register offset:
Register type:
Default value:
E2h
Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−47. Serial IRQ Edge Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
IRQ 15 edge mode
0 = Edge mode (default)
1 = Level mode
15†
IRQ15_MODE
RW
IRQ 14 edge mode
0 = Edge mode (default)
1 = Level mode
14†
13†
12†
11†
10†
9†
IRQ14_MODE
IRQ13_MODE
IRQ12_MODE
IRQ11_MODE
IRQ10_MODE
IRQ9_MODE
IRQ8_MODE
IRQ7_MODE
IRQ6_MODE
IRQ5_MODE
IRQ4_MODE
IRQ3_MODE
IRQ2_MODE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
IRQ 13 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 12 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 11 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 10 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 9 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 8 edge mode
0 = Edge mode (default)
1 = Level mode
8†
IRQ 7 edge mode
0 = Edge mode (default)
1 = Level mode
7†
IRQ 6 edge mode
0 = Edge mode (default)
1 = Level mode
6†
IRQ 5 edge mode
0 = Edge mode (default)
1 = Level mode
5†
IRQ 4 edge mode
0 = Edge mode (default)
1 = Level mode
4†
IRQ 3 edge mode
0 = Edge mode (default)
1 = Level mode
3†
IRQ 2 edge mode
0 = Edge mode (default)
1 = Level mode
2†
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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Table 4−47. Serial IRQ Edge Control Register Description (Continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
IRQ 1 edge mode
0 = Edge mode (default)
1 = Level mode
1†
IRQ1_MODE
RW
IRQ 0 edge mode
0 = Edge mode (default)
1 = Level mode
0†
IRQ0_MODE
RW
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
4.74 Serial IRQ Status Register
This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode IRQ
is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that are
defined as edge mode in the serial IRQ edge control register are not reported in this status register. See
Table 4−48 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
E4h
Read/Clear
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−48. Serial IRQ Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
IRQ 15 asserted. This bit indicates that the IRQ15 has been asserted.
15
IRQ15
RCU
0 = Deasserted
1 = Asserted
IRQ 14 asserted. This bit indicates that the IRQ14 has been asserted.
14
13
12
11
10
9
IRQ14
IRQ13
IRQ12
IRQ11
IRQ10
IRQ9
RCU
RCU
RCU
RCU
RCU
RCU
RCU
RCU
0 = Deasserted
1 = Asserted
IRQ 13 asserted. This bit indicates that the IRQ13 has been asserted.
0 = Deasserted
1 = Asserted
IRQ 12 asserted. This bit indicates that the IRQ12 has been asserted.
0 = Deasserted
1 = Asserted
IRQ 11 asserted. This bit indicates that the IRQ11 has been asserted.
0 = Deasserted
1 = Asserted
IRQ 10 asserted. This bit indicates that the IRQ10 has been asserted.
0 = Deasserted
1 = Asserted
IRQ 9 asserted. This bit indicates that the IRQ9 has been asserted.
0 = Deasserted
1 = Asserted
IRQ 8 asserted. This bit indicates that the IRQ8 has been asserted.
8
IRQ8
0 = Deasserted
1 = Asserted
IRQ 7 asserted. This bit indicates that the IRQ7 has been asserted.
7
IRQ7
0 = Deasserted
1 = Asserted
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Table 4−48. Serial IRQ Status Register Description (Continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
IRQ 6 asserted. This bit indicates that the IRQ6 has been asserted.
6
IRQ6
RCU
0 = Deasserted
1 = Asserted
IRQ 5 asserted. This bit indicates that the IRQ5 has been asserted.
5
4
3
2
1
0
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
RCU
RCU
RCU
RCU
RCU
RCU
0 = Deasserted
1 = Asserted
IRQ 4 asserted. This bit indicates that the IRQ4 has been asserted.
0 = Deasserted
1 = Asserted
IRQ 3 asserted. This bit indicates that the IRQ3 has been asserted.
0 = Deasserted
1 = Asserted
IRQ 2 asserted. This bit indicates that the IRQ2 has been asserted.
0 = Deasserted
1 = Asserted
IRQ 1 asserted. This bit indicates that the IRQ1 has been asserted.
0 = Deasserted
1 = Asserted
IRQ 0 asserted. This bit indicates that the IRQ0 has been asserted.
0 = Deasserted
1 = Asserted
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PCI Express Extended Configuration Space
5
PCI Express Extended Configuration Space
The programming model of the PCI Express extended configuration space is compliant to the PCI Express
Base Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The PCI
Express extended configuration map uses the PCI Express advanced error reporting capability and PCI
Express virtual channel (VC) capability headers.
k
All bits marked with a are sticky bits and are reset by a global reset (GRST) or the internally-generated
power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST), a GRST, or the
internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST,
GRST, or the internally-generated power-on reset.
Table 5−1. PCI Express Extended Configuration Register Map
REGISTER NAME
PCI Express advanced error reporting capabilities ID
OFFSET
100h
104h
108h
10Ch
110h
Next capability offset / capability version
Uncorrectable error status register†
Uncorrectable error mask register†
Uncorrectable error severity register†
Correctable error status register†
Correctable error mask†
114h
Advanced error capabilities and control†
Header log register†
118h
11Ch
120h
124h
128h
12Ch
130h
134h
138h
13Ch
140h
144h
148h
14Ch
150h
154h
158h
15Ch
160h
164h
168h
16Ch
170h
174h
178h – 17Ch
180h
184h
188h
Header log register†
Header log register†
Header log register†
Secondary uncorrectable error status†
Secondary uncorrectable error mask†
Secondary uncorrectable error severity register†
Secondary error capabilities and control register†
Secondary header log register†
Secondary header log register†
Secondary header log register†
Secondary header log register†
Reserved
Next capability offset / capability version
PCI express virtual channel extended capabilities ID
Port VC capability register 1
Port VC capability register 2
Port VC status register
Port VC control register
Reserved
VC resource capability register (VC0)
VC resource control register (VC0)
VC resource status register (VC0)
VC resource capability register (VC1)
VC resource control register (VC1)
VC resource status register (VC1)
Reserved
Reserved
VC arbitration table (phase 7 − phase 0)
VC arbitration table (phase 15 − phase 8)
VC arbitration table (phase 23 − phase 16)
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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Table 5−1. PCI Express Extended Configuration Register Map (Continued)
REGISTER NAME
OFFSET
18Ch
VC arbitration table (phase 31 − phase 24)
Reserved
190h – 1BCh
1C0h
Port arbitration table for VC1 (phase 7 – phase 0)
Port arbitration table for VC1 (phase 15 – phase 8)
Port arbitration table for VC1 (phase 23 – phase 16)
Port arbitration table for VC1 (phase 31 – phase 24)
Port arbitration table for VC1 (phase 39 – phase 32)
Port arbitration table for VC1 (phase 47 – phase 40)
Port arbitration table for VC1 (phase 55 – phase 48)
Port arbitration table for VC1 (phase 63 – phase 56)
Port arbitration table for VC1 (phase 71 – phase 64)
Port arbitration table for VC1 (phase 79 – phase 72)
Port arbitration table for VC1 (phase 87 – phase 80)
Port arbitration table for VC1 (phase 95 – phase 88)
Port arbitration table for VC1 (phase 103 – phase 96)
Port arbitration table for VC1 (phase 111 – phase 104)
Port arbitration table for VC1 (phase 119 – phase 112)
Port arbitration table for VC1 (phase 127 – phase 120)
Reserved
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
1DCh
1E0h
1E4h
1E8h
1ECh
1F0h
1F4h
1F8h
1FCh
200h – FFCh
5.1 Advanced Error Reporting Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express advanced error reporting
capabilities. The register returns 0001h when read.
PCI Express extended register offset:
Register type:
Default value:
100h
Read-only
0001h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
5.2 Next Capability Offset/Capability Version Register
This read-only register identifies the next location in the PCI Express extended capabilities link list. If bit 12
(VC_CAP_EN) in the general control register (offset D4h, see Section 4.65) is 0b, then the upper 12 bits in
this register are 000h, indicating the end of the linked list. If VC_CAP_EN is 1b, then the upper 12 bits in this
register are 150h, indicating the existance of the VC capability structure at offset 150h. The four least
significant bits identify the revision of the current capability block as 1h.
PCI Express extended register offset:
Register type:
Default value:
102h
Read-only
XX01h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
x
0
x
0
x
0
0
0
0
0
0
0
1
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5.3 Uncorrectable Error Status Register
The uncorrectable error status register reports the status of individual errors as they occur on the primary PCI
Express interface. Software may only clear these bits by writing a 1b to the desired location. See Table 5−2
for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
104h
Read-only, Read/Clear
0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−2. Uncorrectable Error Status Register Description
BIT
31:21
20†
FIELD NAME
RSVD
ACCESS
R
DESCRIPTION
Reserved. Returns 000 0000 0000b when read.
UR_ERROR
ECRC_ERROR
MAL_TLP
RCU
RCU
RCU
Unsupported request error. This bit is asserted when an unsupported request is received.
Extended CRC error. This bit is asserted when an extended CRC error is detected.
Malformed TLP. This bit is asserted when a malformed TLP is detected.
19†
18†
Receiver overflow. This bit is asserted when the flow control logic detects that the transmitting
device has illegally exceeded the number of credits that were issued.
17†
RX_OVERFLOW
RCU
Unexpected completion. This bit is asserted when a completion packet is received that does
not correspond to an issued request.
16†
15†
14†
UNXP_CPL
CPL_ABORT
CPL_TIMEOUT
RCU
RCU
RCU
Completer abort. This bit is asserted when the bridge signals a completer abort.
Completion time-out. This bit is asserted when no completion has been received for an issued
request before the time-out period.
Flow control error. This bit is asserted when a flow control protocol error is detected either
during initialization or during normal operation.
13†
FC_ERROR
RCU
12†
11:5
4†
PSN_TLP
RSVD
RCU
R
Poisoned TLP. This bit is asserted when a poisoned TLP is received.
Reserved. Returns 000 0000b when read.
DLL_ERROR
RSVD
RCU
R
Data link protocol error. This bit is asserted if a data link-layer protocol error is detected.
Reserved. Returns 0h when read.
3:0
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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5.4 Uncorrectable Error Mask Register
The uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask
bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the
header log is not loaded, and the first error pointer is not updated. See Table 5−3 for a complete description
of the register contents.
PCI Express extended register offset:
Register type:
Default value:
108h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−3. Uncorrectable Error Mask Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Returns 000 0000 0000b when read.
Unsupported request error mask
31:21
RSVD
R
20†
19†
18†
17†
16†
15†
14†
13†
UR_ERROR_MASK
RW
RW
RW
RW
RW
RW
RW
RW
0 = Error condition is unmasked (default)
1 = Error condition is masked
Extended CRC error mask
ECRC_ERROR_MASK
MAL_TLP_MASK
0 = Error condition is unmasked (default)
1 = Error condition is masked
Malformed TLP mask
0 = Error condition is unmasked (default)
1 = Error condition is masked
Receiver overflow mask
RX_OVERFLOW_MASK
UNXP_CPL_MASK
0 = Error condition is unmasked (default)
1 = Error condition is masked
Unexpected completion mask
0 = Error condition is unmasked (default)
1 = Error condition is masked
Completer abort mask
CPL_ABORT_MASK
CPL_TIMEOUT_MASK
FC_ERROR_MASK
0 = Error condition is unmasked (default)
1 = Error condition is masked
Completion time-out mask
0 = Error condition is unmasked (default)
1 = Error condition is masked
Flow control error mask
0 = Error condition is unmasked (default)
1 = Error condition is masked
Poisoned TLP mask
12†
11:5
4†
PSN_TLP_MASK
RSVD
RW
R
0 = Error condition is unmasked (default)
1 = Error condition is masked
Reserved. Returns 000 0000b when read.
Data link protocol error mask
DLL_ERROR_MASK
RSVD
RW
R
0 = Error condition is unmasked (default)
1 = Error condition is masked
3:0
Reserved. Returns 0h when read.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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5.5 Uncorrectable Error Severity Register
The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or
ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is
cleared, the corresponding error condition is identified as nonfatal. See Table 5−4 for a complete description
of the register contents.
PCI Express extended register offset:
Register type:
Default value:
10Ch
Read-only, Read/Write
0006 2011h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
Table 5−4. Uncorrectable Error Severity Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Returns 000 0000 0000b when read.
Unsupported request error severity
31:21
RSVD
R
20†
19†
18†
17†
16†
15†
14†
13†
UR_ERROR_SEVR
RW
RW
RW
RW
RW
RW
RW
RW
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Extended CRC error severity
ECRC_ERROR_SEVR
MAL_TLP_SEVR
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Malformed TLP severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL (default)
Receiver overflow severity
RX_OVERFLOW_SEVR
UNXP_CPL_SEVR
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL (default)
Unexpected completion severity
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Completer abort severity
CPL_ABORT_SEVR
CPL_TIMEOUT_SEVR
FC_ERROR_SEVR
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Completion time-out severity
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Flow control error severity
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL (default)
Poisoned TLP severity
12†
11:5
4†
PSN_TLP_SEVR
RSVD
RW
R
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Reserved. Returns 000 0000b when read.
Data link protocol error severity
DLL_ERROR_SEVR
RW
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL (default)
3:1
0
RSVD
RSVD
R
R
Reserved. Return 000b when read.
Reserved. Returns 1b when read.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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5.6 Correctable Error Status Register
The correctable error status register reports the status of individual errors as they occur. Software may only
clear these bits by writing a 1b to the desired location. See Table 5−5 for a complete description of the register
contents.
PCI Express extended register offset:
Register type:
Default value:
110h
Read-only, Read/Clear
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−5. Correctable Error Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:13
RSVD
R
Reserved. Returns 000 0000 0000 0000 0000b when read.
Replay timer time-out. This bit is asserted when the replay timer expires for a pending request
or completion that has not been acknowledged.
12†
11:9
8†
REPLAY_TMOUT
RSVD
RCU
R
Reserved. Returns 000b when read.
REPLAY_NUM rollover. This bit is asserted when the replay counter rolls over after a pending
request or completion has not been acknowledged.
REPLAY_ROLL
RCU
Bad DLLP error. This bit is asserted when an 8b/10b error was detected by the PHY during the
reception of a DLLP.
7†
6†
BAD_DLLP
BAD_TLP
RCU
RCU
Bad TLP error. This bit is asserted when an 8b/10b error was detected by the PHY during the
reception of a TLP.
5:1
0†
RSVD
R
Reserved. Returns 00000b when read.
RX_ERROR
RCU
Receiver error. This bit is asserted when an 8b/10b error is detected by the PHY at any time.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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5.7 Correctable Error Mask Register
The correctable error mask register controls the reporting of individual errors as they occur. When a mask bit
is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header
log is not loaded, and the first error pointer is not updated. See Table 5−6 for a complete description of the
register contents.
PCI Express extended register offset:
Register type:
Default value:
114h
Read-only, Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−6. Correctable Error Mask Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:13
RSVD
R
Reserved. Returns 000 0000 0000 0000 0000b when read.
Replay timer time-out mask.
12†
11:9
8†
REPLAY_TMOUT_MASK
RSVD
RW
R
0 = Error condition is unmasked (default)
1 = Error condition is masked
Reserved. Returns 000b when read.
REPLAY_NUM rollover mask.
REPLAY_ROLL_MASK
RW
0 = Error condition is unmasked (default)
1 = Error condition is masked
Bad DLLP error mask.
7†
BAD_DLLP_MASK
RW
0 = Error condition is unmasked (default)
1 = Error condition is masked
Bad TLP error mask.
6†
5:1
0†
BAD_TLP_MASK
RSVD
RW
R
0 = Error condition is unmasked (default)
1 = Error condition is masked
Reserved. Returns 00000b when read.
Receiver error mask.
RX_ERROR_MASK
RW
0 = Error condition is unmasked (default)
1 = Error condition is masked
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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5.8 Advanced Error Capabilities and Control Register
The advanced error capabilities and control register allows the system to monitor and control the advanced
error reporting capabilities. See Table 5−7 for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
118h
Read-only, Read/Write
0000 00A0h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
Table 5−7. Advanced Error Capabilities and Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Returns 000 0000 0000 0000 0000 0000b when read.
Extended CRC check enable
31:9
RSVD
R
8†
7
ECRC_CHK_EN
ECRC_CHK_CAPABLE
ECRC_GEN_EN
RW
R
0 = Extended CRC checking is disabled
1 = Extended CRC checking is enabled
Extended CRC check capable. This read-only bit returns a value of 1b indicating that the
bridge is capable of checking extended CRC information.
Extended CRC generation enable
6†
RW
0 = Extended CRC generation is disabled
1 = Extended CRC generation is enabled
Extended CRC generation capable. This read-only bit returns a value of 1b indicating that
the bridge is capable of generating extended CRC information.
5
ECRC_GEN_CAPABLE
FIRST_ERR
R
First error pointer. This 5-bit value reflects the bit position within the uncorrectable error
status register (offset 104h, see Section 5.3) corresponding to the class of the first error
condition that was detected.
4:0†
RU
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
5.9 Header Log Register
The header log register stores the TLP header for the packet that lead to the most recently detected error
condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a 4DW
TLP header). Each DWORD is stored with the least significant byte representing the earliest transmitted.
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
PCI Express extended register offset:
Register type:
11Ch, 120h, 124h, and 128h
Read-only
Default value:
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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5.10 Secondary Uncorrectable Error Status Register
The secondary uncorrectable error status register reports the status of individual PCI bus errors as they occur.
Software may only clear these bits by writing a 1b to the desired location. See Table 5−8 for a complete
description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
12Ch
Read-only, Read/Clear
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−8. Secondary Uncorrectable Error Status Register Description
BIT
31:14
13†
FIELD NAME
RSVD
ACCESS
DESCRIPTION
R
R
Reserved. Returns 00 0000 0000 0000 0000b when read.
BRIDGE_ERROR
Internal bridge error. This error bit is associated with a PCI-X error and returns 0b when read.
SERR assertion detected. This bit is asserted when the bridge detects the assertion of SERR
on the secondary bus.
12†
11†
10†
9†
SERR_DETECT
PERR_DETECT
DISCARD_TIMER
UNCOR_ADDR
ATTR_ERROR
RCU
RCU
RCU
RCU
R
PERR assertion detected. This bit is asserted when the bridge detects the assertion of PERR
on the secondary bus.
Delayed transaction discard timer expired. This bit is asserted when the discard timer expires
for a pending delayed transaction that was initiated on the secondary bus.
Uncorrectable address error. This bit is asserted when the bridge detects a parity error during
the address phase of an upstream transaction.
Uncorrectable attribute error. This error bit is associated with a PCI-X error and returns 0b
when read.
8†
Uncorrectable data error. This bit is asserted when the bridge detects a parity error during a
data phase of an upstream write transaction, or when the bridge detects the assertion of
PERR when forwarding read completion data to a PCI device.
7†
6†
UNCOR_DATA
SC_MSG_DATA
RCU
R
Uncorrectable split completion message data error. This error bit is associated with a PCI-X
error and returns 0b when read.
Unexpected split completion error. This error bit is associated with a PCI-X error and returns
0b when read.
5†
4
SC_ERROR
RSVD
R
R
Reserved. Returns 0b when read.
Received master abort. This bit is asserted when the bridge receives a master abort on the
PCI interface.
3†
MASTER_ABORT
RCU
Received target abort. This bit is asserted when the bridge receives a target abort on the PCI
interface.
2†
TARGET_ABORT
RCU
Master abort on split completion. This error bit is associated with a PCI-X error and returns 0b
when read.
1†
0
SC_MSTR_ABORT
RSVD
R
R
Reserved. Returns 0b when read.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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PCI Express Extended Configuration Space
5.11 Secondary Uncorrectable Error Mask Register
The secondary uncorrectable error mask register controls the reporting of individual errors as they occur.
When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are
blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5−9 for a complete
description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
130h
Read-only, Read/Write
0000 17A8h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
1
0
1
0
0
0
Table 5−9. Secondary Uncorrectable Error Mask Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:14
RSVD
R
Reserved. Returns 00 0000 0000 0000 0000b when read.
Internal bridge error. This mask bit is associated with a PCI-X error and has no effect
on the bridge.
13†
BRIDGE_ERROR_MASK
RW
SERR assertion detected
12†
SERR_DETECT_MASK
RW
0 = Error condition is unmasked
1 = Error condition is masked (default)
PERR assertion detected
11†
10†
PERR_DETECT_MASK
DISCARD_TIMER_MASK
RW
RW
0 = Error condition is unmasked (default)
1 = Error condition is masked
Delayed transaction discard timer expired
0 = Error condition is unmasked
1 = Error condition is masked (default)
Uncorrectable address error
9†
8†
7†
6†
UNCOR_ADDR_MASK
ATTR_ERROR_MASK
UNCOR_DATA_MASK
SC_MSG_DATA_MASK
RW
RW
RW
RW
0 = Error condition is unmasked
1 = Error condition is masked (default)
Uncorrectable attribute error. This mask bit is associated with a PCI-X error and has no
effect on the bridge.
Uncorrectable data error
0 = Error condition is unmasked
1 = Error condition is masked (default)
Uncorrectable split completion message data error. This mask bit is associated with a
PCI-X error and has no effect on the bridge.
Unexpected split completion error. This mask bit is associated with a PCI-X error and
has no effect on the bridge.
5†
4
SC_ERROR_MASK
RSVD
RW
R
Reserved. Returns 0b when read.
Received master abort
3†
2†
MASTER_ABORT_MASK
TARGET_ABORT_MASK
RW
RW
0 = Error condition is unmasked
1 = Error condition is masked (default)
Received target abort
0 = Error condition is unmasked (default)
1 = Error condition is masked
Master abort on split completion. This mask bit is associated with a PCI-X error and
has no effect on the bridge.
1†
0
SC_MSTR_ABORT_MASK
RSVD
RW
R
Reserved. Returns 0b when read.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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PCI Express Extended Configuration Space
5.12 Secondary Uncorrectable Error Severity Register
The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or
ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is
cleared, the corresponding error condition is identified as nonfatal. See Table 5−10 for a complete description
of the register contents.
PCI Express extended register offset:
Register type:
Default value:
134h
Read-only, Read/Write
0000 1340h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
Table 5−10. Secondary Uncorrectable Error Severity Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:14
RSVD
R
Reserved. Returns 00 0000 0000 0000 0000b when read.
Internal bridge error. This severity bit is associated with a PCI-X error and has no
effect on the bridge.
13†
BRIDGE_ERROR_SEVR
RW
SERR assertion detected
12†
SERR_DETECT_SEVR
RW
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL (default)
PERR assertion detected
11†
10†
PERR_DETECT_SEVR
DISCARD_TIMER_SEVR
RW
RW
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Delayed transaction discard timer expired
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Uncorrectable address error
9†
8†
7†
6†
UNCOR_ADDR_SEVR
ATTR_ERROR_SEVR
UNCOR_DATA_SEVR
SC_MSG_DATA_SEVR
RW
RW
RW
RW
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL (default)
Uncorrectable attribute error. This severity bit is associated with a PCI-X error and has
no effect on the bridge.
Uncorrectable data error
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Uncorrectable split completion message data error. This severity bit is associated with
a PCI-X error and has no effect on the bridge.
Unexpected split completion error. This severity bit is associated with a PCI-X error
and has no effect on the bridge.
5†
4
SC_ERROR_SEVR
RSVD
RW
R
Reserved. Returns 0b when read.
Received master abort
3†
2†
MASTER_ABORT_SEVR
TARGET_ABORT_SEVR
RW
RW
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Received target abort
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
Master abort on split completion. This severity bit is associated with a PCI-X error and
has no effect on the bridge.
1†
0
SC_MSTR_ABORT_SEVR
RSVD
RW
R
Reserved. Returns 0b when read.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
106
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PCI Express Extended Configuration Space
5.13 Secondary Error Capabilities and Control Register
The secondary error capabilities and control register allows the system to monitor and control the secondary
advanced error reporting capabilities. See Table 5−11 for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
138h
Read-only
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−11. Secondary Error Capabilities and Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:5
RSVD
R
Reserved. Returns 000 0000 0000 0000 0000 0000 0000b when read.
First error pointer. This 5-bit value reflects the bit position within the secondary uncorrectable
error status register (offset 12Ch, see Section 5.10) corresponding to the class of the first error
condition that was detected.
4:0†
SEC_FIRST_ERR
RU
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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PCI Express Extended Configuration Space
5.14 Secondary Header Log Register
The secondary header log register stores the transaction address and command for the PCI bus cycle that
led to the most recently detected error condition. Offset 13Ch accesses register bits 31:0. Offset 140h
accesses register bits 63:32. Offset 144h accesses register bits 95:64. Offset 148h accesses register
bits 127:96. See Table 5−12 for a complete description of the register contents.
PCI Express extended register offset:
Register type:
13Ch, 140h, 144h, and 148h
Read-only
Default value:
0000 0000h
BIT NUMBER
RESET STATE
127 126 125 124 123 122 121 120 119
118
117
116
115
114
113
112
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
111
110 109 108 107 106 105 104 103 102 101 100
99
98
97
96
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−12. Secondary Header Log Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Transaction address. The 64-bit value transferred on AD[31:0] during the first and second
address phases. The first address phase is logged to 95:64 and the second address phase
is logged to 127:96. In the case of a 32-bit address, bits 127:96 are set to 0000 0000h.
127:64†
ADDRESS
RU
63:44
RSVD
R
Reserved. Returns 00000h when read.
Transaction command upper. Contains the status of the C/BE terminals during the second
address phase of the PCI transaction that generated the error if using a dual-address cycle.
43:40†
UPPER_CMD
RU
Transaction command lower. Contains the status of the C/BE terminals during the first
address phase of the PCI transaction that generated the error.
39:36†
35:0
LOWER_CMD
RU
R
Transaction attribute. Because the bridge does not support the PCI-X attribute transaction
phase, these bits have no function, and return 0 0000 0000h when read.
TRANS_ATTRIBUTE
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
5.15 Virtual Channel Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express VC capabilities. The register
returns 0002h when read.
PCI Express extended register offset:
Register type:
Default value:
150h
Read-only
0002h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
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PCI Express Extended Configuration Space
5.16 Next Capability Offset/Capability Version Register
This read-only register returns the value 000h to indicate that this extended capability block represents the
end of the linked list of extended capability structures. The four least significant bits identify the revision of the
current capability block as 1h.
PCI Express extended register offset:
Register type:
Default value:
152h
Read-only
0001h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
5.17 Port VC Capability Register 1
The first port VC capability register provides information to software regarding the VC capabilities support by
the bridge. See Table 5−13 for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
154h
Read-only
0000 08X1h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
0
0
0
x
0
0
0
1
Table 5−13. Port VC Capability Register 1 Description
BIT
FIELD NAME
RSVD
ACCESS
DESCRIPTION
Reserved. Returns 00000h when read.
Port arbitration table entry size. This read-only field returns a value of 10b to indicate
31:12
R
11:10
PORT_TABLE_SIZE
R
that the field size within the port arbitration table is four bits. This is necessary to allow
as many as six secondary PCI bus masters.
Reference clock. This read-only field returns a value of 00b to indicate than an internal
100-ns timer is used for time-based, WRR port arbitration.
9:8
7
REF_CLK
RSVD
R
R
Reserved. Returns 0b when read.
Low priority extended VC count. When bit 25 (STRICT_PRIORITY_EN) in the general
control register (offset D4h, see Section 4.65) is 0b, the default
LOW_PRIORITY_COUNT is 001b. When STRICT_PRIORITY_EN is 1b, the default
LOW_PRIORITY_COUNT is 000b. When STRICT_PRIORITY_EN is set, strict priority
VC arbitration is used and the extended VC always receives priority over VC0 at the
PCI Express port.
6:4
LOW_PRIORITY_COUNT
RU
3
RSVD
R
R
Reserved. Returns 0b when read.
Extended VC count. This read-only field returns a value of 001b to indicate support for
one extended VC.
2:0
EXT_VC_COUNT
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April 2007 Revised October 2008
SCPS155C
PCI Express Extended Configuration Space
5.18 Port VC Capability Register 2
The second port VC capability register provides information to software regarding the VC arbitration schemes
supported by the bridge. See Table 5−14 for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
158h
Read-only
0X00 000Xh
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
Table 5−14. Port VC Capability Register 2 Description
BIT
31:24
23:8
FIELD NAME
ACCESS
DESCRIPTION
VC arbitration table offset. If bits 6:4 (LOW_PROIRITY_COUNT) in the port VC capability register 1
(offset 154h, see Section 5.17) are 000b, then this field returns 00h when read. Otherwise, this
read-only field returns the value 03h to indicate that the VC arbitration table begins 48 bytes from
the top of the VC capability structure. When this field equals 00h, the VC arbitration table is a
scratch pad and has no effect in the bridge.
VC_ARB_
TBL_OFFSET
RU
R
RSVD
Reserved. Returns 0000h when read.
VC arbitration capability. This 8-bit encoded field indicates support for the various schemes that are
supported for VC arbitration. The field is encoded as follows:
Bit 0 = Hardware fixed arbitration (round-robin)
Bit 1 = WRR with 32 phases
Bit 2 = WRR with 64 phases
Bit 3 = WRR with 128 phases
Bit 4 = Reserved
7:0
VC_ARB_CAP
RU
Bit 5 = Reserved
Bit 6 = Reserved
Bit 7 = Reserved
If bits 6:4 (LOW_PROIRITY_COUNT) in the port VC capability register 1 (offset 154h, see
Section 5.17) are 000b, then this field returns 00h when read. Otherwise, this field returns 03h to
indicate that hardware-fixed round-robin and WRR with 32 phases are both supported.
110
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April 2007 Revised October 2008
PCI Express Extended Configuration Space
5.19 Port VC Control Register
The port VC control register allows software to configure the VC arbitration options within the bridge. See
Table 5−15 for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
15Ch
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−15. Port VC Control Register Description
FIELD NAME ACCESS DESCRIPTION
BIT
15:4
RSVD
R
Reserved. Returns 000h when read.
VC arbitration select. This read/write field allows software to define the mechanism used for VC
arbitration by the bridge. The value written to this field indicates the bit position within bits 7:0
(VC_ARB_CAP) in the port VC capability register 2 (offset 158h, see Section 5.18) that corresponds
to the selected arbitration scheme. Values that may be written to this field include:
VC_ARB
_SELECT
3:1
RW
000 = Hardware-fixed round-robin (default)
001 = WRR with 32 phases
All other values are reserved for arbitrations schemes that are not supported by the bridge.
Load VC arbitration table. When software writes a 1b to this bit, the bridge applies the values written
in the VC arbitration table within the extended configuration space to the actual VC arbitration tables
used by the device for arbitration. This bit always returns 0b when read.
LOAD_VC
_TABLE
0
RW
5.20 Port VC Status Register
The port VC status register allows software to monitor the status of the VC arbitration table. See Table 5−16
for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
15Eh
Read-only
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−16. Port VC Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:1
RSVD
R
Reserved. Returns 000 0000 0000 0000b when read.
VC arbitration table status. This bit is automatically set by hardware when any modification is
made to the VC arbitration table entries within the extended configuration space. This bit is
cleared by hardware after software has requested a VC arbitration table refresh and the
refresh has been completed.
0
VC_TABLE_STATUS
RU
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5.21 VC Resource Capability Register (VC0)
The VC resource capability register for VC0 provides information to software regarding the port and arbitration
schemes supported by the bridge. See Table 5−17 for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
160h
Read-only
0000 0001h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 5−17. VC Resource Capability Register (VC0) Description
BIT
31:24
23
FIELD NAME
ACCESS
DESCRIPTION
Port arbitration table offset. This read-only field returns the value 00h to indicate that
no port arbitration table is required for this VC.
PORT_ARB_TBL_OFFSET
RSVD
R
R
R
Reserved. Returns 0b when read.
Maximum time slots. This read-only field returns the value 000 0000b because there is
no support for time-based, WRR arbitration on this VC.
22:16
MAX_TIME_SLOTS
Reject snoop transactions. This bit only has meaningful context for root ports;
therefore, returns 0b when read.
15
REJECT_SNOOP
R
Advanced packet switching. This read-only bit returns 0b to indicate that the use of this
VC is not limited to AS traffic.
14
ADV_SWITCHING
RSVD
R
R
13:8
Reserved. Returns 00 0000b when read.
Port arbitration capability. This 8-bit encoded field indicates support for the various
schemes that are supported for port (secondary PCI device) arbitration. The field is
encoded as follows:
Bit 0 = Hardware fixed arbitration (round-robin)
Bit 1 = WRR with 32 phases
Bit 2 = WRR with 64 phases
Bit 3 = WRR with 128 phases
7:0
PORT_ARB_CAP
R
Bit 4 = Time-based WRR with 128 phases
Bit 5 = WRR with 256 phases
Bits 6 and 7 = Reserved
The returned value of 01h indicates that only hardware-fixed, round-robin arbitration is
support for this VC.
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PCI Express Extended Configuration Space
5.22 VC Resource Control Register (VC0)
The VC resource control register for VC0 allows software to control VC0 and the associated port and
arbitration schemes supported by the bridge. See Table 5−18 for a complete description of the register
contents.
PCI Express extended register offset:
Register type:
Default value:
164h
Read-only, Read/Write
8000 00FFh
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 5−18. VC Resource Control Register (VC0) Description
BIT
31
FIELD NAME
VC_EN
ACCESS
DESCRIPTION
VC enable. This field is internally hardwired to 1b to indicate that this VC resource is always
enabled.
R
R
R
R
R
30:27
26:24
23:20
19:17
RSVD
Reserved. Returns 0h when read.
Virtual channel ID. This field is internally hardwired to 000b to indicate that this VC resource
is always used for VC0.
VC_ID
RSVD
Reserved. Returns 0h when read.
Port arbitration select. This read-only field returns 000b when read, because only
hardware-fixed, round-robin arbitration is supported for this VC.
PORT_ARB_SELECT
Load port arbitration table. This read-only bit returns 0b when read, because no port
arbitration table is supported for this VC.
16
LOAD_PORT_TABLE
RSVD
R
R
15:8
Reserved. Returns 00h when read.
TC/VC map. This field indicates all of the traffic classes that are mapped to this VC. A 1b in
any bit position indicates that the corresponding traffic class is enabled for this VC. A 0b
indicates that the corresponding traffic class is mapped to a different VC. The following table
is used:
Bit 0 = Traffic class 0 (This bit is read-only and returns a value of 1b)
Bit 1 = Traffic class 1
7:0
TC_VC_MAP
RW
Bit 2 = Traffic class 2
Bit 3 = Traffic class 3
Bit 4 = Traffic class 4
Bit 5 = Traffic class 5
Bit 6 = Traffic class 6
Bit 7 = Traffic class 7
The default value of FFh indicates that all eight traffic classes are initially mapped to VC0.
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5.23 VC Resource Status Register (VC0)
The VC resource status register allows software to monitor the status of the port arbitration table for this VC.
See Table 5−19 for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
16Ah
Read-only
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−19. VC Resource Status Register (VC0) Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:2
RSVD
R
Reserved. Returns 00 0000 0000 0000b when read.
VC negotiation pending. This bit is asserted when VC negotiation is in progress following
a request by software to enable or disable the VC or at startup for VC0.
1
0
VC_PENDING
RU
RU
Port arbitration table status. This bit is automatically set by hardware when any
modification is made to the port arbitration table entries for this VC within the extended
configuration space. This bit is cleared by hardware after software has requested a port
arbitration table refresh and the refresh has been completed.
PORT_TABLE_STATUS
5.24 VC Resource Capability Register (VC1)
The VC resource capability register for VC1 provides information to software regarding the port and arbitration
schemes supported by the bridge. See Table 5−20 for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
16Ch
Read-only
077F 0011h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
Table 5−20. VC Resource Capability Register (VC1) Description
BIT
31:24
23
FIELD NAME
ACCESS
DESCRIPTION
PORT_ARB_
TBL_OFFSET
Port arbitration table offset. This read-only field returns the value 07h to indicate that the port
arbitration table for this VC begins 112 bytes from the top of the VC capability structure.
R
R
R
RSVD
Reserved. Returns 0b when read.
MAX_TIME_
SLOTS
Maximum time slots. The read-only field returns the value 111 1111b to indicate that all 128 slots
are supported for time-based WRR.
22:16
REJECT_
SNOOP
Reject snoop transactions. This bit only has meaningful context for root ports; therefore, returns 0b
when read.
15
R
ADV_
SWITCHING
Advanced packet switching. This read-only bit returns the value 0b to indicate that the use of this
VC is not limited to AS traffic.
14
R
R
13:8
RSVD
Reserved. Return 00 0000b when read.
Port arbitration capability. This 8-bit encoded field indicates support for the various schemes that
are supported for port (secondary PCI device) arbitration. The field is encoded as follows:
Bit 0 = Hardware fixed arbitration (round-robin)
Bit 1 = WRR with 32 phases
Bit 2 = WRR with 64 phases
Bit 3 = WRR with 128 phases
Bit 4 = Time-based WRR with 128 phases
Bit 5 = WRR with 256 phases
PORT_
ARB_CAP
7:0
R
Bits 6 and 7 = Reserved
The returned value of 11h indicates that hardware-fixed round-robin and time-based WRR with
128 phases are both supported.
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PCI Express Extended Configuration Space
5.25 VC Resource Control Register (VC1)
The VC resource control register for VC1 allows software to control the second VC and associated port and
arbitration schemes supported by the bridge. See Table 5−21 for a complete description of the register
contents.
PCI Express extended register offset:
Register type:
Default value:
170h
Read-only, Read/Write
0100 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−21. VC Resource Control Register (VC1) Description
BIT
31
FIELD NAME
VC_EN
RSVD
ACCESS
DESCRIPTION
VC enable. This bit is used by software to enable this VC resource. Writing a 1b to this bit causes
the bridge to begin VC negotiation and set bit 1 (VC_PENDING) in the VC resource status register
for this VC (offset 176h, see Section 5.26). The default value for this bit is 0b.
RW
R
30:27
26:24
23:20
Reserved. Returns 0h when read.
Virtual channel ID. This field allows software to assign a VC ID to this VC resource. Valid values
range from 001b to 111b, because the value 000b is hardware-fixed to VC0 within the device. The
default value for this field is 001b.
VC_ID
RW
R
RSVD
Reserved. Returns 0h when read.
Port arbitration select. This read/write field allows software to define the mechanism used for port
arbitration by the bridge on this VC. The value written to this field indicates the bit position within
bits 7:0 (PORT_ARB_CAP) in the VC resource capability register for this VC (offset 16Ch, see
Section 5.24) that corresponds to the selected arbitration scheme. Values that may be written to
this field include:
PORT_ARB
_SELECT
19:17
RW
000 = Hardware-fixed round-robin (default)
100 = Time-based WRR with 128 phases
All other values are reserved for arbitrations schemes that are not supported by the bridge.
Load port arbitration table. When software writes a 1b to this bit, the bridge applies the values
written in the port arbitration table for this VC within the extended configuration space to the actual
port arbitration tables used by the device for arbitration on this VC. This bit always returns 0b when
read.
LOAD_PORT
_TABLE
16
RW
R
15:8
RSVD
Reserved. Returns 00h when read.
TC/VC map. This field indicates all of the traffic classes that are mapped to this VC. A 1b in any bit
position indicates that the corresponding traffic class is enabled for this VC. A 0b indicates that the
corresponding traffic class is mapped to a different VC. The following table is used:
Bit 0 = Traffic class 0 (This bit is read only and returns a value of 0b)
Bit 1 = Traffic class 1
Bit 2 = Traffic class 2
7:0
TC_VC_MAP
RW
Bit 3 = Traffic class 3
Bit 4 = Traffic class 4
Bit 5 = Traffic class 5
Bit 6 = Traffic class 6
Bit 7 = Traffic class 7
The default value of 00h indicates that none of the eight traffic classes are initially mapped to this
VC.
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PCI Express Extended Configuration Space
5.26 VC Resource Status Register (VC1)
The VC resource status register allows software to monitor the status of the port arbitration table for this VC.
See Table 5−22 for a complete description of the register contents.
PCI Express extended register offset:
Register type:
Default value:
176h
Read-only
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−22. VC Resource Status Register (VC1) Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Returns 00 0000 0000 0000b when read.
15:2
RSVD
R
VC negotiation pending. This bit is asserted when VC negotiation is in progress following a
request by software to enable the second VC.
1
0
VC_PENDING
RU
RU
Port arbitration table status. This bit is automatically set by hardware when any modification is
made to the port arbitration table entries for this VC within the extended configuration space.
This bit is cleared by hardware after software has requested a port arbitration table refresh and
the refresh has been completed.
PORT_TABLE
_STATUS
5.27 VC Arbitration Table
The VC arbitration table is provided to allow software to define round-robin weighting for traffic targeting the
PCI Express port. The table is divided into 32 phases. See Table 5−24 for a complete description of the register
contents.
PCI Express extended register offset:
Register type:
Default value:
180h – 18Ch
Read-only, Read/Write
0000 0000h
Table 5−23. VC Arbitration Table
REGISTER FORMAT
OFFSET
180h
Phase 7
Phase 15
Phase 23
Phase 31
Phase 6
Phase 14
Phase 22
Phase 30
Phase 5
Phase 13
Phase 21
Phase 29
Phase 4
Phase 12
Phase 20
Phase 28
Phase 3
Phase 11
Phase 19
Phase 27
Phase 2
Phase 10
Phase 18
Phase 26
Phase 1
Phase 9
Phase 17
Phase 25
Phase 0
Phase 8
Phase 16
Phase 24
184h
188h
18Ch
Each phase consists of a four-bit field as indicated below.
BIT NUMBER
RESET STATE
3
2
1
0
0
0
0
0
Table 5−24. VC Arbitration Table Entry Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
3
RSVD
R
Reserved. Returns 0b when read.
Virtual channel ID. This 3-bit field is used by software to identify the VC ID that must be allocated
this slot of arbitration bandwidth depending upon the VC arbitration scheme enabled. The default
value for this field is 000b.
2:0
VC_ARB_ID
RW
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PCI Express Extended Configuration Space
5.28 Port Arbitration Table (VC1)
The port arbitration table is provided to allow software to define round-robin weighting for traffic entering the
PCI interface. The table is divided into 128 phases.
PCI Express extended register offset:
Register type:
Default value:
1C0h – 1FCh
Read/Write
0000 0000h
Table 5−25. Port Arbitration Table
REGISTER FORMAT
OFFSET
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
1DCh
1E0h
1E4h
1E8h
1ECh
1F0h
1F4h
1F8h
1FCh
Phase 7
Phase 15
Phase 23
Phase 31
Phase 39
Phase 47
Phase 55
Phase 63
Phase 71
Phase 79
Phase 87
Phase 95
Phase 103
Phase 111
Phase 119
Phase 127
Phase 6
Phase 14
Phase 22
Phase 30
Phase 38
Phase 46
Phase 54
Phase 62
Phase 70
Phase 78
Phase 86
Phase 94
Phase 102
Phase 110
Phase 118
Phase 126
Phase 5
Phase 13
Phase 21
Phase 29
Phase 37
Phase 45
Phase 53
Phase 61
Phase 69
Phase 77
Phase 85
Phase 93
Phase 101
Phase 109
Phase 117
Phase 125
Phase 4
Phase 12
Phase 20
Phase 28
Phase 36
Phase 44
Phase 52
Phase 60
Phase 68
Phase 76
Phase 84
Phase 92
Phase 100
Phase 108
Phase 116
Phase 124
Phase 3
Phase 11
Phase 19
Phase 27
Phase 35
Phase 43
Phase 51
Phase 59
Phase 67
Phase 75
Phase 83
Phase 91
Phase 99
Phase 107
Phase 115
Phase 123
Phase 2
Phase 10
Phase 18
Phase 26
Phase 34
Phase 42
Phase 50
Phase 58
Phase 66
Phase 74
Phase 82
Phase 90
Phase 98
Phase 106
Phase 114
Phase 122
Phase 1
Phase 9
Phase 0
Phase 8
Phase 17
Phase 25
Phase 33
Phase 41
Phase 49
Phase 57
Phase 65
Phase 73
Phase 81
Phase 89
Phase 97
Phase 105
Phase 113
Phase 121
Phase 16
Phase 24
Phase 32
Phase 40
Phase 48
Phase 56
Phase 64
Phase 72
Phase 80
Phase 88
Phase 96
Phase 104
Phase 112
Phase 120
Each phase consists of a four-bit field as indicated below.
BIT NUMBER
RESET STATE
3
2
1
0
0
0
0
0
Table 5−26. Port Arbitration Table Entry Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Port arbitration select. This 4-bit field is used by software to identify the port ID (secondary PCI
device) that must be allocated to this slot of arbitration bandwidth depending upon the port
arbitration scheme enabled. The default value for this field is 0h.
3:0
PORT_SELECT
RW
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Memory-Mapped TI Proprietary Register Space
6
Memory-Mapped TI Proprietary Register Space
The programming model of the memory-mapped TI proprietary register space is unique to this device. These
custom registers are specifically designed to provide enhanced features associated with upstream
isochronous applications.
k
All bits marked with a are sticky bits and are reset by a global reset (GRST) or the internally-generated
power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST), a GRST or the
internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST,
GRST, or the internally-generated power-on reset.
Table 6−1. Device Control Memory Window Register Map
REGISTER NAME
OFFSET
00h
Upstream isochrony capabilities
Revision ID
Device control map ID
Upstream isochrony control
Upstream isochronous window 0 control
Upstream isochronous window 0 base address
Upstream isochronous window 0 limit
Upstream isochronous window 1 control
Reserved
04h
Reserved
08h
0Ch
10h
Reserved
Reserved
Reserved
14h
Upstream isochronous window 1 base address
Upstream isochronous window 1 limit
18h
1Ch
20h
Upstream isochronous window 2 control
Upstream isochronous window 2 base address
Upstream isochronous window 2 limit
24h
28h
Upstream isochronous window 3 control
2Ch
30h
Upstream isochronous window 3 base address
Upstream isochronous window 3 limit
Reserved
34h
38h−3Ch
40h
GPIO data†
GPIO control†
Serial-bus word address†
Reserved
Serial-bus control and status†
Serial IRQ edge control†
Reserved
One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Serial-bus slave address†
Serial-bus data†
Serial IRQ mode control†
Serial IRQ status
44h
48h
4Ch
†
6.1 Device Control Map ID Register
The device control map ID register identifies the TI proprietary layout for this device control map. The value
01h identifies this as a PCI Express-to-PCI bridge supporting upstream isochronous capabilities.
Device control memory window register offset:
Register type:
Default value:
00h
Read-only
01h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
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Memory-Mapped TI Proprietary Register Space
6.2 Revision ID Register
The revision ID register identifies the revision of the TI proprietary layout for this device control map. The value
00h identifies the revision as the initial layout.
Device control memory window register offset:
Register type:
Default value:
01h
Read-only
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
6.3 Upstream Isochrony Capabilities Register
The upstream isochronous capabilities register provides software information regarding the capabilities
supported by this bridge. See Table 6−2 for a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
02h
Read-only
0004h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Table 6−2. Upstream Isochronous Capabilities Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:4
RSVD
R
Reserved. Returns 000h when read.
Isochronous window count. This 4-bit field indicates the number of isochronous address
windows supported. The value 0100b indicates that 4 separate windows are supported
by the bridge.
3:0
ISOC_WINDOW_COUNT
R
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Memory-Mapped TI Proprietary Register Space
6.4 Upstream Isochrony Control Register
The upstream isochrony control register allows software to control bridge isochronous behavior. See
Table 6−3 for a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
04h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6−3. Upstream Isochrony Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:3
RSVD
R
Reserved. Returns 0 0000 0000 0000b when read.
Port arbitration level 2 enable. This bit is only valid if PORTARB_LEVEL_1_EN is set to
1b, because this enhances the behavior enabled through the assertion of that bit. If
PORTARB_LEVEL_1_EN is clear, then this bit is read-only and returns 0b when read.
2
PORTARB_LEVEL_2_EN
RW
0 = Arbiter behavior follows PORTARB_LEVEL_1_EN rules (default)
1 = Aggressive mode. The arbiter deliberately stops secondary bus masters in the
middle of their transaction to assure that isochrony is preserved.
Port arbitration level 1 enable.
0 = Arbiter behavior is controlled only by the arbiter control registers within the classic
PCI configuration space (default)
1 = Values programmed within the port arbitration table for extended VCs impact the
arbiter’s decision to assert GNT to any particular bus master. Programmed values
in the arbiter control registers within the classic PCI configuration space have no
effect when this bit is asserted.
1
0
PORTARB_LEVEL_1_EN
ISOC_ENABLE
RW
RW
Isochronous enable. Global enable bit for the upstream isochronous capability of the
bridge.
0 = Mapping of upstream traffic to TCs other than TC0 prohibited (default)
1 = Mapping of upstream traffic to TCs other than TC0 permitted
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6.5 Upstream Isochronous Window 0 Control Register
The upstream isochronous window 0 control register allows software to identify the traffic class (TC)
associated with upstream transactions targeting memory addresses in the range defined by the window. See
Table 6−4 for a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
08h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6−4. Upstream Isochronous Window 0 Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:4
RSVD
R
Reserved. Returns 000h when read.
Traffic class ID. ID of the traffic class that upstream transactions targeting the range defined
by the associated window must be mapped to. The default value for this field is 000b.
3:1
0
TC_ID
RW
RW
Isochronous window enable.
0 = Address window does not impact upstream traffic (default)
1 = Upstream transactions targeting addresses within the range of this window are applied
to the appropriate TC
ISOC_WINDOW_EN
6.6 Upstream Isochronous Window 0 Base Address Register
The upstream isochronous window 0 base address register allows software to configure the base address for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Device control memory window register offset:
Register type:
Default value:
0Ch
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6.7 Upstream Isochronous Window 0 Limit Register
The upstream isochronous window 0 limit register allows software to configure the upper address bound for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Device control memory window register offset:
Register type:
Default value:
10h
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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6.8 Upstream Isochronous Window 1 Control Register
The upstream isochronous window 1 control register allows software to identify the TC associated with
upstream transactions targeting memory addresses in the range defined by the window. See Table 6−5 for
a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
14h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6−5. Upstream Isochronous Window 1 Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:4
RSVD
R
Reserved. Returns 000h when read.
Traffic class ID. ID of the traffic class that upstream transactions targeting the range defined
by the associated window must be mapped to. The default value for this field is 000b.
3:1
0
TC_ID
RW
RW
Isochronous window enable.
0 = Address window does not impact upstream traffic (default)
1 = Upstream transactions targeting addresses within the range of this window are
applied to the appropriate TC
ISOC_WINDOW_EN
6.9 Upstream Isochronous Window 1 Base Address Register
The upstream isochronous window 1 base address register allows software to configure the base address for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Device control memory window register offset:
Register type:
Default value:
18h
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6.10 Upstream Isochronous Window 1 Limit Register
The upstream isochronous window 1 limit register allows software to configure the upper address bound for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Device control memory window register offset:
Register type:
Default value:
1Ch
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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6.11 Upstream Isochronous Window 2 Control Register
The upstream isochronous window 2 control register allows software to identify the TC associated with
upstream transactions targeting memory addresses in the range defined by the window. See Table 6−6 for
a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
20h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6−6. Upstream Isochronous Window 2 Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:4
RSVD
R
Reserved. Returns 000h when read.
Traffic class ID. ID of the traffic class that upstream transactions targeting the range defined
by the associated window must be mapped to. The default value for this field is 000b.
3:1
0
TC_ID
RW
RW
Isochronous window enable.
0 = Address window does not impact upstream traffic (default)
1 = Upstream transactions targeting addresses within the range of this window are
applied to the appropriate TC
ISOC_WINDOW_EN
6.12 Upstream Isochronous Window 2 Base Address Register
The upstream isochronous window 2 base address register allows software to configure the base address for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Device control memory window register offset:
Register type:
Default value:
24h
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6.13 Upstream Isochronous Window 2 Limit Register
The upstream isochronous window 2 limit register allows software to configure the upper address bound for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Device control memory window register offset:
Register type:
Default value:
28h
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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6.14 Upstream Isochronous Window 3 Control Register
The upstream isochronous window 3 control register allows software to identify the TC associated with
upstream transactions targeting memory addresses in the range defined by the window. See Table 6−7 for
a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
2Ch
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6−7. Upstream Isochronous Window 3 Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:4
RSVD
R
Reserved. Returns 000h when read.
Traffic class ID. ID of the traffic class that upstream transactions targeting the range defined
by the associated window must be mapped to. The default value for this field is 000b.
3:1
0
TC_ID
RW
RW
Isochronous window enable.
0 = Address window does not impact upstream traffic (default)
1 = Upstream transactions targeting addresses within the range of this window are
applied to the appropriate TC
ISOC_WINDOW_EN
6.15 Upstream Isochronous Window 3 Base Address Register
The upstream isochronous window 3 base address register allows software to configure the base address for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Device control memory window register offset:
Register type:
Default value:
30h
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6.16 Upstream Isochronous Window 3 Limit Register
The upstream isochronous window 3 limit register allows software to configure the upper address bound for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Device control memory window register offset:
Register type:
Default value:
34h
Read/Write
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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6.17 GPIO Control Register
This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of
GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO0
(CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). This register is an alias of the GPIO
control register in the classic PCI configuration space (offset B4h, see Section 4.59). See Table 6−8 for a
complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
40h
Read-only, Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6−8. GPIO Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:8
RSVD
R
Reserved. Returns 00h when read.
GPIO 7 data direction. This bit selects whether GPIO7 is in input or output mode.
7†
6†
5†
4†
3†
2†
1†
0†
GPIO7_DIR
GPIO6_DIR
GPIO5_DIR
GPIO4_DIR
GPIO3_DIR
GPIO2_DIR
GPIO1_DIR
GPIO0_DIR
RW
RW
RW
RW
RW
RW
RW
RW
0 = Input (default)
1 = Output
GPIO 6 data direction. This bit selects whether GPIO6 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 5 data direction. This bit selects whether GPIO5 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.
0 = Input (default)
1 = Output
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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6.18 GPIO Data Register
This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO
terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary
functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). The default
value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs. This
register is an alias of the GPIO data register in the classic PCI configuration space (offset B6h, see
Section 4.60). See Table 6−9 for a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
42h
Read-only, Read/Write
00XXh
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
Table 6−9. GPIO Data Register Description
DESCRIPTION
BIT
FIELD NAME
ACCESS
15:8
RSVD
R
Reserved. Returns 00h when read.
GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of
GPIO7 when in output mode.
7†
6†
5†
4†
3†
2†
1†
0†
GPIO7_Data
GPIO6_Data
GPIO5_Data
GPIO4_Data
GPIO3_Data
GPIO2_Data
GPIO1_Data
GPIO0_Data
RW
RW
RW
RW
RW
RW
RW
RW
GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of
GPIO6 when in output mode.
GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of
GPIO5 when in output mode.
GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of
GPIO4 when in output mode.
GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of
GPIO3 when in output mode.
GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of
GPIO2 when in output mode.
GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of
GPIO1 when in output mode.
GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of
GPIO0 when in output mode.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
6.19 Serial-Bus Data Register
The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this
register prior to writing the serial-bus slave address register that initiates the bus cycle. When reading data
from the serial bus, this register contains the data read after bit 5 (REQBUSY) in the serial-bus control and
status register (offset 47h, see Section 6.22) is cleared. This register is an alias for the serial-bus data register
in the PCI header (offset B0h, see Section 4.55). This register is reset by a PCI Express reset (PERST), a
GRST, or the internally-generated power-on reset.
Device control memory window register offset:
Register type:
Default value:
44h
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
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6.20 Serial-Bus Word Address Register
The value written to the serial-bus word address register represents the word address of the byte being read
from or written to on the serial-bus interface. The word address is loaded into this register prior to writing the
serial-bus slave address register that initiates the bus cycle. This register is an alias for the serial-bus word
address register in the PCI header (offset B1h, see Section 4.56). This register is reset by a PCI Express reset
(PERST), a GRST, or the internally-generated power-on reset.
Device control memory window register offset:
Register type:
Default value:
45h
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
6.21 Serial-Bus Slave Address Register
The serial-bus slave address register indicates the address of the device being targeted by the serial-bus
cycle. This register also indicates if the cycle will be a read or a write cycle. Writing to this register initiates the
cycle on the serial interface. This register is an alias for the serial-bus slave address register in the PCI header
(offset B2h, see Section 4.57). See Table 6−10 for a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
46h
Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 6−10. Serial-Bus Slave Address Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write
transaction. The default value for this field is 000 0000b.
7:1†
SLAVE_ADDR
RW
Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.
0†
RW_CMD
RW
0 = A single byte write is requested (default)
1 = A single byte read is requested
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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6.22 Serial-Bus Control and Status Register
The serial-bus control and status register controls the behavior of the serial-bus interface. This register also
provides status information about the state of the serial-bus. This register is an alias for the serial-bus control
and status register in the PCI header (offset B3h, see Section 4.58). See Table 6−11 for a complete description
of the register contents.
Device control memory window register offset:
Register type:
Default value:
47h
Read-only, Read/Write, Read/Clear
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 6−11. Serial-Bus Control and Status Register Description
BIT
7†
6
FIELD NAME
PROT_SEL
RSVD
ACCESS
DESCRIPTION
Protocol select. This bit selects the serial-bus address mode used.
RW
R
0 = Slave address and word address are sent on the serial-bus (default)
1 = Only the slave address is sent on the serial-bus
Reserved. Returns 0b when read.
Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle is in
progress.
5†
4†
REQBUSY
ROMBUSY
RU
RU
0 = No serial-bus cycle
1 = Serial-bus cycle in progress
Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the bridge is
downloading register defaults from a serial EEPROM.
0 = No EEPROM activity
1 = EEPROM download in progress
Serial EEPROM detected. This bit enables the serial-bus interface. The value of this bit controls
whether the GPIO4//SCL and GPIO5//SDA terminals are configured as GPIO signals or as
serial-bus signals. This bit is automatically set to 1b when a serial EEPROM is detected.
Note: A serial EEPROM is only detected once following PERST.
3†
SBDETECT
RWU
0 = No EEPROM present, EEPROM load process does not happen. GPIO4//SCL and
GPIO5//SDA terminals are configured as GPIO signals.
1 = EEPROM present, EEPROM load process takes place. GPIO4//SCL and GPIO5//SDA
terminals are configured as serial-bus signals.
Serial-bus test. This bit is used for internal test purposes. This bit controls the clock source for the
serial interface clock.
2†
1†
0†
SBTEST
SB_ERR
RW
RCU
RCU
0 = Serial-bus clock at normal operating frequency ~ 60 kHz (default)
1 = Serial-bus clock frequency increased for test purposes ~ 4 MHz
Serial-bus error. This bit is set when an error occurs during a software-initiated serial-bus cycle.
0 = No error
1 = Serial-bus error
Serial EEPROM load error. This bit is set when an error occurs while downloading registers from a
serial EEPROM.
ROM_ERR
0 = No Error
1 = EEPROM load error
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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6.23 Serial IRQ Mode Control Register
This register controls the behavior of the serial IRQ controller. This register is an alias for the serial IRQ mode
control register in the classic PCI configuration space (offset E0h, see Section 4.72). See Table 6−12 for a
complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
48h
Read-only, Read/Write
00h
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 6−12. Serial IRQ Mode Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:4
RSVD
R
Reserved. Returns 0h when read.
Start frame pulse width. Used to set the width of the start frame for a SERIRQ stream.
00 = 4 clocks (default)
01 = 6 clocks
3:2†
START_WIDTH
RW
10 = 8 clocks
11 = Reserved
Poll mode. This bit selects between continuous and quiet mode.
1†
0†
POLLMODE
DRIVEMODE
RW
RW
0 = Continuous mode (default)
1 = Quiet mode
Drive mode. This bit selects the behavior of the serial IRQ controller during the recovery cycle.
0 = Drive high (default)
1 = Tri-state
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
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6.24 Serial IRQ Edge Control Register
This register controls the edge mode of each IRQ in the serial IRQ stream. This register is an alias for the serial
IRQ edge control register in the classic PCI configuration space (offset E2h, see Section 4.73). See
Table 6−13 for a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
4Ah
Read/Write
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6−13. Serial IRQ Edge Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
IRQ 15 edge mode
15†
IRQ15_MODE
RW
0 = Edge mode (default)
1 = Level mode
IRQ 14 edge mode
14†
13†
12†
11†
10†
9†
IRQ14_MODE
IRQ13_MODE
IRQ12_MODE
IRQ11_MODE
IRQ10_MODE
IRQ9_MODE
IRQ8_MODE
IRQ7_MODE
IRQ6_MODE
IRQ5_MODE
IRQ4_MODE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0 = Edge mode (default)
1 = Level mode
IRQ 13 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 12 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 11 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 10 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 9 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 8 edge mode
8†
0 = Edge mode (default)
1 = Level mode
IRQ 7 edge mode
7†
0 = Edge mode (default)
1 = Level mode
IRQ 6 edge mode
6†
0 = Edge mode (default)
1 = Level mode
IRQ 5 edge mode
5†
0 = Edge mode (default)
1 = Level mode
IRQ 4 edge mode
4†
0 = Edge mode (default)
1 = Level mode
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
130
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April 2007 Revised October 2008
Memory-Mapped TI Proprietary Register Space
Table 6−13. Serial IRQ Edge Control Register Description (Continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
IRQ 3 edge mode
3†
IRQ3_MODE
RW
0 = Edge mode (default)
1 = Level mode
IRQ 2 edge mode
2†
1†
0†
IRQ2_MODE
IRQ1_MODE
IRQ0_MODE
RW
RW
RW
0 = Edge mode (default)
1 = Level mode
IRQ 1 edge mode
0 = Edge mode (default)
1 = Level mode
IRQ 0 edge mode
0 = Edge mode (default)
1 = Level mode
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
6.25 Serial IRQ Status Register
This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode IRQ
is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that are
defined as edge mode in the serial IRQ edge control register are not reported in this status register.
This register is an alias for the serial IRQ status register in the classic PCI configuration space (offset E4h,
see Section 4.74). See Table 6−14 for a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
4Ch
Read/Clear
0000h
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6−14. Serial IRQ Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
IRQ 15 asserted. This bit indicates that the IRQ has been asserted.
15
IRQ15
RCU
0 = Deasserted
1 = Asserted
IRQ 14 asserted. This bit indicates that the IRQ has been asserted.
14
13
12
11
10
9
IRQ14
IRQ13
IRQ12
IRQ11
IRQ10
IRQ9
RCU
RCU
RCU
RCU
RCU
RCU
0 = Deasserted
1 = Asserted
IRQ 13 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
IRQ 12 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
IRQ 11 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
IRQ 10 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
IRQ 9 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
131
April 2007 Revised October 2008
SCPS155C
Memory-Mapped TI Proprietary Register Space
Table 6−14. Serial IRQ Status Register Description (Continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
IRQ 8 asserted. This bit indicates that the IRQ has been asserted.
8
IRQ8
RCU
0 = Deasserted
1 = Asserted
IRQ 7 asserted. This bit indicates that the IRQ has been asserted.
7
6
5
4
3
2
1
0
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
RCU
RCU
RCU
RCU
RCU
RCU
RCU
RCU
0 = Deasserted
1 = Asserted
IRQ 6 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
IRQ 5 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
IRQ 4 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
IRQ 3 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
IRQ 2 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
IRQ 1 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
IRQ 0 asserted. This bit indicates that the IRQ has been asserted.
0 = Deasserted
1 = Asserted
132
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Electrical Characteristics
7
Electrical Characteristics
†
7.1 Absolute Maximum Ratings Over Operating Temperature Ranges
Supply voltage range:
Input voltage range,
V
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.65 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.25 V
DD_33
DD_15
CCP
I
I
I
I
I
O
V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
V : PCI Express (RX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 0.6 V
V : PCI Express REFCLK (single-ended) . . . . . . . . . . . . –0.5 V toV
V : PCI Express REFCLK (differential) . . . . . . . . . . . . . . –0.5 V toV
+ 0.5 V
CCP
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5V
+ 0.5 V
DD_33
DD_15
DD_33
DD_33
DD_15
DD_33
V : Miscellaneous 3.3-V IO . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Output voltage range: V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
V : PCI Express (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
V : Miscellaneous 3.3-V IO . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
O
Input clamp current, (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, (V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
I
I
DD
O
O
DD
Human body model (HBM) ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
Charged device model (CDM) ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
stg
†
NOTES: 1. Applies for external input and bidirectional buffers. V < 0 or V > V
or V > V
.
I
I
DD
I
CCP
2. Applies to external output and bidirectional buffers. V < 0 or V > V
or V > V .
CCP
O
O
DD
O
7.2 Recommended Operation Conditions
OPERATION
1.5 V
MIN
1.35
NOM
1.5
MAX
1.65
UNITS
V
V
V
V
DD_15
Supply voltage
V
DDA_15
DD_33
3.3 V
Supply voltage
3
3
3.3
3.6
V
DDA_33
V
DDA_33_AUX
3.3 V
5.0 V
3.3
5
3.6
V
CCP
PCI bus clamping rail voltage
V
4.75
5.25
XIO2000A
(Commercial)
0
25
70
_C
T
Operating ambient temperature range
Virtual junction temperature (Note 3)
A
XIO2000AI
(Industrial)
–40
0
25
25
85
_C
_C
T
J
115
NOTE 3: The junction temperature reflects simulated conditions. The customer is responsible for verifying junction temperature.
133
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Electrical Characteristics
7.3 Nominal Power Consumption
DEVICES
POWER STATE
VOLTS
1.5
AMPERES
0.159
0.019
0.178
0.159
0.026
0.185
0.159
0.026
0.185
0.159
0.032
0.191
0.159
0.032
0.191
WATTS
0.239
0.063
0.301
0.239
0.086
0.324
0.239
0.086
0.324
0.239
0.106
0.344
0.239
0.106
0.344
No downstream
D0 idle
3.3
Totals:
1.5
One downstream
One downstream
Two downstream
Two downstream
D0 idle
D0 active
D0 idle
3.3
Totals:
1.5
3.3
Totals:
1.5
3.3
Totals:
1.5
D0 active
3.3
Totals:
NOTES: 4. D0 idle power state: Downstream PCI device is in PCI state D0. Downstream device driver is loaded. Downstream device is not
actively transferring data.
D0 active power state: Downstream PCI device is in PCI state D0. Downstream device driver is loaded. Downstream device is
acitvely trasferring data.
5. Downstream device 1: Texas Instruments TSB43AB22a OHCI controller.
Downstream device 2: Texas Instruments TSB43AB22a OHCI controller.
No ASPM was used during power consumption testing.
Unused PCI clocks were disabled via XIO2000A PCI register 0xD8.
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Electrical Characteristics
7.4 PCI Express Differential Transmitter Output Ranges
PARAMETER
TERMINALS
MIN
NOM
MAX
UNITS
COMMENTS
Each UI is 400 ps 300 ppm. UI does not account for
SSC dictated variations.
UI
Unit interval
TXP, TXN
399.88
400 400.12
ps
See Note 6.
V
TX-DIFFp-p
V
= 2*|V
TXP
− V |
TXN
Differential
peak-to-peak output
voltage
TX-DIFFp-p
See Note 7.
TXP, TXN
0.8
1.2
V
This is the ratio of the V
TX-DIFFp-p
of the second and
V
TX-DE-RATIO
following bits after a transition divided by the V
of the first bit after a transition.
De-emphasized
differential output
voltage (ratio)
TX-DIFFp-p
TXP, TXN
TXP, TXN
−3.0
0.75
−3.5
−4.0
dB
UI
See Note 7.
The maximum transmitter jitter can be derived as
= 1 − T = 0.3 UI
T
TX-EYE
Minimum TX eye width
T
TXMAX- JITTER
See Notes 7 and 8.
Jitter is defined as the measurement variation of the
crossing points (V = 0 V) in relation to
TX-EYE
T
TX-EYE-MEDIAN-to-MAX
TX-DIFFp-p
-JITTER
Maximum time between
the jitter median and
maximum deviation
from the median
recovered TX UI. A recovered TX UI is calculated over
3500 consecutive UIs of sample data. Jitter is measured
using all edges of the 250 consecutive UIs in the center
of the 3500 UIs used for calculating the TX UI.
TXP, TXN
0.15
UI
See Notes 7 and 8.
T
T
,
TX-RISE
TX-FALL
TXP, TXN
TXP, TXN
0.125
UI
See Notes 7 and 10.
P/N TX output rise/fall
time
V
V
= RMS(|V
+ V
|/2 – V )
TX-CM-DC
V
TX-CM-ACp
TXP
of |V
TXN
+ V
TX-CM-ACp
20
mV
= DC
(avg)
|/2
TXN
RMS ac peak common
mode output voltage
TX-CM-DC
TXP
See Note 7.
V
TX-CM-DC-ACTIVE-IDLE-
|V
– V
| ꢀ 100 mV
TX-CM-DC
TX-CM-Idle-DC
DELTA
V
V
= DC
(avg)
of |V
+ V
|/2 [during L0]
TX-CM-DC
TXP
of |V
TXN
Absolute delta of dc
common mode voltage
during L0 and electrical
idle
TXP, TXN
0
100
mV
= DC
+ V |/2 [during
TXN
TX-CM-Idle-DC
(avg)
TXP
electrical idle]
See Note 7.
|V
– V
TXN-CM-DC
| ꢀ 25 mV when
V
TXP-CM-DC
TX-CM-DC-LINE-DELTA
V
= DC
= DC
of |V
of |V
|
Absolute delta of dc
common mode voltage
between P and N
TXP-CM-DC
(avg)
(avg)
TXP
TXP, TXN
TXP, TXN
0
0
25
20
mV
mV
V
|
TXN-CM-DC
TXN
See Note 7.
V
TX-IDLE-DIFFp
V
= |V
TXP-Idle
− V
| ꢀ 20 mV
TX-IDLE-DIFFp
See Note 7.
TXN-Idle
Electrical idle
differential peak output
voltage
V
TX-RCV-DETECT
The total amount of voltage change that a transmitter
can apply to sense whether a low impedance receiver is
present.
The amount of voltage
change allowed during
receiver detection
TXP, TXN
TXP, TXN
600
3.6
mV
V
V
TX-DC-CM
The allowed dc common mode voltage under any
condition
0
The TX dc common
mode voltage
135
April 2007 Revised October 2008
SCPS155C
Electrical Characteristics
PCI Express Differential Transmitter Output Ranges (continued)
PARAMETER
TX-SHORT
TERMINALS
MIN
NOM
MAX
UNITS
COMMENTS
I
The total current the transmitter can provide when
shorted to its ground.
TXP, TXN
90
mA
TX short circuit current
limit
Minimum time a transmitter must be in electrical idle.
Utilized by the receiver to start looking for an electrical
idle exit after successfully receiving an electrical idle
ordered set.
T
TX-IDLE-MIN
TXP, TXN
TXP, TXN
50
UI
UI
Minimum time spent in
electrical idle
T
TX-IDLE-SET-to-IDLE
After sending an electrical idle ordered set, the
transmitter must meet all electrical idle specifications
within this time. This is considered a debounce time for
the transmitter to meet electrical idle after transitioning
from L0.
Maximum time to
transition to a valid
electrical idle after
sending an electrical
idle ordered set
20
20
T
TX-IDLE-to-DIFF-DATA
Maximum time to meet all TX specifications when
transitioning from electrical idle to sending differential
data. This is considered a debounce time for the TX to
meet all TX specifications after leaving electrical idle.
Maximum time to
transition to valid TX
specifications after
leaving an electrical idle
condition
TXP, TXN
UI
RL
TX-DIFF
TXP, TXN
TXP, TXN
10
6
dB
dB
Measured over 50 MHz to 1.25 GHz. See Note 9.
Measured over 50 MHz to 1.25 GHz. See Note 9.
Differential return loss
RL
TX-CM
Common mode return
loss
Z
TX-DIFF-DC
TXP, TXN
80
100
120
200
Ω
TX dc differential mode low impedance
DC differential TX
impedance
Z
TX-DC
Required TXP as well as TXN dc impedance during all
states
TXP, TXN
TXP, TXN
40
75
Ω
Transmitter dc
impedance
C
All transmitters are ac-coupled and are required on the
PWB.
TX
nF
AC coupling capacitor
NOTES: 6. No test load is necessarily associated with this value.
7. Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX UIs.
8. A T = 0.75 UI provides for a total sum of deterministic and random jitter budget of T = 0.25 UI for the transmitter
TX-EYE TX-JITTER-MAX
collected over any 250 consecutive TX UIs. The T specification ensures a jitter distribution in which the
TX-EYE-MEDIAN-to-MAX-JITTER
median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive
TX UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number
of jitter points on either side is approximately equal as opposed to the averaged time value.
9. The transmitter input impedance results in a differential return loss greater than or equal to 12 dB and a common mode return loss
greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid
input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the P and N line. Note that the series
capacitors C
is optional for the return loss measurement.
TX
10. Measured between 20% and 80% at transmitter package terminals into a test load for both V
and V .
TXN
TXP
136
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April 2007 Revised October 2008
Electrical Characteristics
7.5 PCI Express Differential Receiver Input Ranges
PARAMETER
TERMINALS
MIN
NOM
MAX UNITS
COMMENTS
Each UI is 400 ps 300 ppm. UI does not account for SSC
dictated variations.
UI
Unit interval
RXP, RXN
399.88
400 400.12
ps
V
See Note 11.
V
RX-DIFFp-p
V
= 2*|V
RXP
− V |
RXN
RX-DIFFp-p
See Note 12.
RXP, RXN
RXP, RXN
0.175
0.4
1.200
Differential input
peak-to-peak voltage
The maximum interconnect media and transmitter jitter that
can be tolerated by the receiver is derived as
T
RX-EYE
UI
Minimum receiver eye
width
T
= 1 − T = 0.6 UI
RX-MAX- JITTER
See Notes 12 and 13.
Jitter is defined as the measurement variation of the
crossing points (V = 0 V) in relation to recovered
RX-EYE
T
RX-EYE-MEDIAN-to-MAX-
RX-DIFFp-p
JITTER
TX UI. A recovered TX UI is calculated over
Maximum time between
the jitter median and
maximum deviation
from the median.
3500 consecutive UIs of sample data. Jitter is measured
using all edges of the 250 consecutive UIs in the center of
the 3500 UIs used for calculating the TX UI.
RXP, RXN
RXP, RXN
0.3
UI
See Notes 12 and 13.
V
V
= RMS(|V
+ V
|/2 – V )
RX-CM-DC
V
RX-CM-ACp
RXP
of |V
RXN
+ V
RX-CM-ACp
150
mV
= DC
(avg)
|/2
RXN
AC peak common mode
input voltage
RX-CM-DC
RXP
See Note 12.
Measured over 50 MHz to 1.25 GHz with the P and N lines
biased at +300 mV and −300 mV, respectively.
RL
RX-DIFF
RXP, RXN
RXP, RXN
RXP, RXN
RXP, RXN
RXP, RXN
RXP, RXN
10
6
dB
dB
Ω
Differential return loss
See Note 14.
RL
RX-CM
Measured over 50 MHz to 1.25 GHz with the P and N lines
biased at +300 mV and −300 mV, respectively.
Common mode return
loss
See Note 14.
Z
RX-DIFF-DC
RX dc differential mode impedance
See Note 15.
80
100
50
120
60
DC differential input
impedance
Required RXP as well as RXN dc impedance (50 Ω 20%
tolerance)
Z
RX-DC
DC input impedance
40
Ω
See Notes 12 and 15.
Z
Required RXP as well as RXN dc impedance when the
receiver terminations do not have power.
RX-HIGH-IMP-DC
200K
65
Ω
Powered down dc input
impedance
See Note 16.
V
RX-IDLE-DET-DIFFp-p
V
= 2 * |V | measured at the
− V
RX-IDLE-DET-DIFFp-p
RXP RXN
175
10
mV
Electrical idle detect
threshold
receiver package terminals
T
RX-IDLE-DET-DIFF-ENTER
An unexpected electrical idle
-TIME
(V
<V
) must be recognizedno
to signal an
Unexpected electrical
idle enter detect
threshold integration
time
RX-DIFFp-p RX-IDLE-DET-DIFFp-p
RXP, RXN
ms
longer than T
unexpected idle condition.
RX-IDLE-DET-DIFF-ENTER-TIME
NOTES: 11. No test load is necessarily associated with this value.
12. Specified at the measurement point and measured over any 250 consecutive UIs. A test load must be used as the RX device when
taking measurements. If the clocks to the RX and TX are not derived from the same reference clock, then the TX UI recovered from
3500 consecutive UIs is used as a reference for the eye diagram.
137
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SCPS155C
Electrical Characteristics
13. A T
RX-EYE
= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect
specification ensures a jitter distribution in which the median
collected any 250 consecutive UIs. The T
RX-EYE-MEDIAN-to-MAX-JITTER
and the maximum deviation from the median is less than half of the total UI jitter budget collected over any 250 consecutive TX UIs.
It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of
jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived
from the same reference clock, then the TX UI recovered from 3500 consecutive UIs must be used as the reference for the eye
diagram.
14. The receiver input impedance results in a differential return loss greater than or equal to 15 dB with the P line biased to 300 mV and
the N line biased to −300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range
of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss
measurements for is 50 Ω to ground for both the P and N line (i.e., as measured by a Vector Network Analyzer with 50-Ω probes).
The series capacitors C
is optional for the return loss measurement.
TX
15. Impedance during all link training status state machine (LTSSM) states. When transitioning from a PCI Express reset to the detect
state (the initial state of the LTSSM) there is a 5-ms transition time before receiver termination values must be met on the
unconfigured lane of a port.
16. The RX dc common mode impedance that exists when no power is present or PCI Express reset is asserted. This helps ensure that
the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV
above the RX ground.
138
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April 2007 Revised October 2008
Electrical Characteristics
7.6 PCI Express Differential Reference Clock Input Ranges
PARAMETER
IN-DIFF
TERMINALS
MIN
NOM
MAX
UNITS
COMMENTS
f
REFCLK+
REFCLK−
The input frequency is 100 MHz + 300 ppm and
− 2800 ppm including SSC-dictated variations.
100
MHz
Differential input
frequency
f
IN-SE
REFCLK+
125
MHz
V
The input frequency is 125 MHz 300 ppm.
Single-ended input
frequency
V
RX-DIFFp-p
REFCLK+
REFCLK−
0.175
1.200
V
= 2*|V
REFCLK+
− V |
REFCLK−
Differential input
peak-to-peak voltage
RX-DIFFp-p
Single-ended, reference clock mode high-level
input voltage
V
REFCLK+
REFCLK+
0.7 V
V
DDA_33
V
V
IH-SE
DDA_33
Single-ended, reference clock mode low-level
input voltage
V
V
0
0.3 V
IL-SE
DDA_33
V
V
= RMS( |V
+V
|/2 –
|/2
RX-CM-ACp
RX-CM-ACp
RX-CM-DC
REFCLK+ REFCLK−
REFCLK+
REFCLK−
)
140
mV
AC peak common
mode input voltage
V
=DC
of|V
+V
RX-CM-DC
(avg) REFCLK+ REFCLK−
REFCLK+
REFCLK−
Differential and single-ended waveform input
duty cycle
Duty cycle
40%
60%
Z
RX-DIFF-DC
REFCLK+
REFCLK−
20
20
kΩ
kΩ
REFCLK+/− dc differential mode impedance
DC differential input
impedance
Z
REFCLK+
REFCLK−
RX-DC
DC input impedance
REFCLK+ dc single-ended mode impedance
NOTE 17: The XIO2000A is compliant with the defined system jitter models for a PCI-Express reference clock and associated TX/RX link. These
system jitter models are described in the PCI-Express Jitter Modeling, Revision 1.0RD document. Any usage of the XIO2000A in a
system configuration that does not conform to the defined system jitter models requires the system designer to validate the system jitter
budgets.
139
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SCPS155C
Electrical Characteristics
7.7 Electrical Characteristics Over Recommended Operating Conditions (PCI Bus)
TEST
CONDITIONS
PARAMETER
OPERATION
MIN
MAX
UNITS
V
V
V
V
= 3.3 V
= 5.0 V
= 3.3 V
= 5.0 V
0.5 V
V
V
CCP
CCP
CCP
CCP
DD_33
CCP
V
V
High-level input voltage (Note 18)
Low-level input voltage (Note 18)
V
V
IH
0.5 V
DD_33
0
CCP
0.3 V
0.3 V
DD_33
IL
0
0
0
1
DD_33
V
V
Input voltage
V
CCP
V
V
I
Output voltage (Note 19)
V
O
DD_33
4
t
t
Input transition time (t
rise
and t
)
ns
V
fall
V
High-level output voltage (Note 19)
Low-level output voltage (Note 19)
V
V
V
V
V
V
I
I
= −32 mA
= 32 mA
0.7 V
DD_33
OH
OL
DD_33
OH
V
0.18 V
V
DD_33
OL
DD_33
10
= 3.3 V
V = 0 to V
I
CCP
CCP
CCP
CCP
CCP
CCP
CCP
CCP
I
I
High-impedance, output current (Note 19)
Input current (Note 18)
µA
µA
OZ
= 5.0 V
= 3.3 V
= 5.0 V
V = 0 to V
70
10
70
I
V = 0 to V
I
I
V = 0 to V
I
NOTES: 18. Applies to external inputs and bidirectional buffers.
19. Applies to external outputs and bidirectional buffers.
Note: This table applies to CLK, CLKOUT6:0, AD31:0, C/BE[3:0], DEVSEL, FRAME, GNT5:0, INTD:A,
IRDY, PAR, PERR, REQ5:0, PRST, SERR, STOP, TRDY, SERIRQ, M66EN, and LOCK terminals.
7.8 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O)
TEST
CONDITIONS
PARAMETER
OPERATION
MIN
MAX
UNITS
V
V
V
V
High-level input voltage (Note 20)
Low-level input voltage (Note 20)
Input voltage
V
0.7V
DD_33
V
0.3 V
V
V
V
IH
IL
I
DD_33
DD_33
DD_33
DD_33
V
0
0
0
0
DD_33
V
Output voltage (Note 21)
V
V
O
DD_33
25
t
t
Input transition time (t
rise
and t
)
ns
V
fall
V
hys
V
OH
V
OL
Input hysteresis (Note 23)
High-level output voltage
Low-level output voltage
0.13V
DD_33
V
V
V
I
I
= −4 mA
= 4 mA
0.8V
DD_33
V
DD_33
DD_33
DD_33
OH
0.22V
DD_33
V
OL
I
I
I
High-impedance, output current (Note 21)
V = 0 to V
20
100
1
µA
OZ
I
DD_33
DD_33
DD_33
High-impedance, output current with internal pullup or
pulldown (Note 24)
V
V = 0 to V
µA
µA
OZP
I
DD_33
DD_33
I
Input current (Note 22)
V
V = 0 to V
I
NOTES: 20. Applies to external inputs and bidirectional buffers.
21. Applies to external outputs and bidirectional buffers.
22. Applies to external input buffers.
23. Applies to PERST, GRST, and PME.
24. Applies to GRST (pullup), EXT_ARB_EN (pulldown), CLKRUN_EN (pulldown), and most GPIO (pullup).
Note: This table applies to PERST, WAKE, REFCLK_SEL, PME, CLKRUN_EN, EXT_ARB_EN, GRST,
GPIO7:0, and all RSVD input terminals.
140
SCPS155C
April 2007 Revised October 2008
Electrical Characteristics
7.9 PCI Clock Timing Requirements Over Recommended Operating Conditions
33 MHZ
MIN MAX
66 MHZ
MIN MAX
PARAMETER
UNITS
t
t
t
Cycle time, CLK
30
11
11
1
15
6
30
ns
ns
ns
c
Pulse duration (width), CLK high
Pulse duration (width), CLK low
wH
wL
6
t
t
rise
fall
Slew rate, CLK
1.5
4
1.5
4
V/ns
t
t
t
CLKOUT6:0 duty cycle
40%
60%
0.5
40%
60%
0.5
dc
CLKOUT6:0 skew between clock outputs
Setup time, CLKOUT6:0 stable before PRST is deasserted
ns
skew
su
100
100
µs
7.10 PCI Bus Timing Requirements Over Recommended Operating Conditions
33 MHZ
MIN MAX
11
66 MHZ
MIN MAX
TEST
CONDITION
PARAMETER
UNITS
ns
C
C
C
C
C
C
C
C
= 50 pF
= 30 pF
= 50 pF
= 30 pF
= 50 pF
= 30 pF
= 50 pF
= 30 pF
L
L
L
L
L
L
L
L
t
pd
t
pd
t
on
t
off
CLK to shared signal valid propagation delay time
CLK to shared signal invalid propagation delay time
Enable time, high-impedance-to-active delay time from CLK
Disable time, active-to-high-impedance delay time from CLK
6
2
2
ns
1
1
ns
28
ns
14
t
t
Setup time on shared signals before CLK valid (rising edge)
Hold time on shared signals after CLK valid (rising edge)
7
0
3
0
ns
ns
su
h
Note: The PCI shared signals are AD31:0, C/BE3:0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL,
LOCK, SERIRQ, PAR, PERR, SERR, and CLKRUN.
141
April 2007 Revised October 2008
SCPS155C
Electrical Characteristics
7.11 PCI Bus Parameter Measurement Information
LOAD CIRCUIT PARAMETERS
†
I
OL
TIMING
C
I
I
V
LOAD
(pF)
OL
OH
LOAD
(V)
PARAMETER
(mA)
(mA)
t
0
3
PZH
Test
Point
t
30/50
12
−12
en
t
t
t
PZL
PHZ
PLZ
From Output
Under Test
V
LOAD
t
t
12
12
30/50
30/50
−12
−12
1.5
‡
dis
pd
C
LOAD
†
‡
C
V
includes the typical load-circuit distributed capacitance.
LOAD
LOAD
I
OH
− V
OL
= 50 Ω, where V
= 0.6 V, I
OL
= 12 mA
OL
I
OL
LOAD CIRCUIT
V
Timing
Input
(see Note A )
DD
V
DD
50% V
DD
High-Level
Input
50% V
50% V
DD
DD
0 V
0 V
t
h
t
su
t
w
Data
Input
V
DD
90% V
DD
50% V
V
DD
50% V
DD
10% V
t
DD
DD
Low-Level
Input
0 V
50% V
50% V
DD
DD
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
INPUT RISE AND FALL TIMES
V
DD
Output
Control
(low-level
enabling)
50% V
50% V
DD
DD
V
0 V
DD
Input
(see Note A)
t
50% V
DD
50% V
DD
PZL
t
PLZ
0 V
t
pd
V
t
t
DD
pd
≈ 50% V
V
Waveform 1
(see Note B)
DD
OH
50% V
DD
In-Phase
Output
V
+ 0.3 V
OL
50% V
DD
50% V
DD
V
OL
V
OL
t
PHZ
t
pd
t
PZH
pd
V
OH
V
OH
V
− 0.3 V
OH
Out-of-Phase
Output
Waveform 2
(see Note B)
50% V
DD
50% V
DD
50% V
DD
≈ 50% V
0 V
DD
V
OL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the
following characteristics: PRR = 1 MHz, Z = 50 Ω, t ≤ 6 ns, t ≤ 6 ns.
O
r
f
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. For t
PLZ
and t , V
PHZ OL
and V are measured values.
OH
Figure 7−1. Load Circuit And Voltage Waveforms
142
SCPS155C
April 2007 Revised October 2008
Electrical Characteristics
7.12 PCI Bus Parameter Measurement Information
t
wH
t
wL
2 V
0.8 V
2 V min Peak-to-Peak
t
t
fall
rise
t
c
Figure 7−2. CLK Timing Waveform
CLK
t
w
PRST
t
su
Figure 7−3. PRST Timing Waveforms
CLK
1.5 V
t
t
pd
1.5 V
pd
t
Valid
PCI Output
PCI Input
t
on
off
Valid
t
su
t
h
Figure 7−4. Shared Signals Timing Waveforms
143
April 2007 Revised October 2008
SCPS155C
Glossary
8
Glossary
ACRONYM
DEFINITION
BIST
Built-in self test
ECRC
End-to-end cyclic redundancy code
EEPROM
Electrically erasable programmable read-only memory
GP
General purpose
GPIO
General-purpose input output
ID
IF
Identification
Interface
IO
I2S
Input output
Inter IC sound
LPM
LSB
Link power management
Least significant bit
MSB
MSI
Most significant bit
Message signaled interrupts
PCI
PME
QoS
RX
Peripheral component interface
PCI power management event
Quality-of-service
Receive
SCL
SDA
Serial-bus clock
Serial-bus data
TC
Traffic class
TLP
TX
Transaction layer packet or protocol
Transmit
VC
Virtual channel
WRR
Weighted round-robin
144
SCPS155C
April 2007 Revised October 2008
Mechanical Data
9
Mechanical Data
The XIO2000A/XIO2000AI devices is available in the 175−ball lead−free (Pb atomic number 82) Microstar
BGA package (ZHH), the 175-ball lead-free (Pb atomic number 82) MicroStar BGA package ZHC, the 201-ball
MicroStar BGA package (GZZ – XIO2000A Only,) or the 201-ball lead-free (Pb atomic number 82) MicroStar
BGA package (ZZZ). The following figures show the mechanical dimensions for the packages. The GZZ and
ZZZ packages are mechanically identical.
145
April 2007 Revised October 2008
SCPS155C
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
XIO2000AZAV
XIO2000AZAY
XIO2000AZHH
ACTIVE
ACTIVE
LIFEBUY
NFBGA
NFBGA
ZAV
ZAY
ZHH
201
175
175
126
160
160
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
0 to 70
0 to 70
0 to 70
XIO2000A
SNAGCU
SNAGCU
XIO2000A
XIO2000A
BGA
MICROSTAR
XIO2000AZZZ
LIFEBUY
BGA
ZZZ
201
126
RoHS & Green
SNAGCU
Level-3-260C-168 HR
0 to 70
XIO2000A
MICROSTAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jan-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
ZAY0175A
NFBGA - 1.4 mm max height
S
C
A
L
E
1
.
2
0
0
PLASTIC BALL GRID ARRAY
12.1
11.9
B
A
BALL A1
CORNER
12.1
11.9
1.4 MAX
C
SEATING PLANE
0.45
0.35
⌓ 0.12 C
10.4 TYP
(0.8)
(0.8)
SYMM
℄
P
N
M
L
K
J
SYMM
℄
H
G
10.4 TYP
F
E
D
C
0.55
175X
0.45
B
A
⌀0.15Ⓜ C A B
⌖
⌀0.08Ⓜ C
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0.8 TYP
0.8 TYP
4219814/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZAY0175A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
175X ( 0.4)
(0.8) TYP
1
2
4
5
7
13
3
9
10
11
14
6
8
12
A
B
C
D
E
F
G
H
J
SYMM
℄
K
L
M
N
P
SYMM
℄
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED METAL
(
0.4)
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
METAL EDGE
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219814/A 05/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZAY0175A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
175X ( 0.4)
(0.8) TYP
1
2
4
5
7
13
3
9
10
11
14
6
8
12
A
B
C
D
E
F
G
H
J
SYMM
℄
K
L
M
N
P
SYMM
℄
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4219814/A 05/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
NFBGA - 1.4 mm max height
ZAV0201A
PLASTIC BALL GRID ARRAY
A
15.1
14.9
B
BALL A1 CORNER
15.1
14.9
1.4 MAX
C
SEATING PLANE
BALL TYP
0.45
0.35
0.12 C
12.8 TYP
U
T
R
P
N
M
L
K
J
SYMM
12.8
TYP
H
G
F
0.55
201X Ø
0.45
E
D
0.15
0.05
C
C
A B
C
B
A
(1.1) TYP
0.8 TYP
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
SYMM
0.8 TYP
(1.1) TYP
4225153/A 08/2019
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
ZAV0201A
SYMM
(0.8) TYP
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
201X (Ø 0.4)
U
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
LAND PATTERN EXAMPLE
SCALE: 8X
0.05 MIN
0.05 MAX
ALL AROUND
ALL AROUND
EXPOSED
METAL
METAL UNDER
SOLDER MASK
(Ø 0.40)
SOLDER MASK
OPENING
(Ø 0.40)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225153/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
ZAV0201A
SYMM
(0.8) TYP
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
201X (Ø 0.4)
U
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
SOLDER PASTE EXAMPLE
BASED ON 0.150 mm THICK STENCIL
SCALE: 18X
4225153/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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