XIO3130NMH [TI]
集成 PCI Express® (PCIe) 1:3 4 端口 4 通道分组交换机 | NMH | 196 | 0 to 70;
| 型号： | XIO3130NMH |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 集成 PCI Express® (PCIe) 1:3 4 端口 4 通道分组交换机 | NMH | 196 | 0 to 70 PC 控制器 微控制器 总线控制器 微控制器和处理器 |
| 文件： | 总139页 (文件大小：1627K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XIO3130
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLLS693C
May 2007–Revised June 2008
XIO3130
SLLS693C–MAY 2007–REVISED JUNE 2008
www.ti.com
Contents
1
2
Features............................................................................................................................ 11
Introduction....................................................................................................................... 12
2.1
2.2
2.3
2.4
2.5
2.6
Description .................................................................................................................. 12
Related Documents ........................................................................................................ 12
Document Conventions.................................................................................................... 13
Ordering Information ...................................................................................................... 13
Terminal Assignments ..................................................................................................... 14
Terminal Descriptions...................................................................................................... 17
3
Description........................................................................................................................ 22
3.1
Power-Up/Power-Down Sequencing..................................................................................... 22
3.1.1
Power-Up Sequence ............................................................................................ 22
Power-Down Sequence......................................................................................... 23
3.1.2
3.2
Express Interface........................................................................................................... 23
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
External Reference Clock ...................................................................................... 23
Clock Generator ................................................................................................. 23
Beacon............................................................................................................ 24
WAKE ............................................................................................................ 24
Initial Flow Control Credits ..................................................................................... 24
PCI Express Message Transactions.......................................................................... 24
3.3
3.4
GPIO Terminals ............................................................................................................ 25
Serial EEPROM ............................................................................................................ 25
3.4.1
3.4.2
3.4.3
3.4.4
Serial Bus Interface Implementation .......................................................................... 26
Serial Bus Interface Protocol................................................................................... 26
Serial Bus EEPROM Application .............................................................................. 28
Accessing Serial Bus Devices Through Software........................................................... 31
3.5
Switch Reset Features..................................................................................................... 31
4
XIO3130 Configuration Register Space ................................................................................. 33
4.1
PCI Configuration Register Space Overview ........................................................................... 33
PCI Express Upstream Port Registers .................................................................................. 34
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
PCI Configuration Space (Upstream Port) Register Map .................................................. 35
Vendor ID Register.............................................................................................. 36
Device ID Register .............................................................................................. 36
Command Registers ............................................................................................ 36
Status Register .................................................................................................. 37
Class Code and Revision ID Register ........................................................................ 39
Cache Line Size Register ...................................................................................... 39
Primary Latency Timer Register............................................................................... 39
Header Type Register .......................................................................................... 40
4.2.10 BIST Register .................................................................................................... 40
4.2.11 Primary Bus Number............................................................................................ 40
4.2.12 Secondary Bus Number ........................................................................................ 40
4.2.13 Subordinate Bus Number....................................................................................... 41
4.2.14 Secondary Latency Timer Register ........................................................................... 41
4.2.15 I/O Base Register................................................................................................ 41
4.2.16 I/O Limit Register ................................................................................................ 42
4.2.17 Secondary Status Register..................................................................................... 42
4.2.18 Memory Base Register ......................................................................................... 43
4.2.19 Memory Limit Register.......................................................................................... 43
4.2.20 Pre-fetchable Memory Base Register......................................................................... 43
4.2.21 Pre-Fetchable Memory Limit Register ........................................................................ 44
2
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4.2.22 Pre-Fetchable Base Upper 32 Bits Register................................................................. 44
4.2.23 Pre-fetchable Limit Upper 32 Bits Register .................................................................. 45
4.2.24 I/O Base Upper 16 Bits Register .............................................................................. 45
4.2.25 I/O Limit Upper 16 Bits Register............................................................................... 45
4.2.26 Capabilities Pointer Register................................................................................... 45
4.2.27 Interrupt Line Register .......................................................................................... 46
4.2.28 Interrupt Pin Register ........................................................................................... 46
4.2.29 Bridge Control Register......................................................................................... 46
4.2.30 Capability ID Register........................................................................................... 48
4.2.31 Next-Item Pointer Register ..................................................................................... 48
4.2.32 Power Management Capabilities Register ................................................................... 48
4.2.33 Power Management Control/Status Register ................................................................ 49
4.2.34 Power Management Bridge Support Extension Register .................................................. 50
4.2.35 Power Management Data Register ........................................................................... 50
4.2.36 MSI Capability ID Register ..................................................................................... 50
4.2.37 Next-Item Pointer Register ..................................................................................... 50
4.2.38 MSI Message Control Register ................................................................................ 51
4.2.39 MSI Message Address Register............................................................................... 51
4.2.40 MSI Message Upper Address Register....................................................................... 52
4.2.41 MSI Message Data Register ................................................................................... 52
4.2.42 Capability ID Register........................................................................................... 52
4.2.43 Next-Item Pointer Register ..................................................................................... 52
4.2.44 Subsystem Vendor ID Register................................................................................ 53
4.2.45 Subsystem ID Register ......................................................................................... 53
4.2.46 PCI Express Capability ID Register........................................................................... 53
4.2.47 Next-Item Pointer Register ..................................................................................... 54
4.2.48 PCI Express Capabilities Register ............................................................................ 54
4.2.49 Device Capabilities Register ................................................................................... 54
4.2.50 Device Control Register ........................................................................................ 55
4.2.51 Device Status Register ......................................................................................... 56
4.2.52 Link Capabilities Register ...................................................................................... 57
4.2.53 Link Control Register............................................................................................ 58
4.2.54 Link Status Register............................................................................................. 59
4.2.55 Serial Bus Data Register ....................................................................................... 59
4.2.56 Serial Bus Index Register ...................................................................................... 59
4.2.57 Serial Bus Slave Address Register............................................................................ 60
4.2.58 Serial Bus Control and Status Register ...................................................................... 60
4.2.59 Upstream Port Link PM Latency Register.................................................................... 61
4.2.60 Global Chip Control Register .................................................................................. 63
4.2.61 GPIO A Control Register ....................................................................................... 64
4.2.62 GPIO B Control Register ....................................................................................... 66
4.2.63 GPIO C Control Register ....................................................................................... 68
4.2.64 GPIO D Control Register ....................................................................................... 70
4.2.65 GPIO Data Register............................................................................................. 72
4.2.66 TI Proprietary Register.......................................................................................... 75
4.2.67 TI Proprietary Register.......................................................................................... 75
4.2.68 TI Proprietary Register.......................................................................................... 75
4.2.69 TI Proprietary Register.......................................................................................... 76
4.2.70 TI Proprietary Register.......................................................................................... 76
4.2.71 TI Proprietary Register.......................................................................................... 76
4.2.72 Subsystem Access Register ................................................................................... 77
4.2.73 General Control Register ....................................................................................... 77
4.2.74 Downstream Ports Link PM Latency Register ............................................................... 78
Contents
3
XIO3130
SLLS693C–MAY 2007–REVISED JUNE 2008
www.ti.com
4.2.75 Global Switch Control Register ................................................................................ 79
4.2.76 Advanced Error Reporting Capability ID Register........................................................... 80
4.2.77 Next Capability Offset/Capability Version Register ......................................................... 80
4.2.78 Uncorrectable Error Status Register .......................................................................... 80
4.2.79 Uncorrectable Error Mask Register ........................................................................... 81
4.2.80 Uncorrectable Error Severity Register ........................................................................ 82
4.2.81 Correctable Error Status Register............................................................................. 83
4.2.82 Correctable Error Mask Register .............................................................................. 84
4.2.83 Advanced Error Capabilities and Control Register.......................................................... 85
4.2.84 Header Log Register ............................................................................................ 85
PCI Express Downstream Port Registers............................................................................... 86
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
PCI Configuration Space (Downstream Port) Register Map............................................... 86
Vendor ID Register.............................................................................................. 87
Device ID Register .............................................................................................. 87
Command Register.............................................................................................. 87
Status Register .................................................................................................. 88
Class Code and Revision ID Register ........................................................................ 89
Cache Line Size Register ...................................................................................... 90
Primary Latency Timer Register............................................................................... 90
Header Type Register .......................................................................................... 90
4.3.10 BIST Register .................................................................................................... 90
4.3.11 Primary Bus Number............................................................................................ 91
4.3.12 Secondary Bus Number ........................................................................................ 91
4.3.13 Subordinate Bus Number....................................................................................... 91
4.3.14 Secondary Latency Timer Register ........................................................................... 91
4.3.15 I/O Base Register................................................................................................ 92
4.3.16 I/O Limit Register ................................................................................................ 92
4.3.17 Secondary Status Register..................................................................................... 92
4.3.18 Memory Base Register ......................................................................................... 93
4.3.19 Memory Limit Register.......................................................................................... 94
4.3.20 Pre-fetchable Memory Base Register......................................................................... 94
4.3.21 Pre-fetchable Memory Limit Register ......................................................................... 94
4.3.22 Pre-fetchable Base Upper 32 Bits Register.................................................................. 95
4.3.23 Pre-fetchable Limit Upper 32 Bits Register .................................................................. 95
4.3.24 I/O Base Upper 16 Bits Register .............................................................................. 96
4.3.25 I/O Limit Upper 16 Bits Register............................................................................... 96
4.3.26 Capabilities Pointer Register................................................................................... 96
4.3.27 Interrupt Line Register .......................................................................................... 97
4.3.28 Interrupt Pin Register ........................................................................................... 97
4.3.29 Bridge Control Register......................................................................................... 97
4.3.30 Capability ID Register........................................................................................... 99
4.3.31 Next-Item Pointer Register ..................................................................................... 99
4.3.32 Power Management Capabilities Register ................................................................... 99
4.3.33 Power Management Control/Status Register............................................................... 100
4.3.34 Power Management Bridge Support Extension Register................................................. 101
4.3.35 Power Management Data Register.......................................................................... 101
4.3.36 MSI Capability ID Register.................................................................................... 101
4.3.37 Next-Item Pointer Register.................................................................................... 101
4.3.38 MSI Message Control Register............................................................................... 102
4.3.39 MSI Message Address Register ............................................................................. 102
4.3.40 MSI Message Upper Address Register ..................................................................... 103
4.3.41 MSI Message Data Register.................................................................................. 103
4.3.42 Capability ID Register ......................................................................................... 103
4
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4.3.43 Next-Item Pointer Register.................................................................................... 104
4.3.44 Subsystem Vendor ID Register .............................................................................. 104
4.3.45 Subsystem ID Register........................................................................................ 104
4.3.46 PCI Express Capability ID Register ......................................................................... 104
4.3.47 Next-Item Pointer Register.................................................................................... 105
4.3.48 PCI Express Capabilities Register........................................................................... 105
4.3.49 Device Capabilities Register.................................................................................. 105
4.3.50 Device Control Register....................................................................................... 106
4.3.51 Device Status Register........................................................................................ 107
4.3.52 Link Capabilities Register ..................................................................................... 108
4.3.53 Link Control Register .......................................................................................... 109
4.3.54 Link Status Register ........................................................................................... 110
4.3.55 Slot Capabilities Register ..................................................................................... 110
4.3.56 Slot Control Register .......................................................................................... 112
4.3.57 Slot Status Register............................................................................................ 114
4.3.58 TI Proprietary Register ........................................................................................ 115
4.3.59 TI Proprietary Register ........................................................................................ 115
4.3.60 TI Proprietary Register ........................................................................................ 116
4.3.61 General Control Register...................................................................................... 116
4.3.62 L0s Idle Timeout Register..................................................................................... 118
4.3.63 General Slot Info Register .................................................................................... 118
4.3.64 Advanced Error Reporting Capabilities ID Register ....................................................... 119
4.3.65 Next Capability Offset/Capability Version Register........................................................ 119
4.3.66 Uncorrectable Error Status Register......................................................................... 119
4.3.67 Uncorrectable Error Mask Register.......................................................................... 120
4.3.68 Uncorrectable Error Severity Register ...................................................................... 121
4.3.69 Correctable Error Status Register ........................................................................... 122
4.3.70 Correctable Error Mask Register............................................................................. 123
4.3.71 Advanced Error Capabilities and Control Register ........................................................ 123
4.3.72 Header Log Register .......................................................................................... 124
5
PCI Hot Plug Implementation Overview ............................................................................... 125
5.1
PCI Hot Plug Architecture Overview ................................................................................... 125
PCI Hot Plug Timing...................................................................................................... 126
5.2
5.2.1
Power-Up Cycle ................................................................................................ 126
5.2.1.1 NonPCI Hot Plug Power-Up Cycle................................................................ 127
5.2.1.2 PCI Hot Plug Power-Up Cycle With PWRGDn Feedback ..................................... 127
5.2.1.3 PCI Hot Plug Power-Up Cycle With No PWRGDn Feedback................................. 127
Power-Down Cycles ........................................................................................... 128
5.2.2.1 Normal Power-Down................................................................................ 128
5.2.2.2 Surprise Removal ................................................................................... 129
5.2.2.3 PWRGDn De-Assertion ............................................................................ 129
PMI_Turn_Off and PME_To_Ack Messages............................................................... 129
Debounce Circuits ............................................................................................. 130
HP_INTX Pin ................................................................................................... 130
5.2.2
5.2.3
5.2.4
5.2.5
6
Electrical Characteristics................................................................................................... 131
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ............................................................................................. 131
Recommended Operating Conditions.................................................................................. 131
PCI Express Differential Transmitter Output Ranges ................................................................ 132
PCI Express Differential Receiver Input Ranges ..................................................................... 133
PCI Express Differential Reference Clock Input Ranges............................................................ 134
PCI Express Reference Clock Output Requirements................................................................ 135
3.3-V I/O Electrical Characteristics ..................................................................................... 136
Contents
5
XIO3130
SLLS693C–MAY 2007–REVISED JUNE 2008
www.ti.com
6.8
POWER CONSUMPTION ............................................................................................... 136
6
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List of Figures
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
4-1
5-1
5-2
5-3
5-4
5-5
5-6
Block Diagram ..................................................................................................................... 22
Power-Up Sequence Diagram................................................................................................... 23
Power-Down Sequence Diagram ............................................................................................... 23
Serial EEPROM Applications.................................................................................................... 26
Serial-Bus Start/Stop Conditions and Bit Transfers .......................................................................... 27
Serial-Bus Protocol Acknowledge............................................................................................... 27
Serial-Bus Protocol – Byte Write................................................................................................ 27
Serial-Bus Protocol – Byte Read................................................................................................ 28
Serial-Bus Protocol – Multiple-Byte Read ..................................................................................... 28
XIO3130 Enumerations Topology............................................................................................... 34
NonPCI Hot Plug Power-Up Cycle ............................................................................................ 127
PCI Hot Plug Power-Up Cycle With PWFRDn Feedback .................................................................. 127
PCI Hot Plug Power-Up Cycle With No PWGRDn Feedback ............................................................. 128
Normal Power-Down ............................................................................................................ 128
Surprise Removal................................................................................................................ 129
Effect When PWFRGn Goes Low ............................................................................................. 129
List of Figures
7
XIO3130
SLLS693C–MAY 2007–REVISED JUNE 2008
www.ti.com
List of Tables
2-1
XIO3130 Terminal Assignments ................................................................................................ 14
XIO3130 Terminals Sorted Alphanumerically ................................................................................. 15
XIO3130 Signal Names Sorted Alphabetically ................................................................................ 16
Power Supply Terminals ......................................................................................................... 17
Combined Power Terminals ..................................................................................................... 17
Ground Terminals ................................................................................................................. 18
PCI Express Reference Clock Terminals ...................................................................................... 18
PCI Express Terminals........................................................................................................... 19
PCI Hot Plug Strapping Terminals.............................................................................................. 19
GPIO Terminals ................................................................................................................... 20
Miscellaneous Terminals......................................................................................................... 21
Initial Flow Control Credit Advertisements..................................................................................... 24
Messages Supported by the XIO3130 ......................................................................................... 25
EEPROM Register Loading Map................................................................................................ 29
Register for Programming Serial-Bus Devices ................................................................................ 31
Switch Reset Options............................................................................................................. 32
PCI Express Upstream Port Configuration Register Map (Type 1)......................................................... 35
Extended Configuration Space (Upstream Port).............................................................................. 36
Bit Descriptions – Command Register ......................................................................................... 37
Bit Descriptions – Status Register .............................................................................................. 38
Bit Descriptions – Class Code and Revision ID Register.................................................................... 39
Bit Descriptions – I/O Base Register ........................................................................................... 41
Bit Descriptions – I/O Limit Register............................................................................................ 42
Bit Descriptions – Secondary Status Register ................................................................................ 42
Bit Descriptions – Memory Base Register ..................................................................................... 43
Bit Descriptions – Memory Limit Register...................................................................................... 43
Bit Descriptions – Pre-fetchable Memory Base Register .................................................................... 43
Bit Descriptions – Pre-fetchable Memory Limit Register..................................................................... 44
Bit Descriptions – Pre-fetchable Base Upper 32 Bits Register.............................................................. 44
Bit Descriptions – Pre-fetchable Limit Upper 32 Bits Register .............................................................. 45
Bit Descriptions – I/O Base Upper 16 Bits Register .......................................................................... 45
Bit Descriptions – I/O Limit Upper 16 Bits Register .......................................................................... 45
Bit Descriptions – Bridge Control Register..................................................................................... 47
Bit Descriptions – Power Management Capabilities Register............................................................... 48
Bit Descriptions – Power Management Control/Status Register............................................................ 49
Bit Descriptions – PM Bridge Support Extension Register .................................................................. 50
Bit Descriptions – MSI Message Control Register............................................................................ 51
Bit Descriptions – MSI Message Address Register........................................................................... 51
Bit Descriptions – MSI Data Register........................................................................................... 52
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
8
List of Tables
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4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
4-46
4-47
4-48
4-49
4-50
4-51
4-52
4-53
4-54
4-55
4-56
4-57
4-58
4-59
4-60
4-61
4-62
4-63
4-64
Bit Descriptions – PCI Express Capabilities Register ........................................................................ 54
Bit Descriptions – Device Capabilities Register............................................................................... 55
Bit Descriptions – Device Control Register .................................................................................... 55
Bit Descriptions – Device Status Register ..................................................................................... 56
Bit Descriptions – Link Capabilities Register .................................................................................. 57
Bit Descriptions – Link Control Register ....................................................................................... 58
Bit Descriptions – Link Status Register ........................................................................................ 59
Bit Descriptions – Serial Bus Slave Address Register ....................................................................... 60
Bit Descriptions – Serial Bus Control and Status Register .................................................................. 60
Bit Descriptions – Upstream Port Link PM Latency Register................................................................ 61
Bit Descriptions – Global Chip Control Register .............................................................................. 63
Bit Descriptions – GPIO A Control Register ................................................................................... 65
Bit Descriptions – GPIO B Control Register ................................................................................... 67
Bit Descriptions – GPIO C Control Register................................................................................... 69
Bit Descriptions – GPIO D Control Register................................................................................... 71
Bit Descriptions – GPIO Data Register......................................................................................... 72
Bit Descriptions – Subsystem Access Register ............................................................................... 77
Bit Descriptions – General Control Register................................................................................... 77
Bit Descriptions – Downstream Ports Link PM Latency Register........................................................... 78
Bit Descriptions – Global Switch Control Register............................................................................ 79
Uncorrectable Error Status Register............................................................................................ 80
Uncorrectable Error Mask Register............................................................................................. 81
Uncorrectable Error Severity Register.......................................................................................... 82
Correctable Error Status Register............................................................................................... 83
Correctable Error Mask Register................................................................................................ 84
Advanced Error Capabilities and Control Register ........................................................................... 85
PCI Express Downstream Port Configuration Register Map (Type 1) ..................................................... 86
Extended Configuration Space (Downstream Port) .......................................................................... 87
Bit Descriptions – Command Register ......................................................................................... 88
Bit Descriptions – Status Register .............................................................................................. 88
Bit Descriptions – Class Code and Revision ID Register.................................................................... 89
Bit Descriptions – I/O Base Register ........................................................................................... 92
Bit Descriptions – I/O Limit Register............................................................................................ 92
Bit Descriptions – Secondary Status Register ................................................................................ 93
IBit Descriptions – Memory Base Register .................................................................................... 93
Bit Descriptions – Memory Limit Register...................................................................................... 94
Descriptions – Pre-fetchable Memory Base Register ........................................................................ 94
Bit Descriptions – Pre-fetchable Memory Limit Register..................................................................... 95
Bit Descriptions – Pre-fetchable Base Upper 32 Bits Register.............................................................. 95
Descriptions – Pre-fetchable Limit Upper 32 Bits Register .................................................................. 95
Bit Descriptions – I/O Base Upper 16 Bits Register .......................................................................... 96
List of Tables
9
XIO3130
SLLS693C–MAY 2007–REVISED JUNE 2008
www.ti.com
4-65
4-66
4-67
4-68
4-69
4-70
4-71
4-72
4-73
4-74
4-75
4-76
4-77
4-78
4-79
4-80
4-81
4-82
4-83
4-84
4-85
4-86
4-87
4-88
4-89
4-90
5-1
Bit Descriptions – I/O Limit Upper 16 Bits Register .......................................................................... 96
Bit Descriptions – Bridge Control Register..................................................................................... 97
Bit Descriptions – Power Management Capabilities Register............................................................... 99
Bit Descriptions – Power Management Control/Status Register .......................................................... 100
Bit Descriptions – PM Bridge Support Extension Register................................................................. 101
Bit Descriptions – MSI Message Control Register .......................................................................... 102
Bit Descriptions – MSI Message Address Register ......................................................................... 102
Bit Descriptions – MSI Data Register ......................................................................................... 103
Bit Descriptions – PCI Express Capabilities Register....................................................................... 105
Bit Descriptions – Device Capabilities Register ............................................................................. 106
Bit Descriptions – Device Control Register................................................................................... 106
Bit Descriptions – Device Status Register.................................................................................... 107
Bit Descriptions – Link Capabilities Register................................................................................. 108
Bit Descriptions – Link Control Register...................................................................................... 109
Bit Descriptions – Link Status Register....................................................................................... 110
Bit Descriptions – Slot Capabilities Register................................................................................. 110
Bit Descriptions – Slot Control Register ...................................................................................... 112
Bit Descriptions – Slot Status Register ....................................................................................... 114
Bit Descriptions – General Control Register ................................................................................. 116
Bit Descriptions – General Slot Info Register ................................................................................ 118
Uncorrectable Error Status Register .......................................................................................... 119
Uncorrectable Error Mask Register ........................................................................................... 120
Uncorrectable Error Severity Register ........................................................................................ 121
Correctable Error Status Register ............................................................................................. 122
Correctable Error Mask Register .............................................................................................. 123
Advanced Error Capabilities and Control Register.......................................................................... 124
GPIO Matrix ...................................................................................................................... 125
PCI Hot Plug Sideband Signals................................................................................................ 126
Pins Assigned to GPIO Control Registers.................................................................................... 126
5-2
5-3
10
List of Tables
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1
Features
•
•
•
Wake Event and Beacon Support
•
•
PCI Express Base Specification, Revision 1.1
Support for D1, D2, D3hot, and D3cold
PCI Express Card Electromechanical
Specification, Revision 1.1
Active State Power Management (ASPM) Using
Both L0s and L1
•
•
•
PCI-to-PCI Bridge Architecture Specification,
Revision 1.1
•
•
Low-Power PCI Express Transmitter Mode
PCI Bus Power Management Interface
Specification, Revision 1.2
Integrated AUX Power Switch Drains VAUX
Power Only When Main Power Is Off
PCI Express Fanout Switch With One ×1
Upstream Port and Three x1 Downstream
Ports
•
•
Integrated PCI Hot Plug Support
Integrated REFCLK Buffers for Switch
Downstream Ports
•
Packet Transmission Starts While Reception
Still in Progress (Cut-Through)
•
•
3.3-V Multifunction I/O Pins for PCI Hot Plug
Status and Control or General Purpose I/Os
•
•
256-Byte Maximum Data Payload Size
Peer-to-Peer Support
Optional Serial EEPROM for System-Specific
Configuration Register Initialization
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PCI Express, PCI Hot Plug are trademarks of others.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
XIO3130
SLLS693C–MAY 2007–REVISED JUNE 2008
www.ti.com
2
Introduction
The Texas Instruments XIO3130 switch is an integrated PCI Express fanout switch solution with one
upstream x1 port and three downstream x1 ports. This high-performance integrated solution provides the
latest in PCI Express switch technology including cut-through architecture, integrated reference clock
buffers for downstream ports, integrated main power/VAUX power switch, and downstream port PCI Hot
Plug® support.
The reader is assumed to have prior knowledge of the PCI Express interface and associated terminology
and of the PCI-SIG specifications.
2.1 Description
The Texas Instruments XIO3130 switch is a PCI Express x1 3-port fanout switch. The XIO3130 provides a
single x1 upstream port supporting full 250-MB/s packet throughput in each direction simultaneously.
Three independently configurable x1 downstream ports are provided that also support full 250-MB/s
packet throughput in each direction simultaneously.
A cut-through architecture is implemented to reduce the latency associated with packets moving through
the PCI Express fabric. As soon as the address or routing information is decoded within the header of a
packet entering an ingress port, the packet is directed to the egress port for forwarding. Packet poisoning
using the EDB framing signal is supported in circumstances where packet errors are detected after the
transmission of the egress packet begins.
The downstream ports may be configured to support PCI Hot Plug slot implementations. In this scenario,
the system designer may decide to use the integrated PCI Hot Plug-compliant controller. This feature is
available through the classic PCI configuration space under the PCI Express Capability Structure. When
enabled, the downstream ports provide the PCI Hot Plug standard mechanism to apply and remove power
to the slot or socket.
Power-management features include Active State Power Management, PME mechanisms, the
Beacon/Wake protocol, and all conventional PCI D-states. When ASPM is enabled, each link
automatically saves power when idle using the L0s and L1 states. PME messages are supported along
with the PME_Turn_Off/PME_TO_Ack protocol.
When enabled, the upstream port supports Beacon transmission as well as the WAKE side band signal to
wake the system as the result of a PCI Hot Plug event. Furthermore, the downstream ports may be
configured to detect Beacon from downstream devices and forward this upstream. The switch also
supports the translation and forwarding of WAKE from a downstream device into Beacon on the upstream
port for cabled implementations.
2.2 Related Documents
Trademarks
PCI Express, PCI Hot Plug are trademarks of others.
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2.3 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are
listed below:
1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit
binary field.
2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a
12-bit hexadecimal field.
3. All other numbers that appear in this document that do not have either a b or h following the number
are assumed to be decimal format.
4. If the signal or terminal name has a bar above the name (for example, GRST), then this indicates the
logical NOT function. When asserted, this signal is a logic low, 0, or 0b.
5. Differential signal names end with P, N, +, or – designators. The P or + designators signify the positive
signal associated with the differential pair. The N or – designators signify the negative signal
associated with the differential pair.
6. RSVD indicates that the referenced item is reserved.
7. In Sections 4 through 6, the configuration space for the bridge is defined. For each register bit, the
software-access method is identified in an access column. The legend for this access column includes
the following entries:
–
–
–
–
–
–
r – read access by software
u – updates by the bridge internal hardware
w – write access by software
c – clear an asserted bit with a write-back of 1b by software. Write of zero to the field has no effect
s – the field may be set by a write of one. Write of zero to the field has no effect.
na – not accessible or not applicable
8. The XIO2213 consists of a PCI-Express to PCI translation bridge where the secondary PCI bus is
internally connected to a 1394b OHCI with a 3-port PHY. When describing functionality that is specific
to the PCI-Express to PCI translation bridge, the term bridge is used to reduce text. The term 1394b
OHCI is used to reduce text when describing the 1394b OHCI with 3-port PHY function.
9. LLC is used to refer to the 1394 link layer controller.
2.4 Ordering Information
ORDERING NUMBER
TEMPERATURE
PACKAGE
XIO3130
0°C to 70°C
196-terminal ZHC
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2.5 Terminal Assignments
The XIO3130 is packaged in a 196-ball ZHC MicroStar™ BGA.
Table 2-1. XIO3130 Terminal Assignments
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VSSA
(2)
DN2_
PERn
VSSA
(2)
DN2_
Petn
DN2_
DN2_
14
13
12
11
10
GPIO12
SCL
VDD15
GPIO4
VDD15
GPIO15
VDD15
VDD15
REFCKOn REFCKOp
DN2_
PERp
DN2_
PETp
VSSA
(2)
VSSA
(2)
DN2_
DPSTRP
RSVD
GPIO2
VDD33
GPIO13
RSVD
VDD15
GPIO3
VDD15
SDA
VDD33
VSS
VDD15
VSS
VDD15
GPIO6
VDD15
VDD15
GPIO8
VDD15
GPIO14
GPIO11
VDD15
GPIO7
GPIO16
VDD33
VSSA
(2)
VDDA15
(2)
VSSA
(2)
VDDA15
(2)
VDD33
VSS
GPIO5
VSS
VSSA
(2)
VDDA15
(2)
VDDA15
(2)
VDDA15
(2)
GPIO1
VDD15
VSS
VSSA
(1)
DN1_
DPSTRP
VSSA
(3)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DN1_
REFCK
Op
DN1_
REFCK
On
VSSA
(1)
VDDA15
(1)
VSSA
(3)
VSSA
(3)
DN3_
PERp
DN3_
PERn
9
VSS
VSS
DN1_
PETp
DN1_
PETn
VSSA
(1)
VDDA15
(1)
VDDA15
(3)
VDDA15
(3)
VSSA
(3)
8
7
6
5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD15
VDDA15
(1)
VSSA
(1)
VDDA15
(1)
VDDA15
(3)
VSSA
(3)
DN3_
PETp
DN3_
PETn
VDD15
DN1_
PERp
DN1_
PERn
VDDA15
(3)
VDDA15
(3)
VSSA
(3)
DN3_
REFCKOn
GPIO0
VDD15
VSS
VSS
VSSA
(1)
DN1_
PERST
VSSA
(3)
DN3_
REFCKOp
VSS
VSS
VSS
VDD
COMB
33
VSSA
REF
VDDA15
(0)
VDDA15
(0)
VDDA15
(0)
DN3_
DPSTRP
4
VDD15
VDD33
VDD33
RSVD
RSVD
VDD15
VDD33
VDD15
VDD
COMBIO
VDD15
REF
VSSA
(0)
VDDA15
(0)
3
2
1
VDD15
VDD15
WAKE
GRST
REFR1
VDD15
VDDA33
GPIO18
GPIO17
VDD15
VDD15
GPIO9
VDD15
GPIO10
RSVD
DN2_
PERST
VDD33
REF
UP_
PETn
VDDA15
(0)
UP_
PERn
UP_
REFCKIn
CLKREQ
_UP
REFR0
VDD15
VDD15
VSS
DN3_
PERST
UP_
PERST
VDD
COMB15
VSSD
REF
VAUX33
REF
UP_
PETp
VSSA
(0)
UP_
PERp
VSSA
(0)
UP_
REFCKIp
VDD33
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Table 2-2. XIO3130 Terminals Sorted Alphanumerically
Ball
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
Signal Name
DN3_PERST
DN2_PERST
VDD33
Ball
C13
C14
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
Signal Name
VDD15
VDD15
VSSDREF
REFR0
VDDCOMBIO
RSVD
Ball
F11
F12
F13
F14
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
H01
H02
H03
H04
H05
H06
H06
H07
H08
H09
H10
H11
H12
H13
H14
J01
Signal Name
VSSA(2)
VSSA(2)
DN2_PERp
DN2_PERn
UP_PETp
UP_PETn
VSSA(0)
VDDA15(0)
VSS
Ball
J08
J09
J10
J11
J12
J13
J14
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
L13
L14
M01
M02
M03
M04
M05
Signal Name
VSS
Ball
M06
M07
M08
M09
M10
M11
M12
M13
M14
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
Signal Name
VDDA15(3)
VSSA(3)
VDDA15(3)
VSSA(3)
GPIO8
VSS
VSS
VDD15
VDDA15(2)
VDDA15(2)
VSSA(2)
DN2_REFCKOn
VSSA(0)
VSS
VSSA(1)
DN1_PERp
VDDA15(1)
DN1_PETp
DN1_REFCKOp
VSSA(1)
VDD33
VDD15
VSS
VDD15
VSS
GPIO6
VDDA15(1)
VDDA15(1)
VDDA15(1)
VSS
GPIO15
VSS
VDDA15(0)
VDD15
VDD33
VSS
CLKREQ_UP
GPIO9
GPIO2
VSS
VSS
RSVD
VSS
VSS
VSS
DN3_DPSTRP
VSSA(3)
VSSA(3)
DN3_PETp
VDD15
GPIO12
VDD33
SDA
VSS
VSS
UP_PERST
VDD15
VDDA15(2)
VDDA15(2)
VDD15
VSS
GPIO4
VAUX33REF
VDD33REF
REFR1
VSSAREF
VSS
VSS
VDD15
VSS
VDD33
VSSA(2)
VSSA(0)
VDDA15(0)
VDD15
VSS
DN3_PERp
VDD15
DN1_PERST
DN1_PERn
VDD15
VDD33
VSSA(2)
DN2_REFCKOp
UP_REFCKIp
UP_REFCKIn
GPIO18
VSS
GPIO11
GPIO14
DN1_PETn
DN1_REFCKOn
VDD15
VSS
VDDA15(0)
VSS
VDD15
VSS
VDD15
VSS
VSS
RSVD
GPIO1
VSS
VSS
GPIO10
RSVD
VSS
VSS
VSS
VDD15
GPIO13
VSS
VSS
VDDA15(3)
VDDA15(3)
VDDA15(3)
VSSA(3)
VSS
VDD15
SCL
VSS
VSS
DN3_REFCKOp
DN3_REFCKOn
DN3_PETn
VSSA(3)
DN3_PERn
VSSA(3)
VDD33
VDDCOMB15
GRST
VDD15
VSSA(2)
VDD15
VDD15
VDD15REF
VDDCOMB33
VSS
VSS
VDDA15(2)
VSSA(2)
DN2_PETp
DN2_PETn
UP_PERp
UP_PERn
VDDA33
VDDA15(0)
VSS
WAKE
RSVD
VSS
VDD15
GPIO5
GPIO0
DN2_DPSTRP
VDD15
VSSA(1)
VSSA(1)
VSSA(1)
DN1_DPSTRP
VDD15
J02
GPIO16
VSS
J03
VDD15
GPIO7
VSS
J04
VDD15
VDD15
VSS
J05
GPIO17
VDD33
VSS
J06
VSS
GPIO3
VSS
J07
VSS
VSS
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Table 2-3. XIO3130 Signal Names Sorted Alphabetically
Signal Name
CLKREQ_UP
Ball
Signal Name
GPIO5
Ball
N02
L12
DN1_DPSTRP
DN1_PERn
C10
GPIO6
M13
B06
GPIO7
P13
DN1_PERp
A06
GPIO8
M10
DN1_PERST
DN1_PETn
B05
GPIO9
N03
B08
GRST
C02
DN1_PETp
A08 Suggested Program Value
REFR0
D02
DN1_REFCKOn
DN1_REFCKOp
DN2_DPSTRP
DN2_PERn
B09
A09
L13
F14
F13
A02
H14
H13
J14
K14
N04
P09
REFR1
E03
RSVD
A13, B12, C04, D04, P01
SCL
B14
D13
J02
J01
B01
G02
G01
L02
L01
E01
SDA
DN2_PERp
UP_PERn
UP_PERp
UP_PERST
UP_PETn
UP_PETp
UP_REFCKIn
UP_REFCKIp
VAUX33REF
DN2_PERST
DN2_PETn
DN2_PETp
DN2_REFCKOn
DN2_REFCKOp
DN3_DPSTRP
DN3_PERn
A04, B02, B03, B07, B10, C05, C11, C13,
C14, E13, F01, F02, G13, H03, K04, L14,
M01, M02, M11, M12, N08, N10, N13, N14,
P03, P04, P14
DN3_PERp
N09
VDD15
DN3_PERST
DN3_PETn
DN3_PETp
DN3_REFCKOn
DN3_REFCKOp
GPIO0
A01
P07
N07
P06
P05
C06
B11
P02
N11
A14
B13
VDDA15(0)
VDDA15(1)
VDDA15(2)
VDDA15(3)
VDD15REF
VDD33
G04, H02, H04, J04, K03
A07, D07, D08, D09
G11, G12, H11, J11, J12
L06, L07, L08, M06, M08
F03
A03, A11, B04, D12, K12, M04, N01, P11
GPIO1
VDD33REF
VDDA33
E02
J03
C01
F04
D03
GPIO10
GPIO11
VDDCOMB15
VDDCOMB33
VDDCOMBIO
GPIO12
GPIO13
D05, D06, D10, D11, E05, E06, E07, E08,
E09, E10, E11, E12, F05, F06, F07, F08,
F09, F10, G05, G06, G07, G08, G09, G10,
H05, H06, H07, H08, H09, H10, J05, J06,
J07, J08, J09, J10, K02, K05, K06, K07,
K08, K09, K10, K11, L04, L05, L10, L11,
M05
GPIO14
N12
VSS
GPIO15
GPIO16
GPIO17
GPIO18
GPIO2
M14
P12
M03
L03
A12
C12
D14
VSSA(0)
VSSA(1)
VSSA(2)
VSSA(3)
VSSAREF
VSSDREF
WAKE
G03, H01, K01
A05, A10, C07, C08, C09
E14, F11, F12, G14, H12, J13, K13
L09, M07, M09, N05, N06, P08, P10
E04
D01
C03
GPIO3
GPIO4
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2.6 Terminal Descriptions
Table 2-4. Power Supply Terminals
Signal
Ball
I/O Type
External parts
Description
G04, H02, H04, J04,
K03
1.5-V analog power terminals for PCI-Express upstream port
0
VDDA15(0)
PWR
Filter
1.5-V analog power terminals for PCI-Express downstream
port 1
VDDA15(1)
VDDA15(2)
VDDA15(3)
A07, D07, D08, D09
G11, G12, H11, J11, J12
L06, L07, L08, M06, M08
PWR
PWR
PWR
Filter
Filter
Filter
1.5-V analog power terminals for PCI-Express downstream
port 2
1.5-V analog power terminals for PCI-Express downstream
port 3
A04, B02, B03, B07,
B10, C05, C11, C13,
C14, E13, F01, F02,
G13, H03, K04, L14,
M01, M02, M11, M12,
N08, N10, N13, N14,
P03, P04, P14
Bypass
capacitors
VDD15
PWR
1.5-V digital core power terminals
A03, A11, B04, D12,
K12, M04, N01, P11
Bypass
capacitors
VDD33
PWR
PWR
PWR
3.3-V digital I/O power terminals
3.3-V analog power terminal
VDDA33
J03
Filter
Bypass
capacitors
VAUX33REF
E01
3.3-V digital VAUX power terminal
VDD15REF
VDD33REF
F03
E02
PWR
PWR
Filter
Filter
1.5-V PCI-Express reference power terminal
3.3-V PCI-Express reference power terminal
Table 2-5. Combined Power Terminals
Signal
Ball
I/O Type
External Parts
Description
Internally combined 3.3-V main and VAUX power output for external
bypass capacitor filtering. Supplies all internal 3.3-V input and output
circuitry powered during D3 cold. Caution: Do not use this terminal to
supply external power to other devices.
VDDCOMBIO
D03
Passive
Bypass capacitors
Bypass capacitors
Bypass capacitors
Internally combined 3.3-V main and VAUX power output for external
bypass capacitor filtering. Supplies all internal 3.3-V circuitry powered
during D3 cold. Caution: Do not use this terminal to supply external
power to other devices.
VDDCOMB33
VDDCOMB15
F04
C01
Passive
Passive
Internally combined 1.5-V main and VAUX power output for external
bypass capacitor filtering. Supplies all internal 1.5-V circuitry powered
during D3 cold. Caution: Do not use this terminal to supply external
power to other devices.
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Table 2-6. Ground Terminals
Signal
Ball
I/O Type
Description
D05, D06, D10, D11, E05,
E06, E07, E08, E09, E10,
E11, E12, F05, F06, F07,
F08, F09, F10, G05, G06,
G07, G08, G09, G10,
H05, H06, H07, H08, H09,
H10, J05, J06, J07, J08,
J09, J10, K02, K05, K06,
K07, K08, K09, K10, K11,
L04, L05, L10, L11, M05
VSS
GND
Digital ground terminals
VSSA(0)
VSSA(1)
G03, H01, K01
GND
GND
Analog ground terminals for upstream Port 0
Analog ground terminals for downstream Port 1
A05, A10, C07, C08, C09
E14, F11, F12, G14, H12,
J13, K13
VSSA(2)
VSSA(3)
GND
GND
Analog ground terminals for downstream Port 2
Analog ground terminals for downstream Port 3
L09, M07, M09, N05, N06,
P08, P10
VSSAREF
VSSDREF
E04
D01
GND
GND
1.5-V PCI-Express analog reference ground terminal
1.5-V PCI-Express digital reference ground terminal
Table 2-7. PCI Express Reference Clock Terminals
Signal
Ball
I/O Type
External Parts
Description
Capacitor from
REFCKIn to VSS for
single-ended mode
UP_REFCKIp
UP_REFCKIn
L01
L02
Reference clock inputs. REFCKIp and REFCKIn comprise the
HS DIFF IN
differential input pair for the 100-MHz system reference clock.
100 MHz differential reference clock outputs for downstream port 1
100 MHz differential reference clock outputs for downstream port 2
100 MHz differential reference clock outputs for downstream port 3
DN1_REFCKOp
DN1_REFCKOn
A09
B09
HS DIFF OUT
HS DIFF OUT
HS DIFF OUT
DN2_REFCKOp
DN2_REFCKOn
K14
J14
DN3_REFCKOp
DN3_REFCKOn
P05
P06
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Table 2-8. PCI Express Terminals
Signal
Ball
I/O Type
External Parts
Description
UP_PETp
UP_PETn
G01
G02
HS DIFF
OUT
Series capacitors High-speed differential transmit pair for upstream port 0
Series capacitors High-speed differential transmit pair for downstream port 1
Series capacitors High-speed differential transmit pair for downstream port 2
Series capacitors High-speed differential transmit pair for downstream port 3
High-speed differential receiver pair for upstream port 0
DN1_PETp
DN1_PETn
A08
B08
HS DIFF
OUT
DN2_PETp
DN2_PETn
H13
H14
HS DIFF
OUT
DN3_PETp
DN3_PETn
N07
P07
HS DIFF
OUT
UP_PERp
UP_PERn
J01
J02
HS DIFF IN
HS DIFF IN
HS DIFF IN
HS DIFF IN
Passive
DN1_PERp
DN1_PERn
A06
B06
High-speed differential receiver pair for downstream port 1
DN2_PERp
DN2_PERn
F13
F14
High-speed differential receiver pair for downstream port 2
DN3_PERp
DN3_PERn
N09
P09
High-speed differential receiver pair for downstream port 3
REFR0
REFR1
D02
E03
External bias
resistor
External reference resistor terminals for setting TX driver current. An
external resistor is connected between these terminals.
PCI-Express reset input. When logic high, the PERST signal
identifies that the system power is stable. When logic low, the
PERST signal generates an internal power-on reset.
System-side
pullup resistor
UP_PERST
B01
LV CMOS IN
Note: The UP_PERST input buffer has hysteresis.
DN1_PERST
DN2_PERST
DN3_PERST
B05
A02
A01
LV CMOS O Pulldown resistor PCI-Express reset output for downstream port 1.
LV CMOS O Pulldown resistor PCI-Express reset output for downstream port 2.
LV CMOS O Pulldown resistor PCI-Express reset output for downstream port 3.
WAKE is an active low signal that is driven low to reactivate the
System-side
pullup resistor
PCI-Express link hierarchy’s main power rails and reference clocks.
WAKE
C03
LV CMOS I/O
Note: Since WAKE is an open-drain output buffer, a system-side
pullup resistor is required.
Table 2-9. PCI Hot Plug Strapping Terminals
Signal
Ball
I/O Type
External Parts
Description
Downstream Port 1 Strap. This pin is pulled high at the de-assertion of
reset. GPIO0, GPIO1, and GPIO2 are used as PCI Hot Plug terminals
for downstream port 1 and are no longer available for use as GPIOs.
The three terminals become PRESENT, PWR_ON, and PWR_GOOD
respectively. These GPIOs are available for normal use if this terminal
is pulled low at the de-assertion of reset.
DN1_DPSTR
P
Pullup or pulldown
resistor
C10
LV CMOS IN
LV CMOS IN
LV CMOS IN
Downstream Port 2 Strap. This pin is pulled high at the de-assertion of
reset. GPIO4, GPIO5, and GPIO6 are used as PCI Hot Plug terminals
for downstream port 2 and are no longer available for use as GPIOs.
The three terminals become PRESENT, PWR_ON, and PWR_GOOD
respectively. These GPIOs are available for normal use if this terminal
is pulled low at the de-assertion of reset.
DN2_DPSTR
P
Pullup or pulldown
resistor
L13
N04
Downstream Port 3 Strap. This pin is pulled high at the de-assertion of
reset. GPIO8, GPIO9, and GPIO10 are used as PCI Hot Plug terminals
for downstream port 3 and are no longer available for use as GPIOs.
The three terminals become PRESENT, PWR_ON, and PWR_GOOD
respectively. These GPIOs are available for normal use if this terminal
is pulled low at the de-assertion of reset.
DN3_DPSTR
P
Pullup or pulldown
resistor
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Table 2-10. GPIO Terminals
Signal
Ball
I/O Type
External Parts
Description
GPIO 0. If the DN1_DPSTRP pin is pulled high at the de-assertion of
reset, this pin functions as the PRSNT hotplug pin for downstream
port 1. Otherwise this pin’s function is programmed with the GPIO A
Control register.
GPIO0
C06
LV CMOS I/O
GPIO 1. If the DN1_DPSTRP pin is pulled high at the de-assertion of
reset, this pin functions as the POWERON hotplug pin for
downstream port 1. Otherwise this pin’s function is programmed with
the GPIO A Control register.
GPIO1
B11
LV CMOS I/O
GPIO 2. If the DN1_DPSTRP pin is pulled high at the de-assertion of
reset, this pin functions as the PWRGD hotplug pin for downstream
port 1. Otherwise this pin’s function is programmed with the GPIO A
Control register
GPIO2
GPIO3
GPIO4
A12
C12
D14
LV CMOS I/O
LV CMOS I/O
LV CMOS I/O
GPIO 3. This pin’s function is programmed with the GPIO A Control
register.
GPIO 4. If the DN2_DPSTRP pin is pulled high at the de-assertion of
reset, this pin functions as the PRSNT hotplug pin for downstream
port 2. Otherwise this pin’s function is programmed with the GPIO A
Control register.
GPIO 5. If the DN2_DPSTRP pin is pulled high at the de-assertion of
reset, this pin functions as the POWERON hotplug pin for
downstream port 2. Otherwise this pin’s function is programmed with
the GPIO A Control register.
GPIO5
L12
LV CMOS I/O
GPIO 6. If the DN2_DPSTRP pin is pulled high at the de-assertion of
reset, this pin functions as the PWRGD hotplug pin for downstream
port 2. Otherwise this pin’s function is programmed with the GPIO A
Control register.
GPIO6
GPIO7
GPIO8
M13
P13
M10
LV CMOS I/O
LV CMOS I/O
LV CMOS I/O
GPIO 7. This pin’s function is programmed with the GPIO A Control
register.
GPIO 8. If the DN3_DPSTRP pin is pulled high at the de-assertion of
reset, this pin functions as the PRSNT hotplug pin for downstream
port 3. Otherwise this pin’s function is programmed with the GPIO B
Control register.
GPIO 9. If the DN3_DPSTRP pin is pulled high at the de-assertion of
reset, this pin functions as the POWERON hotplug pin for
downstream port 3. Otherwise this pin’s function is programmed with
the GPIO B Control register.
GPIO9
N03
P02
LV CMOS I/O
LV CMOS I/O
GPIO 10. If the DN3_DPSTRP pin is pulled high at the de-assertion
of reset, this pin functions as the PWRGD hotplug pin for
downstream port 3. Otherwise this pin’s function is programmed with
the GPIO B Control register.
GPIO10
GPIO 11. This pin’s function is programmed with the GPIO B Control
register.
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
N11
A14
B13
N12
M14
P12
M03
L03
LV CMOS I/O
LV CMOS I/O
LV CMOS I/O
LV CMOS I/O
LV CMOS I/O
LV CMOS I/O
LV CMOS I/O
LV CMOS I/O
GPIO 12. This pin’s function is programmed with the GPIO B Control
register.
GPIO 13. This pin’s function is programmed with the GPIO B Control
register.
GPIO 14. This pin’s function is programmed with the GPIO B Control
register.
GPIO 15. This pin’s function is programmed with the GPIO B Control
register.
GPIO16. This pin’s function is programmed with the GPIO C Control
register.
GPIO 17. This pin’s function is programmed with the GPIO C Control
register.
GPIO 18. This pin’s function is programmed with the GPIO C Control
register.
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Table 2-11. Miscellaneous Terminals
Signal
Ball
I/O Type
External Parts
Description
C02
LV CMOS IN
Global power-on reset input. Note: a pullup to Vaux (if supported) or
VDD3.3 (if not) is required unless this terminal is always driven by
the upstream device.
GRST
See description
SDA
SCL
D13
B14
LV CMOS I/O
LV CMOS O
Serial Data. This pin is the serial data pin for the EEPROM interface.
Serial Clock. This pin is the serial clock pin for the EEPROM
interface.
N02
LV CMOS O
Upstream Clock Request. When asserted low, requests upstream
device restart clock in cases where upstream clock may be removed
in L1
CLKREQ_UP
RSVD
RSVD
RSVD
A13, B12,
C04, P01
D04
Reserved. These terminals must tied to VDD15.
Reserved. This terminal must be tied to GND.
See description
Reserved. Pullup to Vaux (if supported) or VDD3.3 (if not)
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3
Description
Figure 3-1 is the block diagram of the XIO3130.
Clock
Distribution/
Reset Logic
PCI
Express
X1 Phy
GPIO
Port 0
(Up)
Logic
PCI Hot
Plug
Virtual
PCI to
PCI
EEPROM
Bridge
Virtual
PCI to
Virtual
PCI to
Virtual
PCI to
PCI Bridge
Bridge
PCI Bridge
Bridge
PCI Bridge
Bridge
Port 1
(Down)
Logic
Port 3
(down)
logic
Port 2
(Down)
Logic
PCI
Express x1
Phy
PCI
Express x1
Phy
PCI
Express x1
Phy
Figure 3-1. Block Diagram
3.1 Power-Up/Power-Down Sequencing
The following sections describe the procedures to power up and power down the XIO3130 switch.
3.1.1 Power-Up Sequence
1. Assert PERST to the device.
2. Apply 1.5-V and 3.3-V voltages in any order with any time relationship and with any ramp rate.
3. Apply a stable PCI Express reference clock.
To meet PCI Express specification requirements, PERST cannot be de-asserted until the following two
delay requirements are satisfied:
•
Wait a minimum of 100 µs after applying a stable PCI Express reference clock. The 100-µs limit
satisfies the requirement for stable device clocks by the de-assertion of PERST.
•
Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable
power by the de-assertion of PERST.
See Figure 3-2, Power-Up Sequence Diagram.
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Figure 3-2. Power-Up Sequence Diagram
3.1.2 Power-Down Sequence
•
•
•
Assert PERST to the device.
Remove the reference clock.
Remove 3.3-V and 1.5-V voltages.
See the power-down sequence diagram in Figure 3-3. If the VAUX33REF terminal is to remain powered
after a system shutdown, the switch power-down sequence is exactly the same as shown in Figure 3-3.
Figure 3-3. Power-Down Sequence Diagram
3.2 Express Interface
3.2.1 External Reference Clock
The Texas Instruments XIO3130 switch requires a differential 100 MHz common clock reference. The
clock reference must meet all PCI Express electrical specification requirements for frequency tolerance,
spread spectrum clocking, and signal electrical characteristics.
3.2.2 Clock Generator
The clock generator is responsible for generating all internal and external clocks from the PCI Express
reference clock. This includes the PHY transmitter serial link clock, the three downstream reference clock
outputs, the 60-kHz serial bus interface clock, and all internal clock domains.
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3.2.3 Beacon
The XIO3130 supports the PCI Express in-band beacon feature. Beacon is driven on the PCI Express link
by the XIO3130 to request the re-application of main power when in the L2 link state. Once beacon is
activated, the XIO3130 continues to send the beacon signal until main power is restored as indicated by
PERST going inactive. At this time, the beacon signal is deactivated.
3.2.4 WAKE
The XIO3130 supports the PCI Express sideband WAKE feature. WAKE is an active-low signal driven by
the XIO3130 to request the re-application of main power when in the L2 link state. Since WAKE is an
open-collector output, a system-side pullup resistor is required to prevent the signal from floating. If WAKE
to Beacon translation is enabled (see section 3.2.60), the XIO3130 detects when WAKE is asserted and
transmits beacon to alert the system. This enables support for devices that use the WAKE protocol in a
system that does not support it.
3.2.5 Initial Flow Control Credits
The XIO3130 flow control credits are initialized using the rules defined in the PCI Express Base
Specification. Table 3-1 identifies the initial flow control credit advertisement for the XIO3130. The initial
advertisement is exactly the same for both upstream and downstream ports.
Table 3-1. Initial Flow Control Credit Advertisements
Initial Advertisement
Credit Type
Hex
10
80
10
10
10
80
Decimal
16
Posted Request Headers (PH)
Posted Request Data (PD)
Non-Posted Header (NPH)
Non-Posted Data (NPD)
128
16
16
Completion Header (CPLH)
Completion Data (CPLD)
16
128
3.2.6 PCI Express Message Transactions
PCI Express messages are initiated by, received by and passed through the XIO3130. Table 3-2 outlines
message support within the switch.
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Table 3-2. Messages Supported by the XIO3130
Message
Supported
Yes
XIO3130 Action
Assert_INTx
Passed through upstream
Passed through upstream
Received and processed
Passed through upstream
Deassert_INTx
Yes
PM_Active_State_Nak
Yes
PM_PME
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Downstream PCI Hot Plug Event: Initiated upstream
Received and processed
PME_Turn_Off
PME_TO_Ack
ERR_COR
Passed through downstream
Downstream port: Received and processed
Downstream ports: Initiated upstream
Passed through upstream
Initiated upstream
Passed through upstream
Initiated upstream
ERR_NONFATAL
ERR_FATAL
Unlock
Passed through upstream
Initiated upstream
Received and processed
Passed through downstream
Upstream port: Received and processed
Downstream port: Initiated downstream
Set_Slot_Power_Limit
Yes
No
Advanced Switching Messages
Vendor Defined Type 0
Discarded
Upstream port: Unsupported request
Passed through downstream
Yes
Upstream port: Discarded
Passed through downstream
Vendor Defined Type 1
Yes
All supported message transactions are processed according to the PCI Express Base Specification.
3.3 GPIO Terminals
Up to 19 general-purpose input/output (GPIO) terminals are provided for system customization. These
GPIO terminals are 3.3-V tolerant.
The exact number of GPIO terminals available varies based on the implementation of various supported
functions that share GPIO terminals. When any of the shared functions are enabled, the associated GPIO
terminal is disabled. When pulled high, the DPSTRP terminals cause some GPIO terminals to be mapped
to PCI Hot Plug functions for specific ports. Additional information can be found in the DPSTRP pin
descriptions and in Chapter 4.
All GPIO terminals are individually configurable as either inputs or outputs by writing the corresponding
bits in the GPIOA, GPIOB, GPIOC, or GPIOD Control Registers. The GPIO data register is used to
monitor GPIO terminals defined as inputs or to set the state of GPIO terminals defined as outputs. For
more information on GPIO terminals, see sections Section 4.2.61 through Section 4.2.65.
3.4 Serial EEPROM
The XIO3130 provides a two-wire serial-bus interface to load subsystem identification information and
specific register defaults from an external EEPROM. This interface supports slow, fast, and high-speed
EEPROM speed options.
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3.4.1 Serial Bus Interface Implementation
To enable the serial bus interface, a pullup resistor must be implemented on the SDA signal. At the rising
edge of PERST or GRST, whichever occurs last, the SDA terminal is checked for a pullup resistor. If one
is detected, bit 3 (SBDETECT) in the serial bus control and status register (see Table 4-32) is set.
Software may disable the serial bus interface at any time by writing a zero to the SBDETECT bit. If no
external EEPROM is required, the serial bus interface is permanently disabled by attaching a pulldown
resistor to the SDA signal.
The XIO3130 implements a two-terminal serial interface with one clock signal (SCL) and one data signal
(SDA). The SCL signal is a unidirectional output from the XIO3130 and the SDA signal is bidirectional.
Both are open-drain signals and require pullup resistors. The XIO3130 is a bus master device and drives
SCL at approximately 60 kHz during data transfers and places SCL in a high-impedance state during bus
idle states. The serial EEPROM is a bus slave device and must acknowledge a slave address equal to
1010_000X binary. Figure 3-4 illustrates a sample application implementing the two-wire serial bus.
VDD33
SERIAL
XIO3130
EEPROM
SCL
SDA
SCL A2
A1
SDA A0
Figure 3-4. Serial EEPROM Applications
3.4.2 Serial Bus Interface Protocol
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a
start condition, which is signaled when the SDA line transitions to a low state while SCL is in the high
state, as illustrated in Figure 3-5. The end of a requested data transfer is indicated by a stop condition,
which is signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3-5.
Data on SDA must remain stable during the high state of the SCL signal because changes on the SDA
signal during the high state of SCL are interpreted as control signals (i.e., a start or a stop condition).
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Figure 3-5. Serial-Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. During a data transfer operation, an unlimited number of bytes
are transmitted. However, each byte must be followed by an acknowledge bit to continue the data transfer
operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA signal low, so that
it remains low during the high state of the SCL signal. Figure 3-6 illustrates the acknowledge protocol.
Figure 3-6. Serial-Bus Protocol Acknowledge
The XIO3130 performs three basic serial bus operations: single-byte reads, single-byte writes, and
multiple-byte reads. The single-byte operations occur under software control. The multiple-byte read
operations are performed by the serial EEPROM initialization circuitry immediately after a PCI Express
Reset. For details on how the XIO3130 automatically loads the subsystem identification and other register
defaults from the serial-bus EEPROM, see Section 3.4.3, Serial Bus EEPROM Application.
Figure 3-7 illustrates a single-byte write. The XIO3130 issues a start condition and sends the 7-bit slave
device address and the R/W command bit equal to zero. A zero in the R/W command bit indicates that the
data transfer is a write. The slave device acknowledges that it recognizes the slave address. If the
XIO3130 receives no acknowledgment, the SB_ERR status bit is set in the serial-bus control and status
register (PCI offset B3h; see Table 4-32). Next, the XIO3130 sends the EEPROM word address, and
another slave acknowledgment is expected. Then the XIO3130 delivers the data byte (MSB first) and
expects a final acknowledgment before issuing the stop condition.
Figure 3-7. Serial-Bus Protocol – Byte Write
Figure 3-8 illustrates a single-byte read. The XIO3130 issues a start condition and sends the 7-bit slave
device address and the R/W command bit equal to zero (write). The slave device acknowledges that it
recognizes the slave address. Next, the XIO3130 sends the EEPROM word address, and another slave
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acknowledgment is expected. Then, the XIO3130 issues a restart condition followed by the 7-bit slave
address and the R/W command bit equal to one (read). Once again, the slave device responds with
acknowledge. Next, the slave device sends the 8-bit data byte, MS bit first. Since this is a one-byte read,
the XIO3130 responds with no acknowledge (logic high), indicating the last data byte. Finally, the XIO3130
issues a stop condition.
Slave Address
Word Address
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
Start
R/W
Slave Address
b6 b5 b4 b3 b2 b1 b0
Data Byte
S
1
A
b7 b6 b5 b4 b3 b2 b1 b0
M
P
Restart
R/W
M = Master Acknowledgement
A = Slave Acknowledgement
S/P = Start/Stop Condition
Figure 3-8. Serial-Bus Protocol – Byte Read
Figure 3-9 illustrates the serial interface protocol during a multiple-byte serial EEPROM download. The
serial bus protocol starts exactly the same way as a one-byte read. The only difference is that multiple
data bytes are transferred. The number of transferred data bytes is controlled by the XIO3130 master.
After each data byte, if more data bytes are requested, the XIO3130 master issues acknowledge (logic
low). The transfer ends after an XIO3130 master no acknowledge (logic high), followed by a stop
condition.
Figure 3-9. Serial-Bus Protocol – Multiple-Byte Read
The PROT_SEL bit (bit 7) in the Serial Bus Control and Status register changes the serial bus protocol.
Each of the three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low).
When this control bit is asserted, the word address and corresponding acknowledge are removed from the
serial bus protocol. This feature allows the system designer a second serial bus protocol option when
selecting external EEPROM devices.
3.4.3 Serial Bus EEPROM Application
The registers and corresponding bits that are loaded through the EEPROM are provided in Table 3-3.
Note the following:
•
•
•
EEPROM bytes 00h through 1Dh affect the general control options for the XIO3130.
EEPROM bytes 1Eh through 27h affect the operation of the upstream port (port 0).
Bytes 00h through 27h are loaded into the configuration registers for the upstream virtual bridge or port
0 (see Figure 4-1).
•
EEPROM bytes 28h through 35h correspond to and are loaded into the configuration space for the first
downstream virtual bridge or port 1 (see Figure 4-1).
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•
EEPROM bytes 36h through 43h correspond to and are loaded into the configuration space for the
second downstream virtual bridge or port 2 (see Figure 4-1).
•
EEPROM bytes 44h through 51h correspond to and are loaded into the configuration space for the
third downstream virtual bridge or port 3 (see Figure 4-1).
Table 3-3. EEPROM Register Loading Map
EEPROM Byte Address
(hex)
Suggested Programmed CONFIG Register Address
Register Description
Value (hex)
(hex)
0
4C
0
NA
Global Switch/Upstream Port Function Indicator(1)
TI Proprietary register(1)
1
NA
2
24
0
0B4
0B5
0B8
0B9
0BA
0BB
0BC
0BD
0BE
0BF
0C0
0C1
0C2
0C3
0C4
0C5
0C6
0C7
0C8
0CC
0CD
0D0
0D1
0D2
0D3
0DC
0DE
0DF
NA
Upstream Port Link PM Latency register
Upstream Port Link PM Latency register
Global Chip Control register
Global Chip Control register
Global Chip Control register
Global Chip Control register
GPIOA register
3
4
0
5
0
6
0
7
0
8
0
9
0
GPIOA register
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
0
GPIOB register
0
GPIOB register
0
GPIOC register
0
GPIOC register
0
GPIOD register
0
GPIOD register
0
GPIO Data register
0
GPIO Data register
0
GPIO Data register
0
GPIO Data register
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
01
0
0
0
0
14
32
2
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
0
0
0
Global Switch/Upstream Port 0 Function Indicator
Not used
0
NA
XX
XX
XX
XX
0
0E0
0E1
0E2
0E3
0E4
0E8
0E9
0EA
NA
Subsystem Access Vendor ID register
Subsystem Access Vendor ID register
Subsystem Access Subsys ID register
Subsystem Access Subsys ID register
General Control register
24
3F
4
Downstream Port Link PM Latency register
Downstream Port Link PM Latency register
Global Switch Control register
Downstream Port 1 Function Indicator
1
(1) Required program value
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Table 3-3. EEPROM Register Loading Map (continued)
EEPROM Byte Address
(hex)
Suggested Programmed CONFIG Register Address
Register Description
Value (hex)
(hex)
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
0
01
0
NA
Not used
0C8
0CC
0CD
0D0
0D1
0D2
0D3
0D4
0D5
0EC
0EE
0EF
NA
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
General Control register
General Control register
L0s Timeout register
0
0
0
14
32
10
60
1A
0
General Slot Info register
General Slot Info register
Downstream Port 2 Function Indicator
Not used
0
2
0
NA
01
0
0C8
0CC
0CD
0D0
0D1
0D2
0D3
0D4
0D5
0EC
0EE
0EF
NA
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
General Control register
General Control register
L0s Timeout register
0
0
0
14
32
10
60
1A
0
General Slot Info register
General Slot Info register
Downstream Port 3 Function Indicator
Not used
0
2
0
NA
01
0
0C8
0CC
0CD
0D0
0D1
0D2
0D3
0D4
0D5
0EC
0EE
0EF
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
TI Proprietary register(1)
General Control register
General Control register
L0s Timeout register
0
0
0
14
32
10
60
1A
0
General Slot Info register
General Slot Info register
0
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This download table must be explicitly followed for the XIO3130 to correctly load initialization values from
a serial EEPROM. All byte locations must be considered when programming the EEPROM.
The XIO3130 addresses the serial EEPROM using a default slave address of 1010_000X binary. For an
EEPROM download operation that occurs immediately after PERST, this address is fixed. The serial
EEPROM in the sample application circuit (Figure 3-4) assumes the 1010b high-address nibble. The lower
three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs
tied to VSS to match the least-significant three address bits.
During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is
asserted. After the download is finished, bit 4 is negated. At that time, bit 0 (ROM_ERR) in the serial-bus
control and status register may be monitored to verify a successful download.
3.4.4 Accessing Serial Bus Devices Through Software
The XIO3130 provides a programming mechanism to control serial bus devices through system software.
The programming is accomplished through a doubleword of PCI configuration space at offset B0h.
Table 3-4 lists the registers used to program a serial-bus device through software.
Table 3-4. Register for Programming Serial-Bus Devices
PCI Offset
Register Name
Description
This register contains the data byte to send on write commands or
the received data byte on read commands.
B0h
Serial-bus data
The content of this register is sent as the word address on byte
writes or reads. This register is not used in the quick command
protocol.
B1h
B2h
B3h
Serial-bus word address
Serial-bus slave address
Control and Status
Write transactions to this register initiate a serial-bus transaction.
The slave device address and the R/W command selector are
programmed through this register.
Serial interface enable, busy, and error status are communicated
through this register. In addition, the protocol-select bit and serial
bus test bit are programmed through this register.
To access the serial EEPROM through the software interface, the software performs five steps:
1. Reads the Control and Status Byte to verify that the EEPROM interface is enabled (SBDETECT
asserted) and not busy (REQBUSY and ROMBUSY negated).
2. Loads the Serial Bus word address. If the access is a write, the data byte is also loaded.
3. Writes the Serial Bus slave address and read/write command selector byte.
4. Monitors REQBUSY until this bit is negated.
5. Checks SB_ERR to verify that the serial bus operation completed without error. If the operation is a
read, after REQBUSY is negated, the serial bus data byte is valid.
3.5 Switch Reset Features
Four XIO3130 reset options are available:
•
•
•
•
Internally-generated power-on reset
A global reset generated by asserting GRST input terminal
A PCI Express reset generated by asserting PERST input terminal
Software-initiated resets that are controlled by sending a PCI Express training control hot reset
Table 3-5 identifies these reset sources and describes how the XIO3130 responds to each reset.
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Table 3-5. Switch Reset Options
Reset Option
XIO3130 Feature
Reset Response
When the internal power-on reset is asserted, all
internal reset and monitors the VDDCOMB15 (N01) control registers, state machines, sticky register bits,
Internally-generated power-on During a power-on cycle, the XIO3130 asserts an
reset
terminal. When this terminal reaches 90% of the
nominal input voltage specification, power is
considered stable. After stable power, the XIO3130
monitors the PCI Express reference clock
(REFCLKI) and waits 10 µs after active clocks are
detected. Then, internal power-on reset is
de-asserted.
and power management state machines are
initialized to their default state.
Global reset input GRST (C02) When GRST is asserted low, an internal power-on
reset occurs. This reset is asynchronous and
When GRST is asserted low, all control registers,
state machines, sticky register bits, and power
functions during both normal power states and VAUX management state machines are initialized to their
power states.
default state. When the rising edge of GRST occurs,
the switch samples the state of all static control
inputs and latches the information internally. If an
external serial EEPROM is detected, then a
download cycle is initiated. Also, the process to
configure and initialize the PCI Express link is
started. The switch starts link training within 80 ms
after PERST or GRST is de-asserted.
PCI Express reset input
PERST (C01)
When PERST is asserted low, all control register
bits that are not sticky are reset. Also, all state
machines that are not associated with sticky
functionality or VAUX power management are reset.
When the rising edge of PERST occurs, the switch
samples the state of all static control inputs and
latches the information internally. If an external
serial EEPROM is detected, then a download cycle
is initiated. Also, the process to configure and
initialize the PCI Express link is started. The switch
starts link training within 80 ms after PERST or
GRST is de-asserted.
This XIO3130 input terminal is used by an upstream
PCI Express device to generate a PCI Express reset
and to signal a system power good condition.
When PERST is asserted low, all control register
bits that are not sticky are reset. Also, all state
machines that are not associated with sticky
functionality or VAUX power management are reset.
When the rising edge of PERST occurs, the switch
samples the state of all static control inputs and
latches the information internally. If an external
serial EEPROM is detected, then a download cycle
is initiated. Also, the process to configure and
initialize the PCI Express link is started. The switch
starts link training within 80 ms after PERST or
GRST is de-asserted.
Note: The system must assert PERST before power
is removed, before REFCLKI is removed, or before
REFCLKI becomes unstable.
PCI Express training control
hot reset
The XIO3130 responds to a training control hot
reset received on the PCI Express interface. After a register bits and state machines are reset. All
training control hot reset, the PCI Express interface remaining bits exclude sticky bits and EEPROM
In the DL_DOWN state, all remaining configuration
enters the DL_DOWN state.
loadable bits. All remaining state machines exclude
sticky functionality, EEPROM functionality, and VAUX
power management.
32
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4
XIO3130 Configuration Register Space
This chapter specifies the configuration registers that are used to enumerate the XIO3130 device within a
PC system.
An overview of the configuration register space is provided along with a detailed description of the register
bits associated with the upstream and downstream ports of the XIO3130.
4.1 PCI Configuration Register Space Overview
Each PCI Express port contains a set of PCI configuration registers. One of the upstream port registers,
the Global Chip Control register, is used to control functions across the entire XIO3130.
For downstream ports, only one register set is specified, but this register set is duplicated for each
downstream port. Figure 4-1 illustrates the enumeration topology.
The XIO3130 must appear as a hierarchy of PCI-to-PCI bridges in the manner outlined by the PCI
Express base specification.
NOTE
This numbering scheme is typical but not ensured. Bus numbers are assigned within the
Type 01h configuration header during the initial enumeration of the PCI bus by the system
at power-up.
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Port# 0
Device# 0
Bus# N**
000h
Upstream Port
Header Type 01h
03Fh
040h
PCI Capability
Structures /
Proprietary
Register Space
0FFh
100h
Extended
Configuration
Space / PCI Express
Capability Structures
FFFh
Virtual Internal PCI Bus (Bus# N+1**)
Device# 0
Device# 1
Device# 2
000h
000h
000h
Downstream Port
Downstream Port
Downstream Port
Header Type 01h
Header Type 01h
Header Type 01h
03Fh
040h
03Fh
040h
03Fh
040h
PCI Capability
Structures /
PCI Capability
Structures /
PCI Capability
Structures /
Proprietary
Proprietary
Proprietary
Register Space
Register Space
Register Space
0FFh
100h
0FFh
100h
0FFh
100h
Extended
Extended
Extended
Configuration
Configuration
Configuration
Space / PCI Express
Capability Structures
Space / PCI Express
Capability Structures
Space / PCI Express
Capability Structures
FFFh
FFFh
FFFh
Port# 1
Port# 2
Port# 3
Bus# N+2**
Bus# N+3**
Bus# N+4**
** Example values. Actual bus numbers may change based on system hierarchy.
Figure 4-1. XIO3130 Enumerations Topology
4.2 PCI Express Upstream Port Registers
The default reset domain for all upstream port registers is IPRST. The internal IPRST reset signal is
asserted when the internally-generated power-on reset is asserted, when GRST is asserted, when PERST
is asserted, or when PCI Express training control hot reset is asserted. Some register fields are placed in
a reset domain different from the default reset domain; all bit or field descriptions identify any unique reset
domains. Generally, all sticky bits are placed in the GRST domain and all (non-sticky) EEPROM loadable
bits are placed in the PERST domain.
34
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4.2.1 PCI Configuration Space (Upstream Port) Register Map
Table 4-1. PCI Express Upstream Port Configuration Register Map (Type 1)
Register Name
Offset
000h
Device ID
Status
Vendor ID
Command
004h
Class Code
Revision ID
008h
BIST
Header Type
Latency Timer
Cache Line Size
00Ch
Reserved
010h-014h
018h
Secondary Latency Timer
Subordinate Bus Number
Secondary Bus Number
I/O Limit
Primary Bus Number
I/O Base
Secondary Status
01Ch
Memory Limit
Memory Base
020h
Pre-fetchable Memory Limit
Pre-fetchable Memory Base
024h
Pre-fetchable Base Upper 32 Bits
Pre-fetchable Limit Upper 32 Bits
028h
02Ch
I/O Limit Upper 16 Bits
I/O Base Upper 16 Bits
030h
Reserved
Capabilities Pointer
034h
Reserved
Reserved
038h
Bridge Control
Interrupt Pin
Interrupt Line
PM CAP ID
03Ch
040h-04Ch
050h
Power Management Capabilities
Next-item Pointer
PM Data (RSVD)
PMCSR_BSE
Power Management CSR
054h
Reserved
058h-06Ch
070h
MSI Message Control
Next-item Pointer
MSI CAP ID
MSI Message Address
074h
MSI Upper Message Address
078h
Reserved
Reserved
MSI Message Data
Next-item Pointer SSID/SSVID CAP ID
Subsystem Vendor ID
07Ch
080h
Subsystem ID
084h
Reserved
Next-item Pointer
088h-08Ch
090h
PCI Express Capabilities Register
Device Status
PCI Express Capability ID
Device Capabilities
Link Capabilities
Reserved
094h
Device Control
098h
09Ch
Link Status
Link Control
0A0h
0A4h-0ACh
0B0h
SB Control and Status
Serial Bus Slave Address
Serial Bus Index
Serial Bus Data
Upstream Port L1 Idle
Upstream Port Link PM Latency
0B4h
Global Chip Control
0B8h
GPIO B Control
GPIO D Control
GPIO A Control
GPIO C Control
0BCh
0C0h
GPIO Data
TI Proprietary
0C4h
0C8h-0DCh
0E0h
Subsystem Access
General Control
0E4h
Global Switch Control
Downstream Ports Link PM Latency
0E8h
Reserved
0ECh-0FCh
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Table 4-2. Extended Configuration Space (Upstream Port)
Register Name
PCI Express Advanced Error Reporting Capabilities ID
Offset
Next Capability Offset / Capability Version
100h
104h
Uncorrectable Error Status Register
Uncorrectable Error Mask Register
Uncorrectable Error Severity Register
Correctable Error Status Register
Correctable Error Mask
108h
10Ch
110h
114h
Advanced Error Capabilities and Control
Header Log Register
118h
11Ch
120h
Header Log Register
Header Log Register
124h
Header Log Register
128h
Reserved
12Ch-FFCh
4.2.2 Vendor ID Register
This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to Texas
Instruments.
PCI register offset:
Register type:
00h
Read-only
104Ch
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
4.2.3 Device ID Register
This 16-bit read-only register contains the value 8232h, which is the device ID assigned by TI to the
XIO3130 upstream port function.
PCI register offset:
Register type:
02h
Read-only
8232Ch
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
0
0
0
1
1
0
0
1
0
4.2.4 Command Registers
PCI register offset:
Register type:
04h
Read/Write; Read-only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Table 4-3. Bit Descriptions – Command Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:11
RSVD
r
INTx disable. This bit is used to enable device-specific interrupts. The XIO3130 upstream port does
not generate any interrupts internally, so this bit is ignored. The XIO3130 does forward INTx
messages from downstream ports to the upstream port.
10
9
INT_DISABLE
FBB_ENB
rw
r
Fast back-to-back enable. This bit does not apply to PCI-Express, and returns zero when read.
SERR enable. When set, the XIO3130 can signal fatal and nonfatal errors on the upstream PCI
Express interface.
8
7
SERR_ENB
STEP_ENB
rw
r
0 – Disable the reporting of nonfatal errors and fatal errors.
1 – Enable the reporting of nonfatal errors and fatal errors.
Address/data stepping control. This bit does not apply to PCI-Express and is hardwired to 0.
Parity error response enable. Mask bit for the DATAPAR bit in the Status Register.
0 – The upstream bridge must ignore any address or data parity errors that it detects and
continue normal operation.
6
PERR_ENB
rw
1 – The upstream bridge must detect address or data parity errors and report them by setting
the DATAPAR bit in the Status Register.
VGA palette snoop enable. The XIO3130 does not support VGA palette snooping, thus this bit
returns zero when read.
5
VGA_ENB
r
Memory write and invalidate enable. This bit does not apply to PCI-Express, and is hardwired to
zero.
4
3
MWI_ENB
SPECIAL
r
r
Special cycle enable. This bit does not apply to PCI-Express and is hardwired to zero.
Bus master enable. When set, the XIO3130 is enabled to initiate cycles on the upstream PCI
Express interface.
0 – Upstream PCI Express interface cannot initiate transactions. The bridge must disable
response to memory and I/O transactions on the PCI interface.
2
MASTER_ENB
rw
1 – Upstream PCI Express interface can initiate transactions. The bridge can forward memory
and I/O transactions from the secondary interface.
Memory response enable. Setting this bit enables the XIO3130 to respond to memory transactions
on the upstream PCI Express interface.
1
0
MEMORY_ENB
IO_ENB
rw
rw
I/O space enable. Setting this bit enables the XIO3130 to respond to I/O transactions on the
upstream PCI Express interface.
4.2.5 Status Register
The Status register provides information about the primary interface to the system.
PCI register offset:
Register type:
06h
Read Only; Cleared by a Write of One; Hardware Update
0010h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
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Table 4-4. Bit Descriptions – Status Register
BIT FIELD NAME
ACCESS
DESCRIPTION
Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP on the
upstream port. This bit is set regardless of the state of the Parity Error Response bit in the Command
Register.
15
PAR_ERR
rcu
0 – No parity error detected.
1 – Parity Error detected.
Signaled system error. This bit is set when the XIO3130 sends an ERR_FATAL or ERR_NONFATAL
message upstream, and the SERR Enable bit in the Command Register is set.
14
13
SYS_ERR
MABORT
rcu
rcu
rcu
rcu
0 – No error signaled.
1 – ERR_FATAL or ERR_NONFATAL signaled.
Received master abort. This bit is set when the upstream PCI Express interface of the XIO3130
receives a Completion with Unsupported Request Status
0 – Unsupported Request not received.
1 – Unsupported Request received on.
Received target abort. This bit is set when the upstream PCI Express interface of the XIO3130
receives a Completion with Completer Abort Status
12 TABORT_REC
0 – Completer Abort not received.
1 – Completer Abort received.
Signaled target abort. This bit is set when the upstream PCI Express interface completes a Request
with Completer Abort Status.
11
TABORT_SIG
0 – Completer Abort not signaled.
1 – Completer Abort signaled.
10:9
8
PCI_SPEED
DATAPAR
r
DEVSEL timing. These bits are read only zero because they do not apply to PCI Express.
Master data parity error. This bit is set when the XIO3130 receives a poisoned completion or poisons
a write request on the upstream PCI Express interface. This bit is never set if the parity error
response enable bit in the Command register is clear.
rcu
Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express device and
is hardwired to 0.
7
6
5
FBB_CAP
RSVD
r
r
r
Reserved. When read, this bit returns zero.
66 MHz capable. This bit does not have a meaningful context for a PCI Express device and is
hardwired to 0.
66MHZ
Capabilities list. This bit returns 1 when read, indicating that the XIO3130 supports additional PCI
capabilities.
4
CAPLIST
r
Interrupt status. This bit reflects the interrupt status of the function. This bit is read-only zero since the
XIO3130 upstream port does not generate any interrupts internally. The XIO3130 does forward INTx
messages from downstream ports to the upstream port (see INTx Support section).
3
INT_STATUS
RSVD
r
r
2:0
Reserved. When read, these bits return zeros.
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4.2.6 Class Code and Revision ID Register
This read-only register categorizes the Base Class, Sub Class, and Programming Interface of the
XIO3130. The Base Class is 06h, identifying the device as bridge device. The Sub Class is 04h,
identifying the function as a PCI-to-PCI bridge, and the Programming Interface is 00h. Also, the TI chip
revision is indicated in the lower byte (02h).
PCI register offset:
Register type:
08h
Read only
0604 0002h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Table 4-5. Bit Descriptions – Class Code and Revision ID Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:24
BASECLASS
r
Base Class. This field returns 06h when read, which classifies the function as a Bridge device.
Sub Class. This field returns 04h when read, which specifically classifies the function as a
PCI-to-PCI bridge.
23:16
SUBCLASS
r
15:8
7:0
PGMIF
r
r
Programming Interface. This field returns 00h when read.
Silicon Revision. This field returns the silicon revision.
CHIPREV
4.2.7 Cache Line Size Register
The Cache Line Size Register is implemented by PCI Express devices as a read-write field for legacy
compatibility purposes but has no impact on any PCI Express device functionality.
PCI register offset:
Register type:
0Ch
Read/Write
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.2.8 Primary Latency Timer Register
This read-only register has no meaningful context for a PCI Express device and returns zeros when read.
PCI register offset:
Register type:
0Dh
Read Only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
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4.2.9 Header Type Register
This read-only register indicates that this function has a type one PCI header. Bit seven of this register is a
zero, indicating that the upstream port is a single device.
PCI register offset:
Register type:
0Eh
Read Only
01h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
4.2.10 BIST Register
Since the XIO3130 does not support a built-in self test (BIST), this read-only register returns the value of
00h when read.
PCI register offset:
Register type:
0Fh
Read Only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.2.11 Primary Bus Number
This read/write register specifies the bus number of the PCI bus segment to which the upstream PCI
Express interface is connected.
PCI register offset:
Register type:
18h
Read/Write
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.2.12 Secondary Bus Number
This read/write register specifies the bus number of the PCI bus segment for the XIO3130’s internal PCI
bus. The XIO3130 uses this register to determine how to respond to a Type 1 configuration transaction.
PCI register offset:
Register type:
19h
Read/Write
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
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4.2.13 Subordinate Bus Number
This register specifies the bus number of the highest number PCI bus segment that is downstream of the
XIO3130’s upstream port. The XIO3130 uses this register to determine how to respond to a Type 1
configuration transaction.
PCI register offset:
Register type:
1Ah
Read/Write
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.2.14 Secondary Latency Timer Register
This register does not apply to PCI-Express. It is hardwired to zero.
PCI register offset:
Register type:
1Bh
Read Only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.2.15 I/O Base Register
This read/write register specifies the lower limit of the I/O addresses that the XIO3130 forwards
downstream.
PCI register offset:
Register type:
1Ch
Read/Write; Read Only
01h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Table 4-6. Bit Descriptions – I/O Base Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:4
IOBASE
rw
I/O base. These bits define the bottom address of the I/O address range that is used to determine
when to forward I/O transactions from one interface to the other. These bits correspond to address
bits [15:12] in the I/O address. The lower 12 I/O address bits are assumed to be 0. The 16 bits
corresponding to address bits [31:16] of the I/O address are defined in the I/O Base Upper 16 Bits
register.
3:0
IOTYPE
r
I/O type. This field is read-only 01h, indicating that the XIO3130 supports 32-bit I/O addressing.
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4.2.16 I/O Limit Register
This read/write register specifies the upper limit of the I/O addresses that the XIO3130 forwards
downstream.
PCI register offset:
Register type:
1Dh
Read/Write; Read Only
01h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Table 4-7. Bit Descriptions – I/O Limit Register
BIT
7:4
3:0
FIELD NAME
IOLIMIT
ACCESS
DESCRIPTION
I/O limit. These bits define the top address of the I/O address range used to determine when to
forward I/O transactions from one interface to the other. These bits correspond to address bits
[15:12] in the I/O address. The lower 12 I/O address bits are assumed to be FFFh. The 16 bits
corresponding to address bits [31:16] of the I/O address are defined in the I/O Limit Upper 16 Bits
register.
rw
r
IOTYPE
I/O type. This field is read-only 01h, indicating that the XIO3130 supports 32-bit I/O addressing.
4.2.17 Secondary Status Register
The Secondary Status register provides information about the XIO3130’s internal PCI bus between the
upstream port and the downstream ports.
PCI register offset:
Register type:
1Eh
Read only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-8. Bit Descriptions – Secondary Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Detected parity error. This bit is hardwired to zero. It is assumed that the relevant error checking
is unnecessary for the XIO3130’s internal PCI bus.
15
14
13
12
PAR_ERR
r
r
r
r
Received system error. This bit is hardwired to zero. It is assumed that the relevant error
checking is unnecessary for the XIO3130’s internal PCI bus.
SYS_ERR
MABORT
Received master abort. This bit is hardwired to zero. It is assumed that the relevant error
checking is unnecessary for the XIO3130’s internal PCI bus.
Received target abort. This bit is hardwired to zero. It is assumed that the relevant error checking
is unnecessary for the XIO3130’s internal PCI bus.
TABORT_REC
Signaled target abort. This bit is hardwired to zero. It is assumed that the relevant error checking
is unnecessary for the XIO3130’s internal PCI bus.
11
10:9
8
TABORT_SIG
PCI_SPEED
DATAPAR
r
r
r
DEVSEL timing. These bits are hardwired to 00. These bits do not apply to PCI Express.
Master data parity error. This bit is hardwired to zero. It is assumed that the relevant error
checking is unnecessary for the XIO3130’s internal PCI bus.
7
6
FBB_CAP
RSVD
r
r
r
r
Fast back-to-back capable. This bit is hardwired to zero. This bit does not apply to PCI Express.
Reserved. When read, this bit returns zero.
5
66MHZ
RSVD
66 MHz capable. This bit is hardwired to zero. This bit does not apply to PCI Express.
Reserved. When read, these bits return zeros.
4:0
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4.2.18 Memory Base Register
This read/write register specifies the lower limit of the memory addresses that the XIO3130 forwards
downstream.
PCI register offset:
Register type:
20h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-9. Bit Descriptions – Memory Base Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Memory base. This field defines the bottom address of the memory address range used to
determine when to forward memory transactions from one interface to the other. These bits
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be 0.
15:4
3:0
MEMBASE
RSVD
rw
r
Reserved. When read, these bits return zeros.
4.2.19 Memory Limit Register
This read/write register specifies the upper limit of the memory addresses that the XIO3130 forwards
downstream.
PCI register offset:
Register type:
22h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 4-10. Bit Descriptions – Memory Limit Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Memory limit. This field defines the top address of the memory address range used to determine
when to forward memory transactions from one interface to the other. These bits correspond to
address bits [31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh.
15:4
3:0
MEMLIMIT
RSVD
rw
r
Reserved. When read, these bits return zeros.
4.2.20 Pre-fetchable Memory Base Register
This read/write register specifies the lower limit of the pre-fetchable memory addresses that the XIO3130
forwards downstream.
PCI register offset:
Register type:
24h
Read/Write; Read Only
0001h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 4-11. Bit Descriptions – Pre-fetchable Memory Base Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Pre-fetchable memory base. This field defines the bottom address of the pre-fetchable memory
address range that is used to determine when to forward memory transactions from one interface
to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20
bits are assumed to be 0. The Pre-fetchable Base Upper 32 Bits register is used to specify the bit
[63:32] of the 64-bit pre-fetchable memory address.
15:4
PREBASE
rw
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Table 4-11. Bit Descriptions – Pre-fetchable Memory Base Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
3:0
64BIT
r
4.2.21 Pre-Fetchable Memory Limit Register
This read/write register specifies the upper limit of the pre-fetchable memory addresses that the XIO3130
forwards downstream.
PCI register offset:
Register type:
26h
Read/Write; Read Only
0001h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 4-12. Bit Descriptions – Pre-fetchable Memory Limit Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Pre-fetchable memory limit. These bits define the top address of the pre-fetchable memory
address range used to determine when to forward memory transactions from one interface to the
other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are
assumed to be FFFFFh. The Pre-fetchable Limit Upper 32 Bits register is used to specify the bit
[63:32] of the 64-bit pre-fetchable memory address.
15:4
3:0
PRELIMIT
rw
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
64BIT
r
4.2.22 Pre-Fetchable Base Upper 32 Bits Register
This read/write register specifies the upper 32 bits of the Pre-fetchable Memory Base register.
PCI register offset:
Register type:
28h
Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-13. Bit Descriptions – Pre-fetchable Base Upper 32 Bits Register
BIT
31:0
FIELD NAME
ACCESS
DESCRIPTION
Pre-fetchable memory base upper 32 bits. This field defines the upper 32 bits of the bottom
address of the pre-fetchable memory address range that is used to determine when to forward
memory transactions downstream.
PREBASE
rw
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4.2.23 Pre-fetchable Limit Upper 32 Bits Register
This read/write register specifies the upper 32 bits of the Pre-fetchable Memory Limit register.
PCI register offset:
Register type:
2Ch
Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-14. Bit Descriptions – Pre-fetchable Limit Upper 32 Bits Register
FIELD
NAME
BIT
ACCESS
DESCRIPTION
Pre-fetchable memory limit upper 32 bits. This field defines the upper 32 bits of the top address of the
pre-fetchable memory address range used to determine when to forward memory transactions
downstream.
PRELIMI
T
31:0
rw
4.2.24 I/O Base Upper 16 Bits Register
This read/write register specifies the upper 16 bits of the I/O Base register.
PCI register offset:
Register type:
30h
Read/Write
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-15. Bit Descriptions – I/O Base Upper 16 Bits Register
BIT
15:0
FIELD NAME
ACCESS
DESCRIPTION
I/O base upper 16 bits. This field defines the upper 16 bits of the bottom address of the I/O
address range that is used to determine when to forward I/O transactions downstream.
IOBASE
rw
4.2.25 I/O Limit Upper 16 Bits Register
This read/write register specifies the upper 16 bits of the I/O Limit register.
PCI register offset:
Register type:
32h
Read/Write
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-16. Bit Descriptions – I/O Limit Upper 16 Bits Register
BIT
15:0
FIELD NAME
IOLIMIT
ACCESS
DESCRIPTION
I/O limit upper 16 bits. This field defines the upper 16 bits of the top address of the I/O address
range used to determine when to forward I/O transactions downstream.
rw
4.2.26 Capabilities Pointer Register
This read-only register provides a pointer into the PCI configuration header where the PCI power
management block resides. Since the PCI power management registers begin at 50h, this register is
hardwired to 50h.
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PCI register offset:
Register type:
34h
Read only
50h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
0
4.2.27 Interrupt Line Register
This read/write register, which is programmed by the system, indicates to the software which interrupt line
the XIO3130 has assigned to it. The default value of this register is FFh, which indicates that an interrupt
line has not yet been assigned to the function. Since the XIO3130 does not generate interrupts internally,
this register is essentially a scratch-pad register; it has no effect on the XIO3130 itself.
PCI register offset:
Register type:
3Ch
Read/Write
FFh
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
4.2.28 Interrupt Pin Register
The Interrupt Pin register is read-only 00h, which indicates that the XIO3130 upstream port does not
generate interrupts. The value of this register has no effect on forwarding interrupts from the downstream
ports to the upstream port.
PCI register offset:
Register type:
3Dh
Read Only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.2.29 Bridge Control Register
The Bridge Control register provides extensions to the Command register that are specific to a bridge.
PCI register offset:
Register type:
3Eh
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Table 4-17. Bit Descriptions – Bridge Control Register
BIT
15:12
11
10
9
FIELD NAME
RSVD
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
r
r
r
r
r
r
DTSERR
DTSTATUS
SEC_DT
Discard timer SERR enable. This bit is hardwired to zero. This bit does not apply to PCI Express.
Discard timer status. This bit is hardwired to zero. This bit does not apply to PCI Express.
Secondary discard timer. This bit is hardwired to zero. This bit does not apply to PCI Express.
Primary discard timer. This bit is hardwired to zero. This bit does not apply to PCI Express.
Fast back-to-back enable. This bit is hardwired to zero. This bit does not apply to PCI Express.
8
PRI_DEC
FBB_EN
7
Secondary bus reset. This bit is set when software wishes to reset all devices downstream of the
XIO3130. Setting this bit causes all of the downstream ports to be reset, and all of the downstream
ports to send a reset via a training sequence.
6
SRST
rw
0 – Downstream ports not in Reset state.
1 – Downstream ports in Reset state.
5
4
MAM
r
Master abort mode. This bit is hardwired to zero. This bit does not apply to PCI Express.
VGA 16-bit decode. This bit enables the XIO3130 to provide full 16-bit decoding for VGA I/O
addresses. This bit only has meaning if the VGA enable bit is set.
VGA16
rw
0 – Ignore address bits [15:10] when decoding VGA I/O addresses.
1 – Decode address bits [15:10] when decoding VGA I/O addresses.
VGA enable. This bit modifies the response by the XIO3130 to VGA-compatible addresses. If this
bit is set, the XIO3130 positively decodes and forwards the following accesses on the primary
interface to the secondary interface (and, conversely, blocks the forwarding of these addresses
from the secondary to primary interface):
•
•
Memory accesses in the range 000A 0000h to 000BFFFFh
I/O addresses in the first 64 KB of the I/O address space (Address bits [31:16] are 0000h)
and where address bits [9:0] is in the range of 3B0h to 3BBh or 3C0h to 3DFh (inclusive of
ISA address aliases – Address bits [15:10] may possess any value and is not used in the
decoding).
If the VGA Enable bit is set, forwarding of VGA addresses is independent of the value of the ISA
Enable bit (located in the Bridge Control register), the I/O address range and memory address
ranges defined by the I/O Base and Limit registers, the Memory Base and Limit registers, and the
Pre-fetchable Memory Base and Limit registers of the bridge. The forwarding of VGA addresses is
qualified by the I/O Enable and Memory Enable bits in the Command register.
3
VGA
rw
0 – Do not forward VGA-compatible memory and I/O addresses from the primary to secondary
interface (addresses defined above) unless they are enabled for forwarding by the defined
I/O and memory address ranges.
1 – Forward VGA-compatible memory and I/O addresses (addresses defined above) from the
primary interface to the secondary interface (if the I/O Enable and Memory Enable bits are
set) independent of the I/O and memory address ranges and independent of the ISA
Enable bit.
ISA enable. This bit modifies the response by the XIO3130 to ISA I/O addresses. This bit applies
only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first
64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the bridge blocks
any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each
1 KB block. In the opposite direction (secondary to primary), I/O transactions are forwarded if they
address the last 768 bytes in each 1K block.
2
ISA
rw
0 – Forward downstream all I/O addresses in the address range defined by the I/O Base and
I/O Limit registers.
1 – Forward upstream ISA I/O addresses in the address range defined by the I/O Base and I/O
Limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each 1
KB block).
SERR enable. This bit controls forwarding of system error events upstream from the secondary
interface to the primary interface. The XIO3130 forwards system error events when:
•
•
•
This bit is set.
The SERR enable bit in the upstream port command register is set.
SERR is asserted on the secondary interface.
1
SERR_EN
rw
0 – Disable the forwarding of system error events.
1 – Enable the forwarding of system error events.
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Table 4-17. Bit Descriptions – Bridge Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Parity error response enable. It is assumed that the relevant error checking is unnecessary for the
XIO3130’s internal PCI bus; therefore, setting this bit has no effect.
0
PERR_EN
rw
4.2.30 Capability ID Register
This read-only register identifies the linked list item as the register for PCI power management. The
register returns 01h when read.
PCI register offset:
Register type:
50h
Read only
01h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
4.2.31 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130. This register reads 70h, which points to the MSI Capabilities registers.
PCI register offset:
Register type:
51h
Read only
70h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
1
1
1
0
0
0
0
4.2.32 Power Management Capabilities Register
This register indicates the capabilities of the XIO3130 related to PCI power management.
PCI register offset:
Register type:
52h
Read only
XX03h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
y
1
1
x
1
1
x
0
0
0
0
0
0
0
1
1
Table 4-18. Bit Descriptions – Power Management Capabilities Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
PME support. This five-bit field indicates the power states from which the (upstream) port may
assert PME. These five bits return a value of 5’by11x1, indicating that the XIO3130 can assert
PME from D0, D2, D3hot, maybe D3cold (i.e., depending on y), and maybe D1 (i.e., depending
on x). The bit defining this for D3cold (i.e., y) is controlled by the AUX_PRSNT bit in the Global
Chip Control register. The bit defining this for D1 (i.e., x) is controlled by the D1_SUPPORT bit in
the Global Switch Control register.
15:11 PME_SUPPORT
r
D2 device power state support. This bit returns a 1 when read, which indicates that the function
supports the D2 device power state.
10
9
D2_SUPPORT
D1_SUPPORT
r
r
D1 device power state support. This bit indicates whether the function supports the D1 device
power state. This bit is controlled by the D1_SUPPORT bit in the Global Switch Control register.
The default value x refers to whatever the default value is for the D1_SUPPORT bit in the Global
Switch Control register.
3.3-VAUX auxiliary current requirements. This field is hardwired to 3’b000. See PCI Power
Management Specification Revision 1.2, Section 3.2.3, Page 26, for mapping this field to specific
current consumption values.
8:6
5
AUX_CURRENT
DSI
r
r
Device-specific initialization. This bit returns 0 when read, which indicates that the XIO3130 does
not require special initialization beyond the standard PCI configuration header before a generic
class driver is able to use it.
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Table 4-18. Bit Descriptions – Power Management Capabilities Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, this bit returns zero.
4
RSVD
r
PME clock. This bit returns zero, which indicates that the PCI clock is not needed to generate
PME.
3
PME_CLK
r
r
2:0
PM_VERSION
Power management version. This field returns 3’b011, which indicates Revision 1.2 compatibility.
4.2.33 Power Management Control/Status Register
This register determines and changes the current power state of the XIO3130.
PCI register offset:
Register type:
54h
Read/Write; Read Only
0008h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Table 4-19. Bit Descriptions – Power Management Control/Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
PME status. This bit is hardwired to 0b since the XIO3130’s upstream port does not generate
PME regardless of PME_SUPPORT field setting.
15
PME_STAT
r
Data scale. This 2-bit field returns 0’s when read since the XIO3130 does not use the Data
Register.
14:13
12:9
DATA_SCALE
DATA_SEL
r
r
Data select. This 4-bit field returns 0’s when read since the XIO3130 does not use the Data
Register
PME enable. This bit enables PME signaling. This bit is hardwired to 0b since the XIO3130’s
upstream port does not generate PME.
8
PME_EN
RSVD
r
r
7:4
Reserved. When read, these bits return zeros.
No soft reset. This bit controls whether the transition from D3hot to D0 resets the state
according to the PCI Power Management Specification Revision 1.2. This bit is hardwired to
1’b1.
3
2
NO_SOFT_RST
RSVD
r
r
0 – D3hot to D0 transition causes reset.
1 – D3hot to D0 transition does not cause reset.
Reserved. When read, this bit returns zero.
Power state. This 2-bit field is used both to determine the current power state of the function
and to set the function into a new power state. This field is encoded as follows:
00 = D0
01 = D1
10 = D2
11 = D3hot
1:0
PWR_STATE
rw
See the Power Management section of this document for information about what the XIO3130
does in these different power states.
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4.2.34 Power Management Bridge Support Extension Register
This read-only register is used to indicate to host software the state of the secondary bus when the
XIO3130 is placed in D3.
PCI register offset:
Register type:
56h
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4-20. Bit Descriptions – PM Bridge Support Extension Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Bus power/Clock control enable. This bit is read-only zero. This bit does not apply to PCI
Express.
7
BPCC
r
6
BSTATE
RSVD
r
r
B2/B3 support. This bit is read-only zero. This bit does not apply to PCI Express.
Reserved. When read, these bits return zeros.
5:0
4.2.35 Power Management Data Register
This read-only register is not applicable to the XIO3130 and returns 00h when read.
PCI register offset:
Register type:
57h
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.2.36 MSI Capability ID Register
This read-only register identifies the linked list item as the register for Message Signaled Interrupts (MSI)
Capabilities. The register returns 05h when read.
PCI register offset:
Register type:
70h
Read only
05h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
1
4.2.37 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130. This register reads 80h, which points to the Subsystem ID and Subsystem Vendor ID
Capabilities registers.
PCI register offset:
Register type:
71h
Read only
80h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
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4.2.38 MSI Message Control Register
This register is used to control the sending of MSI messages.
PCI register offset:
Register type:
72h
Read/Write; Read Only
0080h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Table 4-21. Bit Descriptions – MSI Message Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:8
RSVD
r
64-bit message capability. This bit is read-only 1, which indicates that the XIO3130 supports 64-bit
MSI message addressing.
7
64CAP
r
Multiple message enable. This bit indicates the number of distinct messages that the XIO3130 is
allowed to generate.
000 – 1 Message
001 – 2 Messages
010 – 4 Messages
011 – 8 Messages
100 – 16 Messages
101 – 32 Messages
110 – Reserved
6:4
MM_EN
rw
111 – Reserved
Multiple message capabilities. This field indicates the number of distinct messages that the
XIO3130 is capable of generating. This field is read-only 000, which indicates that the XIO3130
can signal one interrupt.
3:1
0
MM_CAP
MSI_EN
r
MSI enable. This bit is used to enable MSI interrupt signaling. MSI signaling must be enabled by
software for the XIO3130 to send MSI messages.
rw
0 – MSI signaling is prohibited.
1 – MSI signaling is enabled.
4.2.39 MSI Message Address Register
This register contains the lower 32 bits of the address that a MSI message shall be written to when an
interrupt is to be signaled.
PCI register offset:
Register type:
74h
Read/Write; Read Only
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-22. Bit Descriptions – MSI Message Address Register
BIT
FIELD NAME
ADDRESS
RSVD
ACCESS
DESCRIPTION
31:2
1:0
rw
r
System Specified Message Address.
Reserved. When read, these bits return zeros.
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4.2.40 MSI Message Upper Address Register
This register contains the upper 32 bits of the address that a MSI message shall be written to when an
interrupt is to be signaled. If this register is 0000 0000h, 32-bit addressing is used; otherwise, 64-bit
addressing is used.
PCI register offset:
Register type:
78h
Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCI register offset:
Register type:
56h
Read only
00h
Default value:
4.2.41 MSI Message Data Register
This register contains the data that software programmed the device to send when it sends a MSI
message.
PCI register offset:
Register type:
7Ch
Read/Write
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-23. Bit Descriptions – MSI Data Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
System-specific message. This field contains the portion of the message that the XIO3130 can
never modify.
15:4
MSG
rw
Message number. This portion of the message field may be modified to contain the message
number if multiple messages are enabled. Since the XIO3130 only generates one MSI type,
these bits are not modified by XIO3130 hardware.
3:0
MSG_NUM
rw
4.2.42 Capability ID Register
This read-only register identifies the linked list item as the register for Subsystem ID and Subsystem
Vendor ID Capabilities. The register returns 0Dh when read.
PCI register offset:
Register type:
80h
Read only
0Dh
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
1
4.2.43 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130. This register reads 90h, which points to the PCI Express Capabilities registers.
PCI register offset:
81h
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Register type:
Read only
90h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
4.2.44 Subsystem Vendor ID Register
This register, which is used for system and option card identification purposes, may be required for certain
operating systems. This read-only register is a direct reflection of the Subsystem Access register, which is
read/write and is initialized through the EEPROM (if present).
PCI register offset:
Register type:
84h
Read only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.2.45 Subsystem ID Register
This register, which is used for system and option card identification purposes, may be required for certain
operating systems. This read-only register is a direct reflection of the Subsystem Access register, which is
read/write and is initialized through the EEPROM (if present).
PCI register offset:
Register type:
86h
Read only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.2.46 PCI Express Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express Capabilities. The
register returns 10h when read.
PCI register offset:
Register type:
90h
Read only
10h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
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4.2.47 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130. This register reads 00h, which indicates that no additional capabilities are supported.
PCI register offset:
Register type:
91h
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.2.48 PCI Express Capabilities Register
This register indicates the capabilities of the upstream port of the XIO3130 related to PCI Express.
PCI register offset:
Register type:
92h
Read only
0051h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
Table 4-24. Bit Descriptions – PCI Express Capabilities Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:14
RSVD
r
Interrupt message number. This field is used for MSI support and is implemented as read-only
zero in the XIO3130.
13:9
INT_NUM
SLOT
r
r
r
r
Slot implemented. This bit is invalid for the upstream port on the XIO3130 and is read-only
zero.
8
Device/Port type. This read-only field returns 0101b, which indicates that the device is an
upstream port of a PCI Express XIO3130.
7:4
3:0
DEV_TYPE
VERSION
Capability version. This field returns 0001b, which indicates revision 1 of the PCI Express
capability.
4.2.49 Device Capabilities Register
The Device Capabilities register indicates the device-specific capabilities of the XIO3130.
PCI register offset:
Register type:
94h
Read Only; Hardware Update
0000 8001h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
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Table 4-25. Bit Descriptions – Device Capabilities Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
31:28
RSVD
r
Captured slot power limit scale. The value in this register is programmed by the host by issuing
a Set_Slot_Power_Limit Message. When a Set_Slot_Power_Limit Message is received, bits 9:8
are written to this field. The value in this register specifies the scale used for the Slot Power
Limit.
27:26
25:18
CSPLS
ru
00 – 1.0x
01 – 0.1x
10 – 0.01x
11 – 0.001x
Captured slot power limit value. The value in this register is programmed by the host by issuing
a Set_Slot_Power_Limit Message. When a Set_Slot_Power_Limit Message is received, bits 7:0
are written to this field. The value in this register, in combination with the Slot power limit scale
value, specifies the upper limit of power supplied to the slot. The power limit is calculated by
multiplying the value in this field by the value in the Slot power limit scale field.
CSPLV
ru
17:16
15
RSVD
RBER
RSVD
ETFS
r
r
r
r
Reserved. When read, these bits return zeros.
Role-based error reporting. This field is set to 1b to indicate support for role-based error
reporting.
14:6
5
Reserved. When read, these bits return zeros.
Extended tag field supported. This field indicates the size of the tag field supported. This bit is
hardwired to zero, indicating support for 5-bit tag fields.
Phantom functions supported. This field is read-only 00b, indicating that function numbers are
not used for phantom functions.
4:3
2:0
PFS
r
r
Max payload size supported. This field indicates the maximum payload size that the device can
support for TLPs. This field is encoded as 001b, which indicates that the maximum payload size
for a TLP is 256 bytes.
MPSS
4.2.50 Device Control Register
The Device Control register controls PCI Express device-specific parameters.
PCI register offset:
Register type:
98h
Read/Write; Read Only
2000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-26. Bit Descriptions – Device Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, this bit returns zero.
15
RSVD
r
Max read request size. This field is programmed by the host software to set the maximum size
of a read request that the XIO3130 can generate. The XIO3130 uses this field in conjunction
with the cache line size register to determine how much data to fetch on a read request. This
field is encoded as:
000 – 128B
001 – 256B
14:12
MRRS
rw
010 – 512B
011 – 1024B
100 – 2048B
101 – 4096B
110 – Reserved
111 – Reserved
Enable no snoop. Since the XIO3130 does not initiate such transactions, this bit is read-only
zero.
11
ENS
r
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Table 4-26. Bit Descriptions – Device Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Auxiliary power PM enable. This bit is read-only zero, since the XIO3130 requires a minimal
amount of AUX power when PME is disabled.
10
APPE
r
Phantom function enable. Since the XIO3130 part does not support phantom functions, this bit
is read-only zero.
9
8
PFE
r
r
Extended tag field enable. Since the XIO3130 part does not support extended tags, this bit is
read-only zero.
ETFE
Max payload size. This field is programmed by the host software to set the maximum size of
posted writes or read completions that the XIO3130 can initiate. This field is encoded as:
000 – 128B
001 – 256B
010 – 512B
7:5
MPS
rw
011 – 1024B
100 – 2048B
101 – 4096B
110 – Reserved
111 – Reserved
Enable relaxed ordering. Since the XIO3130 part does not support relaxed ordering, this bit is
read-only zero.
4
3
ERO
r
Unsupported request reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_NONFATAL messages to the root complex when an unsupported request is received by
the upstream port.
URRE
rw
0 – Do not report unsupported requests to the root complex.
1 – Report unsupported requests to the root complex.
Fatal error reporting enable. If this bit is set, the XIO3130 is enabled to send ERR_FATAL
messages to the root complex when a system error event occurs.
2
1
0
FERE
NFERE
CERE
rw
rw
rw
0 – Do not report fatal errors to the root complex.
1 – Report fatal errors to the root complex.
Nonfatal error reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_NONFATAL messages to the root complex when a system error event occurs.
0 – Do not report nonfatal errors to the root complex.
1 – Report nonfatal errors to the root complex.
Correctable error reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_CORR messages to the root complex when a system error event occurs.
0 – Do not report correctable errors to the root complex.
1 – Report correctable errors to the root complex.
4.2.51 Device Status Register
The Device Status register controls PCI Express device-specific parameters.
PCI register offset:
Register type:
9Ah
Read Only; Clear by a Write of One; Hardware Update
00X0h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
Table 4-27. Bit Descriptions – Device Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:6
RSVD
r
Transaction PENDING. This bit is set when the XIO3130 has issued a non-posted transaction
that has not been completed yet.
5
PEND
ru
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Table 4-27. Bit Descriptions – Device Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
AUX power detected. This bit indicates that AUX power is present. This bit is a direct reflection
of the AUX_PRSNT bit in the Global Chip Control register and has the same default value.
4
APD
ru
0 – No AUX power detected.
1 – AUX power detected.
Unsupported request detected. This bit is asserted when a request is received that results in
sending a completion with an Unsupported Request status). Errors are logged in this bit
regardless of whether error reporting is enabled in the Device Control register.
3
2
1
URD
FED
rcu
rcu
rcu
Fatal error detected. This bit is set by the XIO3130 when a fatal error is detected. Errors are
logged in this bit regardless of whether error reporting is enabled in the Device Control register.
Nonfatal error detected. This bit is set by the XIO3130 when a nonfatal error is detected. Errors
are logged in this bit regardless of whether error reporting is enabled in the Device Control
register.
NFED
Correctable error detected. This bit is set by the XIO3130 when a correctable error is detected.
Errors are logged in this bit regardless of whether error reporting is enabled in the Device
Control register.
0
CED
rcu
4.2.52 Link Capabilities Register
The Link Capabilities register indicates the link-specific capabilities of the device.
PCI register offset:
Register type:
9Ch
Read only
000X XX11h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
1
y
y
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
y
z
z
z
x
1
0
0
0
0
0
1
0
0
0
1
Table 4-28. Bit Descriptions – Link Capabilities Register
BIT
31:24
23:19
18
FIELD NAME
PORT_NUM
RSVD
ACCESS
DESCRIPTION
Port number. This field indicates the port number for the PCI Express link. This field is
read-only zero.
r
r
r
Reserved. When read, these bits return zeros.
Clock power management. This field is read-only 1b, which indicates that CLKREQ is
supported on the upstream port.
CLK_PM
L1 exit latency. This field indicates the time that it takes to transition from the L1 state to the
L0 state. This field is a direct reflection of the Upstream Port Link PM Latency register
L1_EXIT_LAT field, which is a read/write field that is loaded from EEPROM (if present). The
default value of this field, yyy, is the same as the default value of the Link PM Latency
register L1_EXIT_LAT field.
17:15
L1_LATENCY
r
L0s exit latency. This field indicates the time that required to transition from the L0s state to
the L0 state. This field is a direct reflection of the Upstream Port Link PM Latency register
L0S_EXIT_LAT field, which is a read/write field that is loaded from EEPROM (if present).
The default value of this field, zzz, is the same as the default value of the Link PM Latency
register L0S_EXIT_LAT field.
14:12
11:10
L0S_LATENCY
ASLPMS
r
r
Active state link PM support. This field reads either 01b or 11b, which indicates that the
device supports L0s and may or may not support ASPM-based L1 for Active State Link PM.
ASPM-based L1 support is controlled by the ASPM_L1_EN field in the Global Chip Control
register.
Maximum link width. This field is encoded 000001b to indicate that the device only supports
an x1 PCI Express link.
9:4
3:0
MLW
MLS
r
r
Maximum link speed. This field is encoded 0001b to indicate that the device supports a
maximum link speed of 2.5 Gb/s.
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4.2.53 Link Control Register
The Link Control register is used to control link-specific behavior.
PCI register offset:
Register type:
A0h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-29. Bit Descriptions – Link Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:9
RSVD
r
Clock power management enable. When CLKREQ support is enabled, the EP_LI_LAT field in
the Upstream Ports Link PM Latency register increases due to link PLL locking requirements.
8
CPM_EN
ES
rw
0 – Disable CLKREQ on upstream port
1 – Enable CLKREQ on upstream port
Extended synch. This bit is used to force the device to extend the transmission of FTS ordered
sets and an extra TS2 when exiting from L1 before entering to L0.
7
6
rw
rw
0 – Normal synch
1 – Extended synch
Common clock configuration. This bit is set when a common clock is provided to both ends of
the PCI Express link. This bit can be used to change the L0s and L1 exit latencies.
CCC
0 – Reference clock is asynchronous.
1 – Reference clock is synchronous.
5
4
RL
LD
r
r
Retrain link. This bit has no function for upstream ports and is read-only zero.
Link disable. This bit has no function for upstream ports and is read-only zero.
Read completion boundary. This bit specifies the minimum size read completion packet that the
XIO3130 can send when breaking a read request into multiple completion packets. This field is
not applicable to XIO3130 switches; i.e., the XIO3130 does not break up completion packets
and is hardwired to zero.
3
2
RCB
RSVD
r
r
0 – 64 bytes
1 – 128 bytes
Reserved. When read, this bit returns zero.
Active state link PM control. This field is used to enable and disable active state PM.
00 – Active state PM disabled
1:0
ASLPMC
rw
01 – L0s entry enabled
10 – Reserved
11 – L0s and L1 entry enable
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4.2.54 Link Status Register
The Link Status register indicates the current state of the PCI Express Link.
PCI register offset:
Register type:
A2h
Read only
1X11h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
x
0
0
0
0
0
1
0
0
0
1
Table 4-30. Bit Descriptions – Link Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:13
RSVD
r
Slot clock configuration. This bit reflects the reference clock configurations and is read-only 1,
indicating that a 100 MHz common clock reference is used.
12
SCC
r
11
10
LT
UNDEF
NLW
LS
r
r
r
r
Link training in progress. This bit has no function for upstream ports and is read-only zero.
Undefined. The value read from this bit is undefined.
9:4
3:0
Negotiated link width. This field is read-only 000001b, which indicates that the lane width is x1.
Link speed. This field is read-only 0001b, which indicates that the link speed is 2.5Gb/s.
4.2.55 Serial Bus Data Register
The Serial Bus Data register is used to read and write data on the serial bus interface, e.g., for use with a
serial EEPROM. When writing data to the serial bus, this register must be written before writing to the
Serial Bus Address register to initiate the cycle. When reading data from the serial bus, this register
contains the data read after the REQBUSY (bit 5 Serial Bus Control register) bit is cleared. This register is
reset with PERST.
PCI register offset:
Register type:
B0h
Read/Write
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.2.56 Serial Bus Index Register
The value written to the Serial Bus Index register represents the byte address of the byte being read or
written from the serial bus device. The Serial Bus Index register must be written before initiating a serial
bus cycle by writing to the Serial Bus Slave Address register. This register is reset with PERST.
PCI register offset:
Register type:
B1h
Read/Write
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
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4.2.57 Serial Bus Slave Address Register
The Serial Bus Slave Address register is used to indicate the address of the device being targeted by the
serial bus cycle. This register also indicates whether the cycle will be a read or a write cycle. Writing to
this register initiates the cycle on the serial interface. This register is reset with PERST. The default value
corresponds to a serial EEPROM slave address of 7’b101_0000.
PCI register offset:
Register type:
B2h
Read/Write
A0h
Default value:
BIT NUM BER
RESET STATE
7
6
5
4
3
2
1
0
1
0
1
0
0
0
0
0
Table 4-31. Bit Descriptions – Serial Bus Slave Address Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Serial bus slave address. This bit field represents the slave address for a read/write transaction
on the serial interface.
7:1
SLAVE_ADDR
rw
This field is reset with PERST.
Read/Write command. This bit is used to determine whether the serial bus cycle is a read or a
write cycle.
0 – A single byte write is requested.
1 – A single byte read is requested.
This field is reset with PERST.
0
RW_CMD
rw
4.2.58 Serial Bus Control and Status Register
The Serial Bus Control and Status register is used to control the behavior of the serial bus interface. This
register also provides status information about the state of the serial bus.
PCI register offset:
Register type:
B3h
Read/Write; Read Only; Clear by a Write of One; Hardware Update
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4-32. Bit Descriptions – Serial Bus Control and Status Register
BIT
FIELD NAME
PROT_SEL
RSVD
ACCESS
DESCRIPTION
Protocol select. This bit is used to select the serial bus address mode used.
0 – Slave address and byte address are sent on the serial bus.
1 – Only the slave address is sent on the serial bus.
This field is reset with PERST.
7
6
5
rw
r
Reserved. When read, this bit returns zero.
Requested serial bus access busy. This bit is set when a serial bus cycle is in progress.
0 – No serial bus cycle
REQBUSY
ru
1 – Serial bus cycle in progress
This field is reset with PERST.
Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the XIO3130
device is downloading register defaults from a serial EEPROM.
0 – No EEPROM activity
4
ROMBUSY
ru
1 – EEPROM download in progress
This field is reset with PERST.
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Table 4-32. Bit Descriptions – Serial Bus Control and Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Serial EEPROM detected. This bit is automatically set when a serial EEPROM is detected via
the strapping option. For more information on strapping options, see section 1.9.1. The value
of this bit is used to enable the serial bus interface and to control whether the EEPROM load
occurs. Note that a serial EEPROM is only detected once following PERST or GRST.
0 – No EEPROM present, EEPROM load process does not occur.
1 – EEPROM present, EEPROM load process occurs.
3
SBDETECT
rwu
Note that even if a serial EERPOM is not detected following PERST, system software can still
set this bit to enable the serial bus interface. For more information on system software setting
the bit, see section 1.9.4.
This field is reset with PERST.
2
1
RSVD
r
Reserved. When read, this bit returns zero.
Serial bus error. This bit is set when an error occurs during a software-initiated serial bus
cycle.
0 – No error
SB_ERR
rc
1 – Serial bus error
This field is reset with PERST.
Serial EEPROM load error. This bit is set when an error occurs while downloading registers
from a serial EEPROM.
0 – No error
0
ROM_ERR
rc
1 – EEPROM load error
This field is reset with PERST.
4.2.59 Upstream Port Link PM Latency Register
This read/write register is used to program L0s and L1 exit latencies for the upstream port.
PCI register offset:
Register type:
B4h
Read/Write; Read Only; Clear by a Write of One; Hardware Update
0024h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
Table 4-33. Bit Descriptions – Upstream Port Link PM Latency Register
BIT
15:14
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
Endpoint L0s acceptable latency. This field is used to program the maximum acceptable
RSVD
r
latency when exiting the L0s state. This field is used to set the L0s Acceptable Latency field in
the Device Capabilities register.
000 – Less than 64 ns (default)
001 – 64 ns up to less than 128 ns
010 – 128 ns up to less than 256 ns
011 – 256 ns up to less than 512 ns
100 – 512 ns up to less than 1 µs
101 – 1 µs up to less than 2 µs
13:11
EP_L0S_LAT
rw
110 – 2 µs to 4 µs
111 – More than 4 µs
This field is loaded from EEPROM (when present) and reset with PERST.
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Table 4-33. Bit Descriptions – Upstream Port Link PM Latency Register (continued)
BIT
10:8
7:6
FIELD NAME
EP_L1_LAT
RSVD
ACCESS
DESCRIPTION
Endpoint L1 acceptable latency. This field is used to program the maximum acceptable latency
when exiting the L1 state. This field is used to set the L1 Acceptable Latency field in the Device
Capabilities register.
000 – Less than 1 µs (default)
001 – 1 µs up to less than 2 µs
010 – 2 µs up to less than 4 µs
rw
011 – 4 µs up to less than 8 µs
100 – 8 µs up to less than 16 µs
101 – 16 µs up to less than 32 µs
110 – 32 µs to 64 µs
111 – More than 64 µs
This field is loaded from EEPROM (when present) and reset with PERST.
Reserved. When read, these bits return zeros.
r
L0s exit latency. This field is used to program the maximum latency for the PHY to exit the L0s
state. This field is used to set the L0s Exit Latency field in the Link Capabilities register.
000 – Less than 64 ns
001 – 64 ns up to less than 128 ns
010 – 128 ns up to less than 256 ns
011 – 256 ns up to less than 512 ns
100 – 512 ns up to less than 1 µs (default)
101 – 1 µs up to less than 2 µs
110 – 2 µs to 4 µs
5:3
L0S_EXIT_LAT
rw
111 – More than 4 µs
Define writtenBySW to default to false, be set to true whenever the software or serial EEPROM
writes this field to a value that is different from its current state, and can only be subsequently
set to false as a result of a reset. When writtenBySW is false, this field is set to 011b when the
CCC bit in the Link Control register is asserted (i.e., common clock mode) and set to 100b
when the CCC bit is de-asserted (i.e., non-common clock mode). When writtenBySW is true,
this field is the value that was last written by the software.
This field is loaded from EEPROM (when present) and reset with PERST.
This field may be programmed differently depending on the values programmed in the
DEFER_L_EXIT and SMART_L_EXIT fields in the Global Switch Control register.
L1 exit latency. This field is used to program the maximum latency for the PHY to exit the L1
state. This field is used to set the L1 Exit Latency field in the Link Capabilities register.
000 – Less than 1 µs
001 – 1 µs up to less than 2 µs
010 – 2 µs up to less than 4 µs
011 – 4 µs up to less than 8 µs
100 – 8 µs up to less than 16 µs (default)
101 – 16 µs up to less than 32 µs
110 – 32 µs to 64 µs
2:0
L1_EXIT_LAT
rw
111 – More than 64 µs
Define writtenBySW to default to false, be set to true when the software or serial EEPROM
writes this field to a value that is different from its current state, and can only be subsequently
set to false as a result of a reset. When writtenBySW is false, this field is set to 100b. When
writtenBySW is true, this field is the value last written by the software.
This field is loaded from EEPROM (when present) and reset with PERST.
This field may be programmed differently depending on the values programmed in the
DEFER_L_EXIT and SMART_L_EXIT fields in the Global Switch Control register.
62
XIO3130 Configuration Register Space
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4.2.60 Global Chip Control Register
This read/write register is used to control various functionalities across the entire device.
PCI register offset:
Register type:
B8h
Read/Write; Read Only; Hardware Update; Sticky
0000 000Xh
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
Table 4-34. Bit Descriptions – Global Chip Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, this bit returns zero.
31
RSVD
r
ASPM-based L1 PLL disable. This bit enables or disables PLL during ASPM-based L1 for
all PHYs on the XIO3130. This setting does not affect D-state-based L1, for which PLLs
must be shut off during L1.
30
ASPM_L1_PLL_DIS
rw
rw
0 – Enable PLL during ASPM-based L1.
1 – Disable PLL during ASPM-based L1.
This field is loaded from EEPROM (when present) and reset with PERST.
ASPM-based L1 enable. This bit enables ASPM-based L1 on the PCI Express chip-level
upstream port. This field controls whether the ASPM Support field in the Link Capabilities
register reports support for ASPM-based L1 for all functions in a multifunction device.
29
ASPM_L1_EN
0 – Disable ASPM based L1.
1 – Enable ASPM based L1.
This field is loaded from EEPROM (when present) and reset with PERST.
This bit is a reserved diagnostic bit and must be set to 0 for proper operation. If an
EEPROM is used, the corresponding bit in the EEPROM must be set to 0.
28
RSVD
RSVD
rw
r
27:22
Reserved. When read, these bits return zeros.
Minimum power scale. This value is programmed to indicate the scale of the Minimum
Power Value field.
00 – 1.0x
MIN_POWER_SCA
LE
01 – 0.1x
21:20
rw
10 – 0.01x
11 – 0.001x
This field is loaded from EEPROM (when present) and reset with PERST.
Minimum power value. This value is programmed to indicate the minimum power
requirements for all circuitry powered by a slot, and is not applicable for motherboard
down applications (i.e., must be programmed to zero in that case). This value is multiplied
by the Minimum Power Scale field. When the value is non-zero, the resultant power figure
is compared against information conveyed in Set_Slot_Power_Limit Messages received
on the upstream port. When the value is zero, the comparison is ignored as if there is no
power limit.
MIN_POWER_VAL
UE
19:12
rw
This field is loaded from EEPROM (when present) and reset with PERST.
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Table 4-34. Bit Descriptions – Global Chip Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Power override. This field is used to determine how the device responds when the slot
power limit (via Set_Slot_Power_Limit Message received) is greater than the amount of
power programmed in the MIN_SLOT_POWER field of this register. This power
comparison is disabled when the MIN_SLOT_POWER field of the register is zero.
00 – Ignore slot power limit.
01 – Assert the PWR_OVER pin.
11:10
PWR_OVRD
rw
10 – Assert the PWR_OVER pin and respond with Unsupported request to all transactions
except configuration transactions (Type 0 or Type 1) and Set_Slot_Power_Limit
Messages.
11 – Reserved
This field is loaded from EEPROM (when present) and reset with PERST.
Reserved. When read, these bits return zeros.
9:3
2
RSVD
r
Wake or beacon. This bit controls whether wake events are signaled using the WAKE pin
or a beacon transmission.
0 – Beacon mode.
WAKE_OR_BCN
rwh
1 – WAKE mode.
This field is reset with GRST and is loaded from EEPROM (when present).
Wake to beacon enable. This bit enables externally generated wake events detected on
the WAKE pin to cause a beacon to be transmitted. This field is ignored if
WAKE_OR_BCN is set to WAKE mode.
1
0
WAKE2BCN
AUX_PRSNT
rwh
0 – WAKE input to beacon translation disabled.
1 – WAKE input to beacon translation enabled.
This field is reset with GRST and is loaded from EEPROM (when present).
AUX power present. This bit reflects the state of a 3.3-VAUX presence detection circuit
output in the PCI Express reference macro. This bit controls the AUX Power Detected bit
in the Device Status register (i.e., whether AUX power is present) for all ports.
ru
0 – AUX power is not present.
1 – AUX power is present.
4.2.61 GPIO A Control Register
This register is used to control the function of the PCIE_GPIO 0 – 4 pins.
PCI register offset:
Register type:
BCh
Read/Write; Read Only; Hardware Update; Sticky
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
64
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Table 4-35. Bit Descriptions – GPIO A Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
15
RSVD
r
Reserved. Reads back zero.
GPIO 4 Control. This field controls the GPIO4 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_BTN0
011 – Port 3 ACT_BTN2
100 – Port 1 PWRFLT0
101 – Port 3 PWRFLT2
14:12
PCIE_GPIO4_CTL
rw
110 – Port 1 EMIL_ENG0
111 – Port 3 EMIL_ENG2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If the DN2_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO4 terminal
is directly mapped as the PRESENT PCI Hot Plug terminal for port 3 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
GPIO 3 Control. This field controls the GPIO3 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 CLKREQ0
011 – Port 1 MRLS_DET0
100 – Port 2 PWRFLT1
11:9
PCIE_GPIO3_CTL
rw
101 – Port 3 PWRFLT2
110 – Port 2 MRLS_DET1
111 – Port 3 MRLS_DET2,
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 2 Control. This field controls the GPIO2 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 2 ACT_BTN1
011 – Port 3 ACT_BTN2
100 – Port 2 PWRFLT1
101 – Port 3 PWRFLT2
8:6
PCIE_GPIO2_CTL
rw
110 – Port 2 MRLS_DET1
111 – Port 3 MRLS_DET2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If the DN1_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO2 terminal
is directly mapped as the PWR_GOOD PCI Hot Plug terminal for port 2 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
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Table 4-35. Bit Descriptions – GPIO A Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
GPIO 1 Control. This field controls the GPIO1 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 2 EMIL_CTL1
011 – Port 3 EMIL_CTL2
100 – Port 2 ATN_LED1
101 – Port 3 ATN_LED2
5:3
PCIE_GPIO1_CTL
rw
110 – Port 2 PWR_LED1
111 – Port 3 PWR_LED2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If the DN1_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO1 terminal
is directly mapped as the PWR_ON PCI Hot Plug terminal for port 2 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
GPIO 0 Control. This field controls the GPIO0 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 2 ACT_BTN1
011 – Port 3 ACT_BTN2
100 – Port 2 PWRFLT1
101 – Port 3 PWRFLT2
2:0
PCIE_GPIO0_CTL
rw
110 – Port 2 EMIL_ENG1
111 – Port 3 EMIL_ENG2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If the DN1_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO1 terminal
is directly mapped as the PWR_ON PCI Hot Plug terminal for port 2 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
4.2.62 GPIO B Control Register
This register is used to control the function of the PCIE_GPIO 5 – 9 pins.
PCI register offset:
Register type:
BEh
Read/Write
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
66
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Table 4-36. Bit Descriptions – GPIO B Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
15
RSVD
r
Reserved, reads back zero
GPIO 9 Control. This field controls the GPIO9 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 EMIL_CTL0
011 – Port 2 EMIL_CTL2
100 – Port 1 ATN_LED0
101 – Port 2 ATN_LED1
14:12
PCIE_GPIO9_CTL
rw
110 – Port 1 PWR_LED0
111 – Port 2 PWR_LED1
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If the DN3_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO9 terminal
is directly mapped as the PWR_ON PCI Hot Plug terminal for port 3 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
GPIO 8 Control. This field controls the GPIO8 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_BTN0
011 – Port 2 ACT_BTN1
100 – Port 1 PWRFLT0
101 – Port 2 PWRFLT1
11:9
PCIE_GPIO8_CTL
rw
110 – Port 1 EMIL_ENG0
111 – Port 2 EMIL_ENG1
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If the DN3_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO8 terminal
is directly mapped as the PRESENT PCI Hot Plug terminal for port 3 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
GPIO 7 Control. This field controls the GPIO7 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 2 CLKREQ1
011 – Port 2 MRLS_DET1
100 – Port 1 PWRFLT0
8:6
PCIE_GPIO7_CTL
rw
101 – Port 3 PWRFLT2
110 – Port 1 MRLS_DET0
111 – Port 3 MRLS_DET2,
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
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Table 4-36. Bit Descriptions – GPIO B Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
GPIO 6 Control. This field controls the GPIO6 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_BTN0
011 – Port 3 ACT_BTN2
100 – Port 1 PWRFLT0
101 – Port 3 PWRFLT2
110 – Port 1 MRLS_DET0
5:3
PCIE_GPIO6_CTL
rw
111 – Port 3 MRLS_DET2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If DPSTRP[1] == 1, this bit field is read only and reads back zero.
If the DN2_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO6 terminal
is directly mapped as the PWR_GOOD PCI Hot Plug terminal for port 3 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
GPIO 5 Control. This field controls the GPIO5 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 EMIL_CTL0
011 – Port 3 EMIL_CTL2
100 – Port 1 ATN_LED0
101 – Port 3 ATN_LED2
110 – Port 1 PWR_LED0
2:0
PCIE_GPIO5_CTL
rw
111 – Port 3 PWR_LED2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If DPSTRP[1] == 1, this bit field is read only and reads back zero.
If the DN2_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO5 terminal
is directly mapped as the PWR_ON PCI Hot Plug terminal for port 3 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
4.2.63 GPIO C Control Register
This register is used to control the function of the PCIE_GPIO 10 – 13 pins.
PCI register offset:
Register type:
C0h
Read/Write; Sticky
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
68
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Table 4-37. Bit Descriptions – GPIO C Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
15
RSVD
r
Reserved. Reads back zero.
GPIO 14 Control. This field controls the GPIO14 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_LED0
011 – Port 2 ACT_LED1
100 – Port 3 ACT_LED2
14:12
11:9
8:6
PCIE_GPIO14_CTL
PCIE_GPIO13_CTL
PCIE_GPIO12_CTL
PCIE_GPIO11_CTL
rw
rw
rw
rw
101 – Port 1 PWR_LED0
110 – Port 2 PWR_LED1
111 – Port 3 PWRFLT2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 12 Control. This field controls the GPIO12 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_LED0
011 – Port 2 ACT_LED1
100 – Port 3 ACT_LED2
101 – Port 1 ATN_LED0
110 – Port 2 PWR_LED1
111 – Port 3 PWR_LED2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 12 Control. This field controls the GPIO12 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_LED0
011 – Port 2 ACT_LED1
100 – Port 3 ACT_LED2
101 – Port 1 PWR_LED0
110 – Port 2 ATN_LED1
111 – Port 3 ATN_LED2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 11 Control. This field controls the GPIO11 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 3 CLKREQ2
011 – Port 3 MRLS_DET2
100 – Port 1 PWRFLT0
5:3
101 – Port 2 PWRFLT1
110 – Port 1 MRLS_DET0
111 – Port 2 MRLS_DET1,
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
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Table 4-37. Bit Descriptions – GPIO C Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
GPIO 10 Control. This field controls the GPIO10 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_BTN0
011 – Port 2 ACT_BTN1
100 – Port 1 PWRFLT0
101 – Port 2 PWRFLT1
2:0
PCIE_GPIO10_CTL
rw
110 – Port 1 MRLS_DET0
111 – Port 2 MRLS_DET1
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If the DN3_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO10
terminal is directly mapped as the PWR_GOOD PCI Hot Plug terminal for port 3 and is no
longer available for use as a GPIO. In this situation these bits have no meaning and should
be left at their default value.
4.2.64 GPIO D Control Register
This register is used to control the function of the PCIE_GPIO 15–19 pins.
PCI register offset:
Register type:
C2h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
70
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Table 4-38. Bit Descriptions – GPIO D Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:10
RSVD
r
GPIO 18 Control. This field controls the GPIO18 pin as follows:
00 – General Purpose Input (default)
01 – General Purpose Output
9:8
PCIE_GPIO18_CTL
rw
10 – HP_INTX, PCI Hot Plug Interrupt Output
11 – PD_CHG, Presence Detect Changed Output
See GPIO Data register for a detailed description of this field. This field is loaded from
EEPROM (if present), and reset with FRST.
GPIO 17 Control. This field controls the GPIO19 pin as follows:
00 – General Purpose Input (default)
01 – General Purpose Output
7:6
PCIE_GPIO17_CTL
rw
10 – General Purpose Input
11 – PWR_OVER, Power Limits exceeded
See GPIO Data register for a detailed description of this field. This field is loaded from
EEPROM (if present), and reset with FRST.
GPIO 16 Control. This field controls the GPIO16 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ATN_LED0
011 – Port 2 ATN_LED1
5:3
PCIE_GPIO16_CTL
rw
100 – Port 3 ATN_LED2
101 – Port 1 PWRFLT0
110 – Port 2 PWRFLT1
111 – Port 3 PWRFLT2
See GPIO Data register for a detailed description of this field. This field is loaded from
EEPROM (if present), and reset with FRST.
GPIO 15 Control. This field controls the GPIO15 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ATN_LED0
011 – Port 2 ATN_LED1
2:0
PCIE_GPIO15_CTL
rw
100 – Port 3 PWR_LED2
101 – Port 1 PWRFLT0
110 – Port 2 PWRFLT1
111 – Port 3 PWRFLT2.
See GPIO Data register for a detailed description of this field. This field is loaded from
EEPROM (if present), and reset with FRST.
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4.2.65 GPIO Data Register
This register is used to read the state of the GPIO pins and to change the state of GPIO pins that are in
output mode. Reads to this register return the state of the GPIO pins, regardless of PCI Hot Plug
strapping or GPIO configuration. Writes to this register only affect pins that are configured as a general
purpose output.
PCI register offset:
Register type:
C4h
Read/Write; Read Only
00000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-39. Bit Descriptions – GPIO Data Register
BIT
31:19
FIELD NAME
ACCESS
DESCRIPTION
RSVD
r
GPIO 18 data.
HP_INTX / PD_CHG / GPIO 18 data.
HP_INTX output mode:
Reads indicate current state of pin
Writes have no affect
PD_CHG output mode:
Reads indicate current state of pin
Writes have no affect
18
PCIE_GPIO18_DATA
rw
PD_CHG is asserted whenever all of the following are true for any given slot:
PDC[n] bit is asserted in the Slot Status register for switch downstream port n, and
PDC_EN[n] bit is asserted in Slot Control Register for switch downstream port n
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
This field is loaded from EEPROM (if present), and reset with FRST.
PWR_OVER / GPIO 17 data.
PWR_OVER mode: reads state of pin; writes have no affect
PWR_OVER pin is asserted whenever any of the following conditions are true:
PERST is asserted
17
PCIE_GPIO17_DATA
rw
Conditions are met for exceeding slot power limit (see PWR_OVRD field in
Global Chip Control Register)
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
This field is loaded from EEPROM (if present), and reset with FRST.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 15 data.
16
15
PCIE_GPIO16_DATA
PCIE_GPIO15_DATA
rw
rw
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
This field is loaded from EEPROM (if present), and reset with FRST.
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Table 4-39. Bit Descriptions – GPIO Data Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
GPIO 14 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 13 data.
14
PCIE_GPIO14_DATA
rw
LED driver (see GPIO C Controls)
13
12
11
PCIE_GPIO13_DATA
PCIE_GPIO12_DATA
PCIE_GPIO11_DATA
rw
rw
rw
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
This bit field is loaded from EEPROM (if present), and reset with FRST.
GPIO 12 data.
LED driver (see GPIO C Controls)
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
This bit field is loaded from EEPROM (if present), and reset with FRST.
GPIO 11 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
Program-selectable HP input or output pin
This bit field is loaded from EEPROM (if present), and reset with FRST.
GPIO 10 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
Program-selectable HP input pin
10
PCIE_GPIO10_DATA
rw
This field is valid only if DN3_DPSTRP == 0. If this bit field is valid then it is loaded from
EEPROM (if present), and reset with FRST. If this field is invalid, it is a read-only bit
field.
GPIO 9 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
Program-selectable HP input pin
9
PCIE_GPIO9_DATA
rw
This field is valid only if DN3_DPSTRP == 0. If this bit field is valid then it is loaded from
EEPROM (if present), and reset with FRST. If this field is invalid, it is a read-only bit
field.
GPIO 8 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
Program-selectable HP output pin
8
7
PCIE_GPIO8_DATA
PCIE_GPIO7_DATA
rw
rw
This field is valid only if DN3_DPSTRP == 0. If this bit field is valid then it is loaded from
EEPROM (if present), and reset with FRST. If this field is invalid, it is a read-only bit
field.
GPIO 7 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
GP Output mode: reads and also controls state of pin
This bit field is loaded from EEPROM (if present), and reset with FRST.
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Table 4-39. Bit Descriptions – GPIO Data Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
GPIO 6 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
Program-selectable HP input pin
6
PCIE_GPIO6_DATA
rw
This field is valid only if DN2_DPSTRP == 0. If this bit field is valid then it is loaded from
EEPROM (if present), and reset with FRST. If this field is invalid, it is a read-only bit
field.
GPIO 5 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
Program-selectable HP input pin
5
PCIE_GPIO5_DATA
rw
This field is valid only if DN2_DPSTRP == 0. If this bit field is valid then it is loaded from
EEPROM (if present), and reset with FRST. If this field is invalid, it is a read-only bit
field.
GPIO 4 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
Program-selectable HP output pin
4
3
2
PCIE_GPIO4_DATA
PCIE_GPIO3_DATA
PCIE_GPIO2_DATA
rw
rw
rw
This field is valid only if DN2_DPSTRP == 0. If this bit field is valid then it is loaded from
EEPROM (if present), and reset with FRST. If this field is invalid, it is a read-only bit
field.
GPIO 3 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
Program-selectable HP Input or Output pin
This bit field is loaded from EEPROM (if present), and reset with FRST.
GPIO 2 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
Program-selectable HP input pin
This field is valid only if DN1_DPSTRP == 0. If this bit field is valid then it is loaded from
EEPROM (if present), and reset with FRST. If this field is invalid, it is a read-only bit
field.
GPIO 1 data.
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
Program-selectable HP input pin
1
PCIE_GPIO1_DATA
rw
This field is valid only if DN1_DPSTRP == 0. If this bit field is valid then it is loaded from
EEPROM (if present), and reset with FRST. If this field is invalid, it is a read-only bit
field.
GPIO 0 data.
GP Input mode: reads state of pin; writes have no effect
GP Output mode: reads and also controls state of pin
Program-selectable HP output pin
0
PCIE_GPIO0_DATA
rw
This field is valid only if DN1_DPSTRP == 0. If this bit field is valid then it is loaded from
EEPROM (if present), and reset with FRST. If this field is invalid, it is a read-only bit
field.
74
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4.2.66 TI Proprietary Register
This read/write TI proprietary register is located at offset C8h and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
If an EEPROM is used to load configuration registers, the value loaded for this register must be
00000001h.
PCI register offset:
Register type:
C8h
Read/Write
xxxx 0001h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4.2.67 TI Proprietary Register
This read/write TI proprietary register is located at offset CCh and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
If an EEPROM is used to load configuration registers, the value loaded for this register must be
00000000h.
PCI register offset:
Register type:
CCh
Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.2.68 TI Proprietary Register
This read/write TI proprietary register is located at offset D0h and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
If an EEPROM is used to load configuration registers, the value loaded for this register must be
32140000h.
PCI register offset:
Register type:
D0h
Read/Write
3214 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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4.2.69 TI Proprietary Register
This read/write TI proprietary register is located at offset D4h and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
If an EEPROM is used to load configuration registers, the value loaded for register D5h must be 10h.
PCI register offset:
Register type:
D4h
Read/Write
0000 0010
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
4.2.70 TI Proprietary Register
This read/write TI proprietary register is located at offset D8h and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
PCI register offset:
Register type:
D8h
Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.2.71 TI Proprietary Register
This read/write TI proprietary register is located at offset DCh and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
PCI register offset:
Register type:
DCh
Read/Write
0000 0002h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
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4.2.72 Subsystem Access Register
This register is a read/write register. The contents of this register are aliased to the Subsystem Vendor ID
and Subsystem ID registers at PCI Offsets 84h and 86h for all PCI Express ports.
PCI register offset:
Register type:
E0h
Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-40. Bit Descriptions – Subsystem Access Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Subsystem ID. The value written to this field is aliased to the Subsystem ID register at PCI
Offset 66h. This field is loaded from EEPROM (when present) and reset with PERST.
31:16
SubsystemID
rw
Subsystem Vendor ID. The value written to this field is aliased to the Subsystem Vendor
ID register at PCI Offset 64h. This field is loaded from EEPROM (when present) and reset
with PERST.
15:0
SubsystemVendorID
rw
4.2.73 General Control Register
This register is a read/write register that is used to control various functions of the XIO3130.
PCI register offset:
Register type:
E4h
Read/Write; Read Only
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-41. Bit Descriptions – General Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
31:3
RSVD
r
2
1
0
TI_PROPRIETARY
L1_DISABLE
RSVD
rw
TI proprietary. This bit must not be changed from the specified default value.
L1 disable. This bit may be used to disable software-directed L1 entry when in
lower D-states (D1-D3). The value of L1_DISABLE is 0 (the default). Link
power states are managed in accordance with the PCI Express base
specification. When L1_DISABLE is 1, the upstream port of the XIO3130 does
not enter L1 even when directed to do so through software.
rw
r
Reserved. When read, this bit returns zero.
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4.2.74 Downstream Ports Link PM Latency Register
This read/write register is used to program L0s and L1 exit latencies for all XIO3130 downstream ports.
Similar information is provided in a separate register for the upstream port.
PCI register offset:
Register type:
E8h
Read/Write; Read Only
3F24h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-42. Bit Descriptions – Downstream Ports Link PM Latency Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
Endpoint L0s acceptable latency. This field is used to program the maximum acceptable
15:14
RSVD
r
latency when exiting the L0s state. This field is used to set the L0s Acceptable Latency field
in the Device Capabilities register.
000 – Less than 64 ns
001 – 64 ns up to less than 128 ns
010 – 128 ns up to less than 256 ns
011 – 256 ns up to less than 512 ns
100 – 512 ns up to less than 1 µs
101 – 1 µs up to less than 2 µs
13:11
EP_L0S_LAT
rw
110 – 2 µs to 4 µs
111 – More than 4 µs (default)
This field is loaded from EEPROM (when present) and reset with PERST.
Endpoint L1 acceptable latency. This field is used to program the maximum acceptable
latency when exiting the L1 state. This field is used to set the L1 Acceptable Latency field in
the Device Capabilities register.
000 – Less than 1 µs
001 – 1 µs up to less than 2 µs
010 – 2 µs up to less than 4 µs
10:8
EP_L1_LAT
rw
011 – 4 µs up to less than 8 µs
100 – 8 µs up to less than 16 µs
101 – 16 µs up to less than 32 µs
110 – 32 µs to 64 µs
111 – More than 64 µs (default)
This field is loaded from EEPROM (when present) and reset with PERST.
Reserved. When read, these bits return zeros.
7:6
5:3
RSVD
r
L0s exit latency. This field is used to program the maximum latency for the PHY to exit the
L0s state. This is used to set the L0s Exit Latency field in the Link Capabilities register.
000 – Less than 64 ns
001 – 64 ns up to less than 128 ns
010 – 128 ns up to less than 256 ns
011 – 256 ns up to less than 512 ns
100 – 512 ns up to less than 1 µs (default)
101 – 1 µs up to less than 2 µs
110 – 2 µs to 4 µs
L0S_EXIT_LAT
rw
111 – More than 4 µs
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Table 4-42. Bit Descriptions – Downstream Ports Link PM Latency Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
L1 exit latency. This field is used to program the maximum latency for the PHY to exit the
L1 state. This is used to set the L1 Exit Latency field in the Link Capabilities register.
000 – Less than 1 µs
001 – 1 µs up to less than 2 µs
010 – 2 µs up to less than 4 µs
011 – 4 µs up to less than 8 µs
100 – 8 µs up to less than 16 µs (default)
101 – 16 µs up to less than 32 µs
110 – 32 µs to 64 µs
2:0
L1_EXIT_LAT
rw
111 – More than 64 µs
4.2.75 Global Switch Control Register
This read/write register is used to control various functions across the entire XIO3130.
PCI register offset:
Register type:
EAh
Read/Write; Read Only; Clear by a Write of One; Sticky
0004h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-43. Bit Descriptions – Global Switch Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
Downstream ports L0s independence
15:7
RSVD
r
0 – Downstream ports (all) Tx L0s entry dependent on whether upstream Rx is in L0s according to
6
DP_L0S_IND
rw
PCI Express Base Specification, section 5.4.1.1.1.
1 – Downstream ports Tx L0s entry not dependent on whether upstream Rx is in L0s.
Reserved. When read, this bit returns zero.
5
4
3
RSVD
DEFER_L_EXIT
RSVD
r
rw
r
Defer L0s, L1 exit. This bit configures logic to not automatically power up all downstream ports when
the upstream port receives a downstream flowing packet.
This field is loaded from EEPROM (when present) and reset with PERST.
Reserved. When read, this bit returns zero.
D1 support. This bit enables whether all PCI Express XIO3130 functions are capable of D1 support.
The field controls (1) the D1_SUPPORT bit in the Power Management Capabilities register for all
XIO3130 ports, and (2) bit 1 in the 5-bit PME_SUPPORT field in the Power Management Capabilities
register for all XIO3130 ports.
2
D1_SUPPORT
rw
0 – D1 not supported
1 – D1 supported
This field is loaded from EEPROM (when present) and reset with PERST.
PCI Hot Plug PME message enable. This bit enables PME_Turn_Off/PME_TO_Ack messages when
power is shut off to a slot using the PC_CTL bit in the Slot Control register for downstream ports.
HP_PME_MSG
_EN
0 – Disable PME_Turn_Off / PME_TO_Ack messages for slot power control
1 – Enable PME_Turn_Off / PME_TO_Ack messages for slot power control
This field is loaded from EEPROM (when present) and reset with PERST.
1
0
rw
Beacon detect disable. This bit disables beacon detection on all downstream ports and allows the
reference macro to be placed in low power state during D3cold.
0 – Beacon detection enabled
BCN_DET_DIS
rwh
1 – Beacon detection disabled
This field is loaded from EEPROM (when present) and reset with GRST.
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4.2.76 Advanced Error Reporting Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express Advanced Error
Reporting Capabilities. The register returns 0001h when read.
PCI register offset:
Register type:
100h
Read only
0001h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4.2.77 Next Capability Offset/Capability Version Register
This read-only register returns the value 0000h to indicate that this extended capability block represents
the end of the linked list of extended capability structures. The least significant four bits identify the
revision of the current capability block as 1h.
PCI register offset:
Register type:
102h
Read only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.2.78 Uncorrectable Error Status Register
This register reports the status of individual errors as they occur. Software may clear these bits only by
writing a 1 to the desired location.
PCI register offset:
Register type:
104h
Read Only, Cleared by a Write of one
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-44. Uncorrectable Error Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:21
RSVD
r
Reserved. Return zeros when read.
Unsupported Request error. This bit is asserted when an Unsupported Request error is
20
UR_ERROR
rcuh
detected (i.e., when a request is received that results in the sending of a completion with
an Unsupported Request status).
19
18
ECRC_ERROR
MAL_TLP
rcuh
rcuh
Extended CRC error. This bit is asserted when an Extended CRC error is detected.
Malformed TLP. This bit is asserted when a malformed TLP is detected.
Receiver overflow. This bit is asserted when the flow control logic detects that the
transmitting device has illegally exceeded the number of credits that were issued.
17
16
15
14
13
RX_OVERFLOW
UNXP_CPL
rcuh
rcuh
rcuh
rcuh
rcuh
Unexpected completion. This bit is asserted when a completion packet is received that
does not correspond to an issued request.
Completer abort. This bit is asserted when the completion to a pending request arrives with
Completer Abort status.
CPL_ABORT
CPL_TIMEOUT
FC_ERROR
Completion timeout. This bit is asserted when no completion has been received for an
issued request before the timeout period.
Flow control error. This bit is asserted when a flow control protocol error is detected either
during initialization or during normal operation.
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Table 4-44. Uncorrectable Error Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Poisoned TLP. This bit is asserted when an outgoing packet (request or completion) has
been poisoned by setting the poison bit and has inverted the extended CRC attached to
the end of the packet.
12
PSN_TLP
rcuh
11:6
5
RSVD
SD_ERROR
DLL_ERROR
RSVD
r
rcuh
rcuh
r
Reserved. Return zeros when read.
Surprise down error. See Surprise Down ECN for a description of this error condition.
Data link protocol error. This bit is asserted if a data link layer protocol error is detected.
Reserved. Return zeros when read.
4
3:1
0
Undefined
r
The value read from this bit is undefined.
4.2.79 Uncorrectable Error Mask Register
The Uncorrectable Error Mask register controls the reporting of individual errors as they occur. When a bit
is set to one, the error status bits are still affected, but the error is not logged and no error reporting
message is sent upstream.
PCI register offset:
Register type:
108h
Read Only, Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-45. Uncorrectable Error Mask Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:21
RSVD
r
Reserved. Return zeros when read.
Unsupported Request error mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Extended CRC error mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Malformed TLP mask.
20
UR_ERROR_MASK
rwh
rwh
rwh
rwh
rwh
rwh
rwh
19
18
17
16
15
14
ECRC_ERROR_MASK
MAL_TLP_MASK
0 - Error condition is unmasked.
1 - Error condition is masked.
Receiver Overflow mask.
RX_OVERFLOW_MASK
UNXP_CPL_MASK
0 - Error condition is unmasked.
1 - Error condition is masked.
Unexpected Completion mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Completer Abort mask.
CPL_ABORT_MASK
CPL_TIMEOUT_MASK
0 - Error condition is unmasked.
1 - Error condition is masked.
Completion Timeout mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
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Table 4-45. Uncorrectable Error Mask Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Flow Control error mask.
13
FC_ERROR_MASK
rwh
0 - Error condition is unmasked.
1 - Error condition is masked.
Poisoned TLP mask.
12
11:6
5
PSN_TLP_MASK
RSVD
rwh
r
0 - Error condition is unmasked.
1 - Error condition is masked.
Reserved. Return zeros when read.
Surprise Down error mask.
SD_MASK
rwh
0 - Error condition is unmasked.
1 - Error condition is masked.
Data Link Protocol error mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
4
DLL_ERROR_MASK
rwh
3:1
0
RSVD
r
r
Reserved. Return zeros when read.
The value read from this bit is undefined.
Undefined
4.2.80 Uncorrectable Error Severity Register
The Uncorrectable Error Severity register controls the reporting of individual errors as ERR_FATAL or
ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is
clear, the corresponding error condition is identified as nonfatal.
PCI register offset:
Register type:
10Ch
Read Only, Read/Write
0003 2030h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
Table 4-46. Uncorrectable Error Severity Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Return zeros when read.
Unsupported Request error severity.
31:21
RSVD
r
20
19
18
17
UR_ERROR_SEVR
ECRC_ERROR_SEVR
MAL_TLP_SEVR
rwh
rwh
rwh
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Extended CRC error severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Malformed TLP severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Receiver Overflow severity.
RX_OVERFLOW_SEVR
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
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Table 4-46. Uncorrectable Error Severity Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Unexpected Completion severity.
16
UNXP_CPL_SEVR
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Completer Abort severity.
15
14
13
CPL_ABORT_SEVR
CPL_TIMEOUT_SEVR
FC_ERROR_SEVR
rwh
rwh
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Completion Timeout severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Flow Control error severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Poisoned TLP severity.
12
11:6
5
PSN_TLP_SEVR
RSVD
rwh
r
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Reserved. Return zeros when read.
Surprise Down error severity.
SD_ERROR_SEVR
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Data Link Protocol error severity.
4
DLL_ERROR_SEVR
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Reserved. Return zeros when read.
3:1
0
RSVD
r
r
Undefined
The value read from this bit is undefined.
4.2.81 Correctable Error Status Register
The Correctable Error Status register reports the status of individual errors as they occur. Software may
clear these bits only by writing a 1 to the desired location.
PCI register offset:
Register type:
110h
Read Only, Cleared by a Write of one
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-47. Correctable Error Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:14
13
RSVD
r
Reserved. Return zeroes when read.
Advisory nonfatal error status.
ANFES
rcuh
Replay timer timeout. This bit is asserted when the replay timer expires for a pending
request or completion that has not been acknowledged.
12
11:9
8
REPLAY_TMOUT
RSVD
rcuh
r
Reserved. Return zeroes when read.
REPLAY_NUM rollover. This bit is asserted when the replay counter rolls over when a
pending request of completion has not been acknowledged.
REPLAY_ROLL
rcuh
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Table 4-47. Correctable Error Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Bad DLLP error. This bit is asserted when an 8b/10n error is detected by the PHY during
reception of a DLLP.
7
BAD_DLLP
rcuh
Bad TLP error. This bit is asserted when an 8b/10b error is detected by the PHY during
reception of a TLP.
6
5:1
0
BAD_TLP
RSVD
rcuh
r
Reserved. Return zeros when read.
Receiver error. This bit is asserted when an 8b/10b error is detected by the PHY at any
time.
RX_ERROR
rcuh
4.2.82 Correctable Error Mask Register
The Correctable Error Mask register controls the reporting of individual errors as they occur. When a bit is
set to one, error status bits are still affected, but the error is not logged and no error reporting message is
sent upstream.
PCI register offset:
Register type:
114h
Read Only, Read/Write
0000 2000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-48. Correctable Error Mask Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Return zeros when read.
31:14
RSVD
r
Advisory nonfatal error mask. This bit is set by default to enable compatibility with
software that does not comprehend role-based error reporting.
13
ANFEM
rwh
0 – Error condition is unmasked
1 – Error condition is masked
Replay timer timeout mask.
0 – Error condition is unmasked
1 – Error condition is masked
Reserved. Return zeros when read.
REPLAY_NUM rollover mask.
0 – Error condition is unmasked
1 – Error condition is masked
Bad DLLP error mask.
12
11:9
8
REPLAY_TMOUT_MASK
RSVD
rwh
r
REPLAY_ROLL_MASK
rwh
7
BAD_DLLP_MASK
rwh
0 – Error condition is unmasked
1 – Error condition is masked
Bad TLP error mask.
6
5:1
0
BAD_TLP_MASK
RSVD
rwh
r
0 – Error condition is unmasked
1 – Error condition is masked
Reserved. Return zeros when read.
Receiver error mask.
RX_ERROR_MASK
rwh
0 – Error condition is unmasked
1 – Error condition is masked
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4.2.83 Advanced Error Capabilities and Control Register
The Advanced Error Capabilities and Control register allows the system to monitor and control the
advanced error reporting capabilities.
PCI register offset:
Register type:
118h
Read Only, Read/Write
0000 00A0h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
Table 4-49. Advanced Error Capabilities and Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Return zeros when read.
31:9
RSVD
r
Extended CRC check enable.
8
ECRC_CHK_EN
ECRC_CHK_CAPABLE
ECRC_GEN_EN
rwh
r
0 – Extended CRC checking is disabled
1 – Extended CRC checking is enabled
Extended CRC check capable. This read-only bit returns a value of ‘1’ indicating that
the bridge is capable of checking extended CRC information.
7
6
Extended CRC generation enable.
rwh
0 – Extended CRC generation is disabled
1 – Extended CRC generation is enabled
Extended CRC generation capable. This read-only bit returns a value of ‘1’
indicating that the bridge is capable of generating extended CRC information.
5
ECRC_GEN_CAPABLE
FIRST_ERR
r
First error pointer. This five-bit value reflects the bit position within the Uncorrectable
Error Status register corresponding to the class of the first error condition that was
detected.
4:0
rh
4.2.84 Header Log Register
The Header Log register stores the TLP header for the packet that lead to the most recently detected error
condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a
4DW TLP header).
PCI register offset:
Register type:
11Ch – 128h
Read only
Default value:
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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4.3 PCI Express Downstream Port Registers
The default reset domain for all downstream port registers is SBRST. Some register fields are placed in a
different reset domain from the default reset domain; all bit and field descriptions identify any unique reset
domains. Generally, all sticky bits are placed in the GRST domain and all (non-sticky) EEPROM loadable
bits are placed in the PERST domain.
4.3.1 PCI Configuration Space (Downstream Port) Register Map
Table 4-50. PCI Express Downstream Port Configuration Register Map (Type 1)
Register Name
Offset
000h
Device ID
Status
Vendor ID
Command
004h
Class Code
Revision ID
008h
BIST
Header Type
Latency Timer
Cache Line Size
00Ch
Reserved
010h-014h
018h
Secondary Latency Timer
Subordinate Bus Number
Secondary Bus Number
I/O Limit
Primary Bus Number
I/O Base
Secondary Status
01Ch
Memory Limit
Memory Base
020h
Pre-fetchable Memory Limit
Pre-fetchable Memory Base
024h
Pre-fetchable Base Upper 32 Bits
Pre-fetchable Limit Upper 32 Bits
028h
02Ch
I/O Limit Upper 16 Bits
I/O Base Upper 16 Bits
030h
Reserved
Capabilities Pointer
034h
Reserved
Reserved
038h
Bridge Control
Interrupt Pin
Interrupt Line
PM CAP ID
03Ch
040h-04Ch
050h
Power Management Capabilities
Next-item Pointer
PM Data (RSVD)
PMCSR_BSE
Power Management CSR
054h
Reserved
058h-06Ch
070h
MSI Message Control
Next-item Pointer
MSI CAP ID
MSI Message Address
074h
MSI Upper Message Address
078h
Reserved
Reserved
MSI Message Data
Next-item Pointer SSID/SSVID CAP ID
Subsystem Vendor ID
07Ch
080h
Subsystem ID
084h
Reserved
Next-item Pointer
088h-08Ch
090h
PCI Express Capabilities Register
Device Status
PCI Express Capability ID
Device Capabilities
Link Capabilities
Slot Capabilities
094h
Device Control
098h
09Ch
Link Status
Link Control
Slot Control
0A0h
A4h
Slot Status
A8h
Reserved
TI Proprietary
General Control
Reserved
0ACh-0C4h
0C8h-0D0h
0D4h
0D8h-0E8h
0ECh
General Slot Info
Reserved
LOs Idle Timeout
Reserved
0F0h-0FCh
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Table 4-51. Extended Configuration Space (Downstream Port)
Register Name
PCI Express Advanced Error Reporting Capabilities ID
Offset
100h
Next Capability Offset / Capability Version
Uncorrectable Error Status Register
Uncorrectable Error Mask Register
Uncorrectable Error Severity Register
Correctable Error Status Register
Correctable Error Mask
104h
108h
10Ch
110h
114h
Advanced Error Capabilities and Control
Header Log Register
118h
11Ch
120h
Header Log Register
Header Log Register
124h
Header Log Register
128h
Reserved
12Ch-FFCh
4.3.2 Vendor ID Register
This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to Texas
Instruments.
PCI register offset:
Register type:
00h
Read only
104Ch
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
4.3.3 Device ID Register
This 16-bit read-only register contains the device ID assigned by TI to the XIO3130. The value in this
register is the same for all downstream ports, as defined in the following table.
PCI register offset:
Register type:
02h
Read only
8233h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
4.3.4 Command Register
The Command register controls the way the downstream port bridge behaves on its primary interface; i.e.,
the internal PCI bus between the upstream and downstream ports.
PCI register offset:
Register type:
04h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Table 4-52. Bit Descriptions – Command Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
INTx disable. This bit is used to enable device-specific INTx interrupts. The XIO3130
15:11
RSVD
r
downstream ports can generate INTx interrupts due to PCI Hot Plug events. The XIO3130
forwards INTx messages from downstream ports to the upstream port (see INTx Support
section) regardless of this bit.
10
9
INT_DISABLE
FBB_ENB
rw
r
Fast back-to-back enable. This bit does not apply to PCI-Express, so it returns zero when read.
SERR enable. The relevant error checking is unnecessary for the XIO3130 internal PCI bus.
When set, this bit enables the transmission by the primary interface of ERR_NONFATAL and
ERR_FATAL messages forwarded from the secondary interface. This bit does not affect
transmission of ERR_COR messages.
8
SERR_ENB
rw
7
6
STEP_ENB
PERR_ENB
r
Address/data stepping control. This bit does not apply to PCI-Express and is hardwired to 0.
Parity error response enable. This bit has no impact on hardware behavior. It is assumed that
the relevant error checking is unnecessary for the XIO3130 internal PCI bus.
rw
VGA palette snoop enable. The XIO3130 does not support VGA palette snooping, so this bit
returns zero when read.
5
VGA_ENB
r
Memory write and invalidate enable. This bit does not apply to PCI-Express, so it is hardwired to
zero.
4
3
MWI_ENB
SPECIAL
r
r
Special cycle enable. This bit does not apply to PCI-Express and is hardwired to zero.
Bus master enable. When set, the XIO3130 is enabled to initiate cycles on the downstream PCI
Express interface.
0 – Downstream PCI Express interface cannot initiate transactions. The XIO3130 must
disable response to memory and I/O transactions on the downstream interface.
2
MASTER_ENB
rw
1 – Downstream PCI Express interface can initiate transactions. The bridge can forward
memory and I/O transactions.
Memory response enable. Setting this bit enables the downstream port to respond to memory
transactions.
1
0
MEMORY_ENB
IO_ENB
rw
rw
I/O space enable. Setting this bit enables the downstream port to respond to I/O transactions.
4.3.5 Status Register
The Status register provides information about the downstream port’s primary interface, i.e., the internal
PCI bus between the upstream and downstream ports.
PCI register offset:
Register type:
06h
Read Only; Clear by a Write of One; Hardware Update
0010h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-53. Bit Descriptions – Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Detected parity error. This bit is set when the virtual internal PCI interface receives a
poisoned TLP. This bit is set regardless of the state of the Parity Error Response bit in the
Command register.
15
PAR_ERR
rcu
0 – No parity error detected.
1 – Parity error detected.
Signaled system error. This bit is set when the XIO3130 sends an ERR_FATAL or
ERR_NONFATAL message upstream and the SERR Enable bit in the Command register is
set.
14
13
SYS_ERR
MABORT
rcu
r
0 – No error signaled.
1 – ERR_FATAL or ERR_NONFATAL signaled.
Received master abort. This bit is hardwired to zero. It is assumed that the relevant error
checking is unnecessary for the XIO3130 internal PCI bus.
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Table 4-53. Bit Descriptions – Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Received target abort. This bit is hardwired to zero. It is assumed that the relevant error
checking is unnecessary for the XIO3130 internal PCI bus.
12
TABORT_REC
r
Signaled target abort. This bit is hardwired to zero. It is assumed that the relevant error
checking is unnecessary for the XIO3130 internal PCI bus.
11
TABORT_SIG
PCI_SPEED
r
r
10:9
DEVSEL timing. These bits are read only zero because they do not apply to PCI Express.
Master data parity error. This bit is set when the downstream port receives a poisoned
completion or poisons a write request on the internal virtual PCI bus. This bit is never set if
the parity error response enable bit in the Command register is clear.
8
DATAPAR
rcu
Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express
device and is hardwired to zero.
7
6
5
FBB_CAP
RSVD
r
r
r
Reserved. When read, this bit returns zero.
66-MHz capable. This bit does not have a meaningful context for a PCI Express device and is
hardwired to zero.
66MHZ
Capabilities list. This bit returns 1 when read, indicating that the XIO3130 supports additional
PCI capabilities.
4
CAPLIST
r
Interrupt status. This bit reflects the INTx interrupt status of the function. The XIO3130
forwards INTx messages from downstream ports to the upstream port.
3
INT_STATUS
RSVD
r
r
2:0
Reserved. When read, these bits return zeros.
4.3.6 Class Code and Revision ID Register
This read-only register categorizes the Base Class, Sub Class, and Programming Interface of the
XIO3130. The Base Class is 06h, which identifies the device as a bridge device. The Sub Class is 04h,
which identifies the function as a PCI-to-PCI bridge. The Programming Interface is 00h. In addition, the TI
chip revision is indicated in the lower byte (01h).
PCI register offset:
Register type:
08h
Read only
0604 0001h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 4-54. Bit Descriptions – Class Code and Revision ID Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Base class. This field returns 06h when read, which classifies the function as a bridge
device.
31:24
23:16
BASECLASS
r
Subclass. This field returns 04h when read, which specifically classifies the function as a
PCI-to-PCI bridge.
SUBCLASS
r
15:8
7:0
PGMIF
r
r
Programming interface. This field returns 00h when read.
Silicon revision. This field returns the silicon revision.
CHIPREV
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4.3.7 Cache Line Size Register
The Cache Line Size register is implemented by PCI Express devices as a read-write field for legacy
compatibility, but has no impact on any PCI Express device functionality.
PCI register offset:
Register type:
0Ch
Read/Write
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.8 Primary Latency Timer Register
This read-only register has no meaningful context for a PCI Express device, so it returns zeros when read.
PCI register offset:
Register type:
0Dh
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.9 Header Type Register
This read-only register indicates that this function has a Type 1 PCI header. Bit seven of this register is
zero, indicating that the XIO3130 downstream port PCI-to-PCI bridge is not a multifunction device.
PCI register offset:
Register type:
0Eh
Read only
01h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
4.3.10 BIST Register
Since the XIO3130 does not support a built-in self test (BIST), this read-only register returns the value 00h
when read.
PCI register offset:
Register type:
0Fh
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
90
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4.3.11 Primary Bus Number
This register specifies the bus number of the PCI bus segment for the downstream port primary interface
(i.e., the internal PCI bus).
PCI register offset:
Register type:
18h
Read/Write
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.12 Secondary Bus Number
This register specifies the bus number of the PCI bus segment for the downstream port secondary
interface (i.e., the PCI Express interface). The XIO3130 uses this register to determine how to respond to
a Type 1 configuration transaction.
PCI register offset:
Register type:
19h
Read/Write
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.13 Subordinate Bus Number
This register specifies the bus number of the highest number PCI bus segment that is downstream of the
XIO3130 downstream port. The XIO3130 uses this register to determine how to respond to a Type 1
configuration transaction.
PCI register offset:
Register type:
1Ah
Read/Write
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.14 Secondary Latency Timer Register
This register does not apply to PCI-Express, so it is hardwired to zero.
PCI register offset:
Register type:
1Bh
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
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4.3.15 I/O Base Register
This read/write register specifies the lower limit of the I/O addresses that the XIO3130 downstream port
forwards downstream.
PCI register offset:
Register type:
1Ch
Read/Write; Read Only
01h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Table 4-55. Bit Descriptions – I/O Base Register
BIT
FIELD NAME
IOBASE
ACCESS
DESCRIPTION
I/O base. This field defines the bottom address of the I/O address range that is used to
determine when to forward I/O transactions from one interface to the other. These bits
correspond to address bits [15:12] in the I/O address. The lower 12 bits are assumed to be 0.
The 16 bits that correspond to address bits [31:16] of the I/O address are defined in the I/O
Base Upper 16 Bits register.
7:4
3:0
rw
r
IOTYPE
I/O type. This field is read-only 01h, which indicates 32 bit I/O addressing support.
4.3.16 I/O Limit Register
This read/write register specifies the upper limit of the I/O addresses that the XIO3130 downstream port
forwards downstream.
PCI register offset:
Register type:
1Dh
Read/Write; Read Only
01h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Table 4-56. Bit Descriptions – I/O Limit Register
BIT
FIELD NAME
IOLIMIT
ACCESS
DESCRIPTION
I/O limit. This field defines the top address of the I/O address range that is used to determine
when to forward I/O transactions from one interface to the other. These bits correspond to
address bits [15:12] in the I/O address. The lower 12 bits are assumed to be FFFh. The 16
bits that correspond to address bits [31:16] of the I/O address are defined in the I/O Limit
Upper 16 Bits register.
7:4
3:0
rw
r
IOTYPE
I/O type. This field is read-only 01h, which indicates 32-bit I/O addressing support.
4.3.17 Secondary Status Register
The Secondary Status register provides information about the downstream port PCI Express interface.
PCI register offset:
Register type:
1Eh
Read Only; Clear by a Write of One; Hardware Update
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Table 4-57. Bit Descriptions – Secondary Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP
on the downstream port. This bit is set regardless of the state of the Parity Error Response bit
in the Bridge Control register.
15
PAR_ERR
rcu
0 – No parity error detected.
1 – Parity error detected.
Received System Error. This bit is set when the XIO3130 sends an ERR_FATAL or
ERR_NONFATAL message upstream and the SERR Enable bit in the Command register is set.
14
13
12
11
SYS_ERR
MABORT
rcu
rcu
rcu
rcu
0 – No error signaled.
1 – ERR_FATAL or ERR_NONFATAL signaled.
Received master abort. This bit is set when the downstream PCI Express interface of the
XIO3130 receives a completion with Unsupported Request Status.
0 – Unsupported Request not received.
1 – Unsupported Request received on.
Received target abort. This bit is set when the downstream PCI Express interface of the
XIO3130 receives a completion with Completer Abort Status.
TABORT_REC
TABORT_SIG
0 – Completer Abort not received.
1 - Completer Abort received.
Signaled target abort. This bit is set when the downstream PCI Express interface completes a
Request with Completer Abort Status.
0 – Completer Abort not signaled.
1 – Completer Abort signaled.
10:9
8
PCI_SPEED
DATAPAR
r
DEVSEL timing. These bits are hardwired to 00. These bits do not apply to PCI Express.
Master data parity error. This bit is set when the XIO3130 receives a poisoned completion or
poisons a write request on the downstream PCI Express interface. This bit is never set if the
parity error response enable bit in the Bridge Control register is clear.
rcu
7
6
FBB_CAP
RSVD
r
r
r
r
Fast back-to-back capable. This bit is hardwired to zero. This bit does not apply to PCI Express.
Reserved. When read, this bit returns zero.
5
66MHZ
RSVD
66-MHz capable. This bit is hardwired to zero. This bit does not apply to PCI Express.
Reserved. When read, these bits return zeros.
4:0
4.3.18 Memory Base Register
This read/write register specifies the lower limit of the memory addresses that the downstream port
forwards downstream.
PCI register offset:
Register type:
20h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-58. IBit Descriptions – Memory Base Register
BIT
FIELD NAME
MEMBASE
RSVD
ACCESS
DESCRIPTION
Memory base. This field defines the bottom address of the memory address range that is
used to determine when to forward memory transactions from one interface to the other.
These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are
assumed to be zero.
15:4
3:0
rw
r
Reserved. When read, these bits return zeros.
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4.3.19 Memory Limit Register
This read/write register specifies the upper limit of the memory addresses that the downstream port
forwards downstream.
PCI register offset:
Register type:
22h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-59. Bit Descriptions – Memory Limit Register
BIT
15:4
3:0
FIELD NAME
ACCESS
DESCRIPTION
Memory limit. This field defines the top address of the memory address range that is used to
determine when to forward memory transactions from one interface to the other. These bits
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to
be FFFFFh.
MEMLIMIT
RSVD
rw
r
Reserved. When read, these bits return zeros.
4.3.20 Pre-fetchable Memory Base Register
This read/write register specifies the lower limit of the pre-fetchable memory addresses that the
downstream port forwards downstream.
PCI register offset:
Register type:
24h
Read/Write; Read Only
0001h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 4-60. Descriptions – Pre-fetchable Memory Base Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Pre-fetchable memory base. This field defines the bottom address of the pre-fetchable
memory address range that is used to determine when to forward memory transactions from
one interface to the other. These bits correspond to address bits [31:20] in the memory
address. The lower 20 bits are assumed to be zero. The Pre-fetchable Base Upper 32 Bits
register is used to specify the bit [63:32] of the 64-bit pre-fetchable memory address.
15:4
3:0
PREBASE
rw
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for
this memory window.
64BIT
r
4.3.21 Pre-fetchable Memory Limit Register
This read/write register specifies the upper limit of the pre-fetchable memory addresses that the
downstream port forwards downstream.
PCI register offset:
Register type:
26h
Read/Write; Read Only
0001h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
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Table 4-61. Bit Descriptions – Pre-fetchable Memory Limit Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Pre-fetchable memory limit. This field defines the top address of the pre-fetchable memory
address range that is used to determine when to forward memory transactions from one
interface to the other. These bits correspond to address bits [31:20] in the memory address.
The lower 20 bits are assumed to be FFFFFh. The Pre-fetchable Limit Upper 32 Bits register
is used to specify the bit [63:32] of the 64-bit pre-fetchable memory address.
15:4
PRELIMIT
rw
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for
this memory window.
3:0
64BIT
r
4.3.22 Pre-fetchable Base Upper 32 Bits Register
This read/write register specifies the upper 32 bits of the Pre-fetchable Memory Base register.
PCI register offset:
Register type:
28h
Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-62. Bit Descriptions – Pre-fetchable Base Upper 32 Bits Register
BIT
31:0
FIELD NAME
ACCESS
DESCRIPTION
Pre-fetchable memory base upper 32 bits. This field defines the upper 32 bits of the bottom
address of the pre-fetchable memory address range that is used to determine when to forward
memory transactions downstream.
PREBASE
rw
4.3.23 Pre-fetchable Limit Upper 32 Bits Register
This read/write register specifies the upper 32 bits of the Pre-fetchable Memory Limit register.
PCI register offset:
Register type:
2Ch
Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-63. Descriptions – Pre-fetchable Limit Upper 32 Bits Register
BIT
31:0
FIELD NAME
ACCESS
DESCRIPTION
Pre-fetchable memory limit upper 32 bits. This field defines the upper 32 bits of the top address
of the pre-fetchable memory address range that is used to determine when to forward memory
transactions downstream.
PRELIMIT
rw
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4.3.24 I/O Base Upper 16 Bits Register
This read/write register specifies the upper 16 bits of the I/O Base register.
PCI register offset:
Register type:
30h
Read/Write
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-64. Bit Descriptions – I/O Base Upper 16 Bits Register
BIT
15:0
FIELD NAME
ACCESS
DESCRIPTION
I/O base upper 16 bits. This field defines the upper 16 bits of the bottom address of the I/O
address range that is used to determine when to forward I/O transactions downstream.
IOBASE
rw
4.3.25 I/O Limit Upper 16 Bits Register
This read/write register specifies the upper 16 bits of the I/O Limit register.
PCI register offset:
Register type:
32h
Read/Write
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-65. Bit Descriptions – I/O Limit Upper 16 Bits Register
BIT
15:0
FIELD NAME
ACCESS
DESCRIPTION
I/O limit upper 16 bits. This field defines the upper 16 bits of the top address of the I/O
address range that is used to determine when to forward I/O transactions downstream.
IOLIMIT
rw
4.3.26 Capabilities Pointer Register
This read-only register provides a pointer into the PCI configuration header, which is where the PCI power
management block resides. Since the PCI power management registers begin at 50h, this register is
hardwired to 50h.
PCI register offset:
Register type:
34h
Read only
50h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
0
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4.3.27 Interrupt Line Register
This read/write register, which the system programs, indicates to the software which interrupt line that the
XIO3130 downstream port has assigned to it. The default value of this register is FFh, which indicates that
an interrupt line has not yet been assigned to the function. This register is essentially a scratch-pad
register; it has no effect on the XIO3130 itself.
PCI register offset:
Register type:
3Ch
Read/Write
FFh
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
4.3.28 Interrupt Pin Register
The Interrupt Pin register is read-only, which indicates that the XIO3130 downstream ports generate INTx
interrupts as follows:
•
•
•
Downstream port 0 on PCI Interrupt pin INTA (register value of 01h)
Downstream port 1 on PCI Interrupt pin INTA (register value of 01h)
Downstream port 2 on PCI Interrupt pin INTA (register value of 01h)
Interrupts originated by XIO3130 downstream ports are associated with the primary side of the
downstream port PCI-to-PCI bridge, and as a result are only passed through the upstream port PCI-to-PCI
bridge as described in PCI Express Base Specification Revision 1.1, Page 69, Table 2-13.
PCI register offset:
Register type:
3Dh
Read only
01h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
4.3.29 Bridge Control Register
The Bridge Control register provides extensions to the Command register that are specific to a bridge.
PCI register offset:
Register type:
3Eh
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-66. Bit Descriptions – Bridge Control Register
BIT
FIELD NAME
RSVD
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:12
11
10
9
r
r
r
r
r
r
DTSERR
DTSTATUS
SEC_DT
Discard timer SERR enable. This bit is hardwired to zero. This bit does not apply to PCI Express.
Discard timer status. This bit is hardwired to zero. This bit does not apply to PCI Express.
Secondary discard timer. This bit is hardwired to zero. This bit does not apply to PCI Express.
Primary discard timer. This bit is hardwired to zero. This bit does not apply to PCI Express.
Fast back-to-back enable. This bit is hardwired to zero. This bit does not apply to PCI Express.
8
PRI_DEC
FBB_EN
7
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Table 4-66. Bit Descriptions – Bridge Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Secondary bus reset. This bit is set when the software resets all devices downstream of the
XIO3130 downstream port. Setting this bit causes the downstream port to send a reset downstream
via a training sequence.
6
SRST
rw
0 – Downstream port not in Reset state
1 – Downstream port in Reset state
5
4
MAM
r
Master abort mode. This bit is hardwired to zero. This bit does not apply to PCI Express.
VGA 16-bit decode. This bit enables the XIO3130 downstream port to provide full 16-bit decoding
for VGA I/O addresses. This bit only has meaning if the VGA enable bit is set.
VGA16
rw
0 – Ignore address bits [15:10] when decoding VGA I/O addresses.
1 – Decode address bits [15:10] when decoding VGA I/O addresses.
VGA enable. This bit modifies the response by the XIO3130 downstream port to VGA-compatible
addresses. If this bit is set, the XIO3130 downstream port positively decodes and forwards the
following accesses on the primary interface to the secondary interface (and, conversely, blocks the
forwarding of these addresses from the secondary to primary interface):
•＝ Memory accesses in the range 000A 0000h to 000BFFFFh
•＝ I/O addresses in the first 64KB of the I/O address space (address bits [31:16] are 0000h.) and
where address bits [9:0] are in the range 3B0h to 3BBh or 3C0h to 3DFh (inclusive of ISA
address aliases; address bits [15:10] may possess any value and are not used in the
decoding).
If the VGA Enable bit is set, forwarding of VGA addresses is independent of the value of the ISA
Enable bit (located in the Bridge Control register), the I/O address range and memory address
ranges defined by the I/O Base and Limit registers, the Memory Base and Limit registers, and the
Pre-fetchable Memory Base and Limit registers of the bridge. Forwarding of VGA addresses is
qualified by the I/O Enable and Memory Enable bits in the Command register.
3
VGA
rw
0 – Do not forward VGA-compatible memory and I/O addresses from the primary to secondary
interface unless they are enabled for forwarding by the defined I/O and memory address
ranges.
1 – Forward VGA-compatible memory and I/O addresses from the primary interface to the
secondary interface (if the I/O Enable and Memory Enable bits are set) independent of the I/O
and memory address ranges and independent of the ISA Enable bit.
ISA enable. This bit modifies the response by the XIO3130 downstream port to ISA I/O addresses.
This bit applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and
are in the first 64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the
bridge blocks any forwarding from primary to secondary of I/O transactions addressing the last 768
bytes in each 1 KB block. In the opposite direction (secondary to primary), I/O transactions are
forwarded if they address the last 768 bytes in each 1K block.
2
ISA
rw
0 – Forward downstream all I/O addresses in the address range defined by the I/O Base and I/O
Limit registers.
1 – Forward upstream ISA I/O addresses in the address range defined by the I/O Base and I/O
Limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each 1 KB
block).
SERR enable. This bit controls the forwarding of system error events upstream from the secondary
interface to the primary interface. The XIO3130’s downstream port forwards system error events
upstream when:
•＝ This bit is set.
•＝ The SERR enable bit in the downstream port command register is set.
1
0
SERR_EN
PERR_EN
rw
rw
•＝ A nonfatal or fatal error condition is detected on the secondary interface (i.e., the PCI Express
interface).
0 – Disable the reporting of nonfatal errors and fatal errors.
1 – Enable the reporting of nonfatal errors and fatal errors.
Parity error response enable. For PCI Express, this bit controls responses to poisoned TLPs
received on the downstream port.
0 – Disable responses to poisoned TLPs.
1 – Enable responses to poisoned TLPs.
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4.3.30 Capability ID Register
This read-only register identifies the linked list item as the register for PCI power management. It returns
01h when read.
PCI register offset:
Register type:
50h
Read only
01h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
4.3.31 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130 downstream port. This register reads 70h, which points to the MSI Capabilities registers.
PCI register offset:
Register type:
51h
Read only
70h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
1
1
1
0
0
0
0
4.3.32 Power Management Capabilities Register
This register indicates the capabilities of the XIO3130 downstream port related to PCI power
management.
PCI register offset:
Register type:
52h
Read only
XXX3h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
y
1
1
x
1
1
x
0
0
y
0
0
0
0
1
1
Table 4-67. Bit Descriptions – Power Management Capabilities Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
PME support. This 5-bit field indicates the power states from which the downstream port
may assert PME. These five bits return a value of 5’by11x1, which indicates that the
XIO3130 can assert PME from D0, D2, D3hot, maybe D3cold (i.e., depending on y), and
maybe D1 (i.e., depending on x). The bit that defines this power state for D3cold (i.e., y) is
controlled by the AUX_PRESENT bit in the Global Chip Control register. The bit defining
this power state for D1 (i.e., x) is controlled by the D1_SUPPORT bit in the Global Switch
Control register.
15:11
PME_SUPPORT
r
This bit returns a 1 when read, which indicates that the function supports the D2 device
power state.
10
9
D2_SUPPORT
D1_SUPPORT
r
r
This bit indicates whether the function supports the D1 device power state. This bit is
controlled by the D1_SUPPORT bit in the Global Switch Control register. The default
value x is controlled by the default value for the D1_SUPPORT bit in the Global Switch
Control register.
3.3-VAUX auxiliary current requirements. This field reads 3’b00y, i.e., either 3’b001 or
3’b000, depending on the AUX_PRESENT bit in the Global Chip Control register. 3’b001
indicates 55 mA maximum current in D3cold when PME is enabled, according to PCI
Power Management Specification Revision 1.2, Section 3.2.3, page 26.
8:6
AUX_CURRENT
r
Device-specific initialization. This bit returns 0 when read, which indicates that the
XIO3130 does not require special initialization beyond the standard PCI configuration
header before a generic class driver is able to use it.
5
4
DSI
r
r
RSVD
Reserved. When read, this bit returns zero.
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Table 4-67. Bit Descriptions – Power Management Capabilities Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
PME clock. This bit returns zero, which indicates that the PCI clock is not needed to
generate PME.
3
PME_CLK
r
Power management version. This field returns 3’b011, which indicates Revision 1.2
compatibility.
2:0
PM_VERSION
r
4.3.33 Power Management Control/Status Register
This register determines and changes the current power state of the downstream port.
PCI register offset:
Register type:
54h
Read/Write; Read Only; Clear by a Write of One; Hardware Update; Sticky
0008h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Table 4-68. Bit Descriptions – Power Management Control/Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
PME status. PME events are generated due to PCI Hot Plug events. This bit reflects the
PME status regardless of the state of PME_EN.
0 – No PME event pending
1 – PME event pending
15
PME_STAT
rcuh
This bit is reset with GRST.
Data scale. This 2-bit field returns 0s when read since the XIO3130 does not use the Data
register.
14:13
12:9
DATA_SCALE
DATA_SEL
r
r
Data select. This 4-bit field returns 0s when read since the XIO3130 does not use the Data
register.
PME enable. This bit enables PME/WAKE signaling, even though the XIO3130 never
generates WAKE .
0 – Disable PME signaling.
8
PME_EN
rwh
1 – Enable PME signaling.
This bit is reset with GRST.
7:4
3
RSVD
NO_SOFT_RST
RSVD
r
r
r
Reserved. When read, these bits return zeros.
No Soft Reset. This bit controls whether the transition from D3hot to D0 resets the state
according to PCI Power Management Specification Revision 1.2. This bit is hardwired to
1’b1.
0 – D3hot to D0 transition causes reset.
1 – D3hot to D0 transition does not cause reset.
Reserved. When read, this bit returns zero.
2
Power state. This 2-bit field is used to determine the current power state of the function and
to set the function into a new power state. This field is encoded as follows:
00 = D0
01 = D1
10 = D2
11 = D3hot
1:0
PWR_STATE
rw
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4.3.34 Power Management Bridge Support Extension Register
This read-only register is used to indicate to the host software what the state of the downstream port’s
secondary bus will be when the downstream port is placed in D3.
PCI register offset:
Register type:
56h
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4-69. Bit Descriptions – PM Bridge Support Extension Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Bus power/Clock control enable. This bit is read-only zero. This bit does not apply to PCI
Express.
7
BPCC
r
6
BSTATE
RSVD
r
r
B2/B3 support. This bit is read-only zero. This bit does not apply to PCI Express.
Reserved. When read, these bits return zeros.
5:0
4.3.35 Power Management Data Register
The read-only register is not applicable to the XIO3130 and returns 00h when read.
PCI register offset:
Register type:
57h
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.36 MSI Capability ID Register
This read-only register identifies the linked list item as the register for Message Signaled Interrupts
Capabilities. The register returns 05h when read.
PCI register offset:
Register type:
70h
Read only
05h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
1
4.3.37 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130. This register reads 80h, which points to the Subsystem ID and Subsystem Vendor ID
Capabilities registers.
PCI register offset:
Register type:
71h
Read only
80h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
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4.3.38 MSI Message Control Register
This register is used to control the sending of MSI messages.
PCI register offset:
Register type:
72h
Read/Write; Read Only
0080h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Table 4-70. Bit Descriptions – MSI Message Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:8
RSVD
r
64-bit message capability. This bit is read-only 1, which indicates that the XIO3130 downstream
port supports 64-bit MSI message addressing.
7
64CAP
r
Multiple message enable. This field indicates the number of distinct messages that the XIO3130
downstream port is allowed to generate.
000 – 1 message
001 – 2 messages
010 – 4 messages
011 – 8 messages
100 – 16 messages
101 – 32 messages
110 – Reserved
6:4
MM_EN
rw
111 – Reserved
Multiple message capabilities. This field indicates the number of distinct messages that the
XIO3130 downstream port can generate. This field is read-only 000, which indicates that the
downstream port can signal one interrupt.
3:1
0
MM_CAP
MSI_EN
r
MSI Enable. This bit is used to enable MSI interrupt signaling. The software must enable MSI
signaling for the XIO3130 downstream port to send MSI messages.
rw
0 – MSI signaling is prohibited
1 – MSI signaling is enabled
4.3.39 MSI Message Address Register
This register contains the lower 32 bits of the address that an MSI message shall be written to when an
interrupt is to be signaled.
PCI register offset:
Register type:
74h
Read/Write; Read Only
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-71. Bit Descriptions – MSI Message Address Register
BIT
FIELD NAME
ADDRESS
RSVD
ACCESS
DESCRIPTION
31:2
1:0
rw
r
System-specified message address.
Reserved. When read, these bits return zeros.
102
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4.3.40 MSI Message Upper Address Register
This read/write register contains the upper 32 bits of the address that a MSI message shall be written to
when an interrupt is to be signaled. If this register is 0000 0000h, 32-bit addressing is used in the MSI
Message packet. Otherwise, 64-bit addressing is used.
PCI register offset:
Register type:
78h
Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.3.41 MSI Message Data Register
This register contains the data that the software programmed the device to send when it sends an MSI
message.
PCI register offset:
Register type:
7Ch
Read/Write
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-72. Bit Descriptions – MSI Data Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
System-specific message. This field contains the portion of the message that the XIO3130 can
never modify.
15:4
MSG
rw
Message number. This portion of the message field may be modified to contain the message
number if multiple messages are enabled. Since the XIO3130 downstream port only generates
one MSI type, the XIO3130 hardware does not modify these bits.
3:0
MSG_NUM
rw
4.3.42 Capability ID Register
This read-only register identifies the linked list item as the register for Subsystem ID and Subsystem
Vendor ID Capabilities. This register returns 0Dh when read.
PCI register offset:
Register type:
80h
Read only
0Dh
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
1
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4.3.43 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130 downstream port. This register reads 90h, which points to the PCI Express Capabilities registers.
PCI register offset:
Register type:
81h
Read only
90h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
4.3.44 Subsystem Vendor ID Register
This register is used for system and option card identification and may be required for certain operating
systems. This read-only register is a direct reflection of the upstream port’s Subsystem Access register,
which is read/write and is initialized through the EEPROM (if present).
PCI register offset:
Register type:
84h
Read only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.3.45 Subsystem ID Register
This register is used for system and option card identification and may be required for certain operating
systems. This read-only register is a direct reflection of the upstream port’s Subsystem Access register,
which is read/write and is initialized through the EEPROM (if present).
PCI register offset:
Register type:
86h
Read only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.3.46 PCI Express Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express Capabilities. When
read, this register returns 10h.
PCI register offset:
Register type:
90h
Read only
10h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
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4.3.47 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130 downstream port. This register reads 00h, which indicates that no additional capabilities are
supported.
PCI register offset:
Register type:
91h
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.48 PCI Express Capabilities Register
This register indicates the capabilities of the downstream port of the XIO3130 related to PCI Express.
PCI register offset:
Register type:
92h
Read only
0061h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
Table 4-73. Bit Descriptions – PCI Express Capabilities Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:14
RSVD
r
Interrupt message number. This field is used for MSI support and is implemented as read-only
zero.
13:9
INT_NUM
r
Slot implemented. This bit indicates whether the port is connected to a slot connector (e.g., for
PCI Express, ExpressCard™ or other add-in cards). This field can be programmed by writing to
the General Control register.
8
SLOT
r
0 – Port not connected to a slot
1 – Port connected to a slot
Device/Port type. This read-only field returns 0110b, which indicates that the device is a
downstream port of a PCI Express XIO3130.
7:4
3:0
DEV_TYPE
VERSION
r
r
Capability version. This field returns 0001b, which indicates revision 1 of the PCI Express
capability.
4.3.49 Device Capabilities Register
The Device Capabilities register indicates the device-specific capabilities of the XIO3130 downstream port.
PCI register offset:
Register type:
94h
Read Only; Hardware Update
0000 8XX1h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
u
u
u
v
v
v
0
0
0
0
0
1
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Table 4-74. Bit Descriptions – Device Capabilities Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
31:28
RSVD
r
Captured slot power limit scale. This field is only applicable to upstream ports and is
hardwired to zero.
27:26
CSPLS
ru
Captured slot power limit value. This field is only applicable to upstream ports and is
hardwired to zero.
25:18
17:16
15
CSPLV
RSVD
RBER
ru
r
Reserved. When read, these bits return zeros.
Role-based error reporting. This bit is set to 1b to indicate support for role-based error
reporting.
r
Power indicator present. This bit indicates whether the XIO3130 has a power indicator. This
bit is hardwired to zero.
14
13
PIP
AIP
r
r
Attention indicator present. This bit indicates whether the XIO3130 has an attention
indicator. This bit is hardwired to zero.
Attention button present. This bit indicates whether the XIO3130 has a power button. This bit
is hardwired to zero.
12
11:6
5
ABP
RSVD
ETFS
r
r
r
Reserved. When read, these bits return zeros.
Extended tag field supported. This bit indicates the size of the tag field supported. This bit is
hardwired to 0, which indicates support for 5-bit tag fields.
Phantom functions supported. This field is read-only 00b, which indicates that function
numbers are not used for phantom functions.
4:3
2:0
PFS
r
r
Max payload size supported. This field indicates the maximum payload size that the device
can support for TLPs. This field is encoded as 001b, which indicates that the maximum
payload size for a TLP is 256 bytes.
MPSS
4.3.50 Device Control Register
The Device Control register controls PCI Express device-specific parameters.
PCI register offset:
Register type:
98h
Read/Write; Read Only
2000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-75. Bit Descriptions – Device Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, this bit returns zero.
15
RSVD
r
Max read request size. This field is programmed by the host software to set the maximum
size of a read request that the XIO3130 can generate. The XIO3130 uses this field in
conjunction with the Cache Line Size register to determine how much data to fetch on a
read request. This field is encoded as:
000 – 128B
001 – 256B
14:12
MRRS
rw
010 – 512B (default)
011 – 1024B
100 – 2048B
101 – 4096B
110 – Reserved
111 – Reserved
Enable no snoop. Since the XIO3130 does not support setting the no-snoop attribute, this bit
is read-only zero.
11
10
ENS
r
r
Auxiliary power PM enable. This bit is read-only zero, since the XIO3130 requires a minimal
amount of AUX power when PME is disabled.
APPE
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Table 4-75. Bit Descriptions – Device Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Phantom function enable. Since the XIO3130 part does not support phantom functions, this
bit is read-only zero.
9
PFE
r
Extended tag field enable. Since the XIO3130 part does not support extended tags, this bit
is read-only zero.
8
ETFE
r
Max payload size. This field is programmed by the host software to set the maximum size of
posted writes or read completions that the XIO3130 can initiate. This field is encoded as:
000 – 128B (default)
001 – 256B
010 – 512B
7:5
MPS
rw
011 – 1024B
100 – 2048B
101 – 4096B
110 – Reserved
111 – Reserved
Enable relaxed ordering. Since the XIO3130 part does not support relaxed ordering, this bit
is read-only zero.
4
3
ERO
r
Unsupported request reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_NONFATAL messages to the root complex when an unsupported request is received
by the downstream port.
URRE
rw
0 – Do not report unsupported requests to the root complex.
1 – Report unsupported requests to the root complex.
Fatal error reporting enable. If this bit is set, the XIO3130 is enabled to send ERR_FATAL
messages to the root complex when a system error event occurs.
2
1
0
FERE
NFERE
CERE
rw
rw
rw
0 – Do not report fatal errors to the root complex.
1 – Report fatal errors to the root complex.
Nonfatal error reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_NONFATAL messages to the root complex when a system error event occurs.
0 – Do not report nonfatal errors to the root complex.
1 – Report nonfatal errors to the root complex.
Correctable error reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_CORR messages to the root complex when a system error event occurs.
0 – Do not report correctable errors to the root complex.
1 – Report correctable errors to the root complex.
4.3.51 Device Status Register
The Device Status register controls PCI Express device-specific parameters.
PCI register offset:
Register type:
9Ah
Read Only; Clear by a Write of One; Hardware Update
00X0h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
Table 4-76. Bit Descriptions – Device Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:6
RSVD
r
Transaction pending. This bit is set when the XIO3130 downstream port has issued a
non-posted transaction that has not been completed yet.
5
PEND
ru
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Table 4-76. Bit Descriptions – Device Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
AUX power detected. This bit indicates that AUX power is present. This bit is a direct
reflection of the AUX_PRSNT bit in the Global Chip Control register, and it has the same
default value.
4
APD
ru
0 – No AUX power detected.
1 – AUX power detected.
Unsupported Request detected. This bit is asserted when an Unsupported Request error is
detected (i.e., when a request is received that results in sending a completion with an
Unsupported Request status). Errors are logged in this bit regardless of whether error
reporting is enabled in the Device Control register.
3
URD
rcu
Fatal error detected. This bit is set by the XIO3130 when a fatal error is detected. Errors
are logged in this bit regardless of whether error reporting is enabled in the Device Control
register.
2
1
0
FED
NFED
CED
rcu
rcu
rcu
Nonfatal error detected. This bit is set by the XIO3130 when a nonfatal error is detected.
Errors are logged in this bit regardless of whether error reporting is enabled in the Device
Control register.
Correctable error detected. This bit is set by the XIO3130 when a correctable error is
detected. Errors are logged in this bit regardless of whether error reporting is enabled in
the Device Control register.
4.3.52 Link Capabilities Register
The Link Capabilities register indicates the link-specific capabilities of the XIO3130 downstream port.
PCI register offset:
Register type:
9Ch
Read only
0XXX XC11h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
x
x
0
0
0
w
w
1
y
y
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
y
z
z
z
1
1
0
0
0
0
0
1
0
0
0
1
Table 4-77. Bit Descriptions – Link Capabilities Register
BIT
FIELD NAME
PORT_NUM
RSVD
ACCESS
DESCRIPTION
Port number. This field indicates the port number for the PCI Express link. This field is set to
8’h01 for downstream port 0, 8’h02 for downstream port 1, and 8’h03 for downstream port 2.
31:24
23:21
r
r
Reserved. When read, these bits return zeros.
Data link layer link active reporting capable. This bit indicates whether this slot is capable of
reporting whether the link is active. This field can be programmed by writing to the General
Control register. The default state w is that of the LINK_ACT_RPT_CAP field in the General
Control register.
20
19
DLL_LARC
SDERC
r
r
0 – Incapable of link active reporting
1 – Capable of link active reporting
Surprise down error reporting capable. This bit indicates whether this slot is capable of
detecting and reporting a surprise down error condition. This field can be programmed by
writing to the LINK_ACT_RPT_CAP field in the General Control register. The default state w is
that of the LINK_ACT_RPT_CAP field in the General Control register.
0 – Incapable of detecting and reporting a surprise down error condition
1 – Capable of detecting and reporting a surprise down error condition
Clock power management. This bit is 1b, which indicates support for CLKREQ.
18
CPM
r
r
L1 exit latency. This field indicates the time required to transition from the L1 state to the L0
state. This field is a direct reflection of the Downstream Ports Link PM Latency register
L1_EXIT_LAT field, which is a read/write field that is loaded from EEPROM (if present). The
default value of this field is yyy, which is the same as the default value of the Link PM Latency
register L1_EXIT_LAT field.
17:15
L1_LATENCY
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Table 4-77. Bit Descriptions – Link Capabilities Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
L0s exit latency. This field indicates the time required to transition from the L0s state to the L0
state. This field is a direct reflection of the Downstream Ports Link PM Latency register
L0S_EXIT_LAT field, which is a read/write field that is loaded from EEPROM (if present). The
default value of this field is zzz, which is the same as the default value of the Link PM Latency
register L0S_EXIT_LAT field.
14:12
L0S_LATENCY
r
Active State Link PM support. This field reads 11b, which indicates that the XIO3130 supports
both L0s and L1 for Active State Link PM.
11:10
9:4
ASLPMS
MLW
r
r
r
Maximum link width. This field is encoded 000001b to indicate that the XIO3130 downstream
port supports only an x1 PCI Express link.
Maximum link speed. This field is encoded 0001b to indicate that the XIO3130 downstream
port supports a maximum link speed of 2.5 Gb/s.
3:0
MLS
4.3.53 Link Control Register
The Link Control register is used to control link-specific behavior.
PCI register offset:
Register type:
A0h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-78. Bit Descriptions – Link Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:9
RSVD
r
Clock power management enable. When CLKREQ support is enabled, the EP_LI_LAT field in
the Downstream Ports Link PM Latency register increases due to link PLL locking requirements.
8
CPM_EN
rw
0 – Disables CLKREQ support on downstream port
1 – Enables CLKREQ support on downstream port
Extended synch. This bit is used to force the XIO3130 downstream port to extend the
transmission of FTS ordered sets and an extra TS2 when exiting from L1 before entering to L0.
7
6
ES
rw
rw
0 – Normal synch
1 – Extended synch
Common clock configuration. This bit is set when a common clock is provided to both ends of
the downstream port’s PCI Express link. This bit can be used to change the L0s and L1 exit
latencies.
CCC
0 – Reference clock is asynchronous
1 – Reference clock is synchronous
Retrain link. This bit initiates link retraining on the downstream port. This bit always returns 0b
when read.
5
4
RL
LD
rw
rw
0 – Do not initiate link retraining
1 – Initiate link retraining
Link disable. This bit disables the link. Writes to this bit are immediately reflected in the value
read from the bit, regardless of the actual link state.
0 – Link enabled
1 – Link disabled
Read completion boundary. This bit specifies the minimum size read completion packet that the
XIO3130 can send when breaking a read request into multiple completion packets. This field is
not applicable to XIO3130; i.e., the XIO3130 does not break up completion packets and is
hardwired to zero.
3
2
RCB
r
r
0 – 64 bytes
1 – 128 bytes
RSVD
Reserved. When read, this bit returns zero.
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Table 4-78. Bit Descriptions – Link Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Active State Link PM Control. This field is used to enable and disable active state PM.
00 – Active State PM disabled
1:0
ASLPMC
rw
01 – L0s entry enabled
10 – Reserved
11 – L0s and L1 entry enabled
4.3.54 Link Status Register
The Link Status register indicates the current state of the PCI Express Link.
PCI register offset:
Register type:
A2h
Read Only; Hardware Update
XX11h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
x
0
0
0
0
0
1
0
0
0
1
Table 4-79. Bit Descriptions – Link Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:14
RSVD
r
Data link layer active. When the DLL_LARC field in the Link Capabilities register is asserted,
this field returns the value of the following comparison: (Link_State == DL_Active). This field
returns zero when the DLL_LARC field in the Link Capabilities register is de-asserted.
13
DLL_ACTV
r
Slot clock configuration. This bit reflects the reference clock configurations and is read-only 1,
indicating that a 100 MHz common clock reference is used.
12
11
SCC
LT
r
Link training in progress. The hardware automatically clears this bit when the LTSSM exits the
Configuration/Recovery state.
ru
10
9:4
3:0
UNDEF
NLW
LS
r
r
r
Undefined. The value read from this bit is undefined.
Negotiated link width. This field is read-only 000001b, which indicates that the lane width is x1.
Link speed. This field is read-only 0001b, which indicates that the link speed is 2.5 Gb/s.
4.3.55 Slot Capabilities Register
The Slot Capabilities register indicates the slot-specific capabilities of the downstream port.
PCI register offset:
Register type:
A4h
Read/Write; Read Only; Hardware Update
0000 0060h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
Table 4-80. Bit Descriptions – Slot Capabilities Register
BIT
31:19
FIELD NAME
ACCESS
DESCRIPTION
Physical slot number. This field indicates a system-dependent physical slot number that is
unique to each slot in the system. This field can be programmed by writing to the General
Slot Info register.
SLOT_NUM
r
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Table 4-80. Bit Descriptions – Slot Capabilities Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Electromechanical interlock present. This bit indicates whether an electromechanical
interlock is implemented on the chassis for this slot. This bit can be programmed by writing
to the General Control register.
18
EMILP
ru
0 – Electromechanical interlock not present.
1 – Electromechanical interlock present.
No command completed support. This bit is hardwired to zero, which indicates that
command completed software notification (i.e., interrupt generation) is always supported.
17
NCCS
SPLS
ru
0 – Command completed support is provided.
1 – Command completed support is not provided.
Slot power limit scale. This field Indicates the scale that is used for the slow power limit
value. This field may be written only once after any given PERST; the effect when written is
to cause the port to send the Set_Slot_Power_Limit message.
00 – 1.0x
16:15
rw
01 – 0.1x
10 – 0.01x
11 – 0.001x
This field is loaded from EEPROM (if present) and reset with PERST.
Slot power limit value. When multiplied by the SPLS field (see previous row in this table), this
field indicates the maximum power in watts that can be consumed by a card plugged into a
slot attached to this port,. This field may be written only once after any given PERST; the
effect when written is to cause the port to send the Set_Slot_Power_Limit message.
14:7
SPLV
rw
This field is loaded from EEPROM (if present) and reset with PERST.
PCI Hot Plug capable. This bit indicates whether this slot is capable of supporting PCI Hot
Plug operations. The default setting of this register is defined by the DPSTRP[2,0] strapping.
This bit can be programmed by writing to the General Control register bit 14, which is
SLOT_HPC. For more information on the General Control register, see section 3.3.61.
6
HP_CAPABLE
r
0 – Incapable of supporting PCI Hot Plug operations
1 – Capable of supporting PCI Hot Plug operations
PCI Hot Plug surprise. This bit indicates whether a device present in this slot can be
removed from the system without any prior notification. This bit can be programmed by
writing to the General Control register bit 13, which is SLOT_HPS. For more information on
the General Control register, see section 3.3.61.
5
4
3
2
HP_SURPRISE
r
r
r
r
0 – No device present that can be removed by surprise
1 – Device present that can be removed by surprise
Power indicator present. This bit indicates whether a power indicator is implemented on the
chassis for this slot. This bit can be programmed by writing to the General Control register bit
12, which is SLOT_PIP. For more information on the General Control register, see section
3.3.61.
PIP
0 – Power indicator not present
1 – Power indicator present
Attention indicator present. This bit indicates whether an attention indicator is implemented
on the chassis for this slot. This bit can be programmed by writing to the General Control
register bit 11, which is SLOT_AIP. For more information on the General Control register,
see section 3.3.61.
AIP
0 – Attention indicator not present
1 – Attention indicator present
Manual retention latch sensor present. This bit indicates whether a manual retention latch
(MRL) sensor is implemented on the chassis for this slot. This bit can be programmed by
writing to the General Control register bit 10, which is SLOT_MRLSP. For more information
on the General Control register, see section 3.3.61.
MRLSP
0 – MRL sensor not present
1 – MRL sensor present
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Table 4-80. Bit Descriptions – Slot Capabilities Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Power controller present. This bit indicates whether a power controller is implemented for
this slot. The default setting of this register is defined by the DPSTRP[2,0] strapping. This bit
can be programmed by writing to the General Control register bit 9, which is SLOT_PCP. For
more information on the General Control Register, see section 3.3.61. If this bit is zero, then
the PWRON_EC output signal, which may go to a pin, is forced asserted; there is no such
effect on the PWRON output signal.
1
PCP
r
0 – Power controller not present
1 – Power controller present
Attention button present. This bit indicates whether an attention button is implemented on the
chassis for this slot. This bit can be programmed by writing to the General Control register bit
8, which is SLOT_ABP. For more information on the General Control register, see section
3.3.61.
0
ABP
r
0 – Attention button not present
1 – Attention button present
4.3.56 Slot Control Register
The Slot Control register controls slot-specific parameters.
PCI register offset:
Register type:
A8h
Read/Write; Read Only
07C0h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
Table 4-81. Bit Descriptions – Slot Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:13
RSVD
r
Data link layer state changed enable. This bit enables software notification (i.e., interrupts) due to
an assertion of the DLLSC field in the Slot Status register.
12
DLLSC_EN
rw
0 – DLLSC interrupts disabled
1 – DLLSC interrupts enabled
Electromechanical interlock control. When read, this bit returns zero. A write of 1’b0 has no effect.
If the EMILP field in the Slot Capabilities register is asserted, then a write of 1’b1 causes a 100 ms
high-going pulse on the EMIL_CTL output pin; otherwise, the write has no effect.
11
10
EMIL_CTL
PC_CTL
rw
rw
Power controller control. When read, this bit indicates the current state of power applied to the
slot. Writes set the power state of the slot and control the PWR_ON pin. When this bit transitions
from power on to power off, and the HP_PME_MSG_EN bit in the Global Switch Control register
is asserted, a PME_Turn_Off message is sent and the PWRON output pin gets de-asserted only
after a PME_TO_Ack is received or after a 100 ms timeout.
0 – Power on
1 – Power off
Power indicator control. When read, this field indicates the current state of the power indicator.
Writes set the power indicator state. When writes cause this field to change, the appropriate
POWER_INDICATOR_* messages are sent. This bit controls the PWR_LED output pin.
00b – Reserved
01b – On
9:8
PI_CTL
rw
10b – Blinking
11b – Off
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Table 4-81. Bit Descriptions – Slot Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Attention indicator control. When read, this field indicates the current state of the attention
indicator. Writes set the attention indicator state. When writes cause this field to change, the
appropriate ATTENTION_INDICATOR_* messages are sent. This bit controls the ATN_LED
output pin.
7:6
AI_CTL
rw
00b – Reserved
01b – On
10b – Blinking
11b – Off
PCI Hot Plug interrupt enable. This bit enables generation of PCI Hot Plug interrupts on enabled
PCI Hot Plug events.
5
4
HPI_EN
CCI_EN
rw
rw
0 – PCI Hot Plug interrupts disabled
1 – PCI Hot Plug interrupts enabled
Command-completed interrupt enable. This bit enables generation of an interrupt upon completion
of a command by the PCI Hot Plug Controller. HPI_EN, and MSI_EN (see MSI Message Control
register) must also be enabled for interrupt generation. A Hot Plug Controller Command is defined
as a state change in any of the *_CTL bits in this register (i.e., software writes).
0 – Command-completed interrupts disabled
1 – Command-completed interrupts enabled
Presence detect changed enable. This bit enables generation of a
•＝＝＝＝＝＝＝＝＝ PCI Hot Plug interrupt
•＝＝＝＝＝＝＝＝＝ PME
when the PDC bit in the Slot Status register is asserted.
0 – Disabled
3
2
1
PDC_EN
MRLSC_EN
PFD_EN
rw
rw
rw
1 – Enabled
HPI_EN and MSI_EN (see MSI Message Control register) must also be enabled for interrupt
generation. PME_EN must also be enabled for PME signaling during D1, D2, or D3hot. For more
information, see section 6.7.7 in PCI Express Base Specification Revision 1.0a.
Manual retention latch sensor changed enable. This bit enables generation of a
•＝＝＝＝＝＝＝＝＝ PCI Hot Plug interrupt
•＝＝＝＝＝＝＝＝＝ PME
when the MRLSC bit in the Slot Status register is asserted.
0 – Disabled
1 – Enabled
HPI_EN and MSI_EN (see MSI Message Control register) must also be enabled for interrupt
generation. PME_EN must also be enabled for PME signaling during D1, D2, or D3hot. For more
information, see section 6.7.7 in PCI Express Base Specification Revision 1.0a.
Power fault detected enable. This bit enables generation of a
•＝＝＝＝＝＝＝＝＝ PCI Hot Plug interrupt
•＝＝＝＝＝＝＝＝＝ PME
when the PFD bit in the Slot Status register is asserted.
0 – Disabled
1 – Enabled
HPI_EN and MSI_EN (see MSI Message Control register) must also be enabled for interrupt
generation. PME_EN must also be enabled for PME signaling during D1, D2, or D3hot. For more
information, see section 6.7.7 in PCI Express Base Specification Revision 1.0a.
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Table 4-81. Bit Descriptions – Slot Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Attention button pressed enable. This bit enables generation of a
•＝＝＝＝＝＝＝＝＝ PCI Hot Plug interrupt
•＝＝＝＝＝＝＝＝＝ PME
when the ABP bit in the Slot Status register is asserted.
0 – Disabled
0
ABP_EN
rw
1 – Enabled
HPI_EN and MSI_EN (see Table 3 21) must also be enabled for interrupt generation. PME_EN
must also be enabled for PME signaling during D1, D2, or D3hot. For more information, see
section 6.7.7 in PCI Express Base Specification Revision 1.0a.
4.3.57 Slot Status Register
The Slot Status register provides information about slot-specific parameters.
PCI register offset:
Register type:
AAh
Read Only; Clear by a Write of One; Hardware Update
0010h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Table 4-82. Bit Descriptions – Slot Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:9
RSVD
r
Data link layer state changed. This bit is set when the DLL_ACTV field in the Link Status
register changes state. A write of 1’b1 clears this field. A write of 1’b0 has no effect.
8
DLLSC
ruc
Electromechanical interlock status. If an electromechanical interlock is implemented for the
slot, this field indicates the current status of the electromechanical interlock.
7
6
5
4
EMIL_STAT
r
0 – Electromechanical interlock disengaged
1 – Electromechanical interlock engaged
Presence detect state. This bit indicates whether a card is present in a slot. If the
SLOT_PRSNT bit in the General Control register is de-asserted, this bit always reads back
asserted. If the SLOT_PRSNT bit is asserted, this bit indicates the state of a de-bounced
derivative of the PRSNT input pin.
PDS
MRLSS
CC
ru
0 – Card presence detection output de-asserted (i.e., slot empty)
1 – Card presence detection output asserted (i.e., card present in slot)
Manual retention latch sensor state. This bit indicates the state of a de-bounced derivative of
the MRLS_DET input pin.
ru
0 – MRLS_DET pin asserted (i.e., MRL closed)
1 – MRLS_DET pin de-asserted (i.e., MRL open)
Command completed. This bit is set when the PCI Hot Plug Controller is ready to accept
another command; it does not ensure that the previous command is completely finished. A
Hot Plug controller command is defined as a state change in any of the *_CTL bits in the Slot
Control register (i.e., software writes).
ruc
0 – PCI Hot Plug controller is not ready to accept a new command.
1 – PCI Hot Plug controller is ready to accept a new command.
Presence detect changed. This bit indicates whether the state of the PDS bit has changed.
0 – PDS bit has not changed.
3
2
PDC
ruc
ruc
1 – PDS bit has changed.
MRL sensor changed. This bit indicates whether the state of the MRLSS bit has changed.
0 – MRLSS bit has not changed.
MRLSC
1 – MRLSS bit has changed.
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Table 4-82. Bit Descriptions – Slot Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Power fault detected. This bit indicates the state of the PWRFLT pin.
0 – PWRFLT pin de-asserted (no power fault at slot).
1 – PWRFLT pin asserted (power fault at slot).
1
PFD
ruc
Attention button pressed. This bit indicates a de-asserted-to-asserted transition on a
de-bounced derivative of the ATN_BTN pin.
0
ABP
ruc
0 – Attention button not pressed
1 – Attention button pressed
4.3.58 TI Proprietary Register
This read/write TI proprietary register is located at offset C8h and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
If an EEPROM is used to load configuration registers, the value loaded for this register must be 0000
0001h.
PCI register offset:
Register type:
C8h
Read/Write
xxxx 0001
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4.3.59 TI Proprietary Register
This read/write TI proprietary register is located at offset CCh and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
If an EEPROM is used to load configuration registers, the value loaded for this register must be 0000
0000h.
PCI register offset:
Register type:
CCh
Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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4.3.60 TI Proprietary Register
This read/write TI proprietary register is located at offset D0h and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
If an EEPROM is used to load configuration registers, the value loaded for this register must be 3214
0000h.
PCI register offset:
Register type:
D0h
Read/Write
3214 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.3.61 General Control Register
This read/write register is used to control various functions of the XIO3130 downstream port.
PCI register offset:
Register type:
D4h
Read/Write; Read Only
0000 x0xx
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
x
x
0
0
0
0
0
x
0
0
1
0
0
0
x
Table 4-83. Bit Descriptions – General Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
TI proprietary. This bit must not be changed from the specified default state.
31:17
16
RSVD
r
TI_PROPRIETARY
rw
REFCK power fault control. This bit controls whether REFCK output should be disabled when
PWR_FAULT is asserted.
0 – REFCK output enable is not a function of PWR_FAULT.
1 – REFCK output enable is a function of PWR_FAULT.
15
14
RC_PF_CTL
rw
rw
This field is loaded from EEPROM (if present) and reset with PERST.
PCI Hot Plug capable. This bit indicates whether this slot is capable of PCI Hot Plug operations.
This bit is used to control the PCI Hot Plug capable (HPC) field in the Slot Capabilities register.
0 – Slot is not PCI Hot Plug capable.
1 – Slot is PCI Hot Plug capable.
SLOT_HPC
SLOT_HPS
This field is loaded from EEPROM (if present) and reset with PERST. The default value for this
bit is that of the DNn_DPSTRP pin for the associated port.
PCI Hot Plug surprise. This bit indicates whether a device present in this slot can be removed
from the system without prior notification. This bit is used to control the PCI Hot Plug surprise
(HPS) field in the Slot Capabilities register.
0 – No device present that can be removed without prior notification
1 – Device present that can be removed without prior notification.
13
rw
This field is loaded from EEPROM (if present) and reset with PERST. The default value for this
bit is that of the DNn_DPSTRP pin for the associated port.
116
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Table 4-83. Bit Descriptions – General Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Power indicator present. This bit indicates whether a power indicator is implemented on the
chassis for this slot. This bit is used to control the PIP field in the Slot Capabilities register.
0 – Power indicator not implemented
12
11
SLOT_PIP
rw
1 – Power indicator implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Attention indicator present. This bit indicates whether an attention indicator is implemented on
the chassis for this slot. This bit is used to control the AIP field in the Slot Capabilities register.
0 – Attention indicator not implemented
SLOT_AIP
rw
rw
1 – Attention indicator implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Manual retention latch sensor present. This bit indicates whether an MRL sensor is
implemented on the chassis for this slot. This bit is used to control the MRLSP field in the Slot
Capabilities register.
10
SLOT_MRLSP
0 – MRL sensor not implemented
1 – MRL sensor implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Power controller present. This bit indicates whether a power controller is implemented for this
slot to control power. This bit is used to control the power controller present (PCP) field in the
Slot Capabilities register.
9
SLOT_PCP
SLOT_ABP
rw
rw
0 – Power controller not implemented
1 – Power controller implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Attention button present. This bit indicates whether an attention button is implemented on the
chassis for this slot. This bit is used to control the attention button present (ABP) field in the Slot
Capabilities register.
8
0 – Attention button not implemented
1 – Attention button implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Slot implemented. This bit indicates that the downstream port is connected to an add-in card
slot (e.g., PCI Express, ExpressCard, etc.). This bit is used to control the SLOT bit in the PCI
Express Capabilities register.
0 – Port not connected to slot
1 – Port connected to slot
7
SLOT_PRSNT
rw
This field is loaded from EEPROM (if present) and reset with PERST. The default value for this
bit is that of the DNn_DPSTRP pin for the associated port.
Power fault input present. This bit indicates whether an input pin is used as a power fault
detection input for this slot. This bit is used to control whether the power fault input pin is used,
e.g., for disabling the REFCLK output buffer.
6
5
SLOT_PFIP
rw
rw
0 – Power fault input not implemented
1 – Power fault input implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Electromechanical interlock present. This bit indicates whether an electromechanical interlock is
implemented on the chassis for this slot. This bit is used to control the EMILP field in the Slot
Capabilities register.
SLOT_EMILP
0 – Electromechanical interlock not implemented
1 – Electromechanical interlock implemented
This field is loaded from EEPROM (if present) and reset with PERST.
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Table 4-83. Bit Descriptions – General Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Link active reporting capable. This bit indicates whether this slot is capable of reporting whether
the link is active. This bit is used to control the DLL_LARC field in the Link Capabilities register.
This field is used to control the SDERC field in the Link Capabilities register.
LINK_ACT_RPT_CA
P
4
rw
0 – Slot is not link active reporting capable
1 – Slot is link active reporting capable
This field is loaded from EEPROM (if present) and reset with PERST.
This bit is a reserved diagnostic bit that must be set to 0 for proper operation. If an EEPROM is
used, the corresponding bit in the EEPROM must be set to 0.
3
2
RSVD
RSVD
rw
r
Reserved. When read, this bit returns zero.
Reference clock disable. This bit is used to disable the REFCK output.
0 – REFCK enabled
1
REFCK_DIS
rw
1 – REFCK disabled
This field is loaded from EEPROM (if present) and reset with PERST.
Receiver presence detect enable. This bit selects whether the PRSNT pin or receiver detect us
used to determine whether the slot is present.
0 – PRSNT pin is used to determine whether slot is present
0
RCVR_PRSNT_EN
rw
1 – Receiver detect is used to determine whether slot is present. It is recommended to only use
this option when PRSNT is not available and the card is removable.
This field is loaded from EEPROM (if present) and reset with PERST. The default value for this
bit is the inverse of the DNn_DPSTRP pin for the associated port.
4.3.62 L0s Idle Timeout Register
This read/write register controls the idle timeout for initiating L0s entry on the Tx path. The value is in units
of 256 ns. The default value is set for just under 7 ＝s. The minimum timeout is 256 ns. This register is
loaded from serial EEPROM and is reset with PERST.
PCI register offset:
Register type:
ECh
Read/Write
1Ah
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
1
1
0
1
0
4.3.63 General Slot Info Register
This read/write register contains information that is used in the slot capabilities and control registers for the
downstream port.
PCI register offset:
Register type:
EEh
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-84. Bit Descriptions – General Slot Info Register
BIT
FIELD NAME
SLOT_NUM
RSVD
ACCESS
DESCRIPTION
Slot number. This field is used to program the Physical Slot Number field in the Slot Capabilities
register. This field is loaded from EEPROM (if present) and reset with PERST.
15:3
2:0
rw
r
Reserved. When read, these bits return zeros.
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4.3.64 Advanced Error Reporting Capabilities ID Register
This read-only register identifies the linked list item as the register for PCI Express Advanced Error
Reporting Capabilities. The register returns 0001h when read.
PCI register offset:
Register type:
100h
Read only
0001h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4.3.65 Next Capability Offset/Capability Version Register
This read-only register returns the value 0000h to indicate that this extended capability block represents
the end of the linked list of extended capability structures. The least significant four bits identify the
revision of the current capability block as 1h.
PCI register offset:
Register type:
102h
Read only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.3.66 Uncorrectable Error Status Register
This register reports the status of individual errors as they occur. Software may clear these bits only by
writing a 1 to the desired location.
PCI register offset:
Register type:
104h
Read Only, Cleared by a Write of one
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-85. Uncorrectable Error Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:21
RSVD
r
Reserved. Return zeros when read.
Unsupported Request error. This bit is asserted when an Unsupported Request error is
20
UR_ERROR
rcuh
detected (i.e., when a request is received that results in the sending of a completion with an
Unsupported Request status).
19
18
ECRC_ERROR
MAL_TLP
rcuh
rcuh
Extended CRC error. This bit is asserted when an Extended CRC error is detected.
Malformed TLP. This bit is asserted when a malformed TLP is detected.
Receiver Overflow. This bit is asserted when the flow control logic detects that the
transmitting device has illegally exceeded the number of credits that were issued.
17
16
15
14
13
RX_OVERFLOW
UNXP_CPL
rcuh
rcuh
rcuh
rcuh
rcuh
Unexpected Completion. This bit is asserted when a completion packet is received that does
not correspond to an issued request.
Completer Abort. This bit is asserted when the completion to a pending request arrives with
Completer Abort status.
CPL_ABORT
CPL_TIMEOUT
FC_ERROR
Completion Timeout. This bit is asserted when no completion has been received for an
issued request before the timeout period.
Flow Control error. This bit is asserted when a flow control protocol error is detected either
during initialization or during normal operation.
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Table 4-85. Uncorrectable Error Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Poisoned TLP. This bit is asserted when an outgoing packet (request or completion) has
been poisoned by setting the poison bit and has inverted the extended CRC attached to the
end of the packet.
12
PSN_TLP
rcuh
11:6
5
RSVD
SD_ERROR
DLL_ERROR
RSVD
r
rcuh
rcuh
r
Reserved. Return zeros when read.
Surprise Down error. See Surprise Down ECN for a description of this error condition.
Data Link Protocol error. This bit is asserted if a data link layer protocol error is detected.
Reserved. Return zeros when read.
4
3:1
0
Undefined
r
This value read from this bit is undefined.
4.3.67 Uncorrectable Error Mask Register
The Uncorrectable Error Mask register controls the reporting of individual errors as they occur. When a bit
is set to one, the error status bits are still affected, but the error is not logged and no error reporting
message is sent upstream.
PCI register offset:
Register type:
108h
Read Only, Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-86. Uncorrectable Error Mask Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:21
RSVD
r
Reserved. Return zeros when read.
Unsupported Request error mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Extended CRC error mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Malformed TLP mask.
20
19
18
17
16
15
14
UR_ERROR_MASK
ECRC_ERROR_MASK
MAL_TLP_MASK
rwh
rwh
rwh
rwh
rwh
rwh
rwh
0 - Error condition is unmasked.
1 - Error condition is masked.
Receiver Overflow mask.
RX_OVERFLOW_MASK
UNXP_CPL_MASK
0 - Error condition is unmasked.
1 - Error condition is masked.
Unexpected Completion mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Completer Abort mask.
CPL_ABORT_MASK
CPL_TIMEOUT_MASK
0 - Error condition is unmasked.
1 - Error condition is masked.
Completion Timeout mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
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Table 4-86. Uncorrectable Error Mask Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Flow Control error mask.
13
FC_ERROR_MASK
rwh
0 - Error condition is unmasked.
1 - Error condition is masked.
Poisoned TLP mask.
12
11:6
5
PSN_TLP_MASK
RSVD
rwh
r
0 - Error condition is unmasked.
1 - Error condition is masked.
Reserved. Return zeros when read.
Surprise Down error mask.
SD_MASK
rwh
0 - Error condition is unmasked.
1 - Error condition is masked.
Data Link Protocol error mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Reserved. Return zeros when read.
4
DLL_ERROR_MASK
rwh
3:1
0
RSVD
r
r
Undefined
This value read from this bit is undefined.
4.3.68 Uncorrectable Error Severity Register
The Uncorrectable Error Severity register controls the reporting of individual errors as ERR_FATAL or
ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is
clear, the corresponding error condition is identified as nonfatal.
PCI register offset:
Register type:
10Ch
Read Only, Read/Write
0003 2030h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
Table 4-87. Uncorrectable Error Severity Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Return zeros when read.
Unsupported Request error severity.
31:21
RSVD
r
20
19
18
17
UR_ERROR_SEVR
ECRC_ERROR_SEVR
MAL_TLP_SEVR
rwh
rwh
rwh
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Extended CRC error severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Malformed TLP severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Receiver Overflow severity.
RX_OVERFLOW_SEVR
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
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Table 4-87. Uncorrectable Error Severity Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Unexpected Completion severity.
16
UNXP_CPL_SEVR
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Completer Abort severity.
15
14
13
CPL_ABORT_SEVR
CPL_TIMEOUT_SEVR
FC_ERROR_SEVR
rwh
rwh
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Completion Timeout severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Flow Control error severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Poisoned TLP severity.
12
11:6
5
PSN_TLP_SEVR
RSVD
rwh
r
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Reserved. Return zeros when read.
Surprise Down error severity.
SD_ERROR_SEVR
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Data Link Protocol error severity.
4
DLL_ERROR_SEVR
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Reserved. Return zeros when read.
3:1
0
RSVD
r
r
Undefined
This value read from this bit is undefined.
4.3.69 Correctable Error Status Register
The Correctable Error Status register reports the status of individual errors as they occur. Software may
clear these bits only by writing a 1 to the desired location.
PCI register offset:
Register type:
110h
Read Only, Cleared by a Write of one
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-88. Correctable Error Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:14
13
RSVD
r
Reserved. Return zeroes when read.
Advisory nonfatal error status.
ANFES
rcuh
Replay timer timeout. This bit is asserted when the replay timer expires for a pending request
or completion that has not been acknowledged.
12
11:9
8
REPLAY_TMOUT
RSVD
rcuh
r
Reserved. Return zeroes when read.
REPLAY_NUM rollover. This bit is asserted when the replay counter rolls over when a
pending request of completion has not been acknowledged.
REPLAY_ROLL
rcuh
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Table 4-88. Correctable Error Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Bad DLLP error. This bit is asserted when an 8b/10n error is detected by the PHY during
reception of a DLLP.
7
BAD_DLLP
rcuh
Bad TLP error. This bit is asserted when an 8b/10b error is detected by the PHY during
reception of a TLP.
6
BAD_TLP
rcuh
5:1
0
RSVD
r
Reserved. Return zeros when read.
RX_ERROR
rcuh
Receiver error. This bit is asserted when an 8b/10b error is detected by the PHY at any time.
4.3.70 Correctable Error Mask Register
The Correctable Error Mask register controls the reporting of individual errors as they occur. When a bit is
set to one, error status bits are still affected, but the error is not logged and no error reporting message is
sent upstream.
PCI register offset:
Register type:
114h
Read Only, Read/Write
0000 2000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-89. Correctable Error Mask Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Return zeros when read.
31:14
RSVD
r
Advisory nonfatal error mask. This bit is set by default to enable compatibility with
software that does not comprehend role-based error reporting.
13
ANFEM
rwh
Replay timer timeout mask.
0 – Error condition is unmasked
1 – Error condition is masked
Reserved. Return zeros when read.
REPLAY_NUM rollover mask.
0 – Error condition is unmasked
1 – Error condition is masked
Bad DLLP error mask.
12
11:9
8
REPLAY_TMOUT_MASK
RSVD
rwh
r
REPLAY_ROLL_MASK
rwh
7
BAD_DLLP_MASK
rwh
0 – Error condition is unmasked
1 – Error condition is masked
Bad TLP error mask.
6
5:1
0
BAD_TLP_MASK
RSVD
rwh
r
0 – Error condition is unmasked
1 – Error condition is masked
Reserved. Return zeros when read.
Receiver error mask.
RX_ERROR_MASK
rwh
0 – Error condition is unmasked
1 – Error condition is masked
4.3.71 Advanced Error Capabilities and Control Register
The Advanced Error Capabilities and Control register allows the system to monitor and control the
advanced error reporting capabilities.
PCI register offset:
118h
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Register type:
Default value:
Read Only, Read/Write
0000 00A0h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
Table 4-90. Advanced Error Capabilities and Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Return zeros when read.
31:9
RSVD
r
Extended CRC check enable.
8
7
6
ECRC_CHK_EN
rwh
r
0 – Extended CRC checking is disabled
1 – Extended CRC checking is enabled
Extended CRC check capable. This read-only bit returns a value of ‘1’ indicating
that the bridge is capable of checking extended CRC information.
ECRC_CHK_CAPABLE
ECRC_GEN_EN
Extended CRC generation enable.
rwh
0 – Extended CRC generation is disabled
1 – Extended CRC generation is enabled
Extended CRC generation capable. This read-only bit returns a value of ‘1’
indicating that the bridge is capable of generating extended CRC information.
5
ECRC_GEN_CAPABLE
FIRST_ERR
r
First error pointer. This five-bit value reflects the bit position within the
Uncorrectable Error Status register corresponding to the class of the first error
condition that was detected.
4:0
rh
4.3.72 Header Log Register
The Header Log register stores the TLP header for the packet that lead to the most recently detected error
condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a
4DW TLP header).
PCI register offset:
Register type:
11Ch – 128h
Read only
Default value:
0000 0000h
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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5
PCI Hot Plug Implementation Overview
5.1 PCI Hot Plug Architecture Overview
The PCI Express architecture is designed to natively support both hot-add and hot-removal (collectively
Hot-Plug) of adapters. The architecture also provides a ‘toolbox’ of mechanisms that allow different
user/operator models to be supported using a self-consistent infrastructure. PCI Express defines the
registers necessary to support the integration of a PCI Hot Plug controller within individual root and switch
ports. Under PCI Hot-Plug software control, the PCI Hot-Plug controllers and the associated port interface
within the root or switch port must control the card interface signals to ensure orderly power-down and
power-up as cards are removed and replaced.
Table 5-1. GPIO Matrix
GPIO[#]
0
1
2
3
4
5
6
7
6
4
8
9
10
11
12
13
14
15
16
PRSNT1
S
PWRON1
PWRGD1
CLKREQ1
MRLSDET1
ACTLED1
PWRLED1
ATNLED1
ATNBTN1
PWRFLT1
EMILCTL1
EMILENG1
S
S
2
3
6
6
6
2
5
2
5
2
5
6
4
6
4
2
5
2
5
2
4
2
4
2
4
2
4
4
2
2
6
6
PRSNT2
S
PWRON2
PWRGD2
CLKREQ2
MRLSDET2
ACTLED2
PWRLED2
ATNLED2
ATNBTN2
PWRFLT2
EMILCTL2
EMILENG2
S
S
2
3
6
6
4
7
7
5
3
6
3
6
3
6
6
4
7
5
3
6
3
6
2
4
2
4
3
5
3
5
2
3
6
7
PRSNT3
S
PWRON3
PWRGD3
CLKREQ3
MRLSDET3
ACTLED3
PWRLED3
ATNLED3
ATNBTN3
PWRFLT3
EMILCTL3
EMILENG3
S
S
2
3
7
7
5
7
7
5
4
7
4
7
4
7
7
5
7
5
4
7
4
7
3
5
3
5
3
5
3
5
3
3
7
7
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In Table 2-11, S indicates a strapping option. If the appropriate DNn_DPSTRP pin is pulled high, the GPIO
is mapped to this value and is no longer mapped by the GPIO Control register.
Each downstream port of the XIO3130 is assigned one dedicated sideband pin, DNn_PERST. Three
additional sideband pins may be dedicated to each port for PCI Hot Plug support. The DNn_DPSTRP pins
are set for the corresponding ports to indicate support for PCI Hot Plug. When the DNn_DPSTRP pin
strapping defines a GPIO pin as a PCI Hot Plug support pin, that pin is associated with the Slot Capability,
Slot Status, and Slot Control registers of the corresponding downstream port. These registers are defined
in sections Section 4.3.55, Section 4.3.56, and Section 4.3.57, respectively. When the DPSTRP[2:0] pin
strapping defines a GPIO pin as a GPIO pin, that pin is mapped to a bit field in the GPIO Configuration
registers and Data register. These registers are defined in section Section 4.2.61 through Section 4.2.65.
Table 5-2. PCI Hot Plug Sideband Signals
Signal
I/O
Function
Dn_PERST
O
Port n PE Reset. The PCI Hot Plug card or device is held in a reset state when this signal is low.
Port n Present. A PCI Hot Plug card or device is attached to a port when this signal is low.
PRSNTn
I
This signal is reported in the PDC bit of the Slot Status register. When this signal is in a de-asserted high
state, the DNn_PERST pin is asserted low, REFCLK is disabled, and PWRONn is de-asserted high.
Port n Power On. Power is applied to the PCI Hot Plug card or device attached to the port when this
signal is low.
PWRONn
PWRGDn
O
I
Port n Power Good: The power to the PCI Hot Plug card or device is adequate and it is alright to enable
REFCLK to the card or device and de-assert DNn_PERST. When this signal transitions to a low state, the
XIO3130 switch asserts DNn_PERST low and turns off REFCLK.
Additional GPIO pins may be allocated to PCI Hot Plug support via programming by assigning the pins to
PCI Hot Plug pin functionality in the GPIO Control registers defined in sections Section 4.2.62 through
Section 4.2.65.
Table 5-3. Pins Assigned to GPIO Control Registers
Signal
CLKREQn
I/O
Function
Port n CLK REQ. This signal is used to disable the clock during normal operation. If PWRONn is high or
PRSNTn is high or PWRGDn is low, this signal is ignored by the XIO3130.
I
Port n Activity. This pin toggles at anytime activity is detected on the port interface. Otherwise, this pin is
high.
ACT_LEDn
O
PWR_LEDn
ATN_LEDn
ATN_BTNn
O
O
I
Port n Power Indicator: See PI_CTL bit field in Slot Control register (section Section 4.3.56).
Port n Attention Indicator: See AI_CTL bit field in Slot Control register (section Section 4.3.56).
Port n Attention Push button: See ABP bit field in Slot Status register (section Section 4.3.57).
Port n Manually-Operated Retention Latch (MRL): See MRLSS bit field in Slot Status register (section
Section 4.3.57).
MRLS_DETn
EMIL_CTLn
EMIL_ENGn
I
O
I
Port n Electromechanical Interlock: See EMIL_CTL bit field in Slot Control register (section
Section 4.3.56).
Port n Electromechanical Interlock status: See EMIL_STAT bit field in Slot Status register (section
Section 4.3.57).
5.2 PCI Hot Plug Timing
5.2.1 Power-Up Cycle
The XIO3130 switch can be powered up numerous ways depending on the way the DPSTRP[2:0]
strapping defines the port. The different power-up cycles are: nonPCI Hot Plug power-up cycle, PCI Hot
Plug power-up cycle with PWRGDn feedback, and PCI Hot Plug power-up cycle without PWRGDn
feedback.
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5.2.1.1 NonPCI Hot Plug Power-Up Cycle
For nonPCI Hot Plug power-up cycles, there are no PWRONn, PWRGDn, or PRSNTn signals, and the
Slot Control register is not used to power the port up. As soon as the REFCLKn output is stable on the
port, the PERSTn signal is de-asserted high. If no device is detected on the port before Link Training
times out, the PERSTn signal is asserted low and REFCLKn is disabled.
PERST#
PERSTn#
REFCLKn
Unstable
Stable
<100 ms
Figure 5-1. NonPCI Hot Plug Power-Up Cycle
5.2.1.2 PCI Hot Plug Power-Up Cycle With PWRGDn Feedback
For PCI Hot Plug power up cycles with PWRGDn feedback, the PWRONn signal going low gates the
power-up cycle. The XIO3130 switch asserts PWRONn and waits for the PWRGDn signal to transition
high, indicating that power to the slot is now stable. When PWRGDn goes high, REFCLKn is enabled and
a 100 ms time-out starts. After the 100 ms time-out completes, PERSTn is de-asserted. If the port has
been programmed (see GPIO Control Registers in sections Section 4.2.61 through Section 4.2.64) to have
a CLKREQn input when PERSTn de-asserts high, REFCLKn is disabled when CLKREQn is not low.
PWRONn#
PWRGDn
CLKREQn#
REFCLKn
PERSTn#
Unstable
Stable
>100 ms
100 ms
Figure 5-2. PCI Hot Plug Power-Up Cycle With PWFRDn Feedback
5.2.1.3 PCI Hot Plug Power-Up Cycle With No PWRGDn Feedback
This application requires the PWRGDn signal to be tied high. The PWRONn signal going low gates the
power-up cycle. The XIO3130 switch asserts PWRONn and because the PWRGDn signal is tied high, the
power-up cycle starts as soon as PWRONn is asserted. After 100 ms, REFCLKn is enabled, and a 100
ms time-out starts. After the 100 ms time-out completes, PERSTn is de-asserted. If the port has been
programmed (see GPIO Control registers in sections Section 4.2.61 through Section 4.2.64) to have a
CLKREQn input when PERSTn de-asserts high, REFCLKn is disabled when CLKREQn is not low.
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PWRONn#
PWRGDn
CLKREQn#
REFCLKn
PERSTn#
Unstable
Stable
100 ms
>100 ms
100 ms
Figure 5-3. PCI Hot Plug Power-Up Cycle With No PWGRDn Feedback
5.2.2 Power-Down Cycles
Various conditions cause the assertion of PERSTn, which also cause REFCLKn to stop a short time later.
5.2.2.1 Normal Power-Down
For PCI Hot Plug ports, other conditions may also power-down the port. Software can power the port
down by de-asserting the PC_CTL bit in the Slot Control register. This invokes a normal power-down
cycle, which is the same power-down cycle invoked by the upstream PERST being asserted.
PWRONn#
PWRGDn
CLKREQn#
Stable
REFCLKn
PERSTn#
< 100 ms
Figure 5-4. Normal Power-Down
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5.2.2.2 Surprise Removal
Another PCI Hot Plug Port power-down condition occurs when the PRSNTn pin is de-asserted, indicating
that the card or device has been removed without warning (i.e., surprise removal).
PRSNTn#
PWRONn#
CLKREQn#
Stable
REFCLKn
PERSTn#
PWRGDn
<500 ns
<100 ms
Figure 5-5. Surprise Removal
In the case of surprise removal, the XIO3130 switch de-asserts PERST within 500 ns after a de-bounced
PRSNTn de-asserted state exists. Then REFCLKn is disabled, and the PWRONn signal is de-asserted
within 100 µs.
5.2.2.3 PWRGDn De-Assertion
Another situation that forces a PCI Hot Plug port to power-down is the de-assertion of PWRGDn. If
PWRGDn is de-asserted, the XIO3130 switch disables REFCLKn but does not de-assert PWRONn.
PWRGDn
PWRONn#
CLKREQn#
REFCLKn
PERSTn#
Stable
Unstable
Stable
<500 ns
100 ms
>100 ms
Figure 5-6. Effect When PWFRGn Goes Low
Note that once PERSTn goes low, it must remain low for at least 100 ms.
5.2.3 PMI_Turn_Off and PME_To_Ack Messages
For information on the PME_Turn_Off and PME_To_Ack messages, see section Section 3.2.6.
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5.2.4 Debounce Circuits
Integrated de-bounce circuits are provided for the following input pins:
•
•
•
PRSNT[2:0] present detects for each downstream port; used with PCI Express or ExpressCard
(formerly NEWCARD) slots.
ATN_BTN[2:0], which are attention button inputs, are MUXed onto GPIO pins; de-bounce is only
needed when the relevant GPIO pins are programmed to this mode.
MRLS_DET[2:0], which are manual retention latch detection inputs, are MUXed onto GPIO pins;
de-bounce is only needed when the relevant GPIO pins are programmed to this mode.
A timeout of approximately 10 ms is used.
5.2.5 HP_INTX Pin
The HP_INTX output signal is asserted when a PCI Hot Plug interrupt occurs within the switch, but only
asserted due to PCI Hot Plug events. This signal is typically be connected on system boards to an SCI
(System Control Interrupt) input, which invokes an interrupt service routine included in the system BIOS;
other system implementations may connect HP_INTX to a PCI bus interrupt pin.
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6
Electrical Characteristics
This chapter describes the electrical characteristics of the XIO3130.
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VDDRC,
VAUX33REF,
–0.5 to 3.6
V
VDD33REF
Supply voltage range
VDDAREF,
VDDA, VDDD,
VDD15
–0.5 to 1.65
V
PCI Express (PER)
–0.6 to 0.6
–0.5 to VDD_15
–0.5 to VDD_33
–0.5 to VDD_15
–0.5 to VDD_15
–0.5 to VDD_33
±20
V
V
VI
Input voltage range
Output voltage range
PCI Express REFCKI (differential)
Miscellaneous 3.3 – VIO
PCI Express (PET)
V
V
VO
PCI Express REFCKO
V
Miscellaneous 3.3 – VIO
V
(2)
Input clamp current, (VI < 0 or VI > VDD
)
mA
mA
°C
(3)
Output clamp current, (VO < 0 or VO > VDD
)
±20
Tstg
Storage temperature range
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) Applies to external input. VI < 0 or VI > VDD
.
(3) Applies to external output. VO < 0 or VO > VDD
.
6.2 Recommended Operating Conditions
OPERATION
MIN
NOM
MAX
UNIT
VDDD
VDD15
Supply voltage
VDDAREF
1.5 V
1.35
1.5
1.65
V
VDDA
VDDRC
VDD33
Supply voltage
VAUX33REF
3.3 V
3
3.3
3.6
V
VDD33REF
TA
TJ
Operating ambient temperature range
Virtual junction temperature(1)
0
0
25
25
70
°C
°C
115
(1) The junction temperature reflects simulated conditions. The customer is responsible for verifying junction temperature.
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6.3 PCI Express Differential Transmitter Output Ranges
PARAMETER
TERMINALS
MIN NOM
MAX UNIT
COMMENTS
UI
PETP,
PETN
Each UI is 400 ps ±300 ppm. UI does not account
for SSC dictated variations.See
399.88 400 400.12
ps
V
(1)
Unit interval
VTX-DIFFp-p
Differential peak-to-peak output
voltage
PETP,
PETN
VTX-DIFFp-p = 2*|VTXP – VTXN|.
0.8
–3
1.2
(2)
See
This value is the ratio of the VTX-DIFFp-p of the
second and following bits after a transition divided
by the VTX-DIFFp-p of the first bit after a transition.
VTX-DE-RATIO
De-emphasized differential output
voltage (ratio)
PETP,
PETN
–3.5
–4.0
dB
UI
(2)
See
The maximum transmitter jitter can be derived as
TTXMAX- JITTER = 1 – TTX-EYE = 0.25 UI.
TTX-EYE
Minimum TX eye width
PETP,
PETN
0.75
(2)(3)
See
Jitter is defined as the measurement variation of
the crossing points (VTX-DIFFp-p = 0 V) in relation to
recovered TX UI. A recovered TX UI is calculated
over 3500 consecutive UIs of sample data. Jitter is
measured using all edges of the 250 consecutive
UIs in the center of the 3500 UIs that are used for
TTX-EYE-MEDIAN-to-MAX-JITTER
Maximum time between the jitter
median and maximum deviation
from the median
PETP,
PETN
0.125
UI
(2)(3)
calculating the TX UI. See
TTX-RISE,
TTX-FALL
PETP,
PETN
(2)(4)
0.125
UI
See
Differential TX output rise/fall time
VTX-CM-ACp
RMS ac peak common mode output
voltage
VTX-CM-ACp = RMS(|VTXP + VTXN|/2 – VTX-CM-DC
)
PETP,
PETN
20
mV
VTX-CM-DC = DC(avg) of |VTXP + VTXN|/2
(2)
See
|VTX-CM-DC – VTX-CM-IDLE-DC| ≤ 100 mV
VTX-CM-DC-ACTIVE-IDLE-DELTA
Absolute delta of DC common mode
voltage during L0 and electrical idle.
VTX-CM-DC = DC(avg) of |VTXP + VTXN|/2 [during L0]
VTX-CM-IDLE-DC = DC(avg) of |VTXP + VTXN|/2 [during
electrical idle]
PETP,
PETN
0
100
mV
mV
(2)
See
|VTXP-CM-DC – VTXN-CM-DC| ≤ 25 mV when
VTXP-CM-DC = DC(avg) of |VTXP|
VTX-CM-DC-LINE-DELTA
Absolute delta of DC common mode
voltage between P and N
PETP,
PETN
0
0
25
VTXN-CM-DC = DC(avg) of |VTXN
See
|
(2)
VTX-IDLE-DIFFp
Electrical idle differential peak output
voltage
PETP,
PETN
VTX-IDLE-DIFFp = |VTXP-IDLE – VTXN-IDLE| ≤ 20 mV
20
mV
mV
(2)
See
VTX-RCV-DETECT
The amount of voltage change
allowed during receiver detection
The total amount of voltage change that a
transmitter can apply to sense whether a low
impedance receiver is present.
PETP,
PETN
600
VTX-DC-CM
The TX DC common mode voltage
PETP,
PETN
The allowed DC common mode voltage under any
condition
0
3.6
90
V
ITX-SHORT
TX short circuit current limit
PETP,
PETN
The total current that the transmitter can provide
when shorted to its ground.
mA
Minimum time that a transmitter must be in
electrical Idle. The receiver uses this value to start
looking for an electrical idle exit after successfully
receiving an electrical idle ordered set.
TTX-IDLE-MIN
Minimum time spent in electrical idle
PETP,
PETN
50
UI
UI
After sending an electrical idle ordered set, the
transmitter must meet all electrical idle
specifications within this time. This is considered a
de-bounce time for the transmitter to meet
electrical idle after transitioning from L0.
TTX-IDLE-SET-to-IDLE
Maximum time to transition to a valid
electrical idle after sending an
electrical idle ordered set
PETP,
PETN
20
(1) No test load is necessarily associated with this value.
(2) Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX UIs.
(3) A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the transmitter
collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median
and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It
must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter
points on either side is approximately equal as opposed to the averaged time value.
(4) Measured between 20% and 80% at transmitter package terminals into a test load for both VTX-D+ and VTX-D–.
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PCI Express Differential Transmitter Output Ranges (continued)
PARAMETER
TERMINALS
MIN NOM
MAX UNIT
COMMENTS
Maximum time to meet all TX specifications when
transitioning from electrical idle to sending
differential data. This value is considered a
de-bounce time for the TX to meet all TX
specifications after leaving electrical idle.
TTX-IDLE-to-DIFF-DATA
Maximum time to transition to valid
TX specifications after leaving an
electrical idle condition
PETP,
PETN
20
UI
RLTX-DIFF
Differential return loss
PETP,
PETN
Measured over 50 MHz to 1.25 GHz.
See
10
6
dB
dB
Ω
(5)
RLTX-CM
Common mode return loss
PETP,
PETN
Measured over 50 MHz to 1.25 GHz.
(5)
See
ZTX-DIFF-DC
DC differential TX impedance
PETP,
PETN
80
40
75
100
120
200
TX DC differential mode low impedance
ZTX-DC
PETP,
PETN
Required TX-D+ as well as TX-D– DC impedance
during all states
Ω
Transmitter DC impedance
CTX
PETP,
PETN
All transmitters are AC-coupled and capacitors are
required on the PWB.
nF
AC coupling capacitor
(5) The transmitter input impedance results in a differential return loss greater than or equal to 12 dB and a common mode return loss
greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input
levels. The reference impedance for return loss measurements is 50 Ω to ground for both the P and N lines. Note that the series
capacitors CTX is optional for the return loss measurement.
6.4 PCI Express Differential Receiver Input Ranges
PARAMETER
TERMINALS
MIN NOM
MAX UNIT
COMMENTS
VRX-DIFFp-p
Differential input peak-to-peak
voltage
PERP,
PERN
VRX-DIFFp-p = 2*|VRX-D+ – VRX-D–|
See
0.175
1.2
V
(1)
The maximum interconnect media and transmitter
jitter that can be tolerated by the Receiver is
derived as TRX-MAX- JITTER = 1 - TRX-EYE = .6 UI
TRX-EYE
Minimum receiver eye width
PERP, PERN
0.4
UI
(1)(2)(3)
See
Jitter is defined as the measurement variation of
the crossing points (VRX-DIFFp-p = 0 V) in relation to
recovered TX UI. A recovered TX UI is calculated
over 3500 consecutive unit intervals of sample
data. Jitter is measured using all edges of the 250
consecutive UI in the center of the 3500 UI used
for calculating the TX UI.
TRX-EYE-MEDIAN-to-MAX-JITTER
Maximum time between the jitter
median and maximum deviation
from the median.
PERP,
PERN
0.3
UI
(1)(2)
See
VRX-CM-ACp = RMS( |VRX-D+ + VRX-D–| / 2 –
VRX-CM-DC)
VRX-CM-ACp
AC peak common mode input
voltage
PERP,
PERN
150
mV
VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D-| / 2
(1)
See
(1) Specified at the measurement point and measured using the clock recovery function specified in PCI Express™ Base Specification
Revision 1.1, Section 4.3.3.2. The test load in Figure 4-25 should be used as the RX device when taking measurements (also refer to
the Receiver compliance eye diagram shown in Figure 4-26 of the specification). If the clocks to the RX and TX are not derived from the
same reference clock, the TX UI recovered using the clock recovery function specified in Section 4.3.3.2 must be used as a reference
for the eye diagram.
(2) The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the
median is less than half of the total 0.64. It should be noted that the median is not the same as the mean. The jitter median describes
the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. The RX
UI recovered using the clock recovery function specified in Section 4.3.3.2 must be used as the reference for the eye diagram. This
parameter is measured with the equivalent of a zero jitter reference clock. The TRX-EYE measurement is to be met at the target bit error
rate. The TRX-EYE-MEDIAN-to-MAX-JITTER specification is to be met using the compliance pattern at a sample size of 1,000,000 UI.
(3) See the PCI Express Jitter and BER white paper for more details on the Rx-Eye measurement.
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PCI Express Differential Receiver Input Ranges (continued)
PARAMETER
TERMINALS
MIN NOM
MAX UNIT
COMMENTS
Measured over 50 MHz to 1.25 GHz with the P
and N lines biased at +300 mV and –300 mV,
respectively.
RLRX-DIFF
Differential return loss
PERP,
PERN
10
dB
(4)
See
Measured over 50 MHz to 1.25 GHz with the P
and N lines biased at +300 mV and –300 mV,
RLRX-CM
Common mode return loss
PERP,
PERN
6
dB
respectively.
(4)
See
.
ZRX-DIFF-DC
DC differential input impedance
PERP,
PERN
RX DC differential mode impedance.
80
40
100
50
120
60
Ω
Ω
(5)
See
.
Required RX-D+ as well as RX-D– DC impedance
ZRX-DC
DC input impedance
PERP,
PERN
(50 Ω ±20% tolerance).
(5)
See (1) and
.
Required RX-D+ as well as RX-D– DC impedance
ZRX-HIGH-IMP-DC
Powered-down DC input impedance
PERP,
PERN
200K
65
Ω
when the receiver terminations do not have power.
(6)
See
.
VRX-IDLE-DET-DIFFp-p
Electrical idle detect threshold
PERP,
PERN
VRX-IDLE-DET-DIFFp-p = 2 * |VRX-D+ – VRX-D–
|
175
10
mV
measured at the receiver package pins
An unexpected electrical idle (VRX-DIFFp-p
<
TRX-IDLE-DET-DIFF-ENTER-TIME
Unexpected electrical idle enter
detect threshold integration time
VRX-IDLE-DET-DIFFp-p) must be recognized no longer
than
TRX-IDLE-DET-DIFF-ENTER-TIME to signal an
unexpected idle condition.
PERP,
PERN
ms
(4) The Receiver input impedance shall result in a differential return loss greater than or equal to 10 dB with a differential test input signal of
no less than 200 mV (peak value, 400 mV differential peak to peak) swing around ground applied to D+ and D– lines and a common
mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance
requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 Ω to ground for both the
D+ and D– line (i.e., as measured by a Vector Network Analyzer with 50 Ω probes; see Figure 4-25 in the specification). Note that the
series capacitors CTX is optional for the return loss measurement.
(5) Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM) there is a 5
ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
(6) The RX DC common mode impedance that exists when no power is present or Fundamental Reset is asserted. This helps ensure that
the Receiver Detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 200 mV
above the RX ground.
6.5 PCI Express Differential Reference Clock Input Ranges(1)
PARAMETER
TERMINALS
MIN NOM
MAX UNIT
COMMENTS
fIN-DIFF
REFCKIp
REFCKIn
The input frequency is 100 MHz +300 ppm and
–2800＝ppm including SSC-dictated variations.
100
MHz
Differential input frequency
VRX-DIFFp-p
Differential input peak-to-peak
voltage
REFCKIp
REFCKIn
0.175
1.2
V
VRX-DIFFp-p = 2*|VREFCKp – VREFCKn|
VRX-CM-ACp
AC peak common mode input
voltage
VRX-CM-ACp = RMS(|VREFCKp + VREFCKn|/2 –
VRX-CM-DC)
VRX-CM-DC = DC(avg) of |VREFCKp + VREFCKn|/2
REFCKIp
REFCKIn
140
mV
REFCKIp
REFCKIn
Duty cycle
40%
60%
Differential waveform input duty cycle
ZRX-DIFF-DC
DC differential input impedance
REFCKIp
REFCKIn
REFCKIp/ REFCKIn DC differential mode
impedance
20
kΩ
(1) The XIO3130 is compliant with the defined system jitter models for a PCI Express reference clock and associated TX/RX link. These
system jitter models are described in the PCI Express Jitter Modeling, Revision 1.0RD document. Any usage of the XIO3130 in a
system configuration that does not conform to the defined system jitter models requires the system designer to validate the system jitter
budgets.
134
Electrical Characteristics
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SLLS693C–MAY 2007–REVISED JUNE 2008
6.6 PCI Express Reference Clock Output Requirements
100-MHz INPUT
SYMBOL
PARAMETER
UNIT
NOTES
MIN
0.6
MAX
(2)
Rise Edge Rate Rising edge rate
Fall Edge Rate Falling edge rate
4
4
V/ns
V/ns
mV
See (1) and
See (1) and
.
(2)
0.6
.
(1)
VIH
Differential input high voltage
150
See
See
.
.
(1)
VIL
Differential input low voltage
–150
550
mV
(3)
(5)
(6)
VCROSS
RCROSS DELTA
Absolute crossing point voltage
250
mV
See Notes
,
(4), and
(4), and
.
Variation of VCROSS over all rising
clock edges
(3)
140
100
mV
See Notes
,
.
(7)
(7)
VRB
Ring-back voltage margin
Time before VRB is allowed
Average clock period accuracy
–100
500
mV
ps
See (1) and
See (1) and
See Notes
.
.
TSTABLE
(1)
(9)
TPERIOD AVG
TPERIOD ABS
–300
2800
ppm
,
(8), and
.
Absolute period (including jitter and
spread spectrum)
(10)
9.847 10.203
ns
See (1) and
.
(1)
TCCJITTER
VMAX
Cycle-to-cycle jitter
150
1.15
–0.3
ps
V
See
.
(11)
(12)
Absolute maximum input voltage
Absolute minimum input voltage
Duty cycle
See (3) and
See (3) and
.
.
VMIN
V
(1)
Duty Cycle
40
40
60
20
60
%
See
.
Rise-Fall
Matching
Rising edge rate (REFCKOp) to
falling edge rate (REFCKOn)
matching
(13)
(14)
%
See (3) and
See (3) and
.
ZC-DC
Clock source DC impedance
Ω
.
(1) Measurement taken from differential waveform.
(2) Measured from –150 mV to +150 mV on the differential waveform (derived from REFCKOp minus REFCKOn). The signal must be
monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero
crossing.
(3) Measurement taken from single-ended waveform.
(4) Measured at crossing point where the instantaneous voltage value of the rising edge of REFCKOp equals the falling edge of REFCKOn.
(5) Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
(6) Defined as the total variation of all crossing voltages of rising REFCKOp and falling REFCKOn. This is the maximum allowed variance in
VCROSS for any particular system.
(7) TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is
allowed to droop back into the VRB ±100 mV differential range.
(8) Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations.
(9) PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly
or 100 Hz. For 300 PPM then we have a error budget of 100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a
frequency counter with measurement window set to 100 ms or greater. The ±300 PPM applies to systems that do not employ Spread
Spectrum or that use common clock source. For systems employing Spread Spectrum there is an additional 2500 PPM nominal shift in
maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2800 PPM.
(10) Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and
spread spectrum modulation.
(11) Defined as the maximum instantaneous voltage including overshoot.
(12) Defined as the minimum instantaneous voltage including undershoot.
(13) Matching applies to rising edge rate for REFCKOp and falling edge rate for REFCKOn. It is measured using a ±75 mV window centered
on the median cross point where REFCKOp rising meets REFCKOn falling. The median cross point is used to calculate the voltage
thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCKOp should be compared to the Fall
Edge Rate of REFCKOn, the maximum allowed difference should not exceed 20% of the slowest edge rate.
(14) System board compliance measurements must use the recommended test load card. REFCKOp and REFCKOn are to be measured at
the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single
ended probes with math or differential probe can be used for differential measurements. Test load CL = 2 pF.
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Electrical Characteristics
135
XIO3130
SLLS693C–MAY 2007–REVISED JUNE 2008
www.ti.com
6.7 3.3-V I/O Electrical Characteristics(1)
PARAMETER
OPERATIONS
TEST CONDITIONS
MIN
MAX
VDD33
UNIT
V
(2)
VIH
VIL
VI
High-level input voltage (See
Low-level input voltage (See(2)
)
VDD33
VDD33
0.7 VDD33
)
0
0
0
0
0.3 VDD33
VDD33
V
Input voltage
V
(3)
VO
tπ
Output voltage (See
)
VDD33
V
Input transition time (trise and tfall)
25
ns
V
(4)
Vhys
VOH
VOL
IOZ
Input hysteresis (See
)
0.13 VDD33
High-level output voltage
VDD33
VDD33
VDD33
IOH = –4 mA
IOL = 4 mA
0.8 VDD33
V
Low-level output voltage
0.22 VDD33
V
(3)
High-impedance, output current (See
)
VI = 0 to VDD33
±20
µA
High-impedance, output current with internal
IOZP
II
VDD33
VDD33
VI = 0 to VDD33
VI = 0 to VDD33
±100
±1
µA
µA
(5)
pullup or pulldown resistor (See
)
(6)
Input current (See
)
(1) This table applies to PERST, WAKE, REFCLK_SEL, GRST, and GPIO18:0.
(2) Applies to external inputs and bidirectional buffers.
(3) Applies to external outputs and bidirectional buffers.
(4) Applies to PERST and GRST.
(5) Applies to GRST (pullup resistor) and most GPIO (pullup resistor).
(6) Applies to external input buffers.
6.8 POWER CONSUMPTION(1)
PARAMETER
MIN
NOM(2)
MAX(3)
20.61
UNIT
mA
I3.3V
11.21
578.7
36.99
868.05
5.28
I1.5V
725.8
mA
P3.3V
P1.5V
68.01
mW
mW
mA
1088.7
(4)
IAUX
(1) Measurements taken at 25°C with nominal power supply, 3.3 V and 1.5 V.
(2) Nominal conditions are defined as switch only power, no devices downstream, and downstream clocks not running.
(3) Maximum power conditions are defined as three downstream devices constantly running traffic and downstream clocks running.
(4) Measurement performed with three devices downstream, system in S5.
136
Electrical Characteristics
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Jul-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
XIO3130ZHC
ACTIVE
BGA MI
CROSTA
R
ZHC
196
126 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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