XIWR6432LQGAMF_技术文档

IWRL6432

ZHCSRC3 –DECEMBER 2022

IWRL6432 单芯片57GHz 至64GHz 工业雷达传感器

• 主机接口

1 特性

– UART

• FMCW 收发器

– CAN-FD

– SPI

– 集成PLL、发送器、接收器、基带和ADC

– 57GHz - 64GHz 的覆盖范围，具有7GHz 的连

续带宽

• 用于原始ADC 样本采集的RDIF（雷达数据接口）

• 为用户应用提供的其他接口

– 3 个接收通道和2 个发送通道

– 短距离（通常可达25m）

– 每个Tx 的输出功率典型值为11dBm

– 12.5dB 典型噪声系数

– QSPI

– I2C

– JTAG

– GPIO

– 1MHz 时的典型相位噪声为-89dBc/Hz

– FMCW 运行

– PWM 接口

• 内部存储器

– 5MHz IF 带宽，仅实部Rx 通道

– 基于分数N PLL 的超精确线性调频脉冲引擎

– 每个发送器二进制移相器

– 1MB 片上RAM

– 用于雷达立方体的可配置L3 共享存储器

– (512/640/768KB) 的数据和代码RAM

• 处理要素

• 具有12 x 12、102 个BGA 焊球的FCCSP 封装

• 符合AEC Q-100 标准

• 时钟源

– 具有单精度FPU (160MHz) 的Arm^®M4F^®内核

– 用于FFT、对数幅度和CFAR 运算(80MHz) 的

TI 雷达硬件加速器(HWA 1.2)

• 支持多个低功耗模式

– 用于主时钟的40.0MHz 晶体

– 支持外部驱动、频率为40.0 MHz 的时钟（方波/

正弦波）

– 空闲模式和深度睡眠模式

• 电源管理

– 用于低功耗运行的32kHz 内部振荡器

– 1.8V 与3.3V IO 支持

• 支持工作温度范围

– 内置的LDO 网络，可增强PSRR

– BOM 优化模式和低功耗模式

– 一个或两个电源轨适用于1.8V IO 模式，两个或

三个电源轨适用于3.3V IO 模式

• 封装尺寸：6.45mm × 6.45mm 器件

• 内置校准和自检

– 工作结温范围：–40°C 至105°C

– 内置的固件(ROM)

– 片上自包含校准系统

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SWRS298

IWRL6432

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• 冰箱和冷冻柜

• 扫地机器人

• 割草机

2 应用

• 自动门

• 家庭影院

• 运动检测器

• 占位检测/人员跟踪/人数统计

• 可视门铃

• IP 网络摄像头

• 恒温器

• 空调

• PC/笔记本电脑

• 便携式电子产品

• 电视

• 平板电脑

3 说明

IWRL6432 毫米波传感器器件是一款基于 FMCW 雷达技术的集成式单芯片毫米波传感器。该器件能够在 57GHz

至64GHz 频段内运行，主要分为四个电源域：

• 射频/模拟子系统：该块包含发送和接收射频信号所需的所有射频和模拟元件。

• 前端控制器子系统(FECSS)：FECSS 包含负责雷达前端配置、控制和校准的处理器。

• 应用子系统(APPSS)：在APPSS 中，该器件实现了一个用户可编程的ARM Cortex M4，允许自定义控制和

汽车接口应用。顶部子系统(TOPSS) 是APPSS 电源域的一部分，包含时钟和电源管理子块。

• 硬件加速器(HWA)：HWA 块通过卸载通用雷达处理（例如FFT、恒定误报率(CFAR)、缩放和压缩）来对

APPSS 进行补充。

IWRL6432 专为上述每个电源域配备单独的旋钮，可根据用例要求控制其状态（上电或断电）。该器件还具有运

行各种低功耗状态（如睡眠和深度睡眠）的功能，其中低功耗睡眠模式是通过时钟门控和关闭器件的内部 IP 块来

实现的。该器件还提供了保留器件某些内容的选项，例如在此类情况下保留的应用图像或射频配置文件。

此外，该器件采用 TI 的低功耗 45nm RF CMOS 工艺制造，以超小的外形尺寸实现了出色的集成度。IWRL6432

专为工业（和个人电子产品）领域的低功耗、自监控、超精确雷达系统而设计，适用于楼宇/工厂自动化、商业/住

宅安全、个人电子产品、存在/运动检测以及用于人机界面的手势检测/识别等应用

封装信息

器件型号⁽¹⁾

封装尺寸⁽²⁾

托盘/卷带包装

封装

说明

IWRL6432QGAMF

FCCSP

6.45mm x

6.45mm

托盘

工业量产型号。以符合功能安全标准为目

标。数量少。

IWRL6432QGAMFR

FCCSP

6.45mm x

6.45mm

卷带包装

工业量产型号。以符合功能安全标准为目

标。数量多。

(1) 如需更多信息，请参阅节12

(2) 如需更多信息，请参阅节11.1

2

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4 功能方框图

图4-1. 功能方框图

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Table of Contents

8.12 Timing and Switching Characteristics..................... 26

9 Detailed Description......................................................46

9.1 Overview...................................................................46

9.2 功能方框图................................................................46

9.3 Subsystems.............................................................. 47

9.4 Other Subsystems.................................................... 52

9.5 Memory Partitioning Options.....................................53

9.6 Boot Modes...............................................................54

10 Applications, Implementation, and Layout............... 55

10.1 Application Information........................................... 55

10.2 Reference Schematic..............................................55

11 Device and Documentation Support..........................56

11.1 Device Nomenclature..............................................56

11.2 Tools and Software..................................................57

11.3 Documentation Support.......................................... 57

11.4 Support Resources................................................. 57

11.5 Trademarks............................................................. 57

11.6 Electrostatic Discharge Caution..............................58

11.7 Glossary..................................................................58

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 2

3 说明................................................................................... 2

4 功能方框图.........................................................................3

5 Revision History.............................................................. 4

6 Device Comparison.........................................................5

6.1 Related Products........................................................ 7

7 Terminal Configurations and Functions........................8

7.1 Pin Diagrams.............................................................. 8

7.2 Signal Descriptions..................................................... 9

8 Specifications................................................................ 17

8.1 Absolute Maximum Ratings...................................... 17

8.2 ESD Ratings............................................................. 17

8.3 Power-On Hours (POH)............................................17

8.4 Recommended Operating Conditions.......................18

8.5 Power Supply Specifications.....................................19

8.6 Power Save Modes...................................................21

8.7 Peak Current Requirement per Voltage Rail.............23

8.8 RF Specification........................................................24

8.9 Supported DFE Features..........................................25

8.10 CPU Specifications................................................. 26

8.11 Thermal Resistance Characteristics for FCCSP

Information.................................................................... 59

Package [AMF0102A]................................................. 26

5 Revision History

DATE

REVISION

NOTES

December 2022

*

Initial Release

4

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6 Device Comparison

The following table compares the features of radar devices.

表6-1. Device Features Comparison

FUNCTION

IWRL6432

IWR6843AOP

IWR6843 IWR6443 IWR1843 IWR1642 IWR1443

Antenna on Package (AOP)

Number of receivers

-

Yes

4

-

4

3

Number of transmitters

RF frequency range

2

3

3⁽¹⁾

2

3

60 to 64 GHz

60 to 64

GHz

60 to 64

GHz

76 to 81

GHz

76 to 81

GHz

76 to 81

GHz

57 to 64 GHz

On-chip memory

1.75MB

10

1.75MB

10

1.4MB

10

2MB

10

1.5MB

5

576KB

15

1MB

5

Max I/F (Intermediate

Frequency) (MHz)

Max real sampling rate (Msps)

25

12.5

6.25

37.5

12.5

-

Max complex sampling rate

(Msps)

12.5

18.75

Safety and Security

Functional Safety -Compliance SIL-2 Targeted

SIL-2

Yes

SIL-2

Yes

-

Device Security⁽²⁾

Processors

MCU

-

Yes

M4F

-

R4F

C674x

Yes

R4F

C674x

Yes

R4F

-

R4F

C674x

Yes

R4F

C674x

-

R4F

-

DSP

HWA

Yes

Peripherals

Serial Peripheral Interface

(SPI) ports

2

Yes

1

2

Yes

1

2

Yes

1

2

Yes

1

2

Yes

1

Yes

1

Quad Serial Peripheral

Interface (QSPI)

Yes

1

Inter-Integrated Circuit (I²C)

interface

Controller Area Network

(DCAN) interface

-

Yes

-

Yes

-

Controller Area Network (CAN-

FD) interface

Yes

Trace

-

Yes

-

Yes

-

Yes

-

PWM

Yes

DMM Interface

Hardware In Loop (HIL/DMM)

GPADC

-

Yes

RDIF

2

Yes

LVDS

2

Yes

LVDS

2

Yes

LVDS

2

Yes

LVDS

2

Yes

LVDS

2

-

Yes

LVDS

2

ADC Raw Data Capture

UART

1-V bypass mode

JTAG

N/A

Yes

2

Yes

3

Yes

3

Yes

2

Yes

2

Number of TX that can be

used simultaneously

3

Per Chirp configurable TX

phase shifter

BPM only

Yes⁽³⁾

BPM only BPM only

Yes⁽³⁾

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表6-1. Device Features Comparison (continued)

FUNCTION

IWRL6432

IWR6843AOP

IWR6843 IWR6443 IWR1843 IWR1642 IWR1443

Product Preview

(PP), Advance

Product

Information (AI), or

status

AI

PD⁽⁴⁾

Production Data

(PD)

(1) 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to

be fed on the V_OUTPA pin.

(2) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part

variants as indicated by the Device Type identifier in Section 3, Device Information table.

(3) 6 bits linear Phase Shifter.

(4) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty.

6

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6.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

mmWave sensors

TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less

power using the smallest footprint mmWave sensor portfolio for Industrial applications.

mmWave IWR

The Texas Instruments IWRxxxx family of mmWave Sensors are highly integrated and

built on RFCMOS technology operating in 57- to 64-GHz frequency band. The devices

have a closed-loop PLL for precise and linear chirp synthesis. The devices have a very

small-form factor, low power consumption, and are highly accurate. Industrial applications

from short to ultra short range can be realized using these devices.

Companion

products for

IWRL6432

Review products that are similar to this product.

Reference designs The IWRL6432 TI Designs Reference Design Library is a robust reference design library

for IWRL6432

spanning analog, embedded processor and connectivity. Created by TI experts to help

you jump-start your system design, all TI Designs include schematic or block diagrams,

BOMs, and design files to speed your time to market. Search and download designs at

ti.com/tidesigns.

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7 Terminal Configurations and Functions

7.1 Pin Diagrams

12

11

10

9

8

7

6

5

4

3

2

1

HOST_CLK

_REQ

M

L

VSS

VIOIN

VIOIN_18

VDD_SRAM

GPADC1

VDDA_18BB VDDA_12RF VDDA_10RF

VSSA

UARTA_TX

VIOIN_18

UARTA_RTS

NRESET

VNWA

VSS

VIOIN_18

GPADC2

VSSA

RX1

NERROR

_OUT

K

J

VDD

UARTA_RX

GPIO_5

GPIO_2

VIN_18PM

VBGAP

VSSA

RX2

PMIC

_CLKOUT

H

G

F

VSS

VDD

VSS

VOUT

_14APLL

VIOIN

TDI

RS232_RX

TDO

VDD

VSS

VDD

VSS

VSSA

RX3

VDDA

_18VCO

VSS

VSSA

E

D

C

B

A

TMS

RS232_TX

SPIA_CLK

VSSA_PM

VSSA

CLKP

VSSA

CLKM

SPIA_CS0

_N

VOUT

_14SYNTH

VIOIN

_18CLK

TCK

SPIA_MOSI

VSS

SPIA_MISO

QSPI[0]

VDD

VIOIN_18

QSPI[1]

VPP

QSPI[2]

QSPI[3]

VSS

VSSA

TX2

VSSA

TX1

OSC_CLK

_OUT

QSPI_CLK

QSPI_CS

VSSA

Not to scale

图7-1. BGA Pin Diagram (Top View)

8

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7.2 Signal Descriptions

备注

All digital IO pins of the device (except NRESET) are non-failsafe; hence, care needs to be taken that

they are not driven externally without the VIO supply being present to the device.

表7-1. Analog Signal Descriptions

SIGNAL NAME

DESCRIPTION

PIN TYPE

BGA PIN

CLKM

XTAL CLKM pin

XTAL CLKP pin

GPADC input 1

GPADC input 2

NRESET input

A

B1

D1

M6

L6

CLKP

GPADC1

GPADC2

NRESET

L10

A7

K1

H1

F1

A3

A5

H5

OSC_CLK_OUT

RX1

Oscillator Clock output

RX channel 1

RX2

RX channel 2

RX3

RX channel 3

TX1

TX channel 1

TX2

TX channel 2

VBGAP

VDDA_10RF

BandGap reference pin

Internal LDO output for RF Supply of 1.0V. External

Capacitor needed on this pin

L3, M3

VOUT_14APLL

1.4V LDO output. External Capacitor is needed on this

pin.

A

G5

VOUT_14SYNTH

1.4V LDO output. External Capacitor is needed on this

pin.

D3

表7-2. CAN Signal Descriptions

DESCRIPTION

SIGNAL NAME

PIN TYPE

BGA PIN

CAN_FD_RX

CAN_FD_TX

CAN Receive Data

I

J11

L12

CAN Transmit Data

O

表7-3. Clock Signal Descriptions

DESCRIPTION

SIGNAL NAME

PIN TYPE

BGA PIN

MCU_CLKOUT

MCU clock output

O

K11, M10

H11

PMIC_CLKOUT

PMIC clock output.

This also serves as a Sense On Power [Reset] Line.

Impacts boot mode SOP1.

RTC_CLK_IN

RTC clock input

I

B8, E12, H10, K11,

L11

表7-4. EPWM Signal Descriptions

DESCRIPTION

SIGNAL NAME

PIN TYPE

BGA PIN

C11, D11, G11, L11

B12, C12, D10, J10

E10, E12, J10

E12

EPWMA

EPWM Output A

O

I

EPWMB

EPWM Output B

EPWM_SYNC_IN

EPWM_SYNC_OUT

EPWM Sync Input

EPWM Sync output

O

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BGA PIN

表7-5. GPIO Signal Descriptions

DESCRIPTION

SIGNAL NAME

PIN TYPE

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

General Purpose Input/Output

IO

B12

C11

H10

J11

K11

J10

L11

M10

表7-6. I2C Signal Descriptions

DESCRIPTION

SIGNAL NAME

PIN TYPE

BGA PIN

I2C_SCL

I2C Clock

IO

B10, D10, E10, L12,

M10

I2C_SDA

I2C Data

IO

B9, D11, F11, H10,

J11

表7-7. JTAG Signal Descriptions

DESCRIPTION

SIGNAL NAME

PIN TYPE

BGA PIN

TCK

TDI

JTAG Test Clock Input

I

C12

G11

E11

JTAG Test Data Input

I

TDO

JTAG Test Data Output.

O

Also serves as a Sense On Power [Reset] Line Impacts

boot mode SOP0.

TMS

JTAG Test Mode Select Input

I

E12

表7-8. RDIF Signal Descriptions

DESCRIPTION

SIGNAL NAME

RDIF_CLK

PIN TYPE

BGA PIN

RDIF Clock

O

L11

H10

J11

RDIF_D0

RDIF data 0

RDIF_D1

RDIF data 1

RDIF_D2

RDIF data 2

L12

K11

M10

RDIF_D3

RDIF data 3

RDIF_FRM_CLK

RDIF Frame Clock

表7-9. Power Supply Signal Descriptions

DESCRIPTION

SIGNAL NAME

PIN TYPE

BGA PIN

VDD

1.2V Core supply

PWR

C9, G7, G8, G9, H8,

K7

VDDA_12RF

VDDA_18BB

VDDA_18VCO

VDD_SRAM

VIN_18PM

VIOIN

1.2V RF Supply

PWR

L4, M4

1.8V analog supply

1.2V SRAM supply

1.8V core supply

1.8V analog supply

L5, M5

F3

M7

J5

G12, M11

C8, K12, L8, M8

C6

VIOIN_18

VIOIN_18CLK

10

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表7-9. Power Supply Signal Descriptions (continued)

SIGNAL NAME

DESCRIPTION

1.2V VNWA supply. Always connected to SRAM supply

1.8V VPP supply

PIN TYPE

BGA PIN

VNWA

VPP

PWR

GND

L9

A8

VSS

Ground

A12, B7, E6, E7, E8,

E9, F6, F7, F8, F9,

H12, K9, M12

VSSA

Ground

GND

A1, A2, A4, A6, B2,

B3, B4, B5, B6, C1,

C2, D2, E1, E2, F2,

G1, G2, H2, J1, J2,

K2, L1, L2, M1, M2

VSSA_PM

E5

表7-10. QSPI Signal Descriptions

TYPE

SIGNAL NAME

DESCRIPTION

BGA PIN

QSPI Data bit 0

QSPI Data bit 1

QSPI Data bit 2

QSPI Data bit 3

QSPI clock

IO

I

B11

B8

QSPI_D0

QSPI_D1

QSPI_D2

QSPI_D3

QSPI_SCLK

QSPI_CS

I

B10

B9

I

IO

O

A11

A10

QSPI Chip select

表7-11. RS232 Debug Signal Descriptions

DESCRIPTION

SIGNAL NAME

PIN TYPE

BGA PIN

RS232_RX

RS232_TX

Debug UART (Operates as Bus Main) - Receive Signal

Debug UART (Operates as Bus Main) - Transmit Signal

I

F11

E10

O

表7-12. SPIA Signal Descriptions

DESCRIPTION

PIN TYPE

BGA PIN

SPIA_CLK

SPIA Clock

IO

D10

D11

C11

B12

SPIA_CS0_N

SPIA_MISO

SPIA_MOSI

SPIA Chip Select 0

SPIA MISO

SPIA MOSI

表7-13. SPIB Signal Descriptions

DESCRIPTION

SIGNAL NAME

PIN TYPE

BGA PIN

A11, D10

SPIB_CLK

SPIB Clock

IO

SPIB_CS0_N

SPIB_MISO

SPIB_MOSI

SPIB Chip Select 0

SPIB MISO

A10, D11

B8, C11

SPIB MOSI

B11, B12

表7-14. System Signal Descriptions

DESCRIPTION

SIGNAL NAME

PIN TYPE

BGA PIN

HOST_CLK_REQ

NERROR_OUT

SYNC_IN

Host clock request output

NERROR output signal

Sync input

O

I

M10

K11

B9, E12, J10, J11,

K11

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BGA PIN

表7-14. System Signal Descriptions (continued)

SIGNAL NAME

WARM_RESET_OUT

WU_REQIN

DESCRIPTION

PIN TYPE

Warm reset output

O

I

E12, H10

Wakeup Request input

B10, H10, K11, L11,

L12, M10

表7-15. UARTA Signal Descriptions

DESCRIPTION

SIGNAL NAME

UARTA_RTS

PIN TYPE

BGA PIN

UARTA RTS output

O

I

L11

J11

L12

UARTA_RX

UARTA Receive Data

UARTA_TX

UARTA Transmit Data

O

表7-16. UARTB Signal Descriptions

DESCRIPTION

SIGNAL NAME

UARTB_RX

PIN TYPE

BGA PIN

F11, J11

UARTB Receive Data

I

UARTB_TX

UARTB Transmit Data

O

E10, L12

12

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表7-17. Pin Muxing Table

BGA

BALL

PIN CNTL

PULL UP/

DOWN

PINCNTL

REGISTER

MODE TYPE

BALL STATE

BALL NAME⁽²⁾

SIGNAL NAME⁽³⁾

REGISTER⁽⁴⁾ADDRESS⁽⁵⁾

DURING RST⁽⁹⁾AFTER RST ⁽¹⁰⁾

(6)

(7)

NUMBER

TYPE⁽⁸⁾

(1)

(11)

H10

GPIO_2

PADAL_CFG_ 0x5A00

0

1

2

3

4

5

6

7

IO

I

PU/PD

OFF/OFF/OFF

REG

002C

LIN_RX

WARM_RESET_OUT

I2C_SDA

O

IO

I

SPIA_CS1_N

WU_REQIN

RTC_CLK_IN

MDO_D0

I

O

IO

I

J10

GPIO_5

PADAV_CFG_ 0x5A00 0054 0

REG

PU/PD

OFF/OFF/OFF

SYNC_IN

1

LIN_RX

2

3

4

5

I

EPWMB

O

I

EPWM_SYNC_IN

MDO_D3

O

IO

O

I

M10

HOST_CLK_REQ HOST_CLK_REQ

GPIO_7

PADAX_CFG_ 0x5A00

REG 005C

0

1

2

3

4

5

6

8

9

PU/PD

OFF/OFF/OFF

OFF/SS/OFF

MCU_CLKOUT

LIN_TX

WU_REQIN

SPIB_MISO

IO

O

IO

I

I2C_SCL

MDO_D3

MDO_FRM_CLK

K11

NERROR_OUT

GPIO_4

PADAU_CFG_ 0x5A00 0050 0

PU/PD

OFF/OFF/OFF

REG

1

SYNC_IN

2

SPIB_CS0_N

WU_REQIN

RTC_CLK_IN

MCU_CLKOUT

MDO_D3

3

IO

I

4

5

I

6

O

IO

O

IO

O

I

7

H11

PMIC_CLKOUT

LIN_TX

PADAK_CFG_ 0x5A00 0028 0

PU/PD

OFF/OFF/OFF

REG

1

SPIA_CS1_N

MDO_FRM_CLK

QSPI[0]

2

3

B11

B8

QSPI[0]

QSPI[1]

PADAC_CFG_ 0x5A00 0008 0

PU/PD

OFF/OFF/OFF

REG

SPIB_MOSI

MDO_D0

1

2

QSPI[1]

PADAD_CFG_ 0x5A00

REG 000C

0

1

2

3

SPIB_MISO

RTC_CLK_IN

MDO_D3

IO

I

O

I

B10

QSPI[2]

PADAE_CFG_ 0x5A00 0010 0

PU/PD

OFF/OFF/OFF

REG

I2C_SCL

1

IO

I

WU_REQIN

MDO_D1

2

3

O

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BALL STATE

表7-17. Pin Muxing Table (continued)

BGA

PIN CNTL

PULL UP/

DOWN

BALL

PINCNTL

REGISTER

MODE TYPE

BALL STATE

BALL NAME⁽²⁾

NUMBER

SIGNAL NAME⁽³⁾

REGISTER⁽⁴⁾ADDRESS⁽⁵⁾

DURING RST⁽⁹⁾AFTER RST ⁽¹⁰⁾

(6)

(7)

TYPE⁽⁸⁾

(1)

(11)

B9

QSPI[3]

PADAF_CFG_ 0x5A00 0014 0

I

PU/PD

OFF/OFF/OFF

REG

I2C_SDA

1

IO

I

SYNC_IN

MDO_D2

2

3

O

IO

O

IO

O

I

A11

A10

F11

QSPI_CLK

QSPI_CS

RS232_RX

QSPI_CLK

SPIB_CLK

MDO_CLK

QSPI_CS

SPIB_CS0_N

MDO_FRM_CLK

RS232_RX

I2C_SDA

PADAA_CFG_ 0x5A00 0000 0

REG

PU/PD

OFF/OFF/OFF

OFF/OFF/UP

OFF/OFF/OFF

OFF/OFF/UP

1

2

PADAB_CFG_ 0x5A00 0004 0

REG

1

2

PADAP_CFG_ 0x5A00

REG 003C

0

1

2

3

4

5

IO

I

UARTB_RX

LIN_RX

I

MDO_D2

O

IO

O

IO

O

I

SPIB_MISO

RS232_TX

I2C_SCL

E10

RS232_TX

PADAO_CFG_ 0x5A00 0038 0

REG

PU/PD

OFF/OFF/OFF

OFF/OFF/OFFI

1

UARTB_TX

LIN_TX

2

3

EPWM_SYNC_IN

MDO_D1

4

5

O

IO

O

IO

O

IO

O

IO

O

IO

O

IO

O

IO

O

IO

O

I

SPIB_CS1_N

SPIA_CLK

EPWMB

6

D10

D11

C11

B12

C12

SPIA_CLK

SPIA_CS0_N

SPIA_MISO

SPIA_MOSI

TCK

PADAG_CFG_ 0x5A00 0018 0

PU/PD

OFF/OFF/OFF

REG

1

I2C_SCL

2

3

4

SPIB_CLK

MDO_CLK

SPIA_CS0_N

EPWMA

PADAH_CFG_ 0x5A00

REG 001C

0

1

2

3

4

I2C_SDA

SPIB_CS0_N

MDO_D3

SPIA_MISO

GPIO_1

PADAJ_CFG_ 0x5A00 0024 0

REG

1

EPWMA

2

SPIB_MISO

MDO_D2

3

4

SPIA_MOSI

GPIO_0

PADAI_CFG_ 0x5A00 0020 0

REG

1

EPWMB

2

3

4

SPIB_MOSI

MDO_D1

TCK

PADAT_CFG_ 0x5A00

REG 004C

0

1

2

3

4

OFF/OFF/DOWN OFF/OFF/DOWN

EPWMB

O

IO

O

SPIB_CS1_N

SPIB_MOSI

MDO_D0

14

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表7-17. Pin Muxing Table (continued)

BGA

BALL

PIN CNTL

PULL UP/

DOWN

PINCNTL

REGISTER

MODE TYPE

BALL STATE

BALL NAME⁽²⁾

SIGNAL NAME⁽³⁾

REGISTER⁽⁴⁾ADDRESS⁽⁵⁾

DURING RST⁽⁹⁾AFTER RST ⁽¹⁰⁾

(6)

(7)

NUMBER

TYPE⁽⁸⁾

(1)

(11)

G11

TDI

PADAR_CFG_ 0x5A00 0044 0

I

PU/PD

OFF/OFF/DOWN OFF/OFF/DOWN

REG

EPWMA

1

O

IO

O

I

SPIB_CS0_N

TDO

2

E11

E12

TDO

TMS

PADAS_CFG_ 0x5A00 0048 0

REG

PU/PD

OFF/OFF/OFF

OFF/OFF/UP

OFF/OFF/OFF

OFF/OFF/UP

MDO_FRM_CLK

TMS

1

PADAQ_CFG_ 0x5A00 0040 0

REG

WARM_RESET_OUT

SPIA_CS1_N

SYNC_IN

1

O

IO

I

2

3

SPIB_MISO

SPIB_CLK

RTC_CLK_IN

EPWM_SYNC_IN

EPWM_SYNC_OUT

UART_RTS

GPIO_6

4

IO

I

5

6

7

I

8

O

IO

O

IO

I

L11

J11

L12

UARTA_RTS

UARTA_RX

UARTA_TX

PADAW_CFG_ 0x5A00 0058 0

PU/PD

OFF/OFF/OFF

REG

1

LIN_TX

2

SPIB_CLK

WU_REQIN

EPWMA

3

4

5

O

I

RTC_CLK_IN

MDO_CLK

UARTA_RX

GPIO_3

6

7

O

I

PADAM_CFG_ 0x5A00 0030 0

REG

1

IO

I

LIN_RX

2

CAN_FD_RX

SYNC_IN

3

I

4

I

UARTB_RX

I2C_SDA

5

I

6

IO

O

IO

I

MDO_D1

7

UARTA_TX

LIN_TX

PADAN_CFG_ 0x5A00 0034 0

REG

1

CAN_FC_TX

SPIB_MOSI

WU_REQIN

UARTB_TX

I2C_SCL

2

3

4

5

6

7

O

IO

O

MDO_D2

(1) BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.

(2) BALL NAME: Mechanical name from package device (name is taken from muxmode 0).

(3) SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).

(4) PINCNTL_REGISTER: APPSS Register name for PinMux Control

(5) PINCNTL ADDRESS: APPSS Address for PinMux Control

(6) MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode

column has bit range value.

(7) TYPE: Signal type and direction:

•

I = Input

O = Output

IO = Input or Output

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(8) PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be

enabled or disabled via software.

•

Pull Up: Internal pullup

Pull Down: Internal pulldown

An empty box means No pull.

(9) BALL STATE DURING RST: State of Ball during reset in the format of RX/TX/Pull Status

(10) BALL STATE AFTER RST: State of Ball after reset in the format of RX/TX/Pull Status

(11) Pin Mux Control Value maps to lower 4 bits of register.

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8 Specifications

8.1 Absolute Maximum Ratings

PARAMETERS^{(1) (2)}

1.2 V digital power supply

MIN

MAX

UNIT

VDD

1.4

V

–0.5

I/O supply (3.3 V or 1.8 V): All CMOS I/Os operate

on the same VIOIN voltage level

VIOIN

3.8

V

–0.5

VIOIN_18

VIN_18CLK

VIN_18BB

VIN_18VCO supply

RX1-3

1.8 V supply for CMOS IO

2

V

–0.5

1.8 V supply for clock module

2

1.8-V Analog baseband power supply

1.8-V RF VCO supply

2

V

2

V

Externally applied power on RF inputs

Externally applied power on RF outputs⁽³⁾

Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)

10

dBm

TX1-2

VIOIN + 0.3

VIOIN + 20% up to

–0.3V

Input and output

voltage range

V

Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V

(Transient Overshoot/Undershoot) or external oscillator input

20% of signal period

CLKP, CLKM

Clamp current

Input ports for reference crystal

2

V

–0.5

Input or Output Voltages 0.3 V above or below their respective

power rails. Limit clamp current that flows through the internal

diode protection cells of the I/O.

20

mA

–20

T_J

Operating junction temperature range

105

150

°C

–40

–55

T_STG

Storage temperature range after soldered onto PC board

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma = 1 can be applied on

the TX output.

8.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/

ESDA/JEDEC JS-001 ⁽¹⁾

All Pins

±2000

Electrostatic

discharge

V_(ESD)

V

All Pins

±500

±750

Charged-device model (CDM), per ANSI/

ESDA/JEDEC JS-002 ⁽¹⁾

Corner Pins

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

8.3 Power-On Hours (POH)

JUNCTION

OPERATING

CONDITION

TEMPERATURE (T_j)

NOMINAL CVDD VOLTAGE (V)

POWER-ON HOURS [POH] (HOURS)

(1)

105°C T_j

50% RF duty cycle

1.2

100,000

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard

terms and conditions for TI semiconductor products.

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8.4 Recommended Operating Conditions

MIN

1.14

3.135

1.71

1.17

2.25

NOM

1.2

3.3

1.8

MAX

UNIT

VDD

1.2 V digital power supply

1.26

3.465

1.89

V

I/O supply (3.3 V or 1.8 V):

All CMOS I/Os would operate on this supply.

VIOIN

V

VIOIN_18

VIN_18CLK

VIN18BB

1.8 V supply for CMOS IO

1.8 V supply for clock module

1.8-V Analog baseband power supply

1.8V RF VCO supply

V

VIN_18VCO

Voltage Input High (1.8 V mode)

Voltage Input High (3.3 V mode)

Voltage Input Low (1.8 V mode)

Voltage Input Low (3.3 V mode)

High-level output threshold (I_OH= 6 mA)

Low-level output threshold (I_OL= 6 mA)

V_IL(1.8V Mode)

V_IH

V_IL

V

0.3*VIOIN

0.62

V_OH

V_OL

mV

VIOIN –450

450

0.2

V_IH(1.8V Mode)

0.96

1.57

NRESET

SOP[1:0]

V

V_IL(3.3V Mode)

0.3

V_IH(3.3V Mode)

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8.5 Power Supply Specifications

8.5.1 Power Optimized 3.3V I/O Topology

表8-1 describes the power rails from an external power supply block to the device via a 3.3V I/O topology.

表8-1. Power Supply Rails Characteristics: Power Optimized 3.3V I/O Topology

SUPPLY

DEVICE BLOCKS POWERED FROM THE SUPPLY

RELEVANT IOs IN THE DEVICE

3.3 V

1.8 V

Digital I/Os

Input: VIOIN

Input: VDDA_18VCO, VIOIN_18CLK, VDDA_18BB,

VIOIN_18, VIN_18PM

LDO Output: VOUT_14SYNTH, VOUT_14APLL

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC

Input: VDD, VNWA, VDD_SRAM, VDDA_12RF

LDO Output: VDDA_10RF

1.2 V

Core Digital and SRAMs, RF

8.5.2 BOM Optimized 3.3V I/O Topology

表 8-2 describes the power rails from an external power supply block to the device via a BOM Optimized 3.3V

I/O Topology.

表8-2. Power Supply Rails Characteristics: BOM Optimized 3.3V I/O Topology

SUPPLY

DEVICE BLOCKS POWERED FROM THE SUPPLY

RELEVANT IOs IN THE DEVICE

3.3V

1.8V

Digital I/Os

Input: VIOIN

Input: VIN_18VCO, VIOIN_18CLK, VIN_18BB,

VIOIN_18, VIN_18PM

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC

LDO Output: VOUT_14SYNTH, VDDA_10RF,

VDD_SRAM, VOUT_14APLL, VDDA_12RF, VDD

8.5.3 Power Optimized 1.8V I/O Topology

表 8-3 describes the power rails from an external power supply block to the device via a power optimized 1.8V

I/O topology.

表8-3. Power Supply Rails Characteristics: Power Optimized 1.8V I/O Topology

SUPPLY

DEVICE BLOCKS POWERED FROM THE SUPPLY

RELEVANT IOs IN THE DEVICE

Input: VIOIN, VIN_18PM, VIN_18VCO, VIOIN_18CLK,

VIN_18BB, VIOIN_18

LDO Output: VOUT_14SYNTH, VOUT_14APLL

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC

1.8 V

1.2 V

Input: VDD, VDD_SRAM, VNWA

LDO Output: VDDA_10RF

Core Digital and SRAMs, RF, VNWA

8.5.4 BOM Optimized 1.8V I/O Topology

表8-4 describes the power rails from an external power supply block to the device via a BOM optimized 1.8V I/O

topology.

表8-4. Power Supply Rails Characteristics: BOM Optimized 1.8V I/O Topology

SUPPLY

DEVICE BLOCKS POWERED FROM THE SUPPLY

RELEVANT IOs IN THE DEVICE

Input: VIOIN, VIN_18VCO, VIOIN_18CLK, VIN_18BB,

VIOIN_18, VDDA_18BB, VIN_18PM, VDDA_18VCO

LDO Output: VDD, VDD_SRAM, VDDA_10RF,

VDDA_12RF, VOUT_14APLL, VOUT_14SYNTH

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC, Digital I/Os

1.8 V

8.5.5 System Topologies

The following the system topologies are supported.

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• Topology 1: Autonomous mode, with ability to wake-up external MCU

• Topology 2: Peripheral mode, under control of external MCU

图8-1. System Topologies

8.5.5.1 Power Topologies

The device supports two unique power topologies for BOM optimized and Power Optimized modes. Above

tables summarizes these options.

8.5.5.1.1 BOM Optimized Mode

In this mode the device can be powered using one 1.8V regulator OR using a 3.3V and a 1.8V regulator mode.

The choice of one rail vs two rails is dependent on the IO voltages needed.

图8-2. BOM Optimized Mode Power Management (Left: 1.8V I/O Topology, Right: 3.3V I/O Topology)

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8.5.5.1.2 Power Optimized Mode

This mode is for applications needing ultra-low power applications. The device can either be powered using two

rails (1.8 V and 1.2 V) or with three rails (3.3 V, 1.8 V and 1.2 V).

图8-3. Power Optimized Mode Power Management (Left: 1.8V I/O Topology, Right: 3.3V I/O Topology)

8.5.6 Noise and Ripple Specifications

The 1.8-V power supply ripple specifications mentioned in 表8-5 are defined to meet a target spur level of –105

dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB relationship, for example, a 1-

dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted are peak-peak levels for a

sinusoidal input applied at the specified frequency. These values are being optimized and are subject to change.

表8-5. Noise and Ripple Specifications

NOISE SPECIFICATION

RIPPLE SPECIFICATION

FREQ (kHZ)

1.8 V (mVpp)

1.2V (mVpp)1

1.996

1.8 V (µV/√Hz)

1.2V (µV/√Hz)1

44.987

26.801

28.393

9.559

10

100

6.057

2.677

2.388

0.757

0.419

0.179

0.0798

0.0178

0.035

0.760

0.955

0.504

0.379

0.153

0.079

0.017

2.233

200

3.116

500

1.152

1000

2000

5000

10000

1.182

0.532

1.256

0.561

0.667

0.297

0.104

0.046

1. 1.2V noise/ripple specification is only for power optimized supply configurations.

8.6 Power Save Modes

表8-6 lists the supported power states.

表8-6. Device Power States

Power State

Details

Active

Active Power State is when RF/chirping activity is ongoing

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表8-6. Device Power States (continued)

Details

Power State

Processing

Processing Power State is when data is being processed RF turned off⁽¹⁾

Idle

Idle Power State is during inter-frame/inter-burst/inter-chirp idle time

Lowest possible power state of the device where the contents of the device can be retained (Application

Image, Chirp Profile etc) and device need not boot from scratch again.

Deep Sleep

Device can enter this state after the frame processing is complete in order to save power significantly.

Deep sleep exit can be through a number of external wakeup sources and internal timing maintenance.

(1) The power consumed here also includes the Hardware Accelerator Power Consumption.

8.6.1 Typical Power Consumption Numbers

表8-7 lists the typical power consumption for each power save modes in different power topologies and antenna

configurations.

Below quoted power numbers in 表 8-7, 表 8-8 and 表 8-9 are based on initial silicon measurements and might

be subjected to change/improvement pertaining to further characterization

表8-7. Estimated Power Consumed in 3.3-V IO Mode

Power Consumption (mW)⁽¹⁾

Power Mode

Power Optimized Mode

BOM Optimized Mode

Active (2TX, 3RX)

Active (2TX, 2RX)

Active (1TX, 2RX)

987

874

707

1334

1271

1049

Sampling: 12.5 MSps,

Continuous Streaming Mode

(CW) mode

Freq =60 GHz

TX Power = 10dBm

RX gain = 30 dB

Active (1TX, 1RX)

Processing

655

159

986

233

APPSS CM4 = 20MHz, FECSS,

HWA powered off, SPI Interface

active

Idle

13.80

1.38

23.13

1.34

Deep sleep

Memory Retained = 114KB

(1) The Power consumption numbers are for a typical usecase i.e. for a Nominal device at 25C ambient temperature and nominal voltage

conditions.

表8-8. Estimated Power Consumed in 1.8-V IO Mode

Power Consumption (mW)

Power Mode

Power Optimized Mode

BOM Optimized Mode

Deep Sleep

0.640

0.780

表8-9. Use-Case Power Consumed in 3.3-V Power Optimized Topology

Parameter

Condition

Typical (mW)

RF Front End Configuration : 2TX, 3RX

5MHz Sampling Rate

Num of ADC samples = 64

Ramp End time = 19us

Chirp Idle Time = 6us

Average Power Consumption

(Presence Detection -Minor

Motion)

1Hz Update Rate

2.52

Chirp Slope = 32MHz/us

Number of chirps per burst = 8

Burst Periodicity = 300us

Number of bursts per frame = 1

Device configured to go to deep sleep state after active

operation. Memory Retained in deep sleep = 900KB

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8.7 Peak Current Requirement per Voltage Rail

表8-10 provides the max split rail current numbers.

表8-10. Maximum Peak Current per Voltage Rail

Maximum Current

Mode⁽¹⁾

IO Voltage⁽³⁾

(mA)

(2)

1.2 V: total current drawn 1.8 V: total current drawn 3.3 V: total current drawn

by all nodes driven by

1.2V rail

by all nodes driven by

1.8V rail

by all nodes driven by

3.3V rail

BOM Optimized

Power Optimized

3.3 V

1.8V

NA

1360

1450

270

90

NA

90

3.3 V

1.8 V

1100

270

NA

(1) Exercise full functionality of device, including 2TX, 3RX simultaneous operation, HWA, M4F and various host comm/interface

peripherals active (CAN, I2C, GPADC), test across full temperature range

(2) The specified current values are at typical supply voltage level.

(3) The exact VIOIN current depends on the peripherals used and their frequency of operation.

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8.8 RF Specification

Over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

12.5

–9

40

MAX UNIT

Noise figure

57 to 64 GHz

dB

dBm

dB

1-dB compression point (Out Of Band)⁽¹⁾

Maximum gain

Gain range

10

dB

Receiver

Gain step size

2

dB

IF bandwidth⁽²⁾

5

MHz

ADC sampling rate (real)

ADC resolution

12.5 Msps

Bits

12

11

26

Output Power

dBm

Transmitter

Power backoff range

Frequency range

Ramp rate

dB

57

64 GHz

Clock

subsystem

400 MHz/µs

dBc/Hz

Phase noise at 1-MHz offset

57 to 64 GHz

–89

(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone well below the lowest HPF cut-off frequency.

(2) The analog IF stages include high-pass filtering, with configurable first-order high-pass corner frequency. The set of available HPF

corners is summarized as follows:

Available HPF Corner Frequencies (kHz)

175, 350, 700, 1400

The filtering performed by the digital baseband chain is targeted to provide less than ±0.5 dB pass-band ripple/droop.

图8-4 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed.

图8-4. Noise Figure, In-band P1dB vs Receiver Gain

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8.9 Supported DFE Features

• TX output back-off

– From 0 dB to 26dB TX back-off in steps of 1dB is supported

– Binary Phase Modulation supported on each TX

• RX gain

– Real RX channels

– Total RX gain range of 30 dB to 40 dB, in 2 dB steps

• VCO

– Single VCO covering entire RF sweep bandwidth up to 7 GHz.

• High-pass filter

– Supports corner frequency options 175 KHz, 350 KHz, 700 KHz, 1400 KHz

– First-order high pass filter only

• Low-pass filter

– Max IF bandwidth supported is 5 MHz

– 40 dB stopband rejection, two filtering options supported

– 80% visibility –IF bandwidth is 80% of Nyquist and is 30% faster due to quicker settling time, compared

with 90% visibility

– 90% visibility –IF bandwidth is 90% of Nyquist (has longer setting time due to larger filter length)

• Supported ADC sampling rates

– 1.0, 1.25, 1.5625, 2.0, 2.5, 3.125, 4.0, 5.0, 6.25, 8.333, 10.0, 12.5Msps

• Timing Engine

– Support for chirps, bursts and frames

• Larger idle times can give more power saving

• Chirp accumulation (averaging) possible across closely spaced chirps to reduce memory requirement

– Provision for per-chirp dithering of parameters

图8-5. Chip Profile Supported by Timing Engine

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8.10 CPU Specifications

Over recommended operating conditions (unless otherwise noted)

PARAMETER

TYP

UNIT

Application

Subsystem (M4F

Family)

Clock Speed

160

512

256

MHz

Tightly Coupled Memory - A (Program + Data)

Shared L3 Memory⁽¹⁾

KB

Shared Memory

L3 Memory dedicated for HWA

(1) L3 memory is configurable

8.11 Thermal Resistance Characteristics for FCCSP Package [AMF0102A]

THERMAL METRICS^{(1) (4)}

°C/W^{(2) (3)}

8.5

Junction-to-case

RΘ_JC

RΘ_JB

RΘ_JA

Psi_JC

Psi_JB

6.2

Junction-to-board

Junction-to-free air

Junction-to-package top

Junction-to-board

24.7

0.36

6.2

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(4) Test Condition: Power=1.305W at 25°C

8.12 Timing and Switching Characteristics

8.12.1 Power Supply Sequencing and Reset Timing

The IWRL6432device expects all external voltage rails to be stable before reset is deasserted. 图 8-6 describes

the device wake-up sequence.

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A. MCU_CLK_OUT in autonomous mode, where IWRL6432 application is booted from the serial flash,

MCU_CLK_OUT is not enabled by default by the device bootloader.

图8-6. Device Wake-up Sequence

8.12.2 Synchronized Frame Triggering

The IWRL6432 device supports a hardware based mechanism to trigger radar frames. An external host can

pulse the SYNC_IN signal to start radar frames. The typical time difference between the rising edge of the

external pulse and the frame transmission on air (Tlag) is about 160 ns. There is also an additional

programmable delay that the user can set to control the frame start time.

T_{active_frame}

SYNC_IN

(Hardware

Trigger)

Radar

Frames

T_pulse

T_lag

Frame-2

Frame-1

图8-7. Sync In Hardware Trigger

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表8-11. Frame Trigger Timing

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

T_{active_frame}

Active frame duration

User defined

ns

< T_{active_frame}or

4000

T_pulse

25

8.12.3 Input Clocks and Oscillators

8.12.3.1 Clock Specifications

The IWRL6432 requires external clock source (that is, a 40-MHz crystal or external oscillator to CLKP) for initial

boot and as a reference for an internal APLL hosted in the device. An external crystal connected to the device

pins 图8-8 shows the crystal implementation.

C_f1

CLKP

C_p

40 MHz

CLKM

C_f2

图8-8. Crystal Implementation

备注

The load capacitors, C_f1and C_f2in 图 8-8, should be chosen such that 方程式 1 is satisfied. C_Lin the

equation is the load specified by the crystal manufacturer. All discrete components used to implement

the oscillator circuit should be placed as close as possible to the associated oscillator CLKP and

CLKM pins.

C _f2

C_L= C _f1

´

+C_P

C

_f1+C _f2

(1)

表8-12 lists the electrical characteristics of the clock crystal.

表8-12. Crystal Electrical Characteristics (Oscillator Mode)

NAME

DESCRIPTION

MIN

TYP

40

8

MAX

UNIT

MHz

pF

f_P

Parallel resonance crystal frequency

C_L

Crystal load capacitance

Crystal ESR

5

12

50

ESR

Ω

Temperature range Expected temperature range of operation

105

°C

–40

Frequency

Crystal frequency tolerance^{(1) (2) (3)}

tolerance

200

ppm

µW

–200

Drive level

50

(1) The crystal manufacturer's specification must satisfy this requirement.

(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

(3) Crystal tolerance affects radar sensor accuracy.

In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM

is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. 表 8-13 lists

the electrical characteristics of the external clock signal.

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表8-13. External Clock Mode Specifications

SPECIFICATION

PARAMETER

UNIT

MAX

MIN

TYP

Frequency

40

MHz

AC-Amplitude

700

0.00

1.6

1200

0.20

1.95

–132

–143

–152

–153

65

mV (pp)

ns

DC-V_il

DC-V_ih

ns

Input Clock:

Phase Noise at 1 kHz

Phase Noise at 10 kHz

Phase Noise at 100 kHz

Phase Noise at 1 MHz

Duty Cycle

dBc/Hz

%

External AC-coupled sine wave or DC-

coupled square wave Phase Noise

referred to 40 MHz

35

Freq Tolerance

-50

50

ppm

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8.12.4 MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)

The McSPI module is a multichannel transmit/receive, controller/peripheral synchronous serial bus

8.12.4.1 McSPI Features

The McSPI modules include the following main features:

• Serial clock with programmable frequency, polarity, and phase for each channel

• Wide selection of SPI word lengths, ranging from 4 to 32 bits

• Up to four channels in controller mode, or single channel in receive mode

• Controller multichannel mode:

– Full duplex/half duplex

– Transmit-only/receive-only/transmit-and-receive modes

– Flexible input/output (I/O) port controls per channel

– Programmable clock granularity

– Per channel configuration for clock definition, polarity enabling, and word width

• Single interrupt line for multiple interrupt source events

• Enable the addition of a programmable start-bit for McSPI transfer per channel (start-bit mode)

• Supports start-bit write command

• Supports start-bit pause and break sequence

• Programmable shift operations (1-32 bits)

• Programmable timing control between chip select and external clock generation

• Built-in FIFO available for a single channel

8.12.4.2 SPI Timing Conditions

表8-14 presents timing conditions for McSPI

表8-14. McSPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOAD

Output load capacitance

2

15

pF

8.12.4.3 SPI—Controller Mode

8.12.4.3.1 Timing and Switching Requirements for SPI - Controller Mode

表8-15 and 表8-15 present timing requirements for SPI - Controller Mode.

表8-15. SPI Timing Requirements - Controller Mode

NO.⁽¹⁾

MODE

MIN

MAX UNIT

(8)

SM4 t_{su(MISO-SPICLK)}

SM5 t_{h(SPICLK-MISO)}

Setup time, SPI_D[x] valid before SPI_CLK active edge

ns

5

(1)

Hold time, SPI_D[x] valid after SPI_CLK active edge ⁽¹⁾

3

ns

表8-16. SPI Switching Characteristics - Controller Mode

NO.⁽¹⁾

MODE

MIN

MAX UNIT

(8)

SM1 t_c(SPICLK)

SM2 t_w(SPICLKL)

Cycle time, SPI_CLK ^{(1) (2)}

24.6⁽³⁾

-1 +

ns

Typical Pulse duration, SPI_CLK low ⁽¹⁾

0.5P⁽³⁾

(4)

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表8-16. SPI Switching Characteristics - Controller Mode (continued)

NO.⁽¹⁾

MODE

MIN

MAX UNIT

(8)

SM3 t_w(SPICLKH)

Typical Pulse duration, SPI_CLK high ⁽¹⁾

-1 +

ns

0.5P⁽⁴⁾

SM6 t_{d(SPICLK-SIMO)}

Delay time, SPI_CLK active edge to SPI_D[x] transition

-2

ns

5

(1)

SM7 t_sk(CS-SIMO)

SM8 t_d(SPICLK-CS)

Delay time, SPI_CS[x] active to SPI_D[x] transition

Delay time, SPI_CS[x] active to SPI_CLK first edge

ns

5

Controller_PHA0_POL -4 + B⁽⁶⁾

0;

Controller_PHA0_POL

1;⁽⁵⁾

Controller_PHA1_POL -4 + A⁽⁷⁾

0;

Controller_PHA1_POL

1;⁽⁵⁾

ns

SM9 t_d(SPICLK-CS)

Delay time, SPI_CLK last edge to SPI_CS[x] inactive

Controller_PHA0_POL -4 + A⁽⁷⁾

0;

Controller_PHA0_POL

1;⁽⁵⁾

Controller_PHA1_POL -4 + B⁽⁶⁾

0;

Controller_PHA1_POL

1; ⁽⁵⁾

SM11 Cb

Capacitive load for each bus line

3

15

pF

(1) P = This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are being used to drive output data

and capture input data

(2) Related to the SPI_CLK maximum frequency

(3) 20 ns cycle time = 50 MHz

(4) P = SPICLK period

(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register

(6) B = (TCS + .5) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.

(7) When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.

When P > 20.8 ns, A = (TCS + 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.

(8) The IO timings provided in this section are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are only

valid for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.

This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are being used to

drive output data and capture input data

备注

Supported frequency of Radar SPI Peripheral mode is 40MHz in full cycle and 20MHz in Half cycle

mode.

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8.12.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode

PHA=0

EPOL=1

SPI_CS[x] (OUT)

SM1

SM3

SM8

SM2

SM9

POL=0

POL=1

SPI_SCLK (OUT)

SM1

SM3

SM2

SPI_SCLK (OUT)

SM5

SM4

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

SPI_D[x] (IN)

PHA=1

EPOL=1

SPI_CS[x] (OUT)

SPI_SCLK (OUT)

SM2

SM1

SM8

SM3

SM2

SM9

POL=0

POL=1

SM1

SM3

SPI_SCLK (OUT)

SM5

SM4

SM5

Bit n-2

SM4

Bit n-1

Bit n-3

Bit 1

Bit 0

SPI_D[x] (IN)

SPRSP08_TIMING_McSPI_02

图8-9. SPI Timing -Controller Mode Receive

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PHA=0

EPOL=1

SPI_CS[x] (OUT)

SM1

SM3

SM8

SM2

SM9

POL=0

POL=1

SPI_SCLK (OUT)

SM1

SM3

SM2

SPI_SCLK (OUT)

SPI_D[x] (OUT)

SM7

Bit n-1

SM6

Bit n-2

SM6

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_CS[x] (OUT)

SPI_SCLK (OUT)

SM1

SM2

SM8

SM3

SM2

SM9

POL=0

POL=1

SM1

SM3

SPI_SCLK (OUT)

SPI_D[x] (OUT)

SM6

Bit n-1

SM6

Bit n-2

SM6

Bit n-3

SM6

Bit 1

Bit0

SPRSP08_TIMING_McSPI_01

图8-10. SPI Timing- Controller Mode Transmit

8.12.4.4 SPI—Peripheral Mode

8.12.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode

表8-17 and 表8-18 present timing requirements for SPI -Peripheral Mode.

表8-17. SPI Timing Requirements - Peripheral Mode

NO.^{(1) (3)}PARAMETER

DESCRIPTION

MIN

24.6

MAX

UNIT

ns

SS1

SS2

SS3

SS4

t_c(SPICLK)

Cycle time, SPI_CLK

t_w(SPICLKL)

t_w(SPICLKH)

t_{su(SIMO-SPICLK)}

Typical Pulse duration, SPI_CLK low

Typical Pulse duration, SPI_CLK high

Setup time, SPI_D[x] valid before SPI_CLK active edge

0.45*P⁽²⁾

ns

3

SS5

t_{h(SPICLK-SIMO)}

Hold time, SPI_D[x] valid after SPI_CLK active edge

ns

1

5

1

SS8

SS9

t_{su(CS-SPICLK)}

t_h(SPICLK-CS)

sr

Setup time, SPI_CS[x] valid before SPI_CLK first edge

Hold time, SPI_CS[x] valid after SPI_CLK last edge

Input Slew Rate for all pins

ns

SS10

SS11

3

Cb

Capacitive load on D0 and D1

2

15

pF

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表8-18. SPI Switching Characteristics Peripheral Mode

DESCRIPTION

NO.

PARAMETER

MIN

MAX

5.77

UNIT

SS6

t_{d(SPICLK-SOMI)}

Delay time, SPI_CLK active edge to McSPI_somi transition

0

ns

SS7

t_sk(CS-SOMI)

Delay time, SPI_CS[x] active edge to McSPI_somi transition

ns

5.77

(1) P = This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and

capture input data.

(2) P = SPICLK period.

(3) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

8.12.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode

PHA=0

EPOL=1

SPI_CS[x] (IN)

SS1

SS2

SS8

SS3

SS9

POL=0

POL=1

SPI_SCLK (IN)

SS1

SS2

SS5

SS4

SS5

Bit n-2

SS4

Bit n-1

Bit n-3

Bit n-4

Bit 0

SPI_D[x] (IN)

PHA=1

EPOL=1

SPI_CS[x] (IN)

SS1

SS2

SS8

SS3

SS2

SS9

POL=0

POL=1

SPI_SCLK (IN)

SS1

SS3

SS4

SS5

SS4

SS5

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

SPI_D[x] (IN)

SPRSP08_TIMING_McSPI_04

图8-11. SPI Timing - Peripheral mode Receive

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PHA=0

EPOL=1

SPI_CS[x] (IN)

SS1

SS2

SS8

SS3

SS9

POL=0

POL=1

SPI_SCLK (IN)

SS1

SS2

SPI_SCLK (IN)

SPI_D[x] (OUT)

SS7

Bit n-1

SS6

Bit n-2

SS6

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_CS[x] (IN)

SPI_SCLK (IN)

SS1

SS2

SS8

SS3

SS2

SS9

POL=0

POL=1

SS1

SS3

SPI_SCLK (IN)

SPI_D[x] (OUT)

SS6

Bit n-1

SS6

Bit n-2

SS6

Bit n-3

SS6

Bit 1

Bit 0

SPRSP08_TIMING_McSPI_03

图8-12. SPI Timing - Peripheral mode Transmit

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8.12.5 RDIF Interface Configuration

The supported Radar Data InterFace (RDIF) is developed as a debug interface (for example: to capture raw

ADC data) and not as a production interface. The RDIF has four data lanes, one Bit Clock lane, and one Frame

Clock lane. From this interface, high-speed data is sent out for debug purposes. The RDIF interface supports the

following data rates⁽¹⁾:

• 400 Mbps

• 320 Mbps

• 200 Mbps

• 160 Mbps

• 100 Mbps

1. Aggregated data rate over four data lanes.

8.12.5.1 RDIF Interface Timings

图8-13. RDIF Timing Requirements

表8-19. Timing Requirements for RDIF Interface

PARAMETER

DESCRIPTION

MIN

MAX UNIT

No.

MODE

Bit Interval, RDIF_d[x]

SM1

SM2

Tb (RDIF_D[x])

Internal Clock

9.6

ns

Tvb

Data valid time, RDIF_d[x]

and RDIF_frm_clk valid

before RDIF_clk active

edge

(RDIF_D[x] - RDIF_CLK)

Internal Clock

4.8

ns

Tva

SM3

SM4

Data valid time, RDIF_d[x]

valid after RDIF_clk active

edge

(RDIF_CLK - RDIF_D[x])

C_b

Capacitive load for each

bus line

pF

3

15

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8.12.5.2 RDIF Data Format

图8-14. RDIF Data Format

• The samples are sent one channel by one channel as shown in the diagram above. All the 12-bits of one

channel are sent on 4 data lanes in 3 DDR_CLK edges, followed by next RX channel.

• The frame clock (FRM_CLK) spans 12 DDR_CLK edges and 48 bits are sent in 1 FRM_CLK

• The FRM_CLK can have gaps in between. This is required as the interface rate is greater than the incoming

rate

• DDR_CLK is continuous.

• DDR_CLK is generated from 400MHz ADC CLK (one of the ADC CLKs) - selected for the DFE. It is the same

400MHz clock selected for DFE.

• New sample always starts at the rise edge of the DDR_CLK

• The FRM_CLK is valid for the entire data bit and is meets the Tsu/Th wrt DDR_CLK.

8.12.6 General-Purpose Input/Output

8.12.6.1 Switching Characteristics for Output Timing versus Load Capacitance (C_L)

表8-20 lists the switching characteristics of output timing relative to load capacitance.

表8-20. Switching Characteristics for Output Timing versus Load Capacitance (C_L)

PARAMETER^{(1) (2)}

TEST CONDITIONS

C_L= 20 pF

VIOIN = 1.8V

VIOIN = 3.3V

UNIT

2.8

6.4

9.4

2.8

6.4

9.4

3.0

6.9

10.2

2.8

6.6

9.8

t_r

Max rise time

C_L= 50 pF

ns

C_L= 75 pF

Slew control = 0

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

t_f

Max fall time

ns

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表8-20. Switching Characteristics for Output Timing versus Load Capacitance (C_L) (continued)

PARAMETER^{(1) (2)}

TEST CONDITIONS

VIOIN = 1.8V

VIOIN = 3.3V

UNIT

C_L= 20 pF

3.3

6.7

9.6

3.1

6.6

9.6

3.3

7.2

10.5

3.1

6.6

9.6

t_r

Max rise time

C_L= 50 pF

ns

C_L= 75 pF

Slew control = 1

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

t_f

Max fall time

ns

(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).

(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.

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8.12.7 Controller Area Network - Flexible Data-rate (CAN-FD)

The CAN-FD module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications.

CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD

devices can coexist on the same network without any conflict.

The CAN-FD has the following features:

• Conforms with CAN Protocol 2.0 A, B and ISO 11898-1

• Full CAN FD support (up to 64 data bytes per frame)

• AUTOSAR and SAE J1939 support

• Up to 32 dedicated Transmit Buffers

• Configurable Transmit FIFO, up to 32 elements

• Configurable Transmit Queue, up to 32 elements

• Configurable Transmit Event FIFO, up to 32 elements

• Up to 64 dedicated Receive Buffers

• Two configurable Receive FIFOs, up to 64 elements each

• Up to 128 11-bit filter elements

• Internal Loopback mode for self-test

• Mask-able interrupts, two interrupt lines

• Two clock domains (CAN clock / Host clock)

• Parity / ECC support - Message RAM single error correction and double error detection (SECDED)

mechanism

• Full Message Memory capacity (4352 words).

8.12.7.1 Dynamic Characteristics for the CANx TX and RX Pins

PARAMETER

MIN

TYP

MAX

UNIT

t_{d(CAN_FD_tx)}

t_{d(CAN_FD_rx)}

Delay time, transmit shift register to CAN_FD_tx

pin⁽¹⁾

15

ns

Delay time, CAN_FD_rx pin to receive shift

register⁽¹⁾

15

ns

(1) These values do not include rise/fall times of the output buffer.

8.12.8 Serial Communication Interface (SCI)

The SCI has the following features:

• Standard universal asynchronous receiver-transmitter (UART) communication

• Supports full- or half-duplex operation

• Standard non-return to zero (NRZ) format

• Double-buffered receive and transmit functions in compatibility mode

• Supports two individually enabled interrupt lines: level 0 and level 1

• Configurable frame format of 3 to 13 bits per character based on the following:

– Data word length programmable from one to eight bits

– Additional address bit in address-bit mode

– Parity programmable for zero or one parity bit, odd or even parity

– Stop programmable for one or two stop bits

• Asynchronous or iso-synchronous communication modes with no CLK pin

• Two multiprocessor communication formats allow communication between more than two devices

• Sleep mode is available to free CPU resources during multiprocessor communication and then wake up to

receive an incoming message

• Capability to use Direct Memory Access (DMA) for transmit and receive data

• Five error flags and Seven status flags provide detailed information regarding SCI events

• Two external pins: RS232_RX and RS232_TX

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• Multi-buffered receive and transmit units

8.12.8.1 SCI Timing Requirements

MIN

TYP

MAX

UNIT

f(baud)

Supported baud rate at 20 pF

TBD

kHz

8.12.9 Inter-Integrated Circuit Interface (I2C)

The inter-integrated circuit (I2C) module is a multi-controller communication module providing an interface

between devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an

I²C-bus™. This module will support any target or controller I2C compatible device.

The I2C has the following features:

• Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398

393 40011)

– Bit/Byte format transfer

– 7-bit and 10-bit device addressing modes

– START byte

– Multi-controller transmitter/ target receiver mode

– Multi-controller receiver/ target transmitter mode

– Combined controller transmit/receive and receive/transmit mode

– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)

• Free data format

• Two DMA events (transmit and receive)

• DMA event enable/disable capability

• Module enable/disable capability

• The SDA and SCL are optionally configurable as general purpose I/O

• Slew rate control of the outputs

• Open drain control of the outputs

• Programmable pullup/pulldown capability on the inputs

• Supports Ignore NACK mode

备注

This I2C module does not support:

• High-speed (HS) mode

• C-bus compatibility mode

• The combined format in 10-bit address mode (the I2C sends the target address second byte every

time it sends the target address first byte)

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8.12.9.1 I2C Timing Requirements

STANDARD MODE⁽¹⁾

FAST MODE

UNIT

MIN

10

MAX

MIN

2.5

MAX

t_c(SCL)

Cycle time, SCL

μs

t_{su(SCLH-SDAL)}

Setup time, SCL high before SDA low

(for a repeated START condition)

4.7

0.6

t_h(SCLL-SDAL)

Hold time, SCL low after SDA low

4

0.6

μs

(for a START and a repeated START condition)

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

μs

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

t_h(SCLL-SDA)

t_w(SDAH)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

0

3.45⁽¹⁾

0.9

Pulse duration, SDA high between STOP and START

conditions

4.7

1.3

t_{su(SCLH-SDAH)}

t_w(SP)

Setup time, SCL high before SDA high

(for STOP condition)

4

0.6

0

μs

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

50

ns

(2) (3)

C_b

400

pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum t_h(SDA-SCLL)for I2C bus devices has only to be met if the device does not stretch the low period (t_w(SCLL)) of the SCL

signal.

(3) C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

图8-15. I2C Timing Diagram

备注

• A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the

VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

• The maximum t_h(SDA-SCLL)has only to be met if the device does not stretch the LOW period

(t_w(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-mode I2C-

bus system, but the requirement t_su(SDA-SCLH)≥250 ns must then be met. This will automatically

be the case if the device does not stretch the LOW period of the SCL signal. If such a device does

stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max +

t_su(SDA-SCLH)

.

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8.12.10 Quad Serial Peripheral Interface (QSPI)

The quad serial peripheral interface (QSPI) module is a kind of SPI module that allows single, dual, or quad read

access to external SPI devices. This module has a memory mapped register interface, which provides a direct

interface for accessing data from external SPI devices and thus simplifying software requirements. The QSPI

works as a controller only. The QSPI in the device is primarily intended for fast booting from quad-SPI flash

memories.

The QSPI supports the following features:

• Programmable clock divider

• Six-pin interface

• Programmable length (from 1 to 128 bits) of the words transferred

• Programmable number (from 1 to 4096) of the words transferred

• Optional interrupt generation on word or frame (number of words) completion

• Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles

节8.12.10.2 and 节8.12.10.3 assume the operating conditions stated in 节8.12.10.1.

8.12.10.1 QSPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOAD

Output load capacitance

2

15

pF

8.12.10.2 Timing Requirements for QSPI Input (Read) Timings

MIN^{(1) (2)}

5

TYP

MAX

UNIT

ns

t_su(D-SCLK)

t_h(SCLK-D)

t_su(D-SCLK)

t_h(SCLK-D)

Setup time, d[3:0] valid before falling sclk edge

Hold time, d[3:0] valid after falling sclk edge

1

ns

5 –P⁽³⁾

1 + P⁽³⁾

Setup time, final d[3:0] bit valid before final falling sclk edge

Hold time, final d[3:0] bit valid after final falling sclk edge

ns

(1) Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.

(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although non-

standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Mode 0.

(3) P = SCLK period in ns.

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8.12.10.3 QSPI Switching Characteristics

NO.

Q1

Q2

Q3

PARAMETER

Cycle time, sclk

MIN

12.5

TYP

MAX

UNIT

ns

t_c(SCLK)

Y*P –3^{(1) (2)}

t_w(SCLKL)

t_w(SCLKH)

t_d(CS-SCLK)

Pulse duration, sclk low

ns

Pulse duration, sclk high

ns

–M*P –1⁽²⁾

–M*P + 2.5⁽²⁾

Delay time, sclk falling edge to cs active edge

ns

Q4

Q5

(3)

t_d(SCLK-CS)

Delay time, sclk falling edge to cs inactive edge

N*P + 2.5⁽²⁾

ns

N*P –1^{(2) (3)}

(3)

t_d(SCLK-D1)

t_ena(CS-D1LZ)

t_dis(CS-D1Z)

t_d(SCLK-D1)

Delay time, sclk falling edge to d[1] transition

Enable time, cs active edge to d[1] driven (lo-z)

Disable time, cs active edge to d[1] tri-stated (hi-z)

ns

Q6

Q7

Q8

4

–P +1⁽²⁾

–2

–P –4⁽²⁾

Delay time, sclk first falling edge to first d[1] transition

(for PHA = 0 only)

–2 –P⁽²⁾

4–P⁽²⁾

Q9

Q12

Q13

t_su(D-SCLK)

t_h(SCLK-D)

t_su(D-SCLK)

Setup time, d[3:0] valid before falling sclk edge

Hold time, d[3:0] valid after falling sclk edge

5

1

ns

Setup time, final d[3:0] bit valid before final falling

sclk edge

5 —P⁽²⁾

Q14

Q15

t_h(SCLK-D)

Hold time, final d[3:0] bit valid after final falling sclk

edge

ns

1 + P⁽²⁾

(1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals

(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle

distortion. All required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.

(2) P = SCLK period in ns.

(3) M = QSPI_SPI_DC_REG.DDx + 1, N = 2

图8-16. QSPI Read (Clock Mode 0)

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PHA=0

cs

Q5

Q4

Q1

Q2

Q3

POL=0

sclk

Q8

Q6

Q7

Q9

Q6

Command

Bit n-1

Command

Bit n-2

Write Data

Bit 1

Write Data

Bit 0

d[0]

d[3:1]

SPRS85v_TIMING_OSPI1_04

图8-17. QSPI Write (Clock Mode 0)

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8.12.11 JTAG Interface

节8.12.11.2 and 节8.12.11.3 assume the operating conditions stated in 节8.12.11.1.

8.12.11.1 JTAG Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOAD

Output load capacitance

2

15

pF

8.12.11.2 Timing Requirements for IEEE 1149.1 JTAG

NO.

MIN

TYP

MAX

UNIT

ns

1

t_c(TCK)

Cycle time TCK

66.66

20

1a

1b

t_w(TCKH)

Pulse duration TCK high (40% of tc)

Pulse duration TCK low(40% of tc)

Input setup time TDI valid to TCK high

Input setup time TMS valid to TCK high

Input hold time TDI valid from TCK high

Input hold time TMS valid from TCK high

ns

t_w(TCKL)

20

ns

t_su(TDI-TCK)

t_su(TMS-TCK)

t_h(TCK-TDI)

t_h(TCK-TMS)

2.5

18

ns

3

4

ns

18

ns

8.12.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG

NO.

PARAMETER

MIN

TYP

MAX

UNIT

2

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

0

15

ns

1

1a

1b

TCK

TDO

2

3

4

TDI/TMS

SPRS91v_JTAG_01

图8-18. JTAG Timing

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9 Detailed Description

9.1 Overview

The IWRL6432 device is a complete SOC which include mmWave front end, customer programmable MCU and

analog baseband signal chain for two transmitters and three receivers. This device is applicable as a radar-on-a-

chip in use-cases with quality provision for memory, processing capacity and application code size. Use-cases

include cost-effective industrial radar sensing applications. Examples are:

•Industrial-level sensing

•Industrial automation sensor fusion with radar

•Traffic intersection monitoring with radar

•Industrial radar-proximity monitoring

•People counting

•Gesturing

In terms of scalability, the IWRL6432 device could be paired with a low-end external MCU to address more

complex applications that might require additional memory for a larger application software footprint and faster

interfaces.

9.2 功能方框图

图9-1. 功能方框图

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9.3 Subsystems

9.3.1 RF and Analog Subsystem

The RF and analog subsystem includes the RF and analog circuitry –namely, the synthesizer, PA, LNA, mixer,

IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The two TX can be

operated simultaneously for beam forming in BPM mode or individually in TDM mode. Similarly, the device

allows configuring the number of receive channels based on application and power requirements. For system

power saving, RF and analog subsystems can be put into low power mode configuration.

9.3.2 Clock Subsystem

The IWRL6432 clock subsystem generates 57 to 64 GHz from an input reference from a crystal. It has a built-in

oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF synthesizer is

then processed by an X3 multiplier to create the required frequency in the 57 to 64 GHz spectrum. The RF

synthesizer output is modulated by the timing engine block to create the required waveforms for effective sensor

operation.

The clean-up PLL also provides a reference clock for the host processor after system wakeup.

The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the

quality of the generated clock.

图9-2 describes the clock subsystem.

图9-2. Clock Subsystem

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9.3.3 Transmit Subsystem

The IWRL6432 transmit subsystem consists of two parallel transmit chains, each with independent phase and

amplitude control. The device supports binary phase modulation for MIMO radar, TX Beam forming application,

and interference mitigation.

The transmit chains also support programmable backoff for system optimization.

图9-3 describes the transmit subsystem.

图9-3. Transmit Subsystem (Per Channel)

9.3.4 Receive Subsystem

The IWRL6432 receive subsystem consists of three parallel channels. A single receive channel consists of an

LNA, mixer, IF filtering, ADC conversion, and decimation. All three receive channels can either operate

simultaneously OR can be powered down individually based on system power needs and application design.

The IWRL6432 device supports a real baseband architecture, which uses real mixer, single IF and ADC chains

to provide output for each receiver channel. The device is targeted for fast chirp systems. The band-pass IF

chain has configurable lower cutoff frequencies above 175 kHz and can support bandwidths up to 5 MHz.

图9-4 describes the receive subsystem.

图9-4. Receive Subsystem (Per Channel)

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9.3.5 Processor Subsystem

图9-5. Processor Subsystem

图 9-5 shows the block diagram for customer programmable processor subsystems in the IWRL6432 device. At

a high level there are two customer programmable subsystems, as shown separated by a dotted line in the

diagram. The left hand side shows the HWA, a high-bandwidth interconnect for high performance (64-bit,

80MHz), and associated peripherals data transfer. RDIF interface for Measurement data output, L3 Radar data

cube memory, the ADC buffers, the CRC engine, and data handshake memory (additional memory provided on

interconnect).

The right side of the diagram shows the Main Subsystem. The Main Subsystem is the brain of the device and

controls all the device peripherals and house-keeping activities of the device. The Main Subsystem contains

Cortex-M4F processor and associated peripherals and house-keeping components such as DMAs, CRC and

Peripherals (I²C, UART, SPIs, CAN, PMIC clocking module, PWM, and others) connected to Main Interconnect

through Peripheral Central Resource (PCR interconnect).

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9.3.6 Host Interface

The host interface can be provided through a SPI, UART, or CAN-FD interface. In some cases the serial

interface for industrial applications is transcoded to a different serial standard.

The IWRL6432 device communicates with the host radar processor over the following main interfaces:

• Reference Clock –Reference clock available for host processor after device wakeup

• Control –4-port standard SPI (peripheral) for host control . All radio control commands (and response) flow

through this interface.

• Reset –Active-low reset for device wakeup from host.

• Host Interrupt - an indication that the mmWave sensor needs host interface

• Error –Used for notifying the host in case the radio controller detects a fault

9.3.7 Main Subsystem Cortex-M4F

The main system includes an ARM Cortex M4F processor clocked with a maximum operating frequency of 160

MHz. User applications executing on this processor control the overall operation of the device, including radar

control through well-defined API messages, radar signal processing (assisted by the radar hardware

accelerator), and peripherals for external interfaces.

See the Technical Reference Manual for a complete description and memory map.

9.3.8 Hardware Accelerator (HWA1.2) Features

• Fast FFT computation, with programmable 2^Nsizes, up to 1024-point complex FFT

• Internal FFT bit-width of 24 bits (each for I and Q) for good Signal-to-Quantization-Noise Ratio (SQNR)

performance

• Fully programmable butterfly scaling at every radix-2 stage for user flexibility

• Built-in capabilities for pre-FFT processing –Ex: DC estimation and subtraction

• DC estimation & subtraction, Interference estimation & zero-out, Real window, Complex pre-multiplication

• Magnitude (absolute value) and Log-magnitude computation

• Flexible data flow and data sample arrangement to support efficient multi-dimensional FFT operations and

transpose accesses

• Chaining and looping mechanism to sequence a set of operations one after another with minimal intervention

from the main processor

• Peak detection –CFAR (CFAR-CA, CFAR-OS) detector

• Basic statistics, including Sum and 1D Max

• Compression engine for radar cube memory optimization

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图9-6. HWA 1.2 Functional Block Diagram

9.3.8.1 Hardware Accelerator Feature Differences Between HWA1.1 and HWA1.2

HWA1.0, HWA1.1

(xWR1843, xWR6843)

HWA1.2

(xWRL6432)

Feature

FFT sizes

1024, 512, 256, ...

24-bit I, 24-bit Q

1024, 512, 256, ...

Internal bit-width

24-bit I, 24-bit Q

FFT features

Configurable butterfly scaling at

each stage

Configurable butterfly scaling at

each stage

FFT stitching

up to 4096 point

1312 clock cycles

1320 clock cycles

FFT benchmark for four 256-pt FFTs

(6.56 µs at 200 MHz)

(16.5 µs at 80 MHz)

No. of parameter-sets

Local memory

16

32

64KB

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HWA1.0, HWA1.1

(xWR1843, xWR6843)

HWA1.2

(xWRL6432)

Feature

•

A and B-dim addressing of

local memory

•

A and B-dim addressing of

local memory

Input and Output formatter

Programmable scaling

•

Programmable scaling

DC estimation and

subtraction

•

Interference zero out with

fixed threshold, based on

magnitude

•

Interference zero out with

adaptive statistics, based on

mag, mag-diff. Interference

count indication.

Pre-FFT processing

•

Complex multiplication (7

modes)

•

Complex multiplication (7

modes)

Real window coefficients

Log-magnitude (0.06 dB

accuracy)

Post-FFT processing

Log-magnitude (0.3 dB accuracy)

Not available in HWA1.0

Compression and De-compression support

(xWR1843), Available in HWA1.1 Available

(xWR6843)

•

CFAR-CA (linear and log

modes)

Detection

Statistics

CFAR-CA (linear and log modes)

1D Sum, 1D Max

•

CFAR-OS (window size up to

32 on each side)

1D Sum, 1D Max

9.4 Other Subsystems

9.4.1 GPADC Channels (Service) for User Application

The IWRL6432 device includes provision for an ADC service for user application, where the GPADC engine

present inside the device can be used to measure up to two external voltages. The GPADC1, and GPADC2 pins

are used for this purpose.

• GPADC itself is controlled by TI firmware running inside the FEC subsystem and access to it for customer’s

external voltage monitoring purpose is via ‘APPSS’calls routed to the FEC subsystem. This API could be

linked with the user application running on MSS M4F.

• Device Firmware package (DFP) provides APIs to configure and measure these signals. The API allows

configuring the settling time (number of ADC samples to skip) and number of consecutive samples to take. At

the end of a frame, the minimum, maximum and average of the readings will be reported for each of the

monitored voltages.

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图9-7. GPADC Path

GPADC structures are used for measuring the output of internal temperature sensors. The accuracy of these

measurements is ±7°C.

9.4.2 GPADC Parameters

PARAMETER

TYP

1.8

UNIT

V

ADC supply

ADC unbuffered input voltage range

ADC buffered input voltage range⁽¹⁾

ADC resolution

V

0 –1.8

0.4 –1.3

8

V

bits

ADC offset error

ADC gain error

ADC DNL

±5

LSB

Ksps

–1/+2.5

±2.5

ADC INL

ADC sample rate⁽²⁾

831

ADC sampling time⁽²⁾

300

10

2

ns

pF

uA

ADC internal cap

ADC buffer input capacitance

ADC input leakage current

3

(1) Outside of given range, the buffer output will become nonlinear.

(2) GPADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.

9.5 Memory Partitioning Options

IWRL6432 devices will have a total memory of 1MB. The L3 memory has two memory banks and can be

associated with radar cube memory or with the Cortex-M4F RAM.

表9-1. Memory Partition Options

Config 1

Config 2

Config 3

Includes data cube,

detection matrix, heatmap

Radar data memory* (L3)

256KB

384kB

512KB

Application

Includes drivers,

mmWavelink, BIOS

768KB

640KB

512KB

(M4F program + data)

Total memory

1024KB

The entire RAM is retainable. Additionally, each memory cluster can be independently turned off (if needed). The

clusters are defined as below

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表9-2. Memory Retention Options

RAM_1

RAM_2

RAM_3

Shared

HWA

256KB

128KB

256KB

BANK #1⁽¹⁾

Cluster #3

BANK #2

Cluster #2

16KB

BANK #3

Cluster #5

Cluster #1

64kB

Cluster #4

128KB

Cluster #6

256KB

64KB

112KB

128KB

256KB

(1) Retention memories have power switches. These Banks represent memory configurations.

9.6 Boot Modes

As soon as device reset is de-asserted, the processor of the APPSS starts executing its bootloader from an on-

chip ROM memory.

The bootloader operates in three basic modes and these are specified on the user hardware (Printed Circuit

Board) by configuring what are termed as "Sense on power" (SOP) pins. These pins on the device boundary are

scanned by the bootloader firmware and choice of mode for bootloader operation is made.

表9-3 enumerates the relevant SOP combinations and how these map to bootloader operation.

表9-3. SOP Combinations

SOP1

SOP0

BOOTLOADER MODE AND OPERATION

0

Flashing Mode

Device Bootloader spins in loop to allow flashing of user application (or device

firmware patch - Supplied by TI) to the serial flash.

0

1

Functional Mode

Device Bootloader loads user application from QSPI Serial Flash to internal

RAM and switches the control to it.

Debug Mode

Bootloader is bypassed and M4F processor is halted. This allows user to

connect emulator at a known point.

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10 Applications, Implementation, and Layout

备注

Information in the following Applications section is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI's customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Application Information

Application information can be found on IWR Application web page.

10.2 Reference Schematic

Please check the device product page for latest Hardware design information under Design Kits - typically, at

Design and Development

Listed for convenience are: Design Files, Schematics, Layouts, and Stack up for PCB

• Altium IWRL6432 EVM Design Files

• IWRL6432 EVM Schematic Drawing, Assembly Drawing, and Bill of Materials

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11 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions follow.

11.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for

example, IWRL6432). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

X

P

Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, ABL0161), the temperature range (for example, blank is the default commercial temperature

range). 图11-1 provides a legend for reading the complete device name for any IWRL6432 device.

For orderable part numbers of IWRL6432 devices in the ABL0161 package types, see the Package Option

Addendum of this document (when available), the TI website (www.ti.com), or contact your TI sales

representative.

For additional description of the device nomenclature markings on the die, see the IWRL6432 Device Errata .

56

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图11-1. Device Nomenclature

11.2 Tools and Software

Models

IWRL6432 BSDL model Boundary scan database of testable input and output pins for IEEE 1149.1 of the

specific device.

IWRL6432 IBIS model IO buffer information model for the IO buffers of the device. For simulation on a circuit

board, see IBIS Open Forum.

11.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

The current documentation that describes the peripherals, and other technical collateral follows.

Errata

IWRL6432 device errata Describes known advisories, limitations, and cautions on silicon and provides

workarounds.

11.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help—straight from

the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

E2E^™is a trademark of Texas Instruments.

Arm^®and M4F^®are registered trademarks of Arm Limited.

所有商标均为其各自所有者的财产。

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11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, see the left-hand navigation.

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PACKAGE OUTLINE

AMF0102A

FCCSP - 0.97 mm max height

S

C

A

L

E

2

.

0

FLIP CHIP CHIP SCALE PACKAGE

6.55

6.35

B

A

BALL A1

CORNER

6.55

6.35

0.15 C

0.2 C

0.97 MAX

C

SEATING PLANE

0.08 C

0.338

0.150

(0.475)

PKG

M

L

(0.475)

K

J

H

G

F

PKG

5.5 TYP

E

D

C

0.36

102X

NOTE 4

B

A

0.26

0.15

0.05

C A B

1

2

3

4

5

6

7

8

9

10

11

12

C

0.5 TYP

4228614/A 03/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.

4. Dimension is measured at the maximum solder ball diameter, post reflow, parallel to primary datum C.

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EXAMPLE BOARD LAYOUT

AMF0102A

FCCSP - 0.97 mm max height

FLIP CHIP CHIP SCALE PACKAGE

(0.5) TYP

102X ( 0.25)

3

4

6

7

8

9

10

11

1

2

5

12

A

(0.5) TYP

B

C

D

E

F

PKG

G

H

J

K

L

M

PKG

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

EXPOSED METAL

(

0.25)

(

0.25)

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

METAL EDGE

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4228614/A 03/2022

NOTES: (continued)

5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

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EXAMPLE STENCIL DESIGN

AMF0102A

FCCSP - 0.97 mm max height

FLIP CHIP CHIP SCALE PACKAGE

(0.5) TYP

102X ( 0.25)

(0.5) TYP

3

4

6

7

8

9

10

11

1

2

5

12

A

B

C

D

E

F

PKG

G

H

J

K

L

M

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 15X

4228614/A 03/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	XIWR6432LQGAMF
厂家：	TEXAS INSTRUMENTS
描述：	单芯片低功耗 57GHz 至 64GHz 工业毫米波雷达传感器 \| AMF \| 102 \| -40 to 105 雷达传感器
文件：	总64页 (文件大小：2321K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XIWR6432LQGAMF [TI]

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