XLMH32401QWRGTRQ1 [TI]
汽车类可编程增益差分输出高速跨阻放大器 | RGT | 16 | -40 to 125;
| 型号： | XLMH32401QWRGTRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类可编程增益差分输出高速跨阻放大器 | RGT | 16 | -40 to 125 放大器 |
| 文件： | 总38页 (文件大小：2393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH32401-Q1
ZHCSS23 – APRIL 2023
LMH32401-Q1 汽车级 450MHz、可编程增益、差分输出跨阻放大器
1 特性
3 说明
•
符合面向汽车应用的 AEC-Q100 标准：
LMH32401-Q1 是一款汽车级可编程增益、单端、输入
转差分输出跨阻放大器，适用于光探测和测距 (LIDAR)
应用。可以为 LMH32401-Q1 配置 2kΩ 或 20kΩ 增
益。LMH32401-Q1 具有 1.5VPP 的输出摆幅，可驱动
100Ω 负载。
– 温度等级 1：–40°C 至 +125°C，TA
集成的可编程增益：2kΩ 或 20kΩ
增益 = 2kΩ、CPD = 1pF 时的性能：
– 带宽：450 MHz
•
•
– 输入参考噪声：250nARMS
– 上升和下降时间：0.8ns
增益 = 20kΩ、CPD = 1pF 的性能：
– 带宽：275 MHz
LMH32401-Q1 具有集成的 100mA 电流钳位，可保
护放大器，使其在出现过载输入时能迅速恢复正常。此
外，LMH32401-Q1 还具有集成的环境光消除电路。为
了节省布板空间并降低系统成本，可使用此电路代替光
电二极管 (PD) 或雪崩光电二极管 (APD) 与放大器之间
的交流耦合。当需要直流耦合时，可以禁用环境光消除
电路。
•
– 输入参考噪声：49nARMS
– 上升和下降时间：1.3ns
集成式环境光消除
•
•
•
•
•
•
集成式 100mA 保护钳位
为了在不使用放大器时节省功耗，可使用 EN 引脚将
LMH32401-Q1 置于低功耗模式。当放大器处于低功耗
模式时，输出引脚处于高阻抗状态。此功能允许多个
LMH32401-Q1 放大器多路复用到单个 ADC 中，EN
控制引脚将用作多路复用器选择功能。
集成式输出多路复用器
宽输出摆幅：1.5 V VPP
静态电流：30mA
封装：16 引脚可湿性侧面 VQFN
2 应用
封装信息(1)
封装
•
•
•
•
机械扫描激光雷达
器件型号
封装尺寸（标称值）
固态扫描激光雷达
工业机器人激光雷达
智能弹药
可湿性侧面 RGT
（VQFN，16）
LMH32401-Q1
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
3
0
GAIN
VDD1
VDD2
EN
1 k
100-mA
Clamp
10 k
IN
Differential Output ADC
Driver
-3
-6
-9
TIA
10
OUT
Ambient Light
Cancellation
VBIAS
IDC EN
VOD
+
2x
VOCM
OUT+
–
-12
Gain = 2 kW
Gain = 20 kW
Output Offset
10
-15
10M
100M
Frequency [Hz]
1G
GND
闭环跨阻带宽
简化版方框图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSAF0
LMH32401-Q1
ZHCSS23 – APRIL 2023
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 绝对最大额定值...........................................................4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics: Gain = 2 kΩ....................... 5
6.6 Electrical Characteristics: Gain = 20 kΩ..................... 6
6.7 Electrical Characteristics: Both Gains.........................7
6.8 Electrical Characteristics: Logic Threshold and
7.3 Feature Description...................................................20
7.4 Device Functional Modes..........................................22
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Application ................................................... 25
8.3 Power Supply Recommendations.............................27
8.4 Layout....................................................................... 27
9 Device and Documentation Support............................29
9.1 Device Support......................................................... 29
9.2 Documentation Support............................................ 29
9.3 接收文档更新通知..................................................... 29
9.4 支持资源....................................................................29
9.5 Trademarks...............................................................29
9.6 静电放电警告............................................................ 29
9.7 术语表....................................................................... 29
10 Mechanical, Packaging, and Orderable
Switching Characteristics.............................................. 9
6.9 Typical Characteristics..............................................10
7 Detailed Description......................................................19
7.1 Overview...................................................................19
7.2 Functional Block Diagram.........................................19
Information.................................................................... 30
Tape and Reel Information..............................................30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
April 2023
*
Initial Release
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SBOSAF0
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5 Pin Configuration and Functions
GND
VDD1
IN
1
2
3
4
12
11
10
9
VOCM
OUTœ
OUT+
VOD
Thermal pad
NC
Not to scale
图 5-1. RGT Package, 16-Pin VQFN With Wettable Flanks and Exposed Thermal Pad (Top View)
表 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Device enable pin.
EN
6
Input EN = logic low = normal operation (default)(1)
EN = logic high = power-off mode.
.
Gain setting.
GAIN
16
1, 7
5
Input GAIN = low = 2 kΩ (default)(1)
GAIN = high = 20 kΩ.
.
GND
Input Amplifier ground
Ambient light cancellation (ALC) loop enable.
IDC_EN
Input IDC_EN = logic low = enable dc current cancellation (default)(1)
IDC_EN = logic high = disable dc current cancellation.
.
IN
3
Input Transimpedance amplifier input
NC
4, 8, 13, 15
—
Do not connect
Inverting amplifier output. When light is incident on the photodiode, the output pin transitions in a
negative direction from the no-light condition (APD anode connected to negative bias).
OUT–
11
Output
Noninverting amplifier output. When light is incident on the photodiode, the output pin transitions in a
positive direction from the no-light condition (APD anode connected to negative bias).
OUT+
VDD1
VDD2
10
2
Output
Input Positive power supply for the transimpedance amplifier stage
Positive power supply for the differential amplifier stage. Tie VDD1 and VDD2 to the same power
supply with independent power-supply bypassing.
14
Input
VOCM
VOD
12
9
Input Differential-amplifier common-mode output setting
Input Differential-amplifier differential output offset setting
Thermal
pad
Thermal
pad
—
Connect the thermal pad to GND or the most negative power supply of the device under test (DUT).
(1) Drive a digital pin with a low-impedance source rather than leaving the pin floating because fast-moving transients can couple into the
pin and inadvertently change the logic level.
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English Data Sheet: SBOSAF0
LMH32401-Q1
ZHCSS23 – APRIL 2023
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6 Specifications
6.1 绝对最大额定值
在自然通风条件下的工作温度范围内测得（除非另有说明）(1)
最小值
最大值
3.65
VDD
VDD
25
单位
V
(2)
VDD1、VDD2
总电源电压，VDD
输出引脚处的电压
逻辑引脚处的电压
IN 的持续输入电流
持续输出电流
结温
0
V
-0.25
V
IIN
mA
mA
°C
°C
°C
IOUT
TJ
35
150
125
150
TA
自然通风工作温度
贮存温度
-40
Tstg
–65
(1) 超出绝对最大额定值运行可能会对器件造成损坏。绝对最大额定值并不表示器件在这些条件下或在建议运行条件以外的任何其他条件下
能够正常运行。如果超出建议工作条件但在绝对最大额定值范围内使用，器件可能不会完全正常运行，这可能影响器件的可靠性、功能
和性能，并缩短器件寿命。
(2) 将 VDD1 和 VDD2 连接到同一电源并使用单独的电源旁路电容器。
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
±1500
HBM ESD classification level 1C
V(ESD) Electrostatic discharge
V
Charged device model (CDM), per AEC Q100-011
CDM ESD classification level C6
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.45
125
UNIT
V
VDD
TA
Total supply voltage
3.3
Operating free-air temperature
–40
°C
6.4 Thermal Information
LMH32401-Q1 (2)
THERMAL METRIC(1)
RGT (VQFN)
16 PINS
56.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
67
31.3
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.7
ΨJB
31.2
RθJC(bot)
15.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Thermal information is applicable to packaged parts only.
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English Data Sheet: SBOSAF0
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6.5 Electrical Characteristics: Gain = 2 kΩ
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, VGAIN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA = 25℃
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
LSBW
tR, tF
Small-signal bandwidth
Large-signal bandwidth
Rise and fall time
VOUT = 100 mVPP
450
450
0.8
MHz
MHz
ns
VOUT = 1 VPP
VOUT = 100 mVPP, pulse duration = 10 ns
VOUT = 1 VPP, pulse duration = 10 ns
IIN = 10 mA, pulse duration = 10 ns
f = 500 MHz
Slew rate(2)
1100
4
V/µs
ns
Overload pulse extension(3)
iN
Integrated input current noise
250
nARMS
DC PERFORMANCE
Z21
Small-signal transimpedance gain(4)
Differential output offset voltage
(VOUT– – VOUT+
1.75
–12
2
3.5
2.25
12
kΩ
mV
VOD
)
ΔVOD/ΔTA Differential output offset voltage drift
±5.5
µV/°C
INPUT PERFORMANCE
RIN
Input resistance
60
100
2.47
1.1
120
Ω
V
VIN
Default input bias voltage
Default input bias voltage drift
DC input current range
Input pin floating
2.42
2.52
ΔVIN/ΔTA
IIN_LIN
Input pin floating
mV/°C
µA
Z21 < 3-dB degradation from IIN = 50 µA
600
705
(1) Input capacitance of photodiode.
(2) Average of rising and falling slew rate.
(3) Pulse duration extension measured at 50% of pulse height of a square wave.
(4) Gain measured at the amplifier output pins when driving a 100-Ω resistive load. At higher resistor loads, the gain increases.
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6.6 Electrical Characteristics: Gain = 20 kΩ
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, VGAIN = 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA = 25℃
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
LSBW
tR, tF
Small-signal bandwidth
Large-signal bandwidth
Rise and fall time
VOUT = 100 mVPP
275
275
1.3
700
4
MHz
MHz
ns
VOUT = 1 VPP
VOUT = 100 mVPP, pulse duration = 10 ns
VOUT = 1 VPP, pulse duration = 10 ns
IIN = 10 mA, pulse duration = 10 ns
f = 250 MHz
Slew rate(2)
V/µs
ns
Overload pulse extension(3)
iN
Integrated input current noise
49
nARMS
DC PERFORMANCE
Z21
Small-signal transimpedance gain(4)
Differential output offset voltage
(VOUT– – VOUT+
17
20
5
22.5
20
kΩ
mV
VOD
–20
)
ΔVOD/ΔTA Differential output offset voltage drift
±17.5
µV/°C
INPUT PERFORMANCE
RIN
Input resistance
270
350
2.47
1.1
410
Ω
V
VIN
Default input bias voltage
Default input bias voltage drift
DC input current range
Input pin floating
2.42
2.52
ΔVIN/ΔTA
IIN_LIN
Input pin floating
mV/°C
µA
Z21 < 3-dB degradation from IIN = 5 µA
60
72
(1) Input capacitance of photodiode.
(2) Average of rising and falling slew rate.
(3) Pulse duration extension measured at 50% of pulse height of a square wave.
(4) Gain measured at the amplifier output pins when driving a 100-Ω resistive load. At higher resistor loads, the gain increases.
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6.7 Electrical Characteristics: Both Gains
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, VGAIN = 0 V or 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and
TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT PERFORMANCE
Single-sided output voltage swing (high)
VOH
VOL
TA = 25°C
Single-sided output voltage swing (low)(2) TA = 25°C
2.87
2.9
0.36
26.6
V
V
(2)
0.39
32
TA = 25°C, IIN = 500 µA, gain = 2 kΩ,
RL = 25 Ω
24
TA = –40°C, IIN = 500 µA, gain = 2 kΩ,
RL = 25 Ω
IOUT_LIN Linear output drive (sink and source)
27.1
25.1
mA
TA = 125°C, IIN = 500 µA, gain = 2 kΩ,
RL = 25 Ω
ISC
Output short-circuit current (differential) (3)
DC output impedance (differential)
70
21
mA
Ω
amplifier enabled
18
24
ZOUT
amplifier in shutdown
2.8
3.3
kΩ
OUTPUT COMMON-MODE CONTROL (VOCM) PERFORMANCE
SSBW
LSBW
Small-signal bandwidth
Large-signal bandwidth
VOCM = 100 mVPP at VOCM pin
VOCM = 1 VPP at VOCM pin
285
85
MHz
MHz
f = 10 MHz, 1-nF capacitor to GND on VOCM
pin
eN
Output common-mode noise
17.8
nV/√Hz
V/V
Gain, (ΔVOCM / ΔVVOCM
)
IN floating, VVOCM = 1.1 V (driven)
1
0.5%
±1%
17
AV
TA = 25°C, VVOCM = 0.7 V to 2.3 V
–2%
0
2%
20
Gain error
TA = –40°C to +125°C, VVOCM = 0.7 V to 2.3 V
Input impedance
kΩ
VOCMOS VOCM pin default offset from 1.1 V
VOCM floating, (VVOCM measured –1.1 V)
Gain = 20 kΩ, VOCM driven to 1.1 V
10
mV
ΔVOCM
ΔIIN
/
VOCM error vs Input current
–15
1.1
75
µV/µA
V
Output common-mode voltage,
(VOUT+ + VOUT–) / 2
VOCM
TA = 25°C, VOCM pin floating
1.05
1.15
Output common-mode voltage drift,
(ΔVOCM / ΔTA)
TA = –40°C to +125°C, VOCM pin floating
TA = 25°C, VOCM pin driven to 1.1 V
µV/°C
V
Output common-mode voltage,
(VOUT+ + VOUT–) / 2
VOCM
1.05
1.1
–14
1.15
Output common-mode voltage drift,
(ΔVOCM / ΔTA)
TA = –40°C to +125°C,
VOCM pin driven to 1.1 V
µV/°C
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6.7 Electrical Characteristics: Both Gains (continued)
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, VGAIN = 0 V or 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and
TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DIFFERENTIAL OFFSET (VOD) PERFORMANCE
SSBW
LSBW
Small-signal bandwidth
Large-signal bandwidth
Differential output offset,
VOD = 100 mVPP at VOD pin
45
14
MHz
MHz
VOD = 1 VPP
VOS_D
VOS_D
AV
IN floating, VVOD = 0.5 V
490
490
510
0.03
510
530
530
mV
mV/℃
mV
VOUT = (VOUT– – VOUT+
)
Differential output offset drift,
ΔVOS_D / ΔTA
IN floating, VVOD = 0.5 V
IN floating, VOD floating
Differential output offset,
VOUT = (VOUT– – VOUT+
)
Differential output offset drift,
ΔVOS_D / ΔTA
IN floating, VOD floating
0.04
1.01
mV/℃
V/V
Gain, (ΔVOUT / ΔVVOD), where
IN floating, VVOCM = 1.1 V (driven)
VOUT = (VOUT– – VOUT+
)
TA = 25℃, VVOD = 0 V to 1.2 V
–5%
–1%
±1.5%
2.5
5%
Gain error
TA = –40℃ to +125℃, VVOD = 0 V to 1.2 V
Input impedance
kΩ
AMBIENT LIGHT CANCELLATION PERFORMANCE (IDC_EN = 0 V) (4)
IIN = 0 µA → 100 µA, gain = 2 kΩ
18
2.5
35
IIN = 0 µA → 10 µA, gain = 20 kΩ
IIN = 100 µA → 0 µA, gain = 2 kΩ
IIN = 10 µA → 0 µA, gain = 20 kΩ
Settling time (within VOD limit)
µs
13
Differential output offset (VOUT– – VOUT+) shift
from IDC = 10 µA < ±10 mV
Ambient light current cancellation range
2
3
mA
POWER SUPPLY
TA = 25°C
TA = 125°C
TA = –40°C
24
30
32
27
33.5
IQ
Quiescent current, total
mA
dB
Positive power-supply rejection ratio,
VDD1 = VDD2
PSRR+
54
66
SHUTDOWN
TA = 25°C
TA = –40°C
TA = 125°C
TA = 25°C
2.4
3.3
2.75
5.2
4.2
Quiescent current, amplifier disabled
(EN = VDD
IQ
mA
µA
)
Enable pin input bias current
(1) Input capacitance of photodiode.
75
120
(2) Output levels achieved by adjusting VOCM, VOD, and input current.
(3) Device cannot withstand continuous short-circuit between the differential outputs.
(4) Enabling the ambient light cancellation loop adds noise to the system.
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English Data Sheet: SBOSAF0
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6.8 Electrical Characteristics: Logic Threshold and Switching Characteristics
at VDD = 3.3 V, VOCM = Open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, VGAIN = 0 V or 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and
TA = 25℃. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC THRESHOLD PERFORMANCE
High-gain enable, threshold voltage
Low-gain enable, threshold voltage
Enabled when greater than this voltage
Enabled when less than this voltage
Disabled when greater than this voltage
Enabled when less than this voltage
Disabled when greater than this voltage
Enabled when less than this voltage
1.8
1
2
2
2
V
V
V
V
V
V
0.8
0.8
0.8
EN control, disable threshold voltage
EN control, enable threshold voltage
IDC_EN control, disable threshold voltage
IDC_EN control, enable threshold voltage
GAIN CONTROL TRANSIENT PERFORMANCE
1.8
1
1.8
1
High-gain to low-gain transition time,
(1% settling)
Ambient loop disabled, fIN = 25 MHz,
VOUT = 1 VPP (initial condition), IDC = 0 µA
90
ns
ns
Low-gain to high-gain transition time,
(1% settling)
Ambient loop disabled, fIN = 25 MHz,
VOUT = 1 VPP (final condition), IDC = 0 µA
750
Ambient loop enabled, fIN = 25 MHz,
VOUT = 1 VPP (initial condition),
IDC = 100 µA
High-gain to low-gain transition time,
(1% settling)
4
4
µs
µs
Low-gain to high-gain transition time,
(1% settling)
Ambient loop enabled, fIN = 25 MHz,
VOUT = 1 VPP (final condition), IDC = 100 µA
EN CONTROL TRANSIENT PERFORMANCE
Ambient loop disabled, fIN = 25 MHz,
VOUT = 1 VPP, IDC = 0 µA, gain = 2 kΩ
Enable transition time (1% settling)
125
3
ns
ns
ns
ns
µs
ns
µs
ns
Ambient loop disabled, fIN = 25 MHz,
VOUT = 1 VPP, IDC = 0 µA, gain = 2 kΩ
Disable transition time (1% settling)
Enable transition time (1% settling)
Disable transition time (1% settling)
Enable transition time (1% settling)
Disable transition time (1% settling)
Enable transition time (1% settling)
Disable transition time (1% settling)
(1) Input capacitance of photodiode.
Ambient loop disabled, fIN = 25 MHz,
VOUT = 1 VPP, IDC = 0 µA, gain = 20 kΩ
850
3
Ambient loop disabled, fIN = 25 MHz,
VOUT = 1 VPP, IDC = 0 µA, gain = 20 kΩ
Ambient loop enabled, fIN = 25 MHz,
VOUT = 1 VPP, IDC = 100 µA, gain = 2 kΩ
10
3.5
4
Ambient loop enabled, fIN = 25 MHz,
VOUT = 1 VPP, IDC = 100 µA, gain = 20 kΩ
Ambient loop enabled, fIN = 25 MHz,
VOUT = 1 VPP, IDC = 100 µA, gain = 20 kΩ
Ambient loop enabled, fIN = 25 MHz,
VOUT = 1 VPP, IDC = 100 µA, gain = 2 kΩ
3
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6.9 Typical Characteristics
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
69
66
63
60
57
54
51
89
86
83
80
77
74
71
CIN = PCB only
CIN = 0.5 pF
CIN = 1 pF
CIN = 2 pF
CIN = 4.7 pF
CIN = 10 pF
CIN = PCB only
CIN = 0.5 pF
CIN = 1 pF
CIN = 2 pF
CIN = 4.7 pF
CIN = 10 pF
10M
100M
Frequency [Hz]
1G
1G
1G
10M
100M
Frequency [Hz]
1G
1G
1G
Gain = 2 kΩ, VOUT = 100 mVPP
Gain = 20 kΩ, VOUT = 100 mVPP
图 6-1. Small-Signal Response vs Input Capacitance
图 6-2. Small-Signal Response vs Input Capacitance
69
89
66
63
60
86
83
80
CIN = PCB only
57
CIN = PCB only
77
CIN = 0.5 pF
CIN = 1 pF
CIN = 2 pF
CIN = 4.7 pF
CIN = 10 pF
CIN = 0.5 pF
CIN = 1 pF
CIN = 2 pF
CIN = 4.7 pF
CIN = 10 pF
54
74
51
10M
71
10M
100M
Frequency [Hz]
100M
Frequency [Hz]
Gain = 2 kΩ, VOUT = 1 VPP
Gain = 20 kΩ, VOUT = 1 VPP
图 6-3. Large-Signal Response vs Input Capacitance
图 6-4. Large-Signal Response vs Input Capacitance
69
89
66
63
60
57
86
83
80
77
54
74
CIN = 0.5 pF, CLOAD = open
CIN = 0.5 pF, CLOAD = 2.7 pF
51
CIN = 0.5 pF, CLOAD = open
CIN = 0.5 pF, CLOAD = 2.7pF
71
10M
100M
Frequency [Hz]
10M
100M
Frequency [Hz]
Gain = 2 kΩ, VOUT = 100 mVPP
Gain = 20 kΩ, VOUT = 100 mVPP
图 6-5. Small-Signal Response vs Load Capacitance
图 6-6. Small-Signal Response vs Load Capacitance
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6.9 Typical Characteristics (continued)
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
69
66
63
60
57
54
51
89
86
83
80
77
74
71
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
10M
100M
Frequency [Hz]
1G
10M
100M
Frequency [Hz]
1G
Gain = 2 kΩ, CIN = PCB
Gain = 20 kΩ, CIN = PCB
图 6-7. Small-Signal Response vs Ambient Temperature
图 6-8. Small-Signal Response vs Ambient Temperature
3
10k
Amplifier Enabled
Amplifier Disabled
0
-3
-6
-9
1k
100
10
ALC Disabled
ALC Enabled, Gain = 2 kW
ALC Enabled, Gain = 20 kW
-12
-15
10k
100k
1M
Frequency [Hz]
10M
1M
10M
100M
Frequency (Hz)
1G
IDC_IN = 100 µA
Gain = 2 kΩ
图 6-9. Low-side Frequency Response vs Ambient-Light
图 6-10. Closed-Loop Output Impedance vs Frequency
Cancellation
20
10
CPD = 0.5 pF
CPD = 1 pF
CPD = 2 pF
CPD = 3 pF
CPD = 0.5 pF
CPD = 1 pF
CPD = 2 pF
CPD = 3 pF
10
5
10k
1
10k
100k
1M 10M
Frequency (Hz)
100M
1G
100k
1M 10M
Frequency (Hz)
100M
1G
Gain = 2 kΩ
Gain = 20 kΩ
图 6-11. Input Noise Density vs Input Capacitance
图 6-12. Input Noise Density vs Input Capacitance
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6.9 Typical Characteristics (continued)
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
20
10
5
5
CLOAD = open
CLOAD = 2.7 pF
CLOAD = open
CLOAD = 2.7 pF
1
10k
10k
100k
1M 10M
Frequency (Hz)
100M
1G
100k
1M 10M
Frequency (Hz)
100M
1G
Gain = 2 kΩ
Gain = 20 kΩ
图 6-13. Input Noise Density vs Load Capacitance
100
图 6-14. Input Noise Density vs Load Capacitance
50
IDC = 0 mA
IDC = 0 mA
IDC = 10 mA
IDC = 100 mA
IDC = 1 mA
IDC = 10 mA
IDC = 100 mA
IDC = 1 mA
10
10
5
1
10k
10k
100k
1M 10M
Frequency (Hz)
100M
1G
100k
1M 10M
Frequency (Hz)
100M
1G
Gain = 2 kΩ
Gain = 20 kΩ
图 6-15. Input Noise Density vs Ambient-Light DC Current
图 6-16. Input Noise Density vs Ambient-Light DC Current
10
200
TA = 125èC
TA = 25èC
TA = -40èC
Differential Noise
Single-Ended Noise
100
1
0.5
10k
10
10k
100k
1M 10M
Frequency (Hz)
100M
1G
100k
1M 10M
Frequency (Hz)
100M
1G
Gain = 20 kΩ
Gain = 20 kΩ
图 6-17. Input Noise Density vs Ambient Temperature
图 6-18. Output Noise Density vs Output Configuration
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6.9 Typical Characteristics (continued)
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
1.75
1.5
1.75
1.5
0.1 VPP
1 VPP
1.5 VPP
0.1 VPP
1 VPP
1.5 VPP
1.25
1
1.25
1
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.25
Time (5 ns/div)
Time (5 ns/div)
Gain = 2 kΩ
Gain = 20 kΩ
图 6-19. Pulse Response vs Output Swing
图 6-20. Pulse Response vs Output Swing
1.5
1.5
IIN = 500 mA
IIN = 1 mA
IIN = 50 mA
IIN = 1 mA
1.25
1
1.25
1
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.25
Time (5 ns/div)
Time (5 ns/div)
Gain = 2 kΩ
Gain = 20 kΩ
图 6-21. Overloaded Pulse Response
图 6-22. Overloaded Pulse Response
3.5
3.5
3
EN
Differential Output
EN
Differential Output
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
Time (25 ns/div)
Time (25 ns/div)
Gain = 2 kΩ
Gain = 20 kΩ
图 6-23. Turn-On Time
图 6-24. Turn-On Time
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6.9 Typical Characteristics (continued)
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
3.5
3
3.5
3
2.5
2
2.5
2
EN
Differential Output
EN
Differential Output
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
Time (1 ns/div)
Time (1 ns/div)
Gain = 2 kΩ, VVOD = 0.5 V
Gain = 20 kΩ, VVOD = 0.5 V
图 6-25. Turn-Off Time
图 6-26. Turn-Off Time
0.15
0.125
0.1
0
-0.02
-0.04
-0.06
-0.08
-0.1
0.075
0.05
0.025
0
-0.12
-0.14
-0.16
-0.025
Time (5 ms/div)
Time (5 ms/div)
Gain = 2 kΩ, IDC_IN = 0 µA → 100 µA 1
Gain = 2 kΩ, IDC_IN = 100 µA → 0 µA1
图 6-27. Ambient Loop Cancellation Settling Time
图 6-28. Ambient Loop-Cancellation Settling Time
1.6
1.4
1.2
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
0.8
0.6
0.4
0.2
0
-0.2
Time (1 ms/div)
Time (2 ms/div)
Gain = 20 kΩ, IDC_IN = 0 µA → 100 µA1
Gain = 20 kΩ, IDC_IN = 100 µA → 0 µA1
图 6-29. Ambient Loop-Cancellation Settling Time
图 6-30. Ambient Loop-Cancellation Settling Time
1
Current due to ambient light transitions at the lowest displayed value of the time axis.
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6.9 Typical Characteristics (continued)
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
5
50
125 èC
-40 èC
25 èC
1
10
5
125 èC
-40 èC
25 èC
0.5
-1000 -750 -500 -250
0
250
500
750 1000
-100 -80 -60 -40 -20
0
20
40
60
80 100
Input Current (mA)
Input Current (mA)
Gain = 2 kΩ, positive current is sinking current into the
photodiode cathode
Gain = 20 kΩ, positive current is sinking current into the
photodiode cathode
图 6-31. Transimpedance Gain vs Input Current
图 6-32. Transimpedance Gain vs Input Current
2040
2020
2000
1980
1960
1940
21000
20500
20000
19500
19000
18500
18000
Unit 1
Unit 2
Unit 3
Unit 1
Unit 2
Unit 3
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
Gain = 20 kΩ
Gain = 2 kΩ
图 6-34. Transimpedance Gain vs Ambient Temperature
图 6-33. Transimpedance Gain vs Ambient Temperature
2.5
2.25
2
2.6
2.55
2.5
1.75
1.5
1.25
1
0.75
0.5
0.25
0
2.45
Unit 1
Unit 2
Unit 3
2.4
-40
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Supply Voltage (V)
3
3.3
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Gain = 20 kΩ
图 6-35. Input Bias Voltage vs Supply Voltage
图 6-36. Input Bias Voltage vs Ambient Temperature
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6.9 Typical Characteristics (continued)
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
34
32
30
28
26
35
30
25
20
15
10
5
Unit 1
Unit 2
Unit 3
125 èC
-40 èC
25 èC
0
-40
-20
0
20
40
60
80
100 120 140
0
0.5
1
1.5
Supply Voltage (V)
2
2.5
3
3.5
Temperature (èC)
图 6-37. Quiescent Current vs Ambient Temperature
图 6-38. Quiescent Current vs Supply Voltage
1.8
1.2
1.1
1
1.7
1.6
1.5
0.9
0.8
0.7
0.6
0.5
0.4
Vout- (V)
Vout+ (V)
Vout- (V)
Vout+ (V)
1.4
1.3
1.2
1.1
1
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Input Current (mA)
Input Current (mA)
VVOD = 0.75 V, VVOCM = 1.4 V
图 6-39. High-side Swing vs Input Current
VVOD = 0.75 V, VVOCM = 0.8 V
图 6-40. Low-side Swing vs Input Current
1.5
1.2
0.9
0.6
0.3
0
550
540
530
520
510
500
490
480
470
460
450
125 èC
-40 èC
25 èC
0
0.3
0.6
Differential Output Offset Set (V)
0.9
1.2
1.5
1.8
2
0.5
1
1.5
2
Input Current (mA)
2.5
3
3.5
图 6-41. Differential Output Offset Gain
图 6-42. Ambient Light Cancellation Range vs Ambient
Temperature
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6.9 Typical Characteristics (continued)
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
35
30
25
20
15
10
5
3500
3000
2500
2000
1500
1000
500
125 èC
-40 èC
25 èC
0
0
25
26
27
28
29
30
31
32
33
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Enable Voltage (EN) (V)
3
3.3
Quiescent Current (mA)
Logic switching demonstrated using EN pin.
IDC_EN and gain pins behave similarly.
图 6-43. Logic Threshold vs Ambient Temperature
图 6-44. Quiescent Current Distribution
2500
3500
3000
2500
2000
1500
1000
500
2000
1500
1000
500
0
0
17500
1750
1850
1950
2050
2150
2250
18500
19500
20500
Gain (W)
21500
22500
Gain (W)
Gain = 20 kΩ
图 6-46. Transimpedance Gain (High) Distribution
图 6-45. Transimpedance Gain (Low) Distribution
4500
3000
4000
3500
3000
2500
2000
1500
1000
500
2500
2000
1500
1000
500
0
0
1
1.05
1.1
1.15
1.2
1.25
450 460 470 480 490 500 510 520 530 540 550
Output Common Mode Voltage (V)
Differential Output Voltage(mV)
图 6-47. Output Common-Mode Voltage (VOCM) Distribution
图 6-48. Differential Output Offset Voltage (VOD) Distribution
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6.9 Typical Characteristics (continued)
at VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
2000
1500
1000
500
0
3000
2500
2000
1500
1000
500
0
17.5
18.25
19
19.75
20.5
21.25
22
2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
4
Differential Output Impedance (W)
Differential Output Impedance (kW)
Amplifier enabled
Amplifier disabled
图 6-49. Differential Output Impedance (ZOUT) Distribution
图 6-50. Differential Output Impedance (ZOUT) Distribution
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7 Detailed Description
7.1 Overview
The LMH32401-Q1 device is a single-channel, differential output, high-speed transimpedance amplifier (TIA)
that features several integrated functions geared towards light detection and ranging (LIDAR) and pulsed time-
of-flight (ToF) systems. The LMH32401-Q1 is designed to work with photodiode (PD) configurations that can
source or sink current. When the photodiodesinks the photocurrent (the anode is biased to a negative voltage
and the cathode is tied to the amplifier input), the fast recovery clamp activates when the amplifier input is
overloaded. When the photodiode sources the photocurrent (the cathode is biased to a positive voltage and the
anode is tied to the amplifier input), a soft clamp activates when the amplifier input is overloaded. When the soft
clamp activates, the amplifier requires more time to recover. The recovery time depends on the level of input
overload. The LMH32401-Q1 is offered in a space-saving 3-mm × 3-mm, 16-pin VQFN package and is rated
over the temperature range of –40°C to +125°C.
7.2 Functional Block Diagram
GAIN
VDD1
1 k
VDD2
EN
100-mA
Clamp
IDC + ISIG
IN
10 k
Differential Output ADC Driver
ISIG
R
2.4 × R
10
OUT
TIA
IDC
+
Ambient Light
Cancellation
VBIAS
–
OUT+
VOCM
IDC EN
R
2.4 × R
10
VDD
VREF
VDD
Voltage-to-Current Converter
17 k
50.4 k
VOD
3 k
25 k
GND
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7.3 Feature Description
7.3.1 Switched Gain Transimpedance Amplifier
The LMH32401-Q1 features a programmable gain transimpedance amplifier (TIA) stage followed by a fixed-gain,
single-ended input to differential output amplifier stage. The closed-loop bandwidth and noise of a TIA are
affected by the transimpedance gain and photodiode capacitance. For a given value of photodiode capacitance,
the LMH32401-Q1 has higher bandwidth in the device low-gain configuration compared to the high-gain
configuration. Increasing the gain of the TIA stage by a factor of X increases the output signal by a factor
X, but the noise contribution from the resistor only increases by √X. The input-referred noise density of the
low-gain configuration is therefore higher than the input-referred noise density of the high-gain configuration.
The gain of the TIA stage is controlled by the GAIN pin. Setting this pin low places the TIA in the low-gain
configuration; whereas, setting the pin high places the TIA in a high-gain configuration. The LMH32401-Q1
defaults to the low-gain configuration when the GAIN pin is left floating.
7.3.2 Clamping and Input Protection
The LMH32401-Q1 is designed to work with photodiode (PD) configurations that can source or sink current;
however, the LMH32401-Q1 is optimized for a sinking-current configuration. The LMH32401-Q1 is usually used
with a PD that is configured with the device cathode tied to the amplifier input and the device anode tied to a
negative supply voltage.
The LMH32401-Q1 features two internal clamps: fast-recovery and soft. The fast-recovery clamp is the active
clamp when the photodiode is sinking a photocurrent. The soft clamp is the active clamp when the photodiode
is sourcing a photocurrent. Stray reflections from nearby objects with high reflectivity can produce large output
current pulses from the PD. The linear input range of the LMH32401-Q1 is approximately 65 µA in the high-gain
configuration and 650 µA in the low-gain configuration (PD sinking the photocurrent).
Input currents in excess of the linear current range cause the internal nodes of the amplifier to saturate, which
increases the amplifier recovery time. The end result is a broadening of the output pulse, leading to blind zones
in the system response. To protect against this condition, the LMH32401-Q1 features an integrated clamp that
absorbs and diverts the excess current to the positive supply (VDD1) when the amplifier detects the device nodes
entering a saturated condition. The integrated clamp minimizes the pulse extension to less than a few ns for
input pulses up to 100 mA. The power-supply pins (VDD1 and VDD2) must each have bypass capacitors to
prevent large input pulses from affecting the differential output stage. When the amplifier is in low-power mode,
the clamp circuitry is still active, thereby protecting the TIA input.
7.3.3 ESD Protection
All LMH32401-Q1 pins have an internal electrostatic discharge (ESD) protection diode to the positive and
negative supply rails to protect the amplifier from ESD events.
7.3.4 Differential Output Stage
The differential output stage of the LMH32401-Q1 performs the following two functions, which are common
across all differential amplifiers:
1. Converts the single-ended output from the TIA stage to a differential output.
2. Performs a common-mode output shift to match the specified ADC input common-mode voltage.
The differential output stage has two 10-Ω series resistors on the output to isolate the amplifier output stage
transistors from the package bond-wire inductance and printed circuit board (PCB) capacitance. The net gain
of the LMH32401-Q1 (TIA + output stage) is 2 kΩ (low gain) and 20 kΩ (high gain) when driving an external
100‑Ω resistor. When the external load resistor is increased above 100 Ω, the effective gain from the IN pin to
the differential output pin increases. Conversely, when the external load resistor is decreased to less than 100 Ω,
the effective gain from the IN pin to the differential output pin decreases as a result of the larger voltage drop
across the two internal 10-Ω resistors. When there is no load resistor between the OUT+ and OUT– pins, the
effective gain of the LMH32401-Q1 in the low-gain configuration is 2.4 kΩ, and in the high-gain configuration is
24 kΩ.
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The output common-mode voltage of the LMH32401-Q1 is set externally through the VOCM pin. A resistor
divider internal to the amplifier (between VDD2 and ground) sets the default voltage to 1.1 V. The internal
resistors generate common-mode noise that is typically rejected by the CMRR of the subsequent ADC stage. To
maximize the amplifier signal-to-noise ratio (SNR), place an external noise bypass capacitor to ground on the
VOCM pin. In single-ended signal chains, such as ToF systems that use time-to-digital converters (TDCs), only
a single output of the LMH32401-Q1 is required. In such situations, terminate the unused differential output in
the same manner as the used output to maintain balance and symmetry. The signal swing of the single-ended
output is half of the available differential output swing. Additionally, the common-mode noise of the output stage,
which is typically rejected by the differential input ADC, is now added to the total noise, and further degrades
SNR.
The output stage of the LMH32401-Q1 has an additional VOD input that sets the differential output between
OUT– and OUT+. 图 7-1 shows how each output pin of the LMH32401-Q1 is at the voltage set by the VOCM
pin (default = 1.1 V) when the photodiode output current is zero and the VOD input is set to 0 V. When the VOD
pin is driven to a voltage of X volts, the two output pins are separated by X volts when the photodiode current is
zero. The average voltage is still equal to VOCM. For example, 图 7-2 shows that if VOCM is set to 1.1 V and
VOD is set to 0.4 V, then OUT– = 1.1 V + 0.2 V = 1.3 V and OUT+ = 1.1 V – 0.2 V = 0.9 V.
The VOD pin is functional only when the LMH32401-Q1 is used with a PD that sinks the photocurrent.
Set VOD = 0 V when the LMH32401-Q1 is interfaced with a PD that sources the photocurrent. The VOD
output offset feature is included in the LMH32401-Q1 because the output current of a photodiode is unipolar.
Depending on the reverse bias configuration, the photodiode can either sink or source current, but cannot do
both simultaneously. With the anode connected to a negative bias and the cathode connected to the TIA stage
input, the photodiode can only sink current, which implies that the TIA stage output swings in a positive direction
greater than the default input bias voltage (2.47 V). Subsequently, OUT– only swings less than VOCM, and
OUT+ only swings greater than VOCM. 图 7-1 shows how the LMH32401-Q1 device only uses half of the output
swing range (VOUT = VOUT+ – VOUT–) when VOD = 0 V because one output never swings less than VOCM and
the other output never exceeds VOCM. The signal dynamic range in this case is 0.4 VPP – 0 V = 0.4 VPP
.
图 7-2 shows how the VOD pin voltage allows OUT– to be level-shifted to greater than VOCM, and OUT+ to be
level-shifted below VOCM to maximize the output swing capabilities of the amplifier. The signal dynamic range in
this case is 0.4 VPP – (–0.4 VPP) = 0.8 VPP
.
VOUT = 0.4 VPP
APD Excited
VOUT = 0.4 VPP
APD Excited
VOUTÞ
VOUT+
VOUTÞ
VOUT+
1.3 V
1.3 V
VOD = 0 V
VOCM = 1.1 V
VOD = 0.4 V
VOCM = 1.1 V
0.9 V
0.9 V
VOUT = 0 VPP
No output from APD
VOUT = Þ0.4 VPP
No output from APD
图 7-1. Individual Single-ended Outputs With
图 7-2. Individual Single-Ended Outputs With
VOD = 0 V
VOD = 0.4 V
When the LMH32401-Q1 device drives a 100‑Ω load, the voltage set at the VOD pin is equal to the differential
output offset (VOUT = VOUT+ – VOUT–) when the input signal current is zero. Use 方程式 1 to calculate the
differential output offset under other load conditions.
R
L
+ 20Ω
V
= 1.2 × V
×
VOD
R
(1)
OD
L
Where:
•
•
•
VVOD = Voltage applied at pin 9
VOD = (VOUT– – VOUT+
RL = External load resistance
)
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7.4 Device Functional Modes
7.4.1 Ambient Light Cancellation (ALC) Mode
The LMH32401-Q1 has an integrated, dc, ambient light cancellation (ALC) loop that cancels any voltage offsets
as a result of incidental ambient light. ALC mode only works when the PD is sinking the photocurrent. To enable
ALC mode, set IDC_EN low. Incidental ambient light on a photodiode produces a dc current that results in
an offset voltage at the output of the LMH32401-Q1 TIA stage. 节 7.2 shows how the ALC loop senses the
low-frequency dc offset at the output of the TIA stage and compares the offset against the internal reference
voltage (VREF). The ALC loop then outputs an opposing dc current (IDC) to compensate for the differential offset
voltage at the device input. The ALC loop has a high-pass cutoff frequency of 100 kHz. ALC mode is disabled
when the amplifier is placed in power-down mode.
The shot noise current introduced by the ALC loop increases the overall amplifier noise; therefore, if the
ambient-light level is negligible, disable the loop to improve SNR. The ALC loop helps save PCB space and
system costs by eliminating the need for external ac-coupling, passive components. Additionally, the extra trace
inductance and PCB capacitance introduced by using external ac-coupling components degrade the LMH32401-
Q1 dynamic performance.
7.4.2 Power-Down Mode (Multiplexer Mode)
To place the LMH32401-Q1 into a power-down mode, and thus help save system power, set EN high. Power-
down mode puts the outputs of the LMH32401-Q1 internal amplifiers, including the differential outputs, into a
high-impedance state. If a system consists of several photodiode and amplifier channels multiplexed to a single
ADC channel, 图 7-3 shows how this device feature can further save board space and cost by eliminating the
need for a discrete high-speed multiplexer. The disabled channel outputs are not an ideal open circuit; therefore,
as the number of multiplexed channels increases, the disabled channels begin to load the enabled channel.
Multiplexing more than four channels in parallel degrades the performance of the enabled channel. When the
amplifier is in power-down mode, the clamp circuitry is still active, thereby protecting the TIA input. The ALC
loop is disabled when the amplifier is placed in power-down mode. When the LMH32401-Q1 is brought out of
power-down operation, the ALC loop requires several time constants to settle. 图 6-9 shows the low-frequency
loop response, which in turn determines the time constant required for the loop to settle.
1 k
DISABLED AMPLIFIER
100-mA
Clamp
10 k
IN
10
RISO
TIA
OUT
Ambient Light
Cancellation
VBIAS
+
–
IDC EN
VOD
OUT+
RISO
Output Offset
10
RADC_IN
VEN = 3.3 V
ADC12QJ1600
CFILT
VOCM
RADC_IN
1 k
ENABLED AMPLIFIER
100-mA
Clamp
IN
10 k
10
RISO
TIA
OUT
Ambient Light
Cancellation
VBIAS
+
–
IDC EN
VOD
OUT+
RISO
Output Offset
10
VEN = 0 V
图 7-3. Configuring Two LMH32401-Q1 Devices in Multiplexer Mode to Drive a Single ADC
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8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The differential outputs of the LMH32401-Q1 can directly drive a high-speed differential input ADC. 图 8-1 shows
the LMH32401-Q1 differential outputs directly driving the ADC12QJ1600. The effective signal gain between the
TIA input and the ADC input is 2 kΩ or 20 kΩ when driving an ADC with a 100-Ω differential input impedance
(RADC_IN = 50 Ω). 方程式 2 gives the effective signal gain between the TIA input and the ADC input when driving
an ADC with any other value of differential input impedance (RADC_IN ≠ 50 Ω).
GAIN
VDD1
VDD2
1 k
100-mA
Clamp
IN
10 k
Differential Output
ADC Driver
OUT
TIA
10
RADC_IN
Ambient Light
Cancellation
VBIAS
+
–
VOCM
RADC_IN
ADC12QJ1600
IDC EN
VOD
10
Output Offset
OUT+
GND
EN
图 8-1. LMH32401-Q1 to ADC Interface
2 × R
ADC_IN
A = 2 kΩ or 20 kΩ × 1.2 ×
(2)
Z
2 × R
ADC
IN
+ 20 Ω
Where:
•
•
AZ = Differential gain from the TIA input to the ADC input
RADC_IN = Input resistance of the ADC
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图 8-2 shows a matching resistor network between the LMH32401-Q1 output and the ADC12QJ1600 input. The
matching network is needed to prevent signal reflections when the signal path between the LMH32401-Q1 and
ADC is very long. 方程式 3 gives the effective gain from the TIA input to the ADC input when using a matching
resistor network.
GAIN
VDD1
VDD2
1 k
100-mA
Clamp
IN
10 k
Differential Output
ADC Driver
OUT
10
TIA
RISO
RADC_IN
Ambient Light
Cancellation
VBIAS
+
–
ADC12QJ1600
VOCM
RADC_IN
IDC EN
RISO
VOD
Output Offset
10
OUT+
GND
EN
图 8-2. LMH32401-Q1 to ADC Interface With a Matching Resistor Network
2 × R
ADC_IN
A = 2 kΩ or 20 kΩ × 1.2 ×
(3)
Z
2 × R
ADC_IN
+ 2 × R + 20 Ω
ISO
Where:
•
•
•
AZ = Gain from the TIA input to the ADC input
RADC_IN = Differential input resistance of the ADC
RISO = Series resistance between the TIA and ADC
方程式 4 gives the voltage to be applied at VOD (pin 9) if a certain differential offset voltage (VOD) is needed at
the ADC input for the circuit in 图 8-2.
2 × R
ADC_IN
+ 2 × R + 20 Ω
ISO
1
1.2
V
= V
×
OD
×
(4)
VOD
2 × R
ADC_IN
Where:
•
•
•
•
VVOD = Voltage applied at pin 9
VOD = Desired differential offset voltage at the ADC input
RADC_IN = Differential input resistance of the ADC
RISO = Series resistance between the TIA and ADC
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8.2 Typical Application
This section demonstrates the performance of the LMH32401-Q1 device when the input current flows into the
IN pin. 图 8-3 shows the circuit used to test the LMH32401-Q1 device with a voltage source. This configuration
demonstrates the use case when the photodiode anode is tied to the amplifier input and the photodiode cathode
is tied to a positive voltage greater than 2.47 V.
GAIN
VDD1
VDD2
100-mA
Clamp
1 k
10 k
IN
2 k
Differential Output ADC Driver
50- Measurement
Instrument
ISIG
R
2.4 × R
10
OUT
50
TIA
CAPD
25
1 μF
1 μF
IDC
+
+
–
CLOAD
2.47 V
Ambient Light
Cancellation
–
25
GND
IDC EN
R
2.4 × R
10
VDD
OUT+
VREF
VDD
Voltage-to-Current Converter
17 k
50.4 k
VOCM
VOD
3 k
25 k
GND
EN
图 8-3. LMH32401-Q1 Test Circuit
8.2.1 Design Requirements
The objective is to design a low-noise, wideband differential output transimpedance amplifier. The design
requirements are as follows:
•
•
•
•
•
•
Amplifier supply voltage: 3.3 V
Transimpedance gain: 2 kΩ and 20 kΩ
Input capacitance: CPCB ≅ 1 pF
Target bandwidth: > 250 MHz
Differential output offset (VOD): 0 V
Ambient light cancellation (IDC_EN): 3.3 V (disabled)
8.2.2 Detailed Design Procedure
图 8-3 shows the test circuit used to measure the LMH32401-Q1 bandwidth and transient pulse response. The
voltage source is dc biased close to the input bias voltage of the LMH32401-Q1 (approximately 2.47 V). The
internal design of the LMH32401-Q1 is optimized to only source current out of the input pin (pin 3), and all
the data shown previously are with the current flowing out of the pin. When the voltage input from the source
exceeds 2.47 V, the LMH32401-Q1 input sinks the current. Set VVOD = 0 V when the input must sink the current
from the photodiode, or in this case, the voltage source. Set the dc bias so that sum of the input ac and dc
component is always greater than the input voltage (2.47 V) when testing the LMH32401-Q1 with a network
analyzer or sinusoidal source.
图 8-4 and 图 8-5 shows the bandwidth of the LMH32401-Q1 when the device input is sinking the current.
The input current range of the LMH32401-Q1 is reduced when the device input is sinking the current. This
effect is seen by the decrease in bandwidth as the output swing increases and is more pronounced in a gain
configuration of 20 kΩ. Compare 图 8-4 with 图 6-1 and 图 6-3 to see the effect of current direction and input
range in a 2-kΩ gain configuration. In a similar way, compare 图 8-5 with 图 6-2 and 图 6-4 to see the effect of
current direction and input range in a gain of 20 kΩ.
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图 8-6 and 图 8-7 show the pulsed-output response of the LMH32401-Q1 when the input current is increased
past the amplifier linear input range. When the input is sinking current, a soft clamp aids in fast recovery;
however, the pulse stretches slightly as the input current overrange increases. Compare 图 8-6 with 图 6-21 to
see the pulse extension effect in a gain of 2 kΩ. Compare 图 8-7 with 图 6-22 to see the pulse extension effect
in a gain of 20 kΩ. Knowledge of the pulse extension is used to determine the approximate input current, even
under overrange situations that can occur because of the presence of retro-reflectors in the environment. As 图
7-1 shows, each half of the differential output pulse swings greater than or less than the VOCM voltage, and the
resulting maximum differential output swing is 0.75 VPP because VOD is set to 0 V. Consequently, only half of
the total ADC range is used in this photodiode configuration.
8.2.3 Application Curves
69
66
63
60
57
54
51
89
86
83
80
77
74
71
VOUT = 0.1 VPP
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 0.1 VPP
VOUT = 0.5 VPP
VOUT = 1 VPP
10M
100M
Frequency [Hz]
1G
10M
100M
Frequency [Hz]
1G
图 8-4. Bandwidth vs Output Swing
图 8-5. Bandwidth vs Output Swing
(Gain = 2 kΩ)
(Gain = 20 kΩ)
1
1
IIN = 500 mA
IIN = 1 mA
IIN = 2.5 mA
IIN = 50 mA
IIN = 100 mA
IIN = 500 mA
IIN = 1 mA
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.25
Time (5 ns/div)
Time (5 ns/div)
图 8-6. Pulse Response vs Input Current
图 8-7. Pulse Response vs Input Current
(Gain = 2 kΩ)
(Gain = 20 kΩ)
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8.3 Power Supply Recommendations
The LMH32401-Q1 operates on 3.3-V supplies. The VDD1 and VDD2 pins must always be driven from the
same supply source and individually bypassed. A low power-supply source impedance must be maintained
across frequency. Therefore, use multiple bypass capacitors in parallel. Place the bypass capacitors as close
as possible to the supply pins. Place the smallest capacitor on the same side of the PCB as the LMH32401-Q1
device. If possible, place the larger-valued bypass capacitors on the same side of the PCB. However, if space
constraints are an issue, then the capacitors can be moved to the opposite side of the PCB using multiple vias to
reduce the series inductance resulting from the vias. To operate the LMH32401-Q1 on bipolar supplies, connect
pins 1 and 7 to the negative supply. Always connect the thermal pad to the most negative supply. The digital pin
threshold voltages must be appropriately level shifted because the pins are connected to voltages at pins 1 and
7.
8.4 Layout
8.4.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier, such as the LMH32401-Q1, requires careful
attention to board layout parasitics and external component types. Recommendations that optimize performance
include the following:
•
Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the
output pins can cause instability; whereas, parasitic capacitance on the input pin reduces the amplifier
bandwidth. To reduce unwanted capacitance, cut out the power and ground traces under the signal input and
output pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.
•
Minimize the distance from the power-supply pins to high-frequency bypass capacitors. Use high-
quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three times
greater than the amplifiers maximum power supplies. Place the smallest-value capacitors on the same side
as the DUT. If space constraints force the larger-value bypass capacitors to be placed on the opposite
side of the PCB, then use multiple vias on the supply and ground side of the capacitors. This configuration
provides a low-impedance path to the amplifiers power-supply pins across the amplifiers gain bandwidth
specification. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency
must be used on the supply pins. Place these decoupling capacitors further from the device. Share the
decoupling capacitors among several devices in the same area of the printed circuit board (PCB).
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8.4.2 Layout Example
GND
Place bypass capacitors close to VDD
and GND pins on the same side as
DUT. Use multiple vias to connect to
power and ground planes
GAIN
16
NC
15
VDD2 NC
13
14
VOCM
Optional capacitor to
reduce VOCM noise from
internal resistors
GND
VDD1
IN
1
12
11
10
9
GND
OUT−
OUT+
VOD
2
3
4
Remove ground and power
planes near output pins to
minimize parasitic PCB
capacitance. Add resistors
to further isolate parasitics.
Remove ground and power
planes between IN and APD to
minimize parasitic capacitance
Thermal Pad
Optional capacitor to
reduce VOD noise from
internal resistors
NC
−VBIAS
GND
5
6
7
8
Optional isolation resistor to dampen
resonance due to bond wire
inductances and component
capacitances
IDC_EN
EN
NC
GND
图 8-8. Layout Recommendation
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
For development support on this product, see the following:
•
•
•
Texas Instruments, LMH32401 Transimpedance Amplifier Evaluation Module.
Texas Instruments, Optical Front-End System Reference Design design guide.
Texas Instruments, LIDAR-Pulsed Time-of-Flight Reference Design Using High-Speed Data Converters
design guide.
•
Texas Instruments, LIDAR Pulsed Time of Flight Reference Design design guide.
9.2 Documentation Support
9.2.1 Related Documentation
•
•
•
•
•
Texas Instruments, LMH32401IRGT Evaluation Module user's guide.
Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report.
Texas Instruments, What You Need To Know About Transimpedance Amplifiers – Part 1 blog.
Texas Instruments, An Introduction to Automotive LIDAR.
Texas Instruments, Maximizing the Dynamic Range of Analog Front Ends Having a Transimpedance
Amplifier.
•
•
•
•
•
Texas Instruments, Time of Flight and LIDAR – Optical Front End Design.
Texas Instruments, What You Need To Know About Transimpedance Amplifiers – Part 2 blog.
Texas Instruments, Training Video: How to Design Transimpedance Amplifier Circuits.
Texas Instruments, Training Video: High-Speed Transimpedance Amplifier Design Flow.
Texas Instruments, Training Video: How to Convert a TINA-TI Model into a Generic SPICE Model.
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
XLMH32401QWRGTRQ1
VQFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
XLMH32401QWRGTRQ1
Package Type
Package Drawing Pins
RGT 16
SPQ
Length (mm) Width (mm)
367.0 367.0
Height (mm)
VQFN
3000
35.0
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PACKAGE OUTLINE
RGT0016K
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
A
-
A
4
0
.
0
0
0
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.66 0.1
(0.2) TYP
EXPOSED
THERMAL PAD
5
8
12X 0.5
4
9
(0.16)
TYP
4X
SYMM
A
A
17
1.5
1
12
0.3
0.2
16X
PIN 1 ID
(OPTIONAL)
16
13
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4229414/A 02/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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Product Folder Links: LMH32401-Q1
English Data Sheet: SBOSAF0
LMH32401-Q1
ZHCSS23 – APRIL 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
RGT0016K
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.66)
SYMM
16
13
16X (0.6)
1
12
16X (0.25)
SYMM
17
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4229414/A 02/2023
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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Product Folder Links: LMH32401-Q1
English Data Sheet: SBOSAF0
LMH32401-Q1
ZHCSS23 – APRIL 2023
www.ti.com.cn
EXAMPLE STENCIL DESIGN
RGT0016K
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.51)
16
13
16X (0.6)
1
12
16X (0.25)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
84% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4229414/A 02/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Product Folder Links: LMH32401-Q1
English Data Sheet: SBOSAF0
PACKAGE OPTION ADDENDUM
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4-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
XLMH32401QWRGTRQ1
ACTIVE
VQFN
RGT
16
3000
TBD
Call TI
Call TI
-40 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMH32401-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2023
Catalog : LMH32401
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
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