XOPA2863QDRQ1 [TI]
汽车类双路低功耗 110MHz 12V RRIO 电压反馈放大器 | D | 8 | -40 to 125;
| 型号： | XOPA2863QDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类双路低功耗 110MHz 12V RRIO 电压反馈放大器 | D | 8 | -40 to 125 放大器 |
| 文件： | 总35页 (文件大小：2412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA2863-Q1
ZHCSQ66 –FEBRUARY 2023
OPAx863-Q1 低功耗、110MHz、轨至轨输入和输出汽车级放大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
OPAx863-Q1 器件是单位增益稳定的低功耗、轨至轨
输入/输出、电压反馈运算放大器，需在 2.7V 至 12.6V
的电源电压范围内运行。OPAx863-Q1 器件每通道仅
消耗700µA 的电流，提供的增益带宽积为50MHz、压
摆率为105V/µs，电压噪声密度为5.9nV/√Hz。
– 温度等级1：–40°C 至+125°C，TA
• 宽带宽
– 单位增益带宽：110MHz
– 增益带宽积：50 MHz
• 低功耗
轨到轨输入级使得 OPAx863-Q1 适用于电流检测和光
电二极管接口等通用应用。轨到轨输入级可在整个输入
共模电压范围内很好地适应增益带宽积和噪声，从而在
宽输入动态范围内实现出色的性能。
– 静态电流：700 µA/通道（典型值）
– 电源电压：2.7V 至12.6V
• 输入电压噪声：5.9 nV/√Hz
• 压摆率：105 V/µs
• 轨到轨输入和输出
• HD2/HD3：在20 kHz (2VPP) 时为–129dBc/–
138dBc
OPAx863-Q1 器件包括过载功率限制功能，可限制输
出饱和时 IQ 的增加，从而避免功耗敏感型系统中出现
过度功率耗散。输出级具有短路保护功能，使得该器件
适用于恶劣的环境。
• 其他特性：
– 过载功率限制
– 输出短路保护
封装信息(1)(2)
封装尺寸（标称值）
器件型号
封装
OPA2863-Q1
D（SOIC，8）
4.90mm × 3.91mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 有关相关产品，请参阅器件比较
• 低侧电流检测
• 直流/直流转换器
• 逆变器和电机控制
• 车载充电器和无线充电器
• HVAC 压缩机
• 光电二极管TIA 接口
• 抬头显示
-20
HD2, VOUT = 2 VPP
HD3, VOUT = 2 VPP
HD2, VOUT = 4 VPP
-40
HD3, VOUT = 4 VPP
-60
-80
-100
-120
-140
-160
CF
LED
Driver
RF
VCC
ID
OPAx863-Q1
–
+
LED
To
ADC
Photo-
Diode
VOUT
GND
VEE
1k
10k
100k
1M
10M
Frequency (Hz)
–VBIAS
Transimpedance Amplifier Circuit
G = 1V/V 时的失真性能
Switching
Circuit
RF
ISH
To comparator
VCC
OPAx863-Q1
VOUT
for fault detection
RG
–
+
RSH
To MCU/
ADC
RG
GND
GND
VREF
Low-side Current Sensing
采用以下器件的应用电路： OPAx863-Q1
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSAB2
OPA2863-Q1
ZHCSQ66 –FEBRUARY 2023
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Low-Side Current Sensing........................................19
9.3 Front-End Gain and Filtering.....................................21
9.4 Power Supply Recommendations.............................21
9.5 Layout....................................................................... 22
10 Device and Documentation Support..........................24
10.1 Documentation Support.......................................... 24
10.2 接收文档更新通知................................................... 24
10.3 支持资源..................................................................24
10.4 Trademarks.............................................................24
10.5 静电放电警告.......................................................... 24
10.6 术语表..................................................................... 24
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics: VS = ±5 V ..........................5
7.6 Electrical Characteristics: VS = 3 V.............................6
7.7 Typical Characteristics: VS = 10 V.............................. 8
7.8 Typical Characteristics: VS = 3 V.............................. 12
7.9 Typical Characteristics: VS = 3 V to 10 V..................14
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................16
Information.................................................................... 24
11.1 Tape and Reel Information......................................28
4 Revision History
DATE
REVISION
NOTES
February 2023
*
Initial Release
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5 Device Comparison Table
VOLTAGE NOISE
IQ / CHANNEL GBWP SLEW RATE
DEVICE
±VS (V)
±6.3
AMPLIFIER DESCRIPTION
(mA)
(MHz)
(V/µs)
(nV/√Hz)
OPAx863-Q1
OPAx365-Q1
0.70
50
105
5.9
4.5
Unity-gain stable RRIO Bipolar Amplifier
Unity-gain stable, zero-crossover RRIO
CMOS amplifier
±2.75
4.6
0.9
1
50
50
25
24
Gain of 6V/V stable, NRI/RRO CMOS
amplifier
OPAx607-Q1
OPAx836-Q1
±2.75
±2.75
3.8
4.6
Unity-gain stable, low-power, NRI/RRO
Bipolar Amplifier
110
560
6 Pin Configuration and Functions
VOUT1
1
VS+
8
7
6
5
VIN1-
2
VOUT2
VIN1+
3
VIN2-
VIN2+
VS-
4
图6-1. D Package,
8-Pin SOIC
(Top View)
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
VIN1–
VIN1+
VIN2–
VIN2+
VOUT1
VOUT2
VS–
NO.
2
I
I
Amplifier 1 inverting input pin
Amplifier 1 noninverting input pin
Amplifier 2 inverting input pin
Amplifier 2 noninverting input pin
Amplifier 1 output pin
3
6
I
5
I
1
O
O
P
P
7
Amplifier 2 output pin
4
Negative power-supply pin
Positive power-supply pin
VS+
8
(1) I = input, O = output, and P = power.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage
VS– to VS+
13
1
Supply turn-on/off maximum dV/dt
V/µs
V
VI
VID
II
Input voltage
VS+ + 0.5
±1
VS– –0.5
Differential input voltage
Continuous input current(2)
Continuous output current(3)
Continuous power dissipation
Maximum junction temperature
Operating free-air temperature
Storage temperature
V
±10
mA
mA
IO
±30
See Thermal Information
150
TJ
°C
°C
°C
TA
125
150
–40
–65
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Continuous input current limit for both the ESD diodes to supply pins and amplifier differential input clamp diode. The differential input
clamp diode limits the voltage across it to 1 V with this continuous input current flowing through it.
(3) Long-term continuous current for electromigration limits.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
10
MAX
12.6
125
UNIT
V
VS+ - VS– Total supply voltage
TA Ambient temperature
25
°C
–40
7.4 Thermal Information
OPA2863-Q1
D (SOIC)
8 PINS
120.0
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
63.3
Junction-to-board thermal resistance
63.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
17.2
YJB
62.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics: VS = ±5 V
at G = 1 V/V, RF = 0 Ωfor G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced to mid-supply,
input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
GBWP
LSBW
Small-signal bandwidth
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
VOUT = 20 mVPP, G = 1
110
50
MHz
MHz
MHz
MHz
V/µs
ns
VOUT = 2 VPP
17
VOUT = 20 mVPP
15
SR
105
9
VOUT = 2–V step, G = –1
VOUT = 200–mV step
Rise, fall time
Settling time to 0.1%
Settling time to 0.01%
Overshoot/undershoot
57
ns
%
VOUT = 2–V step
70
1
VOUT = 2–V step
70
G = –1, 0.5 V overdrive beyond supplies
G = 1, 0.5 V overdrive beyond supplies
Overdrive recovery time
ns
100
–129
–138
–107
–125
5.9
HD2
HD3
HD2
HD3
eN
Second-order harmonic distortion
Third-order harmonic distortion
Second-order harmonic distortion
Third-order harmonic distortion
Input voltage noise
f = 20 kHz, VOUT = 2 VPP
f = 100 kHz, VOUT = 2 VPP
dBc
dBc
Flatband, 1/f corner at 25 Hz
Flatband, 1/f corner at 2 kHz
f = 1 MHz
nV/√Hz
pA/√Hz
iN
Input current noise
0.4
Closed-loop output impedance
Channel-to-channel crosstalk
0.2
Ω
f = 1 MHz, VOUT = 2 VPP
dBc
–124
DC PERFORMANCE
AOL
VOS
Open-loop voltage gain
VOUT = ±2.5 V
110
–1.3
–3.5
128
±0.4
±1
dB
Input-referred offset voltage
Input offset voltage drift
1.3
mV
3.5 µV/°C
0.73
1.2
1.6
7.6 nA/°C
TA = –40°C to +125°C, D package
TA ≅ 25°C
0.3
Input bias current
µA
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +125°C
Input bias current drift
Input offset current
±3
-30
±10
30
nA
INPUT
Input common-mode voltage range
Common-mode rejection ratio
VS++0.2
V
VS––0.2
CMRR
100
120
650 || 0.8
200 || 0.5
dB
VCM=VS––0.2 V to VS+ –1.6 V
Input impedance common-mode
Input impedance differential mode
MΩ|| pF
kΩ|| pF
OUTPUT
VS–+0.14
VS–+0.2
TA ≅ 25°C
VOL
Output voltage, low
Output voltage, high
V
V
VS–+0.15 VS–+0.22
TA = –40°C to +125°C
TA ≅ 25°C
VS+–0.2 VS+–0.14
VS+–0.2 VS+–0.15
VOH
TA = –40°C to +125°C
Linear output drive (sourcing/
sinking)
VOUT = ±2.5 V, ΔVOS < 1 mV(2)
25
30
45
mA
mA
Short-circuit current
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7.5 Electrical Characteristics: VS = ±5 V (continued)
at G = 1 V/V, RF = 0 Ωfor G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced to mid-supply,
input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
700
970
TA ≅ 25°C
IQ
Quiescent current per amplifier
Power-supply rejection ratio
µA
dB
1280
TA = –40°C to +125°C
ΔVS = ±2 V(1)
PSRR
100
120
AUXILIARY INPUT STAGE
Gain-bandwidth product
50
6
MHz
nV/√Hz
pA/√Hz
mV
Input voltage noise
Flatband, 1/f corner at 25 Hz
Flatband, 1/f corner at 100 Hz
Input current noise
0.4
Input-referred offset voltage
±0.15
0.2
1.3
0.6
1.3
–1.3
TA ≅ 25°C
Input bias current
µA
0.2
TA = –40°C to +125°C
VCM = 4.1 V to 5.2 V
ΔVS = ±0.6 V
Common-mode rejection ratio
Power supply rejection ratio
100
100
120
120
dB
dB
(1) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.
(2) Change in input offset voltage from no-load condition.
7.6 Electrical Characteristics: VS = 3 V
at G = 1, RF = 0 Ωfor G =1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected to 1 V, input and
output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
GBWP
LSBW
Small-signal bandwidth
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
VOUT = 20 mVPP, G = 1
97
50
MHz
MHz
MHz
MHz
V/µs
ns
VOUT = 1 VPP
26
VOUT = 20 mVPP
10
SR
105
10
VOUT = 1–V step, Gain = –1
VOUT = 200–mV step
Rise, fall time
Settling time to 0.1%
Settling time to 0.01%
Overshoot
58
ns
%
VOUT = 1–V step
VOUT = 1–V step
90
2
Undershoot
16
95
G = –1, 0.5V overdrive beyond supplies
Overdrive recovery time
ns
G = 1, 0.5V overdrive beyond supplies
100
–123
–132
–109
–129
6
HD2
HD3
HD2
HD3
eN
Second-order harmonic distortion
Third-order harmonic distortion
Second-order harmonic distortion
Third-order harmonic distortion
Input voltage noise
f = 20 kHz, VOUT = 1 VPP
f = 100 kHz, VOUT = 1 VPP
dBc
dBc
Flatband, 1/f corner at 25 Hz
Flatband, 1/f corner at 2 kHz
f = 1 MHz
nV/√Hz
pA/√Hz
iN
Input current noise
0.4
Closed-loop output impedance
Channel-to-channel crosstalk
0.2
Ω
f = 1 MHz, VOUT = 1 VPP
dBc
–127
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7.6 Electrical Characteristics: VS = 3 V (continued)
at G = 1, RF = 0 Ωfor G =1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected to 1 V, input and
output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PERFORMANCE
AOL
VOS
Open-loop voltage gain
Input-referred offset voltage
Input offset voltage drift
VOUT = 1 V to 2 V
104
–1.3
–3.5
123
±0.4
±1
dB
1.3
mV
3.5 uV/°C
0.73
1.2
1.56
7.4 nA/°C
TA = –40°C to +125°C, D package
TA ≅ 25°C
0.3
Input bias current
µA
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +125°C
Input bias current drift
Input offset current
±3
-30
±10
30
nA
INPUT
Input common-mode voltage range
Common-mode rejection ratio
VS++0.2
V
VS––0.2
CMRR
94
115
360 || 0.9
200 || 0.5
dB
VCM = VS––0.2 V to VS+ –1.6 V
Input impedance common-mode
Input impedance differential mode
MΩ|| pF
kΩ|| pF
OUTPUT
VS–+ 0.13 VS–+ 0.15
VS–+ 0.13 VS–+ 0.16
TA ≅ 25°C
VOL
Output voltage, low
Output voltage, high
V
V
TA = –40°C to +125°C
TA ≅ 25°C
VS+–0.15 VS+–0.13
VS+–0.15 VS+–0.13
VOH
TA = –40°C to +125°C
Linear output drive (sourcing/
sinking)
VOUT = ±0.7 V, ΔVOS < 1 mV(2)
23
33
45
mA
mA
Short-circuit current
POWER SUPPLY
690
120
910
TA ≅ 25°C
IQ
Quiescent current per amplifier
µA
dB
1180
TA = –40°C to +125°C
ΔVS = ±1 V(1)
PSRR
Power-supply rejection ratio
100
AUXILIARY INPUT STAGE
Gain-bandwidth product
50
6
MHz
nV/√Hz
pA/√Hz
mV
Input voltage noise
Flatband, 1/f corner at 25 Hz
Flatband, 1/f corner at 100 Hz
Input current noise
0.4
Input-referred offset voltage
±0.15
0.2
1.3
0.6
1.2
–1.3
TA ≅ 25°C
Input bias current
µA
0.4
TA = –40°C to +125°C
VCM = 2.1 V to 3.2 V
ΔVS = ±0.6 V
Common-mode rejection ratio
Power supply rejection ratio
100
100
120
115
dB
dB
(1) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.
(2) Change in input offset voltage from no-load condition.
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7.7 Typical Characteristics: VS = 10 V
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
3
0
3
0
-3
-3
-6
-6
-9
-9
-12
-15
-18
-21
-12
-15
-18
-21
G = 1 V/V
G = -1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
RL = 2 k
RL = 500
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
100M
Frequency (Hz)
VOUT = 20 mVPP
VOUT = 20 mVPP
图7-1. Small-Signal Frequency Response vs Gain
图7-2. Small-Signal Frequency Response vs Output Load
6
1
3
0
0.5
0
-3
No CL
CL = 2.2 pF
-0.5
-6
CL =4.7 pF
G = 1 V/V
G = 2 V/V
CL = 10 pF, Rs = 200
CL = 10 pF, G = 2 V/V
-9
-1
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
VOUT = 20 mVPP
VOUT = 20 mVPP
图7-4. Small-Signal Response Flatness vs Gain
图7-3. Frequency Response vs Load Capacitance
3
6
3
0
0
-3
-3
-6
VOUT = 20 mVPP
VOUT = 200 mVPP
VOUT = 500 mVPP
VOUT = 1 VPP
-6
VOUT = 2 VPP
VOUT = 4 VPP
VOUT = 8 VPP
TA = 25°C
TA = 125°C
TA = −45 °C
-9
-9
100k
-12
1M
1M
10M
100M
10M
Frequency (Hz)
100M
Frequency (Hz)
.
VOUT = 20 mVPP
图7-6. Frequency Response vs Output Voltage
图7-5. Frequency Response vs Ambient Temperature
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7.7 Typical Characteristics: VS = 10 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
3
3
0
0
-3
-3
-6
-9
-6
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
-9
TA = 25°C
TA = 125 °C
TA = −45 °C
-12
100k
100k
1M
10M
Frequency (Hz)
100M
1M
10M
100M
Frequency (Hz)
VOUT = 2 VPP
VOUT = 2 VPP
图7-7. Large-Signal Frequency Response vs Gain
图7-8. Frequency Response vs Ambient Temperature
-20
-20
HD2, G = 1 V/V
HD3, G = 1 V/V
HD2, G = 2 V/V
HD3, G = 2 V/V
HD2, VOUT = 2 VPP
HD3, VOUT = 2 VPP
HD2, VOUT = 4 VPP
HD3, VOUT = 4 VPP
-40
-60
-40
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
1k
10k
100k
Frequency (Hz)
1M
10M
1k
10k
100k
Frequency (Hz)
1M
10M
G = 1 V/V
VOUT = 2 VPP
图7-9. Harmonic Distortion vs Frequency
图7-10. Harmonic Distortion vs Gain
0.15
6
0.1
0.05
0
4
2
0
-0.05
-0.1
-0.15
-2
-4
-6
Time (200 ns/div)
Time (50 ns/div)
.
.
图7-11. Small-Signal Transient Response
图7-12. Large-Signal Transient Response
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7.7 Typical Characteristics: VS = 10 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
6
6
4
4
2
2
0
0
-2
-4
-6
-2
-4
-6
Input
Output
Input x -1 V/V
Output
Time (100 ns/div)
Time (100 ns/div)
Gain = 1 V/V
Gain = -1 V/V
图7-13. Input Overdrive Recovery
图7-14. Output Overdrive Recovery
1200
900
600
300
0
1000
750
500
250
0
-250
-500
-750
-1000
-300
-600
-6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
-5.5 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
Measured for 10 units
.
图7-15. Input Offset Voltage vs Input Common-Mode Voltage
图7-16. Input Bias Current vs Input Common-Mode Voltage
6
50
40
30
20
4
2
10
Sourcing
Sourcing
0
Sinking
Sinking
0
-10
-20
-30
-40
-50
-2
-4
-6
0
5
10
15
20
25
30
35
-40
-20
0
20
40
60
80
100 120 140
Output Current (mA)
Ambient Temperature (°C)
.
Output saturated and then short-circuited to opposite supply
图7-17. Output Voltage vs Load Current
图7-18. Output Short-Circuit Current vs Ambient Temperature
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7.7 Typical Characteristics: VS = 10 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
20000
9000
18000
8000
16000
7000
14000
6000
12000
5000
10000
4000
8000
3000
6000
2000
4000
1000
2000
0
0
Quiescent Current per Channel (A)
μ= 678 μA, σ= 13 μA
Input Bias Current (nA)
μ= 251 nA, σ= 5.6 nA
图7-19. Quiescent Current Distribution
图7-20. Input Bias Current Distribution
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.55
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (°C)
μ
Input Offset Voltage ( V)
35 units
μ= 209 μV, σ= 193 μV
图7-22. Quiescent Current vs Ambient Temperature
图7-21. Input Offset Voltage Distribution
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7.8 Typical Characteristics: VS = 3 V
at VS+ = 3 V, VS– = 0 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected to 1
V, G = 1 V/V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
3
0
-3
-6
-9
-12
G = 1 V/V
-15
-18
-21
G = -1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
100k
1M
10M
Frequency (Hz)
100M
VOUT = 20 mVPP
VOUT = 1 VPP
图7-23. Small-Signal Frequency Response vs Gain
图7-24. Harmonic Distortion vs Frequency
0.15
1
0.1
0.05
0
0.5
0
-0.05
-0.1
-0.5
-0.15
-1
Time (200 ns/div)
Time (50 ns/div)
.
.
图7-25. Small-Signal Transient Response
图7-26. Large-Signal Transient Response
1000
1000
750
800
600
400
200
0
500
250
0
-250
-500
-750
-1000
-200
-400
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
Measured for 10 units
.
图7-27. Input Offset Voltage vs Input Common-Mode Voltage
图7-28. Input Bias Current vs Input Common-Mode Voltage
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7.8 Typical Characteristics: VS = 3 V (continued)
at VS+ = 3 V, VS– = 0 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected to 1
V, G = 1 V/V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
3
2.5
2
Sourcing
Sinking
1.5
1
0.5
0
0
5
10
15
20
25
30
35
40
Output Current (mA)
.
图7-29. Output Voltage vs Load Current
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7.9 Typical Characteristics: VS = 3 V to 10 V
At VOUT = 2 VPP, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced to mid-
supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
3
3
0
0
-3
-3
-6
-6
-9
-9
VS = 10 V
VS = 5 V
VS = 3 V
VS = 10 V
VS = 5 V
VS = 3 V
-12
-12
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
100M
Frequency (Hz)
VOUT = 20 mVPP
VOUT = 1 VPP
图7-30. Frequency Response vs Supply Voltage
图7-31. Frequency Response vs Supply Voltage
100
10
Main Stage
Auxiliary Stage
10
1
1
10
10
100
1k
10k
100k
1M
100
1k 10k
Frequency (Hz)
100k
1M
Frequency (Hz)
D401
.
.
图7-33. Input Current Noise Density vs Frequency
图7-32. Input Voltage Noise Density vs Frequency
140
140
PSRR−
PSRR+
120
100
80
60
40
20
0
120
100
80
60
40
20
-20
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
.
.
图7-34. Common-Mode Rejection Ratio vs Frequency
图7-35. Power Supply Rejection Ratio vs Frequency
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7.9 Typical Characteristics: VS = 3 V to 10 V (continued)
At VOUT = 2 VPP, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced to mid-
supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
100
80
60
40
20
0
135
120
105
90
210
180
150
120
90
Magnitude
Phase
75
60
60
45
30
30
0
15
-30
-60
-90
0
-15
1
10
100
1k
10k 100k
1M
10M 100M
1
10
100
1k
10k 100k
1M
10M 100M
Frequency (Hz)
Frequency (Hz)
.
Small-signal response
图7-36. Open-Loop Output Impedance vs Frequency
图7-37. Open-Loop Gain and Phase vs Frequency
-40
-60
-80
-100
-120
-140
-160
HD2, VS = 10 V
HD3, VS = 10 V
HD2, VS = 5 V
HD3, VS = 5 V
1k
10k
100k
Frequency (Hz)
1M
10M
VOUT = 2 VPP
图7-38. Harmonic Distortion vs Supply Voltage
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8 Detailed Description
8.1 Overview
The OPAx863-Q1 devices are low-power, 50 MHz, rail-to-rail input and output (RRIO) bipolar voltage-feedback
operational amplifiers with a voltage noise density of 5.9 nV/√Hz and 1/f noise corner at 25 Hz. The OPAx863-
Q1 devices work in a wide-supply voltage range from 2.7 V to 12.6 V and consumes only 700 µA quiescent
current. The OPAx863-Q1 devices operate with 2.7 V supply, are RRIO capable, consume low-power, and offer
a power-down mode, which makes them ideal amplifiers for 3.3-V or lower voltage applications that need
superior AC performance. The main and auxiliary input stages of the amplifier are matched for gain bandwidth
product (GBW), noise and offset voltage suitable for applications which require wide dynamic input range and
good SNR.
The device includes an overload power limit feature which limits the increase in quiescent current with over-
driven and saturated outputs to either of the supply rails. For more details of this overload power limit feature,
see 节8.3.2.1. The output of the amplifier is protected against short-circuit fault conditions.
8.2 Functional Block Diagram
PD
VS+
OPAx863-Q1
Auxiliary
NPN-
+
–
Stage
VIN+
EN
Output
Short-Circuit
Protection
CC
Main
PNP-
Stage
VOUT
+
–
Overload
Power
EN
Limiting
–
–
+
VIN–
VS+ –1.6 V
VS–
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8.3 Feature Description
8.3.1 Input Stage
The OPAx863-Q1 devices include a rail-to-rail input stage. The main stage differential pair using PNP bipolar
transistors operates for common-mode input voltages from VS–– 0.2 V till VS+ – 1.6 V. The amplifier inputs
transition into the auxiliary stage using NPN transistors for common-mode input voltages from VS+ – 1.6 V till
VS+ + 0.2 V. The PNP and NPN input stages offer a gain-bandwidth product of 50 MHz and a voltage noise
density of 5.9 nV/√Hz. The offset voltage for the two input stages is matched to lie within the device
specifications. The NPN input stage does not use the slew boost circuit during large-signal transient response.
The input bias current for the PNP and NPN input stages is opposite in polarity, which adds an additional offset
based on the values of the gain-setting and feedback resistors. A common-mode input voltage transition
between these input stages will cause a crossover distortion which needs to be considered in high-frequency
applications requiring superior linearity. Limit the common-mode input voltage to VS+ – 1.6 V (maximum) for
main-stage operation across process and ambient temperature.
Since the OPAx863-Q1 devices are bipolar amplifiers, the two inputs are protected with anti-parallel back-to-
back diodes between them, which limits the maximum input differential voltage to 1 V. The amplifier is slew
limited, and the two inputs are pulled apart up to 1 V when the anti-parallel diodes begin to conduct in very fast
input or output transient conditions. Care must be taken to use gain-setting and feedback resistors large enough
to limit the current through these diodes in such conditions.
8.3.2 Output Stage
The OPAx863-Q1 devices feature a rail-to-rail output stage with possible signal swing from VS–+ 0.2 V to VS+–
0.2 V. Violating the output headroom to either of the supplies will cause output signal clipping and introduce
distortion.
The OPAx863-Q1 devices integrate an output short-circuit protection circuit, which makes the device rugged for
use in real-world applications.
8.3.2.1 Overload Power Limit
The OPAx863-Q1 devices include overload power limiting which limits the increase in device quiescent current
with output saturated to either of the supplies. Typically, when the output of the amplifier saturates, the amplifiers
two inputs are pulled apart which can enable the slew boost circuit. The input differential voltage is an error
voltage in negative feedback, which the amplifier core nullifies by engaging the slew boost circuit and driving the
output stage deeper into saturation. Once the input to an amplifier attains a value large enough to saturate its
output, any further increase in this input excitation results in a finite input differential voltage. As the output stage
transistor is pushed deeper into saturation, its hFE (base-to-collector current gain) drops with increase in its base
and collector current, increasing the device quiescent current. This may cause a catastrophic failure in multi-
channel, high-gain, high-density front-end designs and reduce operating lifetime in portable battery powered
systems.
The OPAx863-Q1 devices overload power limiting includes an intelligent output saturation detection circuit which
limits the device's quiescent current to 2.2-mA per channel under DC overload conditions. This increase in
quiescent current is smaller with AC input or output and output saturation duration for only a fraction of the
overall signal time period. Table 8-1 provides a comparison of the increase in quiescent current with 50 mV input
overdrive for OPAx863-Q1 devices and other voltage feedback amplifiers without overload power limit.
表8-1. Quiescent Current with Saturated Outputs
Device
Input Differential
Voltage
Quiescent Current
Increase in IQ from
steady-state
condition
OPAx863-Q1 with overload power limit
50 mV
50 mV
1.1 mA
1.57x
3.43x
Competitor amplifier without overload power limit
1.96 mA
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8.3.3 ESD Protection
As 图 8-1 shows, all device pins are protected with internal ESD protection diodes to the power supplies. These
diodes provide moderate protection to input overdrive voltages above the supplies. The protection diodes can
typically support 10-mA continuous input and output currents. Use series current limiting resistors if the input
voltages exceeding the supply voltages occur at the amplifier inputs, which ensures the current through the ESD
diodes remains within their rated value. Since OPAx863-Q1 is a bipolar amplifier, the two inputs are protected
with anti-parallel back-to-back diodes between them which limits the maximum input differential voltage to
approximately 1 V. Care must be taken to use gain-setting and feedback resistors large enough to limit the
current through these diodes in fast slewing conditions.
VS+
Power Supply
ESD Cell
VIN+
PD
+
œ
VOUT
VIN-
VS-
图8-1. Internal ESD Protection
8.4 Device Functional Modes
The OPAx863-Q1 is operational with a supply voltage greater than 2.7 V (±1.35 V). The maximum
recommended supply voltage is 12.6 V (±6.3 V). The OPAx863-Q1 can be used with unipolar, bipolar or
asymmetric supplies.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.2 Low-Side Current Sensing
Power converters use current-mode feedback control for superior transient response and multi-phase load
sharing. Inverter stages control the phase currents for torque control in motor drives. Due to its simplicity and
low-cost, many of these topologies use difference amplifier based low-side current sensing. 图 9-1 shows the
use of OPAx863-Q1 in a difference amplifier circuit for low-side current sensing.
300 V
3.3 V
Switching
Circuit
TLV3201
VTH
+
–
12 kΩ
Interrupt
ISH
3.3 V
3.3 V
600 Ω
600 Ω
MCU
OPAx863-Q1
–
RSH
ADS7056
Digital I/O
VOUT
+
220 pF
12 kΩ
GND
1.65 V
图9-1. Low-Side Current Sensing in Power Converters
9.2.1 Design Requirements
表9-1. Design Requirements
PARAMETER
DESIGN REQUIREMENT
Shunt resistor
Input current
10 mΩ
15 APP
Output voltage
3 VPP
50 kHz
Switching frequency
Data acquisition
1 MSPS with 0.1% accuracy
10 Vpk
Input voltage due to ground bounce
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9.2.2 Detailed Design Procedure
In a difference amplifier circuit, the output voltage is given by:
R
F
V =
I
R
+ V
REF
(1)
0
SH SH
R
G
For lowest system noise, small values of RF and RG are preferred. The smallest value of RG is limited by the
input transient voltage (10 V here) seen by the circuit, and is given by:
V
max − V − V
D S
IN
R
=
(2)
G
I
max
D
Where,
• VIN(maximum) is the maximum input transient voltage seen by the circuit
• VD is the forward voltage drop of ESD diodes at the amplifier input
• ID(maximum) is the maximum current rating of the ESD diodes at the amplifier input
For a difference amplifier gain of 20 V/V, RF and RG of 12 kΩ and 600 Ω are used, respectively. With a clock
frequency of 40 MHz and ADS7056 sampling at 1 MSPS, the available acquisition time for amplifier output
settling is 550 ns. 表 9-1 provides the simulation results for the circuit in 图 9-1. The worst-case peak-to-peak
input transient condition is simulated. The OPAx863-Q1 devices output settles to within 0.1% accuracy within
543 ns. If use of a slower clock frequency with the ADC is desired, then the acquisition time reduces with the
same sampling rate, which degrades measurement accuracy. Alternatively, the sampling rate may be reduced to
recover the required acquisition time and 0.1% accuracy.
9.2.3 Application Curves
4
3.5
3
1.2
1.1
1
2.5
2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
1
0.5
0
-0.5
-1
VIN x 20
OPAx863-Q1 O/P
S/H Voltage
% Error
-1.5
-2
Time (150 ns/div)
图9-2. 0.1% Settling Performance
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9.3 Front-End Gain and Filtering
C2
D1
RBIAS
R2
-VBIAS
VS+
C1
D2
R1
RISO
œ
VS+
œ
+
CSH
RP
+
VS-
VS-
High-Gain Band Pass Filter
High-Speed Peak Detector
图9-3. High-Gain Narrow Bandpass Filter and Peak Detector Circuit
Ultrasonic signaling is used for proximity and obstacle detection, level sensing, sonars, and so forth. Such signal
chains detect the amplitude of received ultrasonic signal at a particular center frequency. 图 9-3 shows a high-
gain narrow bandpass filter and peak detector circuit using any of the OPAx863-Q1 devices. The signal at the
frequency of interest is filtered out, gained, and peak detected to report the amplitude at the output of this circuit.
The phase information is lost in this circuit. The OPAx863-Q1 devices are used with its 50-MHz GBW to add a
single-stage gain, and the peak detection capability is easily made with the RRIO capability of these amplifiers.
9.4 Power Supply Recommendations
The OPAx863-Q1 devices are intended to operate on supplies ranging from 2.7 V to 12.6 V. The OPAx863-Q1
devices may operate on single-sided supplies, split and balanced bipolar supplies, or unbalanced bipolar
supplies. Operating from a single supply can have numerous advantages. The DC errors, due to the –PSRR
term, can be minimized with the negative supply at ground. Typically, AC performance improves slightly at 10-V
operation with minimal increase in supply current. Minimize the distance (< 0.1 in) from the power supply pins to
high-frequency, 0.01-µF decoupling capacitors. A larger capacitor (2.2 µF typical) is used along with a high-
frequency, 0.01-µF supply-decoupling capacitor at the device supply pins. Only the positive supply has these
capacitors for single-supply operation. Use these capacitors from each supply to ground when a split-supply is
used. If necessary, place the larger capacitors further from the device and share these capacitors among several
devices in the same area of the printed circuit board (PCB). An optional supply decoupling capacitor across the
two power supplies (for split-supply operation) reduces second harmonic distortion.
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9.5 Layout
9.5.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier (like the OPAx863-Q1 devices) require careful
attention to board layout parasitics and external component types. The DEM-OPA-SO-2A Demonstration Fixture
user's guide can be used as a reference when designing the circuit board. Recommendations that optimize
performance include the following:
1. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability—on the noninverting input, it can react with the source
impedance to cause unintentional band-limiting. Open a window around the signal I/O pins in all of the
ground and power planes around those pins to reduce unwanted capacitance. Otherwise, ground and power
planes must be unbroken elsewhere on the board.
2. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency 0.01-µF decoupling
capacitors. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the
supply pins. These capacitors can be placed somewhat farther from the device and shared among several
devices in the same area of the PC board.
3. Careful selection and placement of external components preserve the high frequency performance
of the OPAx863-Q1 devices. Resistors must be a low reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Other network components, such as noninverting input termination
resistors, must also be placed close to the package. Keep resistor values as low as possible and consistent
with load driving considerations. Lowering the resistor values keep the resistor noise terms low and
minimizes the effect of its parasitic capacitance. Lower resistor values, however, increases the dynamic
power consumption because RF and RG become part of the amplifiers output load network.
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9.5.2 Layout Example
VS+
Representative schematic of a
single channel
CBYP
RS
+
t
CBYP
VS-
RF
RG
Ground and power plane exist on inner
layers.
Ground and power plane removed
from inner layers. Ground fill on outer
layers also removed
CBYP
RS
Place series output resistors close
to output pin to minimize
parasitic capacitance
1
8
7
RF
RS
Place bypass capacitors
close to power pins
2
3
RG
RF
Place gain and feedback resistors close
to pins to minimize stray capacitance
6
5
RG
Place bypass capacitors
close to power pins
4
Remove GND and Power plane under
output and inverting pins to minimize
stray PCB capacitance
CBYP
图9-4. Layout Recommendation for Dual-Channel D Package
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, DEM-OPA-SO-2A Demonstration Fixture user's guide
• Texas Instruments, Single-Supply Op Amp Design Techniques application report
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
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PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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11.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
OPA2863QR
OPA2863QT
SOIC
SOIC
D
D
8
8
2500
250
330.0
180.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
2500
250
Length (mm) Width (mm)
Height (mm)
35.0
OPA2863QR
OPA2863QT
SOIC
SOIC
D
D
8
8
853.0
210.0
449.0
185.0
35.0
Copyright © 2023 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
XOPA2863QDRQ1
ACTIVE
SOIC
D
8
3000
TBD
Call TI
Call TI
-40 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2863-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2023
Catalog : OPA2863
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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