XTPS56C230RJET [TI]
针对解决方案成本进行了优化的 4.5V 至 18V、12A 同步 SWIFT™ 降压转换器 | RJE | 20;
| 型号： | XTPS56C230RJET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 针对解决方案成本进行了优化的 4.5V 至 18V、12A 同步 SWIFT™ 降压转换器 | RJE | 20 转换器 |
| 文件： | 总34页 (文件大小：3150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS56C230
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
TPS56C230 4.5V 至 18V、12A 同步降压转换器
1 特性
3 说明
1
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输入电压范围：4.5V 至 18V
TPS56C230 是一款配备集成 FET 的高效同步降压转
换器。系统设计人员可将此器件用于各种 应用 ，因为
它的待机电流低，需要的外部组件也较少。
输出电压范围：0.6V 至 5.5V
支持 12A 的连续输出电流
D-CAP3™架构控制，可实现快速瞬态响应
±1% 反馈电压精度 (25°C)
TPS56C230 采用了 D-CAP3 控制，此控制方式只需
内部补偿即可实现快速瞬态响应以及出色的线路和负载
调整。该器件具有一个专用电路，可支持低等效串联电
阻 (ESR) 输出电容器（例如专用聚合物电容器和超低
ESR 陶瓷电容器）。
集成 17mΩ 和 5.9mΩ FET
可选 Eco-mode™和强制连续导通模式 (FCCM)
（通过 MODE 引脚）
•
•
•
•
•
•
•
•
•
•
500kHz 开关频率
可使用 TPS56C230 的 MODE 引脚来设置 Eco-mode
或 FCCM 模式，以实现轻负载运行。Eco-mode 在轻
负载运行期间可保持高效率，并且 FCCM 模式运行可
在轻负载下保持低输出纹波。此器件同时支持内部和外
部软启动时间选项。它具有 1.2ms 的内部固定软启动
时间，但如果应用需要更长的软启动时间，则可以使用
外部 SS 引脚，通过连接外部电容器来实现。
可调软启动时间，默认为 1.2ms
集成式电源正常状态指示器
内置输出放电功能
逐周期过流保护
非锁存过压、欠压、过热以及欠压锁定保护功能
运行结温范围：-40°C 至 125°C
20 引脚 3.0mm × 3.0mm HotRod™VQFN 封装
与 8A TPS568230 引脚对引脚兼容
可使用 TPS56C230 并借助 WEBENCH® 电源设计
器创建定制设计方案
TPS56C230 集成了电源正常状态指示器并具备输出放
电功能。它提供包括 OVP、UVP、OCP、OTP 和
UVLO 在内的全面保护。该器件可采用 20 引脚
3.0mm × 3.0mm HotRod 封装，额定结温范围为
–40°C 至 125°C。
2 应用
•
•
•
•
数字电视和机顶盒
PC 和工业 PC
有线网络
器件信息(1)
器件型号
TPS56C230
封装
VQFN (20)
封装尺寸（标称值）
3.00mm × 3.00mm
分布式电源系统
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
效率与输出电流 Eco-mode
L
100
95
90
85
80
75
70
65
VIN
VOUT
R1
SW
VIN
VCC
TPS56C230
BST
EN
CIN
CBST
COUT
RM_H
MODE
PGOOD
VCC
FB
SS
PGOOD
R2
RM_L
AGND
PGND
Css
60
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
55
VIN=12V, VOUT=5V
1 10 15
50
0.01
0.1
I-Load (A)
D013
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDE4
TPS56C230
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
Power Supply Recommendations...................... 20
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 器件和文档支持 ..................................................... 22
11.1 器件支持 ............................................................... 22
11.2 接收文档更新通知 ................................................. 22
11.3 社区资源................................................................ 22
11.4 商标....................................................................... 22
11.5 静电放电警告......................................................... 22
11.6 Glossary................................................................ 22
12 机械、封装和可订购信息....................................... 23
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (August 2019) to Revision A
Page
•
已更改 将销售状态从“预告信息”更改为“生产数据”.................................................................................................................. 1
2
Copyright © 2019, Texas Instruments Incorporated
TPS56C230
www.ti.com.cn
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
5 Pin Configuration and Functions
RJE Package
20-Pin VQFN
Top View
SW
SW
PGND VCC
NC
18
17
20
16
19
1
15
BST
MODE
3
3
2
14 FB
VIN
4
3
4
13
PGND
VIN
AGND
VIN
4
12
11
EN
SS
VIN
5
8
6
10
7
9
NC
PGOOD
PGND PGND
SW
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST and SW, 0.1 uF is recommended.
BST
1
I
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
PGND.
VIN
2,3,4,5
P
Switching node connection to the inductor and bootstrap capacitor for buck. This pin voltage swings from a
diode voltage below the ground up to input voltage of buck.
SW
6,19,20
7,8,18,Pad
9
O
G
O
PGND
PGOOD
Power GND terminal for the controller circuit and the internal circuitry.
Open drain power good indicator. It is asserted low if output voltage is out of PG threshold, over voltage or
if the device is under thermal shutdown, EN shutdown or during soft start.
Soft-Start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the soft-start time is about 1.2ms.
SS
11
I
NC
EN
10,16
12
Not connect. Can be connected to GND plane for better thermal achieved.
Enable input of buck converter
I
AGND
13
G
Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
Feedback sensing pin for Buck output voltage. Connect this pin to the resistor divider between output
voltage and AGND.
FB
14
15
17
I
I
Light load operation mode selection pin. Connect this pin to a resistor divider from VCC and AGND for
different MODE options shown in 表 1
MODE
VCC
The driver and control circuits are powered from this voltage. Decouple with a minimum 1 μF ceramic
capacitor as close to VCC as possible.
O
Copyright © 2019, Texas Instruments Incorporated
3
TPS56C230
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–1
MAX
20
25
6
UNIT
V
VIN
BST
V
Input voltage
BST-SW
V
EN, MODE, FB, SS
PGND, AGND,
SW
6
V
0.3
20
22
6
V
V
Output voltage
SW (10-ns transient)
PGOOD
–3
V
–0.3
–40
–55
V
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22- V C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
18
UNIT
V
VIN
4.5
–0.3
–0.3
–0.3
–0.3
–1
BST
23.5
5.5
5.5
0.3
18
V
Input voltage
BST-SW
EN, MODE, FB, SS
PGND, AGND
SW
V
V
V
V
Output voltage
PGOOD
–0.3
5.5
12
V
IOUT
TJ
Output current
A
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TPS56C230
RJE (VQFN)
20 PINS
42.3
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance (standard board)
Junction-to-ambient thermal resistance (4-layer custom board)(2)
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA_effective
RθJC(top)
RθJB
28.2
26.2
Junction-to-board thermal resistance
13
ψJT
Junction-to-top characterization parameter
1.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
(2) 70 mm x 70 mm, 4 layers, thickness: 1.5 mm. 2 oz. copper traces located on the top and bottom of the PCB. 4 thermal vias in the
PowerPAD area under the device package.
4
Copyright © 2019, Texas Instruments Incorporated
TPS56C230
www.ti.com.cn
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
Thermal Information (continued)
TPS56C230
THERMAL METRIC(1)
RJE (VQFN)
20 PINS
12.4
UNIT
ψJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
RθJC(bot)
16.1
6.5 Electrical Characteristics
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage range
4.5
18
V
IVIN
Non-switching supply current
Shutdown supply current
No load, VEN=5V
400
2
μA
μA
IVINSDN
VCC OUTPUT
No load, VEN=0V
VVIN>5.0V
VVIN=4.5V
4.85
20
5
5.15
V
VCC
ICC
VCC output voltage
VCC current limit
4.5
mA
FEEDBACK VOLTAGE
VFB FB voltage
DUTY CYCLE and FREQUENCY CONTROL
TJ = 25°C
594
591
600
600
606
609
mV
mV
TJ = -40°C to 125°C
FSW
Switching frequency
SW minumum on time
SW minimum off time
TJ = 25°C
500
60
kHz
ns
tON(MIN)
tOFF(MIN)
TJ = 25°C
TJ = 25°C, VFB = 0.5 V
180
ns
MOSFET and DRIVERS
RDS(ON)H High side switch resistance
RDS(ON)L Low side switch resistance
OUTPUT DISCHARGE and SOFT START
TJ = 25°C
TJ = 25°C
17
mΩ
mΩ
5.9
RDIS
tSS
Discharge resistance
Soft start time
TJ=25°C, VEN=0V
350
1.2
5
Ω
Internal soft-start time,SS floating
ms
μA
ISS
Soft start charge current
POWER GOOD
tPGDLY PGOOD start-up delay
PGOOD from low to high
VFB falling (fault)
VFB rising (good)
VFB rising (fault)
VFB falling (good)
IOL =4mA
1
ms
%
%
%
%
V
85
90
VPGTH
PGOOD threshold
115
110
VPG_L
IPGLK
CURRENT LIMIT
PGOOD sink current capability
0.4
1
PGOOD leak current
VPGOOD =5.5V
μA
TJ = 25°C
14
13
15
15
4
16
A
A
A
IOCL
Over current threshold (valley)
Negative over current threshold
TJ = -40°C to 125°C
17.5
INOCL
LOGIC THRESHOLD
VENH
VENL
IEN
EN high-level input voltage
1.2
0.9
1.3
1.1
2
1.4
1.2
V
V
EN low-level input voltage
Enable internal pull down current
VEN=0.8V
µA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
Copyright © 2019, Texas Instruments Incorporated
5
TPS56C230
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (continued)
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
125
120
60
MAX
UNIT
%
VOVP
OVP trip threshold
tOVPDLY
VUVP
tUVPDLY
tUVPDEL
OVP prop deglitch
us
UVP trip threshold
%
UVP prop deglitch
256
1.5
us
Output Hiccup delay relative to SS time
cycle
Output Hiccup enable delay relative to SS
time
tUVPEN
10.5
cycle
UVLO
Wake up VIN voltage
4.2
3.7
0.5
4.4
V
V
VUVLOVIN
VIN UVLO threshold
Shutdown VIN voltage
Hysteresis VIN voltage
3.6
OVER TEMPERATURE PROTECTION
TOTP
OTP trip threshold(1)
OTP hysteresis(1)
Shutdown temperature
Hysteresis
150
20
°C
°C
TOTPHSY
(1) Not production tested
6
版权 © 2019, Texas Instruments Incorporated
TPS56C230
www.ti.com.cn
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
6.6 Typical Characteristics
480
460
440
420
400
380
360
3
2.8
2.6
2.4
2.2
2
1.8
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D001
D002
VEN = 5 V
VEN = 0 V
图 1. Supply Current vs Junction Temperature
图 2. Shutdown Current vs Temperature
615
1.45
1.4
610
605
600
595
590
585
1.35
1.3
1.25
1.2
1.15
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D003
D004
图 3. Feedback Voltage vs Junction Temperature
图 4. Enable On Voltage vs Junction Temperature
1.24
1.2
32
28
24
20
16
12
8
1.16
1.12
1.08
1.04
1
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D005
D006
图 5. Enable Off Voltage vs Junction Temperature
图 6. High-Side RDS(on) vs Junction Temperature
版权 © 2019, Texas Instruments Incorporated
7
TPS56C230
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接下页)
12
128
127
126
125
124
123
122
10
8
6
4
2
0
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D007
D008
图 7. Low-Side RDS(on) vs Junction Temperature
图 8. OVP Threshold vs Junction Temperature
64
380
370
360
350
340
330
320
63
62
61
60
59
58
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D009
D010
图 9. UVP Threshold vs Junction Temperature
图 10. Discharge Resistor vs Junction Temperature
22
20
18
16
14
12
10
1.5
1.4
1.3
1.2
1.1
1
0.9
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D011
D012
图 11. Valley Current Limit vs Junction Temperature
图 12. Soft-Start Time vs Junction Temperature
8
版权 © 2019, Texas Instruments Incorporated
TPS56C230
www.ti.com.cn
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
Typical Characteristics (接下页)
100
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
20
10
0
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
0.01
0.1
1
10 15
0.01
0.1
1
10 15
I-Load (A)
I-Load (A)
D013
D014
图 13. Efficiency vs Load Current, Eco-mode
图 14. Efficiency vs Load Current, FCCM
700
700
600
500
400
300
200
100
0
600
500
400
300
200
100
0
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
0
1
2
3
4
5
6
I-Load (A)
7
8
9
10 11 12
0
1
2
3
4
5
6
I-Load (A)
7
8
9
10 11 12
D017
D018
图 15. Switching Frequency vs Load Current, Eco-mode
图 16. Switching Frequency vs Load Current, FCCM
版权 © 2019, Texas Instruments Incorporated
9
TPS56C230
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS56C230 is high density synchronous buck converter which operates from 4.5-V to 18-V input voltage
(VIN), and the output voltage range is from 0.6 V to 5.5 V. It has 17-mΩ and 5.9-mΩ integrated MOSFETs that
enable high efficiency up to 12 A. The device employs D-CAP3 mode control that enables low external
component count, ease of design, optimization of the power design for cost, size and efficiency, and provides
fast transient response with no external compensation components and an accurate feedback voltage. The
control topology supports seamless transition between CCM mode at heavy load conditions and DCM operation
at light load conditions. Eco-mode allows the TPS56C230 to maintain high efficiency at light load and FCCM
mode keeps the output ripple small at light load. The TPS56C230 is able to adapt to both low equivalent series
resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.
7.2 Functional Block Diagram
PG high
threshold
PGOOD
+
+
UV threshold
OV threshold
+
UV
Delay
PG low
threshold
+
OV
VIN
FB
+
LDO
VCC
0.6 V
VREGOK
4.2 V /
3.7 V
+
+
PWM
+
+
Control Logic
BST
VIN
SS
Ripple injection
SW
ñ
ñ
ñ
ñ
ñ
ñ
ñ
On/Off time
Minimum On/Off
TON Extension
OVP/UVP/TSD
Eco-mode/FCCM
Soft-Start
SW
XCON
Internal SS
PGOOD
SS
PGND
One shot
+
OCL
ZC
EN threshold
+
+
+
EN
NOCL
+
THOK
150°C /20°C
AGND
Light load operation set
Discharge control
MODE
10
版权 © 2019, Texas Instruments Incorporated
TPS56C230
www.ti.com.cn
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
7.3 Feature Description
7.3.1 PWM Operation and D-CAP3™ Control
The main control loop of the buck is adaptive on-time pulse width modulation (PWM) controller that supports a
proprietary D-CAP3 mode control. The D-CAP3 mode control combines adaptive on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The TPS56C230 also
includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the converter output voltage, VOUT, and is
inversely proportional to the input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for D-CAP3 control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the TPS56C230 is a low-pass L-C circuit. This L-C filter has a double-pole frequency
described in 公式 1.
1
¦
=
P
2´ p´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the internal output set-point resistor divider network and the
internal gain of the TPS56C230. The low-frequency L-C double pole has a 180 degree drop in phase. At the
output filter frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal
ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB
per decade and increases the phase to 90 degree one decade above the zero frequency. The inductor and
capacitor selected for the output filter must be such that the double pole is placed close enough to the high-
frequency zero so that the phase boost provided by this high-frequency zero provides adequate phase margin for
the stability requirement. The crossover frequency of the overall system should usually be targeted to be less
than one-third of the switching frequency (FSW).
7.3.2 Soft Start
The TPS56C230 has an internal 1.2-ms soft-start time, and also an external SS pin is provided for setting longer
soft start time if needed. When the EN pin becomes high, the soft-start function begins ramping up the reference
voltage to the PWM comparator.
If the application needs a longer soft start time, it can be set by connecting a capacitor on SS pin. When the EN
pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in 公式 2:
%OO (J() × 84'( (8)
6 (IO) =
OO
:
;
Q#
+
OO
(2)
where
VREF is 0.6 V and ISS is 5 μA
•
7.3.3 Large Duty Operation
The TPS56C230 can support large duty operation by its internal TON extension function. When VIN/VOUT < 1.6,
and the VFB is lower than internal VREF, the TON will be extended to implement the large duty operation and also
improve the performance of the load transient performance.
7.3.4 Power Good
The Power Good (PGOOD) pin is an open-drain output. Once the VFB is between 90% and 110% of the target
output voltage, the PGOOD is de-asserted and floats after a 1-ms de-glitch time. A pullup resistor of 100 kΩ is
recommended to pull the voltage up to VCC. The PGOOD pin is pulled low when:
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Feature Description (接下页)
•
•
•
the FB pin voltage is lower than 85% or greater than 115% of the target output voltage
in an OVP, UVP, or thermal shutdown event
during the soft-start period.
7.3.5 Overcurrent Protection and Undervoltage Protection
The TPS56C230 has the overcurrent protection and undervoltage protection. The output overcurrent limit (OCL)
is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the
OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch
current. To improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. When the load current is higher
than the overcurrent threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited, the output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, the output will shut off after a wait time of 256us and then re-start after the hiccup time (typically
10.5*Tss). When the over current condition is removed, the output voltage is recovered.
7.3.6 Overvoltage Protection
The TPS56C230 has the overvoltage protection feature and have the same implementation. When the output
voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high, the output will
be discharged after a wait time of 120 µs. When the over voltage condition is removed, the output voltage will be
recovered.
7.3.7 Out-of-Bounds Operation
The TPS56C230 has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much
lower overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault,
OOB protection operates as an early protection mechanism. During the OOB operation, the device operates in
force PWM mode only by turning on the low-side FET. Turning on the low-side FET beyond the zero inductor
current quickly discharges the output capacitor thus causing the output voltage to fall quickly towards the
setpoint. During the operation, the cycle-by-cycle negative current limit is also activated to ensure the safe
operation of the internal FETs.
7.3.8 UVLO Protection
The undervoltage lockout (UVLO) protection monitors the VCC pin voltage to protect the internal circuitry from
low input voltages. When the voltage is lower than UVLO threshold voltage, the device shuts off and outputs are
discharged to prevent mis-operation of the device. The converter begins operation again when the input voltage
exceeds the threshold by a hysteresis of 500 mV (typical). This is a non-latch protection.
7.3.9 Output Voltage Discharge
The TPS56C230 has the discharge function by using internal MOSFET about 350Ω, which is connected to the
output terminal SW. The discharge is slow due to the lower current capability of the MOSFET.
7.3.10 Thermal Shutdown
The TPS56C230 monitors the internal die temperature. If the temperature exceeds the threshold value (typically
150°C), the device shuts off and the output will be discharged. This is a non-latch protection, the device restarts
switching when the temperature goes below the thermal shutdown threshold.
12
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7.4 Device Functional Modes
7.4.1 Light Load Operation
TPS56C230 has a MODE pin that can setup two different states of operation for light load operation. The light
load running includes Eco-mode and FCCM mode.
7.4.2 Eco-mode™ Control
The Eco-mode control schemes to maintain high light load efficiency. As the output current decreases from
heavy load conditions, the inductor current is also reduced and eventually comes to a point where the rippled
valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction
modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load current
further decreases, the converter runs into discontinuous conduction mode. The on-time is kept almost the same
as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with
smaller load current to the level of the reference voltage. This makes the switching frequency lower, proportional
to the load current, and keeps the light load efficiency high. The light load current where the transition to Eco-
mode operation happens ( IOUT(LL) ) can be calculated from 公式 3.
(V -VOUT ) × VOUT
1
IN
IOUT(LL)
=
×
2 × LOUT × FSW
V
IN
(3)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-to-
peak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). It is
also important to select the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.4.3 Force CCM
Force CCM(FCCM) mode keeps the converter to operate in continuous conduction mode during light-load
conditions and allows the inductor current to become negative. During FCCM mode, the switching frequency
(FSW) is maintained at an almost constant value over the full load range, which is suitable for applications
requiring tight control of the switching frequency and output voltage ripple at the cost of lower efficiency under
light load.
7.4.4 Mode Selection
The device reads the voltage on the MODE pin during start-up and latches onto one of the MODE options listed
below in 表 1 . The voltage on the MODE pin recommended to be set by connecting this pin to the center tap of
a resistor divider connected between VCC and AGND. A guideline for the top resistor (RM_H) and the bottom
resistor (RM_L) as 1% resistors is shown in 表 1. It is recommended to choose the resistor to set the voltage at
around 5%*VCC for Eco-mode or 15%*VCC for FCCM. It is important that the voltage for the MODE pin is
derived from the VCC rail only since internally this voltage is referenced to detect the MODE option, and not to
leave the mode pin floating. The MODE pin setting can be reset only by a VIN power cycling or EN toggle.
表 1. MODE Pin Resistor Settings
Recommended Resistor
Voltage on MODE
LIGHT LOAD OPERATION
RM_H(kΩ)
330
RM_L (kΩ)
(0~10%)*VCC
15
33
Eco-mode
FCCM
(10%~20%)*VCC
180
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图 17 below shows the typical start-up sequence of the device once the enable signal crosses the EN turn on
threshold. After the voltage on VCC crosses the rising UVLO threshold it takes about 500us to read the first
mode setting and approximately 100us from there to finish the last mode setting. The output voltage starts
ramping after the mode reading is done.
EN threshold
1.3V
EN
VCC UVLO
4.2V
VCC
MODE2
MODE1
MODE
500us
tss
100us
VOUT
1ms
1.5*tss
PGOOD
图 17. Power-Up Sequence
7.4.5 Standby Operation
The TPS56C230 can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 2 µA when in standby condition. EN pin is pulled low internally, when floating, the part is disabled by
default.
14
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TPS56C230
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ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
8 Application and Implementation
注
Information in the following application sections are not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The schematic of 图 18 shows a typical application for TPS56C230 with 1.2-V output. This design converts an
input voltage range of 4.5 V to 18 V down to 1.2 V with a maximum output current of 12 A.
8.2 Typical Application
C1
U1
VCC
C2
0.1uF
17
1
VCC
L1
1uF
BST
VIN = 4.5 - 18V
VIN
VOUT = 1.2V/12A
VOUT
GND
2
3
4
5
6
19
20
SW
VIN
VIN
VIN
VIN
SW
SW
SW
680nH
C3
C4
C5
C6
47uF
C7
47uF
C8
47uF
C9
47uF
R1
14
22uF
22uF
0.1uF
FB
C10
18nF
10.0k
11
12
15
9
10
16
SS
NC
NC
GND
EN
EN
GND
GND
13
7
8
18
21
R2
10.0k
AGND
PGND
PGND
PGND
PGND
MODE
MODE
PGOOD
R3
VCC
100k
R4
330k
TPS56C230RJER
GND
R5
GND
15k
GND
图 18. 1.2-V, 12-A Reference Design
8.2.1 Design Requirements
表 2 lists the design parameters for this example.
表 2. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
1.2
12
MAX
UNIT
V
VOUT
IOUT
Output voltage
Output current
A
ΔVOUT
VIN
Transient response
Input voltage
1.2A - 10.8A load step, 2.5A/us
12A load
±5% x VOUT
12
4.5
18
V
VOUT(ripple)
FSW
Output voltage ripple
Switching frequency
Light load operating mode
Ambient temperature
2% x VOUT
500
kHz
°C
Eco-mode
25
TA
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS56C230 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor the user can change the output voltage above 0.6 V. See 公式 4
4722'4
4.19'4
8
176
= 0.6 × (1 +
)
(4)
8.2.2.3 MODE Selection
The light load running mode (Eco-mode or FCCM ) are set by a voltage divider from VCC to GND connected to
the MODE pin. See 表 1 for possible MODE pin configurations. For this design example ,the switching frequency
is about 500kHz, the light load running mode is Eco-mode and the output current is 12 A.
8.2.2.4 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See 表 3 for recommended
inductor values.
The RMS and peak currents through the inductor can be calculated using 公式 5 and 公式 6. It is important that
the inductor is rated to handle these currents.
æ
2 ö
÷
÷
÷
ø
æ
ç
ö
÷
VOUT × V
- VOUT
(
× LOUT × FSW
IN(max)
)
1
IN(max)
ç 2
I
IL(rms)=
+
×
OUT
ç
ç
è
÷
ø
12
V
ç
è
(5)
(6)
IOUT(ripple)
I
= IOUT
+
L(peak)
During transient and short-circuit conditions, the inductor current can increase up to the current limit of the
device, so it is safe to choose an inductor with a saturation current higher than the peak current under current
limit condition.
8.2.2.5 Output Capacitor Selection
After selecting the inductor, the output capacitor needs to be optimized. In D-CAP3, the regulator reacts within
one cycle to the change in the duty cycle, so the good transient performance can be achieved without large
amounts of output capacitance. The recommended output capacitance range is given in 表 3. Ceramic capacitors
have very low ESR, otherwise the maximum ESR of the capacitor should be less than VOUT(ripple)/IOUT(ripple)
.
表 3. Recommended Component Values
RUPPER
(kΩ)
VOUT (V)
RLOWER (kΩ)
Fsw (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
CFF (PF)
0.6
1.2
2.5
3.3
5.0
10
10
20
20
15
0
500
500
500
500
500
0.47
0.68
1.2
66
66
66
66
66
330
330
330
330
330
-
-
10
63
90
1.5
22-110
22-110
110
1.8
16
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TPS56C230
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ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
8.2.2.6 Input Capacitor Selection
The TPS56C230 requires input decoupling capacitors on power supply input VIN, and the bulk capacitors are
needed depending on the application. The minimum input capacitance required is given in 公式 7.
IOUT×VOUT
CIN(min)
=
V
INripple×V ×FSW
IN
(7)
TI recommends using a high-quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin
VIN. The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor
must also have a ripple current rating greater than the maximum input current ripple of the application. The input
ripple current is calculated by 公式 8:
VIN(min)-VOUT
(
)
VOUT
ICIN(rms) = IOUT ×
×
VIN(min)
VIN(min)
(8)
A 1-µF ceramic capacitor is needed for the decoupling capacitor on VCC pin.
8.2.3 Application Curves
图 19 through 图 34 apply to the circuit of 图 18. VIN = 12 V. TA = 25°C unless otherwise specified.
100
90
80
70
60
50
40
30
20
10
0
1
0.6
0.2
-0.2
-0.6
-1
VIN=4.5V, VOUT=1.2V
VIN=7.4V, VOUT=1.2V
VIN=12V, VOUT=1.2V
VIN=18V, VOUT=1.2V
VIN=4.5V, VOUT=1.2V
VIN=7.4V, VOUT=1.2V
VIN=12V, VOUT=1.2V
VIN=18V, VOUT=1.2V
0.01
0.1
1
10 15
0.001
0.01
0.1
I-Load (A)
1
1015
I-Load (A)
D000
D032
图 19. Efficiency Curve
图 20. Load Regulation
800
700
600
500
400
300
200
700
600
500
400
300
200
100
0
VIN=4.5V, VOUT=1.2V
VIN=7.4V, VOUT=1.2V
VIN=12V, VOUT=1.2V
VIN=18V, VOUT=1.2V
4
6
8
10
VIN (V)
12
14
16
18
0
1
2
3
4
5
6
I-Load (A)
7
8
9
10 11 12
D033
D034
IOUT = 12 A
图 21. Switching Frequency vs Input Voltage
图 22. Switching Frequency vs Output Load
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www.ti.com.cn
1
0.6
0.2
-0.2
-0.6
-1
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
4
6
8
10
12
14
16
18
4
6
8
10
12
14
16
18
VIN (V)
VIN (V)
D035
D036
IOUT=0.1A
IOUT=12A
图 23. Line Regulation
图 24. Line Regulation
EN=5V/div
EN=5V/div
Vout=1V/div
IL=5A/div
Vout=1V/div
IL=5A/div
800us/div
800us/div
IOUT = 6A
IOUT = 6A
图 25. Start-Up Through EN
图 26. Shut-down Through EN
Vin=10V/div
Vout=1V/div
Vin=10V/div
Vout=1V/div
IL=5A/div
IL=5A/div
800us/div
800us/div
IOUT = 6 A
IOUT = 6 A
图 27. Start Up Relative to VIN Rising
图 28. Shut Down Relative to VIN Falling
18
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TPS56C230
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Vout=20mV/div (AC coupled)
Vout=20mV/div (AC coupled)
SW=10V/div
SW=10V/div
20us/div
2us/div
IOUT = 0.1 A
IOUT = 12 A
图 29. Output Voltage Ripple
图 30. Output Voltage Ripple
Vout=100mV/div (AC coupled)
Vout=100mV/div (AC coupled)
Iout=10A/div
Iout=10A/div
200us/div
Slew Rate=2.5A/us
200us/div
Slew Rate=2.5A/us
1.2 A to 10.8 A
0 A to 12 A
图 31. Transient Response
图 32. Transient Response
Vout=1V/div
Vout=1V/div
SW=10V/div
IL=10A/div
SW=10V/div
IL=10A/div
100us/div
10ms/div
图 33. Normal Operation to Output Hard Short
图 34. Output Hard Short Hiccup Protection
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9 Power Supply Recommendations
The TPS56C230 is intended to be powered by a well regulated DC voltage. The input voltage range is 4.5 V to
18 V. TPS56C230 is a buck converter. The input supply voltage must be greater than the desired output voltage
for proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS56C230 circuit, some additional input bulk capacitance is recommended.
Typical values are 100 μF to 470 μF.
20
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TPS56C230
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ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
10 Layout
10.1 Layout Guidelines
•
Recommend a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 2.75-
inch, two-layer PCB with 2-oz copper used as example.
•
•
Place the decoupling capacitors right across VIN and VCC as close as possible.
Place output inductors and capacitors with IC at the same layer, SW routing should be as short as possible to
minimize EMI, and should be a width plane to carry big current, enough vias should be added to the GND
connection of output capacitors and also as close to the output pin as possible.
•
•
Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace
is recommended to reduce line parasitic inductance.
Feedback could be 20mil and must be routed away from the switching node, BST node or other high
efficiency signal.
•
•
VIN trace must be wide to reduce the trace impedance and provide enough current capability.
Place multiple vias under the device near VIN and GND and near input capacitors to reduce parasitic
inductance and improve thermal performance
10.2 Layout Example
图 35 shows the recommended top-side layout. Component reference designators are the same as the circuit
shown in 图 18.
Trace on the top layer
Trace on the bottom layer
C
VIN
C
R
C
Additional Vias to
the GND plane
SW
SW
SW
Trace on the bottom layer
SW
PGND
PGND
PGND
GND
VCC
PGOOD
R
Vias to the GND plane
L
PGND
NC
NC
VOUT
R
R
Additional Vias to
the GND plane
R
R
Additional Vias to
the GND plane
C
C
0Ω
AGND
PGND
Additional Vias to
the GND plane
图 35. PCB Layout Recommendation Diagram
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11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 开发支持
11.1.2.1 使用 WEBENCH® 工具创建定制设计
单击此处，使用 TPS56C230 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 商标
D-CAP3, Eco-mode, HotRod, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
22
版权 © 2019, Texas Instruments Incorporated
TPS56C230
www.ti.com.cn
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
23
TPS56C230
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
www.ti.com.cn
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
RJE0020B
PLASTIC QUAD FLATPACK- NO LEAD
3.1
2.9
A
B
(45°X0.08) TYP
(0.25)
DETAIL A
CHAMFERS ARE OPTIONAL
TYPICAL
3.1
2.9
PIN 1 INDEX AREA
0.5
0.3
0.25
0.15
DETAIL B
OPTIONAL PIN 1
1 MAX
C
SEATING PLANE
0.08
0.05
0.00
C
2X 1.8
PKG
(0.1) TYP
SEE TERMINAL
DETAIL A
10
6
16X 0.45
5
11
(0.007)
PKG
2X
1.8
0.975 0.1
21
0.25
0.15
20X
0.1
C B A
1
15
0.05
C
16
20
(0.123)
PIN 1 ID
DETAIL B
0.5
0.3
20X
0.926 0.1
4224338 / B 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
24
版权 © 2019, Texas Instruments Incorporated
TPS56C230
www.ti.com.cn
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0020B
(0.926)
(0.123)
20
16
20X (0.6)
20X (0.2)
1
15
(0.007)
16X (0.45)
21
PKG
(2.8)
(0.975)
11
5
(R0.05) TYP
6
10
PKG
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224338 / B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271)
.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
版权 © 2019, Texas Instruments Incorporated
25
TPS56C230
ZHCSJH9A –AUGUST 2019–REVISED AUGUST 2019
www.ti.com.cn
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
RJE0020B
PLASTIC QUAD FLATPACK- NO LEAD
(0.926)
(0.123)
20
16
20X (0.6)
20X (0.2)
1
15
(0.007)
16X (0.45)
PKG
21
(2.8)
(0.975)
5
11
(R0.05) TYP
10
6
PKG
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE: 20X
4224338 / B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
26
版权 © 2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS56C230RJER
XTPS56C230RJET
ACTIVE
VQFN-HR
RJE
RJE
20
20
3000 RoHS & Green Call TI | SN | NIPDAU Level-2-260C-1 YEAR
TBD Call TI Call TI
-40 to 125
56C230
Samples
OBSOLETE VQFN-HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS56C230RJER
TPS56C230RJER
VQFN-
HR
RJE
RJE
20
20
3000
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
VQFN-
HR
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS56C230RJER
TPS56C230RJER
VQFN-HR
VQFN-HR
RJE
RJE
20
20
3000
3000
346.0
367.0
346.0
367.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RJE 20
3 x 3, 0.45 mm pitch
VQFN-HR - 1 mm max height
QUAD FLATPACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224683/A
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0020B
3.1
2.9
A
B
(45°X0.08) TYP
(0.25)
DETAIL A
CHAMFERS ARE OPTIONAL
TYPICAL
3.1
2.9
PIN 1 INDEX AREA
0.5
0.3
0.25
0.15
DETAIL B
OPTIONAL PIN 1
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.8
PKG
(0.1) TYP
SEE TERMINAL
DETAIL A
10
6
16X 0.45
11
5
(0.007)
PKG
2X
1.8
0.975±0.1
21
0.25
0.15
20X
0.1
C B A
1
15
0.05
C
16
20
(0.123)
PIN 1 ID
DETAIL B
0.5
0.3
20X
0.926±0.1
4224338 / B 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0020B
(0.926)
(0.123)
20
16
20X (0.6)
20X (0.2)
1
15
(0.007)
16X (0.45)
21
PKG
(2.8)
(0.975)
11
5
(R0.05) TYP
6
10
PKG
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224338 / B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0020B
(0.926)
(0.123)
20
16
20X (0.6)
20X (0.2)
1
15
(0.007)
(0.975)
16X (0.45)
21
PKG
(2.8)
5
11
(R0.05) TYP
10
6
PKG
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE: 20X
4224338 / B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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