XTR108EA/2K5 [TI]
具有“智能”可编程信号调节的 4-20mA 两线制发送器 | DBQ | 24 | -40 to 85;
| 型号： | XTR108EA/2K5 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有“智能”可编程信号调节的 4-20mA 两线制发送器 | DBQ | 24 | -40 to 85 放大器 光电二极管 |
| 文件： | 总33页 (文件大小：661K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XTR108
X
T
R
1
0
8
SBOS187C – OCTOBER 2001 – REVISED JULY 2005
4-20mA, TWO-WIRE TRANSMITTER
“Smart” Programmable with Signal Conditioning
FEATURES
DESCRIPTION
● COMPLETE TRANSMITTER + RTD
The XTR108 is a “smart,” programmable, 4-20mA, two-wire
transmitter designed for temperature and bridge sensors.
Zero, span, and linearization errors in the analog signal
path can be calibrated via a standard digital serial interface,
eliminating manual trimming. Non-volatile external EEPROM
stores calibration settings.
LINEARIZATION
● TWO-WIRE, 4-20mA OUTPUT
● VOLTAGE OUTPUT (0.5V to 4.5V)
● ELIMINATES POTENTIOMETERS AND
TRIMMING
The all-analog signal path contains an input multiplexer,
autozeroed programmable-gain instrumentation amplifier, dual
programmable current sources, linearization circuit, voltage
reference, sub-regulator, internal oscillator, control logic, and
an output current amplifier. Programmable level shifting
compensates for sensor DC offsets. Selectable
up- and down-scale output indicates out-of-range and burn-
out per NAMUR NE43. Automatic reset is initiated when
supply is lost.
● DIGITALLY CALIBRATED
● 5V SUB-REGULATOR OUTPUT
● SERIAL SPI BUS INTERFACE
● SSOP-24 PACKAGE
APPLICATIONS
● REMOTE RTD TRANSMITTERS
● PRESSURE BRIDGE TRANSMITTERS
● STRAIN GAGE TRANSMITTERS
● SCADA REMOTE DATA ACQUISITION
● WEIGHING SYSTEMS
Current sources, steered through the multiplexer, can be
used to directly excite RTD temperature sensors, pressure
bridges, or other transducers. An uncommitted op amp can
be used to convert current into a voltage. The XTR108 is
specified for –40°C to +85°C.
● INDUSTRIAL PROCESS CONTROL
EEPROM
SPI and
Control Circuits
Excitation
VPS
V/I-0
V/I-1
V/I-2
Linearization
4-20mA
IO
PGA
V/I
V/I-3
V/I-4
V/I-5
RLOAD
XTR108
R1 R2 R3 R4 R5
IRet
RTD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2005, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
mentsrecommendsthatallintegratedcircuitsbehandledwith
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Loop Supply Voltage, VPS ............................ Dependent on External FET
XTR Supply Voltage, External VS (Referenced to IRET Pin) ............ +5.5V
Input Voltage to Multiplexer (Referenced to IRET Pin) ................ 0V to VS
Output Current Limit ................................................................ Continuous
Storage Temperature Range .........................................–55°C to +125°C
Junction Temperature .................................................................... +165°C
Lead Temperature (soldering, 10s)............................................... +300°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
XTR108EA
SSOP-24
DBQ
–40°C to +85°C
XTR108EA
XTR108EA
Rails
"
"
"
"
"
XTR108EA/2K5
Tape and Reel, 2500
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TA = +25°C, VPS = 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to IRET pin.
XTR108EA
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN TO IOUT TRANSFER FUNCTION
Output
IO = VIN (Span) + 4mA
Specified Range
4
20
mA
mA
mA
mA
mA
Over-Scale Limit Resolution
Fault Over-Scale Level(1)
Under-Scale Limit Resolution
Fault Under-Scale Level(1)
Output for Zero Input
Digital Select: 21-28.5mA
Above Over-Scale Selected
Digital Select: 2.2-3.6mA
Below Under-Scale Selected
0.5
+1.0
0.2
–0.4
Zero Error, Unadjusted
vs Temperature
VIN = 0V
±50
±0.2
0.02
±1
1.8
±4
µA
µA/°C
µA/V
µA/V
µA/Step
mA
±1.5
vs Loop-Supply Voltage, VLOOP
vs Common-Mode Voltage
Adjustment Resolution, Zero Input
Adjustment Range, Zero Input
Span(2)
VLOOP = 7.5V to 24V
VCM = 0.2V to 3.5V
Span = IO/VIN
Initial, Unadjusted
±1
40
0.05
%
ppm/°C
%
Drift (vs Temperature)
Span Adjustment Resolution
Span Adjustment Range
PGA + Output Amplifier(3)
Nonlinearity, Ideal Input
RVI = 6.34kΩ
Full-Scale VIN = 50mV
49.3
3150
mA/V
%
0.01
PGA
Autozeroing Internal Frequency
PGA Offset Voltage (RTI)(4)
vs Temperature
vs Supply Voltage, VS
vs Common-Mode Voltage
Common-Mode Input Range
Input Bias Current
6.5
±10
±0.02
±0.5
105
kHz
µV
µV/°C
µV/V
dB
VCM = 1V
±50
VS = 4.5V to 5.5V
VCM = 0.2V to 3.5V
0.2
VS – 1.5
V
pA
50
vs Temperature
Input Offset Current
vs Temperature
Doubles/10°C
10
Doubles/10°C
pA
pA
pA
XTR108
2
SBOS187C
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TA = +25°C, VPS = 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to IRET pin.
XTR108EA
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PGA (Cont.)
Input Impedance: Differential
Input Impedance: Common-Mode
Voltage Noise, 0.1Hz to 10Hz
PGA Gain
30 || 6
50 || 20
6
GΩ || pF
GΩ || pF
µVp-p
Gain Range Steps
Initial Error
6.25, 12.5, 25, 50, 100, 200, 400
Gain = 6.25, 12.5, 25, 50
G = 100, 200
6.25
0.2
400
±2.5
±3
V/V
%
%
%
ppm/°C
V
±0.5
±0.5
±0.8
±30
G = 400
±3.5
vs Temperature
Output Voltage Range(5)
Typical Operating Range
Capacitive Drive
RLOAD = 6.34kΩ to IRET
for 4-20mA XTR Output
4.5
0.5 to 2.5
200
V
pF
Short-Circuit Current
+6/–9
mA
ZERO OFFSET DACS
Zero-Code Output Level
RTO(6) of Current Amplifier
RTO(6) of PGA
VCM = 1V, VIN = 0V
RV/I = 6.34kΩ
4.116
522
mA
mV
Coarse DAC, 256 Steps
Adjustment Range
RTO(6) of Current Amplifier
RTO(6) of PGA
7 Bits + Sign
Relative to Zero-Code Level
–3.77 to +3.77
–470 to +470
mA
mV
Step Size
RTO(6) of Current Amplifier
RTO(6) of PGA
0.029
3.7
mA
mV
Linearity
±0.5
LSB
Fine DAC, 256 Steps
Adjustment Range
RTO(6) of Current Amplifier
RTO(6) of PGA
Relative to Zero-Code Level
7 Bits + Sign
–236 to +236
–29.4 to +29.4
µA
mV
Step Size
RTO(6) of Current Amplifier
RTO(6) of PGA
Linearity
Noise, RTO(6)
0.0018
0.23
±1
mA
mV
LSB
µAp-p
f = 0.1Hz to 10Hz
1.1
CURRENT AMPLIFIER
Current Gain
Current Gain Drift
49
50
10
51
A/A
ppm/°C
CURRENT SOURCES, IREF1 AND IREF2
Zero-Code Output Level, Each
Coarse DAC, 256 Steps
Adjustment Range(7)
Step Size
RSET = 12.1kΩ
480
493
510
µA
7 Bits + Sign
–195 to +195
1.54
µA
µA
Fine DAC, 256 Steps
Adjustment Range(7)
Step Size
7 Bits + Sign
–12.2 to +12.2
96
µA
nA
Linearity
Coarse
Fine
±0.2
±0.5
LSB
LSB
vs Temperature
Matching
±35
±0.2
ppm/°C
%
vs Temperature
±10
VS – 1.5
100
ppm/°C
V
MΩ
Compliance Voltage, Positive(5)
Output Impedance
Current Noise
VS – 2
f = 0.1Hz to 10Hz
0.015
µAp-p
LINEARIZATION DAC
Linearization Range, 256 Steps
Max Linearization Coefficient
Step Size
8 Bits
0.99
3.9
∆IREF/∆VIN, RLIN = 15.8kΩ
µA/mV
nA/mV
SUB-REGULATOR, VS
Voltage
vs Temperature
Supply Voltage for XTR
4.8
5.1
±50
±0.03
5.4
V
ppm/°C
mV/V
vs Loop-Supply Voltage
VLOOP = 7.5V to 24V
XTR108
SBOS187C
3
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TA = +25°C, VPS = 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to IRET pin.
XTR108EA
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OVER- AND UNDER-SCALE LIMITING
Over-Scale DAC: 16 Steps
Adjustment Range
RTO(6) of Current Amplifier
RTO(6) of PGA
4
Bits
RVI = 6.34kΩ
20.7 to 28.1
2.625 to 3.563
mA
V
Step Size
RTO(6) of Current Amplifier
RTO(6) of PGA
Accuracy
Under-Scale DAC: 8 Steps
Adjustment Range
RTO(6) of Current Amplifier
RTO(6) of PGA
0.49
62.5
±10
3
mA
mV
%
Bits
RVI = 6.34kΩ
2.17 to 3.55
275 to 450
mA
mV
Step Size
RTO(6) of Current Amplifier
RTO(6) of PGA
Accuracy
0.195
25
±5
mA
mV
%
VOLTAGE REFERENCE, VREF
Internal Bandgap
1.193
V
vs Temperature
±5
±50
ppm/°C
UNCOMMITTED OP AMP
Input
Offset Voltage
vs Temperature
vs Common-Mode Voltage
Open-Loop Gain
VCM = 2V
±2
±3
90
mV
µV/°C
dB
110
dB
Common-Mode Input Range
Output Voltage Range
0 to 3.5
V
V
RL = 10kΩ to VS/2
0.2
VS – 0.2
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIL
VIH
VOL
CMOS
0
3.5
0.8
VS
0.4
V
V
V
V
IOL = 300µA
IOH = –300µA
VOH
VS – 1
Input Current
IIH (CS1)
IIL (CS1)
3.5 < VIN < VS
0 < VIN < 0.8
0 < VIN < VS
–200
–20
–20
–120
–6
–6
10
10
10
µA
µA
µA
I
IH, IIL (SCLK, DIO)
INTERNAL OSCILLATOR
Frequency, fOSC
210
kHz
TEMPERATURE RANGE
Specification
Operating
–40
–55
+85
+125
°C
°C
θJA, Junction to Ambient
100
0.5
°C/W
LOOP SUPPLY
Voltage Range
Quiescent Current
with Supertex DN2540
RSET Open, LINReg = 0, No Sensor Current(8)(9)
7.5
V
mA
NOTES: (1) Over-scale and under-scale complies with NAMUR NE43 recommendation. (2) Span adjustment is determined by PGA gain and sensor
excitation. (3) Span can be digitally adjusted in three ways: PGA gain, current reference Coarse, and current reference Fine. (4) RTI = Referred to Input.
(5) Current source output voltage measured with respect to IRET. (6) RTO = Referred to Output. (7) Excitation DAC range sufficient to adjust span fully
between PGA gain steps. (8) Output current into external circuitry is limited by an external MOS power FET. (9) Measured with over- and under-scale limits
disabled.
XTR108
4
SBOS187C
www.ti.com
PIN CONFIGURATION
Top View
SSOP
V/I-0
V/I-1
V/I-2
V/I-3
V/I-4
V/I-5
CFILTER
RLIN
1
2
3
4
5
6
7
8
9
24 OPA +IN
23 OPA –IN
22 OPA OUT
21 REFOUT
20 REFIN
19 RSET
XTR108
18 CS1
17 SCLK
16 SDIO
15 CS2
VO
IIN 10
IO 11
14 VGATE
13 VS
IRET 12
PIN ASSIGNMENTS
PIN
NAME
FUNCTION
V/I-0
MUX Input Channel 0 and/or IREF Out
MUX Input Channel 1 and/or IREF Out
MUX Input Channel 2 and/or IREF Out
MUX Input Channel 3 and/or IREF Out
MUX Input Channel 4 and/or IREF Out
MUX Input Channel 5 and/or IREF Out
Filter Capacitor
MUX Input to PGA and/or IREF to Sensor
MUX Input to PGA and/or IREF to Sensor
MUX Input to PGA and/or IREF to Sensor
MUX Input to PGA and/or IREF to Sensor
MUX Input to PGA and/or IREF to Sensor
MUX Input to PGA and/or IREF to Sensor
Filter to Reduce Chopper Noise in Autozeroing PGA
Linearization Range Adjustment Resistor
PGA Amplified Output of Differential Sensor Input
Input to Output Current Amplifier
V/I-1
V/I-2
V/I-3
V/I-4
V/I-5
CFILTER
RLIN
Linearization
VO
PGA Output
IIN
Current Input
IO
Output Current
4-20mA Current for Output Loop
IRET
Return Current
Return for All External Circuitry Current
Supply Voltage for XTR and External Circuitry, If Used
Gate Voltage for External MOSFET Transistor
VS
Voltage Regulator
VGATE
CS2
Gate Voltage
Chip Select 2
Select for XTR Serial Port to External EEPROM (Output from XTR Only)
Serial Data Input or Output
SDIO
SCLK
CS1
Serial Data Input/Output
Serial Clock
Serial Clock
Chip Select 1
Select for External µC Serial Port (Input to XTR Only)
Sets Current Reference
RSET
Resistor for Reference
Voltage Reference Input
Voltage Reference Output
Uncommitted Op Amp Output
Uncommitted Op Amp Negative Input
Uncommitted Op Amp Positive Input
REFIN
REFOUT
OPA OUT
OPA –IN
OPA +IN
Voltage Reference Input to XTR
Voltage Reference Output from Internal Bandgap
Uncommitted Op Amp Output
Uncommitted Op Amp Negative Input
Uncommitted Op Amp Positive Input
XTR108
SBOS187C
5
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, V+ = 24V, unless otherwise noted. RVI = 6.34kΩ.
TRANSCONDUCTANCE vs FREQUENCY
70
COMMON-MODE REJECTION vs FREQUENCY
90
80
70
60
50
40
30
20
10
G = 400
60
50
40
G = 200
G = 6.25
G = 50
30
G = 100
20
10
0
–10
–20
–30
G = 6.25
G = 400
100
10k
100k 200k
10
100
1k
10k
100k
1k
Frequency (Hz)
Frequency (Hz)
IZERO VLOOP REJECTION RATIO vs FREQUENCY
IREF VLOOP REJECTION RATIO vs FREQUENCY
100
90
80
70
60
50
40
30
20
120
110
100
90
80
70
60
10
100
1k
10k
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
IREF vs TEMPERATURE
IOUT DRIFT AVERAGE
492
490
488
486
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
–75
–50
–25
0
25
50
75
100
125
Temperature (°C)
IOUT Drift (µA/°C)
XTR108
6
SBOS187C
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, V+ = 24V, unless otherwise noted. RVI = 6.34kΩ.
LARGE INPUT STEP RESPONSE
LARGE INPUT STEP RESPONSE
20mA
20mA
4mA
4mA
CFILT = 0.01µF
PGA Gain = 6.25
CFILT = 0
PGA Gain = 6.25
500µs/div
250µs/div
SMALL INPUT STEP RESPONSE
SMALL INPUT STEP RESPONSE
20mA
20mA
4mA
4mA
PGA Gain = 200
CFILT = 0.01µF
PGA Gain = 200
CFILT = 0
500µs/div
250µs/div
IREF NOISE POWER
IZERO CURRENT NOISE POWER
10
1.0
0.1
100
10
1
1
10
100
1k
10k
1
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
XTR108
SBOS187C
7
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, V+ = 24V, unless otherwise noted. RVI = 6.34kΩ.
INPUT NOISE POWER DENSITY
1000
PGA PEAK-TO-PEAK NOISE (RTI)
BW: 0.1Hz to 10Hz
100
CFILT = 0.01
10
5s/div
1
10
100
1k
10k
Frequency (Hz)
OVERVIEW
The XTR108 is a 4-20mA current-loop transmitter that
allows the user to digitally adjust the gain, offset, and
linearity correction of the analog output to calibrate the
sensor. The digital data for adjustment are stored in an
external EEPROM device.
EE PROM
SDIO
SCLK
CS1
Isolation
Couplers
Calibration
System
The analog signal path is composed of a compound multi-
plexer (MUX), programmable gain instrumentation amplifier
(PGA), and an output current amplifier. Analog support func-
tions include digitally controlled current sources for sensor
excitation, PGA offset control, linearization, voltage refer-
ence, and voltage regulator.
Calib
GND
XTR108
IO
The digital interface communicates with external devices for
calibration and to store the resultant data in an SPI compat-
ible EEPROM. A complete system is shown in Figure 1. The
XTR108 serial interface is SPI compatible and only requires
four connections to the calibration controller: a serial clock
(SCLK), a serial data line (SDIO), a chip select line (CS1),
and a ground sense line. All logic signals to the XTR108
must be referenced to the potential of the ground sense line
(IRET pin on the XTR108).
RV
PS
IRET
TX
GND
RX
GND
FIGURE 1. Complete System Level Configuration with
Three Unique Ground Voltage Levels.
Within this entire system there may exist three different
“GND” voltage levels. In addition, the voltage difference
between the IRET and IO potential will depend on the output
current level. It is not certain that the “GND” potential of the
calibration system will be at the same potential of either the
IRET or IO potential, and therefore the isolation couplers are
shown in Figure 1. All voltages specified for the XTR108
are with reference to the IRET pin.
The XTR108 also needs to communicate with the external
EEPROM device independently from the calibration control-
ler to retrieve the calibration constants during normal opera-
tion. The XTR108 provides a second chip select function
(CS2) for the EEPROM device to facilitate this communica-
tion.
XTR108
8
SBOS187C
www.ti.com
If over-scale and under-scale limiting is disabled, the PGA
can be used with rail-to-rail voltage output, for example, in
applications that require a 0.5V to 4.5V voltage scale.
THEORY OF OPERATION
REFERENCE
The XTR108 has an on-board precision bandgap voltage
reference with output at pin 21 (REFOUT). The value of the
reference is factory-trimmed to 1.193V, with a typical tem-
perature drift of 5ppm/°C. Pins 21 (REFOUT) and 20 (REFIN)
must be connected together to use the internal reference.
The PGA uses advanced auto-zero circuit techniques to achieve
high DC precision, and reduce mismatches and errors within
the chip such as input offset, offset temperature drift, and low-
frequency noise (see the input noise typical characteristic).
The basic clock frequency of the auto-zero loop is about
6.5kHz. Due to the switching nature of the auto-zero circuit,
the output of the PGA can have a noticeable clock feed-
through ripple in higher gains. This noise can be reduced by
External circuitry, such as a voltage excited sensor or an
Analog-to-Digital Converter (ADC), can be connected to the
REFOUT pin. The unbuffered REFOUT is capable of sourcing
current but not sinking.
the addition of a 0.01µF capacitor between pin 7 (CFILTER
)
and the local ground, pin 12 (IRET). This creates a one-pole
low-pass filter with –3dB frequency at about 1.5kHz. If
wider bandwidth or faster settling time is needed, the CFILTER
can be reduced or eliminated at the expense of higher glitch
amplitude at the output. Please refer to the typical step
response traces for settling time comparisons.
If the application necessitates, an external reference can be
connected to the XTR108 REFIN pin, as long as the reference
does not exceed 1.4V. The REFIN pin has a high input
impedance with the input current not exceeding a few
nanoamps.
INPUT MULTIPLEXER
ZERO DACS
The XTR108 input multiplexer is a full 6 by (2+2) cross-
point switch. The current references and PGA inputs can be
independently connected to any of the six external pins,
including simultaneous connections to the same pin. This
allows a great flexibility in the sensor excitation and input
configuration. The input pins must not be driven below the
IRET potential or above VS.
Two output-referred, 8-bit Digital-to-Analog Converters
(DACs) (coarse and fine with a pedestal) set the zero level of
the PGA output. They allow setting a desired zero-scale
output level and compensate the initial offset at the PGA input
due to the sensor and resistor mismatches, sensor non-ideali-
ties, etc. Both coarse and fine DACs are bidirectional and
allow the output level to be set above or below a preset
pedestal.
See Figure 2 for an RTD sensor connected to pin VIN0 with
both IREF supplied and PGA VIN+ sensed at that pin. The
other five input pins are used for a bank of RZ resistors that
can be selected during the calibration process for a particular
measurement range.
Output signals of the DACs, IZ COARSE and IZ FINE, are
summed with the pedestal, IZ PROGRAM. Each of the DACs
has 8-bit resolution (256 steps) with 4-bit overlap between
the coarse and fine DACs. This means that one LSB of the
coarse DAC is equal to 16 fine LSBs, and the full-scale
range of the fine DAC is equal to 16 coarse LSBs. This
effectively produces 12-bit adjustment resolution.
PROGRAMMABLE GAIN
INSTRUMENTATION AMPLIFIER
The programmable gain instrumentation amplifier has seven
voltage-gain settings in binary steps from 6.25V/V to 400V/V.
The input common-mode range of the PGA is 0.2V to 3.5V
above the IRET potential.
This overlap allows the user to set pre-calculated values
before the calibration, using the coarse DAC only and adjust
the zero output level with the fine DAC during the calibra-
tion process see Table II for the equations for calculating the
value of the output when zero differential voltage is applied
at the PGA input. For the adjustment range, LSB sizes, and
linearity values of the Zero DACs, please refer to the
electrical characteristics table.
Normally, in the application for 4-20mA transmitters, the
PGA output voltage range should be set to VZERO = 0.5V and
VFS = 2.5V. Connecting a resistor (RVI = 6.34kΩ) between
pin 9 (VO) and pin 10 (IIN) converts this voltage to the signal
for the output amplifier that produces a 4-20mA scale
current output. In this mode, the PGA voltage gain converts
to an overall transconductance in the range of 50mA/V to
3200mA/V (approximately). Table I shows the gain to
transconductance relationship.
Note that a DAC can be set to a value that produces an
output below the under-scale level. In this case, the under-
scale limit will prevent the output from getting to the desired
value. The value of the minimum scale should not be set so
low that the PGA voltage output, VO, goes below its speci-
fied range of 0.2V from IRET
.
VOLTAGE GAIN
6.25 12.5 25
50 100 200 400
V/V
ADJUSTABLE OVER-SCALE AND
UNDER-SCALE LIMITING CIRCUIT
OUTPUT TRANSCONDUCTANCE 49 99 197 394 789 1577 3155
mA/V
The XTR108 incorporates circuitry to set adjustable limits at
the output in cases when the sensor signal goes above or
below its range. There are 16 levels for over-scale limit
adjustment (4-bit DAC) and 8 levels for the under-scale (3-bit
DAC).
FULL-SCALE DIFFERENTIAL VIN 320 160 80
40
20
10
5
mV
TABLE I. PGA Gain, Corresponding Loop Transductance
and Input Full-Scale Differential Voltage.
XTR108
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M u l t i p l e x e r
FIGURE 2. XTR108 Internal Block Diagram.
XTR108
10
SBOS187C
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VOLTAGE REFERRED TO VO PIN
WITH RESPECT TO IRET
CURRENT REFERRED TO IOUT PIN
IZERO = IZ PROGRAM + IZ COARSE + IZ FINE
175VREF
OVERALL
PROGRAM
VZERO = VZ PROGRAM + VZ COARSE + VZ FINE
3.5VREF
IZ PROGRAM
=
VZ PROGRAM
=
8RVI
8
5VREF N13
VREF N13
IZ COARSE
=
•
VZ COARSE
=
•
COARSE DAC
FINE DAC
8RVI
4
80
4
5VREF N12
VREF N12
IZ FINE
=
•
VZ FINE
=
•
8RVI
64
80
64
NOTE: N13 and N12 are assigned decimal values of registers 13 and 12, respectively.
TABLE II. Equations for Calculating Zero Output.
matched internal resistors determines a current gain of this
block. Note that the IOUT pin is always biased below the
substrate potential.
The circuit is designed for compliance with NAMUR NE43
recommendation for sensor interfaces. The limit levels are
listed in Tables VII and VIII. Because of the large step sizes,
units that use this feature should be checked if the value is
critical. The under-scale limit circuit will override the Zero
DAC level if it is set lower and there is not enough sensor
offset at the PGA input.
EXCITATION CURRENT DACS AND RSET RESISTOR
Two matched adjustable reference current sources are avail-
able for sensor excitation. The defining equations are given
in Table III. Both current sources are controlled simulta-
neously by the coarse and fine DACs with a pedestal.
It may be necessary to disable limiting if the XTR108 is used
in applications other than a 4-20mA transmitter, where the
PGA output is between 0.5V and 4.5V.
The external resistor RSET is used to convert the REF voltage
into the reference current for the sensor excitation DACs.
The total current output of the DACs is split, producing two
references: IREF1 and IREF2. Both of the current references
match very closely over the full adjustment range without
mismatched differential steps. Both current reference out-
puts must be within the compliance range, i.e.: one reference
cannot be floated since it will change the value of the other
current source.
SENSOR FAULT DETECTION CIRCUIT
To detect sensor burnout and/or short, a set of four compara-
tors is connected to the inputs of the PGA. If any of the
inputs are taken outside of the PGA’s common-mode range,
the corresponding comparator sets a sensor fault flag that
causes the PGA output to go either to the upper or lower
error limit. The state of the fault condition can be read in the
digital form from register 3. The direction of the analog
output is set according to the “Alarm Configuration Regis-
ter” (see Table X). The level of the output is produced as
follows: if the over-scale/under-scale limiting is enabled, the
error levels are: over-scale limit +2LSBs of the over-scale
DAC, about 1mA referred to IOUT or 0.125V referred to VO,
of under-scale limit –2LSBs of the under-scale DAC, about
0.4mA referred to IOUT or 0.05V referred to VO. If the over-
scale/under-scale limiting is disabled, the PGA output volt-
age will go to within 150mV of either positive or negative
supply (VS or IRET), depending on the alarm configuration
bit corresponding to the error condition.
The recommended value of RSET is 12.1kΩ for use with
100Ω RTD sensors. This generates IREF1, 2 = 492µA currents
when both coarse and fine DACs are set to zero. The value
of the RSET resistor can be increased if lower reference
currents are required, i.e.: for 1000Ω RTD or a bridge
sensor.
REFERENCE CURRENT
OVERALL
PROGRAM
IREF1, 2 = IREF PROGRAM + IREF COARSE + IREF FINE
5VREF
IREF PROGRAM
=
RSET
VREF N11
IREF COARSE
=
•
COARSE DAC
FINE DAC
RSET
64
OUTPUT CURRENT AMPLIFIER + RVI RESISTOR
VREF
N10
IREF FINE
=
•
RSET 1024
To produce the 4-20mA output, the XTR108 uses a current
amplifier with a fixed gain of 50A/A. The voltage from the
PGA is converted to current by the external resistor, RVI. Pin
IRET, the common potential of the circuit (substrate and local
ground), is connected to the output and inverting input of the
amplifier. This allows collecting all external and internal
supply currents, sensor return current, and leakage currents
from the different parts of the system and accounting for
them in the output current. The current from RVI flows into
the pin IIN that is connected to the noninverting input and
therefore, is at ground potential as well. The ratio of two
NOTE: N11 and N10 are the decimal values of registers 11 and 10,
respectively.
TABLE III. Equations for Calculating the Values of Each
Reference Current.
Similar to the Zero DACs, the outputs of the fine and coarse
DAC are summed together with the pedestal IREF PROGRAM
.
Each of the excitation DACs has 8-bit resolution (256 steps)
with 4-bit overlap between the coarse and the fine. This
XTR108
SBOS187C
11
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means that one LSB of the coarse DAC is equal to 16 fine
LSBs, and the full-scale range of the fine DAC is equal to 16
coarse LSBs. This effectively produces 12-bit adjustment
resolution. This allows the user to set pre-calculated values
before the calibration, using the coarse DAC only and adjust
the reference current output level with the fine DAC during
the calibration process.
n-channel depletion-mode MOS transistor and three capaci-
tors, see Figure 2.
A number of third-party suppliers make n-channel deple-
tion-mode MOSFETs. A list of devices tested by Texas
Instruments, Inc. is shown in Table IV with the capacitor
values recommended for those devices.
MANUFACTURER
MOSFET MODEL
CGATE VALUE
LINEARIZATION CIRCUIT AND RLIN RESISTOR
Supertex
DN2535, DN2540
DN3535, DN3525
220pF
1000pF
The XTR108 incorporates circuitry for correcting a second-
order sensor nonlinearity. A current proportional to the
voltage at the input of the PGA is added to the sensor
excitation. The RLIN resistor is used to convert this voltage
into current. By appropriately scaling this current using the
linearization DAC, parabolic sensor nonlinearity can be
improved by up to a 40:1 ratio, as shown in Figure 3. The
linearization coefficient (ratio of the reference current change
to the input voltage) is expressed in µA/mV as follows:
Siliconix
Infineon
ND2012, ND2020
BSP149
220pF
1000pF
TABLE IV. Recommended Gate Capacitor Values For Se-
lected MOSFETs.
The capacitors CLOOP (0.01µF), CREG (2.2µF), and CGATE
are required for the regulator loop stability and supply
bypass. They should be placed in close proximity to the
XTR108 on the PCB. An additional 1µF capacitor may be
used to bypass the supply of an EEPROM chip.
∆IREF
N14
GLIN
=
•
VIN 16 • RLIN
If a MOSFET other than those listed in Table IV is used, the
value of CGATE should be adjusted such that there is no
overshoot of VS during power-up and supply glitches. Any
VS overshoot above 7.5V may damage the XTR108 or
deteriorate its performance.
where N14 is the decimal value from register 14.
The recommended value of the resistor is 15.8kΩ, for use
with 100Ω RTD sensors. This value produces a full-scale
linearization coefficient of about 1mA/V. Please see the
section below on using the XTR108 with an RTD tempera-
ture sensor. If the sensor excitation is scaled down by
increasing the value of RSET, the value of RLIN should be
scaled proportionally.
LOOP VOLTAGE
The XTR108 transmitter minimum loop voltage can some-
what be effected by the choice of the external MOSFET. The
devices are tested to 7.5V compliance with Supertex DN2540;
choosing other MOSFETs can change this value slightly.
The maximum loop voltage is limited by the power dissipa-
tion on the MOSFET as well as its breakdown voltage.
Possible ambient temperatures and the power dissipation
should be taken into account when selecting the MOSFET
package. The external MOSFET can dissipate a consider-
able amount of power when running at high loop supply. For
example, if VLOOP = 24V and IOUT = 20mA, the DC power
dissipated by the MOSFET is:
5
4
3
Uncorrected
RTD Nonlinearity
2
Corrected
Nonlinearity
1
0
PMOSFET = IOUT (VLOOP – VS) = 380mΩ
For a SOT-89 package soldered on an FR5 board, this will
cause a 30°C rise in the temperature. The power dissipation
gets significantly higher when the circuit is driven into an
over-scale condition. Therefore, special attention should be
paid to removing the heat from the MOSFET, especially
with small-footprint packages such as SOT-89 and TO-92.
Please follow manufacturer’s recommendations about the
package thermal characteristics and board mounting.
–1
–200°C
+850°C
Process Temperature (°C)
FIGURE 3. Pt100 Nonlinearity Correction Using the XTR108.
SUB-REGULATOR WITH EXTERNAL MOSFET
UNCOMMITTED OP AMP
The XTR108 is manufactured using a low-voltage CMOS
process with maximum supply voltage limited to 5.5V. For
applications in a 4-20mA current loop, a special sub-regulator
circuit is incorporated in the device that requires an external
For added flexibility in various applications, the XTR108
has an on-chip uncommitted operational amplifier. The op
amp has rail-to-rail output range. The input range extends to
IRET potential.
XTR108
12
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The uncommitted amplifier can be used for a variety of
purposes, such as voltage sensor excitation, buffering the
REFOUT pin, four-wire RTD connection, or sensing the
bridge voltage for temperature compensation.
CONTROL REGISTERS
Table V shows the registers that control the analog functions
of the XTR108.
DESCRIPTION OF CONTROL REGISTERS
Address = 0: Control Register 1
POWER-GOOD/POWER-ON RESET
In case of a supply brownout condition or short interruption,
the XTR108 power-good detection circuit will initiate a chip
reset that will cause all registers to be reset to 0’s and a cycle
of EEPROM read to begin. The circuit generates a reset if
VS droops below 1.5V and then recovers up to the normal
level.
If the RST bit is set to ‘1’ in a write operation, all the
registers in the XTR108 will be returned to their power-on
reset condition. The RST bit will always read as a ‘0’. CSE,
the checksum error bit, is read only and will be set to ‘1’ if
a checksum error has been detected. This bit is cleared by a
reset operation or by detection of a valid checksum. The
remaining bits are reserved and must be set to ‘0’.
USING THE XTR108 IN VOLTAGE OUTPUT MODE
Address = 3: Fault Status Register
The XTR108 can be used not only in 4-20mA current loops,
but also as a low-power, single-supply, "smart" sensor-
conditioning chip with voltage output. In this mode,
the IRET pin must be connected below ground
(–200mV < IRET < –25mV). This negative voltage is
required to overcome the input offset voltage of the output
current amplifier and prevent it from turning on and drawing
excessive current. An application circuit that generates this
negative voltage using the XTR108 clock output and a
simple charge pump is shown in the application section.
This register is a read-only register. If the input voltage to
the PGA exceeds the linear range of operation, the XTR108
will indicate this error condition (typically caused by a
sensor fault) by setting the under-scale or over-scale error
level depending on the state of the Alarm Configuration
Register (Address = 7). Information on the nature of the fault
may be read in digital form from this register, as shown in
Table VI. The remaining bits will be set to ‘0’.
The sub-regulator with an external MOSFET may or may not
be used. If the circuit is powered externally, the supply
voltage must be in the range of 5V ±0.5V.
BIT
F0
F1
F2
F3
FAULT MODE
Negative Input Exceeds Positive Limit.
Negative Input Exceeds Negative Limit.
Positive Input Exceeds Positive Limit.
Positive Input Exceeds Negative Limit.
TABLE VI. Register 3, Fault Status Register.
Instruction
Read/Write
D7
R/W
0
D6
0
D5
0
D4
0
D3
A3
1
D2
A2
1
D1
A1
1
D0
A0
1
Read/Write Operation
Assert CS2
EEPROM Mode
1
1
1
Ignore Serial Data/A
Data Bit
D7
D6
D5
D4
D3
D2
D1
D0
0
1
RST
0
CSE
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
Reserved
Control Register 1
0
2
0
0
0
0
0
0
0
0
Reserved
3
0
0
0
0
F3
0
F2
F1
F0
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Fault Status Register
4
0
0
0
0
0
0
RBD
OS0
G0
Control Register 2
5
FD
0
US2
0
US1
0
US0
0
OS3
0
OS2
G2
AC2
VN2
IA2
FG2
CG2
FZ2
CZ2
L2
OS1
G1
AC1
VN1
IA1
FG1
CG1
FZ1
CZ1
L1
Over/Under-Scale Register
PGA Gain
6
7
AC7
0
AC6
VP2
IB2
FG6
CG6
FZ6
CZ6
L6
AC5
VP1
IB1
FG5
CG5
FZ5
CZ5
L5
AC4
VP0
IB0
FG4
CG4
FZ4
CZ4
L4
AC3
0
AC0
VN0
IA0
FG0
CG0
FZ0
CZ0
L0
Alarm Config. Register
PGA Input Config. Register
IREF Output Config. Register
Fine IREF Adjust Register
Coarse IREF Adjust Register
Fine Zero Adjust Register
Coarse Zero Adjust Register
Linearization Adjust Register
Checksum Register
8
9
0
0
10
11
12
13
14
15
FG7
CG7
FZ7
CZ7
L7
S7
FG3
CG3
FZ3
CZ3
L3
S6
S5
S4
S3
S2
S1
S0
TABLE V. Analog Control Registers.
XTR108
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Address = 4: Control Register 2
IO UNDER-SCALE
THRESHOLD
RVI = 6.34kΩ
VO UNDER-SCALE
THRESHOLD
If the RBD bit is set to ‘1’, the automatic read-back from the
EEPROM will be disabled after a valid checksum byte is
received in Register 15. This bit is read from the EEPROM
during a read-back by the XTR108 and allows the user to
program the XTR108 to read the EEPROM data once
(instead of continuously), and then disables the automatic
read-back function. The XTR108 will continuously read the
EEPROM if RBD is set to ‘0’. The remaining bits in this
register must be set to ‘0’.
US2
US1
US0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
450mV
425mV
400mV
375mV
350mV
325mV
300mV
275mV
3.55mA
3.35mA
3.15mA
2.96mA
2.76mA
2.56mA
2.37mA
2.17mA
TABLE VIII. Register 5, Under-Scale Threshold.
Address = 5: Over- and Under-Scale Register
This register sets the magnitude of the over-scale current
limit and the magnitude of the under-scale current limit. The
threshold level, as shown in Table VII and VIII, is the
normal analog (no error condition) output limit. If an input
voltage to the PGA exceeds the linear operation range, the
output will be programmed to either the over-scale error
level or the under-scale error level. The over-scale error
level is 10mA greater than the over-scale threshold level.
The under-scale error level is 0.4mA less than the under-
scale threshold level. The FD bit will disable the over-scale
and under-scale limiting function as well as the PGA fault
indication error levels.
SIGNAL PATH
TRANSCONDUCTANCE
PGA
VOLTAGE GAIN
G2
G1
G0
RVI = 6.34kΩ
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6.25V/V
12.5V/V
25V/V
49mA/V
99mA/V
197mA/V
394mA/V
789mA/V
1577mA/V
3155mA/V
50V/V
100V/V
200V/V
400V/V
Reserved
TABLE IX. Register 6, PGA Gains.
BIT
AC
AC
AC
AC
AC
AC
AC
AC
Address = 6: PGA Gain Register
#
VINN
VINP
7
h
l
6
l
h
5
l
l
4
h
h
3
n
l
2
n
h
1
l
n
0
h
n
This register sets the gain of the programmable-gain ampli-
fier. The unused bits must always be set to ‘0’. The gain step
to register content is given in Table IX.
NOTES: ‘h’ = input exceeds positive common-mode range, ‘l’ = input exceeds
negative common-mode range, and ‘n’ = input pin is within the CM range.
Address = 7: Alarm Configuration Register
TABLE X. Register 7, Alarm Configuration Register.
This register configures whether the XTR108 will go over-
scale or under-scale for various detected fault conditions at
the input of the PGA. Table X defines each of the bits.
Address = 8: PGA Input Configuration Register
If a bit corresponding to the particular error is set to ‘1’, the
output will go over-scale when it occurs and if a bit corre-
sponding to the particular error is set to ‘0’, the output will
go under-scale.
This register connects the inputs of the PGA to the various
multiplexed input pins. Tables XI and XII show the relation-
ship between register, contents, and PGA inputs.
VP2
VP1
VP0
PGA POSITIVE INPUT
IO OVER-SCALE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PGA VIN+ Connected to V/ I-0
PGA VIN+ Connected to V/ I-1
PGA VIN+ Connected to V/ I-2
PGA VIN+ Connected to V/ I-3
PGA VIN+ Connected to V/I-4
PGA VIN+ Connected to V/I-5
Reserved
VO OVER-SCALE
THRESHOLD
THRESHOLD
OS3
OS2 OS1
OS0
RVI = 6.34kΩ
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.625V
2.6875V
2.75V
2.8125V
2.875V
2.9375V
3.0V
3.0625V
3.125V
3.1875V
3.25V
3.3125V
3.375V
3.4375V
3.5V
20.7mA
21.2mA
21.7mA
22.2mA
22.7mA
23.2mA
23.7mA
24.2mA
24.6mA
25.1mA
25.6mA
26.1mA
26.6mA
27.1mA
27.6mA
28.1mA
Reserved
TABLE XI. Register 8, PGA Positive Input Selection.
VN2
VN1
VN0
PGA NEGATIVE INPUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PGA VIN– Connected to V/I-0
PGA VIN– Connected to V/I-1
PGA VIN– Connected to V/I-2
PGA VIN– Connected to V/I-3
PGA VIN– Connected to V/I-4
PGA VIN– Connected to V/I-5
Reserved
3.5625V
TABLE VII. Register 5, Over-Scale Threshold.
Reserved
TABLE XII. Register 8, PGA Negative Input Selection.
XTR108
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Address = 9: IREF Output Configuration Register
SERIAL INTERFACE
PROTOCOL
This register connects the reference currents to the various
multiplexed input pins. IREF connection codes are given in
Table XIII.
The XTR108 has an SPI-compatible serial interface. The
data is transmitted MSB first in 8-bit bytes. The first byte is
an instruction byte in which the first bit is a read/write flag
(‘0’ = write, ‘1’ = read), the lowest four bits are the register
address and the remaining three bits are set to zero. The
second, and all successive bytes, are data. During a write
operation, the successive data bytes are written to successive
registers within the XTR108. The address is automatically
incremented at the completion of each byte. The SDIO line
is always an input during a write operation. During a read
operation, the SDIO line becomes an output during the
second and successive bytes. As in the case of a write
operation, the address is automatically incremented at the
completion of each byte. Each communication transaction is
terminated when CS1 is de-asserted. The CS2 line remains
de-asserted during read and write operations.
Address = 10: Fine IREF Adjust Register
This register sets the code to the 8-bit Fine DAC that adjusts
the magnitude of both reference currents. The DAC output
value has a bipolar range (for each reference current) and
can be calculated using the equations in Table III.
IA2
IA1
IA0
IREF CONNECTION
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IREF1 Connected to V/ I-0
I
I
REF1 Connected to V/ I-1
REF1 Connected to V/ I-2
I
I
REF1 Connected to V/ I-3
REF1 Connected to V/ I-4
IREF1 Connected to V/ I-5
Reserved
Reserved
IB2
IB1
IB0
IREF CONNECTION
The calibration controller also needs to be able to read from
and write to the external EEPROM device. This is accom-
plished by sending a special instruction code (0x7F) to the
XTR108. At the completion of this instruction byte, the
XTR108 will assert the CS2 line to select the EEPROM
device and ignore all data on the SDIO line until CS1 is de-
asserted and reasserted. The CS2 line will also be de-
asserted when CS1 is de-asserted. This allows the calibra-
tion controller to communicate with the EEPROM device
directly. The calibration controller then has control over the
timing required to write data to the EEPROM device.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IREF2 Connected to V/ I-0
REF2 Connected to V/ I-1
REF2 Connected to V/ I-2
I
I
I
I
REF2 Connected to V/ I-3
REF2 Connected to V/ I-4
IREF2 Connected to V/ I-5
Reserved
Reserved
TABLE XIII. Register 9, IREF Output Configuration.
Address = 11: Coarse IREF Adjust Register
In normal operation, the XTR108 reads data from the EEPROM
device to retrieve calibration coefficients. This is accom-
plished by the read-back controller on the XTR108. The read-
back controller is clocked by an on-chip oscillator and pro-
vides stimulus to the EEPROM device over the SCLK, SDIO,
and CS2 lines to perform the read operation, while simulta-
neously providing stimulus to the serial interface controller in
the XTR108. The read-back controller defaults to being active
when the XTR108 is powered on and will be continuously
active unless disabled. (It will start a new read operation as
soon as the previous operation is completed, see Figure 4.) A
control bit (RBD) is provided to allow the XTR108 to read the
EEPROM once and then stop.
This register sets the code to the 8-bit coarse DAC that adjusts
the magnitude of both reference currents. The nominal value
for the reference current (both Coarse and Fine adjust set to ‘0’)
is IPROGRAM • 5. See Table III for formulas.
Address = 12: Fine Zero-Adjust Register
This register sets the code to the 8-bit Fine DAC that adjusts
the magnitude of the zero output currents. Equations are
given in Table II. Negative numbers are in Binary Two’s
Complement.
Address = 13: Coarse Zero-Adjust Register
This register sets the code to the 8-bit Coarse DAC that
adjusts the magnitude of zero-output current. See Table II
for equations. Negative numbers are given in Binary Two’s
Complement.
The read-back controller will abort a read-back operation
when the CS1 line is asserted. The calibration controller
must wait at least 40µs after setting the CS1 line LOW
before the first rising edge of SCLK occurs.
Address = 14: Linearization Adjust Register
This register sets the code to the 8-bit DAC that adjusts the
magnitude of the linearization feedback current. Value is
unipolar to 255.
For an external controller to write directly to the XTR108
(sensor calibration operation) or load data into the EEPROM,
it is necessary to interrupt the default read-back mode. For
both of these modes, the SCLK direction must be reversed.
See Figure 5 for the timing of this operation. First, the SCLK
line must be pulled LOW for at least 20ns (t10). Then CS1
is set LOW. The XTR108 will set DIO to a tri-state within
20ns (t13) and CS2 HIGH within 50ns (t12). After a delay of
at least 40µs (t11), the external system will start communica-
tion with a rising edge on SCLK.
Address = 15: Checksum Register
This register contains the checksum byte that is used to
validate the data read from the EEPROM. If a write occurs
to this register, and the checksum is invalid, an error condi-
tion will set (CSE = ‘1’). If the checksum is valid, the error
condition will be cleared (CSE = ‘0’).
If a checksum error is detected, the XTR108 will program
itself to the lowest under-scale error level.
XTR108
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Hi-Z
SCLK
t8
t8
DIO
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
t9
Instruction/Address to EEPROM
Data from EEPROM
CS2
FIGURE 4. Timing Diagram for the XTR108 Continuous Readback Cycle. (See Table XIV for timing key.)
SCLK
t10
t11
DIO
t13
CS2
t12
CS1
FIGURE 5. Interrupting an XTR108 EEPROM Readback Cycle. (See Table XIV for timing key.)
As long as CS1 is held LOW, the external system can write to
the EEPROM. See Figure 7 for this timing. Releasing CS1
will allow the XTR108 to resume in the read-back mode.
contents which will overwrite the data just loaded. Figure 6
shows read and write timing.
To be compatible with SPI EEPROM devices, the XTR108
latches input data on the rising edge of SCLK. Output data
transitions on the falling edge of SCLK. All serial interface
transactions must be framed by CS1. CS1 must be asserted
to start an operation, and it must be de-asserted to terminate
an operation.
For interactive calibration operations, the first command to
the XTR108 should set bit 0, Register 4 (RBD). This will
disable the read-back mode. It will be possible to write to the
various registers and cycle CS1. If RBD is not set, then as
soon as CS1 is released, the XTR108 will read the EEPROM
XTR108
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CS1
t7
t1
t5
SCLK
t2
t2
t3
t4
t6
DIO
FIGURE 6. Timing Diagram for Writing to and Reading From the XTR108 with EEPROM Readback Disabled. (See Table
XIV for timing key.)
SCLK
0
1
1
1
1
1
1
1
DIO
Instruction to XTR108
Data to/from EEPROM
CS1
CS2
t14
FIGURE 7. Writing to and Reading From the EEPROM Device From External Controller. (See Table XIV for timing key.)
SPEC
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
t2
CS1 LOW to SCLK Rising Setup Time
SCLK Pulse Width HIGH and LOW
2.0
100
20
20
20
0
ns
ns
ns
ns
ns
ns
ns
us
us
ns
us
ns
ns
ns
kHz
t3
DIO to SCLK Rising Setup Time
t4
DIO to SCLK Rising Hold Time
t5
CS1 to Last SCLK Rising Hold Time
t6
SCLK Falling to DIO Driven Valid by XTR108
CS1 to DIO Tri-State
50
20
t7
0
t8
SCLK Pulse Width During EEPROM Readback
CS2 HIGH Between Successive EEPROM Readbacks
SCLK Driven LOW Before CS1 LOW When Interrupting XTR108 Readback from EEPROM
CS1 LOW to SCLK Rising Setup Time When Interrupting XTR108 EEPROM Readback
CS1 Falling to CS2 HIGH
5
t9
10
t10
t11
t12
t13
t14
20
40
0
50
20
20
CS1 Falling to DIO Tri-State
0
CS1 Rising to CS2 HIGH
0
XTR108 EEPROM Update Rate in Continuous Readback Mode
0.9
TABLE XIV. Timing Diagram Key.
XTR108
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write enable instruction to be executed to write data to the
EEPROM. It is unlikely that this would accidentally be
written to the EEPROM device and then be followed by a
valid write operation. Further security can be obtained by
using an SPI EEPROM device that has internal write-protect
control bits. These bits are nonvolatile and must be cleared
before write operations are allowed.
EEPROM DATA STORAGE
The XTR108 automatically reads data from an SPI-compat-
ible EEPROM device. The models 25C040 from MicroChip
and the AT25010 from Atmel have been tested and are
known to work. Equivalent devices with an SPI interface can
be expected to work. The XTR108 will read data from
addresses 4 through 15 of the EEPROM. The address in the
EEPROM is the same as the address for the corresponding
data in the XTR108. The XTR108 will not write data to the
EEPROM. The external calibration controller is responsible
for writing data to the EEPROM.
SURGE PROTECTION
Remote connections to current transmitters can sometimes
be subjected to voltage surges. It is prudent to limit the
maximum surge voltage applied to the XTR108 with various
zener diodes and surge-clamping diodes specially designed
for this purpose. Since the maximum voltage on the XTR108
loop is limited by the external MOSFET breakdown voltage,
usually more than 200V, the requirement to the clamping
devices are not very strict. For example, a 50V protection
diode will assure proper transmitter operation at normal loop
voltages without significant leakage yet provide an appro-
priate level of protection against voltage surges. In case of
prolonged (seconds and longer) overvoltage, lower voltage
clamps may be used to limit the power dissipation on the
transmitter.
CHECKSUM FUNCTION
To validate the data from the EEPROM device, the XTR108
calculates a checksum on the incoming serial-data stream
during each write operation. The value written to the EEPROM
that will be transferred to register 15 during an EEPROM read
operation must be such that the sum of the data in registers 4
through 15 totals 0xFF (255). The sum is calculated by
performing an add/accumulate function on all of the data
bytes of a read operation. An end-around carry is used during
the add/accumulate operation. If a carry-out was generated in
the previous add operation, it is used as a carry-in for the next
add operation for the checksum operation. The following code
shows how the value of register 15 could be calculated:
Most surge-protection zener diodes have a diode character-
istic in the forward direction that will conduct excessive
current, possibly damaging receiving-side circuitry if the
loop connections are reversed. If a surge protection diode is
used, a series diode or diode bridge should be used for
protection against reversed connections.
Sum = 0
FOR Index = 4 TO 14
Sum = Sum + Data [Index]
IF Sum > 255 THEN
Sum = Sum – 255
NEXT Index
REVERSE-VOLTAGE PROTECTION
The XTR108’s low compliance rating (7.5V) permits the
use of various voltage protection methods without compro-
mising operating range. Figure 8 shows a diode bridge
circuit which allows normal operation even when the volt-
age connection lines are reversed. The bridge causes a two
diode drop (approximately 1.4V) loss in loop supply volt-
age. This results in a compliance voltage of approximately
9V—satisfactory for most applications. If 1.4V drop in loop
supply is too much, a diode can be inserted in series with the
loop supply voltage and the V+ pin. This protects against
reverse output connection lines with only a 0.7V loss in loop
supply voltage.
Data [15] = 255 – Sum
For a test or calibration operation, it may be necessary to
write to a few select registers. This may be accomplished
without writing to register 15. To accomplish this, write to
the necessary registers and release CS1. There is no need to
update register 15.
If the command is to disable the automatic read-back func-
tion by setting the RDB bit in register 4, it is necessary to
rewrite the entire register set data with a correct checksum
value in register 15. The automatic read-back mode will be
disabled upon successful checksum operation.
RADIO FREQUENCY INTERFERENCE
The long wire lengths of current loops invite radio frequency
interference. RF energy can be rectified by the sensitive
input circuitry of the XTR108 causing errors. This generally
appears as an unstable output current that varies with the
position of loop supply or input wiring.
The checksum error flag is also cleared when the XTR108
is reset (i.e.: at power ON). Write operations that do not
write to the checksum register will have no effect on the
checksum error flag. By locating the checksum register after
the last configuration register and including the checksum
register in the EEPROM read operation, the data is validated
by the checksum function.
If the RTD sensor is remotely located, the interference may
enter at the input terminals. For integrated transmitter as-
semblies with short connection to the sensor, the interfer-
ence more likely comes from the current loop connections.
EEPROM DATA SECURITY
Bypass capacitors on the input reduce or eliminate this input
interference. Connect these bypass capacitors to the IRET
terminal, see Figure 9. Although the DC voltage at the IRET
terminal is not equal to 0V (at the loop supply, VPS) this
circuit point can be considered the transmitter’s “ground.”
The 0.01µF capacitor connected between VLOOP and IO may
help minimize output interference.
Since the data in the EEPROM directly affects the analog
output of the XTR108, the data in the EEPROM needs to be
secure from accidental write operations. SPI EEPROM de-
vices have a write-protect function on one of the pins. An
additional connection to the calibration controller would be
required if the write-protect pin is used to prevent accidental
write operations. SPI EEPROM devices require a special
XTR108
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NOTE: (1) Zener Diode 36V: 1N4753A or General
Semiconductor TransorbTM 1N6286A. Use lower
voltage zener diodes with loop power supply
voltages less than 30V for increased protection.
See “Over-Voltage Surge Protection.”
10
V+
0.01µF
1N4148
Diodes
(1)
14
13
D1
XTR108
Maximum VPS must be
less than minimum
voltage rating of zener
RL
VPS
diode.
IO
11
The diode bridge causes
a 1.4V loss in loop supply
voltage.
IRET
12
FIGURE 8. Reverse Voltage and Over-Voltage Protection.
1) For a chosen temperature range, using an industry-stan-
dard polynomial set as shown in Table XVI, calculate
RTD values at min, max, and the middle temperatures:
RTD APPLICATION
The values to be entered into the DAC control registers are
given by the formulas in Table XV.
R
MIN, RMAX, and RMID
(
)
EXCITATION CURRENT IREF
2) Calculate a relative nonlinearity BV using the RTD val-
ues from above:
Coarse DAC code
64 • IREFRSET
N11 = round
− 320
R
+ R
MIN
VREF
MAX
R
–
MID
2
B
=
V
Fine DAC Code
N10 = round
R
– R
MAX
MIN
1024 • IREFRSET
− 5120 − 16 • N11
VREF
3) Pick an external zero resistor, RZ closest to RMIN. Select-
ing RZ greater than RMIN will cause a voltage offset that
must be corrected by the PGA zero adjustment.
4) Calculate the linearization coefficient::
ZERO OUTPUT IZERO
Coarse DAC Code
32 • IZERORVI
N13 = round
− 140
5 • VREF
2BV
GLIN
=
0.5 + B
R
– 0.5 – B
R
– 2BVRZ
MIN
(
)
(
)
V
MAX
V
Fine DAC Code
512 • IZERORVI
5 • VREF
N12 = round
− 2240 − 16 • N13
If the value of GLIN is larger than GLIN MAX = (16/
RLIN) the external resistor RLIN has to be changed. If
GLIN is significantly smaller (> 10 times) than GLIN
MAX, the RLIN value should be increased to minimize
the DAC quantization errors. For 100Ω RTD sensors
the required linearization coefficients are in the range
from 0.3 to 0.6 mA/V (1/kΩ) for all measurement
ranges. Therefore an external RLIN value of 15.8kΩ is
good setting the full-scale GLIN MAX ~ = 1mA/V. For
1kΩ RTD’s the RLIN should be increased proportion-
ally.
LINEARIZATION COEFFICIENT GLIN
Lin DAC Code
N14 = round 16 • GLINRLIN
(
)
TABLE XV. Equations for DAC Code Calculation.
This procedure allows calculation of the parameters needed
to calculate the DAC codes for an RTD sensors application.
Standard RTD Polynomials :
5) Choose the output zero and full-scale level values, for
instance: IOUTMIN = 4mA, IOUTMAX = 20mA.
Rt = RO 1+ At + B12 + C t − 100°C t3 for − 200°C < t < 0°C
(
)
[
[
]
Rt = RO 1+ At + B12 for 0°C < t < 850°C
]
A = 3.9083e − 3
B = −5.775e − 7
C = −4.183e − 12
RO − base RTD value at 0°C 100Ω or 1kΩ
(
)
TABLE XVI. Standard RTD Descriptive Equations.
XTR108
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6) Choose PGA gain from the available list and calculate
the initial excitation current using:
Step 3.
• Calculate corrections using the following equations:
I
– IMEAS1 R
VI
(
=
)
MEAS2
I
– I
• 1– G
R
– RZ • R
MAX VI
(
)
(
)
(
)
I
OUTMAX
OUTMIN
LIN
REFA
50APGA
R
– RMIN
MAX
IREF
=
(
)
1,2
50 • APGA • R
– RMIN
(
)
MAX
I
– IMEAS1 R
(
)
ZERO
VI
RZ = RMIN
+
A
50APGAIREFA
Important: the PGA gain value should be chosen such
that the IREF value is within ±35% of 5VREF/RSET to
allow room for calibration adjustments without having
to go to another span step.
2BV
GLINA
=
0.5 + B
R
– 0.5 – B
R
– 2BVRZA
MIN
(
)
(
)
V
MAX
V
I
(
– I OUT
• 1– G
R
– RZA • RVI
7) The required DAC zero offset current value can be
calculated by:
)
(
)
OUT
MAX
(
LIN_ A
MAX
)
MIN
IREF
=
B
50 • APGA • R
– RMIN
(
)
MAX
∆IREF = I
– IREF + I
– IREF
REF
B
(
)
(
)
REF
A
50 • APGAIREF
R
– RZ
MIN
(
)
IZERO = I
–
OUTMIN
1024 • ∆IREFRSET
RVI
Adjusted IREF fine DAC Code : N10 = N10 + round
A
VREF
50 • APGA REF
I
R
(
MIN – RZA
Example:
)
B
∆IZERO = IOUT
– IZERO –
MIN
Measurement Range: TMIN = –20°C, TMAX = 50°C; 100Ω
RVI
RTD.
512 • ∆IZERORVI
5 • VREF
Adjusted IZERO fine DAC Code : N12 = N12 + round
A
1) RMIN = 92.16Ω, RMAX = 119.40Ω, RMID = 105.85Ω;
2) Sensor relative nonlinearity: BV = 0.0026;
3) Choosing RZ = 90.9Ω (closest to RMIN 2% value);
4) Linearization coefficient: GLIN = 0.3804mA/V;
5) 4-20mA output span;
This takes into account resistor value deviations, all
offsets and gain errors of the coarse DACs and PGA. If
the adjusted abs(N12A) > 128 or abs(N10A) > 128, adjust
the coarse DAC first, then recalculate the fine DAC
value;
6) PGA voltage gain APGA = 200, sensor excitation current
IREF1,2 = 368.39mA;
• Update all the DAC register value, including lineariza-
tion DAC.
7) Zero offset DAC: IZERO = 3.268mA
Step 4 (optional).
Measure output signal IMEAS3 with maximum RTD value
still connected to the input from step 2;
CALIBRATION PROCEDURE FOR RTD SENSORS
Step 1 Initial parameters calculation.
• Using the procedure above, compute IREF, APGA, IZERO
,
Step 5 (optional).
and GLIN based on TMIN, TMAX, and nominal values of
RZ, RSET, and RVI. Use the equation in Table XV to
calculate the DAC register values.
Compute GLIN correction and update LinDAC register;
Step 6 (optional).
Make verification measurements at min- and max-input
signal; If linearity check is needed: make a measurement at
mid-scale; write EEPROM data.
• Configure the input MUX, write PGA gain, reference,
and offset DAC registers of the XTR108 with calcu-
lated settings. Note: write GLIN = 0 (no linearization) to
XTR108 at this step;
Step 7.
Set the desired over-scale, under-scale signal limits and
sensor burnout indication configuration. Verify and adjust
the over-scale and under-scale levels by applying the posi-
tive and negative overdriving differential signals to the PGA
inputs.
Step 2 Measurement.
• Set RTD resistor value (or oven temperature) to mini-
mum scale, measure output signal IMEAS1
• Set RTD resistor value (or oven temperature) to maxi-
mum scale, measure output signal IMEAS2
;
;
XTR108
20
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assumption is made that all errors are positive and additive.
As the various error sources are independent, a closer
approximation to nominal performance might be to accumu-
late the errors with a root-sum-square calculation.
SAMPLE ERROR ANALYSIS
Table XVII shows a detailed computation of the error
accumulation. The sample error budget is based on a typical
RTD circuit (Pt100, 200°C measurement span). Note that
these calculations are based on typical characteristics where
no maximum or minimum characteristic is available. The
SAMPLE ERROR CALCULATION
RTD value at 4mA Output (RRTD MIN) 100Ω: RTD Measurement Range 200°C; Ambient Temperature Range (∆TA) 20°C; Supply Voltage Change (∆V+) 5V; Common-
Mode Voltage Change (∆CM) 0.1V.
Chosen XTR108 parameters: PGIA gain = 50; IREF = 518.9µA; Full-scale VIN = 40mW. Register 06 = 0H03; Register 11 = 0H11; Register 13 = 0HFC; Register 14 = 0H70.
CALIBRATED ERROR
ERROR SOURCE
ERROR EQUATION
SAMPLE ERROR CALCULATION
(ppm of Full Scale)
INPUT
Input Offset Voltage
vs Common Mode
Input Bias Current
Input Offset Current
Note (1)
CMRR • ∆CM/(VIN MAX) • 106
Note (1)
0
12.5
0
5µV/V • 0.1V/0.04V • 106
Note (1)
0
Total Input Error:
12.5
EXCITATION
Current Reference Accuracy
vs Common Mode
Current Reference Matching
DAC Resolution and Linearity
Note (1)
0
2.5
∆CM/ROUT • RRTD MIN/(VIN MAX) • 106
Note (1)
0.1V/100MΩ • 100Ω/40mV
1LSBFINE • RRTD MIN/(VIN MAX) • 106
96nA • 100Ω/40mV • 106
240
Total Excitation Error:
242.5
GAIN
Span
Nonlinearity
Note (1)
Nonlinearity (%)/100% • 106
0
100
100
0.01%/100% • 106
Total Gain Error:
OUTPUT
Zero Output
vs Supply
DAC Resolution and Linearity
Note (1)
(IZERO vs V+) • ∆V+/16mA • 106
2LSBFINE/16mA • 106
0
6
225
231
Note (2)
2 • 1.8µA/16mA • 106
Total Output Error:
DRIFT (∆TA = 20°C)
Input Offset Voltage
Current Reference Accuracy
Current Reference Matching
Span
Drift • ∆TA/(VIN MAX) • 106
Drift • ∆TA
Drift • ∆TA • IREF • RRTD MIN/(VIN MAX
0.02µV/°C • 20°C/40mV • 106
35ppm • 20°C
15ppm • 20°C • 518.9µA • 100/40mV
30ppm • 20°C
10
700
390
600
250
1950
)
Drift • ∆TA
Drift • ∆TA
Zero Output
Note (1)
Total Drift Error:
NOISE (0.1Hz to 10Hz, Typ)
Input Offset Voltage
Current Reference
Zero Output
VN/(VIN MAX) • 106
IREF Noise • RRTD MIN/(VIN MAX) • 106
IZERO Noise/16mA • 106
6µV/40mV • 106
0.015µA • 100Ω/40mV • 106
1.1µA/16mA • 106
150
37.5
68.5
256
Total Noise Error:
TOTAL ERROR:
2792 (1997)(3)
0.28% (0.20%)(3)
NOTES: (1) Does not contribute to the output error due to calibration. (2) All errors are referred to input unless otherwise stated. (3) Calculated as root-
sum–square.
TABLE XVII. Sample Error Budget Calculation.
XTR108
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Four-Wire Connection
APPLICATIONS
For those applications where the resistance of the lead-wires
is not equal, it may be an advantage to add a precision op
amp to a four-wire connection, see Figure 11. The voltage
offset and drift are error terms that degrade the operation of
the system. This circuit does not suffer any loss of accuracy
for the resistance of the RTD lead-wires.
RTD CONNECTION METHODS
Two-Wire Connection
The simplest circuit that can be used to connect an RTD to
the XTR108 is the two-wire connection shown in Figure 9.
If the RTD is separated from the XTR108 by any distance
the resistance of the lead wires can cause significant error in
the reading. This wire resistance is noted as RLINE1 and
RLINE2. If the RF filter is not required, then the PGA inputs
could be taken from the same pins as are used for the current
sources.
BRIDGE SENSOR CONNECTIONS
Fixed Voltage Excitation
There exists a class of sensors that are best supplied with a
voltage source excitation such as the bridge sensor shown in
Figure 12. The excitation voltage here is given by:
Three-Wire Connection
It is possible to minimize the errors caused by the lead-wire
resistance by connecting the RTD, see Figure 10. Operating
under the assumption that the wire connecting pin 1 to the
XTR108 is the same length as the wire at pin 2, and with the
current through the RTD identical to the current through RZ
any error voltage caused by the lead-wire is the same on both
sides. This appears as a common-mode voltage and is
subtracted by the PGA.
R1
VEX = VREF 1+
R2
Uni-Directional Linearity Control
The circuit in Figure 13 shows a bridge sensor with an
excitation voltage that is adjusted to linearize the response
using the same algorithm as the RTD linearization.
The circuit in Figure 10 also shows a scheme where one
board can be optimized for a wide range of temperatures.
Consider a range of applications where there are up to five
different minimum temperatures. Select RZ1 through RZ5 to
be optimum for each of the minimum temperatures. The
configuration codes in the EEPROM can be set to select that
resistor for that unique situation.
VEX = 2 • IREF RI
1kΩ
1
1kΩ
RLINE1
RTD
RZ
0.01µF
0.01µF
RLINE2
IRET
RCM
2
0.01µF
FIGURE 9. Two-Wire RTD Connection with RF Filter at Input Terminals.
XTR108
22
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R21
R22
R23
R24
R25
Equal line resistances here create a
small common-mode voltage which is
rejected by the XTR108.
2
1
RLINE2
RLINE1
RTD
IRET
RLINE3
RCM
3
Resistance in this line causes a small
common-mode voltage which is rejected
by the XTR108.
0.01µF
FIGURE 10. Three-Wire RTD Connection with Multiple Minimum Temperature Capabilities.
VS
RLINE1
1
RLINE2
2
RTD
RZ
RLINE3
OPA277
3
4
IRET
RLINE4
RCM
0.01µF
FIGURE 11. Four-Wire RTD Connection.
XTR108
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VREF
R1
R2
IRET
FIGURE 12. Voltage Excited Bridge with Excitation Derived from VREF
.
VREF
R1
IRET
FIGURE 13. Voltage Excited Bridge with Uni-Directional Linearity by Control.
XTR108
24
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VOLTAGE OUTPUT MODE USING SIMPLE
CURRENT PUMP
to build this charge pump using two resistors, two capaci-
tors, and two diodes (in an SOT package). The charge pump
uses the clock signal from the XTR108 SCLK pin to operate;
consequently, the XTR108 must be in continuous EEPROM
read mode (register 4, bit 0). Figure 15 shows the typical
output of this circuit (–50mV dc).
In order for the voltage output mode of the XTR108 to
operate properly, a negative voltage needs to be applied to
the IRET pin (–200mV < IRET < –25mV). For systems without
a negative supply a charge pump is an easy way to generate
this voltage. Figure 14 shows a simple and inexpensive way
VOUT = −50mV
BAV99
36.5kΩ
1nF
OPA –IN
OPA +IN
CS1 CS2 SDIO SCLK
30kΩ 330pF
XTR108
SPI and
Control Circuits
OPA OUT
REFIN
OSC
Voltage
Reference
REFOUT
IREF
Σ
DAC
+5V
ILIN
VGate
DAC
Sub-Regulator
VS
Driver
1
2
−200mV < VOA+ < −25mV
Zero
DAC
Q1
V/I-0
V/I-1
V/I-2
Output
Current
Amplifier
IQ1 = 0mA
DSUB
PGA
V/I-3
V/I-4
V/I-5
0mV
RZ1 RZ2 RZ3 RZ4 RZ5
2.5kΩ
51Ω
Linearization
Circuit
IO
RTD
CFILT
0.01µF
RLIN
RSET
VOUT
IIN
IRET
RCM
15.8kΩ
12.1kΩ
VOUT
FIGURE 14. Voltage Output Mode Using Simple Current Pump.
XTR108
SCLK
5.0V
−50mV
Charge
Pump
Output
FIGURE 15. Output Waveform of Simple Current Pump.
XTR108
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COMMUNICATIONS WITH THE XTR108 USING A
MICROCONTROLLER
SCLK is driven low by the
microcontroller just before
CS1 is driven low.
When communicating with the XTR108, special care must
be taken to avoid getting a false clock. When CS1 is driven
low, the false clock is generated because the microcontroller
clock pin is in high-impedance state, which forces the clock
pin to a logic high. Immediately after CS1 is driven low, the
microcontroller drives the clock pin low. This sequence
creates a glitch that the XTR interprets as a clock; see Figure
16. This condition can be avoided by driving the SCLK pin
low just prior to applying CS1 low; see Figure 17. A series
resistance should be placed between the microcontroller and
the XTR108 because driving SCLK low before CS1 can
create a bus contention; see Figure 18.
SCLK is in High Z mode
(Pulled high by the pull-up
in the XTR108)
SCLK
CS1
FIGURE 17. Proper Method to Drive the XTR108 to Avoid
False Clock.
SCLK will be high immediately
after CS1 is driven low. This is
seen by the XTR108 as an
false clock.
XTR108
Microcontroller
VCC
CS1
SCLK is in High Z mode
(Pulled high by the pull-up
in the XTR108)
1kΩ
SCLK
SCLK
DIO
DIO
CS2
SCLK
CS SCLK DIO
Memory
CS1
FIGURE 16. False Clock.
FIGURE 18. Resistor Protects XTR108 and Microcontroller
During Bus Contention.
XTR108
26
SBOS187C
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
XTR108EA
ACTIVE
ACTIVE
SSOP
SSOP
DBQ
DBQ
24
24
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
XTR108EA
XTR108EA
XTR108EA/2K5
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
XTR108EA/2K5
SSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DBQ 24
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
XTR108EA/2K5
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DBQ SSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
XTR108EA
24
50
506.6
8
3940
4.32
Pack Materials-Page 3
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