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XTR305

ZHCSHO6 –FEBRUARY 2018

XTR305 工业模拟电流或电压输出驱动器

1 特性

3 说明

1

•

用户可选：电流或电压输出

_OUT：±10V（电源电压为 ±20V 时高达 ±17.5V）

_OUT：±20mA（线性电流高达 ±24mA）

XTR305 是一个完整的输出驱动器，适用于成本敏感型

工业和过程控制应用供电的绝佳器件。数字 I/V 选择

引脚可将输出配置为电流或电压。无需外部分流电阻

器。只需要外部增益设置电阻器和环路补偿电容器。

V

I

40V 电源电压

诊断特性：

独立的驱动器和接收器通道可提供灵活性。仪表放大器

(IA) 可用于远程电压传感或用作高电压、高阻抗测量通

道。在电压输出模式下，提供输出电流的副本，允许计

算负载电阻。

–

短路或开路故障指示灯引脚

热保护

过流保护

•

无需电流分流

利用数字输出选择功能、错误标志以及监控器引脚，可

进行远程配置和故障排除。输出和 IA 输入的故障条件

以及过热情况由错误标志指示。监控引脚提供有关负载

功率或阻抗的持续反馈。为了获得额外的保护，最大输

出电流是受限的，并提供过热保护。

适用于单输入模式的输出禁用

独立驱动器和接收器通道

专为可测试性而设计

2 应用

•

电机驱动器模式输出：电流为 4-20mA，电压为

±10V

XTR305 具有 −40°C 至 +85°C 的额定工业温度范围，

电源电压最高可达 40V，并可在 −55°C 至 +125°C 的

扩展温度范围内正常运行。

•

PLC 输出可编程驱动器

工业交叉连接器

器件信息⁽¹⁾

工业高电压 I/O

器件型号

XTR305

封装

VQFN (20)

封装尺寸（标称值）

3 线传感器电流或电压输出

±10V 2 线和 4 线电压输出

美国专利号7,427,898、7,425,848 和 7,449,873

5.00mm × 5.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

典型应用

C_C

V-

Current Copy

I_COPY

V+

XTR305

IMON

R_IMON

1 kΩ

I_DRV

Input Signal

(Optional)

V_IN

DRV

IA_IN+

OPA

SET

R_OS

R_SET

I_IA

RG₁

RG₂

R_GAIN

Load

IA

GND1

V_REF

IA_IN-

IA_OUT

GND2

EF_CM

EF_LD

EF_OT

R_IA

OD

M1

M2

1 kΩ

Digital

Error

Control

Flags

GND3

DGND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBOS913

XTR305

ZHCSHO6 –FEBRUARY 2018

www.ti.com.cn

7.2 Functional Block Diagrams ..................................... 16

7.3 Feature Description................................................. 18

7.4 Device Functional Modes........................................ 20

Application and Implementation ........................ 21

8.1 Application Information............................................ 21

8.2 Typical Application ................................................. 21

Power Supply Recommendations...................... 29

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics: Voltage Output Mode....... 5

6.6 Electrical Characteristics: Current Output Mode....... 6

8

9

10 Layout................................................................... 30

10.1 Layout Guidelines ................................................. 30

10.2 Layout Example .................................................... 30

10.3 VQFN Package and Heat Sinking......................... 31

10.4 Power Dissipation ................................................. 32

11 器件和文档支持 ..................................................... 33

11.1 文档支持 ............................................................... 33

11.2 接收文档更新通知 ................................................. 33

11.3 社区资源................................................................ 33

11.4 商标....................................................................... 33

11.5 静电放电警告......................................................... 33

11.6 Glossary................................................................ 33

12 机械、封装和可订购信息....................................... 33

6.7 Electrical Characteristics: Operational Amplifier

(OPA) ......................................................................... 7

6.8 Electrical Characteristics: Instrumentation Amplifier

(IA) ............................................................................. 8

6.9 Electrical Characteristics: Current Monitor................ 9

6.10 Electrical Characteristics: Power and Digital .......... 9

6.11 Typical Characteristics.......................................... 10

Detailed Description ............................................ 16

7.1 Overview ................................................................. 16

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2018 年 2 月

*

初始发行版

2

XTR305

www.ti.com.cn

ZHCSHO6 –FEBRUARY 2018

5 Pin Configuration and Functions

RGW Package

20-Pin VQFN With Thermal Pad

Top View

20 19 18 17 16

1

15

V+

M2

M1

Exposed

Thermal

Die Pad

on

2

3

4

5

14

13

12

11

NC

DRV

NC

V-

V_IN

Underside

(must be

connected

to V-)

SET

I_MON

6

7

8

9

10

Pad

Pin Functions

I/O

DESCRIPTION

NO.

1

NAME

M2

I

Mode input

2

M1

3

V_IN

I

Noninverting signal input

4

SET

I_MON

IA_OUT

IA_IN–

IA_IN+

RG1

RG2

V–

I

Input for gain setting; inverting input

Current monitor output

5

O

I

6

Instrumentation amplifier signal output

7

Instrumentation amplifier inverting input

Instrumentation amplifier noninverting input

Instrumentation amplifier gain resistor

Negative power supply

8

I

9

I

10

11

12

13

14

15

16

17

18

19

20

Pad

I

-

NC

-

No internal connection

DRV

NC

O

-

Operational amplifier output

No internal connection

V+

-

Positive power supply

DGND

EF_CM

EF_LD

EF_OT

OD

-

Ground for digital I/O

O

I

Error flag for common mode over range, active low

Error flag for load error, active low

Error flag for over temperature, active low

Output disable, disabled low

Exposed Pad

-

Exposed thermal pad must be connected to V−

3

XTR305

ZHCSHO6 –FEBRUARY 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

+44

UNIT

V

Supply voltage, V_VSP

Voltage⁽²⁾

Signal input terminals

Current⁽²⁾

(V−) − 0.5

(V+) + 0.5

±25

V

mA

DGND

±25

Output short circuit⁽³⁾

Operating temperature

Junction temperature

Storage temperature, T_stg

Continuous

–55

125

150

125

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must

be current limited. DRV pin allows a peak current of 50 mA. See the Output Protection section in Application and Implementation.

(3) See Driver Output Disable in Application and Implementation for thermal protection.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

−40

−55

NOM

MAX

85

125⁽¹⁾

UNIT

°C

Specified temperature range

Operating temperature range

°C

(1) EF_OTnot connected with OD.

6.4 Thermal Information

XTR305

THERMAL METRIC⁽¹⁾

RGW (VQFN)

20 PINS

32.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

25.1

12.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

12.6

R_θJC(bot)

3.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

4

XTR305

www.ti.com.cn

ZHCSHO6 –FEBRUARY 2018

6.5 Electrical Characteristics: Voltage Output Mode

All specifications at T_A= 25°C, V_S= ±20 V, R_LOAD= 800 Ω, R_SET= 2 kΩ, R_OS= 2 kΩ, V_REF= 4 V, R_GAIN= 10 kΩ, input signal

span 0 V to 4 V, and C_C= 100 pF, unless otherwise noted.

PARAMETER

OFFSET VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OS

Offset voltage, RTI

±0.4

±1.6

±0.2

±2.5

±10

mV

dV_OS/dT

PSRR

Offset voltage vs temperature

Offset voltage vs power supply

T_A= –40°C to 85°C

μV/°C

μV/V

V_S= ±5 V to ±22 V

INPUT VOLTAGE RANGE

Nominal setup for ±10-V output

See Figure 35

Input voltage for linear operation

(V−) + 3

(V+) − 3

V

NOISE

Voltage noise, f = 0.1 Hz to 10 Hz,

RTI

3

μV_PP

Voltage noise density, f = 1 kHz,

RTI

e_n

40

nV/√Hz

OUTPUT

Voltage output swing from rail

Gain nonlinearity

I

_DRV≤ 15 mA, T_A= –40°C to 85°C

(V−) +3

(V+) − 3

±0.2

±1

V

±0.01

±0.1

±0.04

±0.2

7

%FS

Gain nonlinearity vs temperature

Gain error

T_A= –40°C to 85°C

ppm/°C

%FS

I_B

±0.2

±1

Gain error vs temperature

Output impedance, dV_DRV/dI_DRV

ppm/°C

mΩ

Output leakage current while output

disabled

OD pin = L⁽¹⁾, T_A= –40°C to 85°C

30

nA

I_SC

Short-circuit current

Capacitive load drive

T_A= –40°C to 85°C

C_C= 10 nF, R_C= 15⁽²⁾

±15

±20

1

±24

mA

C_LOAD

μF

Rejection of voltage difference

between GND1 and GND2, RTO

130

dB

FREQUENCY RESPONSE

Bandwidth⁽³⁾

−3 dB, G = 5

300

1

kHz

SR

Slew rate⁽²⁾

V/μs

C_C= 10 nF, C_LOAD= 1 μF, R_C= 15 Ω

0.015

8

Settling time⁽²⁾⁽⁴⁾, 0.1%, small signal V_DRV= ±1 V

Overload recovery time 50% overdrive

(1) Output leakage includes input bias current of INA.

μs

12

(2) Refer to Driving Capacitive Loads and Loop Compensation section in Application and Implementation.

(3) Small signal with no capacitive load.

(4) 8 μs plus number of chopping periods. See Application and Implementation, Internal Current Sources, Switching Noise, and Settling

Time section.

5

XTR305

ZHCSHO6 –FEBRUARY 2018

www.ti.com.cn

6.6 Electrical Characteristics: Current Output Mode

All specifications at T_A= 25°C, V_S= ±20 V, R_LOAD= 800 Ω, R_SET= 2 kΩ, R_OS= 2 kΩ, V_REF= 4 V, input signal span 0 V to 4 V,

and C_C= 100 pF, unless otherwise noted.

PARAMETER

OFFSET VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OS

Input offset voltage

Output current < 1 μA

±0.4

±1.5

±0.2

±2.5

±10

mV

μV/°C

μV/V

dV_OS/dT

PSRR

Input offset voltage vs temperature

Input offset voltage vs power supply V_S= ±5 V to ±22 V

INPUT VOLTAGE RANGE

Nominal setup for ±20-mA output

See Figure 36

Maximum input voltage for linear

operation

(V−) + 3

(V+) − 3

V

NOISE

Voltage noise, f = 0.1Hz to 10Hz,

RTI

3

μV_PP

e_n

Voltage noise density, f = 1kHz, RTI

33

nV/√Hz

OUTPUT

Compliance voltage swing from rail

I_DRV= ±24 mA

(V−) +3

(V+) − 3

V

Output conductance (dI_DRV/dV_DRV

)

dV_DRV= ±15 V, dI_DRV= ±24 mA

See transfer function in Figure 36

I_DRV= ±24 mA

0.7

μA/V

Transconductance

Gain error

±0.04

±3.6

±0.2

±10

±0.2

±10

%FS

ppm/°C

%FS

Gain error vs temperature

Linearity error

I_DRV= ±24 mA

I_B

I_DRV= ±24 mA

±0.01

±1.5

Linearity error vs temperature

I_DRV= ±24 mA

ppm/°C

Output leakage current while output

disabled

OD pin = L

0.6

nA

I_SC

Short-circuit current

Capacitive load drive⁽¹⁾⁽²⁾

±24.5

±32

1

±38.5

mA

C_LOAD

μF

FREQUENCY RESPONSE

Bandwidth

Slew rate⁽²⁾

−3 dB

160

1.3

kHz

SR

mA/μs

Settling time⁽²⁾⁽³⁾, 0.1%, Small

Signal

I_DRV= ±2 mA

8

1

μs

Overload recovery time

C_LOAD= 0, 50% overdrive

(1) Refer to Driving Capacitive Loads and Loop Compensation section in Application and Implementation.

(2) With capacitive load, the slew rate can be limited by the short circuit current and the load error flag can trigger during slewing.

(3) 8 μs plus number of chopping periods. See Application and Implementation, Internal Current Sources, Switching Noise, and Settling

Time section.

6

XTR305

www.ti.com.cn

ZHCSHO6 –FEBRUARY 2018

6.7 Electrical Characteristics: Operational Amplifier (OPA)

All specifications at T_A= 25°C, V_S= ±20 V, and R_LOAD= 800 Ω, unless otherwise noted.

PARAMETER

OFFSET VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

±2.5

UNIT

V_OS

Offset voltage, RTI

I_DRV= 0 A

±0.4

±1.5

±0.2

mV

μV/°C

μV/V

dV_OS/dT

PSRR

Offset voltage drift

T_A= –40°C to 85°C

V_S= ±5 V to ±22 V

Offset voltage vs power supply

±10

INPUT VOLTAGE RANGE

V_CM

Common-mode voltage range

Common-mode rejection ratio

(V−) + 3

(V+) − 3

V

CMRR

(V−) + 3 V < V_CM< (V+) − 3 V

95

126

dB

INPUT BIAS CURRENT

I_B

Input bias current

Input offset current

±20

±35

±10

nA

I_OS

±0.3

INPUT IMPEDANCE

Differential

Common-mode

OPEN-LOOP GAIN

10⁸|| 5

Ω || pF

(V−) + 3 V < V_DRV< (V+) − 3 V,

I_DRV= ±24 mA

A_OL

Open-loop voltage gain

95

126

dB

OUTPUT

Voltage output swing from rail

Short-circuit current

I_DRV= ±24 mA

M2 = high

(V−) + 3

±25.5

±16

(V+) − 3

±38.5

±24

V

I_LIMIT

±32

±20

mA

M2 = low

Output leakage current while output

disabled

I_{LEAK_DRV}

OD pin = L

10

pA

FREQUENCY RESPONSE

GBW

SR

Gain-bandwidth product

Slew rate

G = 1

2

1

MHz

V/μs

7

XTR305

ZHCSHO6 –FEBRUARY 2018

www.ti.com.cn

6.8 Electrical Characteristics: Instrumentation Amplifier (IA)

All specifications at T_A= 25°C, V_S= ±20 V, R_IA= 2 kΩ, and R_GAIN= 2 kΩ, unless otherwise noted. See Figure 37.

PARAMETER

OFFSET VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OS

Offset voltage, RTI

I_DRV= 0 A

±0.7

±2.4

±0.8

±2.7

±10

mV

μV/°C

μV/V

dV_OS/dT

PSRR

Offset voltage vs temperature

Offset voltage vs power supply

T_A= –40°C to 85°C

V_S= ±5 V to ±22 V

INPUT VOLTAGE RANGE

V_CM

Input voltage range

Common-mode rejection ratio

(V−) + 3

(V+) − 3

V

CMRR

RTI

100

130

dB

INPUT BIAS CURRENT

I_B

Input bias current

Input offset current

±20

±1

±35

±10

nA

I_OS

INPUT IMPEDANCE

Differential

10⁵|| 5

Ω || pF

Common-mode

TRANSCONDUCTANCE (Gain)⁽¹⁾

IA_OUT= ±2.4 mA, (V−) + 3 V <

V_IAOUT< (V+) − 3 V

Transconductance error

±0.04

±0.2

±0.1

%FS

Transconductance error vs

temperature

T_A= –40°C to 85°C

ppm/°C

Linearity error

Input bias current to G1, G2

Input offset current to G1, G2⁽²⁾

OUTPUT

(V−) + 3 V < V_IAOUT< (V+) − 3 V

±0.01

±20

±1

%FS

nA

Output swing to the rail

Output impedance

IA_OUT= ±2.4 mA

M2 = High

(V−) + 3

(V+) − 3

V

600

±7.2

±4.5

mΩ

mA

I_LIMIT

Short-circuit current

M2 = Low

FREQUENCY RESPONSE

GBW

SR

Gain-bandwidth product

G = 1, R_GAIN= 10 kΩ, R_IA= 5 kΩ

1

MHz

Slew rate

V/μs

IA_OUT= ±40 μA, R_GAIN= 10 kΩ,

R_IA= 5 kΩ, C_L= 100 pF

Settling time⁽³⁾, 0.1%

6

μs

R_GAIN= 10 kΩ, R_IA= 15 kΩ,

C_L= 100 pF

Overload recovery time, 50%

10

(1) Use equation: IA_OUT= 2 (IA_IN+− IA_IN−) / R_GAIN

(2) See typical characteristics curve (Figure 3).

(3) 6 μs plus number of chopping periods. See Application and Implementation, Internal Current Sources, Switching Noise, and Settling

Time.

8

XTR305

www.ti.com.cn

ZHCSHO6 –FEBRUARY 2018

6.9 Electrical Characteristics: Current Monitor

All specifications at T_A= 25°C and V_S= ±20 V, unless otherwise noted. See Figure 37.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

I_OS

Offset current

I_DRV= 0 A

±30

±0.05

±0.1

±100

nA

nA/°C

nA/V

V

dI_OS/dT

PSRR

Offset current drift

T_A= –40°C to 85°C

V_S= ±5 V to ±22 V

I_MON= ±2.4 mA

Offset current vs power supply

Monitor output swing to the rail

Monitor output impedance

±10

(V−) + 3

(V+) − 3

I_MON= ±2.4 mA

200

MΩ

MONITOR CURRENT GAIN⁽¹⁾

Current gain error

I_DRV= ±24 mA

±0.04

±3.6

±0.12

±0.1

%FS

ppm/°C

%FS

Current gain error vs temperature

I_DRV= ±24 mA, T_A= –40°C to 85°C

I_DRV= ±24 mA

Linearity error

±0.01

±1.5

Linearity error vs temperature

I_DRV= ±24 mA, T_A= –40°C to 85°C

ppm/°C

(1) Use equation: I_MON= I_DRV/ 10

6.10 Electrical Characteristics: Power and Digital

All specifications at T_A= 25°C and V_S= ±20 V, unless otherwise noted. See Figure 37.

PARAMETER

POWER SUPPLY

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_S

Specified voltage range

Operating voltage range

Quiescent current

±5

±20

±22

2.3

2.8

V

I_Q

I_DRV= IA_OUT= 0 A

1.8

mA

Quiescent current over temperature T_A= –40°C to 85°C

THERMAL FLAG (EF_OT) OUTPUT

Alarm (EF_OTpin LOW)

140

125

°C

Return to normal operation (EF_OT

pin HIGH)

DIGITAL INPUTS (M1, M2, OD)

V_ILlow-level input voltage

V_IHhigh-level input voltage

Input current

≤ 0.8

> 1.4

±1

V

μA

DIGITAL OUTPUTS (EF_LD, EF_CM, EF_OT

)

I_OHhigh-level leakage current (open-

drain)

−1.2

μA

V_OLlow-level output voltage

I_OL= 5 mA

0.8

0.4

V

I_OL= 2.8 mA

DIGITAL GROUND PIN⁽¹⁾

M1 = M2 = L, OD = H, all digital

outputs H

Current input

−25

μA

(1) Use equation: (V−) ≤ DGND ≤ (V+) − 7 V

9

XTR305

ZHCSHO6 –FEBRUARY 2018

www.ti.com.cn

6.11 Typical Characteristics

at T_A= 25°C and V+ = ±20 V, unless otherwise noted

3.0

2.5

2.0

1.5

1.0

0.5

0

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

-50

-25

0

25

50

75

100

125

10

15

20

25

30

35

40

45

Temperature (°C)

Total Supply Voltage (V)

Figure 1. Quiescent Current vs Temperature

Figure 2. Quiescent Current vs Supply Voltage

0

2.2

2.0

1.8

1.6

1.4

1.2

1.0

I_DRV= +24mA

I_DRV= -24mA

-5

-10

-15

-20

-25

-30

I_DRV= +20mA

I_DRV= +10mA

I_DRV= -10mA

I_DRV= -20mA

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (°C)

(V_IN, SET, IA_IN+, IA_IN−, RG1, RG2)

Figure 3. Input Bias Current vs Temperature

Figure 4. OPA Output Swing to Rail vs Temperature

80

60

0

180

160

140

120

100

80

0

R_GAIN= 10kW

-20

-45

-40

R_IA= 500kW

R_IA= 50kW

-60

40

-90

Phase

-80

20

-135

-100

-120

-140

-160

-180

-200

R_IA= 10kW

60

0

-180

40

R_IA= 5kW

Gain

20

-20

-40

-225

R_IA= 1kW

Gain

Phase

0

-270

10M

-20

1

10

100

1k

10k

100k

1M

0.001 0.01 0.1

1

10 100 1k 10k 100k 1M 10M

Frequency (Hz)

Figure 6. IA Gain and Phase vs Frequency

Figure 5. OPA Gain and Phase vs Frequency

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Typical Characteristics (continued)

at T_A= 25°C and V+ = ±20 V, unless otherwise noted

160

140

120

100

80

140

120

PSRR+

CMRR

100

PSRR-

80

PSRR-

60

PSRR+

40

CMRR

20

0

1

10

100

1k

10k

100k

1

10

100

1k

10k

100k

Frequency (Hz)

Figure 7. OPA CMRR and PSRR vs Frequency

Figure 8. IA CMRR and PSRR vs Frequency

I_OUT= ±200mA

G = 8

I_OUT= ±20mA

G = 8

C_L= 100nF || R_L= 800W

C_C= 4.7nF

C_L= 100nF || R_L= 800W

C_C= 4.7nF

R_SET= 1kW

R_GAIN= 10kW

See Figure 3

R_GAIN= 10kW

See Figure 3

200ms/div

Figure 9. Small-Signal Step Response

Current Mode

Figure 10. Large-Signal Step Response

Current Mode

G = 5

C_L= 100nF || R_L= 800W

C_C= 4.7nF

C_L= 100nF || R_L= 800W

C_C= 4.7nF

R_SET= 1kW

R_GAIN= 10kW

See Figure 2

R_GAIN= 10kW

See Figure 2

200ms/div

Figure 11. Small-Signal Step Response

Voltage Mode

Figure 12. Large-Signal Step Response

Voltage Mode

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Typical Characteristics (continued)

at T_A= 25°C and V+ = ±20 V, unless otherwise noted

1M

G = 5

100k

10k

1k

100

10

1

1s/div

1

10

100

1k

10k

100k

Frequency (Hz)

Figure 13. Input-Referred Noise Spectrum

Voltage Output Mode

Figure 14. Input-Referred 0.1-Hz to 10-Hz Noise

Voltage Output Mode

1M

100k

10k

1k

G = 10

100

10

1

10

100

1k

10k

100k

1s/div

Frequency (Hz)

Figure 15. Input-Referred Noise Spectrum

Current Output Mode

Figure 16. Input-Referred 0.1-Hz to 10-Hz Noise

Current Output Mode

1M

100k

10k

1k

G = 20

100

10

1

1s/div

1

10

100

1k

10k

100k

Frequency (Hz)

Figure 18. IA Input-Referred 0.1-Hz to 10-Hz Noise

Figure 17. IA Input-Referred Noise Spectrum

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Typical Characteristics (continued)

at T_A= 25°C and V+ = ±20 V, unless otherwise noted

18

30

25

20

15

10

5

16

14

12

10

8

6

4

2

0

Offset Voltage (mV)

Figure 19. OPA Offset Voltage Distribution

Figure 20. IA Offset Voltage Distribution

60

40

35

30

25

20

15

10

5

50

40

30

20

10

0

Offset Voltage Drift (mV/°C)

Figure 21. OPA Offset Voltage Drift Distribution

Figure 22. IA Offset Voltage Drift Distribution

40

30

25

20

15

10

5

35

30

25

20

15

10

5

0

Gain Error (ppm)

Figure 24. Current Mode Gain Error Distribution

Figure 23. Voltage Mode Gain Error Distribution

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Typical Characteristics (continued)

at T_A= 25°C and V+ = ±20 V, unless otherwise noted

60

50

40

30

20

10

0

50

40

30

20

10

0

Nonlinearity (ppm)

Figure 26. Current Mode Nonlinearity Distribution

Figure 25. Voltage Mode Nonlinearity Distribution

70

60

50

40

30

20

10

0

60

50

40

30

20

10

0

Gain Error Drift (ppm/°C)

Figure 28. Current Mode Gain Error Drift Distribution

Figure 27. Voltage Mode Gain Error Drift Distribution

80

100

90

80

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

Nonlinearity Drift (ppm/°C)

Figure 30. Current Mode Nonlinearity Drift Distribution

Figure 29. Voltage Mode Nonlinearity Drift Distribution

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Typical Characteristics (continued)

at T_A= 25°C and V+ = ±20 V, unless otherwise noted

36

-16

-18

-20

-22

-24

-26

-28

-30

-32

-34

-36

34

Voltage Mode

32

Current Mode

30

28

26

24

Voltage Mode

22

20

18

16

Current Mode

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (°C)

Figure 31. Positive Current Limit vs Temperature

Figure 32. Negative Current Limit vs Temperature

0.025

-55°C

+25°C

-55°C

0

-0.025

-0.050

-0.075

-0.100

-0.025

-0.050

-0.075

-0.100

+85°C

+125°C

+85°C

+125°C

-24 -20 -16 -12 -8 -4

0

4

8

12 16 20 24

-24 -20 -16 -12 -8 -4

0

4

8

12 16 20 24

Output Current (mA)

(±24-mA End Point Calibration)

Figure 33. Nonlinearity vs Output Current

(±20-mA End Point Calibration)

Figure 34. Nonlinearity vs Output Current

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7 Detailed Description

7.1 Overview

Built on a robust high-voltage BiCMOS process, the XTR305 is designed to interface the 5-V or 3-V supply

domain used for processors, signal converters, and amplifiers to the high-voltage and high-current industrial

signal environment. The device is specified for up to ±20-V supply, but can also be powered asymmetrically (for

example, +24 V and −5 V). It is designed to allow insertion of external circuit protection elements and drive large

capacitive loads.

7.2 Functional Block Diagrams

C_C

V-

V+

XTR305

I_MON

Current Copy

R_IMON

1 kΩ

I_COPY

I_DRV

Input Signal

V_IN= 0 V to 4.0 V

GND3

V_IN

DRV

IA_IN+

OPA

SET

Transfer Function:

R_OS

R_SET

I_IA

R_GAIN

V_IN

V_IN- V_REF

R_OS

RG₁

RG₂

V_OUT

=

+

(

)

R_GAIN

Load

IA

2

R_SET

V_REF= 4.0 V

IA_IN-

IA_OUT

OD

EF_CM

EF_LD

EF_OT

H

L

M1

M2

Digital

Error

Control

Flags

DGND

DV_GND

GND2

GND1

Figure 35. Standard Circuit for Voltage Output Mode

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Functional Block Diagrams (continued)

C_C

V-

Current Copy

I_COPY

V+

XTR305

I_MON

I_DRV

Input Signal

V_IN= 0 V to 4.0 V

V_IN

DRV

IA_IN+

OPA

SET

Transfer Function:

V_IN

V_IN- V_REF

R_OS

I_OUT= 10

+

R_OS

R_SET

(

I_IA

R_SET

RG₁

RG₂

IA

V_REF= 4.0 V

IA_IN-

IA_OUT

I_OUT

EF_CM

EF_LD

EF_OT

OD

M1

M2

H

Digital

Control

Error

L

H

Flags

DGND

GND1

GND2

Figure 36. Standard Circuit for Current Output Mode

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Functional Block Diagrams (continued)

Feedback

Network

V-

Current Copy

I_COPY

V+

XTR305

I_MON

I_DRV

GND3

V_IN

DRV

IA_IN+

Input Signal

OPA

SET

R_SET

I_IA

RG₁

RG₂

R_GAIN

IA

GND1

IA_IN-

IA_OUT

OD

EF_CM

EF_LD

EF_OT

R_IA

H

M1

M2

Digital

Control

Error

Flags

DGND

GND3

Figure 37. Standard Circuit for Externally Configured Mode

7.3 Feature Description

7.3.1 Functional Features

The XTR305 provides two basic functional blocks: an instrumentation amplifier (IA) and a driver that is a unique

operational amplifier (OPA) for current or voltage output. This combination represents an analog output stage

which can be digitally configured to provide either current or voltage output to the same terminal pin.

Alternatively, it can be configured for independent measurement channels.

Three open collector error signals are provided to indicate output related errors such as overcurrent or open-load

(EF_LD) or exceeding the common-mode input range at the IA inputs (EF_CM). An overtemperature flag (EF_OT) can

be used to control output disable to protect the circuit. The monitor outputs (I_MONand IA_OUT) and the error flags

offer optimal testability during operation and configuration. The I_MONoutput represents the current flowing into the

load in voltage output mode, while the IA_OUTrepresents the voltage across the connectors in current output

mode. Both monitor outputs can be connected together when used in current or voltage output mode because

the monitor signals are multiplexed accordingly.

7.3.2 Current Monitor

In current output mode (M2 = high), the XTR305 provides high output impedance. A precision current mirror

generates an exact 1/10th copy of the output current and this current is either routed to the summing junction of

the OPA to close the feedback loop (in the current output mode) or to the I_MONpin for output current monitoring in

other operating modes.

The high accuracy and stability of this current split results from a cycling chopper technique. This design

eliminates the need for a precise shunt resistor or a precise shunt voltage measurement, which would require

high common-mode rejection performance.

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Feature Description (continued)

During a saturation condition of the DRV output (the error flag is active), the monitor output (I_MON) shows a

current peak because the loop opens. Glitches from the current mirror chopper appear during this time in the

monitor signal. This part of the signal cannot be used for measurement.

7.3.3 Error Flags

The XTR305 is designed for testability of its proper function and allows observation of the conditions at the load

connection without disrupting service.

If the output signal is not in accordance to the transfer function, an error flag is activated (limited by the dynamic

response capabilities). These error flags are in addition to the monitor outputs, I_MONand IA_OUT, which allow the

momentary output current (in voltage mode) or output voltage (in current mode) to be read back.

This combination of error flag and monitor signal allows easy observation of the XTR305 for function and working

condition, providing the basis for not only remote control, but also for remote diagnosis.

All error flags of the XTR305 have open collector outputs with a weak pullup of approximately 1 μA to an internal

5 V. External pullup resistors to the logic voltage are required when driving 3-V or 5-V logic.

The output sink current should not exceed 5 mA. This is just enough to directly drive optical-couplers, but a

current-limiting resistor is required.

There are three error flags:

1. IA Common-Mode Over Range (EF_CM): goes low as soon as the inputs of the IA reach the limits of the

linear operation for the input voltage. This flag shows noise from the saturated current mirrors which can be

filtered with a capacitor to GND.

2. Load Error (EF_LD): indicates fault conditions driving voltage or current into the load. In voltage output mode

it monitors the voltage limits of the output swing and the current limit condition caused from short or low load

resistance. In current output mode it indicates a saturation into the supply rails from a high load resistance or

open load.

3. Overtemperature Flag (EF_OT): a digital output that goes low if the chip temperature reaches a temperature

of 140°C and resets as soon as it cools down to 125°C. It does not automatically shut down the output; it

allows the user system to take action on the situation. If desired, this output can be connected to output

disable (OD) which disables the output and therefore removes the source of power. This connection acts like

an automatic shut down, but requires a 2.2-kΩ external pullup resistor to safely override the internal current

sources. The IA channel is not affected, which allows continuous observation of the voltage at the output.

7.3.4 Power On/Off Glitch

When power is turned on or off, most analog amplifiers generate some glitching of the output because of internal

circuit thresholds and capacitive charges. Characteristics of the supply voltage, as well as its rise and fall time,

directly influence output glitches. Load resistance and capacitive load also affect the amplitude.

The output disable control (OD) cannot fully suppress glitches during power-on and power-off, but reduces the

energy significantly. The glitch consists of a small amount of current and capacitive charge (voltage) that reacts

with the resistive and capacitive load. The bias current of the IA inputs that are normally connected to the output

also generate a voltage across the load.

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Feature Description (continued)

Figure 38 indicates no glitches when transitioning between disable and enable. This measurement is made with

a load resistance of 1 kΩ and tested in the circuit configuration of Figure 40.

Output

0.5V/div

OD

2.0V/div

Time (10ms/div)

Figure 38. Output Signal During Toggle of OD

When the power is off or with low supply, the output is diode clamped to the momentary supply voltage, but can

float while output disabled within those limits unless terminated. Only an external switch (relays or opto-relays)

can isolate the output under such conditions. Refer to Figure 39 for an illustration of this configuration. The same

consideration applies if low impedance zero output is required, even during power off.

C_C

V_{EN_OPTO}

47 nF

0 V to 5 V

R_LED

5 kW

XTR305

R_C

15 W

CPC1017N

+

S_OUT

DRV

4

3

1

2

OPA

œ

C₄

100 nF

I_LED

0 mA to 1

mA

R₆

2.2 kW

IA_IN+

RG₁

+

R_GAIN

10 kW

C₅

10 nF

IA

R₇

2.2 kW

RG₂

IA_INœ

œ

R_LOAD

1 kW

Figure 39. Example for Opto-Relay Output Isolation

7.4 Device Functional Modes

The XTR305 has a three functional modes: voltage output mode as shown in Figure 35, current output mode as

shown in Figure 36, and externally configured mode as shown in Figure 37.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The following sections provide details regarding the typical application of the XTR305 using three different

functional modes: voltage output mode as shown in Figure 35, current output mode as shown in Figure 36, and

externally configured mode as shown in Figure 37.

8.2 Typical Application

V-

GND

V+

C₂

100 nF

C₃

100 nF

C_C

47 nF

GND1

Thermal

Pad⁽²⁾

V-

V+

XTR305

I_MON

Current Copy

I_COPY

I_MON

R₃

I_DRV

1 kΩ

V_IN

R_C

External Load

S_IN

OS

15 Ω

DRV

R_OS

OPA

2 kΩ

C₄

SET

100 nF R₆

2.2 kΩ

IA_IN+

RG₁

RG₂

GND1

R_IMON

1 kΩ

R_SET

2 kΩ

C_LOAD

R_LOAD

I_IA

R_GAIN

10 kΩ

C₅

SG

IA

R₇

10 nF

GND1

2.2 kΩ

IA_O

IA_IN-

IA_OUT

OD

GND2

EF_CM

EF_LD

EF_OT

R_IA

Logic Supply

M1

M2

Digital

Error

1 kΩ

(+2.7 V to +5 V)

Control

Flags

(1)

DGND

GND3

Pull-up Resistors

(10 kΩ)

GND4

(1) See the Electrical Characteristics: Power and Digital and Digital I/O and Ground Considerations section for operating

limits of DGND.

(2) Connect thermal pad to V−.

Figure 40. Standard Circuit Configuration

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8.2.1 Design Requirements

Consider the following information during XTR305 circuit configuration:

•

Recommended bypassing: 100 nF or more for supply bypassing at each supply.

R_IMONcan be in the kΩ range or short-circuited if not used. Do not leave this current output unconnected — it

would saturate the internal current source. The current at this I_MONoutput is I_DRV/ 10. Therefore, V_IMON

R_IMON(I_DRV/1 0).

=

•

R₃is not required but can match R_SET(or R_SET||R_OS) to compensate for the bias current.

R_IAcan be short-circuited if not used. Do not leave this current output unconnected. R_GAINis selected to 10

kΩ to match the output of 10 V with 20 mA for the equal input signal.

•

R_Censures stability for unknown load conditions and limits the current into the internal protection diodes. C₄

helps protect the device. Overvoltage clamp diodes (standard 1N4002) might be necessary to protect the

output.

•

R₆, R₇, and C₅protect the IA.

R_LOADand C_LOADrepresent the load resistance and load capacitance.

R_SETdefines the transfer gain. It can be split to allow a signal offset and, therefore, allow a 5-V single-supply

digital-to-analog converter (DAC) to control a ±10-V or ±20-mA output signal.

The XTR305 can be used with asymmetric supply voltages; however, the minimum negative supply voltage must

be equal to or more negative than −3 V (typically −5 V). This supply value ensures proper control of 0 V and 0

mA with wire resistance, ground offsets, and noise added to the output. For positive output signals, the current

requirement from this negative voltage source is less than 5 mA.

GND1 through GND4 must be selected to fulfill specified operating ranges. DGND must be in the range of (V−) ≤

DGND ≤ (V+) −7 V.

8.2.2 Detailed Design Procedure

8.2.2.1 Voltage Output Mode

In voltage output mode (M1 and M2 are connected low or left unconnected), the feedback loop through the IA

provides high impedance remote sensing of the voltage at the destination, compensating the resistance of a

protection circuit, switches, wiring, and connector resistance. The output of the IA is a current that is proportional

to the input voltage. This current is internally routed to the OPA summing junction through a multiplexer, as

shown in Figure 41.

A 1:10 copy of the output current of the OPA can be monitored at the I_MONpin. This output current and the

known output voltage can be used to calculate the load resistance or load power.

During an output short-circuit or an overcurrent condition the XTR305 output current is limited and EF_LD(load

error, active low) flag is activated.

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C_C

V-

Current Copy

I_COPY

V+

XTR305

I_MON

R_IMON

GND3

I_DRV

Input Signal

V_IN

DRV

IA_IN+

OPA

SET

R_SET

I_IA

RG₁

RG₂

R_GAIN

Load

IA

GND1

IA_IN-

IA_OUT

OD

EF_CM

EF_LD

EF_OT

GND2

M1

M2

Digital

Error

L

Control

Flags

L

DGND

Figure 41. Simplified Voltage Output Mode Configuration

Applications not requiring the remote sense feature can use the OPA in stand-alone operation (M1 = high). In

this case, the IA is available as a separate input channel.

The IA gain can be set by two resistors, R_GAINand R_SET(Equation 1):

R_GAIN

V_OUT

=

V_IN

2R_SET

(1)

or when adding an offset, V_REF, to get bidirectional output with a single-ended input shown in Equation 2:

V_IN

V

_IN- V_REF

R_GAIN

2

+

V_OUT

=

(

R_SET

R_OS

(2)

The R_SETresistor is also used in current output mode. Therefore, it is useful to define R_SETfor the current mode,

then set the ratio between current and voltage span with R_GAIN

.

8.2.2.2 Current Output Mode

The XTR305 does not require a shunt resistor for current control because it uses a precise current mirror

arrangement.

In current output mode (M1 connected low, or left unconnected and M2 connected high), a precise copy of 1/10th

of the output is internally routed back to the summing junction of the OPA through a multiplexer, closing the

control loop for the output current.

The OPA driver can deliver more than ±24 mA within a wide output voltage range. An open-output condition or

high-impedance load that prevents the flow of the required current activates the EF_LDflag and the IA can become

overloaded and draw greater than 7-mA saturation current.

While in current output mode, a current (I_IA) that is proportional to the voltage at the IA input is routed to IA_OUT

and can be used to monitor the load voltage. A resistor converts this current into voltage. This arrangement

makes level shifting easy.

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Alternatively, the IA can be used as an independent monitoring channel. If this output is not used, connect it to

GND to maintain proper function of the monitor stage, as shown in Figure 42.

V-

V+

XTR305

I_MON

Current Copy

I_COPY

I_DRV

Input Signal

V_IN

DRV

IA_IN+

OPA

SET

R_SET

I_IA

RG₁

RG₂

R_GAIN

Load

IA

GND1

IA_IN-

IA_OUT

OD

GND2

EF_CM

EF_LD

EF_OT

R_IA

M1

M2

Digital

Error

L

Control

Flags

H

DGND

GND3

Figure 42. Simplified Current Output Mode Configuration

The transconductance (gain) can be set by the resistor, R_SET, according to Equation 3:

10

I_OUT

=

V_IN

R_SET

(3)

(4)

or when adding an offset V_REFto get bidirectional output with a single-ended input shown in Equation 4:

V_IN

V_IN- V_REF

+

I_OUT= 10

(

R_SET

R_OS

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8.2.2.3 Input Signal Connection

It is possible to drive the XTR305 with a unidirectional input signal and still get a bidirectional output by adding an

additional resistor, R_OS, and an offset voltage signal, V_REF. It can be a mid-point voltage or a signal to shift the

output voltage to a desired value.

This design is illustrated in Figure 43a, Figure 43b, and Figure 43c. As with a normal operational amplifier, there

are several options for offset-shift circuits. The input can be connected for inverting or noninverting gain. Unlike

many op amp input circuits, however, this configuration uses current feedback, which removes the voltage

relationship between the noninverting input and output potential because there is no feedback resistor.

a) Noninverting Input

XTR305

V_IN

(0 to V_OFFSET

)

OPA

V_REF

R_OS

R_SET

2 kΩ

I_Feedback

b) Noninverting Input

XTR305

V_IN

( V_MIDSCALE

)

OPA

V_MIDSCALE

R_SET

1 kΩ

I_Feedback

c) Inverting Input (V_REF= V_OFFSET

)

XTR305

V_OFFSET

OPA

V_IN

( V_OFFSET

)

R_SET

1 kΩ

I_Feedback

Figure 43. Circuit Options for Op Amp Output Level Shifting

The input bias current effect on the offset voltage can be reduced by connecting a resistor in series with the

positive input that matches the approximate resistance at the negative input. This resistor placed close to the

input pin acts as a damping element and makes the design less sensitive to RF noise. See R₃in Figure 40.

8.2.2.4 Externally-Configured Mode: OPA and IA

It is possible to use the precision of the operational amplifier (OPA) and instrumentation amplifier (IA)

independently from each other by configuring the digital control pins (M1 high). In this mode, the IA output

current is routed to IA_OUTand the copy of the OPA output current is routed to I_MON, as shown in Figure 37.

This mode allows external configuration of the analog signal routing and feedback loop.

The current output IA has high input impedance, low offset voltage and drift, and very high common-mode

rejection ratio. An external resistor (R_IA) can be used to convert the output current of the IA (I_IA) to an output

voltage. The gain is given by Equation 5:

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2

2R_IA

I_IA=

V_INor V_IA=

V_IN

R_GAIN

(5)

The OPA provides low drift and high voltage output swing that can be used like a common operational amplifier

by connecting a feedback network around it. In this mode, the copy of the output current is available at the I_MON

pin (it includes the current into the feedback network). It provides an output current limit for protection, which can

be set between two ranges by M2. The error flag indicates an overcurrent condition, as well as indicating driving

the output into the supply rails.

Alternatively, the feedback can be closed through the I_MONpin to create a precise voltage-to-current converter.

8.2.2.5 Driver Output Disable

The OPA output (DRV) can be switched to a high-impedance mode by driving the OD control pin low. This input

can be connected to the overtemperature flag, EF_OT, and a pullup resistor to protect the IC from over-

temperature by disconnecting the load.

The output disable mode can be used to sense and measure the voltage at the IA input pins without loading from

the DRV output. This mode allows testing of any voltage present at the I/O connector. However, consider the

bias current of the IA input pins.

The digital control inputs, M1 and M2, set the four operation modes of the XTR305 as shown in Table 1. When

M1 is asserted low, M2 determines voltage or current mode and the corresponding appropriate current limit (I_SC

)

setting. When M1 is high, the internal feedback connections are opened; IA_OUTand I_MONare both connected to

the output pins; and M2 only determines the current limit (I_SC) setting.

M1 and M2 are pulled low internally with 1 μA. Terminate these two pins to avoid noise coupling. Output disable

(OD) is internally pulled high with approximately 1 μA. When connecting OD to EF_OT, a 2.2-kΩ pullup resistor is

recommended.

Table 1. Summary of Configuration Modes⁽¹⁾

M1

L

M2

L

MODE

V_OUT

I_OUT

DESCRIPTION

Voltage output mode, I_SC= 20 mA

Current output mode, I_SC= 32 mA

IA and I_MONon external pins, I_SC= 20 A

L

H

L

Ext

IA and I_MONon external pins, I_SC= 32

mA

H

Ext

(1) OD is a control pin independent of M1 or M2.

8.2.2.6 Driving Capacitive Loads and Loop Compensation

For normal operation, the driver OPA and the IA are connected in a closed loop for voltage output. In current

output mode, the current copy closes the loop directly.

In current output mode, loop compensation is not critical, even for large capacitive loads. However, in voltage

output mode, the capacitive load, together with the source impedance and the impedance of the protection

circuit, generates additional phase lag. The IA input might also be protected by a low-pass filter that influences

phase in the closed loop.

The loop compensation low-pass filter consists of C_Cand the parallel resistance of R_OSand R_SET. For loop

stability with large capacitive load, the external phase shift has to be added to the OPA phase. With C_C, the

voltage gain of the OPA has to approach zero at the frequency where the total phase approaches 180° + 135°.

The best stability for large capacitive loads is provided by adding a small resistor, R_C(15 Ω). See the Output

Protection section.

An empirical method of evaluation is using a square wave input signal and observing the settling after transients.

Use small signal amplitudes only—steep signal edges cause excessive current to flow into the capacitive load

and may activate the current limit, which hides or prevents oscillation. A small-signal oscillation can be hidden

from large capacitive loads, but observing the I_MONoutput on an appropriate resistor (use a similar value like

R_SET||R_OS) would indicate stability issues. Note that noise pulses at I_MONduring overload (EF_LDactive) are normal

and are caused by cycling of the current mirror.

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The voltage output mode includes the IA in the loop. An additional low-pass filter in the input reverses the phase

and therefore increases the signal bandwidth of the loop, but also increases the delay. Again, loop stability has to

be observed. Overloading the IA disconnects the closed loop and the output voltage rails.

8.2.2.7 Internal Current Sources, Switching Noise, and Settling Time

The accuracy of the current output mode and the DC performance of the IA rely on dynamically-matched current

mirrors.

Identical current sources are rotated to average out mismatch errors. It can take several clock cycles of the

internal 100-kHz oscillator (or a submultiple of that frequency) to reach full accuracy. This may dominate the

settling time to the 0.1% accuracy level and can be as much as 100 μs in current output mode or 40 μs in voltage

output mode.

A small portion of the switching glitches appear at the DRV output, and also at the I_MONand IA_MONoutputs. The

standard circuit configuration, with R_C, C₄, and C_C, which are required for loop compensation and output

protection, also helps reduce the noise to negligible levels at the signal output. If necessary, the monitor outputs

can be filtered with a shunt capacitor.

8.2.2.8 IA Structure, Voltage Monitor

The instrumentation amplifier has high-impedance NPN transistor inputs that do not load the output signal, which

is especially important in current output mode. The output signal is a controlled current that is multiplexed either

to the SET pin (to close the voltage output loop) or to IA_OUT(for external access).

The principal circuit is shown in Figure 44. The two input buffer amplifiers reproduce the input difference voltage

across R_GAIN. The resulting current through this resistor is bidirectionally mirrored to the output. That mirroring

results in the transfer function of Equation 6:

(IA_IN+– IA_IN-

)

I_IA= IA_OUT= 2

R_GAIN

(6)

The accuracy and drift of R_GAINdefines the accuracy of the voltage to current conversion. The high accuracy and

stability of the current mirrors result from a cycling chopper technique.

Current Mirror

I_R

IA_IN+

A1

Current Mirror

I_R

R_GAIN

I_R

2I_R

I_IA

A2

IA_IN-

2I_R

Current Mirror

Figure 44. IA Block Diagram

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www.ti.com.cn

The output current, IA_OUT, of the instrumentation amplifier is limited to protect the internal circuitry. This current

limit has two settings controlled by the state of M2 (see Electrical Characteristics: Instrumentation Amplifier (IA),

Short-Circuit Current specification).

NOTE

If R_SETis too small, the current output limitation of the instrumentation amplifier can disrupt

the closed loop of the XTR305 in voltage output mode.

With M2 = low, the nominal R_GAINof 10 kΩ allows an input voltage of 20 V_PP, which produces an output current

of 4 mA_PP. When using lower resistors for R_GAINthat can allow higher currents, the IA output current limitation

must be taken into account.

8.2.2.9 Digital I/O and Ground Considerations

The XTR305 offers voltage output mode, current output mode, external configuration, and instrumentation mode

(voltage input). In addition, the internal feedback mode can be disconnected and external loop connections can

be made. These modes are controlled by M1 and M2 (see Table 1). The OD input pin controls enable or disable

of the output stage (OD is active low).

The digital I/O is referenced to DGND and signals on this pin must remain within 5 V of the DGND potential. This

DGND pin carries the output low-current (sink current) of the logic outputs. DGND can be connected to a

potential within the supply voltage but needs to be 8 V below the positive supply. Proper connection avoids

current from the digital outputs flowing into the analog ground.

CAUTION

The DGND has normally reverse-biased diodes connected to the supply. Therefore,

high and destructive currents could flow if DGND is driven beyond the supply rails by

more than a diode forward voltage. Avoid this condition during power on and power off.

8.2.2.10 Output Protection

The XTR305 is intended to operate in a harsh industrial environment. Therefore, a robust semiconductor process

was chosen for this design. However, some external protection is still required.

The instrumentation amplifier inputs can be protected by external resistors that limit current into the protection

cell behind the IC pins, as shown in Figure 45. This cell conducts to the power-supply connection through a

diode as soon as the input voltage exceeds the supply voltage. The circuit configuration example shows how to

arrange these two external resistors.

The bias current is best cancelled if both resistors are equal. The additional capacitor reduces RF noise in the

input signal to the IA.

R₆

2.2 kΩ

IA_IN+

RG₁

V_SENSE+

C₅

10 nF

IA

R_GAIN

R₇

RG₂

IA_IN-

2.2 kΩ

V_SENSE-

Figure 45. Current-Limiting Resistors

The load connection to the DRV output must be low impedance; therefore, external protection diodes may be

necessary to handle excessive currents, as shown in Figure 46. The internal protection diodes start to conduct

earlier than a normal external PN-type diode because they are affected by the higher die temperature. Therefore,

either Schottky diodes are required, or an additional resistor (R_C) can be placed in series with the input. An

example of this protection is shown in Figure 46. Assuming the standard diodes limit the voltage to 1.4 V and the

internal diodes clamp at 0.7 V, this resistor can limit the current into the internal protection diodes to 50 mA

shown in Equation 7:

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XTR305

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(1.4V – 0.7V)

15W

= 47mA

(7)

R_Cis also part of the recommended loop compensation. C₄helps protect the output against RFI and high-voltage

spikes.

C_C

V+

47 nF

D

XTR305

1N4002

R_C

15 Ω

DRV

I/V OUT

OPA

D

C₄

100 nF

1N4002

V-

Figure 46. Example for DRV Output Protection

8.2.3 Application Curves

The nonlinearity of the XTR305 when operating in current output mode is shown in Figure 47 and Figure 48.

V-

V+

0.025

0

+25°C

-55°C

L₁

L₂

10 µH

-0.025

-0.050

-0.075

-0.100

C_B1

+85°C

100 nF

C_B2

100 nF

C_B3

1 µF

+125°C

C_B4

1 µF

-24 -20 -16 -12 -8 -4

0

4

8

12 16 20 24

Output Current (mA)

(±24-mA End Point Calibration)

V-

V+

XTR305

(±20-mA End Point Calibration)

Figure 48. Nonlinearity vs Output Current

Figure 47. Nonlinearity vs Output Current

9 Power Supply Recommendations

Built on a robust high-voltage BiCMOS process, the XTR305 is designed to interface the 5-V or 3-V supply

domain used for processors, signal converters, and amplifiers to the high-voltage and high-current industrial

signal environment. The device is specified for up to ±20-V supply, but can also be powered asymmetrically (for

example, +24 V and −5 V). XTR305 is designed to allow insertion of external circuit protection elements and

drive large capacitive loads.

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10 Layout

10.1 Layout Guidelines

Supply bypass capacitors must be close to the package and connected with low-impedance conductors. Avoid

noise coupled into R_GAIN, and observe wiring resistance. For thermal management, see the VQFN Package and

Heat Sinking section.

Layout for the XTR305 is not critical; however, its internal current chopping works best with good (low dynamic

impedance) supply decoupling. Therefore, avoid through-hole contacts in the connection to the bypass

capacitors or use multiple through-hole contacts. Switching noise from power supplies should be filtered enough

to reduce influence on the circuit. Small resistors (2-Ω, for example) or damping inductors in series with the

supply connection (between the DC-DC converter and the XTR circuit) act as a decoupling filter together with the

bypass capacitor as shown in Figure 49.

Resistors connected close to the input pins help dampen environmental noise coupled into conductor traces.

Therefore, place the OPA input- and IA input-related resistors close to the package. Also, avoid additional wire

resistance in series to R_SET, R_OS, and R_GAIN(observe the reliability of the through-hole contacts), because this

resistance could produce gain and offset error as well as drift; 1 Ω is already 0.1% of the 1-kΩ resistor.

The exposed lead-frame die pad on the bottom of the package must be connected to V−, pin 11 (see the VQFN

Package and Heat Sinking section for more details).

V-

V+

L₁

L₂

10 µH

C_B1

100 nF

C_B2

100 nF

C_B3

1 µF

C_B4

1 µF

V-

V+

XTR305

Figure 49. Suggested Supply Decoupling for Noisy Chopper-Type Supplies

10.2 Layout Example

A detailed layout example can be found in the technical document XTR300EVM. This document is available for

download at www.ti.com. The example layout is also shown in Figure 50.

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XTR305

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Layout Example (continued)

Figure 50. Layout Example

10.3 VQFN Package and Heat Sinking

The XTR305 is available in a VQFN package. This leadless, near-chip-scale package maximizes board space

and enhances thermal and electrical characteristics of the device through an exposed thermal pad.

Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but

printed circuit board (PCB) layout greatly influences overall heat dissipation. The thermal resistance from

junction-to-ambient (θ_JA) is specified for the packages with the exposed thermal pad soldered to a normalized

PCB, as described in the technical brief PowerPAD™ Thermally-Enhanced Package. See also EIA/JEDEC

Specifications JESD51-0 to 7, VQFN/SON PCB Attachment, and Quad Flatpack No-Lead Logic Packages.

These documents are available for download at www.ti.com.

NOTE

All thermal models have an accuracy variation of ±20%.

Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load

conditions should be tested in the real environment to ensure proper thermal conditions. Minimize thermal stress

for proper long-term operation with a junction temperature well below +125°C.

The exposed lead-frame die pad on the bottom of the package must be connected to the V− pin.

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www.ti.com.cn

10.4 Power Dissipation

Power dissipation depends on power supply, signal, and load conditions. It is dominated by the power dissipation

of the output transistors of the OPA. For DC signals, power dissipation is equal to the product of output current,

I_OUTand the output voltage across the conducting output transistor (V_S– V_OUT).

It is very important to note that the temperature protection does not shut the device down in overtemperature

conditions, unless the EF_OTpin is connected to the output enable pin OD; see the Driver Output Disable section.

The power that can be safely dissipated in the package is related to the ambient temperature and the heat sink

design and conditions. The VQFN package with an exposed thermal pad is specifically designed to provide

excellent power dissipation, but board layout greatly influences the heat dissipation.

To appropriately determine the required heat sink area, calculate required power dissipation; also consider the

relationship between power dissipation and thermal resistance to minimize overheat conditions and allow for

reliable long-term operation.

The heat-sinking efficiency can be tested using the EF_OToutput signal. This output goes low at nominally 140°C

junction temperature (assume 6% tolerance). With full power dissipation (for example, maximum current into a 0-

Ω load), the ambient temperature can be slowly raised until the OT flag goes low. This flag would indicate the

minimum heat sinking for the usable operation condition.

The recommended landing pattern for the VQFN package is shown at the end of this data sheet.

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11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

如需相关文档，请参阅：

•

《PowerPAD™ 散热增强型封装》

EIA/JEDEC 规范 JESD51-0 至 7、《VQFN/SON PCB 连接》

《四方扁平无引线逻辑器件封装》

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收

产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，也

不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

33

GENERIC PACKAGE VIEW

RGW 20

5 x 5, 0.65 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4227157/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

5.1

4.9

B

PIN 1 INDEX AREA

5.1

4.9

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

3.15±0.1

2X 2.6

(0.1) TYP

10

6

16X 0.65

5

11

SYMM

21

2X

2.6

15

1

0.36

0.26

20X

PIN1 ID

(OPTIONAL)

0.1

C A B

C

20

16

0.05

SYMM

0.65

0.45

20X

4219039/A 06/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

(4.65)

3.15)

(2.6)

(

20

16

16X (0.65)

15

1

(1.325)

21

SYMM

(4.65) (2.6)

(R0.05) TYP

11

5

20X (0.31)

20X (0.75)

(Ø0.2) VIA

6

10

TYP

(1.325)

SYMM

LAND PATTERN EXAMPLE

SCALE: 15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

EXPOSED METAL

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219039/A 06/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

(4.65)

4X ( 1.37)

2X (0.785)

16

20

16X (0.65)

21

1

15

2X (0.785)

SYMM

(4.65) (2.6)

(R0.05) TYP

11

5

20X (0.31)

20X (0.75)

METAL

TYP

6

10

SYMM

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED COVERAGE BY AREA

SCALE: 15X

4219039/A 06/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	XTR305IRGWR
厂家：	TEXAS INSTRUMENTS
描述：	工业模拟电流/电压输出驱动器 \| RGW \| 20 \| -55 to 125 驱动驱动器
文件：	总40页 (文件大小：2156K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XTR305IRGWR [TI]

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