T15L256A [TMT]
32K X 8 LOW POWER CMOS STATIC RAM; 32K ×8低功耗CMOS静态RAM
| 型号： | T15L256A |
| 厂家： | 
TAIWAN MEMORY TECHNOLOGY |
| 描述： | 32K X 8 LOW POWER CMOS STATIC RAM |
| 文件： | 总10页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TE
CH
T15L256A
32K X 8 LOW POWER
CMOS STATIC RAM
SRAM
FEATURES
GENERAL DESCRIPTION
·
The T15L256A is a high speed, low power
CMOS static RAM organized as 32,768 x 8 bits that
operates on a single 3.3-volt power supply. This
device is packaged in standard 28-pin 300 mil SOJ ,
28-pin SOP, TSOP-I forward.
Access time: 35ns/70ns
· Low power consumption : Active 200 mW(typ.)
·
·
·
Low operating current : 50mA
Single + 3.3V power supply
Fully static operation – No clock or refreshing
required
BLOCK DIAGRAM
·
·
·
All inputs and outputs directly LVTTL compatible
Common I/O capability
Vcc ®
Vss®
A0®
Available packages : 28-pin 300 mil SOJ, 28-pin
SOP, TSOP-I (forward type ).
.
.
CORE
ARRAY
DECODER
CONTROL
·
OE
Output enable (
) available for very fast access
.
A14 ®
CS ®
OE ®
WE ®
PIN CONFIGURATION
¬ I / O1
.
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
A13
A8
DATA I/O
.
2
¬
I / O8
3
A6
4
A5
5
A9
SOJ
&
SOP
A4
6
A11
OE
PIN DESCRIPTION
A3
7
A2
8
A10
CS
SYMBOL
A0 - A14
I/O1 - I/O8
CS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable
A1
9
A0
10
11
12
13
14
I/O8
I/O7
I/O6
I/O5
I/O4
I/O1
I/O2
I/O3
Vss
WE
Output Enable
Power Supply
Ground
OE
Vcc
Vss
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
PART NUMBER EXAMPLES
TSOP-I
PACKAGE
SOJ
TSOP-I
SOP
SPEED
35ns
70ns
T15L256A-35J
T15L256A-70P
T15L256A-70D
A6
A5
A4
A3
70ns
A1
A2
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: APR. 2001
Revision:C
TE
CH
T15L256A
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage to Vss Potential
Inputs to Vss Potential
Power Dissipation
RATING
-0.5 to + 4.6
-0.5 to Vcc +0.5
0.5
UNIT
V
V
W
°
C
Storage Temperature
-60 to +150
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage, low
Input Voltage, high
Ambient Temperature
SYM
Vcc
MIN
Typ-5%
-0.3
TYP
3.3
MAX
Typ+5%
0.8
UNIT
V
V
-
-
-
V
IL
VIH
2.1
Vcc+0.3
70
V
T
°
0
C
A
TRUTH TABLE
CS
H
OE
X
WE
X
MODE
Not Selected
I/O1- I/O8
High-Z
Vcc
ISB1
ISB,
Icc
L
L
L
H
L
X
H
H
L
Output Disable
Read
High-Z
Data Out
Data In
Icc
Icc
Write
OPERATING CHARACTERISTICS
(Vcc = 3.3V 5%, Vss = 0V, Ta = 0 to 70 C)
±
°
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
ILI
Input Leakage Current
Vin=Vss to Vcc
-10
-10
-
-
+10
+10
uA
uA
CS
V
IH
VI/O=Vss to Vcc ,
=
ILO
Output Leakage Current
VIH
OE
WE V
IL
or
=
or
=
VOL
VOH
I
I
OL= + 8.0mA
OH= - 4.0mA
Output Low Voltage
Output High Voltage
-
-
-
0.4
-
V
V
2.4
V
mA
CS = IL, I/O=0mA
-35
-70
-
-
40
Operating Power
Supply Current
Icc
Cycle = MIN.
Duty = 100%
mA
-
-
-
-
-
-
35
8
ISB
mA
mA
CS V
IH, Cycle=MIN, Duty=100%
=
Standby Power
Supply Current
ISB1
0.8
³
V
-0.2V,f=0MHz
CS
cc
°
Note: Typical characteristics are at Vcc = 3.3V, Ta = 25 C
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 2
Publication Date: APR. 2001
Revision:C
TE
CH
T15L256A
CAPACITANCE
(Vcc = 3.3V, Ta = 25 C, f = 1 MHz)
°
PARAMETER
Input Capacitance
SYMBOL
CONDITION
VIN
MAX.
UNIT
pF
CIN
CI/O
= 0V
V
OUT= 0V
6
8
Input/ Output Capacitance
pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
CONDITIONS
0V to 3V
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
3 ns
1.5V
C
I
I
/ OL= -4mA/8mA
OH
L =30pF,
AC TEST LOADS AND WAVEFORM
DQ
DQ
50
30 pF
5 pF
ohm
Z0 = 50
50 ohm
Z0 = 50 ohm
ohm
Vt =1.5V
Vt =1.5V
Fig.3
Fig.1
R1 320 ohm
R1 320 ohm
3.3V
OUTPUT
3.3V
OUTPUT
R2
350
ohm
5pF
30pF
R2
350 ohm
Including
Jig and
Scope
Including
Jig and
Scope
Fig.4
Fig.2
(For TCLZ, TOLZ, TCHZ , TOHZ, TWHZ, TOW )
3.0V
0 V
90%
90%
10%
10%
3ns
3ns
Fig.5
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 3
Publication Date: APR. 2001
Revision:C
TE
CH
T15L256A
AC CHARACTERISTICS
(
=3.3V 5%, Vss = 0V, Ta = 0 to 70 C)
V
±
°
cc
(1) READ CYCLE
T15M256A-35
MIN. MAX.
T15M256A-70
UNIT
PARAMETER
SYM.
MIN.
MAX.
TRC
35
-
70
-
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
-
35
35
25
-
-
-
70
70
35
-
Address Access Time
AA
-
Chip Select Access Time
TACS
T
-
-
Output Enable to Output Valid
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
AOE
TCLZ
3
0
-
3
0
-
*
TOLZ
*
-
-
TCHZ
25
25
-
35
35
-
*
TOHZ*
-
-
T
3
3
OH
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
T15M256A-35
T15M256A-70
UNIT
PARAMETER
Write Cycle Time
SYM.
TWC
MIN.
MAX.
MIN.
MAX.
35
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCW
30
30
0
-
-
60
60
0
-
-
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
T
AW
T
-
-
AS
TWP
TWR
TDW
25
0
-
50
0
-
Write Pulse Width
-
-
Write Recovery Time
20
0
-
30
0
-
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
T
-
-
DH
TWHZ
*
-
10
10
-
-
25
25
-
T
*
-
-
OHZ
T
0
0
OW
* These parameters are sampled but not 100% tested.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 4
Publication Date: APR. 2001
Revision:C
TE
CH
T15L256A
TIMING WAVEFORMS
READ CYCLE 1
(Address
Controlled)
t
R C
A d d r e s s
t
A A
t
OH
t
OH
D
O U T
READ CYCLE 2
(Chip Select Controlled)
C S
t
A CS
t
CH Z
t
CLZ
D
O U T
READ CYCLE 3
(Output Enable Controlled)
t
RC
A d d r e s s
t
A A
O E
C S
t
t
t
OH
A OE
OLZ
t
t
t
t
A CS
CLZ
OH Z
CH Z
D
O U T
DON'T CARE
UNDEF INED
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 5
Publication Date: APR. 2001
Revision:C
TE
CH
T15L256A
WRITE CYCLE 1 (OE CLOCK)
t
WC
A d d r e s s
t
WR
O E
t
CW
CS
t
t
AW
WP
WE
t
AS
t
OHZ
(1,4)
D
OU T
t
t
DW
DH
D
I N
(
=
Fixed)
OE
V
WRITE CYCLE 2
IL
t
WC
CW
A d d r e s s
t
t
WR
C S
t
t
A W
WP
W E
t
t
OH
A S
t
WH Z
t
OW
( 1,4 )
( 2)
(3)
D
O U T
t
t
D W
DH
D
I N
DON'T CARE
UNDE FINE D
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 6
Publication Date: APR. 2001
Revision: C
TE
CH
T15L256A
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs
should not be applied.
DOUT
DIN
during the write cycle.
2. The data output from
are the same as the data written to
D
3.
provides the read data for the next address.
OUT
±
C
4. Transition is measured 500 mV from steady state with L = 5pF. This parameter is
guaranteed but not 100% tested.
OE
WE
controlled write cycle, the write pulse width must be the larger of
5. If
is low during a
or (t + t ) to allow the I/O drivers to turn off and data to be placed on the bus for the
t
WP
WHZ DW
required t If OE is high during a WE controlled write cycle, this requirement does not
.
DW
apply and the write pulse can be as short as the specified t
.
WP
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 7
Publication Date: APR. 2001
Revision: C
TE
CH
T15L256A
PACKAGE DIMENSIONS
28-LEAD SOJ SRAM (300 mil)
SYMBOL
DIMENSIONS IN INCHES
DIMENSIONS IN MM
18.03±0.05
7.62±0.13
1.52±0.05
1.27±0.03
1.63±0.03
0.38±0.05
0.76±0.05
1.27±0.05
0.46±0.05
0.71±0.05
8.56±0.05
0.25±0.03
0.66±0.05
6.81±0.08
7.62±0.05
1.35±0.03
3.56±0.10
0.10(MAX)
A
B
C
D
E
F
G
H
I
0.710±0.002
0.300±0.005
0.060±0.002
0.050±0.001
0.063±0.001
0.015±0.002
0.030±0.002
0.050±0.002
0.018±0.002
0.028±0.002
0.337±0.002
0.010±0.001
0.026±0.002
0.268±0.003
0.300±0.002
0.053±0.001
0.140±0.004
0.004(MAX)
J
K
L
M
N
O
P
Q
y
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 8
Publication Date: APR. 2001
Revision: C
TE
CH
T15L256A
PACKAGE DIMENSIONS
28-LEAD TSOP-I SRAM (8X13.4mm)
D
C
1
28
b
e
E
14
15
A2 A1
A
Seating plane
y
"A"
Db
0.010
Gauge plane
Seating plane
L
Detail "A"
L1
SYMBOL
DIMENSIONS IN INCHES
0.047(max.)
DIMENSIONS IN MM
1.20(max.)
A
A1
A2
b
0.004±0.002
0.10±0.05
0.039 0.002
1.00 0.05
±
±
0.008(typ.)
0.006(typ.)
0.20(typ.)
0.15(typ.)
c
Db
E
0.465 0.004
11.80 0.10
±
±
0.315 0.004
8.00 0.10
±
±
e
0.022(typ.)
0.55(typ.)
D
L
0.528 0.008
13.40 0.20
±
0.50 0.10
±
±
0.020 0.004
±
L1
y
0.0315 0.004
0.004(max.)
0.80 0.10
0.10(max.)
±
±
0 ~5
° °
0 ~5
° °
q
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 9
Publication Date: APR. 2001
Revision: C
TE
CH
T15L256A
PACKAGE DIMENSIONS
28-LEAD SOP
e1
28
15
E HE
Detail F
L
1
14
b
e1
D
C
A2
A1
A
S
e
LE
y
See Detail F
Notes :
1. Dimensions D max. & S include
mold flash or tie bar burrs.
2. Dimension b does not include
dambar protrusion / intrusion.
3. Dimensions D & E include mold
mismatch and determined at the
mold parting line.
Seating Plane
Dimension in inches
Symbol
Dimension in mm
min.
-
typ.
max min.
typ.
-
max.
-
-
0.098
-
-
2.5
-
A
A1
A2
b
0.01
0.25
-
0.083 0.085 0.087 2.13
0.014 0.016 0.018 0.39
2.15
0.4
0.15
2.17
0.41
0.2
0.004 0.006 0.008
0.1
C
724 0.728 0.732 18.4 18.5
0.342 0.346 0.350 8.7 8.8
0.044 0.050 0.056 1.12 1.27
18.6
8.9
4. controlling dimension : inches
5. general appearance spec should
be based on final visual inspection
spec.
D
E
1.42
12.1
1.05
1.8
e
0.453 0.465 0.476 11.5
0.026 0.033 0.041 0.65
11.8
0.85
1.5
1.0
-
HE
L
0.047 0.059 0.071
1.2
LE
S
-
-
39
-
-
-
-
-
0.005
0.12
y
0
-
10
0
-
10
q
°
°
°
°
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 10
Publication Date: APR. 2001
Revision: C
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