XC6109C3XXNX [TOREX]
Voltage Detector with External Delay Type Capacitor; 电压检测器与外部延迟型电容器
| 型号： | XC6109C3XXNX |
| 厂家： | 
Torex Semiconductor |
| 描述： | Voltage Detector with External Delay Type Capacitor |
| 文件： | 总13页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
■APPLICATIONS
◆CMOS
◆Highly Accurate
◆Low Power Consumption : 0.9µA (TYP.)
(VDF=1.9V, VIN = 2.0V)
◆Built-In Delay Circuit, Delay Pin Available
●Microprocessor reset circuitry
●Charge voltage monitors
: +2%
●Memory battery back-up switch circuits
●Power failure detection circuits
■FEATURES
■GENERAL DESCRIPTION
The XC6109 series is highly precise, low power
consumption voltage detector, manufactured using CMOS
and laser trimming technologies.
Highly Accurate
: +2%
(Setting Voltage Accuracy>1.5V)
: +30mV
(Setting Voltage Accuracy<1.5V)
With the built-in delay circuit, connecting the delay
capacitance pin to the capacitor enables the IC to provide an
arbitrary release delay time.
Using an ultra small package (SSOT-24), the series is suited
for high density mounting.
Low Power Consumption : 0.9 µA
(TYP., VDF=1.9V, VIN= 2.0V)
Detect Voltage Range
: 0.8V ~ 5.0V
in 100mV increments
Operating Voltage Range : 0.7V ~ 6.0V
Detect Voltage Temperature Characteristics
: ±100ppm/ OC (TYP.)
Both CMOS and N-channel open drain output configurations
are available.
Output Configuration
: CMOS or
N-channel open drain
Operating Temperature Range : -40 OC ~ +85 OC
Ultra Small Package
: SSOT-24
■TYPICAL PERFORMANCE
CHARACTERISTICS
■TYPICAL APPLICATION CIRCUIT
●Release Delay Time vs. Delay Capacitance
XC6109xxxAN
R=100kΩ
VIN
VIN(MIN.)=0.7V,VIN(MAX.)=6.0V
Tr=5µs, Ta=25
℃
VIN
10000
1000
100
10
Cd
VOUT
Cd
(No resistor needed for
CMOS output products)
VSS
1
0.1
0.0001
0.001
0.01
0.1
1
Delay Capacitance: Cd (µF)
1/13
XC6109 ETR0206_004
XC6109 Series
■PIN CONFIGURATION
■PIN ASSIGNMENT
PIN NUMBER
PIN NAME
FUNCTION
Input
Ground
1
2
3
4
VIN
VSS
Cd
VOUT
Delay Capacitance
Output (Detect ”L”)
■PRODUCT CLASSIFICATION
●Ordering Information
XC6109 ①②③④⑤⑥
DESIGNATOR
DESCRIPTION
SYMBOL
DESCRIPTION
C
N
: CMOS output
①
Output Configuration
: N-ch open drain output
② ③
④
Detect Voltage
Output Delay & Hysteresis
Package
08 ~ 50
: e.g. 18→1.8V
A
: Built-in delay pin & hysteresis 5% (TYP.)
⑤
N
: SSOT-24
R
L
: Embossed tape, standard feed
: Embossed tape, reverse feed
⑥
Device Orientation
2/13
XC6109
Series
■PACKAGING INFORMATION
●SSOT-24
■MARKING RULE
●SSOT-24
①
Represents output configuration and integer number of detect voltage
4
3
CMOS output (XC6109C Series)
N-ch Open Drain output (XC6109N Series)
MARK VOLTAGE (V) PRODUCT SERIES MARK VOLTAGE (V) PRODUCT SERIES
①
②
④
A
B
C
D
E
F
0.x
1.x
2.x
3.x
4.x
5.x
XC6109C0xxNx
XC6109C1xxNx
XC6109C2xxNx
XC6109C3xxNx
XC6109C4xxNx
XC6109C5xxNx
K
L
M
N
P
R
0.x
1.x
2.x
3.x
4.x
5.x
XC6109N0xxNx
XC6109N1xxNx
XC6109N2xxNx
XC6109N3xxNx
XC6109N4xxNx
XC6109N5xxNx
1
2
SSOT-24
(TOP VIEW)
②Represents decimal number of detect voltage
MARK
VOLTAGE (V)
PRODUCT SERIES
N
P
R
S
T
U
V
X
Y
Z
x.0
x.1
x.2
x.3
x.4
x.5
x.6
x.7
x.8
x.9
XC6109xx0xNx
XC6109xx1xNx
XC6109xx2xNx
XC6109xx3xNx
XC6109xx4xNx
XC6109xx5xNx
XC6109xx6xNx
XC6109xx7xNx
XC6109xx8xNx
XC6109xx9xNx
④Represents production lot number
0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated/
(G, I, J, O, Q, W excepted)
3/13
XC6109 Series
■BLOCK DIAGRAMS
(1) XC6109C (CMOS Output)
(2) XC6109N (N-ch Open Drain Output)
4/13
XC6109
Series
■ABSOLUTE MAXIMUM RATINGS
Ta = 25OC
UNITS
V
PARAMETER
Input Voltage
Output Current
SYMBOL
VIN
RATINGS
VSS - 0.3 ~ 7.0
10
IOUT
mA
XC6109C (*1)
XC6109N (*2)
Delay Pin Voltage
Delay Pin Current
Power Dissipation SSOT-24
VSS - 0.3 ~ VIN + 0.3
VSS - 0.3 ~ 7.0
Output Voltage
VOUT
V
VCD
ICD
VSS-0.3 ~ VIN + 0.3
5.0
V
mA
Pd
Ta
Tstg
150
- 40 ~ + 85
- 40 ~ + 125
mW
OC
Operating Temperature Range
Storage Temperature Range
OC
NOTE:
*1: CMOS output
*2: N-ch open drain output
■ELECTRICAL CHARACTERISTICS
O
Ta = 25 C
CIRCUIT
PARAMETER
Operating Voltage
Detect Voltage
SYMBOL
VIN
CONDITIONS
VDF(T)=0.8~5.0V (*1)
VDF(T)=0.8~5.0V
MIN.
0.7
TYP.
-
E-1
MAX.
6.0
UNIT
V
V
-
1
VDF
VDF
x 0.02
VDF
x 0.05
0.80
0.90
1.00
0.90
1.10
1.20
VDF
x 0.08
1.70
1.90
2.00
1.80
2.00
2.20
Hysteresis Range 1
VHYS1
ISS1
VIN=1.0~6.0V
V
1
VDF(T)=0.8~1.9V
-
-
-
-
-
-
Supply Current 1
VIN=VDF x 0.9
VIN=VDF x 1.1
2
VDF(T)=2.0~3.9V
VDF(T)=4.0~5.0V
VDF(T)=0.8~1.9V
VDF(T)=2.0~3.9V
VDF(T)=4.0~5.0V
µA
Supply Current 2
Output Current
ISS2
2
µA
VIN=VDFx0.9
VDS=0.5V (N-ch)
VIN=VDFx1.1
IOUT1
E-2
mA
3
3
1
IOUT2
E-3
mA
(*2)
VDS=0.5V (P-ch)
UVDF
UTa・VDF
Rdelay
ICD
ppm/
Temperature
Characteristics
O
O
-
±100
-
-40 C<Ta<85 C
O
C
Delay Resistance (*3)
Delay Pin Sink Current
Delay Capacitance Pin
Threshold Voltage
Unspecified Operating
Voltage (*4)
VIN=6.0V, VCD=0V
VDS=0.5V, VIN=0.7V
VIN=1.0V
1.6
8
0.4
2.0
60
0.5
2.4
-
0.6
4
4
MΩ
µA
VTCD
VUNS
TDF0
TDR0
V
5
6
7
7
VIN=6.0V
2.9
3.0
3.1
VIN=0~0.7V
-
-
-
0.3
30
30
0.4
230
200
V
VIN=6.0 down to 0.7V
Cd: Open
Detect Delay Time (*5)
µs
µs
Release Delay Time
(*6)
NOTE:
*1: VDF(T): Setting Detect Voltage
VIN=0.7~6.0V
Cd: Open
*2: This numerical value is applied only to the XC6109C series (CMOS output).
*3: Calculated from the voltage value and the current value of both ends of the resistor.
*4: The maximum voltage of the VOUT in the range of the VIN 0 to 0.7V. This numerical value is applied only to the XC6109C series
(CMOS output).
*5: Time which ranges from the state of VIN =VDF to the VOUT reaching 0.6V when the VIN falls without connecting to the Cd pin.
*6: Time which ranges from the state of VIN= VDF +VHYS to the VOUT reaching 5.4V when the VIN rises without connecting to the Cd pin.
5/13
XC6109 Series
■VOLTAGE CHART
SYMBOL
E-1
E-2
E-3
SETTING
OUTPUT
VOLTAGE
(V)
DETECT VOLTAGE (*1)
(V)
OUTPUT CURRENT
(mA)
OUTPUT CURRENT (*2)
(mA)
VDF
IOUT1
TYP.
IOUT2
TYP.
VDF(T)
MIN.
TYP.
0.800
0.900
1.000
1.100
1.200
1.300
1.400
1.500
1.600
1.700
1.800
1.900
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
3.600
3.700
3.800
3.900
4.000
4.100
4.200
4.300
4.400
4.500
4.600
4.700
4.800
4.900
5.000
MAX.
MIN.
0.01
MAX.
MIN.
MAX.
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
NOTE:
0.770
0.870
0.970
1.070
1.170
1.270
1.370
1.470
1.568
1.666
1.764
1.862
1.960
2.058
2.156
2.254
2.352
2.450
2.548
2.646
2.744
2.842
2.940
3.038
3.136
3.234
3.332
3.430
3.528
3.626
3.724
3.822
3.920
4.018
4.116
4.214
4.321
4.410
4.508
4.606
4.704
4.802
4.900
0.830
0.930
1.030
1.130
1.230
1.330
1.430
1.530
1.632
1.734
1.836
1.938
2.040
2.142
2.244
2.346
2.448
2.550
2.652
2.754
2.856
2.958
3.060
3.162
3.264
3.366
3.468
3.570
3.672
3.774
3.876
3.978
4.080
4.182
4.284
4.386
4.488
4.590
4.692
4.794
4.896
4.998
5.100
0.36
0.70
-0.40
-0.20
-0.01
0.10
0.30
0.70
1.00
1.30
-0.60
-0.30
-0.40
-0.08
1.80
2.60
-0.80
-1.00
-0.14
-0.20
0.60
1.60
-0.50
1.00
2.00
3.10
-1.20
-0.60
-0.40
1.30
2.30
3.30
-1.30
-0.65
-0.60
*1: When VDF(T)≦1.4V, the detection accuracy is ±30mV. When VDF(T)≧1.5V, the detection accuracy is ±2%.
*2: This numerical value is applied only to the XC6109C series (CMOS output).
6/13
XC6109
Series
■TEST CIRCUITS
Circuit 1
Circuit 2
R=100kΩ
No resistor needed for
CMOS output products
VIN
VIN
A
VOUT
VOUT
V
Cd
V
Cd
VSS
VSS
Circuit 3
Circuit 4
VIN
VIN
VOUT
VOUT
A
Cd
A
Cd
VSS
VSS
Circuit 5
Circuit 6
R=100kΩ
No resistor needed for
CMOS output products
VIN
VIN
VOUT
VOUT
Cd
V
Cd
V
VSS
VSS
V
Circuit 7
R=100kΩ
No resistor needed for
CMOS output products
VIN
VOUT
Waveform Measurement Point
Cd
VSS
7/13
XC6109 Series
■OPERATIONAL EXPLANATION
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on the next page.
① As an early state, the input voltage pin is applied sufficiently high voltage to the release voltage and the delay capacitance
(Cd) is charged to the input pin voltage. While the input pin voltage (VIN) starts dropping to reach the detect voltage
(VDF) (VIN > VDF), the output voltage (VOUT) keeps the “High” level (=VIN).
② When the input pin voltage keeps dropping and becomes equal to the detect voltage (VIN = VDF), an N-ch transistor for
the delay capacitance discharge is turned ON, and starts to discharge the delay capacitance. For the internal circuit,
which uses the delay capacitance pin as power input, the reference voltage operates as a comparator of VIN, and the
output voltage changes into the “Low” level (≦VIN×0.1). The detect delay time (TDF) is defined as time which ranges
from VIN =VDF to the VOUT of “Low” level (especially, when the Cd pin is not connected: TDF0).
③ While the input pin voltage keeps below the detect voltage, and 0.7V or more, the delay capacitance is discharged to the
ground voltage (=VSS) level. Then, the output voltage (VOUT) maintains the “Low” level.
④ While the input pin voltage drops to 0.7V or less and it increases again to 0.7V or more, the output voltage may not be
able to maintain the “Low” level. Such an operation is called “Unspecified Operation”, and voltage which occurs at the
output pin voltage is defined as unstable operating voltage (VUNS).
⑤ While the input pin voltage increases more than 0.7V and it reaches to the release voltage level (VIN＜VDF +VHYS), the
output voltage (VOUT) maintains the “Low” level.
⑥ When the input pin voltage continues to increase more than 0.7V up to the release voltage level (= VDF + VHYS), the N-ch
transistor for the delay capacitance discharge will be turned OFF, and the delay capacitance will be started discharging
via a delay resistor (Rdelay). The internal circuit, which uses the delay capacitance pin as power input, will operate as a
hysteresis comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic Threshold: VTHL=VSS) while the input pin voltage
keeps higher than the detect voltage (VIN > VDF).
⑦ While the input pin voltage becomes equal to the release voltage or higher and keeps the detect voltage or higher, the
delay capacitance (Cd) will be charged up to the input pin voltage. When the delay capacitance pin voltage (VCD)
reaches to the delay capacitance pin threshold voltage (VTCD), the output voltage changes into the “High” (=VIN) level.
TDR is defined as time which ranges from VIN =VDF+VHYS to the VOUT of “High” level (especially when the Cd pin is not
connected: TDR0). TDR can be given by the formula (1).
TDR = －Rdelay×Cd×In (1－VTCD / VIN) +TDR0 …(1)
* In = a natural logarithm
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
the delay capacitance pin threshold voltage is VIN /2 (TYP.)
TDR = 2.0e6×Cd×0.69…(2)
As an example, presuming that the delay capacitance is 0.68μF, TDR is :
2.0e6×0.68e－6×0.69 = 938 (ms)
* Note that the release delay time may remarkably be short when the delay capacitance is not discharged to the ground
(=VSS) level because time described in ③ is short.
⑧ While the input pin voltage is higher than the detect voltage (VIN > VDF), therefore, the output voltage maintains the
“High”(=VIN) level.
●Release Delay Time Chart
Delay Capacitance [Cd]
Release Delay Time [TDR] (TYP.)
Release Delay Time [TDR] (MIN. ~ MAX.)
(μF)
0.01
0.022
0.047
0.1
0.22
0.47
1
(ms)
13.8
30.4
64.9
138
304
649
(ms)
11.0 ~ 16.6
24.3 ~ 36.4
51.9 ~ 77.8
110 ~ 166
243~ 364
519 ~ 778
1100 ~ 1660
1380
8/13
XC6109
Series
■OPERATIONAL EXPLANATION (Continued)
Figure 1: Typical application circuit example
Figure 2: The timing chart of Figure 1
Input Voltage: VIN
Release Voltage: VDF+VHYS
Detect Voltage: VDF
Minimum Operating Voltage (0.7V)
Delay Capacitance Pin Voltage: VCD
Delay Capacitance Pin Threshold Voltage: VTCD
Output Pin Voltage: VOUT
①
④
⑤
⑦
⑧
③
⑥
②
9/13
XC6109 Series
■NOTES ON USE
1. Use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent
damage to the device.
2. The input pin voltage drops by the resistance between power supply and the VIN pin, and by through current at
operation of the IC. At this time, the operation may be wrong if the input pin voltage falls below the minimum operating
voltage range. In CMOS output, for output current, drops in the input pin voltage similarly occur. Oscillation of the
circuit may occur if the drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis
voltage. Note it especially when you use the IC with the VIN pin connected to a resistor.
3. Note that a rapid and high fluctuation of the input pin voltage may cause a wrong operation.
4. When there is a possibility of which the input pin voltage falls rapidly (e.g.: 6.0V to 0V) at release operation with the
delay capacitance pin (Cd) connected to a capacitor, use a schottky barrier diode connected between the VIN pin and
the Cd pin as the Figure 3 shown below.
Figure 3: Circuit example with the delay capacitance pin (Cd) connected to a schottky barrier diode
VIN
R=100kΩ
SBD
(No resistor needed for
CMOS output products)
VIN
Cd
VOUT
VOUT
Cd
VSS
10/13
XC6109
Series
■TYPICAL PERFORMANCE CHARACTERISTICS
(1) Supply Current vs. Input Voltage
(2) Detect Voltage vs. Ambient Temperature
XC6109x25AN
XC6109x25AN
2.0
1.5
1.0
0.5
0.0
2.55
2.50
2.45
Ta=85
℃
25
℃
-40
℃
0
1
2
3
4
5
6
-50
-25
0
25
50
75
)
100
Input Voltage: VIN (V)
Ambient Temperature: Ta (
℃
(3) Hysteresis Voltage vs. Ambient Temperature
XC6109x25AN
0.20
0.15
0.10
0.05
-50
-25
0
25
50
75
)
100
Ambient Temperature: Ta (
℃
(4) Output Voltage vs. Input Voltage
XC6109C25AN
XC6109N25AN
No Pull-up
Pull-up=VIN, R=100k
Ω
4.0
3.0
4.0
3.0
2.0
1.0
0.0
-1.0
Ta=85
℃
Ta=85
℃
2.0
25
25
℃
℃
-40
℃
1.0
0.0
-40
℃
-1.0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Input Voltage: VIN (V)
Input Voltage: VIN (V)
11/13
XC6109 Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(5) Output Current vs. Input Voltage
XC6109C08AN
XC6109x50AN
VDS(P-ch)=0.5V
VDS(N-ch)=0.5V
0.0
-0.5
-1.0
-1.5
-2.0
4.0
3.0
2.0
1.0
0.0
Ta=-40
℃
Ta=85
℃
25
℃
25
℃
-40
℃
85
℃
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Input Voltage: VIN (V)
Input Voltage: VIN (V)
(6) Cd Pin Sink Current vs. Input Voltage
XC6109x50AN
(7) Delay Resistance vs. Ambient Temperature
XC6109xxxAN
VCD=0.0V, VIN=6.0V
VDS=0.5V
4
3.0
Ta=-40
3.5
3
℃
2.5
25
℃
2.0
1.5
1.0
2.5
2
85
℃
1.5
1
0.5
0.0
-50
-25
0
25
50
75
)
100
0
1
2
3
4
5
6
Ambient Temperature: Ta (
℃
Input Voltage: VIN (V)
(8) Release Delay Time vs. Delay Capacitance
XC6109xxxAN
(9) Detect Delay Time vs. Delay Capacitance
XC6109xxxAN
VIN(MIN.)=0.7V,VIN(MAX.)=6.0V
VIN(MIN.)=0.7V, VIN(MAX.)=6.0V
Tr=5µs, Ta=25
℃
Tf=5µs, Ta=25
℃
10000
1000
100
10
100000
10000
1000
100
1
10
0.1
0.0001
1
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
Delay Capacitance: Cd (µF)
Delay Capacitance: Cd (µF)
12/13
XC6109
Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics. Consult us, or our representatives
before use, to confirm that the information in this catalog is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this catalog.
3. Please ensure suitable shipping controls (including fail-safe designs and aging
protection) are in force for equipment employing products listed in this catalog.
4. The products in this catalog are not developed, designed, or approved for use with such
equipment whose failure of malfunction can be reasonably expected to directly
endanger the life of, or cause significant injury to, the user.
(e.g. Atomic energy; aerospace; transport; combustion and associated safety
equipment thereof.)
5. Please use the products listed in this catalog within the specified ranges.
Should you wish to use the products under conditions exceeding the specifications,
please consult us or our representatives.
6. We assume no responsibility for damage or loss due to abnormal use.
7. All rights reserved. No part of this catalog may be copied or reproduced without the
prior permission of Torex Semiconductor Ltd.
13/13
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