XC6113D243ML_技术文档

XC6101~XC6107, XC6111~XC6117 Series

ETR0207_010

Voltage Detector (V_DF=1.6V~5.0V)

■GENERAL DESCRIPTION

The XC6101~XC6107, XC6111~XC6117 series are groups of high-precision, low current consumption voltage detectors with

manual reset input and watchdog functions incorporating CMOS process technology. The series consist of a reference

voltage source, delay circuit, comparator, and output driver. With the built-in delay circuit, the XC6101 ~ XC6107, XC6111 ~

XC6117 series do not require any external components to output signals with release delay time. Moreover, with the manual

reset function, reset can be asserted at any time. The ICs produce two types of output; VDFL (low when detected) and VDFH

(high when detected). With the XC6101 ~ XC6105, XC6111 ~ XC6115 series, the WD pin can be left open if the watchdog

function is not used. Whenever the watchdog pin is opened, the internal counter clears before the watchdog timeout occurs.

Since the manual reset pin is internally pulled up to the VIN pin voltage level, the ICs can be used by leaving the manual reset

pin unconnected if the pin is unused. The detect voltages are internally fixed 1.6V ~ 5.0V in increments of 100mV, using laser

trimming technology. Six watchdog timeout periods are available in a range from 6.25ms to 1.6s. Seven release delay times

are available in a range from 3.13ms to 1.6s.

■APPLICATIONS

■FEATURES

Detect Voltage Range

: 1.6V ~ 5.0V, +2%

(100mV increments)

: V_DFx 5%, TYP.

●Microprocessor reset circuits

●Memory battery backup circuits

●System power-on reset circuits

●Power failure detection

Hysteresis Width

(XC6101~XC6107)

V_DFx 0.1%, TYP.

(XC6111~XC6117)

Operating Voltage Range : 1.0V ~ 6.0V

Detect Voltage Temperature: +100ppm/^OC (TYP.)

Coefficient

Output Configuration

: N-channel open drain,

CMOS

Reset Output Options

: V_DFL(Low when detected)

V_DFH(High when detected)

Watchdog Function

: Watchdog input WD;

If it remains ether high or low for

the duration of the watchdog

timeout period,

a

reset is

asserted.

Manual Reset Function

Release Delay Time

: Manual Reset Input MRB;

When it changes from high to

low, a reset is asserted.

: 1.6s, 400ms, 200ms, 100ms,

50ms, 25ms, 3.13ms (TYP.)

Watchdog Timeout Period : 1.6s, 400ms, 200ms, 100ms,

50ms, 6.25ms (TYP.)

Packages

: SOT-25, USP-6C

■TYPICAL APPLICATION CIRCUIT

■TYPICAL PERFORMANCE

CHARACTERISTICS

●Supply Current vs. Input Voltage

μP

VIN

XC61X1~XC61X5 (2.7V)

30

VIN

XC6101/XC6102

Rpull^＊

25

RESETB

INPUT

VIN

RESETB

20

Ta=25

MRB

WD

I/O

℃

Ta=85

℃

15

10

5

VSS

Ta=-40

5

℃

0

1

2

3

4

6

* Not necessary with CMOS output products.

Input Voltage: VIN (V)

ꢀ

* ‘x’ represents both ‘0’ and ‘1’. (ex. XC61x1⇒XC6101 and XC6111)

1/27

XC6101~XC6107, XC6111~XC6117 Series

■PIN CONFIGURATION

●SOT-25

XC6101, XC6102 Series

XC6111, XC6112 Series

XC6103 & XC6113 Series

XC6104, XC6105 Series

XC6114, XC6115 Series

XC6106, XC6107 Series

XC6116, XC6117 Series

MRB

V

IN

WD

4

V

IN

V

IN

WD

4

V

IN

4

5

4

5

1

2

3

1

2

3

1

2

3

1

2

3

RESETB

V

SS RESET

RESET

V

SS

MRB

RESETB

V

SS RESET

RESETB

V

SS

MRB

SOT-25 (TOP VIEW)

●USP-6C

XC6101, XC6102 Series

XC6111, XC6112 Series

XC6103 & XC6113 Series

XC6104, XC6105 Series

XC6114, XC6115 Series

XC6106, XC6107 Series

XC6116, XC6117 Series

V_IN

1 MRB

6

WD

1

2

V_IN

1 WD

V_IN

1 WD

2 MRB

3 NC

V _IN

6

V_{SS 5}

V_SS

V_{SS 5}

V _SS

MRB

2

2 RESET

5

RESET

NC

3

5

4

3 NC

RESETB 4

4

RESETB

3 NC

4

RESETB

RESET

USP-6C (BOTTOM VIEW)

* The dissipation pad for the USP-6C package should be

solder-plated in recommended mount pattern and metal

masking so as to enhance mounting strength and heat

release. If the pad needs to be connected to other pins, it

should be connected to the VSS (No.5) pin.

■PIN ASSIGNMENT

PIN NUMBER

XC6101, XC6102

XC6111, XC6112

XC6103

XC6113

XC6104, XC6105 XC6106, XC6107

XC6114, XC6115 XC6116, XC6117

PIN NAME

FUNCTION

SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C

Reset Output

RESETB

VSS

1

4

-

1

4

1

4

(VDFL: Low Level When Detected)

Ground

2

3

4

5

2

1

6

2

3

4

5

2

1

6

2

-

5

-

2

4

-

5

1

-

MRB

WD

VIN

Manual Reset

Watchdog

4

5

1

6

5

6

Power Input

Reset Output

-

1

4

3

2

3

2

RESET

(VDFH: High Level When Detected)

2/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■PRODUCT CLASSIFICATION

●Selection Guide

MANUAL

RESET

RESET OUTPUT

SERIES

WATCHDOG

VDFL (RESETB)

CMOS

VDFH (RESET)

XC6101

XC6102

XC6103

XC6104

XC6105

XC6106

XC6107

XC6111

XC6112

XC6113

XC6114

XC6115

XC6116

XC6117

Available

-

Available

N-channel open drain

-

Available

CMOS

Available

Not Available

Available

CMOS

Available

N-channel open drain

CMOS

Not Available

Available

N-channel open drain

●Ordering Information

XC61①②③④⑤⑥⑦⑧

DESIGNATOR

DESCRIPTION

SYMBOL

DESCRIPTION

0

1

: V_DFx 5% (TYP.) with hysteresis

: V_DFx 0.1% (TYP.) without hysteresis

: Watchdog and manual functions, and reset

output type as per Selection Guide in the above

chart

①

Hysteresis Width

Functions and

②

1 ~ 7

Type of Reset Output

Release Delay Time *

A

B

C

D

E

F

: 3.13ms (TYP.)

: 25ms (TYP.)

: 50ms (TYP.)

③

: 100ms (TYP.)

: 200ms (TYP.)

: 400ms (TYP.)

H

: 1.6s (TYP.)

: No WD timeout period for

XC6106, XC6107, XC6116, XC6117 Series

: 6.25ms (TYP.)

0

1

2

3

4

5

6

: 50ms (TYP.)

④

Watchdog Timeout Period

: 100ms (TYP.)

: 200ms (TYP.)

: 400ms (TYP.)

: 1.6s (TYP.)

: Detect voltage

⑤⑥

⑦

Detect Voltage

Packages

16 ~ 50

ex.) 4.5V: ⑤⇒4, ⑥⇒5

: SOT-25

M

E

R

L

: USP-6C

: Embossed tape, standard feed

: Embossed tape, reverse feed

⑧

Device Orientation

* Please set the release delay time shorter than or equal to the watchdog timeout period.

ex.) XC6101D427MR or XC6101D327MR

3/27

XC6101~XC6107, XC6111~XC6117 Series

■BLOCK DIAGRAMS

●XC6101, XC6111 Series

●XC6102, XC6112 Series

●XC6103, XC6113 Series

4/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■BLOCK DIAGRAMS (Continued)

●XC6104, XC6114 Series

●XC6105, XC6115 Series

●XC6106, XC6116 Series

●XC6107, XC6117 Series

5/27

XC6101~XC6107, XC6111~XC6117 Series

■ABSOLUTE MAXIMUM RATINGS

Ta = 25^OC

UNITS

V

PARAMETER

SYMBOL

VIN

RATINGS

VSS -0.3 ~ 7.0

Input Voltage

MRB

WD

VSS -0.3 ~ VIN +0.3

VSS -0.3 ~ 7.0

20

V

Output Current

IOUT

mA

CMOS Output

RESETB/RESET

RESETB

VSS -0.3 ~ VIN +0.3

VSS -0.3 ~ 7.0

250

Output Voltage

V

N-ch Open Drain Output

SOT-25

Power Dissipation

Pd

mW

USP-6C

100

Operational Temperature Range

Storage Temperature Range

Topr

Tstg

-40 ~ +85

^OC

-40 ~ +125

6/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■ELECTRICAL CHARACTERISTICS

●XC6101~XC6107, XC6111~XC6117 Series

Ta = 25 ^OC

PARAMETER

Detect Voltage

SYMBOL

VDFL

CONDITIONS

MIN.

VDF(T)

× 0.98

VDF

TYP.

VDF(T)

VDF

MAX.

VDF(T)

× 1.02

VDF

UNITS CIRCUIT

V

①

VDFH

Hysteresis Width

XC6101~XC6107 ^(*1)

Hysteresis Width

VHYS

× 0.02 × 0.05 × 0.08

VDF

XC6111~XC6117 ^(*2)

× 0.001 x 0.01

VHYS

0

XC61X1/XC61X2/XC61X3

XC61X4/XC61X5 ^(*3)

(The MRB & the WD Pin:

No connection)

VIN=VDF(T)×0.9V

VIN=VDF(T)×1.1V

VIN=6.0V

-

5

10

12

4

11

16

18

10

14

Supply Current

ISS

VIN

μA

V

②

XC61X6/XC61X7 ^(*3)

(The MRB Pin:

VIN=VDF(T)×0.9V

VIN=VDF(T)×1.1V

VIN=6.0V

8

No connection)

-

10

-

0.5

16

6.0

-

Operating Voltage

1.0

0.15

①

③

VIN=1.0V

VIN=2.0V (VDFL(T)> 2.0V)

VIN=3.0V (VDFL(T) >3.0V)

VIN=4.0V (VDFL(T) >4.0V)

2.0

3.0

3.5

2.5

3.5

4.0

-

N-ch.

VDS = 0.5V

VDFL

Output Current

(RESETB)

IRBOUT

mA

CMOS,

P-ch

VIN=6.0V

-

- 1.1

-0.8

④

③

VDS = 0.5V

N-ch

VIN=6.0V

4.4

4.9

-

VDS = 0.5V

VIN=1.0V

VIN=2.0V (VDFH(T)> 2.0V)

VIN=3.0V (VDFH(T)>3.0V)

VIN=4.0V (VDFH(T)>4.0V)

-

- 0.08

- 0.50

- 0.75

- 0.95

- 0.02

- 0.30

- 0.55

- 0.75

VDFH

Output Current

(RESET)

IROUT

mA

P-ch.

VDS = 0.5V

④

①

Temperature

Coefficient

△VDF /

△Topr・VDF

-40^OC < Topr < 85 ^OC

-

+100

-

ppm/ ^OC

2

3.13

25

5

38

13

Time until VIN is increased from

1.0V to 2.0V

and attains to the release time level,

and the Reset output pin inverts.

25

50

75

Release Delay Time

(VDF<1.8V)

TDR

ms

⑤

60

100

200

400

1600

3.13

25

140

280

560

2240

5

120

240

960

2

13

38

Time until VIN is increased from

1.0V to (VDFx1.1V)

25

60

50

75

Release Delay Time

(VDF>1.9V)

100

200

400

1600

140

280

560

2240

TDR

TDF

ms

⑤

and attains to the release time level,

and the Reset output pin inverts.

120

240

960

Time until VIN is decreased from 6.0V to

1.0V and attains to the detect voltage

level, and the Reset output pin detects

while the WD pin left opened.

Detect Delay Time

-

3

30

μs

VDFL/VDFH

CMOS Output

Leak Current

VDFL N-ch Open Drain

Output

VIN=6.0V, RESETB=6.0V (VDFL)

VIN=6.0V, RESET=0V (VDFH)

ILEAK

-

0.01

-

μA

③

VIN=6.0V, RESETB=6.0V

0.10

Leak Current

NOTE:

*1: XC6101~XC6107 (with hysteresis)

*2: XC6111~XC6117 (without hysteresis)

*3: ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)

*4: V^DF(T): Setting detect voltage

*5: If only “VDF” is indicated, it represents both VDFL (low when detected) and VDFH (high when detected).

7/27

XC6101~XC6107, XC6111~XC6117 Series

■ELECTRICAL CHARACTERISTICS (Continued)

●XC6101~XC6105, XC6111~XC6115 Series

Ta = 25 ^OC

PARAMETER

SYMBOL

CONDITIONS

MIN.

3.13

TYP.

6.25

MAX. UNITS CIRCUIT

9.38

25

60

50

100

200

400

1600

75

Time until VIN increases form

1.0V to 2.0V and

the Reset output pin is released to go into

Watchdog

Timeout Period

(VDF<1.8V)

140

TWD

ms

⑥

120

240

960

280

560

the detection state. (WD=VSS)

2240

3.13

25

60

120

240

6.25

50

100

200

400

9.38

75

140

280

560

Time until VIN increases form

1.0V to (VDFx1.1V)

and the Reset output pin is released to go

Watchdog

Timeout Period

(VDF>1.9V)

TWD

ms

ns

⑥

⑦

into the detection state. (WD=VSS)

960

1600

2240

VIN=6.0V,

Apply pulse from 6.0V to 0V

to the WD pin.

Watchdog

Minimum Pulse Width

TWDIN

300

-

Watchdog

High Level Voltage

Watchdog

VWDH

VWDL

VIN=VDF x 1.1V ~ 6.0V

VIN x 0.7

0

-

6

V

⑦

VIN x 0.3

Low Level Voltage

VIN=6.0V, VWD=6.0V (Avg. when peak )

VIN=6.0V, VWD=0V (Avg. when peak)

-

12

19

-

Watchdog

Input Current

IWD

μA

kΩ

⑧

- 19

-12

Watchdog

Input Resistance

RWD

VIN=6.0V, VWD=0V, RWD=VIN/ |IWD|

315

500

880

●XC6101 ~ XC6103, XC6106 ~ XC6107, XC6111 ~ XC6113, XC6116 ~ XC6117 Series

O

Ta = 25 C

PARAMETER

MRB

High Level Voltage

MRB

Low Level Voltage

MRB

Pull-up Resistance

MRB Minimum

Pulse Width ^(*3)

XC6101~XC6105

XC6111~XC6115

MRB Minimum

Pulse Width ^(*4)

XC6106, XC6107

XC6116, XC6117

SYMBOL

VMRH

CONDITIONS

MIN.

1.4

TYP.

-

MAX. UNITS CIRCUIT

VIN=VDFx1.1V ~ 6.0V

VIN

0.35

3.0

⑨

⑩

V

VMRL

RMR

VIN=VDFx1.1V ~ 6.0V

0

-

VIN=6.0V, MRB=0V, RMR=VIN/ |IMRB|

1.6

2.4

MΩ

VIN=6.0V,

Apply pulse from 6.0V to 0V to

the MRB pin

TMRIN

2.8

1.2

-

μs

⑪

VIN=6.0V,

Apply pulse from 6.0V to 0V to

the MRB pin

NOTE:

*1: VDF(T): Setting detect voltage

*2: If only “VDF” is indicated, it represents both VDFL (low when detected) and VDFH (high when detected).

*3: Watchdog function is available.

*4: Watchdog function is not available.

8/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■OPERATIONAL EXPLANATION

The XC6101~XC6107, XC6111~XC6117 series compare, using the error amplifier, the voltage of the internal voltage

reference source with the voltage divided by R1, R2 and R3 connected to the VIN pin. The resulting output signal from the

error amplifier activates the watchdog logic, manual reset logic, delay circuit and the output driver. When the VIN pin voltage

gradually falls and finally reaches the detect voltage, the RESETB pin output goes from high to low in the case of the VDFL type

ICs, and the RESET pin output goes from low to high in the case of the VDFH type ICs.

* VDFL (RESETB) type - output signal: Low when detected.

The RESETB pin output goes from high to low whenever the VIN pin voltage falls below the detect voltage, or whenever the

MRB pin is driven from high to low. The RESETB pin remains low for the release delay time (TDR) after the VIN pin voltage

reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period,

the RESETB pin output remains low for the release delay time (TDR), and thereafter the RESET pin outputs high level signal.

* VDFH (RESET) type – output signal: High when detected.

The RESET pin output goes from low to high whenever the VIN pin voltage falls below the detect voltage, or whenever the

MRB pin is driven from high to low. The RESET pin remains high for the release delay time (TDR) after the VIN pin voltage

reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period,

the VOUT pin output remains high for the release delay time (TDR), and thereafter the RESET pin outputs low level signal.

When the internal comparator output is high, the NMOS transistor connected in parallel to R3 is turned ON, activating the

hysteresis circuit. The difference between the release and detect voltages represents the hysteresis width, as shown by the

following calculations:

VDF (detect voltage) = (R1+R2+R3) x Vref(R2+R3)

VDR (release voltage) = (R1+R2) x Vref(R2)

VHYS (hysteresis width)=VDR-VDF (V)

VDR > VDF

* Detect voltage (VDF) includes conditions of both VDFL (low when detected) and VDFH (high when detected).

* Please refer to the block diagrams for R1, R2, R3 and Vref.

Hysteresis width is selectable from VDF x 0.05V (XC6101~XC6107) or VDF x 0.001V (XC6111~XC6117).

The XC6101~XC6107, XC6111~XC6117 series use a watchdog timer to detect malfunction or “runaway” of the

microprocessor. If neither rising nor falling signals are applied from the microprocessor within the watchdog timeout period,

the RESETB/RESET pin output maintains the detection state for the release delay time (TDR), and thereafter the

RESET/RESETB pin output returns to the release state (Please refer to the FUNCTION CHART). The timer in the watchdog

is then restarted. Six watchdog timeout period settings are available in 1.6s, 400ms, 200ms, 100ms, 50ms, 6.25ms.

Using the MRB pin input, the RESET/RESETB pin signal can be forced to the detection state. When the MRB pin is driven

from high to low, the RESETB pin output goes from high to low in the case of the VDFL type ICs, and the RESET pin output

goes from low to high in the case of the VDFH type. Even after the MRB pin is driven back high, the RESET/RESETB pin

output maintains the detection state for the release delay time (TDR). Since the MRB pin is internally pulled up to the VIN pin

voltage level, leave the MRB pin open if unused (Please refer to the FUNCTION CHART). A diode, which is an input

protection element, is connected between the MRB pin and VIN pin. Therefore, if the MRB pin is applied voltage that exceeds

VIN, the current will flow to VIN through the diode. Please use this IC within the stated maximum ratings (VSS -0.3 ~ VIN +0.3)

on the MRB pin.

Release delay time (TDR) is the time that elapses from when the VIN pin reaches the release voltage, or when the watchdog

timeout period expires with no rising signal applied to the WD pin, until the RESET/RESETB pin output is released from the

detection state. Seven release delay time (TDR) watchdog timeout period settings are available in 1.6s, 400ms, 200ms,

100ms, 50ms, 25ms, 3.13ms.

Detect Delay Time (TDF) is the time that elapses from when the VIN pin voltage falls to the detect voltage until the RESET/

RESETB pin output goes into the detection state.

9/27

XC6101~XC6107, XC6111~XC6117 Series

■TIMING CHARTS

●CMOS Output

●TDF (CMOS Output)

VIN

6.0V

VIN Pin Wave Form

VDFL Level

1.0V

GND

TDF

VIN Level

VDFL Level

RESETB Pin Wave Form (VDFL)

VIN x 0.1V

GND

0.6V

10/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■NOTES ON USE

1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent

damage to the device.

2. When a resistor is connected between the VIN pin and the input, the VIN voltage drops while the IC is operating and a

malfunction may occur as a result of the IC’s through current. For the CMOS output products, the VIN voltage drops while

the IC is operating and malfunction may occur as a result of the IC’s output current. Please be careful with using the

XC6111~XC6117 series (without hysteresis).

3. In order to stabilize the IC’s operations, please ensure that the VIN pin’s input frequency’s rise and fall times are more than

1 μs/V.

4. Noise at the power supply may cause a malfunction of the watchdog operation or the circuit. In such case, please

strength the line between VIN and the GND pin and connect about 0.22μF of a capacitor between the VIN pin and the GND

pin.

5. Protecting against a malfunction while the watchdog time out period, an ignoring time (no reaction time) occurs to the rise

and fall times. Referring to the figure below, the ignoring time (no reaction time) lasts for 900μs at maximum.

6. The watchdog function can be disabled by connecting a three-state device to the WDI pin as a result of the high impedance

state of the WDI pin. This is effective when the watchdog function is not required, for example, during data loading to the

CPU. The WDI input is internally driven through a buffer (LOGIC) and series resistor (R_WD) from the watchdog counter as

showed in the block diagrams of page 4 and 5. The WDI input is designed for minimizing the input current by placing the

series resistor (R_WD) in the maximum resistance of 880kΩ. A voltage drop occurs in proportion to the leakage current of the

three-state device multiplied by the resistance value of the series resistor (RWD) when the three-state device is in the state

of high impedance. The voltage level must be reaching the threshold level of the WD so that a three-state device with small

leakage current should be selected.

The other series is available in the name of XC6121~XC6124 with the ON/OFF control pin for the watchdog function.

When these series is used, external parts such as the three-state device is not required.

● No Reaction Time

No reaction time

(MAX 900μs)

11/27

XC6101~XC6107, XC6111~XC6117 Series

■PIN LOGIC CONDITIONS

PIN NAME

LOGIC

CONDITIONS

NOTE:

H

VIN>VDF+VHYS

*1: If only “VDF” is indicated, it represents both VDFL (low when

detected) and VDFH (high when detected).

*2: For the details of each parameter, please see the electrical

characteristics.

VIN

L

VIN<VDF

H

MRB>1.40V

MRB

WD

L

H

MRB<0.35V

VDF: Detect Voltage

VHYS: Hysteresis Width

When keeping WD>VWDH more than TWD

When keeping WD<VWDL more than TWD

VWDL → VWDH, TWDIN>300ns

VWDH →VWDH, TWDIN>300ns

VWDH: WD High Level Voltage

VWDL: WD Low Level Voltage

TWDIN: WD Pulse Width

L

L → H

H → L

TWD: WD Timeout Period

■FUNCTION CHART

●XC6101/XC61111, XC6102/6112 Series

VIN

H

L

MRB

WD

H

RESETB ^(*2)

Repeat detect and release (H→L→H)

L

H or Open

Open

L → H

H → L

H

L

*1

●XC6103/XC61113 Series

VIN

H

L

MRB

WD

H

RESETB ^(*3)

Repeat detect and release (L→H→L)

L

H or Open

Open

L → H

H → L

L

*1

H

●XC6104/XC61114, XC6105/XC6115 Series

VIN

H

L

WD

H

RESETB ^(*2)

RESET ^(*3)

Repeat detect and release (H→L→H)

Repeat detect and release (L→H→L)

L

Open

L → H

H → L

H

L

*1

H

●XC6106/XC61116, XC6107/XC6117 Series

VIN

H

MRB

RESETB ^(*2)

RESET ^(*3)

L

H or Open

H

L

H

L

*1: Including all logic of WD (WD=H, L, L→H, H→L, OPEN).

*2: When the RESETB is High, the circuit is in the release state.

When the RESETB is Low, the circuit is in the detection state.

*3: When the RESET is High, the circuit is in the release state.

When the RESET is Low, the circuit is in the detection state.

*4: VIN=L and MRB=H can not be combined for the rated input voltage of the MRB pin is Vss-0.3V to VIN+0.3V.

*5: The RESET/RESETB pin becomes indefinite operation while 0.35V<MRB<1.4V.

12/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■TEST CIRCUITS

Circuit 1

Circuit 2

Circuit 3

Circuit 4

13/27

XC6101~XC6107, XC6111~XC6117 Series

■TEST CIRCUITS (Continued)

Circuit 5

Circuit 6

Circuit 7

14/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■TEST CIRCUITS (Continued)

Circuit 8

Circuit 9

100kΩ

(Not used when the CMOS

Output products selected.)

Circuit 10

Circuit 11

15/27

XC6101~XC6107, XC6111~XC6117 Series

■TYPICAL PERFORMANCE CHARACTERISTICS

(1.1) Supply Current vs. Input Voltage

XC61X1~XC61X5 (1.6V)

XC61X1~XC61X5 (2.7V)

30

25

20

15

10

5

30

25

20

15

10

5

Ta=25

℃

Ta=25

Ta=85

℃

Ta=85

℃

Ta=-40

5

℃

Ta=-40

5

℃

0

1

2

3

4

6

0

1

2

3

4

6

Input Voltage: VIN (V)

ꢀ

Input Voltage: VIN (V)

ꢀ

XC61X1~XC61X5 (5.0V)

30

25

20

15

10

5

Ta=85

℃

Ta=25

℃

Ta=-40

5

℃

0

1

2

3

4

6

Input Voltage: VIN (V)

ꢀ

Input Voltage: VIN (V)

(1.2) Supply Current vs. Input Voltage

XC61X6~XC61X7 (1.6V)

30

XC61X6~XC61X7 (2.7V)

30

25

20

15

10

5

25

20

15

Ta=25

℃

Ta=25

℃

Ta=85

℃

Ta=85

℃

10

5

Ta=-40

5

Ta=-40

5

℃

0

1

2

3

4

6

0

1

2

3

4

6

Input Voltage: VIN (V)

ꢀ

Input Voltage: VIN (V)

ꢀ

* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)

16/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(1.2) Supply Current vs. Input Voltage (Continued)

XC61X6~XC61X7 (5.0V)

30

25

20

15

Ta=25

Ta=85

℃

10

5

Ta=-40

5

℃

0

1

2

3

4

6

Input Voltage: VIN (V)

ꢀ

Input Voltage: VIN (V)

(2) Detect, Release Voltage vs. Ambient Temperature

XC61X1~XC61X7 (1.6V)

1.70

XC61X1~XC61X7 (2.7V)

2.90

2.80

2.70

2.60

VDR

1.65

VDR

1.60

VDF

1.55

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Ambient Temperature: Ta (

)

Ambient Temperature: Ta (

)

℃

Ambient Temperature: Ta (℃)

XC61X1~XC61X7 (5.0V)

5.30

5.20

5.10

5.00

4.90

VDR

VDF

-50

-25

0

25

50

75

100

Ambient Temperature: Ta (

)

℃

Ambient Temperature: Ta (℃)

* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)

17/27

XC6101~XC6107, XC6111~XC6117 Series

■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(3-.1) DOeuttepcutt, VRoellteaagseevVs.oIlntapguet Vvso.ltIangpeut(VVDoFltLa)ge (VDFL)

XC6101~XC6107 (1.6V)

Rpull:100kΩ

XC6101~XC6107 (2.7V)

2.0

1.5

1.0

0.5

0.0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Rpull:100kΩ

Ta=-40

℃

Ta=-40

℃

25

85

ꢀꢀ

↓：

↑：

25

85

ꢀꢀ

↓：

↑：

VDF

VDR

VDF

VDR

0

1

2

0

1

2

3

Input Voltage: VIN (V)

ꢀ

Input Voltage: VIN (V)

ꢀ

XC6101~XC6107 (5.0V)

6.0

Rpull:100kΩ

5.0

4.0

3.0

2.0

1.0

0.0

Ta=-40

℃

25

85

ꢀꢀ

↓：

↑：

VDF

VDR

0

1

2

3

4

5

6

Input Voltage: VIN (V)

ꢀ

Input Voltage: VIN (V)

(3.2) Detect, Release Voltage vs. Input Voltage (VDFH)

XC6103~XC6107 (1.6V)

XC6103~XC6107 (2.7V)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

2.0

Rpull:100kΩ

Ta=-40

℃

25

85

VDF

VDR

25

85

VDF

VDR

ꢀꢀ

↑：

↓：

℃

ꢀꢀ

↑：

↓：

℃

1.5

1.0

0.5

0.0

0

1

2

0

1

2

3

Input Voltage: VIN (V)

ꢀ

Input Voltage: VIN (V)

ꢀ

* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)

18/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(3.2) Detect, Release Voltage vs. Input Voltage (VDFH) (Continued)

XC6103~XC6107 (5.0V)

6.0

Rpull:100kΩ

Ta=-40

℃

5.0

4.0

3.0

2.0

1.0

0.0

25

85

ꢀꢀ

↑：

↓：

VDF

VDR

0

1

2

3

4

5

6

Input Voltage: VIN (V)

ꢀ

Input Voltage: VIN (V)

(4) N-ch Driver Output Current vs. VDS

XC61X1~XC61X7

6

XC61X1~XC61X7

20

16

12

8

Ta=25

℃

VIN=4.0V

VIN=2.0V

5

4

3

2

1

0

VIN=3.0V

4

VIN=1.0V

0

1

2

3

0

1

2

3

4

5

6

VDS (V)

(5) N-ch Driver Output Current vs. Input Voltage

XC61X1~XC61X7

6.0

VDS=0.5V

Ta=-40

℃

5.0

4.0

3.0

2.0

1.0

0.0

Ta=25

℃

Ta=85

℃

0

1

2

3

4

5

6

Input Voltage: VIN (V)

ꢀ

* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)

19/27

XC6101~XC6107, XC6111~XC6117 Series

■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(6) P-ch Driver Output Current vs. Input Voltage 1

(7) P-ch Driver Output Current vs. Input Voltage 2

XC61X1, XC61X3~XC61X7

6.0

XC61X1, XC61X3~XC61X7

2.0

VDS=0.5V

Ta=25

℃

5.0

4.0

3.0

2.0

1.0

0.0

1.6

VDS=2.0V

1.5V

Ta=-40

℃

1.2

0.8

0.4

0.0

Ta=25

℃

1.0V

0.5V

Ta=85

℃

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Input Voltage: VIN (V)

ꢀ

(8) Release Delay Time vs. Ambient Temperature

XC61X1~XC61X7

6.0

300

TDR=3.13msec

TDR=100msec

5.0

4.0

3.0

2.0

1.0

0.0

250

200

150

100

50

0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Ambient Temperature: Ta (

)

Ambient Temperature: Ta (

)

℃

XC61X1~XC61X7

TDR=1.6sec

3000

2500

2000

1500

1000

500

0

-50 -25

0

25

50

75

100

Ambient Temperature: Ta (

)

℃

* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)

20/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(9) Watchdog Timeout Period vs. Ambient Temperature

XC61X1~XC61X5

12

300

250

200

150

100

50

TWD=100msec

TWD=100ms

TWD=6.25msec

TWD=6.25ms

10

8

6

4

2

0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Ambient Temperature: Ta (

)

℃

Ambient Temperature: Ta (

)

℃

XC61X1~XC61X5

3000

TWD=1.6sec

TWD=1.6s

2500

2000

1500

1000

500

0

-50

-25

0

25

50

75

100

Ambient Temperature: Ta (

)

℃

(10) Release Delay Time vs. Input Voltage

(11) Watchdog Timeout Period vs. Input Voltage

XC61x1~XC61x5

120

XC61x1~XC61x7

120

Ta=25

TDR=100msec

Ta=25

℃

Ta=25℃ TWD=100ms

TWD=100msec

Ta=25℃ TWD=100ms

110

100

90

110

100

90

80

70

60

1

2

3

4

5

6

7

1

2

3

4

5

6

7

Input Voltage: VIN (V)

ꢀ

* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)

21/27

XC6101~XC6107, XC6111~XC6117 Series

■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(12) Watchdog Low Level Voltage vs. Ambient Temperature

(13) Watchdog High Level Voltage vs. Ambient Temperature

XC61X1~XC61X5

6.0

XC61X1~XC61X5

6.0

5.0

4.0

3.0

2.0

1.0

0.0

5.0

4.0

VIN=6.0V

3.0

2.0

1.0

0.0

VIN=6.0V

VIN=3.0V

VIN=1.76V

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Ambient Temperature: Ta (

)

℃

Ambient Temperature: Ta (

)

℃

(14) MRB Low Level Voltage vs. Ambient Temperature

(15) MRB High Level Voltage vs. Ambient Temperature

XC61X1~XC61X3, XC61X6~XC61X7

1.10

XC61X1~XC61X3, XC61X6~XC61X7

1.10

1.00

0.90

VIN=6.0V

VIN=3.0V

0.80

VIN=6.0V

VIN=3.0V

0.70

VIN=1.76V

0.60

VIN=1.76V

0.50

-50

-25

0

25

50

75

100

-50 -25

0

25

50

75 100

Ambient Temperature: Ta (

)

℃

Ambient Temperature: Ta (

)

℃

* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)

22/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■PACKAGING INFORMATION

●SOT-25

●USP-6C

23/27

XC6101~XC6107, XC6111~XC6117 Series

■PACKAGING INFORMATION (Continued)

●USP-6C Recommended Pattern Layout

●USP-6C Recommended Metal Mask Design

24/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

■MARKING RULE

●SOT-25

① Represents product series

MARK

PRODUCT SERIES

MARK

PRODUCT SERIES

XC6111xxxxxx

XC6112xxxxxx

XC6113xxxxxx

XC6114xxxxxx

XC6115xxxxxx

XC6116xxxxxx

XC6117xxxxxx

0

1

2

3

4

5

6

XC6101xxxxxx

XC6102xxxxxx

XC6103xxxxxx

XC6104xxxxxx

XC6105xxxxxx

XC6106xxxxxx

XC6107xxxxxx

7

8

9

A

B

C

D

①

②

③ ④

SOT-25

(TOP VIEW)

② Represents release delay time and watchdog timeout period

RELEASE

DELAY

TIME

RELEASE

DELAY

TIME

WATCH DOG

TIMEOUT PERIOD

PRODUCT

SERIES

WATCH DOG

TIMEOUT PERIOD

PRODUCT

SERIES

MARK

A

0

1

2

3

4

5

B

6

7

3.13ms XC61X6, XC61X7 series XC61xxA0xxxx

E

F

D

H

K

L

M

E

P

R

S

F

50ms

400ms

1.6s

XC61xxC5xxxx

XC61xxC6xxxx

3.13ms

25ms

6.25ms

50ms

100ms

200ms

400ms

1.6s

XC61xxA1xxxx

XC61xxA2xxxx

XC61xxA3xxxx

XC61xxA4xxxx

XC61xxA5xxxx

XC61xxA6xxxx

100ms

200ms

400ms

1.6s

XC61X6, XC61X7 series XC61xxD0xxxx

100ms

200ms

400ms

1.6s

XC61xxD3xxxx

XC61xxD4xxxx

XC61xxD5xxxx

XC61xxD6xxxx

XC61X6, XC61X7 series XC61xxB0xxxx

XC61X6, XC61X7 series XC61xxE0xxxx

25ms

50ms

100ms

200ms

400ms

1.6s

XC61xxB2xxxx

XC61xxB3xxxx

XC61xxB4xxxx

XC61xxB5xxxx

XC61xxB6xxxx

200ms

400ms

1.6s

XC61xxE4xxxx

XC61xxE5xxxx

XC61xxE6xxxx

8

9

XC61X6, XC61X7 series XC61xxF0xxxx

A

C

B

C

D

25ms

T

400ms

1.6s

XC61xxF5xxxx

XC61xxF6xxxx

50ms

XC61X6, XC61X7 series XC61xxC0xxxx

U

H

V

50ms

100ms

200ms

XC61xxC2xxxx

XC61xxC3xxxx

XC61xxC4xxxx

XC61X6, XC61X7 series XC61xxH0xxxx

1.6s

XC61xxH6xxxx

③ Represents detect voltage

MARK

DETECT VOLTAGE

PRODUCT SERIES

XC61Xxxx16xx

XC61Xxxx17xx

XC61Xxxx18xx

XC61Xxxx19xx

XC61Xxxx20xx

XC61Xxxx21xx

XC61Xxxx22xx

XC61Xxxx23xx

XC61Xxxx24xx

XC61Xxxx25xx

XC61Xxxx26xx

XC61Xxxx27xx

XC61Xxxx28xx

XC61Xxxx29xx

XC61Xxxx30xx

XC61Xxxx31xx

XC61Xxxx32xx

XC61Xxxx33xx

MARK

DETECT VOLTAGE

PRODUCT SERIES

XC61Xxxx34xx

XC61Xxxx35xx

XC61Xxxx36xx

XC61Xxxx37xx

XC61Xxxx38xx

XC61Xxxx39xx

XC61Xxxx40xx

XC61Xxxx41xx

XC61Xxxx42xx

XC61Xxxx43xx

XC61Xxxx44xx

XC61Xxxx45xx

XC61Xxxx46xx

XC61Xxxx47xx

XC61Xxxx48xx

XC61Xxxx49xx

XC61Xxxx50xx

F

H

K

L

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3

4

5

6

7

3.4

3.5

3.6

3.7

3.8

3.9

4.0

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.0

M

N

P

R

S

T

U

V

X

Y

Z

0

8

9

A

B

C

D

E

F

H

K

L

1

2

M

④ Represents production lot number

0 to 9 and A to Z and inverted 0 to 9 and A to Z repeated. (G, I, J, O, Q, W expected.)

* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)

25/27

XC6101~XC6107, XC6111~XC6117 Series

■MARKING RULE (Continued)

●USP-6C

① Represents product series

MARK

PRODUCT SERIES

MARK

PRODUCT SERIES

XC6111xxxxxx

XC6112xxxxxx

XC6113xxxxxx

XC6114xxxxxx

XC6115xxxxxx

XC6116xxxxxx

XC6117xxxxxx

3

4

5

6

7

3

4

XC6101xxxxxx

XC6102xxxxxx

XC6103xxxxxx

XC6104xxxxxx

XC6105xxxxxx

XC6106xxxxxx

XC6107xxxxxx

8

9

A

B

C

8

USP-6C

9

(TOP VIEW)

② Represents release delay time

MARK

RELEASE DELAY TIME

PRODUCT SERIES

XC61XxAxxxxx

XC61XxBxxxxx

XC61XxCxxxxx

XC61XxDxxxxx

XC61XxExxxxx

XC61XxFxxxxx

XC61XxHxxxxx

A

B

C

D

E

F

3.13ms

25ms

50ms

100ms

200ms

400ms

1.6s

H

③ Represents watchdog timeout period

MARK

WATCHDOG TIMEOUT PERIOD

PRODUCT SERIES

XC61Xxx0xxxx

XC61Xxx1xxxx

XC61Xxx2xxxx

XC61Xxx3xxxx

XC61Xxx4xxxx

XC61Xxx5xxxx

XC61Xxx6xxxx

0

1

2

3

4

5

6

XC61X6, XC61X7 series

6.25ms

50ms

100ms

200ms

400ms

1.6s

④⑤ Represents detect voltage

MARK

DETECT VOLTAGE (V)

PRODUCT SERIES

④

3

⑤

3

3.3

5.0

XC61Xxxx33xx

XC61Xxxx50xx

5

0

⑥ Represents production lot number

0 to 9 and A to Z repeated. (G, I, J, O, Q, W excepted.)

* No character inversion used.

** ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)

26/27

XC6101 ~ XC6107, XC6111~ XC6117

Series

1. The products and product specifications contained herein are subject to change without

notice to improve performance characteristics. Consult us, or our representatives

before use, to confirm that the information in this catalog is up to date.

2. We assume no responsibility for any infringement of patents, patent rights, or other

rights arising from the use of any information and circuitry in this catalog.

3. Please ensure suitable shipping controls (including fail-safe designs and aging

protection) are in force for equipment employing products listed in this catalog.

4. The products in this catalog are not developed, designed, or approved for use with such

equipment whose failure of malfunction can be reasonably expected to directly

endanger the life of, or cause significant injury to, the user.

(e.g. Atomic energy; aerospace; transport; combustion and associated safety

equipment thereof.)

5. Please use the products listed in this catalog within the specified ranges.

Should you wish to use the products under conditions exceeding the specifications,

please consult us or our representatives.

6. We assume no responsibility for damage or loss due to abnormal use.

prior permission of Torex Semiconductor Ltd.

27/27


型号：	XC6113D243ML
厂家：	Torex Semiconductor
描述：	Power Management Circuit
文件：	总27页 (文件大小：417K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC6113D243ML [TOREX]

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