XC61FC1631ML [TOREX]
Power Management Circuit;型号: | XC61FC1631ML |
厂家: | Torex Semiconductor |
描述: | Power Management Circuit 光电二极管 |
文件: | 总12页 (文件大小:700K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
■APPLICATIONS
◆CMOS
◆Mini Mold Package
◆Highly Accurate
◆Built-In Delay Circuit ①1ms ~ 50ms
②50ms ~ 200ms
●Microprocessor reset circuitry
●Memory battery back-up circuits
●Power-on reset circuits
: ± 2%
●Power failure detection
●System battery life and charge voltage monitors
●Delay circuitry
③80ms ~ 400ms
◆Low Power Consumption
:
1.0
μ
A (TYP.) [VIN = 2.0V]
■GENERAL DESCRIPTION
The XC61F series are highly accurate, low power
consumption voltage detectors, manufactured using
CMOS and laser trimming technologies. A delay circuit
is built-in to each detector.
Detect voltage is extremely accurate with minimal
temperature drift.
Both CMOS and N-channel open drain output
configurations are available.
Since the delay circuit is built-in, peripherals are
unecessary and high density mounting is possible.
■FEATURES
Highly Accurate
: ± 2%
Low Power Consumption : 1.0μA(TYP.)[ VIN=2.0V ]
Detect Voltage Range
Operating Voltage Range : 0.7V ~ 10.0V
Detect Voltage Temperature Characteristics
:±100ppm/℃(TYP.)
Built-In Delay Circuit : ①1ms ~ 50ms
②50ms ~ 200ms
:
1.6V ~ 6.0V in 100mV increments
③80ms ~ 400ms
Output Configuration
Ultra Small Packages
:
:
:
N-channel open drain or CMOS
SOT-23(150mW) mini-mold
SOT-89 (500mW) mini-power mold
: TO-92 (300mW)
* No parts are available with an accuracy of ± 1%
■TYPICAL PERFORMANCE
■TYPICAL APPLICATION CIRCUITS
CHARACTERISTICS
Ambient Temperature:Ta(℃)
89
XC61F Series
■PIN CONFIGURATION
■PIN ASSIGNMENT
PIN NUMBER
PIN NAME
FUNCTION
SOT-23
SOT-89
TO-92(T)
TO-92(L)
3
2
1
2
3
1
2
3
1
1
2
3
VIN
VSS
VOUT
Supply Voltage Input
Ground
Output
90
XC61F
Series
■PRODUCT CLASSIFICATION
●Ordering Information
XC61F ①②③④⑤⑥⑦
DESIGNATOR
DESCRIPTION
SYMBOL
DESCRIPTION
: CMOS output
: N-ch open drain output
: e.g. 2.5V → ②2 , ③5
: e.g. 3.8V → ②3 , ③8
: 1ms ~ 200ms
: 80ms ~ 400ms
: 1ms ~ 50ms
: Within ±2.0%
C
N
①
Output Configuration
②
③
Detect Voltage
16 ~ 60
1
2
3
④
⑤
Output Delay
Detect Accuracy
1
M
P
T
L
R
L
: SOT-23
: SOT-89
⑥
⑦
Package
: TO-92 (Standard)
: TO-92 (Custom pin configuration)
: Embossed tape, Standard feed
: Embossed tape, Reverse feed
: Paper type ( TO-92)
: Bag : ( TO-92 )
Device Orientation
H
B
■PACKAGING INFORMATION
●SOT-23
91
XC61F Series
■PACKAGING INFORMATION (Continued)
●SOT-89
●TO-92
92
XC61F
Series
■MARKING RULE
●SOT-23, SOT-89
3
①
1
②
③
④
2
1
2
3
①Represents integer of detect voltage and output configuration
CMOS output (XC61FC series)
N-channel open drain (XC61FN series)
MARK
CONFIGURATION
CMOS
VOLTAGE(V)
0. X
MARK
CONFIGURATION VOLTAGE(V)
A
B
C
D
E
F
K
L
N-ch
N-ch
N-ch
N-ch
N-ch
N-ch
N-ch
0. X
1. X
2. X
3. X
4. X
5. X
6. X
CMOS
1. X
CMOS
2. X
M
N
P
R
S
CMOS
3. X
CMOS
4. X
CMOS
CMOS
5. X
H
6. X
②Represents decimal number of detect voltage
③Represents delay time
MARK
VOLTAGE(V) DESIGNATOR VOLTAGE(V)
VOLTAGE(V)
DELAY TIME
50 to 200ms
80 to 400ms
1 to 50ms
5
6
7
0
1
2
3
4
X.0
X.1
X.2
X.3
X.4
5
6
7
8
9
X.5
X.6
X.7
X.8
X.9
④Represents assembly lot number
(Based on internal standards. )
●TO-92
②Represents detect voltage
①Represents output
configuration
MARK
VOLTAGE
( )
V
OUTPUT
②
3
③
3
MARK
CONFIGURATION
CMOS
3.3
5.0
C
N
5
0
N-ch
④Represents delay time
MARK
DELAY TIME
1
4
5
500ms~200ms
80ms~400ms
1ms~50ms
⑤Represents detect voltage accuracy
MARK
2
DETECT VOLTAGE ACCURACY
Within ± 2%
⑥Represents a least significant digit of
the production year
MARK
PRODUCTION YEAR
⑦Represents production lot number
0 to 9, A to Z repeated (G,I,J,O,Q,W excepted)
3
4
2003
2004
93
XC61F Series
■BLOCK DIAGRAMS
■
Ta = 25℃
UNITS
V
(1)CMOS output
PARAMETER
Input Voltage
Output Current
SYMBOL
RATINGS
VIN
12.0
IOUT
50
mA
CMOS
V
SS-0.3~VIN+0.3
Output Voltage
VOUT
V
N-ch open drain
SOT-23
VSS -0.3 ~ 9
150
Power
Pd
mW
SOT-89
500
Dissipation
TO-92
300
Operating Temperature Range
Strage Temperature Range
Topr
Tstg
-30~+85
-40~+125
℃
℃
(2)N-channel open drain output
■ELECTRICAL CHARACTERISTICS
Ta=25℃
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX. UNITS
CIRCUIT
V
DF(T)
x 0.98
VDF
VDF(T)
VDF(T)
Detect Voltage
VDF
V
1
1
x 1.02
VDF
VDF
Hysteresis Range
VHYS
V
x 0.02 x 0.05 x 0.08
VIN = 1.5V
= 2.0V
-
0.9
1.0
2.6
-
3.0
Supply Current
ISS
VIN
μA
2
1
3
= 3.0V
-
1.3
3.4
= 4.0V
= 5.0V
-
1.6
3.8
-
2.0
4.2
Operating Voltage
VDF= 1.6V to 6.0V
0.7
-
10.0
V
VIN = 1.0V
-
-
-
-
-
-
2.2
-
-
-
-
-
-
=2.0V
=3.0V
=4.0V
=5.0V
7.7
N-ch VDF =0.5V
10.1
11.5
13.0
-10.0
Output Current
IOUT
mA
CMOS, P-ch VDF=2.1V VIN=8.0V
4
-
Detect Voltage
Temperature
ΔVDF
ΔTopr・VDF
ppm/
℃
-
±100
-
Characteristics
Transient Delay Time
VIN changes from
0.6V to 10V
*
TDLY
50
-
200
ms
5
(VDR
→
VOUT inversion)
VDF (T) : Setting detect voltage value
Release Voltage : VDR = VDF + VHYS
* Transient Delay Time : 1ms to 50ms & 80ms to 400ms versions are also available.
Note: The power consumption during power-start to output being stable (release operation) is 2μA greater than it is after that period
(completion of release operation) because of delay circuit through current.
94
XC61F
Series
■OPERATIONAL EXPLANATION
●CMOS output
①
When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN), the voltage will
gradually fall. When a voltage higher than the detect voltage (VDF) is applied to VIN , output (VOUT) will be equal to
the input at VIN.
Note that high impedeance exists at VOUT with the N-channel open drain configuration. If the pin is pulled up, VOUT will
be equal to the pull up voltage.
②
③
④
When VIN falls below VDF , VOUT will be equal to the ground voltage (VSS) level (detect state). Note that this also
applies to N-channel open drain configurations.
When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable.Because
the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up voltage.
When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to
VSS until VIN reaches the VDR level.
⑤
⑥
Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit.
Following transient delay time, VIN will be output at VOUT. Note that high impedeance exists with the N-channel open
drain configuration and that voltage will be dependent on pull up.
Notes :
1. The difference between VDR and VDF represents the hysteresis range.
2. Propagation delay time (tDLY) represents the time it takes for VIN to appear at VOUT once the said voltage has
exceeded the VDR level.
●Timing Chart
95
XC61F Series
■DIRECTIONS FOR USE
●Notes on Use
1. Please use this IC within the stated maximum ratings. The IC is liable to malfunction should the ratings be exceeded.
2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may
occur as a result of voltage drops at RIN if load current (IOUT) exists. It is therefore recommend that no resistor be added.
( refer to Oscillation Description (1) below )
3. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch
output configurations, oscillation may occur as a result of through current at the time of voltage release even if load
current (IOUT ) does not exist. ( refer to Oscillation Description (2) below )
4. With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the
IC'ssupply current flowing through the VIN pin.
5. If a resistor (RIN ) must be used, then please use with as small a level of input impedance as possible in order to control
the occurences of oscillation as described above.
Further, please ensure that RIN is less than 10kΩ and that CIN is more than 0.1μF (Figure 1). In such cases, detect
and release voltages will rise due to voltage drops at RIN brought about by the IC's supply current.
●Oscillation Description
(1) Oscillation as a result of output current with the CMOS output configuration :
When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load
current (IOUT) will flow through RL. Because a voltage drop ( RIN x IOUT) is produced at the RIN resistor, located
between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to
a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect
operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will
disappear, the voltage level at the VIN pin will rise and release operations will begin over again.
Oscillation may occur with this " release - detect - release " repetition.
Further, this condition will also appear via means of a similar mechanism during detect operations.
(2) Oscillation as a result of through current :
Since the XC61F series are CMOS ICS, through current will flow when the IC's internal circuit switching operates
( during release and detect operations ). Consequently, oscillation is liable to occur during release voltage operations
as a result of output current which is influenced by this through current ( Figure 3 ).
Since hysteresis exists during detect operations, oscillation is unlikely to occur.
Figure 1. When using an input resistor
96
XC61F
Series
■DIRECTIONS FOR USE (Continued)
●Oscillation Description (Continued)
97
XC61F Series
98
XC61F
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
99
XC61F Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
100
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