XC61FN2542PR [TOREX]

Voltage Detectors ( Delay Circuit Built-In); 电压检测器(延迟电路内置)
XC61FN2542PR
型号: XC61FN2542PR
厂家: Torex Semiconductor    Torex Semiconductor
描述:

Voltage Detectors ( Delay Circuit Built-In)
电压检测器(延迟电路内置)

电源电路 电源管理电路
文件: 总12页 (文件大小:192K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
02S_04XC61F 02.09.12 14:04 ページ 157  
Series  
Voltage Detectors ( Delay Circuit Built-In)  
CMOS  
■Applications  
Microprocessor reset circuitry  
Memory battery back-up circuits  
Power-on reset circuits  
Mini Mold Package  
Highly Accurate  
2
: ±±%  
Built-In Delay Circuit (1ms ~ 50ms)  
(50ms ~ ±00ms)  
Power failure detection  
System battery life and charge voltage monitors  
Delay circuitry  
(80ms ~ 400ms)  
Low Power Consumption : 1.0µA (VIN = ±.0V)  
■General Description  
The XC61F series are highly accurate, low power consumption voltage  
detectors, manufactured using CMOS and laser trimming technologies. A  
delay circuit is built-in to each detector.  
■Features  
Highly Accurate  
: Detect voltage 2%  
Low Power Consumption : TYP 1.0 µA [ VIN=2.0V ]  
Detect Voltage Range : 1.6V ~ 6.0V in 0.1V increments  
Detect voltage is extremely accurate with minimal temperature drift.  
Both CMOS and N-channel open drain output configurations are  
available.  
Operating Voltage Range : 0.7V ~ 10.0V  
Detect Voltage Temperature Characteristics  
: TYP 100ppm/°C  
Since the delay circuit is built-in, peripherals are unecessary and high  
density mounting is possible.  
Built-In Delay Circuit  
: 1ms ~ 50ms, 50ms ~ 200ms, 80ms ~  
400ms  
Output Configuration  
Ultra Small Packages  
: N-channel open drain or CMOS  
: SOT-23 (150mW) mini-mold  
: SOT-89 (500mW) mini-power mold  
: TO-92 (300mW)  
* No parts are available with an accuracy of ± 1%  
■Typical Application Circuits  
■Typical Performance  
Characteristic  
AMBIENT TEMPERATURE vs.  
R
100kΩ  
VIN  
VIN  
VIN  
VIN  
TRANSIENT DELAY TIME  
XC61FC3012�  
VOUT  
VOUT  
VSS  
VSS  
200  
150  
100  
50  
CMOS output  
N-channel open drain output  
-30  
-10  
10  
30  
50  
70  
Ambient Temp.: Ta(℃)  
157  
02S_04XC61F 02.09.12 14:04 ページ 158  
XC61F Seires  
■Pin Configuration  
VIN  
3�  
2�  
SS  
1
OUT  
1
OUT  
2�  
IN  
3�  
SS  
V
V
V
V
V
SOT-23  
(TOP VIEW)  
SOT-89  
(TOP VIEW)  
2
1
2
3
1
2
3
VOUTꢀ  
VIN  
VSS  
VIN  
VSS  
VOUT  
TO-92 (T Type)�  
(TOP VIEW)�  
TO-92 (L Type)�  
(TOP VIEW)�  
■Pin Assignment  
PIN NUMBER  
PIN  
FUNCTION  
SOT-23 SOT-89 TO-92 (T) TO-92 (L) NAME  
3
2
1
2
3
1
2
3
1
1
2
3
V
V
IN  
Supply Voltage Input  
Ground  
SS  
VOUT  
Output  
158  
02S_04XC61F 02.09.12 14:04 ページ 159  
XC61F  
Series  
■Product Classification  
Ordering Information  
XC61F XX XX XX X  
ꢀꢀꢀꢀꢀ↑↑↑↑↑↑↑�  
a b b c d e f  
DESIGNATOR  
DESCRIPTION  
Output Configuration :  
C = CMOS  
N = N-ch open drain  
Detect Voltage (VDF) :  
25 = 2.5V  
DESIGNATOR  
e
DESCRIPTION  
Package Type :  
M = SOT-23  
a
b
c
P = SOT-89  
2
T = TO-92 (Regular)  
L = TO-92 (Custom pin  
Configuration)  
38 = 3.8V  
Output Delay :  
Device Orientation :  
1 = 50ms to 200ms  
4 = 80ms to 400ms  
5 = 1ms to 50ms  
Detect Accuracy :  
2 = within 2.0%  
f
R = Embossed Tape ( Right )  
L = Embossed Tape ( Left )  
H: Paper Tape (TO-92)  
B: Bag (TO-92)  
d
■Packaging Information  
SOT-23  
+0.1�  
-0.05  
+0.1�  
-0.05  
0.15  
0.4  
0~0.1  
(0.95)�  
1.1±0.1  
1.9±0.2  
2.9±0.2  
159  
02S_04XC61F 02.09.12 14:04 ページ 160  
XC61F Seires  
SOT-89  
1.5±0.1  
4.5±0.1  
+0.15�  
-0.2  
1.6  
2
+0.03�  
-0.02  
0.4  
0.42±0.06  
0.42±0.06  
0.47±0.06  
1.5±0.1 1.5±0.1  
TO-92  
+0.35�  
-0.45  
4.65  
3.7±0.3  
0.45±0.1  
0.4±0.05  
+0.4�  
+0.4�  
2.5  
2.5  
-0.1  
-0.1  
160  
02S_04XC61F 02.09.12 14:04 ページ 161  
XC61F  
Series  
■Marking  
SOT-23, SOT-89  
w
r
e
w
q
e r  
q
SOT-23  
(TOP VIEW)  
SOT-89  
(TOP VIEW)  
2
q Represents the integer of the Detect Voltage and the Output Configuration  
CMOS output (XC61FC series) N-channel open drain (XC61FN series)  
DESIGNATOR  
CONFIGURATION  
CMOS  
VOLTAGE (V)  
0.w  
DESIGNATOR  
CONFIGURATION  
VOLTAGE (V)  
0.w  
A
B
C
D
E
F
K
L
N-ch  
N-ch  
N-ch  
N-ch  
N-ch  
N-ch  
N-ch  
CMOS  
CMOS  
CMOS  
CMOS  
1.w  
2.w  
3.w  
4.w  
5.w  
6.w  
1.w  
2.w  
3.w  
4.w  
5.w  
6.w  
M
N
P
R
S
CMOS  
H
CMOS  
w Represents the decimal number of the Detect Voltage  
e Indicates the presence of delay time  
DESIGNATOR VOLTAGE (V) DESIGNATOR VOLTAGE (V)  
DESIGNATOR DELAY TIME  
q.0  
q.1  
q.2  
q.3  
q.4  
q.5  
q.6  
q.7  
q.8  
q.9  
0
1
2
3
4
5
6
7
8
9
5
6
7
50 to 200ms  
80 to 400ms  
1 to 50ms  
r Represents the assembly lot no.  
Based on internal standards  
TO-92  
w
Represents the Detect Voltage  
q
Represents the output �  
configuration  
DESIGNATOR  
61C  
1
5
7
1
L
7
61C  
VOLTAGE(V)�  
DESIGNATOR OUTPUT CONFIGURATION  
w
e
2
3
4
6
2
3
4
5
6
C
N
CMOS  
N-ch  
3
5
3
0
3.3  
5.0  
r
Indicates Delay Time  
DESIGNATOR  
DELAY TIME  
1
4
5
50ms~200ms  
80ms~400ms  
1ms~50ms  
TO-92(T Type)�  
(TOP VIEW)  
TO-92(L Type)�  
(TOP VIEW)  
t
Represents the Detect Voltage Accuracy  
DESIGNATOR  
DETECT VOLTAGE ACCURACY  
y
Represents a least significant digit of �  
the produced yearꢀ�  
2
within 2%  
DESIGNATOR PRODUCED YEAR  
u
Denotes the production lot number�  
0 to 9, A to Z repeated(G.I.J.O.Q.W excepted)  
0
1
2000  
2001  
161  
02S_04XC61F 02.09.12 14:04 ページ 162  
XC61F Seires  
■Block Diagram  
Absolute Maximum Ratings  
Ta=25℃�  
PARAMETER  
Input Voltage  
Output Current  
SYMBOL  
IN  
OUT  
RATINGS  
UNITS  
(1)CMOS output  
V
12  
50  
V
V
IN  
I
mA  
CMOS  
V
SS -0.3 VIN +0.3  
Output Voltage  
V
OUT  
Pd  
V
N-ch open drain  
SOT-23  
V
SS -0.3 9  
150  
V
OUT  
Delay Circuit  
Continuous Total  
Power Dissipation  
SOT-89  
500  
mW  
Vref  
TO-92  
300  
O
Operating Ambient Temperature  
Storage Temperature  
Topr  
Tstg  
-30 +80  
C
O
-40 +125  
C
2
V
SS  
(2)N-channel open drain output  
V
IN  
VOUT  
Delay Circuit  
Vref  
VSS  
■Electrical Characteristics  
Ta=25℃�  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
DF (T)  
MAX  
UNITS CIRCUIT  
VDF (T)  
V
VDF (T)  
Detect Voltage  
V
DF  
V
V
1
1
x 0.98  
DF  
x 0.02  
x 1.02  
V
VDF  
VDF  
Hysteresis Range  
VHYS  
x 0.05  
x 0.08  
V
IN=1.5V  
=2.0V  
=3.0V  
=4.0V  
=5.0V  
0.9  
1.0  
1.3  
1.6  
2.6  
3.0  
3.4  
3.8  
Supply Current  
I
SS  
µA  
2
1
3
2.0  
4.2  
Operating Voltage  
V
IN  
V
DF=1.6V to 6.0V  
0.7  
10.0  
V
N-ch  
P-ch  
VDS=0.5V  
V
IN=1.0V  
=2.0V  
=3.0V  
=4.0V  
=5.0V  
DS=2.1V  
2.2  
7.7  
10.1  
11.5  
13.0  
Output Current  
I
OUT  
mA  
V
VIN=8.0V  
-10.0  
100  
4
( CMOS output )  
Detect Voltage  
VDF  
ppm/°C  
-
Temperature Characteristics  
Transient Delay Time  
Topr  
VDF  
V
IN changes from  
0.6V to 10V  
ms  
tDLY *  
50  
200  
5
(VDR  
VOUT inversion)  
VDF(T):established detect voltage value  
Release Voltage : VDR = V DF + V HYS  
* Transient Delay Time : 1ms to 50ms & 80ms to 400ms versions are also available.  
Note : The power consumption during power-start to output being stable (release operation) is 2 µA greater than it is after that period�  
(completion of release operation) because of delay circuit through current.  
162  
02S_04XC61F 02.09.12 14:04 ページ 163  
XC61F  
Series  
■Functional Description  
Functional Description ( CMOS output )  
q
When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN), the voltage will gradually fall.  
When a voltage higher than the detect voltage (VDF) is applied to VIN , output (VOUT) will be equal to the input at VIN  
.
Note that high impedeance exists at VOUT with the N-channel open drain configuration. If the pin is pulled up, VOUT will be  
equal to the pull up voltage.  
w
e
When VIN falls below VDF , VOUT will be equal to the ground voltage (VSS) level (detect state).  
Note that this also applies to N-channel open drain configurations.  
When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable.  
Because the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up  
voltage.  
2
r
When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to VSS until  
V
IN reaches the VDR level.  
Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit.  
Following transient delay time, VIN will be output at VOUT  
Note that high impedeance exists with the N-channel open drain configuration and that voltage will be dependent on pull up.  
t
y
.
Notes :  
1. The difference between VDR and VDF represents the hysteresis range.  
2. Propagation delay time (tDLY) represents the time it takes for VIN to appear at VOUT once the said voltage has exceeded the  
V
DR level.  
Timing Chart  
IN  
Input Voltage (V  
Detect Release Voltage (VDR  
Detect Voltage (VDF  
)
)
y
)
Minimum Operating Voltage  
(VMIN  
)
Ground Voltage (VSS  
)
Output Voltage(VOUT  
)
Propagation Delay Time (tDLY)  
Ground Voltage (VSS  
)
w
e
r
q
t
y
163  
02S_04XC61F 02.09.12 14:04 ページ 164  
XC61F Seires  
■Directions for use  
Notes on Use  
1. Please use this IC within the stated maximum ratings. The IC is liable to malfunction should the ratings be exceeded.  
2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur  
as a result of voltage drops at RIN if load current (IOUT) exists.  
It is therefore recommend that no resistor be added. ( refer to N.B. 1 - (1) below )  
3. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch  
output configurations, oscillation may occur as a result of through current at the time of voltage release even if load  
current (IOUT ) does not exist. ( refer to N.B. 1 - (2) below )  
2
4. With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's  
supply current flowing through the VIN pin.  
5. If a resistor (RIN ) must be used, then please use with as small a level of input impedance as possible in order to control  
the occurences of oscillation as described above.  
Further, please ensure that RIN is less than 10kand that CIN is more than 0.1µF (Diagram 1). In such cases, detect and  
release voltages will rise due to voltage drops at RIN brought about by the IC's supply current.�  
6. Depending on circuit's operation, transient delay time of this IC can be widely changed due to upper limits or lower limits  
of operational ambient temparature.  
N.B.  
1. Oscillation  
(1) Oscillation as a result of output current with the CMOS output configuration :  
When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load  
current (IOUT) will flow through RL. Because a voltage drop ( RIN x IOUT) is produced at the RIN resistor, located between  
the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the  
voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will  
commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the  
voltage level at the VIN pin will rise and release operations will begin over again.  
Oscillation may occur with this " release - detect - release " repetition.  
Further, this condition will also appear via means of a similar mechanism during detect operations.  
(2) Oscillation as a result of through current :  
Since the XC61F series are CMOS ICS, through current will flow when the IC's internal circuit switching operates ( during  
release and detect operations ). Consequently, oscillation is liable to occur during release voltage operations as a result  
of output current which is influenced by this through current ( Diagram 3 ).  
Since hysteresis exists during detect operations, oscillation is unlikely to occur.  
XC61FN Series  
XC61FC Series  
RIN  
RIN  
VIN  
VOUT  
VIN  
VOUT  
VSS  
VSS  
CIN  
CIN  
Diagram1. When using an input resistor  
164  
02S_04XC61F 02.09.12 14:04 ページ 165  
XC61F  
Series  
XC61FC Series  
RIN  
RIN X IOUT  
IOUT  
VIN  
VOUT  
Voltage drop  
VSS  
RL  
2
Diagram 2. Oscillation in relation to output current  
XC61FC Series  
XC61FN Series  
RIN  
RIN X IOUT  
VIN  
VOUT  
Voltage drop  
VSS  
ISS*  
(includes through current)  
Diagram 3. Oscillation in relation to through current  
165  
02S_04XC61F 02.09.12 14:04 ページ 166  
XC61F Seires  
■Typical Performance Characteristics  
(1) SUPPLY CURRENT vs. INPUT VOLTAGE  
XC61FN2512�  
XC61FN3512�  
XC61FN1612�  
4.0  
3.0  
2.0  
1.0  
0.0  
4.0  
3.0  
2.0  
1.0  
0.0  
4.0  
3.0  
2.0  
1.0  
0.0  
Ta=80℃�  
Ta=80℃�  
Ta=80℃�  
-30℃�  
-30℃�  
-30℃�  
8
2
25℃�  
25℃�  
6
25℃�  
0
2
4
6
8
10  
0
2
4
6
10  
0
2
4
8
10  
Input Voltage: VIN (V)  
Input Voltage: VIN (V)  
Input Voltage: VIN (V)  
(2) DETECT VOLTAGE, RELEASE VOLTAGE vs. AMBIENT TEMPERATURE  
XC61FN3512�  
XC61FN1612�  
XC61FN2512�  
1.8  
1.7  
1.6  
1.5  
1.4  
2.8  
2.7  
2.6  
2.5  
2.4  
2.3  
3.8  
3.7  
3.6  
3.5  
3.4  
3.3  
3.2  
VDR  
VDF  
VDR  
VDF  
VDR  
VDF  
-40 -20  
0
20  
40  
60  
80  
-40  
-20  
0
20  
40  
60  
80  
-40 -20  
0
20  
40  
60  
80  
Ambient Temp.: Ta(℃)  
Ambient Temp.: Ta(℃)  
Ambient Temp.: Ta(℃)  
(3) OUTPUT VOLTAGE vs. INPUT VOLTAGE  
XC61FN1612�  
XC61FN2512�  
XC61FN3512�  
3.0  
5
4
3
2
1
0
4
3
2
1
0
VIN-VOUT:100kΩ�  
a=-30℃�  
25℃�  
VIN-VOUT:100kΩ�  
VIN-VOUT:100kΩ�  
Ta=-30℃�  
25℃�  
a=-30℃�  
2.5  
25℃�  
80℃�  
2.0  
80℃�  
80℃�  
1.5  
1.0  
0.5  
0.0  
0
1
2
3
0
1
2
3
4
0
1
2
3
4
5
Input Voltage: VIN (V)  
Input Voltage: VIN (V)  
Input Voltage: VIN (V)  
(4) N-CHANNEL DRIVER OUTPUT CURRENT vs. VDS  
XC61FN1612�  
XC61FN1612�  
XC61FN2512�  
15  
12  
9
30  
25  
20  
15  
10  
5
1400  
1200  
1000  
800  
600  
400  
200  
0
Ta=25℃�  
Ta=25℃�  
Ta=25℃�  
VIN =0.8V  
VIN =2.0V  
VIN=1.5V  
0.7V  
6
1.5V  
1.0V  
3
0
0
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
0.0  
0.5  
1.0  
1.5  
2.0  
0
0.2  
0.4  
0.6  
0.8  
1.0  
VDS (V)  
VDS (V)  
VDS (V)  
166  
02S_04XC61F 02.09.12 14:04 ページ 167  
XC61F  
Series  
(4) N-CHANNEL DRIVER OUTPUT CURRENT vs. VDS  
XC61FN2512�  
XC61FN3512�  
XC61FN3512�  
1400  
1200  
1000  
800  
600  
400  
200  
0
1200  
1000  
800  
60  
50  
40  
30  
20  
10  
0
Ta=25℃�  
Ta=25℃�  
Ta=25℃�  
V
IN =0.8V  
V
IN =3.0V  
2.5V  
V
IN =0.8V  
0.7V  
600  
0.7V  
2.0V  
400  
1.5V  
200  
2
0
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5  
VDS (V)  
V
DS (V)  
V
DS (V)  
(5) N-CHANNEL DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE  
XC61FN1612�  
XC61FN2512�  
XC61FN3512�  
15.0  
12.5  
10.0  
7.5  
25  
20  
15  
10  
5
40  
35  
30  
25  
20  
15  
10  
5
V
DS=0.5V  
Ta=-30℃�  
VDS=0.5V  
VDS=0.5V  
Ta=-30℃�  
Ta=-30℃�  
80℃�  
25℃�  
80℃�  
25℃�  
80℃�  
25℃�  
5.0  
2.5  
0.0  
0.0  
0
0.0  
0
0.5  
1.0  
1.5  
2.0 2.5  
3.0  
0.5  
1.0  
1.5  
2.0  
0
1.0  
2.0  
3.0  
4.0  
Input Voltage: VIN (V)  
Input Voltage: VIN (V)  
Input Voltage: VIN (V)  
(6) P-CHANNEL DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE  
XC61FC2712�  
XC61FC4412�  
20  
18  
16  
14  
12  
10  
8
20  
18  
16  
14  
12  
10  
8
Ta=25℃�  
Ta=25℃�  
V
DS =2.1V  
VDS =2.1V  
1.5V  
1.0V  
1.5V  
1.0V  
0.5V  
6
6
0.5V  
4
4
2
2
0
0
0.0  
2.0  
4.0  
6.0  
8.0  
10.0  
0.0  
2.0  
4.0  
6.0  
8.0  
10.0  
Input Voltage: VIN(V)  
Input Voltage: VIN(V)  
(7) AMBIENT TEMPERATURE vs. TRANSIENT DELAY TIME  
XC61FC3012�  
XC61FC3042�  
XC61FC3052�  
200  
150  
100  
50  
400  
320  
240  
160  
80  
50  
40  
30  
20  
10  
0
-30  
-10  
10  
30  
50  
70  
-30  
-10  
10  
30  
50  
70  
-30  
-10  
10  
30  
50  
70  
Ambient Temp.: Ta(℃)  
Ambient Temp.: Ta(℃)  
Ambient Temp.: Ta(℃)  
167  
02S_04XC61F 02.09.12 14:04 ページ 168  
XC61F Seires  
(8) INPUT vs. TRANSIENT DELAY TIME  
XC61FC2712�  
230  
200  
170  
140  
110  
80  
Ta=25℃�  
2
50  
0.0  
2.0  
4.0  
6.0  
8.0  
10.0  
Input Voltage: VIN (V)  
168  

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