XC61HC5952MR-G [TOREX]
Power Management Circuit, Fixed, +5.9VV, CMOS;型号: | XC61HC5952MR-G |
厂家: | Torex Semiconductor |
描述: | Power Management Circuit, Fixed, +5.9VV, CMOS |
文件: | 总13页 (文件大小:549K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
XC61HSeries
ETR0212-004
Voltage Detector with Delay Circuit Built-In
■GENERAL DESCRIPTION
The XC61H series is a highly accurate, low power consumption CMOS voltage detector with a delay circuit. Detect voltage is
accurate with minimal temperature drift. Output configurations are available in both CMOS and N-channel open drain.
Since the full delay circuit is built-in, an external delay-time capacitor is not necessary so that high density mounting is possible.
■FEATURES
■APPLICATIONS
Detect Voltage Accuracy : ± 2%
●Microprocessor reset circuitry
●System battery life and charge voltage monitors
●Memory battery back-up circuits
●Power-on reset circuits
Low Power Consumption
Detect Voltage Range
Operating Voltage Range
: 1.0μA(TYP.)[ VIN=2.0V ]
1.6V ~ 6.0V (0.1V increments)
: 0.7V ~ 10.0V
:
Detect Voltage Temperature Characteristics
: ±100ppm/℃(TYP.)
Built-In Release Delay time: 1ms (MIN.)
50ms (MIN.)
●Power failure detection
●Delay circuitry
80ms (MIN.)
Output Configuration
Operating Ambient Temperature
Package
:
:
N-ch open drain output or CMOS
30℃~+80℃
:
SOT-23
Environmentally Friendly : EU RoHS Compliant, Pb Free
■TYPICAL PERFORMANCE
■TYPICAL APPLICATION CIRCUITS
CHARACTERISTICS
●Release Delay Time (tDR) vs. Ambient Temperature
μP
XC61HC3012
VIN
R pull
RESETB
RESETB
2
INPUT
VIN
3
VSS
VSS
1
XC61HN series
Rpull is not necessary with CMOS output products
Ambient Temperature: Ta (℃)
1/13
XC61H Series
■PIN CONFIGURATION
■PIN ASSIGNMENT
PIN NUMBER
PIN NAME
SOT-23
FUNCTION
1
2
3
VSS
RESETB
VIN
Ground
Output
Supply Voltage Input
OP VIEW)
■PRODUCT CLASSIFICATION
●Ordering Information
(*1)
XC61H①②③④⑤⑥⑦-⑧
DESIGNATOR
ITEM
SYMBOL
DESCRIPTION
C
CMOS output
①
Output Configuration
N
N-ch open drain output
e.g. 2.5V → ②2 , ③5
50ms ~ 200ms
②③
Detect Voltage (VDF
)
16 ~ 60
1
4
5
2
④
⑤
Release Delay Time
Detect Accuracy
80ms ~ 400ms
1ms ~ 50ms
±2.0%(*2)
Package
(*1)
⑥⑦-⑧
MR-G
SOT-23 (3000/Reel)
(Oder Unit)
(*1) The ”-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
(*2) No parts are available with an accuracy of ± 1%
■BLOCK DIAGRAMS
(2)N-ch open drain output
(1)CMOS output
2/13
XC61H
Series
■ABSOLUTE MAXIMUM RATINGS
Ta=25℃
PARAMETER
Input Voltage
Output Current
SYMBOL
RATINGS
VSS -0.3 ~ 12.0
50
UNITS
V
VIN
IOUT
mA
CMOS
VSS-0.3 ~VIN+0.3
VSS -0.3 ~ 12
250
Output Voltage
VRESETB
V
N-ch open drain output
SOT-23
Power Dissipation
Pd
mW
℃
Operating Ambient Temperature
Storage Temperature
Topr
Tstg
-30~+80
-40~+125
℃
Ta = 25℃
■ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN.
VDF(T)
x 0.98
VDF
TYP.
VDF(T)
VDF
MAX.
VDF(T)
x 1.02
VDF
UNITS
V
CIRCUIT
VDF
①
①
Detect Voltage
VHYS
V
Hysteresis Width
x 0.02 x 0.05 x 0.08
VIN = 1.5V
-
0.9
1.0
1.3
1.6
2.0
-
2.6
3.0
3.4
3.8
4.2
10.0
-
VIN = 2.0V
VIN = 3.0V
-
Supply Current (*1)
Operating Voltage
-
ISS
μA
②
①
③
VIN = 4.0V
-
VIN = 5.0V
-
VIN
VDF=1.6V~6.0V
0.7
1.0
3.0
5.0
6.0
7.0
V
VIN = 1.0V
VIN = 2.0V
VIN = 3.0V
VIN = 4.0V
VIN = 5.0V
2.2
7.7
10.1
11.5
13.0
-
N-ch, VDS = 0.5V
-
Output Current
IOUT
mA
-
-
P-ch, VDS=2.1V
(CMOS Output)
VIN = 8.0V
-10.0
-2.0
④
③
CMOS Output
VIN=VDF x 0.9V, VRESETB=0V
-
-0.01
-
Leakage
Current
(Pch)
ILEAK
μA
Nch Open
VIN=10.0V, VRESETB=10.0V
-
-
0.01
0.1
-
Drain Output
Δ
VDF
/
Detect Voltage
Temperature Characteristics
-30℃≦Topr≦80℃
±100
ppm/℃
①
⑤
(Δ
Topr
・
VDF)
50
80
1
-
-
-
200
400
50
Release Delay Time
(VDR → RESETB inversion)
tDR
VIN changes from 0.6V to 10V
ms
VDF (T) is nominal detect voltage value
Release Voltage: VDR = VDF + VHYS
(*1) The supply current during power-start until output being stable (during release operation) is 2μA greater with comparison to the period
after the completion of release operation because of the shoot-through current in delay current.
3/13
XC61H Series
■OPERATIONAL EXPLANATION
●CMOS output
①
An input voltage VIN starts higher than the release voltage VDR. Then, VIN voltage will gradually fall. When VIN voltage is
higher than detect voltage VDF, output voltage RESETB is equal to the VIN voltage.
*Note that high impedance exists at RESETB with the N-channel open drain output configuration. If the RESETB pin is
pulled up, RESETB will be equal to the pull up voltage.
②
③
When VIN falls below VDF, RESETB will be equal to ground voltage VSS level (detect state).
* Note that this also applies to N-channel open drain output configurations.
When VIN falls to a level below that of the minimum operating voltage VMIN, output will become unstable.
*When the output pin is generally pulled up with N-channel open drain output configurations, output will be equal to pull
up voltage.
④
When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), RESETB will be equal to
VSS until VIN reaches the VDR level.
⑤
⑥
Although VIN will rise to a level higher than VDR, RESETB maintains ground voltage level via the delay circuit.
After taking a release delay time, VIN voltage will be output at the RESETB pin.
*High impedance exists with the N-channel open drain output configuration and that voltage will be dependent on pull up.
Notes:
1. The difference between VDR and VDF represents the hysteresis width.
2. Release delay time (tDR) represents the time it takes until when VIN voltage appears at RESETB pin once the input
voltage has exceeded the VDR level.
●Timing Chart
Output Voltage (RESETB)
Release Delay Time (tDR
)
4/13
XC61H
Series
■NOTES ON USE
1. Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising
phenomenon, the IC is liable to malfunction should the ratings be exceeded.
2. When a resistor is connected between the VIN pin and the power supply with CMOS output configurations, irregular
oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. It is therefore recommend that no
resistor be added. (refer to Figure 1 below)
3. When a resistor (RIN) is connected between the VIN pin and the power supply with CMOS output configurations,
irrespective of N-ch open drain output configurations, oscillation may occur as a result of shoot-through current at the time
of voltage release even if load current (IOUT) does not exist. (refer to Figure 2 below)
4. If a resistor (RIN) must be used, then please use with as small a level of input impedance as possible in order to control the
occurrences of oscillation as described above. Further, please ensure that RIN is less than 10kΩ and that CIN is more than
0.1μF, please test with the actual device. However, N-ch open drain output only. (Figure 1).
5. With a resistor RIN connected between the VIN pin and the power supply, the VIN pin voltage will be getting lower than the
power supply voltage as a result of the IC's supply current flowing through the VIN pin.
6. Depending on circuit's operation, release delay time of this IC can be widely changed due to upper limits or lower limits of
operational ambient temperature.
7. Torex places an importance on improving our products and its reliability.
However, by any possibility, we would request user fail-safe design and post-aging treatment on system or equipment.
●Irregular Oscillations
(1) Irregular oscillation as a result of load current with the CMOS output configuration:
When the voltage applied at power supply, release operations commence and the detector's output voltage
increases. Load current (IOUT) will flow through RL. Because a voltage drop (RIN x IOUT) is produced at the RIN resistor,
located between the power supply and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will
also lead to a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level,
detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at
RIN will disappear, the voltage level at the VIN pin will rise and release operations will begin over again.
Irregular oscillation may occur with this "release - detect - release" repetition.
Further, this condition will also appear via means of a similar mechanism during detect operations.
(2) Irregular oscillation as a result of shoot-through current:
Since the XC61H series are CMOS ICS, shoot-through current will flow when the IC's internal circuit switching
operates (during release and detect operations). Consequently, irregular oscillation is liable to occur during release
voltage operations as a result of output current which is influenced by this shoot-through current (Figure 3).
Since hysteresis exists during detect operations, irregular oscillation is unlikely to occur.
XC61HC Series
XC61HN Series
Power Supply
Power Supply
Figure 1 Use of input resistor RIN
5/13
XC61H Series
■NOTES ON USE (Continued)
●Irregular Oscillations (Continued)
XC61HC Series
XC61H C Series
RIN
RIN ×IOU T
Power Supply
IOUT
VIN
V
RESETB
Voltage drop
VSS
RL
Figure 2 Irregular Oscillation by output current
XC61HC Series
XC61HN Series
XC61HN Series
XC61HC Series
RIN
Power Supply
RIN×ISS
*
VIN
RESETB
Voltage drop
VSS
ISS*
(includes through current)
Figure 3 Irregular Oscillation by shoot-through current
6/13
XC61H
Series
■TEST CIRCUITS
●Circuit ①
●Circuit ②
A
*R
220kΩ
VIN
VSS
VIN
VIN
VIN
RESETB
V
RESETB
VSS
V
●Circuit ③
●Circuit ④
VIN
VDS
VIN
VIN
VIN
A
A
RESETB
RESETB
VSS
VSS
VDS
●Circuit ⑤
*R
220kΩ
VIN
VSS
measurement of
waveform
RESETB
*R is not necessary with CMOS output products.
7/13
XC61H Series
■TYPICAL PERFORMANCE CHARACTERISTICS
XC61HN3512
XC61HN1612
XC61HN2512
XC61HN1612
XC61HN2512
(3) Detect Voltage, Release Voltage vs. Input Voltage
XC61HN1612
XC61HN2512
XC61HN3512
R-pull:100kΩ
Ta=-30℃
25℃
R-pull:100kΩ
Ta=-30℃
25℃
R-pull:100kΩ
Ta=-30℃
25℃
80℃
80℃
80℃
XC61HN1612
XC61HN1612
XC61HN2512
8/13
XC61H
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
XC61HN3512
XC61HN3512
XC61HN2512
XC61HN1612
XC61HN2512
XC61HN3512
XC61HC2712
XC61HC4412
(7)Ambient Temperature vs. Release Delay Time (tDR
)
XC61HC3052
XC61HC3042
XC61HC3012
9/13
XC61H Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(8)Input Voltage vs. Release Delay Time (tDR
)
XC61HC2712
10/13
XC61H
Series
■PACKAGING INFORMATION
●SOT-23
11/13
XC61H Series
■MARKING RULE
●SOT-23
① represents product series
MARK
8
PRODUCTS SERIES
XC61H*******-G
② standard:represents output configuration and integer number of detect voltage
CMOS output (XC61HC series)
N-channel open drain (XC61HN series)
VOLTAGE
VOLTAGE
MARK
(V)
MARK
(V)
A
B
C
D
E
F
1. X
2. X
3. X
4. X
5. X
6. X
P
R
S
T
1. X
2. X
3. X
4. X
5. X
6. X
U
V
③ represents decimal number of detect voltage and delay time.
MARK
DELAY TIME
DETECT
VOLTAGE
(V)
DELAY TIME
50ms~200ms
DELAY TIME
1ms~50ms
80ms~400ms
(XC61H***4***-G)
A
(XC61H***1***-G)
(XC61H***5***-G)
X.0
X.1
X.2
X.3
X.4
X.5
X.6
X.7
X.8
X.9
0
1
2
3
4
5
6
7
8
9
N
P
R
S
T
B
C
D
E
F
U
V
X
Y
Z
H
K
L
M
④ represents production lot number
0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated.
(G, I, J, O, Q,W excluded)
*No character inversion used.
12/13
XC61H
Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics. Consult us, or our representatives
before use, to confirm that the information in this datasheet is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this datasheet.
3. Please ensure suitable shipping controls (including fail-safe designs and aging
protection) are in force for equipment employing products listed in this datasheet.
4. The products in this datasheet are not developed, designed, or approved for use with
such equipment whose failure of malfunction can be reasonably expected to directly
endanger the life of, or cause significant injury to, the user.
(e.g. Atomic energy; aerospace; transport; combustion and associated safety
equipment thereof.)
5. Please use the products listed in this datasheet within the specified ranges.
Should you wish to use the products under conditions exceeding the specifications,
please consult us or our representatives.
6. We assume no responsibility for damage or loss due to abnormal use.
7. All rights reserved. No part of this datasheet may be copied or reproduced without the
prior permission of TOREX SEMICONDUCTOR LTD.
13/13
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