XC9101C30AKL_技术文档

04S_01XC9101/9102新規 02.09.12 14:37 ページ 387

Series

PWM Controlled Step-Up DC/DC Controllers

ꢁInput Voltage Range :2.5V ~ 20V

ꢁOutput Voltage Range

■Applications

ꢀMobile, Cordless phones

ꢀPalm top computers, PDAs

ꢀPortable games

:2.5V ~ 16V

(Fixed Voltage Type)

:30V + (Adjustable Type)

ꢀCameras, Digital cameras

ꢀLaptops

ꢁOscillation Frequency Range

:100kHz ~ 600kHz

:up to 1.5A

ꢁOutput Current

4

ꢁCeramic Capacitor Compatible

ꢁMSOP-8A Package

■General Description

The XC9101 series are step-up multiple current and voltage feedback

DC/DC controller ICs. Current sense, clock frequencies and amp

feedback gain can all be externally regulated.

■Features

ꢀStable Operations via Current & Voltage Multiple Feedback

ꢀUnlimited Options for Peripheral Selection

ꢀCurrent Protection Circuit

A stable power supply is possible with output currents of up to 1.5A.

With output voltage fixed internally, VOUT is selectable in 0.1V steps

within a 2.5V - 16.0V range ( 2.5%).

ꢀCeramic Capacitor Compatible

For output voltages outside this range, we recommend the FB version

which has a 0.9V internal reference voltage. Using this version, the

required output voltage can be set-up using 2 external resistors.

Switching frequencies can also be set-up externally within a range of

100~600 kHz and therefore frequencies suited to your particular

application can be selected.

With the current sense function, peak currents (which flow through

the driver transistor and the coil) can be controlled. Soft-start time can

be adjusted using external resistor and capacitor.

During shutdown (CE pin =L), consumption current can be reduced to

as little as 0.5µA (TYP.) or less.

■Typical Application Circuit

■Typical Performance

Characteristic

U3FWJ44N

22μH

VOUT:5.0V FOSC:180kHz

XP161A1355PR

100

Vss 8

1 EXT

VOUT 7

2 Isen

3 VIN

50mΩ�

150kΩ�

GAIN 6

CLK 5

80

4.2V

94μF

4 CE/SS

220μF�

+10μF

0.1μF

470pF

3.3V

22KΩ�

1μF

180pF

60

40

VIN=2.5V

1

10

100

1000

Output Current : IOUT (mA)

387

04S_01XC9101/9102新規 02.09.12 14:38 ページ 388

XC9101Series

■Pin Configuration

■Pin Assignment

PIN NUMBER

PIN NAME

FUNCTION

Driver

EXT

Isen

8

7

6

5

1

2

3

4

VSS

1

2

3

4

5

6

7

8

EXT

VOUT／FB

Isen

Current Sense

Power Input

CE/Soft Start

Clock Input

VIN

CC／GAIN

CLK

V^IN

CE／SS

CLK

MSOP-8A�

(TOP VIEW)

CC／GAIN

V^OUT／FB

V^SS

Phase Compensation

Voltage Sense

Ground

■Product Classification

ꢀOrdering Information

4

ＸＣ９１０１�

qwerty

SYMBOL

VOUT/FB

VOUT (Fixed Voltage Type)

FB

Soft-start

DISIGNATOR

C

D

Soft-start externally set-up

q

Output Voltage : For voltages above 10V, see below :�

10=A, 11=B, 12=C, 13=D, 14=E, 15=F, 16=H�

e.g. VOUT=2.3V→w=2, e=3 VOUT=13.5V→w=D, e=5�

FB products→w=0, e=9 fixed

we

Number

A

K

R

L

Adjustable Frequency

MSOP-8A

r

t

E�mbossed tape. Standard Feed

Embossed tape. Reverse Feed

y

�

The standard output voltages of the XC9101C series are 2.5V, 3.3V, and 5.0V. �

Voltages other than those listed are semi-custom.

■Packaging Information

ꢀMSOP-8A

+0.08

-0.02

0.15

3.00±0.10

0.30 ⁺^-0⁰^.^.⁰⁰²⁸

(0.65)

388

04S_01XC9101/9102新規 02.09.12 14:38 ページ 389

XC9101

Series

■Marking

MSOP-8A

q Represents the product series

DESIGNATOR

4

PRODUCT NAME

XC9101 AK

***

*

① ② ③ �

④ ⑤ ⑥ �

w Represents product type, DC/DC converter

DESIGNATOR

TYPE

PRODUCT NAME

XC9101C AK

C

D

VOUT, CE PIN

FB, CE PIN

**

*

XC9101D09AK

*

e Represents integral number of output voltage, or FB type

4

DESIGNATOR VOLTAGE（V）�

PRODUCT NAME

XC9101C2 AK

PRODUCT NAME

XC9101CA AK

2

3

4

5

6

7

8

9

0

2. X

3. X

A

B

C

D

E

F

10. X

11. X

12. X

13. X

14. X

15. X

16. X

*

XC9101CB AK

XC9101C3 AK

*

XC9101CC AK

XC9101C4 AK

4. X

*

XC9101CD AK

*

XC9101C5 AK

5. X

*

XC9101CE AK

XC9101C6 AK

*

6. X

*

XC9101CF AK

XC9101C7 AK

7. X

*

XC9101CH AK

XC9101C8 AK

*

H

8. X

*

XC9101C9 AK

9. X

*

XC9101D09AK

FB products

*

r Represents decimal number of output voltage

DESIGNATOR

VOLTAGE（V）�

PRODUCT NAME

XC9101C 0AK

0

3

9

X. 0

X. 3

*

XC9101C 3AK

*

XC9101D09AK

FB products

*

t Represents oscillation frequency's control type

DESIGNATOR

A

TYPE

PRODUCT NAME

XC9101 AK

Adjustable Frequency

***

*

389

04S_01XC9101/9102新規 02.09.12 14:38 ページ 390

XC9101Series

■Block Diagram

EXT timming�

controll�

logic

Current�

Limit�

Protection

VSS

EXT

VOUT

R1

R2

Verr

ISEN

VIN

Limitter comp.

MIX

PWM

CC/GAIN

Internal�

Voltage�

Regulator

Ierr

Ramp Wave,�

Internal CLK�

generator

2.0V�

to internal�

circuit

4

Sampling

CE,UVLO�

to internal�

circuit

CLK

Chip Enable,�

Soft Start up,�

U.V.L.O.

CE/SS

0.9V

Vref generator

■Absolute Maximum Ratings

Ta=25℃�

RATINGS

PARAMETER

UNITS

Ｖ�

SYMBOL

VEXT

VIsen

VIN

EXT Pin Voltage�

Isen Pin Voltage�

VIN Pin Voltage�

－0.3～VDD＋0.3

－0.3～＋22

－0.3～VDD＋0.3

－0.3～＋22

±100

CE/SS Pin Voltage�

CLK Pin Voltage�

CC/GAIN Pin Voltage�

VOUT/FB Pin Voltage�

EXT Pin Current�

VCE

VCLK

VCC

VOUT/FB

IEXT

mA

Continuous Total Power Dissipation� Pd

150

mW

℃�

Operating Ambient Temperature�

Storage Temperature

Topr

Tstg

－40～＋85

－55～＋125

390

04S_01XC9101/9102新規 02.09.12 14:38 ページ 391

XC9101

Series

■Electrical Characteristics

XC9101C33AKR

Ta=25℃�

MAX. UNITS CIRCUITS

SYMBOL

VOUT

PARAMETER

CONDITIONS

�

MIN.

3.218

20

TYP.

3.300

－�

IOUT=300mA

VIN=2.5V �

3.382

－�

2.5

V

q

Output Voltage�

�

Maximum Operating Voltage� VINmax

�

－�

VINmin

－�

�

Minimum Operating Voltage�

�

150

255

176

μA

w

Supply Current 1�

�

IDD1

VOUT=CE=Set Output Voltage×0.95V

VIN=2.5V, CE=VIN�

�

IDD2

ISTB

90�

Supply Current 2�

�

VOUT=Set Output Voltage×1.05V

VIN=2.5V, CE=VOUT=VSS

RT=10.0kΩ, CT=220pF

�

0.5�

Stand-by Current�

�

280

�

2.0

380

�

μA

w

e

CLK Oscillation Frequency� FOSC

�

330�

kHz

�

ΔFOSC

�

Frequency Input Stability�

VIN=2.5V～20V

±5

%

e

4

ΔVIN･FOSC

�

Frequency Temperature�

Fluctuation�

VIN=2.5V

�

ΔFOSC

ΔTopr･FOSC

MAXDTY

MINDTY

ILIM

±5�

Topr=－40～+85℃�

�

85

�

Maximum Duty Cycle�

89

0

VOUT=Set Voltage×0.95V

VOUT=Set Voltage×1.05V

VIN pin voltage－ISEN pin voltage

VIN=2.5V, ISEN=2.5V

79

%

r

y

t

�

Minimum Duty Cycle�

�

150

7

%

�

Current Limiter Voltage�

90

220

13

mV

μA

�

4.5

－0.1

ISEN Current

IISEN

ICEH

CE "High" Current�

CE=VIN=2.5V, VOUT=0V

0�

0.1

�

0�

CE=0V, VIN=2.5V, VOUT=0V

Existence of CLK Oscillation,

VOUT=0V, CE : Voltage applied

Disappearance of CLK Oscillation,

CE "Low" Current�

ICEL

�

0.6

V

CE "High" Voltage

VCEH

t

r

CE "Low" Voltage�

�

VCEL

0.2

58

45

V

VOUT=0V, CE : Voltage applied

EXT=VIN－0.4V, CE=VIN=2.5V�

VOUT=Set voltage×0.95V

EXT "High" ON�

Resistance

REXTH

31�

�

Ω�

EXT "Low" ON�

Resistance

EXT=0.4V, CE=VIN=2.5V �

VOUT=Set voltage×1.05

REXTL

27�

�

88�

Efficiency *1

EFFI

TSS

�

%

q

�

10

Soft-Start Time

Connect CSS and RSS, CE : 0V→2.5V

5

20

ms

CC/GAIN Pin�

RCCGAIN

400�

�

kΩ�

u

Output Impedance

VIN = 2.5V unless specified�

*1 : EFFI = {[(Output Voltage) × (Output Current)] ÷ [(Input Voltage) × (Input Current)]} × 100�

*2 : The capacity range of the capacitor used to set the external CLK frequency is 150 220pF

~

391

04S_01XC9101/9102新規 02.09.12 14:38 ページ 392

XC9101Series

XC9101C50AKR

Ta=25℃�

SYMBOL

PARAMETER

Output Voltage

CONDITIONS

MAX. UNITS CIRCUITS

�

MIN.

4.875

20

TYP.

5.000

－�

IOUT=300mA

VIN=3.0V �

5.125

－�

2.5

V

q

VOUT

VINmax

VINmin

Maximum Operating Voltage

Minimum Operating Voltage

�

－�

�

160

270

176

μA

w

Supply Current 1

Supply Current 2

IDD1

IDD2

VOUT=CE=Set Output Voltage×0.95V

VIN=3.0V, CE=VIN�

�

90�

VOUT=Set Output Voltage×1.05V

VIN=3.0V, CE=VOUT=VSS

RT=10.0kΩ, CT=220pF

�

Stand-by Current

ISTB

FOSC

�

280

�

0.5�

2.0

380

�

μA

w

e

CLK Oscillation Frequency

�

330�

kHz

ΔFOSC

ΔVIN･FOSC

�

Frequency Input Stability

VIN=2.5V～20V

±5

%

e

�

VIN=3.0V

�

ΔFOSC

ΔTopr･FOSC

MAXDTY

MINDTY

ILIM

Frequency Temperature

Fluctuation

4

±5�

Topr=－40～+85℃�

�

85

Maximum Duty Cycle

Minimum Duty Cycle

Current Limiter Voltage

ISEN Current

89

0

VOUT=Set Voltage×0.95V

VOUT=Set Voltage×1.05V

VIN pin voltage－ISEN pin voltage

VIN=3.0V, ISEN=3.0V

79

%

r

y

t

�

150

7

%

90

220

13

mV

μA

4.5

－0.1

IISEN

ICEH

CE "High" Current

CE "Low" Current

CE=VIN=3.0V, VOUT=0V

0�

0.1

�

0�

CE=0V, VIN=3.0V, VOUT=0V

Existence of CLK Oscillation,

VOUT=0V, CE : Voltage applied

Disappearance of CLK Oscillation,

ICEL

�

CE "High" Voltage

CE "Low" Voltage

VCEH

0.6

�

V

t

r

VCEL

0.2

51

V

VOUT=0V, CE : Voltage applied

EXT=VIN－0.4V, CE=VIN=3.0V�

VOUT=Set voltage×0.95V

�

EXT "High" ON

Resistance

REXTH

27�

�

Ω�

EXT=0.4V, CE=VIN=3.0V �

EXT "Low" ON

Resistance

REXTL

25�

37

�

VOUT=Set voltage×1.05V

�

87�

Efficiency *1

EFFI

TSS

%

q

�

5�

Soft-Start Time

CC/GAIN Pin

Output Impedance

Connect CSS and RSS, CE : 0V→3.0V

ms

�

RCCGAIN

400�

kΩ�

u

�

V

IN = 3.0V unless specified

�

*1 : EFFI = {[(Output Voltage) × (Output Current)] ÷ [(Input Voltage) × (Input Current)]} × 100

*2 : The capacity range of the capacitor used to set the external CLK frequency is 150 ~ 220pF

�

392

04S_01XC9101/9102新規 02.09.12 14:38 ページ 393

XC9101

Series

XC9101D09AKR

Ta=25℃�

SYMBOL

PARAMETER

CONDITIONS

MIN.

0.8775

20

TYP.

0.9

MAX.

0.9225

－�

2.5

UNITS CIRCUITS

�

IOUT=300mA

V

q

w

e

Output Voltage

Maximum Operating Voltage

Minimum Operating Voltage

Supply Current 1

VOUT

VINmax

VINmin

IDD1

－�

－��

�

V

�

150

VIN=2.5V, VIN=CE, FB=0.9×0.95V

VIN=2.5V, CE=VIN, VOUT=0.9×1.05V

VIN=2.5V, CE=FB=VSS

255

176

2.0

μA

kHz

IDD2

�

90�

Supply Current 2

Stand-by Current

ISTB

�

0.5�

�

CLK Oscillation Frequency

FOSC

�

330�

RT=10.0kΩ, CT=220pF

280

�

380

�

ΔFOSC

ΔVIN･FOSC

�

Frequency Input Stability

VIN=2.5V～20V

±5

%

e

�

Frequency Temperature�

Fluctuation

VIN=2.5V

�

ΔFOSC

ΔTopr･FOSC

MAXDTY

MINDTY

ILIM

±5�

Topr=－40～+85℃�

�

85

Maximum Duty Cycle

Minimum Duty Cycle

Current Limiter Voltage

ISEN Current�

V

OUT=0.9×0.95V

OUT=0.9×1.05V

79

%

r

y

t

89

0

4

V

�

150

7

%

VIN pin voltage－ISEN pin voltage

VIN=2.5V, ISEN=2.5V

90

220

13

mV

μA

4.5

－0.1

IISEN

ICEH

�

CE "High" Current

CE=VIN=2.5V, FB=0V

0�

0.1

�

0�

CE=0V, VIN=2.5V, FB=0V

Existence of CLK Oscillation,�

CE "Low" Current

CE "High" Voltage

ICEL

�

VCEH

0.6

�

V

t

r

V

OUT=0V, CE : Voltage applied

Disappearance of CLK Oscillation,�

OUT=0V, CE : Voltage applied�

CE "Low" Voltage

VCEL

REXTH

REXTL

0.2

58

45

V

E�XT=VIN－0.4V, CE=VIN�

�

EXT "High" ON Resistance

EXT "Low" ON Resistance

31�

�

Ω�

VOUT=Set voltage×0.95V�

�

EXT=0.4V, CE=VIN�

27�

VOUT=Set voltage×1.05V�

�

88�

Efficiency *1

EFFI

TSS

�

5�

�

%

q

�

10

Soft-Start Time�

Connect CSS and RSS, CE : 0V→2.5V

20�

ms

�

CC/GAIN Pin

RCCGAIN

400�

�

kΩ�

u

Output Impedance

�

VIN = 2.5V unless specified�

External Components : RFB1=200kΩ, RFB2=100kΩ, CFB=82pF�

*1 : EFFI = {[(Output Voltage) × (Output Current)] ÷ [(Input Voltage) × (Input Current)]} × 100�

*2 : The capacity range of the capacitor used to set the external CLK frequency is 150

~ 220pF

393

04S_01XC9101/9102新規 02.09.12 14:38 ページ 394

XC9101Series

■Typical Application Circuits

XC9101C33AKR

22μH

SD

3.3V

NMOS

EXT

Isen

1

2

VSS

8

7

VOUT

20mΩ�

2.5V

6

5

3

4

VIN

CC/GAIN

CLK

470pF

100kΩ�

0.1μF

CE/SS

220μF

47μF(OS) +220μF(any)

180pF

～33kΩ�

1μF

4

NMOS

Coil

: XP161A1355PR

: 22µH(CR105 SUMIDA)

: 20mΩ for Isen (NPR1 KOA), 33kΩ(trimmer) for CLK, 100kΩ for SS

Resistor

Capacitors : 180pF(ceramic) for CLK, 470pF(ceramic) for CC/GAIN, 0.1µF(ceramic) for SS,1µF(ceramic) for Bypass

47µF(OS)+220µF(any) for CL, 220µF(any) for C^IN

SD

: U3FWJ44N (TOSHIBA)

XC9101C50AKR

22μH

SD

5.0V

NMOS

EXT

Isen

1

2

VSS

8

7

VOUT

20mΩ�

6

5

3

4

VIN

CC/GAIN

CLK

470pF

100kΩ�

0.1μF

CE/SS

220μF

3.0V

47μF(OS) +220μF(any)

180pF

～33kΩ�

1μF

NMOS

Coil

: XP161A1355PR

: 22µH(CR105 SUMIDA)

: 20mΩ for Isen (NPR1 KOA), 33kΩ(trimmer) for CLK, 100kΩ for SS

Resistor

Capacitors : 180pF(ceramic) for CLK, 470pF(ceramic) for CC/GAIN, 0.1µF(ceramic) for SS,1µF(ceramic) for Bypass

47µF(OS)+220µF(any) for CL, 220µF(any) for C^IN

SD

: U3FWJ44N (TOSHIBA)

394

04S_01XC9101/9102新規 02.09.12 14:38 ページ 395

XC9101

Series

XC9101D09AKR

22μH

SD

NMOS

CFB

EXT

Isen

1

2

8

7

6

VSS

FB

RFB1

10mΩ�

3

4

CC/GAIN

CLK

RFB2

VIN

150kΩ�

0.1μF

470pF

CE/SS

5

220μF

47μF(OS) +220μF(any)

～33kΩ�

180pF

1μF

4

NMOS

Coil

: XP161A11A1PR

: 22µH(CDRH127 SUMIDA)

: 10mΩ for Isen (NPR1 KOA), 33kΩ(trimmer) for CLK, 150kΩ for SS

Resistor

Capacitors : 180pF(ceramic) for CLK, 470pF(ceramic) for CC/GAIN, 0.1µF(ceramic) for SS,1µF(ceramic) for Bypass

47µF(OS)+220µF(any) for CL, 220µF(any) for C^IN

SD

: U5FWJ44N (TOSHIBA)

VOUT

RFB1

RFB2

CFB

: 16V

: 560kΩ

: 33kΩ

: 27pF

VOUT

RFB1

RFB2

CFB

: 20V

: 470kΩ

: 22kΩ

: 33pF

395

04S_01XC9101/9102新規 02.09.12 14:38 ページ 396

XC9101Series

■Operational Explanation

Step-up DC/DC converter controllers of the XC9101 series carry out pulse width modulation (PWM) according to the multiple feedback signals

of the output voltage and coil current.

The internal circuits consist of different blocks that operate at VIN or the stabilized power (2.0 V) of the internal regulator. The output setting

voltage of the type C controller and the FB pin voltage (Vref = 0.9 V) of type D controller have been adjusted and set by laser-trimming.

<Clock>

With regard to clock pulses, a capacitor and resistor connected to the CLK pin generate ramp waveforms whose top and bottom are 0.7V and

0.15V, respectively. The frequency can be set within a range of 100 to 600 kHz externally (refer to the "Functional Settings" section for further

information). The clock pulses are processed to generate a signal used for synchronizing internal sequence circuits.

The Verr amplifier is designed to monitor the output voltage. A fraction of the voltage applied to internal resistors R1, R2 in the case of a type C

controller, and the voltage at the FB pin in the case of a type D controller, are fed back and compared with the reference voltage. In response to

feedback of a voltage lower than the reference voltage, the output voltage of the Verr amplifier increases.

The output of the Verr amplifier enters the mixer via resistor (RVerr). This signal works as a pulse width control signal during PWM operations.

By connecting an external capacitor and resistor through the CE/GAIN pin, it is possible to set the gain and frequency characteristics of Verr

4

amplifier signals (refer to the "Functional Settings" section for further information).

The Ierr amplifier monitors the coil current. The potential difference between the VIN and Isen pins is sampled at each switching operation.

Then the potential difference is amplified or held, as necessary, and input to the mixer. The Ierr amplifier outputs a signal ensuring that the

greater the potential difference between the VIN and Isen pins, the smaller the switching current. The gain and frequency characteristics of this

amplifier are fixed internally.

The mixer modulates the signal sent from Verr by the signal from Ierr. The modulated signal enters the PWM comparator for comparison with

the sawtooth pulses generated at the CLK pin. If the signal is greater than the sawtooth waveforms, a signal is sent to the output circuit to turn

on the external switch.

The current flowing through the coil is monitored by the limiter comparator via the VIN and Isen pins. The limiter comparator outputs a signal

when the potential difference between the V^INand Isen pins reaches about 150 mV or more. This signal is converted to a logic signal and

handled as a DFF reset signal for the internal limiter circuit. When a reset signal is input, a signal is output immediately at the EXT pin to turn off

the MOS switch. When the limiter comparator sends a signal to enable data acceptance, a signal to turn on the MOS switch is output at the

next clock pulse. If at this time the potential difference between the VIN and Isen pins is large, operation is repeated to turn off the MOS switch

again. DFF operates in synchronization with the clock signal of the CLK pin.

Limiter signal

/RESET

PWM/PFM switching signal

CLK sync signal

D

Q

Output signal to EXT pin

CLK

PWM/PFM switching signal

The soft start function is made available by attaching a capacitor and resistor to the CE/SS pin. The Vref voltage applied to the Verr amplifier is

restricted by the start-up voltage of the CE/SS pin. This ensures that the Verr amplifier operates with its two inputs in balance, thereby

preventing the ON-TIME signal from becoming stronger than necessary. Consequently, soft start time needs to be set sufficiently longer than

the time set to CLK. The start-up time of the CE/SS pin equals the time set for soft start (refer to the "Functional Settings" section for further

information).

The soft start function operates when the voltage at the CE/SS pin is between 0V to 1.55V. If the voltage at the CE/SS pin doesn't start from 0V

but from a mid level voltage when the power is switched on, the soft start function will become ineffective and the possibilities of large rush

currents and ripple voltages occuring will be increased.

396

04S_01XC9101/9102新規 02.09.12 14:38 ページ 397

XC9101

Series

ꢀFunctional Settings

1. Soft Start

CE and soft start (SS) functions are commonly assigned to the CE/SS pin. The soft start function is effective until the voltage at the CE pin

reaches approximately 1.55 V rising from 0 V. Soft start time is approximated by the equation below according to values of Vcont, Rss, and

Css.

T = -Css × Rss × ln((Vcont - 1.55)/Vcont)

Example: When C^SS= 0.1 µF, RSS = 470 kΩ, and Vcont = 5 V, T = -0.1 e^-6× 470 e³× ln ((5 - 1.55)/5) = 17.44 ms.

CE/SS pin

Rss

[Inside the IC]

CE,�

UVLO

Vref��

circuit�

To Verr amplifier

Vcont

Css

Set the soft start time to a value sufficiently longer than the period of a clock pulse.

4

> Circuit example 1: N-ch open drain

Vcont

[Inside the IC]

Rss

CE/SS pin

ON/OFF signal

Css

> Circuit example 2: CMOS logic (low current dissipation)

Vcont

[Inside the IC]

Rss

ON/OFF signal

CE/SS pin

Css

> Circuit example 3: CMOS logic (low current dissipation), quick off

Vcont

[Inside the IC]

CE/SS pin

Rss

ON/OFF signal

Css

397

04S_01XC9101/9102新規 02.09.12 14:38 ページ 398

XC9101Series

2. Oscillation Frequency

The oscillation frequency of the internal clock generator is approximated by the following equation according to the values of the capacitor and

resistor attached to the CLK pin. To stablize the IC's operation, set the oscillation frequency within a range of 100kHz to 600kHz. Select a value

for Cclk within a range of 150pF to 220pF and fix the frequency based on the value for Rclk.

f = 1/(-Cclk × Rclk × ln0.26)

Example: When Cclk = 220 pF and Rclk = 10 kΩ, f = 1/(-220e^-12× 10e³× ln(0.26)) = 337.43 kHz.

[Inside the IC]

CLK pin

Rclk

Cclk

CLK Generater

4

3. Gain and Frequency Characteristics of the Verr Amplifier

The gain at output and frequency characteristics of the Verr amplifier are adjusted by the values of the capacitor and resistor attached to the

CC/GAIN pin. It is generally recommended to attach a CC of 220 to 1,000 pF without RGAIN. The greater the CC value, the more stable the

phase and the slower the transient response. When using the IC with RGAIN connected, it should be noted that if the RGAIN resistance value

is too high, abnormal oscillation may occur during transient response time. The size of RGAIN should be carefully evaluated before connection.

[Inside the IC]

CC/GAIN pin

VOUT/FB

Verr

Vref

RGAIN

RVerr

CC

4. Current Limit

The current limit value is approximated by the following equation according to resistor RSEN inserted between the VIN and Isen pins. Double

function, current FB input and current limiting, is assigned to the Isen pin. The current limiting value is approximated by the following equation

according to the value for RSEN.

Ilpeak_limit = 0.15/Rsen

Example: When RSEN = 100 mΩ, Ilpeak_limit = 0.15/0.1 = 1.5 A

[Inside the IC]

Isen pin

Rsen

Limiter signal

Comparator with�

150ｍV offset

VIN pin

The inside error ampliphier sends feedback signal when the voltage occurs at RSEN resisitors because of the flow of coil current in order to

phase compensate. The more the RSEN value becomes larger, the more the error signal becomes bigger, and it could lead to an intermittent

oscillation. Please be careful if there is a problem with the application. When the regular operation, the voltage which occurs between RSEN

resistors because of coil peak should be set lower than the current limit voltage of 90mV (min.). For more details, please refer the notes on the

external components.

398

04S_01XC9101/9102新規 02.09.12 14:38 ページ 399

XC9101

Series

5. FB Voltage and Cfb

With regard to the XC9101D series, the output voltage is set by attaching externally divided resistors. The output voltage is determined by the

equation shown below according to the values of Rfb1 and Rfb2. In general, the sum of Rfb1 and Rfb2 should be 1 MEG Ω or less.

VOUT = 0.9 × (Rfb1 + Rfb2)/Rfb2

The value of Cfb (phase compensation capacitor) is approximated by the following equation according to the values of Rfb1 and fzfb. The value

of fzfb should be 10 kHz, as a general rule.

Cfb = 1/(2 × π × Rfb1 × fzfb)

Example: When Rfb1 = 455 kΩ and Rfb2 = 100 kΩ : V^OUT= 0.9 × (455 k + 100 k)/100 k = 4.995 V

: Cfb = 1/(2 × π × 455 k × 10 k) = 34.98 pF

[Inside the IC]

Output voltage

Cfb

Rfb1

Rfb2

FB pin

4

Verr

0.9V

Verr amplifier

■Directions for use

ꢀApplication Notes

1. The XC9101 series are designed for use with an output ceramic capacitor. If, however, the potential difference between input and output is

too large, a ceramic capacitor may fail to absorb the resulting high switching energy and oscillation could occur on the output side. If the

input-output potential difference is large, connect an electrolytic capacitor in parallel to compensate for insufficient capacitance.

2. The EXT pin of the XC9101 series is designed to minimize the through current that occurs in the internal circuitry. However, the gate drive

of external PMOS has a low impedance for the sake of speed. Therefore, if the input voltage is high and the bypass capacitor is attached

away from the IC, the charge/discharge current to the external PMOS may lead to unstable operations due to switching operation of the

EXT pin.

As a solution to this problem, place the bypass capacitor as close to the IC as possible, so that voltage variations at the V^INand VSS pins

caused by switching are minimized. If this is not effective, insert a resistor of several to several tens of ohms between the EXT pin and

PMOS gate. Remember that the insertion of a resistor slows down the switching speed and may result in reduced efficiency.

3. A PNP transistor can be used in place of PMOS. If using a PNP transistor, insert a resistor (Rb) and capacitor (Cb) between the EXT pin

and the base of the PNP transistor in order to limit the base current without slowing the switching speed. Adjust Rb in a range of 500 Ω to

1 kΩ according to the load and hFE of the transistor. Use a ceramic capacitor for Cb, complying with Cb ≤ 1/(2 × π × Rb × Fosc × 0.7), as a

rule.

[Inside the I�C]

VIN

EXT pin

Rb

Cb

4. Although the C_CLK connection capacitance range is from 150 ~ 220pF, the most suitable value for maximum stability is around 180pF.

399

04S_01XC9101/9102新規 02.09.12 14:38 ページ 400

XC9101Series

ꢀRecommended Pattern Layout

q

In order to stablize VDD's voltage level, we recommend that a by-pass capacitor (CDD) be connected as close as possible to the VIN & VSS

pins.

w

In order to stablize the GND voltage level which can fluctuate as a result of switching, we suggest that C_CLK's, R_CLK's & C_GAIN's GND

be separated from Power GND and connected as close as possible to the V^SSpin (by-pass capacitor, CDD). Please use a multi layer board

and check the wiring carefully.

Pattern Layout Examples

XC9101D Series

2 Layer Evaluation Board

L

SD

CDD

4

CFB

N-MOS

RFB1

VDD Line

5

1

CL

IC GND

6

7

2

RSEN

3

Power GND

RFB2

R_SS

C_GAIN

CIN

8

R_CLK

4

VIN

C_SS

C_CLK

Through Hole

1

2

3

4

5

6

7

8

R_CLK, C_CLK, C_GAIN, RFB2ꢀ�

GND

Through Hole

400

04S_01XC9101/9102新規 02.09.12 14:38 ページ 401

XC9101

Series

1 Layer Evaluation Board

L

SD

CDD

CFB

N-MOS

RFB1

VDD Line

1

2

3

4

5

6

7

CL

IC GND

RSEN

VIN

Power GND

R_SS

C_GAIN

CIN

8

RFB2

R_CLK

C_SS

C_CLK

4

ꢀNotes

Ensure that the absolute maximum ratings of the external components and the XC9101 DC/DC IC itself are not exceeded.

We recommend that sufficient counter measures are put in place to eliminate the heat that may be generated by the external N-MOSFET as a

result of switching losses.

Try to use a N-MOSFET with as small a gate capacitance as possible in order to avoid overly large output spike voltages that may occur (such

spikes occur in proportion to gate capacitance).

The performance of the XC9101 DC/DC converter is greatly influenced by not only its own characteristics, but also by those of the external

components it is used with. We recommend that you refer to the specifications of each component to be used and take sufficient care when

selecting components.

Wire external components as close to the IC as possible and use thick, short connecting wires to reduce wiring impedance. In particular,

minimize the distance between the by-pass capacitor and the IC.

Make sure that the GND wiring is as strong as possible as variations in ground potential caused by ground current at the time of switching may

result in unstable operation of the IC. Specifically, strengthen the ground wiring in the proximity of the V^SSpin.

401

04S_01XC9101/9102新規 02.09.12 14:38 ページ 402

XC9101Series

■Test Circuits

・Fig. q(FB Type)

・Fig. q(V^OUTType)

SD

22μH

SD

NMOS

CFB

RFB1

Vss 8

1 EXT

2 Isen

1 EXT

Vss 8

FB 7

VOUT 7

GAIN 6

CLK 5

2 Isen

3 VIN

100mΩ�

220μF

100mΩ�

R_SS

RL

3 VIN

RFB2

V

RL

GAIN 6

V

R_SS

0.1μF

4 CE/SS

4 CE/SS CLK 5

20μF

220μF 0.1μF

470pF

10KΩ�

20μF

470pF

10KΩ�

1μF

220pF

1μF

XC9101C33A ꢀR_�SS：104kΩ C-SS：0.1μF�

XC9101C50A R_SS：138kΩ C-SS：0.1μF

・Fig. w

・Fig. e

4

Vss 8

1 EXT

Vss 8

VOUT/FB 7

2 Isen

VOUT/FB 7

2 Isen

3 VIN

GAIN 6

3 VIN

GAIN 6

CLK 5

4 CE/SS

A

4 CE/SS CLK 5

10KΩ�

OSC

220pF

0.1μF

10KΩ�

220pF

0.1μF

・Fig. r

・Fig. t

1 EXT

Vss 8

1 EXT

Vss 8

VOUT/FB 7

GAIN 6

2 Isen

3 VIN

V

VOUT/FB 7

2 Isen

3 VIN

OSC

GAIN 6

0.1μF

4 CE/SS CLK 5

10KΩ�

A

4 CE/SS CLK 5

10KΩ�

V

220pF

0.1μF

220pF

・Fig. y

・Fig. u

1 EXT

Vss 8

1 EXT

Vss 8

VOUT/FB 7

GAIN 6

2 Isen

3 VIN

2 Isen

3 VIN

GAIN 6

A

V

4 CE/SS CLK 5

10KΩ�

4 CE/SS CLK 5

1MΩ�

V

0.1μF

220pF

402

04S_01XC9101/9102新規 02.09.12 14:38 ページ 403

XC9101

Series

■Typical Performance Characteristics

XC9101D09AKR

(1) OUTPUT VOLTAGE vs. OUTPUT CURRENT

VOUT = 3.3V, FOSC : 180kHz

VOUT = 5.0V, FOSC : 180kHz

L=22μH, CIN=220μF（Electrolytic）+10μF（Ceramic）�

CL=40μF（Ceramic）, RSEN=50mΩ, CDD=1μF（Ceramic）�

SD：U3FWJ44N, CGAIN=470pF（Ceramic）, Tr：XP161A1355PR

L=22μH, CIN=220μF（Electrolytic）+10μF（Ceramic）�

CL=40μF（Ceramic）, RSEN=50mΩ, CDD=1μF（Ceramic）�

SD：U3FWJ44N, CGAIN=470pF（Ceramic）, Tr：XP161A1355PR

3.6

3.5

3.4

3.3

3.2

3.1

3.0

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4

VIN=2.5V�

3.3V�

VIN=2.5V�

3.0V

4.2V

1

10

100

1000

1

10

100

1000

Output Current : IOUT（mA）�

VOUT = 8.0V, FOSC : 330kHz

VOUT = 12.0V, FOSC : 330kHz

L=22μH, CIN=220μF（Electrolytic）+10μF（Ceramic）�

CL=40μF（Ceramic）, RSEN=50mΩ, CDD=1μF（Ceramic）�

SD：U3FWJ44N, CGAIN=470pF（Ceramic）, Tr：XP161A1355PR

L=22μH, CIN=220μF（Electrolytic）+10μF（Ceramic）�

CL=40μF（Ceramic）, RSEN=50mΩ, CDD=1μF（Ceramic）�

SD：U3FWJ44N, CGAIN=470pF（Ceramic）, Tr：XP161A1265PR

8.3

8.2

8.1

8.0

7.9

7.8

7.7

13.0

12.5

12.0

11.5

11.0

VIN=5.0V�

8.0V

VIN=3.3V�

5.0V

1

10

100

1000

1

10

100

1000

Output Current : IOUT（mA）�

403

04S_01XC9101/9102新規 02.09.12 14:38 ページ 404

XC9101Series

(2) EFFICIENCY vs. OUTPUT CURRENT

VOUT = 3.3V, FOSC : 180kHz

VOUT = 5.0V, FOSC : 180kHz

L=22μH, CIN=220μF（Electrolytic）+10μF（Ceramic）�

CL=40μF（Ceramic）, RSEN=50mΩ, CDD=1μF（Ceramic）�

SD：U3FWJ44N, CGAIN=470pF（Ceramic）, Tr：XP161A1355PR

100

L=22μH, CIN=220μF（Electrolytic）+10μF（Ceramic）�

CL=40μF（Ceramic）, RSEN=50mΩ, CDD=1μF（Ceramic）�

SD：U3FWJ44N, CGAIN=470pF（Ceramic）, Tr：XP161A1355PR

100

80

�

80

3.0V

4.2V

3.3V

VIN=2.5

�

60

�

60

VIN=2.5V

40

4

1

10

100

1000

1

10

100

1000

Output Current : IOUT（mA）�

VOUT = 8.0V, FOSC : 180kHz

VOUT = 12.0V, FOSC : 180kHz

L=22μH, CIN=220μF（Electrolytic）+10μF（Ceramic）�

CL=40μF（Ceramic）, RSEN=50mΩ, CDD=1μF（Ceramic）�

SD：U3FWJ44N, CGAIN=470pF（Ceramic）, Tr：XP161A1355PR

L=22μH, CIN=220μF（Electrolytic）+10μF（Ceramic）�

CL=40μF（Ceramic）, RSEN=50mΩ, CDD=1μF（Ceramic）�

SD：U3FWJ44N, CGAIN=470pF（Ceramic）, Tr：XP161A1265PR

100

80

100

80

8.0V

5.0V

VIN=5.0V

VIN=3.3

60

40

1

10

100

1000

1

10

100

1000

Output Current : IOUT（mA）�

404

04S_01XC9101/9102新規 02.09.12 14:38 ページ 405

XC9101

Series

(3) RIPPLE VOLTAGE vs. OUTPUT CURRENT

VOUT = 3.3V, FOSC : 180kHz

VOUT = 5.0V, FOSC : 180kHz

L=22μH,C^IN=220μF(Electrolytic)+10μF(Ceramic)�

C^L=40μF(Ceramic),RSEN=50mΩ,CDD=1μF(Ceramic)�

SD:U3FWJ44N,C^GAIN=470pF(Ceramic),Tr:XP161A1355PR

L=22μH,CIN=220μF(Electrolytic)+10μF(Ceramic)�

C^L=40μF(Ceramic),RSEN=50mΩ,CDD=1μF(Ceramic)�

SD:U3FWJ44N,C^GAIN=470pF(Ceramic),Tr:XP161A1355PR

100

80

100

80

60

40

20

0

4.2V

60

3.3V

3.0V

VIN=2.5V

40

VIN=2.5V

20

0

4

1

1 0

100

1000

1

1 0

100

1000

Output Current : IOUT (mA)

V^OUT= 8.0V, FOSC : 330kHz

L=22μH,CIN=220μF(Electrolytic)+10μF(Ceramic)�

C^L=40μF(Ceramic),RSEN=50mΩ,CDD=1μF(Ceramic)�

SD:U3FWJ44N,C^GAIN=470pF(Ceramic),Tr:XP161A1355PR

VOUT = 12.0V, FOSC : 330kHz

L=22μH,CIN=220μF(Electrolytic)+10μF(Ceramic)�

CL=40μF(Ceramic),RSEN=50mΩ,CDD=1μF(Ceramic)�

SD:U3FWJ44N,C^GAIN=470pF(Ceramic),Tr:XP161A1265PR

�

100

80

60

40

20

0

100

80

60

40

20

0

8.0V

5.0V

VIN=5.0V

VIN=3.3V

1

1 0

100

1000

1

1 0

Output Current : IOUT (mA)

VOUT = 5.0V, FOSC : 180kHz

100

1000

Output Current : IOUT (mA)

V^OUT= 3.3V, FOSC : 180kHz

�

L=22μH,CL=94μF(Tantalum),CIN=94μF(Tantalum)�

R^SEN=50mΩ,CDD=1μF(Ceramic)�

L=22μH,CL=94μF(Tantalum),CIN=94μF(Tantalum)�

R^SEN=50mΩ,CDD=1μF(Ceramic)�

SD:U3FWJ44N,C^GAIN=470pF(Ceramic),Tr:XP161A1355PR

200

160

120

80

200

160

120

80

4.2V

3.0V

VIN=3.3V

VIN=2.5V

40

0

1

1 0

100

1000

1

1 0

100

1000

Output Current : IOUT (mA)

Note : If the difference between the input and output voltage is large or small, switching ON / OFF time will be shortened. As such, the external

components used and their values ( inductance value of the coil, resistor connected to CLK, capacitor etc. ) may have a critical influence on the

actual operation of the IC.

405


型号：	XC9101C30AKL
厂家：	Torex Semiconductor
描述：	PWM Controlled Step-Up DC/DC Controllers PWM控制的升压型DC / DC控制器控制器
文件：	总19页 (文件大小：294K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC9101C30AKL [TOREX]

相关型号：

XC9101C30AKR

XC9101C30ASR

XC9101C31AKL

XC9101C33AKL

XC9101C33AKR

XC9101C33AKR-G

XC9101C34AKR

XC9101C35AKR

XC9101C36AKL

XC9101C36AKR

XC9101C37AKR

XC9101C38AKL