JT6N57 [TOSHIBA]
IC SPECIALTY MEMORY CIRCUIT, UUC5, DIE-5, Memory IC:Other;
| 型号： | JT6N57 |
| 厂家： | 
TOSHIBA |
| 描述： | IC SPECIALTY MEMORY CIRCUIT, UUC5, DIE-5, Memory IC:Other 内存集成电路 |
| 文件： | 总9页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JT6N57
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
JT6N57
LSIs for Serial Port Controller with Built-in Non-Volatile Memory
JT6N57 is a low-power-dissipation, low-operating-voltage LSI developed using Toshiba’s CMOS and EEPROM
technology combined. The LSI integrates a serial I/O controller and 4-KB EEPROM on a single chip. With low
power dissipation, 3- to 5-V operating voltage, Sleep mode, and battery level detector, JT6N57 is ideal for hand-held
devices and battery-operated systems.
To protect data, JT6N57 can prohibit write to EEPROM when the LSI is abnormal (eg, power supply voltage is
low). JT6N57 features protect bits which prevent written data from being erroneously overwritten, a response
function which confirms that operation is normal, and a parity check function which confirms that data
communications are performed correctly.
Features
•
•
•
•
•
•
•
•
•
•
•
Built-in EEPROM: 4 Kbytes (32 bytes/page × 128 pages)
Pins: five (V , GND, CLK, RST, I/O (I/O-port-only pin))
DD
Battery level detector (anti-erroneous EEPROM write operations)
Byte/Page-write/read function
Sleep mode (low-power dissipation at standby for input)
Operating voltage: 2.7 to 5.5 V
Operating frequency: 1 kHz to 1 MHz (1 kHz to 100 kHz for Page-write)
Response function and function to display after reset information about the LSI type
EEPROM protect bits against erroneous overwrite
Parity check function
Package: chip/wafer
Note: Overwrite time: 8 ms (max)
Number of writes: 105 times (provisional)
Year for retaining data: 10 years (provisional)
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JT6N57
Block Diagram
JT6N57
Serial I/O control
System control
I/O
RST
CLK
EEPROM (4 Kbytes)
V
DD
GND
Pad Functions
Pad
I/O
Input or Output
Name and Function
I/O port:Serial interface for external devices.
Internally pulled up.
Input or output
Input
Reset: Input for reset signals from external devices.
Schmitt trigger input with internal pull-up.
RST
CLK
Clock: Input for clock signals from external devices.
Schmitt trigger input with internal pull-up.
Input
V
Power supply: Input for power supply from external devices.
DD
GND
Ground: Input for power supply from external devices. (+0 V)
Equivalent Circuit Diagrams
(1) CLK, RST
Both CLK and RST are Schmitt trigger inputs with a pull-up resistor.
CLK or
RST
Input
Figure 1
(2) I/O
Serial I/O interface with a pull-up resistor.
I/O control
I/O
Output
Input
Latch
Figure 2
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JT6N57
External View
GND
V
DD
Y
X
(0, 0)
RST
CLK
Chip size
L : 2.19 mm
L : 2.88 mm
Y
X
I/O
Pad size
100 µm × 100 µm
Pad Coordinates
(µm, µm)
Signal
(X Point, Y Point)
Signal
(X Point, Y Point)
RST
CLK
I/O
(900, −50)
(900, −1030)
(−880, −1040)
V
(900, 1060)
DD
GND
(−880, 1050)
1. Data Memory
Features are listed below:
• 4 Kbytes (32 bytes × 128 pages)
• Automatic byte overwrite
• Automatic page overwrite (32 bytes)
• Data protection function by protect bits
• Write cycle time: 8 ms (max)
Figure 3 below is the memory map.
Addresses within page (A4 to A0)
32 bytes
(1 bit/page)
Protect bit (D7)
Pages
(A11~A5)
....
....
0000
0020
0001
0021
~
~
001E
003E
001F
003F
....
....
128 pages
....
....
....
....
0FC0
0FE0
0FC1
0FE1
~
~
0FDE
0FFE
0FDF
0FFF
Figure 3 Memory Map
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JT6N57
2. Write to EEPROM
JT6N57 supports a Page Write mode for 1-byte write and 32-byte (A4 to A0) write, thus implementing
high-speed data storing.
3. Protect Bits
JT6N57 supports protect bits which prohibit writes to EEPROM in units of pages. A protect bit prevents
data from being erroneously written to or erased from EEPROM. Writing to a protect bit is the same as
writing to the EEPROM data area. A protect bit is assigned to each page. The protect bit address uses A11
to A5 to specify the page. A4 to A0 can be any value.
The data bus for input/output of a protect bit is D7.
Once a protect bit is set to disable write to EEPROM, the protect bit cannot be modified.
Protect Bit (D7) Value
Write to EEPROM Data Area
0
1
Disable
Enable
4. Basic Timing
Figure 4 shows the timing when JT6N57 is reset by a reset signal ( RST ). To reset JT6N57, the RST
pin must be Low for 3 CLKs or longer from a CLK falling edge followed by a rising edge. After the reset
signal ( RST ) goes High, information about the LSI type is output at the seventh CLK rising edge following
the rising edge of the next CLK signal. I/O input can start from the 35th CLK.
Information about LSI type
CLK
RST
Figure 4 Timing at Reset
5. Sleep Mode
At standby for I/O input after reset or at completion of command execution, JT6N57 automatically enters
low-power-dissipation state (Sleep mode). JT6N57 is woken up from Sleep mode by command input.
6. Battery Level Detector
Prohibits erroneous write to EEPROM at low power supply voltage to protect data.
If power supply voltage is abnormal, the response function indicates abnormality.
7. Parity Check Function
An even-parity check function is used for data transfer. Whether communication data are
transmitted/received correctly is checked.
If data reception is abnormal, the function prohibits command reception, indicating abnormality using
the response function.
8. Response Function
Whether command transmission is normal can be checked.
The response function outputs whether there is a parity error or 2-state battery level detector (BLD)
error. If operation is normal, outputs 00h.
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JT6N57
Maximum Ratings (levels are shown with GND = 0 V.)
Characteristics
Supply voltage
Symbol
Rating
Unit
V
−0.5~6.0
V
V
DD
Input voltage
V
−0.5~V
+ 0.5
DD
IN
Operating temperature
Storage temperature
T
−40~85
°C
°C
opr
T
−55~125
stg
Electrical Characteristics
DC Characteristics (unless otherwise noted, V = 2.7~5.5 V, GND = 0 V, Ta = −40~85°C)
DD
Parameter
Pad
RST
CLK
I/O
Symbol
Test Condition
Min
Max
Unit
V
V
V
DD
+ 0.3
DD
× 0.8
V
V
DD
+ 0.3
DD
High-level input voltage
V
V
IH
× 0.7
V
V
DD
+ 0.3
DD
V
× 0.7
V
× 0.2
DD
RST
CLK
I/O
−0.3
V
V
× 0.2
DD
Low-level input voltage
V
IL
−0.3
−0.3
V
V
× 0.2
DD
V
V
− 0.8
DD
High-level output voltage
Low-level output voltage
V
I
I
= −100 µA, V
= 2.5 V
V
DD
V
OH
OH
OL
DD
I/O
V
= 1 mA, V
= 2.5 V
DD
0
0.4
10
V
µA
µA
µA
µA
kΩ
V
OL
RST
CLK
RST
CLK
I/O
V
V
V
V
= V
= V
× 0.8~V
× 0.7~V
−20
−20
−50
−50
10
IN
IN
IN
IN
DD
DD
DD
High-level input current
Low-level input current
I
IH
10
DD
= GND~V
= GND~V
× 0.12
−0.1
−0.1
30
DD
DD
I
IL
× 0.12
Pull-up resistance
R
IN
Battery level detection voltage
V
BLD
2.10
2.65
7
DD
Normal conditions
V
V
= 5.5 V, f (CLK) = 1 MHz
= 5.5 V, f (CLK) = 1 MHz
mA
DD
DD
Battery open check
(CLK IN)
Current
dissipation
70
7
µA
µA
V
I
DD
DD
Sleep mode
(CLK H STOP)
V
= 5.5 V, f (CLK) = 1 MHz
DD
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JT6N57
AC Characteristics (unless otherwise noted, V = 2.7~5.5 V, GND = 0 V, Ta = −40~85°C)
DD
AC Characteristics at Byte Write/Read and PAGE Read
(values enclosed by square brackets [ ] are AC characteristics at page write)
Parameter
Clock cycle time
Pad
CLK
CLK
CLK
Symbol
Test Condition
Figure 5
Min
Max
Unit
µs
1.0
[10]
1000
[1000]
t
cyc
0.35
[3.5]
Tcyc − 0.35
[tcyc − 3.5]
Clock pulse width (high)
Clock pulse width (low)
t
Figure 5
Figure 5
µs
DTYH
0.35
[3.5]
Tcyc − 0.35
[tcyc − 3.5]
t
µs
DTYL
Clock fall time
CLK
CLK
I/O
t
Figure 5
Figure 5
Figure 6
Figure 6
100
100
200
200
ns
ns
ns
ns
cf
Clock rise time
t
cr
I/O port fall time
t
t
f
I/O port rise time
I/O
r
Setup time:
RST
RST
tRSF
tRSR
Figure 7
Figure 7
90
90
50
ns
ns
RST fall to CLK falling time
Setup time:
RST rise to CLK falling time
Hold time:
RST
I/O
tRHD
tOD
Figure 7
Figure 6
Figure 6
ns
ns
ns
RST rise to CLK rising time
I/O output delay to CLK rising time
Hold time:
200
I/O
tIHR
200
200
200
200
I/O input rise to CLK rising time
Setup time:
I/O
I/O
I/O
tISR
tIHF
Figure 6
Figure 6
Figure 6
ns
ns
ns
I/O input rise to CLK rising time
Hold time:
I/O input fall to CLK rising time
Setup time:
tISF
twc
I/O input fall to CLK rising time
EEPROM write cycle time
EEPROM data hold term
8
ms
Ta = 85°C
10
years
5
EEPROM data re-write times
(tentative)
10
times
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JT6N57
AC Test Conditions
t
cyc
V
× 0.7
V
× 0.7
DD
DD
CLK
(V
× 0.9)/2
(V
× 0.9)/2
(V
× 0.9)/2
DD
DD
DD
V
× 0.2
V
× 0.2
V
× 0.2
DD
DD
DD
t
cf
t
t
t
DTYL
cr
DTYH
Figure 5 CLK Input Waveform
V
× 0.7
V
× 0.7
DD
DD
I/O
(Input)
V
× 0.2
V
× 0.2
DD
DD
t
t
f
r
V
× 0.7
V
× 0.7
V
× 0.7
V
× 0.7
DD
DD
DD
DD
CLK
I/O
tOD
(Output)
tOD
(Output)
tISF
tISR
tIHF
tIHR
V
× 0.7
V
× 0.7
× 0.2
DD
DD
V
× 0.2
V
DD
DD
Figure 6
I/O Input Waveform
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2002-02-13
JT6N57
Reset Timing
To reset JT6N57, the RST pin must be Low for 3 states or longer from a CLK falling edge followed by a rising
edge. After the reset signal ( RST ) goes High, information about the LSI type is output at the seventh state
following the rising edge of the next CLK signal. I/O input can start from the 35th state.
Information about LSI type
CLK
RST
V
× 0.7
DD
CLK
RST
V
DD
V
× 0.2
DD
× 0.2
tRSF
tRSR
tRHD
V
× 0.7
DD
V
× 0.2
V
× 0.2
DD
DD
Figure 7
Input Waveform
RST
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JT6N57
RESTRICTIONS ON PRODUCT USE
000707EAA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
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2002-02-13
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