SSM6L10TU(TE85L) [TOSHIBA]
SSM6L10TU(TE85L);SSM6L10TU
TOSHIBA Field Effect Transistor Silicon P/N Channel MOS Type
SSM6L10TU
High Speed Switching Applications
•
•
Optimum for high-density mounting in small packages
Low on-resistance Q1: R = 395mΩ (max) (@V
= 1.8 V)
= -1.8 V)
on
GS
GS
Unit: mm
Q2: R = 980mΩ (max) (@V
on
2.1±0.1
1.7±0.1
Q1 Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Drain-Source voltage
Symbol
Rating
Unit
1
2
6
5
V
20
± 12
0.5
V
V
DS
Gate-Source voltage
V
GSS
DC
I
D
4
3
Drain current
A
Pulse
I
1.5
DP
Q2 Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Drain-Source voltage
Symbol
Rating
Unit
V
-20
± 8
V
V
DS
Gate-Source voltage
V
GSS
1.Source1 4.Source2
2.Gate1
3.Drain2
5.Gate2
6.Drain1
DC
I
-0.5
-1.5
D
Drain current
A
Pulse
I
DP
UF6
JEDEC
JEITA
―
―
Absolute Maximum Ratings(Q1,Q2 Common)(Ta = 25°C)
Characteristics
Symbol
Rating
500
Unit
mW
TOSHIBA
2-2T1B
P
D
Drain power dissipation
(Note 1)
Weight: 7.0 mg (typ.)
Channel temperature
T
150
°C
°C
ch
Storage temperature range
T
stg
−55~150
Note:
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: Mounted on FR4 board. (total dissipation)
(25.4 mm × 25.4 mm × 1.6 t, Cu Pad: 645 mm )
2
Marking
Equivalent Circuit (top view)
6
5
4
6
5
4
Q1
Q2
1
2
3
1
2
3
Handling Precaution
When handling individual devices (which are not yet mounted on a circuit board), be sure that the environment is
protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects
that come into direct contact with devices should be made of anti-static materials.
1
2007-11-01
SSM6L10TU
Q1 Electrical Characteristics (Ta = 25°C)
Characteristics
Gate leakage current
Symbol
Test Condition
Min
Typ.
Max
Unit
I
V
= ±12V, V = 0
GS DS
⎯
20
10
⎯
0.5
1.2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
±1
⎯
μA
GSS
V
V
I
I
= 1 mA, V
= 0
(BR) DSS
(BR) DSX
D
D
GS
GS
Drain-Source breakdown voltage
V
= 1 mA, V
= −12 V
= 0
⎯
⎯
Drain cut-off current
I
V
V
V
= 20 V, V
⎯
1
μA
V
DSS
DS
DS
DS
GS
Gate threshold voltage
Forward transfer admittance
V
= 3 V, I = 0.1 mA
⎯
1.1
⎯
th
D
⏐Y ⏐
= 3 V, I = 0.25 A
(Note2)
(Note2)
(Note2)
(Note2)
2.4
125
150
200
268
34
S
fs
D
I
D
I
D
I
D
= 0.25 A, V
= 0.25 A, V
= 0.25 A, V
= 4.0 V
145
190
395
⎯
GS
GS
GS
Drain-Source on-resistance
R
mΩ
= 2.5 V
DS (ON)
= 1.8 V
Input capacitance
C
V
V
V
V
V
= 10 V, V
= 10 V, V
= 10 V, V
= 0, f = 1 MHz
= 0, f = 1 MHz
= 0, f = 1 MHz
pF
pF
pF
iss
rss
oss
on
DS
DS
DS
DD
GS
GS
GS
GS
Reverse transfer capacitance
Output capacitance
C
⎯
C
t
44
⎯
Turn-on time
Switching time
= 10 V, I = 0.25 A,
11
⎯
D
ns
= 0~2.5 V, R = 4.7 Ω
⎯
Turn-off time
t
15
G
off
Note2:
Pulse test
Switching Time Test Circuit
(a) Test Circuit
(b) V
IN
2.5 V
0 V
90%
OUT
2.5 V
IN
10%
0
V
DD
(c) V
OUT
10 μs
10%
90%
V
DD
V
= 10 V
DD
V
DS (ON)
R
= 4.7 Ω
t
f
t
G
r
<
D.U. 1%
t
t
off
on
V
: t , t < 5 ns
IN
r
f
Common Source
Ta = 25°C
Precaution
V
th
can be expressed as the voltage between gate and source when the low operating current value is I =100 μA for
D
this product. For normal switching operation, V
requires a higher voltage than V and V requires a lower
GS (off)
GS (on)
th
voltage than V
th.
(The relationship can be established as follows: V
< V < V
)
GS (on)
GS (off)
th
2
2007-11-01
SSM6L10TU
Q2 Electrical Characteristics (Ta = 25°C)
Characteristics
Gate leakage current
Symbol
Test Condition
Min
Typ.
Max
Unit
I
V
= ±8 V, V = 0
DS
⎯
-20
-12
⎯
⎯
⎯
±1
⎯
μA
GSS
GS
V
V
I
I
= -1 mA, V
= -1 mA, V
= 0
GS
(BR) DSS
(BR) DSX
D
D
Drain-Source breakdown voltage
V
= +8 V
⎯
⎯
GS
Drain cut-off current
I
V
V
V
= -20 V, V
= 0
⎯
-1
μA
V
DSS
DS
DS
DS
GS
Gate threshold voltage
Forward transfer admittance
V
= -3 V, I = -0.1 mA
-0.5
0.8
⎯
⎯
-1.1
⎯
th
D
⏐Y ⏐
= -3 V, I = -0.25 A
(Note3)
(Note3)
(Note3)
(Note3)
1.7
200
260
400
250
35
S
fs
D
I
I
I
= -0.25 A, V
= -4 V
230
330
980
⎯
D
D
D
GS
GS
GS
Drain-Source on-resistance
R
mΩ
= -0.25 A, V
= -0.25 A, V
= -2.5 V
= -1.8 V
⎯
DS (ON)
⎯
Input capacitance
C
V
V
V
V
V
= -10 V, V
= -10 V, V
= -10 V, V
= 0, f = 1 MHz
= 0, f = 1 MHz
= 0, f = 1 MHz
⎯
pF
pF
pF
iss
rss
oss
on
DS
DS
DS
DD
GS
GS
GS
GS
Reverse transfer capacitance
Output capacitance
C
⎯
⎯
C
t
⎯
45
⎯
Turn-on time
Switching time
= -10 V, I = -0.25 A,
⎯
14
⎯
D
ns
= 0~-2.5 V, R = 4.7 Ω
⎯
⎯
Turn-off time
t
15
G
off
Note3:
Pulse test
Switching Time Test Circuit
(a) Test circuit
(b) V
(c) V
IN
0 V
OUT
10%
0
IN
90%
−2.5V
10 μs
R
L
−2.5 V
V
DD
V
OUT
DS (ON)
90%
V
= -10 V
= 4.7 Ω
DD
R
G
10%
<
D.U. 1%
V
DD
t
t
f
r
V
: t , t < 5 ns
IN
r
f
Common Source
t
t
off
on
Ta = 25°C
Precaution
V
th
can be expressed as the voltage between gate and source when the low operating current value is I =-100 μA for
D
this product. For normal switching operation, V
requires a higher voltage than V and V requires a lower
GS (off)
GS (on)
th
voltage than V
th.
(The relationship can be established as follows: V
< V < V
)
GS (on)
GS (off)
th
.
3
2007-11-01
SSM6L10TU
Q1(Nch MOS FET)
ID - VGS
ID - VDS
1.8
10000
1000
100
10
1600
1400
1200
1.6
2.0
3.0
4.0
5.0
VGS=1.4V
1000
800
600
400
200
0
Ta=100°C
1
25°C
-25°C
Common Source
Ta=25°C
0.1
Common Source
VDS=3V
0.01
0
0.2
0.4
0.6
0.8
1
0
1
2
3
Drain-Source voltage VDS (V)
Gate-Source voltage VGS (V)
RDS(ON) - VGS
RDS(ON) - ID
1.8V
400
350
300
250
200
150
100
50
200
180
160
140
120
100
80
Common Source
ID=250mA
2.5V
VGS=4V
25°C
Ta=100°C
60
40
-25°C
Common Source
Ta=25°C
20
0
0
0
200 400 600 800 1000 1200 1400 1600
Drain current ID (mA)
0
1
2
3
4
5
6
7
8
9
10
Gate-Source voltage VGS (V)
RDS(ON) - Ta
Vth - Ta
400
350
300
250
200
150
100
50
1
0.8
0.6
0.4
0.2
0
Common Source
ID=250mA
Common Source
ID=0.1mA
VDS=3V
1.8V
2.5V
VGS=4V
0
-60 -40 -20
0
20 40 60 80 100 120 140 160
-60 -40 -20
0
20 40 60 80 100 120 140 160
Ambient temperature Ta (°C)
Ambient temperature Ta (°C)
4
2007-11-01
SSM6L10TU
Q1(Nch MOS FET)
|Yfs| - ID
IDR - VDS
Common Source
VGS=0V
Ta=25°C
10
1600
1400
1200
1000
800
600
400
200
0
25°C
D
-25°C
G
IDR
Ta=100°C
1
S
Common Source
VDS=3V
Ta=25°C
0
10
100
1000
10000
0
-0.2
-0.4
-0.6
-0.8
-1
Drain-Source voltage VDS (V)
Drain current ID (mA)
C - VDS
t - ID
1000
100
10
1000
100
10
Common Source
VDD=10V
VGS=0 2.5V
~
Ta=25°C
toff
tf
Ciss
ton
tr
Common Source
VGS=0V
f=1MHz
Coss
Crss
Ta=25°C
1
10
100
1000
10000
0.1
1
10
100
Drain current ID (mA)
Drain-Source voltage VDS (V)
5
2007-11-01
SSM6L10TU
Q2(Pch MOS FET)
ID - VDS
-3.0
ID - VGS
-10000
-1600
-2.0
-5.0
-1400
1000
-
-1.8
-1.6
-1200
100
-4.0
-
-1000
Ta=100°C
10
-
-800
-600
-400
-200
0
25°C
-25°C
-
1
VGS=-1.4V
-
0.1
Common Source
VDS=-3V
Common Source
Ta=25°C
-
-
0.01
0
-0.2
-0.4
-0.6
-0.8
-1
0
-1
-2
-3
Drain-Source voltage VDS (V)
Gate-Source voltage VGS (V)
RDS(ON) - VGS
RDS(ON) - ID
500
400
300
200
100
0
500
400
300
200
100
0
Common Source
ID=-250mA
-1.8V
-2.5V
Ta=100°C
VGS=-4V
25°C
-25°C
Common Source
Ta=25°C
0
-200 -400 -600 -800 -1000 -1200 -1400 -1600
Drain current ID (mA)
0
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10
Gate-Source voltage VGS (V)
RDS(ON) - Ta
-1.8V
Vth - Ta
500
400
300
200
100
0
-1
Common Source
ID=-250mA
Common Source
ID=-0.1mA
VDS=-3V
-0.8
-0.6
-0.4
-0.2
0
-2.5V
VGS=-4V
-60 -40 -20
0
20 40 60 80 100 120 140 160
Ambient temperature Ta (°C)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Ambient temperature Ta (°C)
6
2007-11-01
SSM6L10TU
Q2(Pch MOS FET)
|Yfs| - ID
IDR - VDS
Common Source
VGS=0V
Ta=25°C
10
1600
1400
1200
1000
800
600
400
200
0
25°C
-25°C
1
Ta=100°C
Common Source
VDS=-3V
Ta=25°C
0
-10
-100
-1000
-10000
0.0
0.2
0.4
0.6
0.8
1.0
Drain-Source voltage VDS (V)
Drain current ID (mA)
C - VDS
t - ID
1000
100
10
1000
100
10
Common Source
VDD=-10V
VGS=0 2.5V
~-
Ta=25°C
toff
tf
Ciss
ton
tr
Common Source
VGS=0V
f=1MHz
Coss
Crss
Ta=25°C
1
-0
-1
-10
-100
-10
-100
-1000
-10000
Drain current ID (mA)
Drain-Source voltage VDS (V)
PD* - Ta
1000
800
600
400
200
0
mounted FR4 board
t=10s
DC
(25.4mm*25.4mm*1.6t
2
Cu Pad :645mm )
0
20
40
60
80 100 120 140 160
Ambient temperature Ta(
)
℃
*:Total Rating
7
2007-11-01
SSM6L10TU
r
th
– t
w
1000
100
10
Single pulse
Mounted on FR4 board
2
(25.4 mm × 25.4 mm × 1.6 t, Cu Pad: 645 mm )
1
0.001
0.01
0.1
1
10
100
1000
Pulse width
t
(s)
w
8
2007-11-01
SSM6L10TU
RESTRICTIONS ON PRODUCT USE
•
•
•
Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively “Product”) without notice.
This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.
Though TOSHIBA works continually to improve Product’s quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before creating and producing designs and using, customers must
also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document,
the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the “TOSHIBA
Semiconductor Reliability Handbook” and (b) the instructions for the application that Product will be used with or for. Customers are
solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the
appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any
information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other
referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO
LIABILITY FOR CUSTOMERS’ PRODUCT DESIGN OR APPLICATIONS.
•
Product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring
equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document.
Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or
reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious
public impact (“Unintended Use”). Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used
in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling
equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric
power, and equipment used in finance-related fields. Do not use Product for Unintended Use unless specifically permitted in this
document.
•
•
Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
•
•
The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR
LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND
LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO
SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
•
•
Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product
or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations.
Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
9
2007-11-01
相关型号:
SSM6L13TU,LF(T
Small Signal Field-Effect Transistor, 0.8A I(D), 20V, 2-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET
TOSHIBA
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