TA1318N [TOSHIBA]
SYNC Processor, Frequency Counter IC for TV Component Signals; 同步处理器，频率计IC，适用于电视分量信号
| 型号： | TA1318N |
| 厂家： | 
TOSHIBA |
| 描述： | SYNC Processor, Frequency Counter IC for TV Component Signals |
| 文件： | 总42页 (文件大小：631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TA1318N
TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic
TA1318N
SYNC Processor, Frequency Counter IC for TV Component Signals
TA1318N is a sync processor for TV component signals.
TA1318N provides sync and frequency counter processing for
external input signals.
These functions are integrated in a 24 pin dual-in-line
shrink-type plastic package.
2
TA1318N provides I C bus interface, so various functions and
controls are adjustable via the bus.
Features
•
Horizontal synchronization circuit (15.75 kHz, 31.5 kHz, 33.75
Weight: 1.22 g (typ.)
kHz, 45 kHz)
•
•
•
•
•
•
•
•
•
Vertical synchronization circuit (525I, 525P, 625I, 750P, 1125I, 1125P, PAL 100 Hz, NTSC 120 Hz)
Horizontal and vertical frequency counter
Horizontal PLL
Accepts 2-level and 3-level sync
Accepts both negative and positive HD and VD
Clamp pulse output
HD, VD output (polarity inverter)
Separated sync output
Mask for the copy guard signal
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TA1318N
Block Diagram
DAC3
24
VD2-OUT
23
VD1-OUT
22
SYNC1-IN
21
DAC1
20
SYNC2-IN Address SW
SCL
17
SDA
16
HD2-OUT
15
Digital GND
14
HD1-OUT
13
19
18
2
DAC3
SW
INV
SW
INV
SW
SYNC
SEPA
DAC1
SW
SYNC
SEPA
I CBUS
INV
SW
INV
SW
Decoder
TEST DAC3
DAC1
DV2-OUT
SW
DV1-OUT
SW
HD2-OUT
SW
HD1-OUT
SW
V-Input
SW
V-FREQ
SW
V C/D
H/V-
FREQ
Counter
V-FREQ
DET SW
V-SYNC
DAC2
Clamp
Pulse
CP
SW
DAC2
SW
V
HD
Polarity
H/C-
SYNK
2 × f
H
Integral
H-FREQ
DET SW
H-INPUT
SW
H-AFC
HVCO
H C/D
H-Ramp
H-FREQ
SW
1
2
3
4
5
6
7
8
9
DAC2
10
VD3-IN
11
HD3-IN
12
CP-OUT
HD2-IN
VD2-IN
HD1-IN
VD1-IN
Analog GND
AFC Filter
HVCO
V
CC
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TA1318N
Pin Functions
Pin
Pin Name
Function
Interface Circuit
8
Input Signal/Output Signal
No.
Th: 0.7 V
or
Inputs horizontal sync signal.
Accepts input of both positive
and negative polarity.
1 kΩ
1
HD2-IN
1
Input signal from this pin is not
synchronized.
Th: 0.7 V
5
8
Th: 0.7 V
or
Inputs vertical sync signal.
Accepts input of both positive
and negative polarity.
1 kΩ
2
VD2-IN
2
Input signal from this pin is not
synchronized.
Th: 0.7 V
5
3
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TA1318N
Pin
No.
Pin Name
Function
Interface Circuit
8
Input Signal/Output Signal
Th: 0.7 V
or
Inputs horizontal sync signal.
Accepts input of both positive
and negative polarity.
1 kΩ
3
HD1-IN
3
Input signal from this pin is not
synchronized.
Th: 0.7 V
5
8
Th: 0.7 V
or
Inputs vertical sync signal.
Accepts input of both positive
and negative polarity.
1 kΩ
4
5
VD1-IN
4
Input signal from this pin is not
synchronized.
Th: 0.7 V
5
GND pin for analog circuit
blocks.
Analog GND
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TA1318N
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
8
Connects filter for horizontal
AFC.
6
AFC Filter
DC
300 Ω
30 kΩ
Voltage on this pin determines
horizontal output frequency.
6
5
8
Connects ceramic oscillator for
horizontal oscillation.
4 kΩ
7
HVCO
Use Murata
CSBLA503KECZF30.
7
1 kΩ
10 kΩ
5
VCC pin.
8
V
CC
Connects 9 V (typ.).
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TA1318N
Pin
No.
Pin Name
Function
Interface Circuit
8
Input Signal/Output Signal
DC
or
DAC2 output pin.
In Test mode, outputs HD or
composite sync signal to
frequency counter.
H/C SYNC
To improve the driving ability, it
is possible to connect a
resister (minimum: 2 kΩ)
between this pin and GND.
However, when the resister is
added, the output DC voltage
is down.
9
DAC2 (H/C. SYNC output)
7 V
0 V
200 Ω
9
14
8
Th: 0.7 V
or
Inputs vertical sync signal.
1 kΩ
10 VD3-IN
10
Accepts input of both positive
and negative polarity.
Th: 0.7 V
5
8
Th: 0.7 V
or
Inputs horizontal sync signal.
1 kΩ
11 HD3-IN
11
Accepts input of both positive
and negative polarity.
Th: 0.7 V
5
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TA1318N
Pin
No.
Pin Name
Function
Interface Circuit
8
Input Signal/Output Signal
5.0 V
0 V
Clamp pulse (CP) output pin.
12 CP-OUT
Outputs CP generated by sync
circuit.
200 Ω
12
14
8
HD output pin.
Open collector output.
HD1/HD2 input signal is output
from this pin without
200 Ω
or
13 HD1-OUT
13
synchronization.
Polarity is switched by BUS
write function.
14
14 Digital GND
GND pin for logic blocks.
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TA1318N
Pin
No.
Pin Name
Function
Interface Circuit
8
Input Signal/Output Signal
HD output pin.
Open collector output.
or
200 Ω
HD1/HD2 input signal is output
from this pin without
15 HD2-OUT
15
synchronization.
Polarity is switched by BUS
write function.
14
8
50 Ω
20 kΩ
SDA
2
16
16 SDA
SDA pin for I C bus.
ACK
5
14
8
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TA1318N
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
8
2
20 kΩ
SCL
17 SCL
SCL pin for I C bus.
17
5
8
9 V
DC/DD
7.5 V
7.5 V
Slave address switch pin.
1 kΩ
When this pin is connected to
DA/DB
D8/D9
18 Address SW
18
V
(GND), used for DC/DD
H
CC
(D8/D9 ); when left open,
H
1.5 V
DA/DB .
H
1.5 V
0 V
5
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TA1318N
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
White 100％ = 1 V
p−p
8
Inputs Y signal (Note 1) for
sync separation circuit.
19
19 SYNC2-IN
or
Input via clamp capacitor.
1 kΩ
5
8
DAC1 output pin.
DC
or
In Test mode, outputs VD or
composite sync signal to
frequency counter.
V SYNC
To improve the driving ability, it
is possible to connect a
resister (minimum: 2 kΩ)
between this pin and GND.
However, when the resister is
added, the output DC voltage
is down.
20 DAC1 (V SYNC output)
7 V
0 V
200 Ω
20
14
Note 1: The signal format for SYNC1-IN (pin 21) and SYNC2-IN (pin 19)
NTSC (525I/60 Hz), PAL/SECAM (625I/50 Hz), NTSC Double Scan (525I/120 Hz), PAL/SECAM Double Scan (625I/100 Hz), 525P/60 Hz, 750P/60 Hz,
1125I/60 Hz, 1125P/30 Hz
This IC doesn’t have the sync-separation circuit for non-standard signals like weak strength signal, ghost signal and so on.
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TA1318N
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
White 100％ = 1 V
p−p
8
Inputs Y signal (Note 1) for
sync separation circuit.
21
21 SYNC1-IN
or
Input via clamp capacitor.
1 kΩ
5
8
VD output pin.
Open collector output.
Start phase
or
VD1/VD2 input signal is output
from this pin without
200 Ω
22
synchronization.
22 VD1-OUT
Polarity is switched by BUS
write function.
(Note) When HD PHASE will
be changed, synchronized VD
width will change. Use the start
phase of VD.
14
Start phase
Note 1: The signal format for SYNC1-IN (pin 21) and SYNC2-IN (pin 19)
NTSC (525I/60 Hz), PAL/SECAM (625I/50 Hz), NTSC Double Scan (525I/120 Hz), PAL/SECAM Double Scan (625I/100 Hz), 525P/60 Hz, 750P/60 Hz,
1125I/60 Hz, 1125P/30 Hz
This IC doesn’t have the sync-separation circuit for non-standard signals like weak strength signal, ghost signal and so on.
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TA1318N
Pin
No.
Pin Name
Function
Interface Circuit
8
Input Signal/Output Signal
VD output pin.
Open collector output.
Start phase
or
VD1/VD2 input signal is output
from this pin without
200 Ω
23
synchronization.
23 VD2-OUT
Polarity is switched by BUS
write function.
(Note) When HD PHASE will
be changed, synchronized VD
width will change. Use the start
phase of VD.
14
Start phase
8
DAC3 output pin.
DC
500 Ω
Open collector output.
24 DAC3
or
24
In Test mode, outputs test
pulse for shipping.
test pulse for shipping
14
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TA1318N
Bus Control Map
Write Mode
Slave Address: D8/DA/DC
H
Preset
D7
D0
Sub-Add
D6
D5
D4
D3
D2
D1
MSB
LSB
MSB
1000
1000
1000
1000
LSB
0000
0000
0000
0000
00
01
02
03
H-FREQUENCY
DAC1
HD1/VD1-OUT SW
DAC2
HD2/VD2-OUT SW
DAC3 TEST
FREQ DET SW
SEPA LEVEL
HD1-INV
HD2-INV
V-FREQUENCY
CLP-PHS
INPUT SW
HD PHASE
VD1-INV
VD2-INV
Read Mode
Slave Address: D9/DB/DD
H
D7
MSB
D0
LSB
D6
D5
D4
D3
D2
D1
0
1
POR
V FREQUENCY DET
H FREQUENCY DET
HD-IN
Bus Control Functions
Write Mode (*: Preset)
•
H-FREQUENCY (Horizontal oscillation frequency)
Switches horizontal frequency.
(00): 15.75 kHz
(01): 31.5 kHz
*(10): 33.75 kHz
(11): 45 kHz
•
HD1/VD1-OUT SW (HD1/VD1 output switch)
Switches output from pin 13/22. When set to 00, 01, or 10, outputs HD/VD without synchronization.
When set to 11, outputs HD/VD from the sync circuit. (Note) Synchronized VD width will change, when
HD PHASE will be changed.
*(00): HD1/VD1
(01): HD2/VD2
(10): HD3/VD3
(11): Synchronized HD/VD
•
•
HD2/VD2-OUT SW (HD2/VD2 output switch)
Switches output from pin 15/23. When set to 00, 01, or 10, outputs HD/VD without synchronization.
When set to 11, outputs HD/VD from the sync circuit.
*(00): HD1/VD1
(01): HD2/VD2
(10): HD3/VD3
(11): Synchronized HD/VD
SEPA LEVEL (Sync separation level switch)
Switches sync separation level of pin 19/21. Set values are the levels from sync tip. Sync separation level
is changed according to the ratio of H-SYNC width during 1H period.
*(00): 10IRE
(01): 15IRE
(10): 20IRE
*(10): 5 V
(10): 5 V
(11): 25IRE (at 1125I/60)
•
•
•
•
DAC1 (DAC1 control)
Controls 2-bit DAC (pin 9).
(00): 1 V
(01): 3 V
(11): 7 V
DAC2 (DAC2 control)
Controls 2-bit DAC (pin 20).
*(00): 1 V
(01): 3 V
(11): 7 V
DAC3 (DAC3 control)
Controls open collector 1-bit DAC (pin 24).
*(0): OPEN (HIGH)
(1): ON (LOW)
TEST (Test mode)
Switches DAC1, 2, and 3 outputs. Also used to test IC for shipping.
*(0): DAC outputs are used as DAC.
(1): DAC1 outputs V. SYNC to the frequency counter.
DAC2 outputs H. SYNC or C. SYNC to the frequency counter.
DAC3 outputs IC test pulse for shipping.
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TA1318N
•
•
•
HD1-INV (HD1 output polarity switch)
Switches HD1 output (pin 13) polarity. When set to 0, positive HD input is output as negative HD. When
set to 0, output from the sync circuit is output as negative HD.
*(0): Normal
(1): Inverse
HD2-INV (HD2 output polarity switch)
Switches HD1 output (pin 15) polarity. When set to 0, positive HD input is output as negative HD. When
set to 0, output from the sync circuit is output as negative HD.
*(0): Normal
(1): Inverse
V-FREQUENCY (Vertical frequency switch (pull-in range))
Sets vertical frequency pull-in range, VD-STOP, or free-running frequency.
Free-running frequency is controlled by H-FREQUENCY.
Pull-in Range
Format/H (V) Frequency
1125P/30 Hz (33.75 kHz)
*(000)
48~1281 H
48~849 H
(001)
750P/60 Hz (45 kHz)
Free-running frequency is controlled by H-FREQUENCY.
(00): 262 H (01): 525 H (10): 562 H (11): 750 H
(010)
FREE-RUN
(011)
(100)
48~637 H
48~613 H
1125I/60 Hz (33.75 kHz)
525P/60 Hz (31.5 kHz)
PAL/SECAM/50 Hz (15.625 kHz)
(101)
48~363 H
PAL/SECAM double scan/100 Hz (31.5 kHz)
NTSC/60 Hz (15.734 kHz)
(110)
(111)
48~307 H
VP STOP
NTSC double scan /120 Hz (31.5 kHz)
VD output is HIGH
•
•
CLP PHS (Clamp pulse phase switch)
Switches clamp pulse phase.
If no signal input, 0.9 µs pulse is output from the H-C/D circuit.
*(0): 1 µs (3.4%) delay following HD stop phase, 0.8 µs (2.7%) pulse
(1): 0.5 µs (1.7%) delay following HD stop phase, 0.8 µs (2.7%) pulse
FREQ DET SW (Horizontal/vertical frequency counter switch)
Switches input signal used for horizontal/vertical frequency counter. This switch is controlled
independently from INPUT SW. The detection result is output as read BUS data.
*(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs
INPUT SW (Input signal switch for synchronization)
•
•
Switches input signal used for synchronization.
*(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs
HD PHASE (HD phase adjustment)
Adjusts phase of HD output from the sync circuit. The phase of the adjustment center value is the same
as that of input H-SYNC or input HD. (Note) Synchronized VD width will change, when HD PHASE will
be changed.
(000000):
*(100000):
(111111) :
−5% (H periodically)
0%
5%
•
•
VD1-INV (VD1 output polarity switch)
Switches VD1 output (pin 22) polarity. When set to 0, negative VD input is output as negative VD. When
set to 0, output from the sync circuit is output as negative VD.
*(0): Normal
(1): Inverse
VD2-INV (VD2 output polarity switch)
Switches VD2 output (pin 23) polarity. When set to 0, negative VD input is output as negative VD. When
set to 0, output from the sync circuit is output as negative VD.
*(0): Normal
(1): Inverse
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TA1318N
Read Mode
•
•
•
POR (Power on reset)
(0): Status read (at second data read and subsequent)
(1): Power on (at first data read)
HD-IN (Input signal self-check result)
Detects HD or H-SYNC input signal selected by INPUT SW.
(0): No signal input (1): Signal input
V FREQ DET (Vertical frequency of SYNC or VD input selected by FREQ DET SW)
(0000000)∼(0001100): No-VD
(0001101): Vicinity of 162 Hz
(1111110) : Vicinity of 17 Hz
How to calculate vertical frequency (X):
Convert V-FREQ DET read data into decimal and define the resulting value as Y.
Where H-FREQUENCY is 15.75 kHz/31.5 kHz, Z = 476.2 µs
Where H-FREQUENCY is 33.75 kHz/45 kHz, Z = 474.1 µs
Vertical frequency (X) = 1 ÷ (Y × Z) [Hz]
Error of Y is +1, −0. If vertical frequency is 162 Hz or more, the frequency cannot be accurately
measured. Time constant used to separate V.SYNC from integrated C.SYNC is 9 µs (error: ±1 µs).
H FREQ DET (Horizontal frequency of SYNC or HD input selected by FREQ DET SW)
(0000000): No signal input (1111110): 53 kHz or more
•
How to calculate horizontal frequency (X):
X, Y, and Z are defined same as for V FREQ.
Horizontal frequency (X) = Y ÷ (5 × Z) [kHz]
Error of Y is +1, −0. If horizontal frequency is 53 kHz or more, the frequency cannot be accurately
measured. When V-SYNC or VD is not input, horizontal frequency cannot be measured, resulting in
data = (0000000).
Note 1:The start trigger for frequency counting is the internal reset-pulse made from ACK of 2nd byte in BUS
read mode. The counting period is between the first V-sync (VD) and the second V-sync (VD) after the
trigger.
The counted data will have +1 or −0 error according to the read timing.
To assume stable data reading;
1. Set BUS reading interval more than 60 ms.
2. Don’t use the first data because it is unsettled.
are recommended.
Note 2:Ignore data (1111111). This data may be obtained in case the trigger pulse and the V-sync (VD) are
simultaneous.
Data 1 and
Start trigger 2
Data 2 and
Start trigger 3
Start trigger 1
More than 60 ms
Read Timing
V-SYNC or VD
Counting period 1
(to Data 1)
Counting period 2
(to Data 2)
Decision algorithm (detection range, detection times and so on) should be determined under
consideration of Note 1, Note 2 and the other factors such as signal strength, existence of ghost signal,
2
H-AFC stability, I C BUS data transmission and so on via prototype TV set evaluation.
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TA1318N
2
Data Transfer Format via I C BUS
Slave Address: D8/DA/DC
H
A6
1
A5
1
A4
A3
1
A2
1
A1
A0
W/R
0/1
0
0/1
0/1
Start and Stop Condition
SDA
SCL
S
P
Start condition
Stop condition
Bit Transfer
SDA
SCL
SDA stable
Change of SDA allowed
Acknowledge
SDA by transmitter
SDA by receiver
Bit 9: High impedance
Only bit 9: Low impedance
SCL from master
1
8
9
S
Clock pulse for acknowledgment
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TA1318N
Data Transmit Format 1
S
Slave address
7 bit
0
A
Sub address
8 bit
A
Transmit data
8 bit
A
A
P
MSB
S: Start condition
MSB
A: Acknowledge
MSB
P: Stop condition
Data Transmit Format 2
S
Slave address
0
A
A
Sub address
A
Transmit data
･･････
･･････
Sub address
A
Transmit data n
A P
Data Receive Format
S
Slave address
7 bit
1
Received data 1
8 bit
A
Received data 2
A P
MSB
MSB
At the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave
transmitter. This acknowledge is still generated by this slave.
The Stop condition is generated by the master.
(* important) The data read from THIS IC should always be completed in whole two words, not one word,
otherwise the IICBUS may cause error.
Optional Data Transmit Format: Automatic Increment Mode
S
Slave address
7 bit
0
A
1
Sub address
7 bit
A
Transmit data 1 ････ Transmit data 2
8 bit 8 bit
A P
MSB
MSB
MSB
MSB
In this transmission method, data is set on automatically incremented sub-address from the specified
sub-address.
2
2
Purchase of TOSHIBA I C components conveys a license under the Philips I C Patent Rights to use
2
2
these components in an I C system, provided that the system conforms to the I C Standard Specification
as defined by Philips.
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TA1318N
Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
V
Supply voltage
V
12
9
CCmax
Input pin signal voltage
Power dissipation
e
V
p-p
inmax
P
(*1)
1250
−10
mW
mW/°C
°C
D
Power dissipation reduction rate
Operating temperature
Storage temperature
1/Qja
T
−20~65
−55~150
opr
T
°C
stg
Note: Refer to the figure below.
1250
850
10 mW/°C
0
0
25
65
150
Ambient temperature Ta (°C)
Figure P - Ta Curve
D
Operating Condition
Characteristics
Description
Min
Typ.
Max
Unit
V
Power supply voltage (V
)
Pin 8
8.5
2.0
9.0
5.0
5.0
9.5
9.0
CC
HD1, HD2, HD3 Input level
VD1, VD2, VD3 Input level
Pin 3, 1, 11
Pin 4, 2, 10
V
p-p
2.0
9.0
Synchronization Pin 11
0.02
0.20
H
HD3 input width
Frequency
Pin 11
0.45
0.25H
47H
400
1.1
µs
detection
µs
Synchronization Pin 10
1 µs
VD3 input width
Frequency
Pin 10
1
detection
SYNC1, SYNC2 Input level
Pin 21, 19, white 100% with negative sync
0.9
1.0
0.9
V
p-p
HD1, HD2, VD1, VD2-OUT
Input current
Pin 13, 15, 22, 23
1.5
mA
DAC3 Input current
Pin 24
0
0.5
0
1.0
1.0
9.0
D8/D9
H
Address switching voltage
Pin 18
V
DC/DD
8.0
9.0
H
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TA1318N
Electrical Characteristics (V = 9 V, Ta = 25°C, unless otherwise specified)
CC
Current Dissipation
Test
Pin Name
Symbol
Min
32
Typ.
38
Max
44
Unit
mA
Circuit
V
I
CC
CC
AC Characteristics
Horizontal Block
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
S
S
0.6
0.6
0.6
61
0.7
0.7
0.7
66
0.8
0.8
0.8
71
1PH
2PH
Sync1/2 input horizontal sync phase
HD3 input horizontal sync phase
Polarity distinction active range
(Note HA01)
(Note HA02)
(Note HA03)
µs
µs
%
HD
3PH
HD-
HD-
DUTY1
DUTY2
thS10
thS11
thS12
thS13
thS20
thS21
thS22
thS23
48
53
58
V
V
V
V
V
V
V
V
0.040 0.070 0.100
0.060 0.106 0.152
0.081 0.142 0.203
0.102 0.178 0.255
0.040 0.070 0.100
0.060 0.106 0.152
0.081 0.142 0.203
0.102 0.178 0.255
Sync1 input threshold amplitude
Sync2 input threshold amplitude
(Note HA04)
V
p-p
HD3 input threshold amplitude
(Synchronization block)
V
(Note HA05) 0.65
0.75
0.85
V
V
thHD3
p-p
p-p
V
V
V
0.65
0.75
0.75
0.75
3.18
3.18
1.59
1.59
1.48
1.48
1.11
1.11
1.00
0.80
5.0
0.85
0.85
0.85
3.49
3.49
1.75
1.75
1.63
1.63
1.22
1.22
1.15
0.95
5.3
thHD1
thHD2
thHD3
HD1 input threshold voltage
HD2 input threshold voltage
HD3 input threshold voltage
(SW block)
(Note HA06)
(Note HA07)
0.65
0.65
2.86
2.86
1.43
1.43
1.33
1.33
1.00
1.00
0.85
0.65
4.7
∆HP0−
∆HP0+
∆HP1−
∆HP1+
∆HP2−
∆HP2+
∆HP3−
∆HP3+
HD output phase adjustment variable
range
µs
CP
S0
µs
V
CP
W0
CP
CP
V0
S1
0.35
0.65
4.7
0.50
0.80
5.0
0.65
0.95
5.3
µs
V
Clamp pulse phase/width/level
(Note HA08)
CP
W1
CP
CP
V1
S3
0
1
µs
V
CP
0.50
4.7
0.90
5.0
1.30
5.3
W3
CP
V3
19
2003-02-19
TA1318N
Test
Characteristics
Symbol
Test Condition
(Note HA09)
Min
Typ.
Max
Unit
Circuit
Delayed HD pulse width
W
1.0
4.5
1.2
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
385
385
650
650
4.2
1.8
1.8
1.8
1.8
1.4
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
460
460
780
780
4.5
2.2
2.2
2.2
2.2
µs
d-HD
V13TH0
V13TL0
V13TH1
V13TL1
V13TH2
V13TL2
V13TH3
V13TL3
V15TH0
V15TL0
V15TH1
V15TL1
V15TH2
V15TL2
V15TH3
V15TL3
V13IH0
V13IL0
V13IH1
V13IL1
V13IH2
V13IL2
V13IH3
V13IL3
V15IH0
V15IL0
V15IH1
V15IL1
V15IH2
V15IL2
V15IH3
V15IL3
ID1
4.5
HD1 output voltage
V
V
V
V
4.5
4.5
4.5
4.5
HD2 output voltage
4.5
4.5
4.5
4.5
HD1 output voltage (polarity inverse)
4.5
4.5
4.5
4.5
HD2 output voltage (polarity inverse)
4.5
4.5
310
310
520
520
3.9
1.4
1.4
1.4
1.4
ID2
AFC phase detection current
VCO oscillation start voltage
(Note HB01)
(Note HB02)
(Note HB03)
µA
V
ID3
ID4
V
VCO
TH00
TH01
TH10
TH11
HD output pulse width
(free-run)
µs
20
2003-02-19
TA1318N
Test
Characteristics
Symbol
Test Condition
Min
15.59 15.75 15.91
31.19 31.5 31.82
33.41 33.75 34.09
44.55 45 45.45
15.47 15.625 15.78
Typ.
Max
Unit
Circuit
F00
F01
Horizontal free-run frequency
(Note HB04)
kHz
F10
F11
F50
BH00
BH01
BH10
BH10
2.4
4.8
4.8
7.1
0.5
2.7
4.7
6.5
0.5
2.7
4.7
6.5
3.0
6.0
6.0
8.9
1.0
3.0
5.0
7.0
1.0
3.0
5.0
7.0
0.5
8.8
3.6
7.2
7.2
10.7
1.5
3.3
5.3
7.5
1.5
3.3
5.3
7.5
0.7
Horizontal oscillation control
sensitivity
(Note HB05)
kHz/V
VDAC
VDAC
VDAC
VDAC
VDAC
VDAC
VDAC
VDAC
VDAC
VDAC
10
11
12
13
20
21
22
23
30
31
DAC1 output voltage
V
DAC2 output voltage
DAC3 output voltage
V
V
8.5
21
2003-02-19
TA1318N
Vertical Block
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
V
V
V
0.65
0.65
0.65
0.75
0.75
0.75
0.85
0.85
0.85
VD1 input threshold voltage
VD2 input threshold voltage
VD3 input threshold voltage
(SW block)
thVD1
thVD2
thVD3
(Note VA01)
V
p-p
VD3 input threshold voltage
(synchronization block)
V
(Note VA02) 0.65
0.75
0.85
V
p-p
thVD3
V22TH0
V22TL0
V22TH1
V22TL1
V22TH2
V22TL2
V22TH3
V22TL3
V23TH0
V23TL0
V23TH1
V23TL1
V23TH2
V23TL2
V23TH3
V23TL3
V22IH0
V22IL0
V22IH1
V22IL1
V22IH2
V22IL2
V22IH3
V22IL3
V23IH0
V23IL0
V23IH1
V23IL1
V23IH2
V23IL2
V23IH3
V23IL3
4.5
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
5.0
0.1
286
143
133
100
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
321
160
150
112
4.5
VD1 output voltage
V
V
V
4.5
4.5
4.5
4.5
VD2 output voltage
4.5
4.5
4.5
4.5
VD1 output voltage (polarity inverse)
4.5
4.5
4.5
4.5
VD2 output voltage (polarity inverse)
V
4.5
4.5
VP
VP
VP
VP
251
W0
W1
W2
W3
126
(Note VA03)
117
Vertical output pulse width
µs
88
22
2003-02-19
TA1318N
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
FV0
FV1
26.02 26.35 26.67
39.21 39.75 40.30
52.20 52.98 53.77
54.24 55.06 55.89
91.28 92.98 94.69
107.8 109.9 112.1
FV3
FV4
FV5
Vertical free-run frequency
(Note VA04)
Hz
FV6
FV20
57.0
57.0
57.0
57.0
311
624
668
891
9.6
60.0
60.0
60.0
60.0
321
643
689
918
11.8
6.8
63.0
63.0
63.0
63.0
332
663
710
947
14.0
7.9
FV21
FV22
FV23
FVPL0
FVPL1
FVPL2
FVPL3
15.75 kHz
31.50 kHz
33.75 kHz
45.00 kHz
Vertical pull-in range
(Note VA05)
Hz
5.7
Sync input-VD output phase
difference
µs
5.3
6.4
7.5
4.4
5.2
6.0
23
2003-02-19
TA1318N
Test Conditions and Measuring Method
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
HA01
Sync1/2 input horizontal sync phase
b
a
b
↓
a
(1) Set sub-address (02) 60.
(2) SW19-a and SW21-b.
↓
b
(3) Input Signal a (horizontal 33.75 kHz ) to pin 21 (SYNC1-IN).
(4) Set sub-address (02) 61.
(5) Measure the phase difference S
(6) SW19-b and SW21-a.
between pin 21 and pin 6 (AFC filter) wave form.
1PH
(7) Input Signal a (33.75 kHz ) to pin 19 (SYNC2-IN).
(8) Set sub-address (02) 01.
(9) Measure the phase difference S
between pin 19 and pin 6 (AFC filter) wave form.
2PH
29.63 µs
0.593 µs
Signal a
0.285 V
S
･S
1PH 2PH
Pin 6 wave form
24
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
(1) Set sub-address (00) 40 and (02) 82.
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
HA02
HD3 input horizontal sync phase
b
(2) Input signal b (horizontal 31.5 kHz ) to pin 11 (HD3-IN).
(3) Measure the phase difference HD
between pin 11 and pin 6 (AFC filter) wave form.
3PH
31.75 µs
2.35 µs
Signal b
1.5 V
HD
3PH
Pin 6 wave form
HA03
Polarity distinction active range
c
b
(1) Set sub-address (00) 70 and (02) 82.
(2) Input signal b ((horizontal 31.5 kHz ) to pin 11 (HD3-IN).
(3) Decreasing the duty of signal b to 0% (get negative period shorter), measure the duty of Signal b
(HD-DUTY1) when the phase between pin 11 and pin 13 (HD1-OUT) change.
(4) Increasing the duty of Signal b to 100% (get negative period longer), measure the duty of Signal b
(HD-DUTY2) when the phase between pin 11 and pin 13 (HD1OUT) change.
31.75 µs
2.35 µs
Signal b
1.5 V
A
B
* duty = A/(A + B) × 100 (%)
25
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
(1) Set sub-address (00) 0B and (02) 60.
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
HA04
Sync1 input threshold amplitude
Sync2 input threshold amplitude
b
a
b
↓
a
↓
(2) Input Signal a (33.75 kHz) to pin 21 (SYNC1-IN)
b
(3) Measure the sync. tip DC voltage of signal a on pin 21 (SYNC1-IN). (V
)
sync11
(4) Supply external voltage via 100 kΩ to pin 21 and increase the voltage.
(5) Measure the sync. tip DC voltage (V
) when HD-OUT desynchronizes with signal a calculate V
.
sync12
thS10
V
= V
− V
sync12 sync11
thS10
(6) Set sub-address (00) B1, B2 and B3 and calculate V
, V
and V
as well.
thS13
thS11 thS12
(7) Calculate V
, V
, V
and V
against pin 19 (SYNC2-IN) in the same way as 4 to 6.
thS23
thS20 thS21 thS22
29.63 µs
0.593 µs
Signal a
0.285 V
HA05
HD3 input threshold amplitude
(synchronization block)
c
b
(1) Set sub-address (00) 70 and (02) 62.
(2) Input Signal b (31.5 kHz) to pin 11 (HD3-IN).
(3) Increasing the voltage of Signal b from 0 V, measure the voltage of Signal b V
when HD1-OUT lock.
thHD3
31.75 µs
2.35 µs
Signal b
V
thHD1
26
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
HA06
HD1 input threshold voltage
HD2 input threshold voltage
HD3 input threshold voltage
(SW block)
b
(1) Set sub-address (00) 40.
(2) Input Signal b (31.5 kHz) to pin 3 (HD1-IN).
(3) Increasing the voltage of Signal b from 0 V, measure the voltage of Signal b V
when HD1-OUT lock.
thHD1
(4) Measure the voltage of pin 1 V
. Measure the voltage of pin 11 V
thHD2
as well.
thHD3
31.75 µs
2.35 µs
Signal b
V
thHD1
27
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
HA07
HD output phase adjustment variable
range
b
(1) Set sub-address (00) 30.
(2) Input Signal b (horizontal period T = 63.5 µs) to pin 11 (HD3-IN).
(3) Set sub-address (02) 02.
(4) Change form 00 to 7C sub-address (03), then measure the phase change quantity (∆HP0−) of pin 13
(HD1-OUT) wave form.
(5) Change form 80 to FC sub-address (03), then measure the phase change quantity (∆HP0+) of pin 13
(HD1-OUT) wave form.
(6) When horizontal period of Signal b is T = 31.75 µs measure ∆HP1− and ∆HP1+ as well.
(7) When horizontal period of Signal b is T = 29.63 µs measure ∆HP2− and ∆HP2+ as well.
(8) When horizontal period of Signal b is T = 22.22 µs measure ∆HP3− and ∆HP3+ as well.
T µs
2.35 µs
Signal b
1.5 V
Pin 15 wave form
data (00)
∆HP*−
Pin wave form
data (7C) (80)
∆HP*+
Pin wave form
data (FC)
28
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
HA08
Clamp pulse phase/width/level
b
(1) Set sub-address (00) B0.
(2) Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN).
(3) Set sub-address (02) 02.
(4) Measure the clamp pulse phase (CP ), width (CP ), output level (CP ) of pin 12 (CLP-OUT) against
S0
W0
V0
Signal a.
(5) Set sub-address (02) 12.
(6) Measure the clamp pulse phase (CP ), width (CP ), output level (CP ) of pin 12 (SCP-OUT) against
S1
W1
V1
Signal a.
(7) Input no-signal to pin 11.
(8) Measure the clamp pulse phase (CP ), width (CP ), output level (CP ) of pin 12 (SCP-OUT) against pin
S2
W2
V2
13 (HD-OUT).
29.63 µs
2.35 µs
Signal a
1.5 V
CP ･CP
S0
S1
Pin 12 wave form
Pin 13 wave form
Pin 12 wave form
CP ･CP
V0 V1
CP ･CP
W0
W1
CP
S3
CP
V3
CP
W3
29
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
HA09
Delayed HD pulse width
b
(1) Set sub-address (00) 70.
(2) Input Signal b (horizontal 31.5 kHz) to pin 11 (HD3-IN).
(3) Set sub-address (02) 62.
(4) Measure the pulse width (WdHD) of pin 6 (AFC filter) wave form.
31.75 µs
2.35 µs
Signal b
1.5 V
Wd-HD
Pin 6 wave form
30
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
S21
b
HB01
AFC phase detection current
OPEN
b
a
(1) BUS control data preset.
(2) Horizontal oscillation frequency is 15.75 kHz (00).
(3) SW6 open. Measure the Voltage of pin 6 V6 (no external supply).
(4) Connect external supply with pin 6, and supply the voltage (V6).
(5) Input signal (below figure) to pin 21 (SYNC1-IN). When INPUT SW is SYNC1-IN , measure V1 and V2 of pin
6 wave form.
(6) Supply V6 − 0.1 V and V6 + 0.1 V to pin 6, then measure V3 and V4.
(7) Calculate by following equations.
ID1 [µA] = (V1 [V] ÷ 1 [kΩ]) × 1000
ID2 [µA] = (V2 [V] ÷ 1 [kΩ]) × 1000
ID3 [µA] = (V3 [V] ÷ 1 [kΩ]) × 1000
ID4 [µA] = (V4 [V] ÷ 1 [kΩ]) × 1000
63.5 µs
Pin 21 wave form
0.25 V
V1, V3
Pin 6 wave form
V2, V4
HB02
VCO oscillation start voltage
(1) Increasing the voltage of pin 8 V
wave form.
form 2.5V, measure the voltage V
when pin 7 appear oscillation
VCO
CC
31
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
HB03
HD output pulse width
(free-run)
b
(1) BUS control data preset.
(2) When horizontal oscillation frequency is 15.75 kHz (00), measure the output pulse width TH00 of pin 13
(HD1-OUT) wave form.
(3) When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), measure the output
pulse width TH01, TH02, TH03 as well.
Pin 13 (HD1OUT)
wave form
TH
HB04
HB05
Horizontal free-run frequency
OPEN
b
b
(1) BUS control data preset.
(2) SW6 open. When horizontal oscillation frequency is 15.75 kHz (00), measure the oscillation frequency F00 of
pin 13 (HD1-OUT) wave form.
(3) When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), measure the oscillation
frequency F01, F10, F11 as well.
(4) When horizontal oscillation frequency is 15.75 kHz (00) and vertical free-run frequency is (101), measure the
oscillation frequency F50 of pin 15 wave form.
Horizontal oscillation control sensitivity OPEN
(1) BUS control data preset.
(2) SW6 open.
(3) Connect external voltage with pin 6 . Horizontal oscillation frequency is 15.75 kHz (00). Supply V6 (about 6.3
V) + 0.05 V or V6 − 0.05 V to pin 6, then measure the frequency FA, FB of pin 13 (HD1-OUT) wave form.
Calculate frequency changing ratio (BH00). BH00 = (FB − FA)/0.1
(4) When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), calculate BH01, BH10,
BH11 as wall.
32
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
VA01
VD1 input threshold voltage
VD2 input threshold voltage
VD3 input threshold voltage
(SW block)
b
(1) Set sub-address (00) 80.
(2) Input Signal a (vertical 60 Hz) to pin 4 (VD1-IN).
(3) Set sub-address (02) 00.
(4) Increasing the voltage of Signal a from 0 V. measure the voltage of Signal b V
when VD1-OUT lock.
thVD1
(5) Measure V
and V
against pin 2 and pin 10 as wall.
thVD3
thVD2
16.67 ms
0.12 ms
Signal a
V
thVD1
VA02
VD3 input threshold voltage
(synchronization block)
c
b
(1) Set sub-address (00) 70.
(2) Input Signal b (vertical 60 Hz) to pin 10 (VD3-IN).
(3) Set sub-address (02) 03.
(4) Increasing the voltage of Signal b from 0 V, measure the voltage of Signal a V
when VD1-OUT lock.
thVD3
16.67 ms
0.12 ms
Signal a
33
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
VA03
Vertical output pulse width
b
(1) Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN).
(2) Set sub-address (02) 02.
(3) When sub-addrss (00) is B0, measure the pulse width VPW2 of pin 22 (VD1-OUT) wave form.
(4) When sub-addrss (00) is 30, 70, F0, measure the pulse width VPW0, VPW1, VPW3 of pin 22 (VD1-OUT)
wave form as well.
29.63 µs
0.593 µs
Signal a
V period
Pin 22 wave form
VPW*
34
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
VA04
Vertical free-run frequency
b
(1) Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN).
(2) Set sub-address (00) B0.
(3) When sub-address (02) is 02, 22, 62, 82, A2 or C2, measure the frequency FV0, FV1, FV3, FV4, FV5 or FV6
of pin 22 (VD1-OUT) wave form.
(4) Input no-signal to pin 3 (HD1-IN).
(5) Set sub-address (02) 42.
(6) When sub-address (00) is 30, 70, B0 or F0, measure the frequency FV20, FV21, FV22 or FV23 of pin 22
(VD1-OUT) wave form.
29.63 µs
0.593 µs
Signal a
0.285 V
V period
Pin 22 wave form
VPW*
35
2003-02-19
TA1318N
SW Mode
S18 S19
Note
Item
Test Conditions and Measuring Method (V
= 9 V, Ta = 25 ± 3°C, unless otherwise specified)
CC
S06
c
S21
VA05
Vertical pull-in range
b
(1) Input Signal a (horizontal period T = 63.5 µs) to pin 11 (HD3-IN).
(2) Set sub-address (02) 02.
(3) Set sub-address (00) 30.
(4) Input Signal C (vertical period initial T = 1ms) to pin 10 (VD3-IN). Increasing vertical period of Signal C,
measure the frequency FVPL0 when pin 22 (VD1-OUT) wave form synchronize with Signal C.
(5) Input Signal a (horizontal period T = 31.75 µs) to pin 11 (HD3-IN).
(6) Set sub-address (00) 70.
(7) Measure FVPL1 as well.
(8) Input Signal a (horizontal period T = 29.63 µs) to pin 11 (HD3-IN).
(9) Set sub-address (00) B0.
(10) Measure FVPL2 as well.
(11) Input Signal a (horizontal period T = 22.22 µs) to pin 11 (HD3-IN).
(12) Set sub-address (00) F0.
(13) Measure FVPL3 as well.
horizontal period Tµs
0.593 µs
Signal a
1.5 V
V period (initial T = 1 ms)
0.25 ms
Signal c
1.5 V
measuring period
Pin 22 wave form
36
2003-02-19
TA1318N
Test Circuit
TP 1-in
S
0.01 µF
REG.
10 µF
9 V
9 V 5 V
a
b
c
SW18
Pin 20
SYNC1
a
SYNC2
a
SCL
#17
SDA
#16
b
b
SW21
SW19
#19
#24
#23
#22
#21
#20
#18
#15
#13
TP 2-in
S
24
23
22
21
20
19
18
17
16
15
14
13
10 µF
TA1318N
1
2
3
4
5
6
7
8
9
10
11
12
#1
#2
#3
#4
#6
#7
#9
#10
#11
#12
SW6
a
1 kΩ
c
b
Pin 7
Pin 6
Pin 1
Pin 2
Pin 3
Pin 4
Pin 9
Pin 10
Pin 11
Pin 12
M
○ Mylar capacitor
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TA1318N
Application Circuit 1 (Typical values)
9 V
VD2-
OUT
VD1- SYNC1-
SYNC2-
IN
HD2-
OUT
HD1-
OUT
DAC3
DAC1
20
SCL
17
SDA
16
OUT
IN
24
23
22
21
19
18
15
14
13
TA1318N
1
2
3
4
5
6
7
8
9
10
11
12
0.01 µF
360 Ω
100 µF
CSBLA503
KECZF30
HD2-IN
VD2-IN
HD1-IN
VD1-IN
DAC2
VD3-IN
HD3-IN CP-OUT
M
○ Mylar capacitor
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TA1318N
Application Circuit 2 (How to measure H/V frequency)
To measure H/V frequency of signal 2 (fH2: unknown) correctly, use two separated input terminals as the
following figure. One is for frequency measuring (SYNC2-in) and the other is for the AFC (SYNC1-IN). And
measure H/V frequency of signal 2 (fH2: unknown) on condition that AFC is stable (AFC locks in signal 1 (fH1:
known).) or that AFC is free-run when SYNC1-IN is no-signal.
Signal 1
(fH1: known)
Signal 1
AFC
SYNC1-IN
for H-AFC
Signal 2
(fH2: unknown)
BUS READ
Internal pulse (A)
Signal 2
H/V FREQ
COUNTER
SYNC2-IN
for
H/V freq. counter
TA1318N
This IC’s H/V frequency counting is done by internal pulse (A) which is made in AFC circuit. So, if AFC circuit
doesn’t lock in the regular frequency, the frequency of pulse (A) will not be correct and the H/V frequency data will
not be showed correct data.
Decision algorithm of H/V frequency detection (detection range, detection times and so on) should be determined
2
under consideration the factors such as signal strength, existence of ghost signal, H-AFC stability, I C BUS data
transmission and so on via prototype TV set evaluation.
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TA1318N
Package Dimensions
Weight: 1.22 g (typ.)
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TA1318N
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
41
2003-02-19
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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