TB62202AFG_技术文档

TB62202AFG

TOSHIBA Bi−CMOS Processor IC Silicon Monolithic

TB62202AFG

Dual-Stepping Motor Driver IC for OA Equipment Using PWM Chopper Type

The TB62202AFG is a dual-stepping motor driver driven by

chopper micro-step pseudo sine wave.

To drive two-phase stepping motors, Two pairs of 16-bit latch and

shift registers are built in the IC. The IC is optimal for driving

stepping motors at high efficiency and with low-torque ripple.

The IC supports Mixed Decay mode for switching the attenuation

ratio at chopping. The switching time for the attenuation ratio

can be switched in four stages according to the load.

Features

z Two stepping motors driven by micro−step pseudo sine wave

Weight: 0.79 g (typ.)

are controlled by a single driver IC

z Monolithic Bi-CMOS IC

z Low ON-resistance of Ron = 1.2 Ω (T = 25°C @1.0 A: Typ.)

j

z Two pairs of built-in 16-bit shift and latch registers

z Two pairs of built-in 4-bit DA converters for micro steps

z Built-in ISD, TSD, V

and V power monitor (reset) circuit for protection

M

DD

z Built-in charge pump circuit (two external capacitors)

z 36-pin power flat package (HSOP36-P-450-0.65)

z Output voltage: 40 V max

z Output current: 1.0 A/phase max

z Built-in Mixed Decay mode enables specification of four-stage attenuation ratio.

(The attenuation ratio table can be overwritten externally.)

z Chopping frequency can be set by external resistors and capacitors. High-speed chopping possible at 100 kHz or

higher.

Note: When using the IC, pay attention to thermal conditions.

These devices are easy damage by high static voltage.

In regards to this, please handle with care.

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TB62202AFG

Block Diagram

1. Overview (Power lines: A/B unit (C/D unit is the same as A/B unit))

RESET

Logic circuit

Current control data logic circuit

DATA

Chopping

16-bit shift register

reference circuit

16-bit latch

CLK

Chopping

waveform

generator

circuit

CR

STROBE

Current setting

Waveform

chapping

circuit

V

ref

4-bit DA

(analog control)

Torque control

Current feedback circuit

R

S

V

R

RS

S COMP

Output control circuit

circuit

V

M

ISD

TSD

Ccp 2

Ccp 1

circuit

Charge pump

circuit

Output circuit

(H-bridge)

V

/V

DDR MR

circuit

V

DD

M

Protected circuit

Out X

Stepping

motor

High voltage wiring (V )

M

Logic DATA

Analog DATA

IC terminal

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TB62202AFG

2. Logic unit A/B (C/D unit is the same as A/B unit)

Function

This circuit is used to input from the DATA pins micro−step current setting data and to transfer them to the

subsequent stage. By switching the SETUP pin, the data in the mixed decay timing table can be overwritten.

SETUP

Output control

circuit

Micro-step current setting data logic circuit

16-bit shift register

MIXED

DECAY

TIMING

DATA

CLK

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

A unit side

STROBE

16-bit latch

Data input

selector

DECAY

CURRENT

× 4 bits

B unit side

PHASE

TORQUE

× 2 bits

B unit side

× 1 bit

B

× 2 bits

RESET

Current feedback circuit

D/A circuit

Output control circuit

Note: The RESET and SETUP pins are pulled down in the IC by 10-kΩ resistor.

When not using these pins, connect them to GND. Otherwise, malfunction may occur.

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TB62202AFG

3. Current feedback circuit and current setting circuit

(A/B unit (C/D unit is the same as A/B unit)

Function

The current setting circuit is used to set the reference voltage of the output current using the micro−step

current setting data input from the DATA pins.

The current feedback circuit is used to output to the output control circuit the relation between the set

current value and output current. This is done by comparing the reference voltage output to the current

setting circuit with the potential difference generated when current flows through the current sense resistor

connected between RS and V .

M

The chopping waveform generator circuit to which CR is connected is used to generate clock used as

reference for the chopping frequency.

LOGIC

UNIT

TORQUE

0, 1

CURRENT

0~3

V

ref

15

Chopping waveform

generator circuit

100%

14

13

12

11

10

9

CR

85%

70%

50%

Torque

Control

circuit

8

7

6

Mixed decay

timing circuit

5

Waveform shaping circuit

Chopping reference circuit

Output stop signal (ALL OFF)

4

4-bit

D/A

3

2

circuit

1

0

Current setting circuit

Use in Charge mode

V

circuit 1

RS

(detects

potential

Output

R

COMP

S

control circuit

circuit 1

(Note 1)

NF

difference

between

(set current reached signal)

R

S

R

S

and V )

M

V

circuit 2

RS

(detects

potential

V

M

R

S

COMP

circuit 2

(Note 2)

RNF

difference

between

(set current monitor signal)

V

M

and R )

S

Use in Fast mode

Current feedback circuit

Note 1: RS COMP 1: Compares the set current with the output current and outputs a signal when the output current

reaches the set current.

Note 2: RS COMP 2: Compares the set current with the output current at the end of Fast mode during chopping.

Outputs a signal when the set current is below the output current.

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TB62202AFG

4. Output control circuit, current feedback circuit and current setting circuit (A/B unit

(C/D unit is the same as A/B unit)

Micro-step current setting

data logic circuit

Chopping

reference circuit

DECAY

MODE

MIXED

DECAY

TIMING

circuit

Output control circuit

PHASE

NF

set current

reached signal

Current

feedback

circuit

CR

COUNTER

RNF

MIXED

DECAY

TIMING

set current

monitor signal

CR COUNTER

Charge start

Current

setting

circuit

Output stop

signal

U

L

1

2

1

2

Output circuit

Output control circuit

L

Output RESET signal

V

DD

V

M

Power supply

for upper

output MOS

transistors

RESET

Output

circuit

ISD (current

shutdown)

circuit

Charge

pump

halt

V

H

Output pin

signal

V

Reset signal

MR

Ccp A

Ccp B

Ccp C

Charge pump

circuit

V

M

circuit

selector

circuit

V

DDR

V

DD

circuit

Thermal

shut down

(TSD)

circuit

Charge pump

circuit

Protection circuit

MICRO-STEP

CURRENT SETUP

LATCH CLEAR signal

MIXED DECAY

TIMING TABLE

CLEAR signal

LOGIC

V

: V

DDR DD

power on Reset

V

MR

:

V

M

ISD:

Current shutdown circuit

TSD: Thermal shutdown circuit

Note: The RESET pins is pulled down in the IC by 10-kΩ resistor.

When not using the pin, connect it to GND. Otherwise, malfunction may occur.

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TB62202AFG

5. Output equivalent circuit (A/B unit (C/D unit is the same as A/B unit)

To V

M

R

S A

R

RS A

Output driver

circuit

U

1

U

2

U

1

2

L

1

From output

control circuit

2

Output A

Power supply

for upper

L

1

L

2

Output

A

output MOS

transistors

(V )

H

Phase A

V

M B

R

S B

R

RS B

Output driver

circuit

U

1

U

2

U

1

2

L

1

From output

control circuit

2

Output B

M

Power supply

for upper

L

1

L

2

Output B

output MOS

transistors

(V )

H

Phase B

PGND

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TB62202AFG

6. Input equivalent circuit

(1) Logic input circuit (CLK, DATA, STROBE)

V

27

IN

DD

To Logic IC

150 Ω

30/29/31

25/26/24

GND

F

IN

(2) Input circuit (

)

RESET

V

27

DD

IN

28

To Logic IC

150 Ω

GND

F

IN

(3) V input circuit

ref

V

27

IN

DD

4

9/10

To D/A circuit

GND

F

IN

Note: RESET pin is pulled down. Do not use them open.

When not using these pins, connect them to GND.

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TB62202AFG

Pin Assignment

(top view)

V

1

2

3

4

5

6

7

8

9

36

35 OUT

34

33 PGND

V

M B

M A

OUT B

A

R

S B

S A

PGND

OUT B

NC

32 OUT A

31 STROBE AB

30 CLK AB

29 DATA AB

28 RESET

Ccp A

CR

V

REF AB

TB62202AFG

V

(F

)

V

(F )

IN

SS

IN

SS

DD

V

27

REF CD

NC

10

11

12

13

14

15

16

26 DATA CD

25 CLK CD

24 STROBE CD

23 OUT C

Ccp B

Ccp C

OUT D

PGND

22 PGND

R

S D

21

20 OUT C

19

R

S C

OUT D

17

18

V

M C

M D

Note: [Important] If this IC is inserted reverse, voltages exceeding the voltages of standard may be applied to some

pins, causing damage.

Please confirm the pin assignment before mounting and using the IC.

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TB62202AFG

Pin Description

Pin No.

Pin Symbol

Description

Voltage major for output B block

1

2

3

4

5

6

7

8

9

V

M B

OUT B

Output B pin

R

S B

Channel B current pin

Power GND pin

PGND

OUT B

NC

Output B pin

Non connection

C

cp

A

Capacitor pin for charge pump (Ccp1)

External C/R (osc) pin (sets chopping frequency)

CR

V

input pin AB

ref

REF AB

F

IN

V

F (V ) : Logic GND pin

IN SS

SS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

V

Vref input pin CD

REF CD

NC

Non connection

C

B

C

Capacitor pin for charge pump (Ccp2)

Output D pin

cp

OUT D

PGND

Power GND pin

R

S D

Channel D current pin

Output D pin

OUT D

V

Voltage major for output D block

Voltage major for output C block

Output C pin

M D

M C

OUT C

R

S C

Channel C current pin

Power GND pin

PGND

OUT C

Output C pin

STROBE CD CD STROBE (latch) signal input pin (

: LATCH)

CLK CD

CD clock input pin

DATA CD

CD serial data signal input pin

Power pin for logic block

V

DD

F

IN

V

F (V ) : Logic GND pin

IN SS

SS

28

RESET

DATA AB

CLK AB

Output reset signal input pin (L : RESET)

AB serial data signal input pin

AB clock input pin

29

30

31

32

33

34

35

36

STROBE AB AB STROBE (latch) signal input pin (

: LATCH)

OUT A

PGND

Output A pin

Power GND pin

R

S A

Channel A current pin

Output A pin

OUT A

V

Voltage major for output A block

M A

Note: How to handle GND pins

All power GND pins and FIN (V : signal GND) pins must be grounded.

SS

Since FIN also functions as a heat sink, take the heat dissipation into consideration when designing the board.

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TB62202AFG

Signal Functions

1. Serial input signals (for A/B. C/D is the same as A/B)

Data No.

Name

TORQUE 0

Functions

0

LSB

DATA No.0, 1 = HH: 100%, LH: 85%

HL: 70%, LL: 50%

1

TORQUE 1

2

DECAY MODE B

0

1

00: DECAY MODE 0, 01: DECAY MODE 1

10: DECAY MODE 2, 11: DECAY MODE 3

3

4

Current B

0

1

2

3

Used for setting current.

(LLLL = Output ALL OFF MODE)

4−bit current B data

5

6

(Steps can be divided into 16 by 4−bit data)

7

(Note 1)

8

PHASE B

Phase information (H: OUT A: H, OUT A : L)

9

DECAY MODE A

0

1

00: DECAY MODE 0, 01: DECAY MODE 1

10: DECAY MODE 2, 11: DECAY MODE 3

10

11

Current A

0

1

2

3

Used for setting current.

(LLLL = Output ALL OFF MODE)

4−bit current A data

12

13

(Steps can be divided into 16 by 4−bit data)

14

15 MSB

PHASE A

Phase information (H : OUT A : H, OUT A : L)

Note 1: Serial data input order

Serial data are input in the order LSB (DATA 0)

→ MSB (DATA 15)

Role of Data

Data Name

Number of Bits

2

Functions

Roughly regulates the current (four stages).

Common to A and B units.

TORQUE

Selects Decay mode.

A and B units are set separately.

DECAY MODE

CURRENT

PHASE

2 × 2 phases

4 × 2 phases

1 × 2 phases

Sets a 4−bit micro−step electrical angle.

A and B units are set separately.

Determines polarity (+ or −).

A and B units are set separately.

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TB62202AFG

2. Serial input signal functions

Input

Action

VDDR

(Note 1) or

Operation of

TSD/ISD

CLK

STROBE

DATA

RESET

(Note 2)

V

MR

×

H

L

×

H

L

No change in shift register.

H

H level is input to shift register.

L level is input to shift register.

Shift register data are latched.

Qn

×

Output off, charge pump halted

(S/R DATA CLR)

×

L

×

L

Output off (S/R DATA CLR)

Charge pump halted

×

L

Mixed decay timing table cleared (only V

)

DDR

Output off (S/R DATA HOLD)

Charge pump halted

×

H

Restored when RESET goes from Low to High

×:

Qn:

Note 1: V

Don’t Care

Latched output level when STROBE is

and V

.

DDR

MR

H when the operable range (3 V typical) or higher and L when lower.

When one of V or V is operating, the system resets (OR relationship).

DDR

MR

Note 2: High when TSD is in operation.

When one of TSD or ISD is operating, the system resets (OR relationship).

Note: Function of overcurrent protection circuit

Until the RESET signal is input after ISD is triggered, the overcurrent protection circuit remains in operation.

During ISD, the charge pump stays halted.

When TSD and ISD are operating, the charge pump halts.

3. PHASE functions

Input

Function

H

L

Positive polarity (A: H, Α : L)

Negative polarity (A: L, Α : H)

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TB62202AFG

4. DECAY mode X0, X1 functions

DECAY Mode X1

DECAY Mode X0

Function

Decay Mode 0

(Initial value: SLOW DECAY MODE)

L

H

L

Decay Mode 1

(Initial value: MIXED DECAY MODE: 37.5%)

Decay Mode 2

(Initial value: MIXED DECAY MODE: 75%)

H

Decay Mode 3

(Initial value: FAST DECAY MODE)

H

5. TORQUE functions

TORQUE 0

TORQUE 1

Comparator Reference Voltage Ratio

H

L

H

L

100%

85%

70%

50%

H

L

6. Current AX (BX) functions

Set Angle

Step

A

B

0

3

2

1

0

3

2

1

16

15

14

13

12

11

10

9

90.0

84.4

78.8

73.1

67.5

61.2

56.3

50.6

45.0

39.4

33.8

28.1

22.5

16.9

11.3

5.6

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

8

L

H

7

H

L

H

L

H

L

H

L

6

L

H

L

5

L

H

L

H

L

4

L

H

3

L

H

L

H

L

H

L

2

L

H

1

L

H

L

H

0

0.0

L

By inputting the above current data (A: 4-bit, B: 4-bit), 17-microstep drive is possible. For 1 step fixed to 90

degrees, see the section on output current vector line (85 page).

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TB62202AFG

7. Serial data input setting

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

STROBE

Note: Data input to the DATA pin are 16-bit serial data.

Data are transferred from DATA 0 (Torque 0) to DATA 15 (Phase A). Data are input and transferred at the

following timings.

At CLK falling edge: data input

At CLK rising edge: data transfer

After data are transferred, all data are latched on the rising edge of the STROBE signal.

As long as STROBE is not rising, the signal can be either Low or High during data transfer.

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TB62202AFG

Maximum Ratings (Ta = 25°C)

Characteristics

Symbol

Rating

Unit

Logic supply voltage

Output voltage

V

7

V

DD

V

40

1.5

V

M

Output current

I

A/phase (Note 1)

V

OUT

Current detect pin voltage

V

4.5

+ 7.0

+ 0.4

RS

M

Charge pump pin maximum voltage

(CCP1 pin)

V

H

Logic input voltage

V

to V

DD

IN

1.4

3.2

W

(Note 2)

(Note 3)

Power dissipation

P

D

Operating temperature

Storage temperature

Junction temperature

T

−40 to 85

−50 to 150

150

°C

opr

T

stg

T

j

Note 1: Perform thermal calculations for the maximum current value under normal conditions. Use the IC at 1.2 A or

less per phase.

Note 2: Input 7 V or less as V

.

IN

Note 3: Measured for the IC only. (Ta = 25°C)

Note 4: Measured when mounted on the board. (Ta = 25°C)

Ta: IC ambient temperature

T

: IC ambient temperature when starting operation

opr

T : IC chip temperature during operation T (max) is controlled by TSD (thermal shut down circuit)

j

Recommended Operating Conditions (Ta = 0 to 85°C)

Characteristics

Power supply voltage

Symbol

Test Condition

Min

Typ.

Max

Unit

V

⎯

4.5

20

5.0

24

5.5

34

V

DD

Output voltage

V

= 5.0 V

DD

M

Ta = 25°C, per phase

I

⎯

0.6

0.9

A

OUT (1)

OUT (2)

(when one motor is driven)

Output current

Ta = 25°C, per phase

(when two motors are driven)

Logic input voltage

Clock frequency

V

⎯

GND

1.0

40

⎯

6.25

100

3.0

V

MHz

KHz

V

IN

DD

f

V

= 5.0 V

25

CLK

DD

Chopping frequency

Reference voltage

Current detect pin voltage

f

150

chop

V

= 24 V, T

orque

= 100%

2.0

0

V

ref

M

DD

V

= 5.0 V

1.0

1.5

V

RS

DD

Note: Use the maximum junction temperature (T ) at 120°C or less

j

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TB62202AFG

Electrical Characteristics 1

(Unless otherwise specified, Ta = 25°C, V = 5 V, V = 24 V)

DD

M

Test

Circuit

Characteristics

Symbol

Test Condition

Min

2.0

Typ.

Max

Unit

V

DD

High

Low

V

DD

IN (H)

+ 0.4

Input voltage

1

2

CLK, RESET , STROBE, DATA pins

GND

− 0.4

V

GND

0.8

IN (L)

I

―

1.0

IN1 (H)

Input current 1

Input current 2

CLK, STROBE, DATA pins

RESET , SETUP pins

µA

I

IN1 (L)

IN2 (H)

I

700

I

IN2 (L)

V

_DD= 5 V (STROBE, RESET ,

I

^DATA= L), RESET = L,

―

3.0

4.0

6.0

8.0

DD1

Logic, output all off

Power dissipation (V

pin)

2

3

mA

DD

Output OPEN, f

= 6.25 MHz

CLK

LOGIC ACTIVE, V

I

= 5 V,

DD

DD2

Charge pump = charged

Output OPEN (STROBE, RESET ,

DATA = L), RESET = L,

Logic, output all off

I

―

5.0

12

6.0

20

M1

M2

Charge Pump = no operation

Output OPEN, f

CLK

LOGIC ACTIVE, V

= 6.25 MHz

= 5 V,

DD

Power dissipation (V pin)

M

mA

V

= 24 V, Output off

M

Charge Pump = charged

Output OPEN, f

LOGIC ACTIVE, 100 kHz

= 6.25 MHz

CLK

I

4

5

chopping (emulation), Output OPEN,

Charge Pump = charged Ccp1 =

0.22 µF, Ccp2 = 0.01µf

―

30

40

M3

Output standby

current

V

= VM = 24 V, V

= 0 V,

out

RS

RESET = H, DATA = ALL L

Upper

Lower

I

−400

−200

―

OH

V

= VM = 24 V, V = 24 V,

RS

out

µA

Output bias current

I

OB

RESET = H, DATA = ALL L

Output leakage

current

V

= VM = CcpA = V = 24 V,

RS

RESET = L

out

I

1.0

OL

V

= 3.0 V,

ref

High

(Reference)

V

(Gain) = 1/5.0

―

100

―

RS (H)

TORQUE = (H.H) = 100% set

V

= 3.0 V, V (Gain) = 1/5.0

ref

Comparator

reference voltage

ratio

Mid High

Mid Low

LOw

V

83

68

48

85

70

50

87

72

52

RS (MH)

TORQUE = (H.L) = 85% set

6

7

%

V

= 3.0 V, V (Gain) = 1/5.0

ref

V

RS (ML)

TORQUE = (L.H) = 70% set

V

= 3.0 V, V (Gain) = 1/5.0

ref

V

RS (L)

TORQUE = (L.L) = 50% set

Differences between output current

channels

Output current differential

∆I

out1

−5

―

5

I

= 1000 mA

out

Output current setting differential

RS pin current

∆I

7

8

I

= 1000 mA

−5

―

5

%

out2

out

VRS = 24 V, V = 24 V,

RESET = L (RESET status)

M

IRS

―

10

µA

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TB62202AFG

Test

Circuit

Characteristics

Symbol

Test Condition

Min

―

Typ.

1.1

1.4

Max

1.3

1.6

Unit

I

= 1.0 A, V

= 5.0 V

DD

out

T = 25°C, Drain-source

R

ON (D-S) 1

ON (D-S) 2

j

I

= 1.0 A, V

= 5.0 V

DD

out

T = 25°C, Source-drain

―

j

Output transistor drain-source

on-resistance

9

Ω

I

= 1.0 A, V

= 5 V,

DD

out

T = 105°C, Drain-source

―

j

I

= 1.0 A, V

= 5 V,

DD

out

j

―

T = 105°C, Source-drain

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TB62202AFG

Electrical Characteristics 2

(Unless otherwise specified, Ta = 25°C, V = 5 V, V = 24 V)

DD

M

Test

Circuit

Characteristics

input voltage

Symbol

Test Condition

Min

2.0

Typ.

Max

Unit

V

= 24 V, V

= 5 V,

DD

M

V

10

⎯

V

DD

ref

RESET = H, Output on

RESET = H, Output off

input current

I

V

= 24 V, V

= 3.0 V

= 5 V,

0

⎯

100

µA

ref

M

ref

DD

V

= 24 V, V

M

V

attenuation ratio

V

(GAIN)

ref

6

RESET = H, Output on,

1/4.8

1/5.0

1/5.2

⎯

ref

V

= 2.0 to V

− 1.0 V

ref

DD

T TSD (Note

j

TSD temperature

11

12

13

14

V

= 5 V, V = 24 V

130

⎯

170

⎯

°C

V

DD

M

1)

T TSD

j

− 35

TSD return temperature difference

∆T TSD

j

T TSD = 130 to 170°C

j

V

= 24 V, RESET = H,

M

V

return voltage

V

2.0

⎯

4.0

⎯

DD

DDR

STROBE = H

V

= 5 V, RESET = H,

DD

STROBE = H

return voltage

V

⎯

V

M

MR

Over current protected circuit

operation current

I

V

= 5V, V = 24V,

M

SD

DD

fchop = 100 kHz set

2.6

A

(Note 2)

Note 1: Thermal shut down (TSD) circuit

When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal

reset circuit is activated switching the outputs of both motors to off.

When the temperature is set between 130 (min) to 170°C (max), the TSD circuit operates. When the TSD

circuit is activated, the function data latched at that time are cleared. Output is halted until the reset is

released. While the TSD circuit is in operation, the charge pump is halted.

Even if the TSD circuit is activated and RESET goes H → L → H instantaneously, the IC is not reset until

the IC junction temperature drops 35°C (typ.) below the TSD operating temperature (hysteresis function).

Note 2: Overcurrent protection circuit

When current exceeding the specified value flows to the output, the internal reset circuit is activated

switching the outputs of both shafts to off.

When the ISD circuit is activated, the function data latched at that time are cleared.

Until the RESET signal is input, the overcurrent protection circuit remains activated.

During ISD, the charge pump halts.

For failsafe operation, be sure to add a fuse to the power supply.

17

2005-04-04

TB62202AFG

Electrical Characteristics 3

(Ta = 25°C, V = 5 V, V = 24 V, I

= 1.0 A)

DD

M

out

Test

Circuit

Characteristics

SymboL

Test Condition

θA = 90 (θ16)

Min

Typ.

Max

Unit

⎯

93

91

87

83

78

72

66

58

51

42

33

24

15

5

100

98

96

92

88

83

77

71

63

56

47

38

29

20

10

0

⎯

―

97

93

88

82

76

68

61

52

43

34

25

15

⎯

θA = 84 (θ15)

θA = 79 (θ14)

θA = 73 (θ13

θA = 68 (θ12)

θA = 62 (θ11)

θA = 56 (θ10)

θA = 51 (θ9)

θA = 45 (θ8)

θA = 40 (θ7)

θA = 34 (θ6)

θA = 28 (θ5)

θA = 23 (θ4)

θA = 17 (θ3)

θA = 11 (θ2)

θA = 6 (θ1)

Chopper current

Vector

15

⎯

%

θA = 0 (θ0)

⎯

18

2005-04-04

TB62202AFG

AC Characteristics (Ta = 25°C, V = 24 V, V = 5 V, 6.8 mH/5.7 Ω)

M

DD

Test

Circuit

Characteristics

Clock frequency

SymboL

Test Condition

Min

Typ.

Max

Unit

f

16

⎯

1.0

40

20

40

20

⎯

25

⎯

400

MHz

CLK

t

w (CLK)

Minimum clock pulse width

16

⎯

ns

t

⎯

wp (CLK)

t

⎯

wn (CLK)

t

⎯

STROBE

Minimum STROBE pulse width

t

⎯

STROBE (H)

t

⎯

STROBE (L)

t

⎯

suSIN-CLK

Data setup time

Data hold time

16

⎯

ns

t

⎯

suST-CLK

t

⎯

hSIN-CLK

⎯

t

⎯

hCLK-ST

t

0.1

15

10

1.2

2.5

300

r

Output Load ; 6.8 mH/5.7 Ω

t

⎯

f

t

⎯

pLH (ST)

pHL (ST)

pLH (CR)

pHL (CR)

Output transistor switching

characteristic

STROBE (↑) to VOUT

Output Load; 6.8 mH/5.7 Ω

18

µs

⎯

t

⎯

CR to VOUT

Output Load; 6.8 mH/5.7 Ω

⎯

Noise rejection dead band time

t

19

20

I

_out= 1.0 A

200

ns

BLNK

CR reference signal oscillation

frequency

f

C

_osc= 560 pF, R_osc= 3.6 kΩ

⎯

40

⎯

800

100

2

⎯

150

⎯

kHz

CR

f

Output active (I_out= 1.0 A)

^{Step fixed, Ccp1}= 0.22 µF,

Ccp2 = 0.01µF

chop (min)

chop (typ.)

chop (max)

Chopping frequency range

Chopping frequency

kHz

ms

20

21

Output active (I = 1.0 A)

out

CR CLK = 800 kHz

f

chop

Ccp2 = 0.22µF, Ccp = 0.01 µF

= 24 V, V = 5 V,

Charge pump rise time

t

V

4

ONG

M

DD

RESET = L → H

19

2005-04-04

TB62202AFG

Test Waveforms (Timing waveforms and names)

t

w (CLK)

50%

CLK

t

hCLK-ST

suST-CLK

t

wp

wn

50%

STROBE

t

STROBE (H)

STROBE (L)

t

STROBE

t

hSIN-CLK

suSIN-CLK

50%

DATA15

DATA0

DATA

50%

CR waveform

(reference)

t

pHL (CR)

t

pHL (ST)

90%

50%

10%

OUTPUT

voltage A

t

pLH (CR)

pLH (ST)

90%

50%

10%

90%

50%

10%

OUTPUT

voltage A

t

f

r

20

2005-04-04

TB62202AFG

Test Waveforms (Timing waveforms and names)

OSC-Charge Delay

H

OSC-Fast Delay

OSC (CR)

L

T chop

H

OUTPUT

50%

voltage A

L

H

OUTPUT

50%

voltage A

L

Set current

OUTPUT

current

L

Charge

Slow

Fast

21

2005-04-04

TB62202AFG

Calculation of Set Current

Determining R and V determines the set current value.

RS

ref

T

(T

=100, 85,70,50%: input serial data)

1

orque orque

I

out

(Max) =

× V (V) ×

ref

R

(Ω)

V

ref

(GAIN)

RS

1/5.0 is V (gain) : V attenuation ratio (typ.).

ref

For example,

to input V = 3 V and Torque = 100% and to output I

ref out

= 0.8 A,

R

RS

= 0.75 Ω (0.5 W or more) is required.

Formulas for Calculating CR Oscillation Frequency (Chopping reference frequency)

The CR oscillation frequency and f

1

can be calculated by the following formulas:

chop

f

=

[Hz]

CR

KA ×(C× R× KB×C)

KA (constant): 0.523

KB (constant): 600

f

CR

8

f

=

[Hz]

chop

Example : When Cosc = 1,000 pF and Rosc = 2.0 kΩ are connected, f

= 735 kHz.

CR

At this time, the chopping frequency f

is : f

= f_CR/8 = 92 kHz.

chop

1

Note:

f

=

CR

t

CR

t

= t (Charge) + t (Dis- Charge)

CR

CR oscillation CR charge

cycle time

CR distance

time

At this time, t (CR-discharge) is subject to the following condition:

600 ns > t (CR-discharge) > 400 ns.

Be sure to set the CR value in accordance with this condition.

22

2005-04-04

TB62202AFG

CR Circuit Constants

OSC circuit oscillation waveform

t (CR-charge)

t (CR-dis-charge)

E1

E2

t = 0

t = 1

t = 2

The OSC circuit generates the chopping reference signal by charging and discharging the external capacitor Cosc

through current supplied from the external resistor Rosc in the OSC block.

Voltages E1 and E2 in the diagram are set by dividing the V

The actual current chopping time is 1/8 the CR frequency.

by approximately 3/5 (E1) and 2/5 (E2).

DD

[Important: Setting the CR Circuit Constants]

The CR oscillation waveform is converted in the IC to the CLK waveform (CR-CLK signal) and used for control.

If the CR waveform discharge time is set outside the range shown below, the operation of the IC is not guaranteed.

Be sure to set the CR waveform discharge time within the following range.

600 ns > t (CR discharge) > 400 ns

23

2005-04-04

TB62202AFG

IC Power Dissipation

IC power dissipation is classified into two: power consumed by transistors in the output block and power consumed

by the logic block and the charge pump circuit.

(1) Power consumed by the Power Transistor (calculated with R_on= 1.3 Ω)

In Charge mode, Fast Decay mode, or Slow Decay mode, power is consumed by the upper and lower

transistors of the H bridges. The following expression expresses the power consumed by the transistors of a

H bridge.

P (out) = 2 (T ) × I

(A) × V (V) = 2 × I ^2 × R ·························(1)

DS out on

r

out

The average power dissipation for output under 4-bit micro step operation (phase difference between

phases A and B is 90°) is determined by expression (1).

Thus, power dissipation for output per unit is determined as follows (2) under the conditions below.

R

I

= 1.3 Ω (@1.0 A)

(Peak : Max) = 0.6 A

= 24 V

on

t

ou

V

M

= 5 V

DD

P (out) = 2 (T ) × 0.6 (A)^2 × 1.3 (Ω) ·················································(2)

r

= 0.936 (W)

(2) Power consumed by the logic block and IM

The following standard values are used as power dissipation of the logic block and IM at operation.

I (LOGIC) = 2 mA (Typ.): /unit

I (IM3) = 12.5 mA (Typ.): operation/unit

I (IM1) = 6.0 mA (Typ.): stop/unit

The logic block is connected to V

(5 V). IM (total of current consumed by the circuits connected to V

DD

M

and current consumed by output switching) is connected to V (24 V). Power dissipation is calculated as

M

follows:

P (Logic and IM) = 5 (V) × 0.002 (A) + 24 (V) × 0.0125 (A) ....................... (3)

= 0.31 (W)

(3) Thus, power dissipation for 1 unit (P) is determined as follows by (2) and (3) above.

P = P (out) + P (Logic and IM) = 1.246 (W)

Power dissipation for 1 unit at standby is determined as follows:

P (standby) = 24 (V) × 0.006 (A) + 5 (V) × 0.002 (A)

= 0.154 (W)

When one motor driving = 100 %, power dissipation is determined as follows:

P (all) = 1.246 (W) + 0.154 (W) = 1.4 (W)

For thermal design on the board, evaluate by mounting the IC.

24

2005-04-04

TB62202AFG

MIXED DECAY Mode Waveforms (concept of mixed decay mode)

f

chop

CR pin

input

waveform

Set current value

DECAY MODE 0

Slow

NF

SLOW

DECAY

MODE

Charge

DECAY MODE 1

Set current value

Slow

NF

37.5%

MIXED

DECAY

MODE

Charge

Monitoring

set current

value

Fast

MDT

RNF

DECAY MODE 2

Set current value

NF

Charge

75%

Fast

MIXED

DECAY

MODE

MDT

Monitoring

set current

value

RNF

DECAY MODE 3

FAST

NF

Set current value

Charge

DECAY

MODE

Fast

Monitoring

set current

value

RNF

100%

87.5%

75%

62.5%

50%

37.5%

25%

12.5%

0

NF is the point where the output current reaches the set current value. RNF is the timing for monitoring the set

current.

In Mixed Decay and Fast Decay modes, where the condition RNF (set current monitor signal) < (output current)

applies, Charge mode is cancelled at the next chopping cycle (charge cancel circuit). Therefore, at the next chopping

cycle, the IC enters Slow + Fast modes (Slow → Fast at MDT).

25

2005-04-04

TB62202AFG

Test Circuit (A/B unit only. C/D unit conforms to A/B unit.)

1. V

, V

IN (H) IN (L)

V

9

ref AB

8

CR

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

A

27 V

A 32

DD

I

, I

DD1 DD2

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

Vary V

IN

R

3

1

RS B

R

RS B

V

M B

I

, I

A

IN (H) IN (L)

V

SS

)

(F

IN

SGND

Ccp 2

28 RESET

0 V to 5 V

No reset at testing

RESET = 5 [V]

Ccp C 13

Ccp B 12

6

SETUP

Ccp A 7

P-GND

V

DD

SGND

Ccp 1

: PGND

: SGND (V

)

SS

Test method

V

IN

(H): Set RESET to High and vary the logic input voltage from 0 to 7 V.

Monitor I

and measure the change point (V = 24 V).

M

DD

(L): Set RESET to High and vary the logic input voltage from 5 to 0 V.

VIN

Monitor I

and measure the change point.

DD

Setup data

H

DATA

L

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

CLK

L

H

STROBE

L

26

2005-04-04

TB62202AFG

2. I

_,I

, I

(A/B unit only. C/D unit conforms to A/B unit.)

IN (H) IN (L) DD1 DD2

V

9

ref AB

8

CR

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

A

27 V

A 32

DD

I

, I

DD1 DD2

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

Vary V

IN

R

3

1

RS B

R

RS B

V

M B

I

, I

A

IN (H) IN (L)

V

SS

)

(F

IN

SGND

Ccp 2

28 RESET

0 V to 5 V

Ccp C 13

Ccp B 12

No reset at testing

RESET = 5 [V]

6

SETUP

Ccp A 7

P-GND

V

DD

SGND

Ccp 1

: PGND

: SGND (V

)

SS

Test method

I

: Set RESET to High, set the the logic input voltage to 5 V, and measure the input current.

: Set RESET to High, set the the logic input voltage to 0 V, and measure the input current.

IN (H)

:

Apply V , input RESET, and measure I

.

DD1

DD

Input 6.25 MHz clock and measure the current when the logic is operating. Set output to OPEN.

DD2

Setup data

H

DATA

L

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

CLK

L

H

STROBE

L

27

2005-04-04

TB62202AFG

3. IM , IM (A/B unit only. C/D unit conforms to A/B unit.)

1

2

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

A

IM

28 RESET

Ccp C 13

Ccp B 12

At IM1 testing: RESET = L (0 V)

At IM2 testing: RESET = H (5 V)

Ccp A

7

P-GND

SETUP

6

Ccp 1

: PGND

V

DD

SGND

: SGND (V

)

SS

Test method

IM : Set the logic block to non-active (DATA = all 0), V

= 5 V, V = 24 V, and output to open. Measure the

M

1

DD

current input from V supply. RESET = L

M

IM : Set the logic block only to active (CLK = 6.25 MHz), V = 24 V, and output to open. Measure the

2

M

current input from V supply. RESET = H

M

Setup data

H

DATA

L

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

CLK

L

H

STROBE

L

28

2005-04-04

TB62202AFG

4. IM (A/B unit only. C/D unit conforms to A/B unit.)

3

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

A

IM

28 RESET

Ccp C 13

Ccp B 12

No reset at testing

V

DD

SGND

RESET = 5 [V]

Ccp A

7

P-GND SETUP

6

Ccp 1

: PGND

: SGND (V

)

SS

This is the IM current when all of the circuits, including the output transistors, in the IC are operating.

The IM current includes the current dissipation in the charge pump circuit, output gate loss, and output

predriver.

Because the IM current (IM ) is input from the RS pin, which is also used for the output current, IM cannot be

3

measured by the normal testing methods.

Use the method shown below.

Setup data

The serial data PHASE signal (both A and B) switch over to high or low.

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

Test method

Set output to open, change phase data from 1 → 0 → 1 → 0 and perform switching. When testing, input

phase data at double the chopping frequency (if f = 100 kHz, fDATA = 200 kHz) and measure the current

chop

value of V supply.

M

fDATA = 200 kHz means that the phase switches at 200 kHz.

29

2005-04-04

TB62202AFG

Number of switchings at phase switching

Number of switchings at actual operation

Mode changes three times

in one chopping cycle.

One phase switching

(16-bit data input)

To V

M

Four transistors switching

Chopping cycle

U

1

U

2

U

1

U

2

OFF

ON

OFF

ON

Load

Switches by phase data

Load

Two transistors

switching

OFF

ON

L

1

L

2

L

1

L

2

Charge

Slow

Two transistors

switching

OFF

ON

OFF

ON

OFF

ON

Four transistors switching

One phase switching

(16-bit data input)

PGND

Eight transistors switching

in one chopping cycle

OFF

ON

Four transistors are switched at one phase switching

Fast

Number of switchings at actual operation = 2 × number of switchings at phase switching.

Therefore, switching the phase at 2 × chopping cycle matches the number of switchings at actual operation

with the number of switchings at phase switching, and allows the actual current dissipation, IM , to be

3

measured.

30

2005-04-04

TB62202AFG

5. I , I , I (A/B unit only. C/D unit conforms to A/B unit.)

OB OH OL

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

27 V

A 32

A

DD

I

OB

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

I

, I

OH OL

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

I

Ccp C 13

Ccp B 12

OL

No reset at testing

V

DD

SGND

RESET = 5 [V]

Ccp A

7

P-GND

Ccp 1

: PGND

: SGND (V

)

SS

Test method

I

:

With V = 24 V, V

to GND, and measure the supply current.

= 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins

OH

M

DD

:

With V = 24 V, V = 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins

OB

M

DD

to V , and measure the supply current.

M

:

With V = 24 V, V

= 5 V, and logic input all = 0 applied, set RESET = L, connect the output pins

OL

M

DD

to GND, and measure the supply current.

Setup data

H

DATA

L

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

CLK

L

H

STROBE

L

31

2005-04-04

TB62202AFG

6. V (H to L), V (GAIN) (when measuring phase A) after measurement

RS

ref

(A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

V

31 STROBE AB

30 CLK AB

Oscilloscope

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

Vary between

0 and 1 V.

V

M B

V

SS

(F

IN

)

SGND

28 RESET

Ccp C 13

Ccp B 12

Ccp 2

Ccp 1

No reset at testing

V

DD

RESET = 5 [V]

Ccp A

7

P-GND

SGND

: PGND

: SGND (V

)

SS

V

Input torque data = 100% (HH) and vary the voltage between V and R pins.

M S

RS (H to L):

Measure the voltage (V ) when output changes from fixed Charge mode to another mode.

RS

Also measure V when torque data = 85% (HL), 70% (LH), or 50% (LL) as above and calculate the

RS

ratio using V value at 100% as reference.

RS

V

(*)

ref

RS

: V

=

((*) V : when torque data = 100%)

RS

ref (GAIN)

Setup data

H

L

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

L

H

L

STROBE

32

2005-04-04

TB62202AFG

7. ∆I

, ∆I

out1

(A/B unit only. C/D unit conforms to A/B unit.)

out2

V

9

ref AB

8

CR

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

27 V

A 32

DD

Monitors

current

waveform.

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

No reset at testing

V

DD

SGND

RESET = 5 [V]

Ccp A

7

P-GND

Ccp 1

: PGND

: SGND (V

)

SS

With L load, perform chopping in Mixed Decay mode. Monitor the output current waveform and measure the

various output currents at constant current operation.

Setup data

Set to100%

10 11 12 13 14 15

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

L

H

L

H

L

STROBE

MDT

Output current

value (set

current value)

Current

0%

Charge

100% 0%

Fast

waveform

Slow

Measurement of

peak current

Fast

Charge

33

2005-04-04

TB62202AFG

8. I (when measuring phase A) (A/B unit only. C/D unit conforms to A/B unit)

RS

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

A

27 V

A 32

DD

A

B

35

2

31 STROBE AB

30 CLK AB

5

29 DATA AB

R

3

1

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

RESET = L

V

DD

SGND

Ccp A

7

P-GND

Ccp 1

: PGND

: SGND (V

)

SS

With L input to RESET , connect V and R to the power supply, and measure the current input to the R

M

RS

S

pin. (Either drop all the input pins to GND level or input all Low data to the DATA pin, then perform

measurement. At that time, leave all other output pins open.)

Setup data

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

34

2005-04-04

TB62202AFG

9. R

_,R

when measuring output A (A/B unit only. C/D unit conforms to A/B

ON (D-S) ON (S-D)

unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

Curve tracer

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

V

M B

Curve tracer

SGND

V

SS

)

(F

IN

28 RESET

Ccp C 13

Ccp B 12

Ccp 2

Ccp 1

No reset at testing

RESET = 5 [V]

Ccp A

7

P-GND

SGND

: PGND

: SGND (V

)

SS

Input the current setting data (HHHH signal) to the DATA pin and measure the voltage between V and OUT

M

when I

= 1000 mA or the voltage between OUT and GND. Then, change the phase and repeat measurement.

out

At that time, leave the output pins which are not measured open.

Setup data (Vary the phase data during testing.)

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

35

2005-04-04

TB62202AFG

10. V , I (A/B unit only. C/D unit conforms to A/B unit.)

ref ref

*: When measuring I

,

ref

Oscilloscope

fix V = 3 V and

ref

measure.

Monitor

A

V

9

ref AB

8

CR AB

Vary V

= 2 to V

ref

I

(*)

ref

SGND

− 1.0 V

DD

V

36

34

M A

SGND

R

RS A

27 V

A 32

DD

A

B

35

2

31 STROBE AB

30 CLK AB

5

29 DATA AB

R

3

1

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

No reset at testing

V

DD

SGND

RESET = 5 [V]

Ccp A

7

P-GND

Ccp 1

: PGND

: SGND (V

)

SS

V

ref

: Vary V = 2 to V

− 1 V and confirm that output is on.

ref

DD

I

ref

:

When V = 24 V and V

= 5 V, apply the specified voltage of 3 V to the V and monitor the current

DD ref

M

flow value.

36

2005-04-04

TB62202AFG

11. T TSD, ∆T TSD (Measure in an environment such as an constant temperature chamber where

j

the temperature for the IC can be freely changed) (A/B unit only. C/D unit conforms to A/B

unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

Curve tracer

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

V

M B

Curve tracer

SGND

V

SS

)

(F

IN

28 RESET

Ccp C 13

Ccp B 12

Ccp 2

Ccp 1

No reset at testing

RESET = 5 [V]

Ccp A

7

P-GND

SGND

: PGND

: SGND (V

)

SS

T TSD:

j

Increase the ambient temperature. Measure the temperature when output stops.

∆T TSD: Gradually lower the temperature from the level when the TSD circuit was operating (output off). At

j

that time, control the RESET input thus : H → L → H → L. Output will begin at a certain

temperature level.

∆T TSD is the difference between the temperature at which output begins and the temperature at

j

which TSD is triggered.

Setup data

H

L

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

L

H

L

STROBE

37

2005-04-04

TB62202AFG

12. V

(A/B unit only. C/D unit conforms to A/B unit.)

DDR

Oscilloscope

V

9

ref AB

8

CR AB

SGND

V

DD

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

V

M

No reset at testing

RESET = 5 [V]

Ccp A

7

P-GND

V

Ccp 1

DD

SGND

: PGND

Vary from 0 V

: SGND (V

)

SS

Monitor the output pins. Increase the V

voltage from 0. Measure the V

value when output starts.

DD

Next, decrease the V

voltage and measure the V

value when output stops.

DD

Setup data

H

DATA

L

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

CLK

L

H

STROBE

L

38

2005-04-04

TB62202AFG

13. V

(A/B unit only. C/D unit conforms to A/B unit.)

MR

Oscilloscope

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

Vary from 0 V

No reset at testing

RESET = 5 [V]

Ccp A

7

P-GND

Ccp 1

V

DD

SGND

: PGND

: SGND (V

)

SS

With the CLK signal and DATA (all High) input, increase the V voltage from 0.

M

Measure the V value when output starts.

M

Next, decrease the V voltage and measure the V value when output stops.

M

Setup data

H

DATA

L

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

CLK

L

H

STROBE

L

39

2005-04-04

TB62202AFG

14. Overcurrent protector circuit (ISD) (To measure output A : )

(A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

Curve tracer

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

V

M B

Curve tracer

SGND

V

SS

)

(F

IN

28 RESET

Ccp C 13

Ccp B 12

Ccp 2

Ccp 1

At measuring, non-reset

RESET = 5 [V]

Ccp A

7

P-GND

SGND

: PGND

: SGND (V

)

SS

Test method: To monitor operating current of the overcurrent protector circuit when output A is short-circuited

to the power supply

Input the current setting data (HHHH signal) to the DATA pin. If short-circuited to the supply, measure the

lower output transistors. If short-circuited to ground, measure the upper output transistors (see how to measure

R ).

ON

When measuring R , increase the current flow. There is a current value at which output is switched off and

ON

R

ON

cannot be measured. This value is the set current value for the overcurrent protector circuit.

Make sure to leave open the output pins not being measured.

Note that if the temperature changes, the value may fluctuate. Try to avoid applying power to the IC by

one-shot measuring.

Setup data (Example : The phase signal must be changed depending on the pin.)

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

40

2005-04-04

TB62202AFG

15. Current vector (A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

27 V

A 32

DD

Monitor

current

waveform

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

At measuring, non-reset

V

DD

SGND

RESET = 5 [V]

Ccp A

7

P-GND

Ccp 1

: PGND

: SGND (V

)

SS

Perform chopping in Mixed Decay mode with load L. Monitor the output current waveform and measure the output

current at constant current operation. At this time, vary the 4-bit data for current setting and measure the

current values. Using the set output current as 100%, calculate the output current ratio.

100%

Output current

(example)

71%

100%

0%

41

2005-04-04

TB62202AFG

16. f

t

, t

_,t

, t

, t_{STROBE (H)}, t

(A/B unit only. C/D unit conforms to A/B unit.)

,

CLK w (CLK) wp (CLK) wn (CLK) STROBE

STOBE (L)

, t

suSIN-CLK suST-CLK hSIN-CLK hCLK-ST

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

No reset at testing

RESET = 5 [V]

Ccp A

7

P-GND

V

Ccp 1

DD

SGND

: PGND

: SGND (V

)

SS

Input any data at f

(max), perform chopping, and monitor the output waveform.

CLK

For the measuring points, see the timing chart below.

Setup data

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

Measuring points

t

w (CLK)

CLK

50%

t

hCLK-ST

suST-CLK

50%

t

wn (CLK) wp (CLK)

STROBE

t

STROBE (H)

STROBE (L)

t

STROBE

t

hSIN-CLK

t

suSIN-CLK

DATA15

DATA

50%

DATA0

42

2005-04-04

TB62202AFG

17. OSC-fast delay, OSC-charge delay (A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

No reset at testing

V

DD

SGND

RESET = 5 [V]

Ccp A

7

P-GND

Ccp 1

: PGND

: SGND (V

)

SS

Fix the output current value in Mixed Decay mode and turn the output on. Measure the time until the output

switches from the CR pin waveform and the output voltage waveform.

Setup data

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

Top

CR

Bottom

Osc-fast delay

Osc-charge delay

50%

V

out A

50%

(Mode)

Charge

Slow

Fast

Charge

43

2005-04-04

TB62202AFG

18. t

, t

, t , t (A/B unit only. C/D unit conforms to A/B unit.)

pHL (ST) pLH (ST)

r

f

Monitor

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

R

L

= 5.7 Ω

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

No reset at testing

V

DD

RESET = 5 [V]

Ccp A

7

P-GND

SGND

Ccp 1

: PGND

: SGND (V

)

SS

Setup data

H

DATA

L

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

CLK

L

H

STROBE

L

Switch PHASE every 130 µs and measure the output pin voltage and the STROBE signal.

[Oscilloscope waveform (example)]

130 µs

50%

STROBE

t

pHL (ST)

OUTPUT

50%

Voltage A

t

pLH (ST)

OUTPUT

Voltage A

90%

50%

90%

10%

t

f

r

44

2005-04-04

TB62202AFG

19. t

(A/B unit only. C/D unit conforms to A/B unit.)

BRANK

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

No reset at testing

RESET = 5 [V]

Ccp A

7

P-GND

SGND

Ccp 1

: PGND

: SGND (V

)

SS

t

is the dead time band for avoiding malfunction caused by noise. Apply sufficient differential voltage

BRANK

(when V = 3 V, 0.6 V or higher) to V -R and apply duty. When the pulse width reaches a certain value,

ref

M

S

triggering feedback and changing the output. Check the value.

Measure the pulse width

where output changes.

V

M

R

S

pin voltage

H

Apply pulse to the R pin so that the

S

R

S

pin = V voltage − 1.0 V.

M

Output operation

L

Setup data

H

DATA

L

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

CLK

L

H

STROBE

L

45

2005-04-04

TB62202AFG

20. f

(f

(min), f

(max)) (A/B unit only. C/D unit conforms to A/B unit.)

chop

chop chop

Oscilloscope

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

27 V

A 32

DD

A

B

35

2

31 STROBE AB

30 CLK AB

5

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

V

DD

Ccp A

7

P-GND

SGND

Ccp 1

: PGND

: SGND (V

)

SS

Change the R

and C

values and measure the frequency on the CR pin using the oscilloscope.

osc

At this time, 1/8 of the frequency of the measured CR waveform is f

.

chop

Oscilloscope waveform (example)

1/8 f

(SYNC) = f

CR

chop

t = 0

t = 1

46

2005-04-04

TB62202AFG

21. t

(A/B unit only. C/D unit conforms to A/B unit.)

ONG

V

9

ref AB

8

CR AB

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

At measuring, change

from reset to non-reset.

V

DD

SGND

Ccp A

7

P-GND

Ccp 1

: PGND

: SGND (V

)

SS

Apply V and V

and change RESET from L to H.

M

DD

Measure the time until the CcpA pin becomes V + V

× 90%.

M

DD

V

+ V

M

DD

V

+ (V

× 90%)

DD

M

V

M

5 V

0 V

RESET

50%

t

ONG

47

2005-04-04

TB62202AFG

22. Mixed decay timing (A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR

SGND

V

36

34

M A

SGND

R

RS A

R

RS A

27 V

A 32

DD

A

B

35

2

5 V

0 V

31 STROBE AB

30 CLK AB

5 V

0 V

5

5 V

0 V

29 DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28 RESET

Ccp C 13

Ccp B 12

At measuring, non-reset

RESET = 5 [V]

V

DD

SGND

6

SETUP

Ccp A 7

P-GND

Ccp 1

: PGND

: SGND (V

)

SS

With V = 24 V, V

= 5 V, RESET = H, change the SETUP pin from L to H and overwrite the MIXED DECAY

M

DD

TIMING TABLE.

Then change the SETUP pin from H to L. With load L, perform chopping and monitor the output current

waveform at that time. Confirm that the switching timing from Slow Decay Mode to Fast Decay Mode within an

fchop cycle is the specified MIXED DECAY TIMING.

(Depending on the load L value and the test environment, chopping may be performed every two cycles or there

may be no Slow Decay Mode. If so, conditions, for example, load condition, may need to be changed.

MDT

Output current value

(set current value)

0%

MDT

100% 0%

MDT

Slow

Fast

Slow

Fast

Charge

Current waveform

48

2005-04-04

TB62202AFG

Waveforms in Various Current Modes (Ideal Waveform)

Normal MIXED DECAY MODE Waveform

NF is the point at which the output current

reaches the set current value.

f

chop

CR CLK

signal

I

out

NF

Set current value

NF

Set current

value

12.5% MIXED

DECAY MODE

RNF

MDT (MIXED DECAY TIMING) point

When NF is after MIXED DECAY Timing

Fast Decay mode after Charge mode.

I

out

Set current value

MDT (MIXED DECAY TIMING) point

NF

Set current

value

RNF

37.5% MIXED

DECAY MODE

STROBE signal input

49

2005-04-04

TB62202AFG

In MIXED DECAY MODE, when the output current > the set current value

f

chop

Set

NF

current

value

CHARGE MODE for one f

chop

cycle after STROBE signal input

Because the set current value > the

output current, no CHARGE MODE in

the next cycle.

RNF

NF

I

out

12.5%

MIXED

DECAY

MODE

RNF

NF

Set current value

RNF

MDT (MIXED DECAY TIMING) point

STROBE signal input

FAST DECAY MODE Waveform

NF is the point at which the output

current reaches the set current value.

f

chop

Set current

value

I

out

FAST DECAY

MODE

Because the set current value > the output current,

FAST DECAY MODE in the next cycle, too

(0% MIXED

DECAY MODE)

Set current value

NF

RNF

Because the set current value > the output current, CHARGE

MODE → NF → FAST DECAY MODE in the next cycle, too

RNF

STROBE signal input

Response delay time

50

2005-04-04

TB62202AFG

STROBE Signal, Internal CR CLK, and output Current Waveform

(When STROBE Signal is input in SLOW DECAY MODE)

f

chop

f

chop

37.5% MIXED DECAY MODE

Set current

value

MDT

I

out

NF

Set current

value

MDT

RNF

Momentarily enters

CHARGE MODE

STROBE signal input

Reset CR-CLK

counter here

When STROBE signal is input, the chopping counter (CR-CLK counter) is forced to reset at the next CR-CLK

timing.

Because of this, compared with a method in which the counter is not reset, response to the input data is faster.

(The delay time, the theoretical value in the logic portion, is expected to be a one-cycle CR waveform: 1.25 µS

@100 kHz CHOPPING.)

When the CR-CLK counter is reset due to STROBE signal input, CHARGE MODE is entered momentarily due to

current comparison.

Note: In FAST DECAY MODE, too, CHARGE MODE is entered momentarily due to current comparison.

51

2005-04-04

TB62202AFG

STROBE Signal, Internal CR CLK, and output Current Waveform

(When STROBE signal is input in CHARGE MODE)

f

chop

f

chop

Set current

value

MDT

37.5% MIXED DECAY MODE

I

out

NF

Set current

value

MDT

RNF

Momentarily enters

CHARGE MODE

STROBE signal input

52

2005-04-04

TB62202AFG

(When STROBE Signal is input in FAST DECAY MODE)

f

chop

f

chop

37.5% MIXED DECAY MODE

NF

Set

current

value

MDT

I

out

NF

Set current value

MDT

RNF

Momentarily enters

CHARGE MODE

STROBE signal input

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2005-04-04

TB62202AFG

(When PHASE Signal is input)

37.5% MIXED DECAY MODE

f

chop

f

chop

Set current

value

I

out

0

RNF

MDT

Set current

value

NF

STROBE signal input

54

2005-04-04

TB62202AFG

(When current point 0 control is included)

37.5% MIXED DECAY MODE

f

chop

f

chop

Set current

value

I

out

(1)

(2)

(1)

0

(2)

(1)

Set current

value

STROBE signal input

Reset CR-CLK

counter here

Reset CR-CLK

counter here

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2005-04-04

TB62202AFG

(When FAST DECAY MODE is included during the sequence)

f

chop

Set current

value

37.5% MIXED DECAY MODE

FAST DECAY MODE

Set current

value

56

2005-04-04

TB62202AFG

(When SLOW DECAY MODE is included during the sequence)

f

chop

Set current

value

SLOW DECAY MODE

37.5% MIXED DECAY MODE

f

chop

Set current

value

In SLOW DECAY MODE, depending on the load,

the set current cannot be accurately traced.

Therefore, do not use SLOW DECAY MODE.

37.5% MIXED DECAY MODE

STROBE

57

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TB62202AFG

Current Modes

+

(MIXED (= SLOW FAST) Decay Mode Effect)

z Sine wave in increasing (Slow Decay Mode (Charge + Slow + Fast) normally used)

Slow

Fast

Set current

value

Charge

Fast

Charge

Slow

Set current

value

Fast

Charge

Fast

Charge

z Sine wave in decreasing (When using MIXED DECAY Mode with large attenuation ratio (MDT%) at attenuation)

Slow

Because current attenuates so quickly, the current

immediately follows the set current value.

Set current

value

Charge

Fast

Charge

Fast

Slow

Set current

value

Fast

Charge

z Sine wave in decreasing (When using MIXED DECAY Mode with small attenuation ratio (MDT%) at attenuation)

Because current attenuates slowly, it takes a

long time for the current to follow the set current

value (or the current does not follow).

Slow

Set current

value

Fast

Charge

Fast

Set current

value

Note: The above charts are schematics. The actual current transient responses are curves.

58

2005-04-04

TB62202AFG

Output Transistor Operating Mode

To V

M

R

RS

R

S

R

R pin

S

U

1

U

2

U

1

U

2

U

1

U

2

(Note)

Load

L

1

L

2

L

1

L

2

L

1

L

2

PGND

Charge mode

(Charges coil power)

Slow mode

(Slightly attenuates coil power)

Fast mode

(Drastically attenuates coil power)

Output Transistor Operation Functions

CLK

U

1

U

2

L

1

L

2

CHARGE

SLOW

ON

OFF

ON

OFF

ON

FAST

ON

OFF

Note: The above table is an example where current flows in the direction of the arrows in the above figures.

When the current flows in the opposite direction of the arrows, see the table below.

CLK

U

1

U

2

L

1

L

2

CHARGE

SLOW

OFF

ON

OFF

ON

OFF

ON

FAST

OFF

ON

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2005-04-04

TB62202AFG

Output Transistor Operating Mode 2

(Sequence of MIXED DECAY MODE)

To V

M

R

RS

R

RS

U

1

U

2

U

1

U

2

U

1

U

2

OUT A

OUT A OUT A

OUT A

L

1

L

2

L

1

L

2

L

1

L

2

PGND

H

OUTPUT

voltage A

50%

L

H

OUTPUT

voltage A

50%

L

Set current

OUPUT

current

L

Charge Mode

Slow Mode

Fast Mode

The constant current is controlled by changing mode from Charge → Slow → Fast.

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TB62202AFG

Current Discharge Path when Current Data = 0000 are input during operation

In Slow Decay Mode, when all output transistors are forced to switch off, coil energy is discharged in the following

MODES :

Note: Parasitic diodes are located on dotted lines. In normal MIXED DECAY MODE, the current does not flow to the

parasitic diodes. However, when signal 0000 is input during operation, the current flows to them.

To V

To V power supply

M

R

RS

R

RS

R

RS

R

S

R

S

R pin

S

U

1

U

2

U

1

U

2

U

1

U

2

OFF

ON

(Note)

Input Current DATA

= 0000

Load

L

1

L

2

L

1

L

2

L

1

L

2

OFF

ON

OFF

PGND

Charge mode

PGND

Slow Decay mode

PGND

Forced OFF mode

As shown in the figure at right, an output transistor has parasitic diodes.

To discharge energy from the coil, each transistor is switched on allowing current to flow in the reverse direction to

that in normal operation. As a result, the parasitic diodes are not used. If all the output transistors are forced to

switch off, the energy of the coil is discharged via the parasitic diodes.

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TB62202AFG

PD-Ta (Package Power Dissipation)

P

– Ta

D

3.5

(2)

(1) R

th (j-a)

IC only (96°C/W)

(2) When mounted on the board

(38°C/W)

Board size(100 × 200 × 1.6 mm)

3.0

2.5

2.0

* R : 8.5°C/W

th (j-c)

1.5

(1)

1.0

0.5

0

25

50

75

100

125

150

Ambient temperature Ta (°C)

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2005-04-04

TB62202AFG

Power Supply Sequence (Recommended)

V

DD (max)

DD (min)

DDR

V

DD

GND

V

M

V

M (min)

MR

V

M

GND

NON-RESET

Internal reset

RESET

H

L

RESET

input

････*

Takes up to t

ONG

until operable.

t

Non-operable area

Note 1: If the V

drops to the level of the V or below while the specified voltage is input to the V pin, the IC is

DDR M

DD

internally reset. This is a protective measure against malfunction. Likewise, if the V drops to the level of the

M

V

MR

or below while regulation voltage is input to the V , the IC is internally reset as a protective measure

DD

against malfunction. To avoid malfunction, when turning on V or V , we recommend you input the

M

DD

RESET signal at the above timing.

It takes time for the output control charge pump circuit to stabilize. Wait up to t

before driving the motors.

time after power on

ONG

Note 2: When the V value is between 3.3 to 5.5 V, the internal reset is released, thus output may be on. In such a

M

case, the charge pump cannot drive stably because of insufficient voltage. We recommend the RESET state

be maintained until V reaches 20 V or more.

M

Note 3: Since V_DD= 0 V and V = voltage within the rating are applied, output is turned off by internal reset. At that

M

time, a current of several mA flows due to the Pass between V and V

M

.

DD

63

2005-04-04

TB62202AFG

Relationship between V and V

M

H

V

H

is the voltage of the CcpA pin. It is the highest voltage in this IC (power supply for driving the upper gate of the

H bridge).

V

– V (& Vcharge up)

H

M

50

40

30

20

10

0

V

voltage

H

M

V

= 5 V

DD

Charge up voltage

Ccp1 = 0.22 µF

Ccp2 = 0.02 µF

V

= V

+ V (CcpA)

DD M

H

Input RESET.

( RESET = 0 V)

Maximum

VMR

Usable area

Recommended operation area

0

5

10

15

20

25

30

35

40

Supply voltage

V

M

(V)

z V charge Up is the voltage to boost V to V . Usually equivalent to V .

DD

M

H

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2005-04-04

TB62202AFG

Operation of Charge Pump Circuit

V

= 24 V

M

R

RS

V

M

V

= 5 V

R

S

DD

27

3/16/21/34

1/18/19/36

V

Ccp A

Ccp B

H

7

i2

i1

Di2

Di1

(2)

12

T

r2

Output

(1)

(2)

Comparator

&

Controller

V

Z

Output

H switch

13

Ccp C

Di3

R

1

T

r1

V

H

= V + V

= charge pump voltage

M

DD

i1 = charge pump current

i2 = gate block power dissipation

z Initial charging

(1) When RESET is released, T is turned ON and T turned OFF. Ccp2 is charged from Ccp2 via Di1

r1

r2

(This is the same as when TSD and ISD are operating and the IC is restored from Reset state.)

(2) T is turned OFF, T is turned ON, and Ccp1 is charged from Ccp2 via Di2.

r1

r2

(3) When the voltage difference between V and V (CcpA pin voltage = charge pump voltage) reaches V or

DD

M

H

higher, operation halts (Steady state : Because the capacitor is naturally discharged, the IC is continually

charging to the capacitor).

z Actual operation

(4) Ccp1 charge is used at fchop switching and the V potential drops.

H

(5) Charges up by (1) and (2) above.

Output switching

Initial charging

Normal state

V

H

V

M

(1)

(4)

(2)

(3)

t

(5)

65

2005-04-04

TB62202AFG

External Capacitors for Charge Pumps

When V

= 5V, fchop = 100 kHz, and L = 10 mH is driven with V = 24 V, I = 1100 mA, the theoretical values

out

DD

M

for Ccp1 and Ccp2 are as shown below:

Ccp 1 – Ccp 2

0.05

0.045

0.04

0.035

0.03

0.025

0.02

0.015

0.01

0.005

0

Usable area

Ccp 1 = (NG)

Ccp 2 = (OK)

Recommended area

Recommended value

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Ccp 1 capacitance (µF)

Combine Ccp1 and Ccp2 as shown in the shaded area in the above graph.

Select values 10: 1 or more for Ccp1: Ccp2.

When making a setting, evaluate properly and set values with a margin.

66

2005-04-04

TB62202AFG

Charge Pump Rise Time

V

+ V

M

DD

V

+ (V

× 90%)

M

DD

V

M

5 V

0 V

50%

RESET

t

ONG

t

: Time taken for capacitor Ccp2 (charging capacitor) to fill up Ccp1 (capacitor used to save charge) to V

+

ONG

M

V

DD

after a reset is released.

The internal IC cannot drive the gates correctly until the voltage of Ccp1 reaches V + V . Be sure to

M

DD

wait for t

or longer before driving the motors.

ONG

Basically, the larger the Ccp1 capacitance, the longer the initial charge-up time but the smaller the

voltage fluctuation.

The smaller the Ccp1 capacitance, the shorter the initial charge-up time but the larger the voltage

fluctuation.

Depending on the combination of capacitors (especially with small capacitance), voltage may not be

sufficiently boosted. Thus, use the capacitors under the capacitor combination conditions (Ccp1 = 0.22 µF,

Ccp2 = 0.01 µF) recommended by Toshiba.

67

2005-04-04

TB62202AFG

Operating Time for Overcurrent Protector Circuit

(ISD non-sensitivity time and ISD operating time)

Output halts (Reset status)

CR oscillation

(basic chopping waveform)

MIN

MAX

MIN

MAX

(Non-sensitivity time)

ISD BLANK time

ISD operating time

Point where overcurrent flows to output transistors (overcurrent status start)

A non-sensitivity time is set for the overcurrent protector circuit to avoid misdetection of overcurrent due to spike

current at irr or switching.

The non-sensitivity time synchronizes with the frequency of the CR for setting the chopping frequency. The

non-sensitivity time is set as follows :

Non-sensitivity time = 4 × CR cycle

The time required for the ISD to actually operate after the non-sensitivity time is as follows :

Minimum: 5 × CR cycle

Maximum: 8 × CR cycle

Therefore, from the time overcurrent flows to the output transistors to the time output halts is as follows.

Note that ideally, the operating time is the operating time when overcurrent flows. Depending on the output control

mode timing, the overcurrent protector circuit may not be triggered.

Therefore, to ensure safe operation, add a fuse to the V power supply for protection.

M

The fuse capacity would vary according to the use conditions. However, select a fuse whose capacity avoids any

operating problems and does not exceed the power dissipation for the IC.

68

2005-04-04

TB62202AFG

Application Operation Input Data (Example: 2-Phase Excitation Mode)

TORQUE TORQUE DECAY DECAY

DECAY

A

0

PHASE BDECAY A

PHASE A

B

A

3

0

1

2

3

0

1

2

0

1

B

0

1

Bit

1

0

1

2

3

4

5

6

7

8

1

0

1

9

1

10

0

11 12 13 14

15

1

0

1

2

0

1

3

0

4

0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 9, Functions.

We recommend Mixed Decay mode (37.5%) as Decay mode. Set torque to 100%.

Output current waveform of 2-phase excitation sine wave

(%)

100

Phase B

0

Phase A

−100

Note: We recommended 2-phase excitation drive in 37.5% Mixed Decay mode.

Please refer to the caution of 2-phase excitation mode on next page.

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TB62202AFG

Application Operation Input Data (Example: 1-2 Phase Excitation Mode Typ.A)

TORQUE TORQUE DECAY DECAY

DECAY DECAY

PHASE B

PHASE A

B

A

3

0

1

2

3

0

1

2

0

1

B

A

1

0

1

0

Bit

1

0

1

2

3

4

5

6

7

8

1

0

1

9

10

0

11 12 13 14

15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

0

1

3

0

1

4

0

5

0

6

0

7

0

8

0

1

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 10, Functions.

We recommend Mixed Decay Mode (37.5%) as Decay Mode.

Set torque to 100%.

When using this excitation mode, high efficiency can be achieved by setting the phase data to 10% (−10%). Set

current values in the order +100% → −10% → −100% → +10%.

Output Current Waveform of 1-2 Phase Excitation Sine Wave (Typ. A)

(%)

100

Phase A

10

0

−10

−100

(%)

100

Phase B

10

0

−10

−100

70

2005-04-04

TB62202AFG

Points for Control that Includes Current of 0%

In modes other than 2-Phase Excitation mode (from 1-2 Phase Excitation mode to 4W1-2 Phase Excitation mode),

when the current is controlled to 0%, the TB62201F’s output transistors are all turned off.

At the time, the coil's energy returns to the power supply through the parasitic diodes. If the same current is

applied several times and is within the rated current, then : the power consumed by the on-resistance when current

flows to the output MOS will be less than the power consumed when current is applied to the parasitic diodes.

Therefore, when controlling the current, rather than setting 0%, set the current to the next step beyond 0% (the

minimum step in the reverse direction) for better power dissipation results.

However, if the 0% (actually 10%) current cycle is long, the power dissipation may be greater than in Off mode

because of the need for constant-current control.

Therefore, Toshiba recommend setting the current according to the actual operating pattern. (1-2 Phase Excitation

mode is the most effective.)

Flyback diode mode

Charge

To V power supply

M

[%]

100

R

RS

The coil’s energy returns through

the parasitic diodes.

Constant-

current

control

R pin

S

Because V < V , the power

DS

dissipation is large.

F

U

2

U

1

Output off

period

OFF

10

0

−10

Load

L

1

L

2

OFF

Constant-

current

control

Forced Off mode

−100

Diode parasite

PGND

Non-flyback diode mode

The coil’s energy returns through

the MOS, which is turned on.

Then the coil is charged to a level

of 10%.

Charge

[%]

To V

M

R

RS

100

Constant-

current

control

R

S

The power dissipation is smaller

than when the energy is returned

via the parasitic diode.

U

2

1

OFF

ON

10

0

−10

(However, the longer the 10%

rated current control time, the

longer the period of current

dissipation.)

Constant-

current

control

Load

ON

OFF

L

1

L

2

Constant-

current

control

Charge mode

PGND

−100

Charge

Specifies a level of 10%,

either side of 0.

71

2005-04-04

TB62202AFG

Application Operation Input Data (Example: 1-2 Phase Excitation mode Typ.B)

TORQUE TORQUE

DECAY

B

PHASE

B

DECAY

A

PHASE

A

MDMB

B

MDM A

A

3

0

1

2

3

0

1

2

0

1

Bit

1

0

1

2

1

3

0

4

5

6

7

8

1

0

9

1

10

0

11 12 13 14

15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

0

1

3

0

1

4

0

1

5

0

6

0

7

0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 10, Functions.

We recommend Mixed Decay Mode (37.5%) as Decay Mode.

Set torque to 100%. Same as 1-2 phase excitation (typ. A) in the previous section, power dissipation can be reduced

by changing 0% level to 10% or −10%.

Output Current Waveform of 1-2 Phase Excitation Sine Wave (Typ. B)

(%)

100

71

Phase A

0

Phase B

−71

−100

72

2005-04-04

TB62202AFG

Application Operation Input Data (Example: 4-bit micro steps)

(4-bit micro steps = W1-2 phase excitation drive)

TORQUE TORQUE DECAY DECAY

PHASE DECAY DECAY

PHASE

B

A

3

0

1

2

3

0

1

2

0

1

B

A

1

A

0

1

0

Bit

1

0

1

2

3

4

5

6

7

8

9

10

0

1

0

11 12 13 14

15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 9, Functions.

We recommend Slow Decay Mode in the ascending direction of the sine wave ; Mixed Decay Mode (37.5%) in the

descending direction. Set torque to 100%.

73

2005-04-04

TB62202AFG

Output Current Waveform of Pseudo Sine Wave (4-bit micro steps)

(%)

100

92

71

Phase A

38

0

Phase B

−38

−71

−92

−100

STEP

5 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.

For input Current DATA at that time, see section on Current X in the list of the Functions.

Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave

rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.

74

2005-04-04

TB62202AFG

Application Operation Input Data (Example: 3-bit micro steps)

(3-bit micro steps = 2W1-2 phase excitation drive)

TORQUE TORQUE DECAY DECAY

PHASE DECAY DECAY

PHASE

B

A

3

0

1

2

3

0

1

2

0

1

B

8

1

A

1

A

15

1

0

1

0

Bit

1

2

3

4

5

6

7

9

10

0

11 12 13 14

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

1

0

1

0

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

0

1

0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 10, Functions.

We recommend Slow Decay Mode in the ascending direction of the sine wave; Mixed Decay Mode (37.5%) in the

descending direction. Set torque to 100%.

75

2005-04-04

TB62202AFG

Output Current Waveform of Pseudo Sine Wave (3-bit micro steps)

[%]

100

98

92

83

71

Phase A

56

38

20

0

−20

Phase B

−38

−56

−71

−83

−92

−98

−100

STEP

9 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.

For input Current DATA at that time, see section on Current X in the list of the Functions.

Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave

rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.

76

2005-04-04

TB62202AFG

Application Operation Input Data (Example: 4-bit micro steps)

TORQUE TORQUE DECAY DECAY

PHASE DECAY DECAY

PHASE

B

A

3

0

1

2

3

0

1

2

0

1

B

8

1

A

1

A

15

1

0

1

0

Bit

1

2

3

4

5

6

7

9

10

0

11 12 13 14

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

1

0

1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

0

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TB62202AFG

TORQUE TORQUE DECAY DECAY

PHASE DECAY DECAY

PHASE

B

A

3

0

1

2

3

0

1

2

0

1

B

8

0

A

1

A

15

0

1

0

Bit

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

2

3

4

5

6

7

9

10

1

11 12 13 14

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 10, Functions. In the above input data example, Decay mode has a Mixed Decay

mode (37.5%) setting for both the rising and falling directions of the sine wave, and a torque setting of 100%.

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TB62202AFG

4W1-2 Output Current Waveform of Pseudo Sine Wave (4-bit micro steps)

[%]

100

98

96

92

88

83

77

71

63

Phase A

56

47

38

29

20

10

0

−10

Phase B

−20

−29

−38

−47

−56

−63

−71

−77

−83

−88

−92

−96

−98

−100

STEP

17 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.

For input Current DATA at that time, see section on Current X in the list of the Functions.

Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave

rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.

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TB62202AFG

Output Current Vector Line

4W-1-2 phase excitation (4-bit micro steps)

X = 16

X = 15

100

98

X = 14

X = 13

96

X = 12

92

88

X = 11

X = 10

83

77

X = 9

71

63

X = 8

X = 7

X = 6

56

47

X = 5

X = 4

38

X = 3

29

20

X = 2

θ

X

X = 1

10

θ

X

X = 0

98 100

0

10

20

29

38

47

56

63

71

77

83

88

92

96

I

(%)

B

For data to be input, see the function of Current AX (BX) in the list of Functions (10 page).

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TB62202AFG

Output Current Vector Line 2 (Each mode: except 4W1-2 phase)

1-2 phase excitation (Typ. A)

1-2 phase excitation (Typ. B)

100

0

100

0

71

100

I

(%)

I

(%)

B

W 1-2 phase excitation

2W 1-2 phase excitation

100

92

100

98

92

83

71

38

71

56

38

20

0

38

71

92 100

0

20

38

56

71

83

92 100

98

I

(%)

I

(%)

B

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TB62202AFG

Recommended Application Circuit

The values for the devices are all recommended values. For values under each input condition, see the

above-mentioned recommended operating conditions.

(Example : f_chop= 96 kHz, CR : I_out= 0.6 (A), LF : I_out= 0.6 (A) )

R

osc

= 2.0 kΩ

V

ref AB

CR

V

2.63 V

SGND

ref AB

C

osc

= 1000 pF

1 µF

SGND

V

M A

V

DD

R

RS A

5 V

0 V

R

RS A

0.75 Ω

STEPUP

A

5 V

0 V

CLK AB

A

B

5 V

0 V

STEPPING

MOTOR 1

DATA AB

M

(CR: 6.8 mH/5.7 Ω)

5 V

0 V

STROBE AB

R

RS B

R

RS B

0.75 Ω

V

M B

P-GND

V

SS

(F

IN

)

5 V

0 V

SGND

CLK CD

V

M C

5 V

0 V

DATA CD

STROBE CD

RESET

R

RS C

C

R

RS C

0.75 Ω

5 V

0 V

C

D

5 V

0 V

STEPPING

MOTOR 2

M

D

(LF: 6.8 mH/5.7 Ω)

R

RS D

R

RS D

0.75 Ω

V

M D

V

ref CD

Ccp A Ccp B

Ccp C

5 V

SGND

100 µF

4.13 V

1 µF

100 µF

24 V

SGND

Ccp 2

0.015 µF

Cop 1

0.22 µF

SGND

Note: We recommend the user add bypass capacitors as required.

Make sure as much as possible that GND wiring has only one contact point.

Also, make sure that the VM pins are connected.

For the data to be input, see the section on the recommended input data.

Because there may be shorts between outputs, shorts to supply, or shorts to ground, be careful when designing

output lines, V (V ) lines, and GND lines.

DD

M

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2005-04-04

TB62202AFG

Package Dimensions

HSOP36-P-450-0.65

Unit: mm

Weight: 0.79 g (typ.)

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2005-04-04

TB62202AFG

About solderability, following conditions were confirmed

• Solderability

(1) Use of Sn-63Pb solder Bath

· solder bath temperature = 230°C

· dipping time = 5 seconds

· the number of times = once

· use of R-type flux

(2) Use of Sn-3.0Ag-0.5Cu solder Bath

· solder bath temperature = 245°C

· dipping time = 5 seconds

· the number of times = once

· use of R-type flux

RESTRICTIONS ON PRODUCT USE

030619EBA

• The information contained herein is subject to change without notice.

• The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of

TOSHIBA or others.

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical

stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of

safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of

such TOSHIBA products could cause loss of human life, bodily injury or damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as

set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and

conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability

Handbook” etc..

• The TOSHIBA products listed in this document are intended for usage in general electronics applications

(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,

etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires

extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or

bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or

spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,

medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this

document shall be made at the customer’s own risk.

• The products described in this document are subject to the foreign exchange and foreign trade laws.

• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced

and sold, under any law and regulations.

84

2005-04-04


型号：	TB62202AFG
厂家：	TOSHIBA
描述：	Dual-Stepping Motor Driver IC for OA Equipment Using PWM Chopper Type 双步进电机驱动器IC，用于办公自动化设备使用PWM斩波型驱动器电机
文件：	总84页 (文件大小：1248K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TB62202AFG [TOSHIBA]

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