TC51WHM716AXBN70 [TOSHIBA]
IC 8M X 16 PSEUDO STATIC RAM, 70 ns, PBGA69, 9 X 12 MM, 0.80 MM PITCH, PLASTIC, FBGA-69, Static RAM;
| 型号： | TC51WHM716AXBN70 |
| 厂家： | 
TOSHIBA |
| 描述： | IC 8M X 16 PSEUDO STATIC RAM, 70 ns, PBGA69, 9 X 12 MM, 0.80 MM PITCH, PLASTIC, FBGA-69, Static RAM 内存集成电路 |
| 文件： | 总13页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC51WHM716AXBN70
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
8,388,608-WORD BY 16-BIT CMOS PSEUDO STATIC RAM
DESCRIPTION
The TC51WHM716AXBN is a 134,217,728-bit pseudo static random access memory(PSRAM) organized as
8,388,608 words by 16 bits. Using Toshiba’s CMOS technology and advanced circuit techniques, it provides high
density, high speed and low power. The device operates single power supply. The device also features SRAM-like
W/R timing whereby the device is controlled by CE1 , OE , and WE on asynchronous. The device has the page
access operation. Page size is 8 words. The device also supports deep power-down mode, realizing low-power
standby.
•
Access Times:
FEATURES
•
•
•
•
•
Organized as 8,388,608 words by 16 bits
Single power supply voltage of 2.6 to 3.3 V
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
Page read/write operation by 8 words
Logic compatible with SRAM R/W ( WE ) pin
Standby current
TC51WHM716AXBN
Access Time
70 ns
70 ns
25 ns
25 ns
CE1 Access Time
OE Access Time
Page Access Time
Package:
•
•
Standby
Deep power-down standby
200 µA
3 µA
P-FBGA69-0912-0.80B3 (Weight:0.25 g typ.)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
1
2
3
4
5
6
7
8
9
10
A0 to A22
A0 to A2
Address Inputs
Page Address Inputs
I/O1 to I/O16 Data Inputs/Outputs
A
B
C
D
E
F
NC
NC
NC
NC
NC
CE1
CE2
Chip Enable Input
Chip select Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power
A7
A6
A5
A4
/LB
/UB
A18
A17
NC
NC
NC
/WE
CE2
A20
A8
A19
A9
A11
A12
A13
A14
NC
WE
A3
A2
A1
A0
NC
A15
A21
A22
A16
OE
LB , UB
NC
NC
A10
I/O7
NC
NC
V
DD
G
H
J
GND I/O2
/OE I/O10 I/O4
NC
I/O3 I/O12 NC
GND
NC
Ground
I/O5 I/O14 I/O16 NC
No Connection
/CE1 I/O1 I/O11
I/O9
V
DD
I/O13 I/O8 GND
I/O6 I/O15
K
L
NC
NC
NC
NC
M
(FBGA48)
2004-07-06 1/13
TC51WHM716AXBN70
Mode Register Definition
Mode configuration register setting
tRC
tRC
tWC
tWC
tWC
tWC
Address
All “1”
All “1”
All “1”
All “1”
All “1”
Add. Code
/CE1
/OE
/WE
tAS
tAS
tAS
tAS
tAS
tAS
tMH
tMH
tMH
tMH
tMH
Fix-L
/LB,/UB
I/O
Qa
Da
Da
X
X
Q(Invalid)
tDS tDH
tDS tDH
In case that holding the data for All”1” address is not needed, input data “Da” for 2nd & 3rd cycle can be randomly.
(Address Code)
A22 to A21
All “1”
A20
A19
A18 to A0
All “1”
Partial Refresh Area Set
A20
A19
Partial Refresh Area
0
0
1
1
0
1
0
1
32M(1/4) : 000000h to 1FFFFFh
16M(1/8) : 000000h to 0FFFFFh
8M(1/16) : 000000h to 07FFFFh
Deep Stand-by
Bold letters : Default setting
OPERATION MODE
MODE
CE1
CE2
OE
WE
LB
UB
Add
I/O1 to I/O8
I/O9 to I/O16
POWER
Read(Word)
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
D
D
D
I
I
I
I
I
I
I
OUT
OUT
OUT
DDO
DDO
DDO
DDO
DDO
DDO
DDO
Read(Lower Byte)
Read(Upper Byte)
Write(Word)
High-Z
L
H
L
High-Z
D
OUT
X
X
X
H
X
X
L
D
D
D
IN
IN
Write(Lower Byte)
Write(Upper Byte)
Outputs Disabled
Standby
L
L
H
L
Invalid
IN
L
H
X
X
X
Invalid
High-Z
High-Z
High-Z
D
IN
H
X
X
X
X
X
High-Z
High-Z
High-Z
I
DDS
Deep Power-down Standby
I
DDSD
Notes: L = Low-level Input(V ), H = High-level Input(V ), X = V or V , High-Z = High-impedance
IL IH IH IL
2004-07-06 2/13
TC51WHM716AXBN70
ABSOLUTE MAXIMUM RATINGS (See Note 1)
SYMBOL
RATING
VALUE
UNIT
V
V
V
Power Supply Voltage
Input Voltage
−1.0 to 3.9
−1.0 to 3.9
−1.0 to 3.9
−25 to 85
−55 to 150
260
V
V
DD
IN
Output Voltage
V
OUT
opr.
T
T
T
Operating Temperature
Storage Temperature
°C
°C
°C
W
mA
strg.
solder
Soldering Temperature (10 s)
Power Dissipation
P
0.6
D
I
Short Circuit Output Current
50
OUT
DC RECOMMENDED OPERATING CONDITIONS (Ta = −25°C to 85°C)
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP.
MAX
3.3
UNIT
V
V
V
V
2.6
2.0
2.75
⎯
DD
Input High Voltage
Input Low Voltage
V
+ 0.3*
IH
IL
DD
−0.3*
⎯
0.4
* : V (Max) V +1.0 V with 10 ns pulse width
IH DD
V (Min) -1.0 V with 10 ns pulse width
IL
DC CHARACTERISTICS (Ta = −25°C to 85°C, V = 2.6 to 3.3 V) (See Note 3 to 4)
DD
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP. MAX
UNIT
I
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
V
= 0 V to V
DD
−1.0
−1.0
2.0
⎯
⎯
⎯
⎯
+1.0
+1.0
⎯
µA
µA
V
IL
IN
I
Output disable, V
= 0 V to V
OUT DD
LO
V
V
I
I
= − 0.5 mA
= 1.0 mA
OH
OL
OH
⎯
0.4
V
OL
CE1 = V
IL
CE2 = V , I
I
Operating Current
t
= min
⎯
⎯
55
mA
DDO1
DDO2
RC
Read
Write
= 0 mA
IH OUT
⎯
⎯
⎯
⎯
⎯
⎯
25
40
mA
mA
CE1 = V , CE2 = V , t = min
Page add. cycling, I
IL
IH PC
= 0 mA
I
Page Access Operating Current
OUT
Ta=−25～85℃
Ta=40℃
200
CE1 = V
− 0.2 V,
DD
− 0.2 V
I
Standby Current(MOS)
µA
DDS
CE2 = V
DD
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
125
⎯
⎯
160
150
145
⎯
1/4 area
Ta=
1/8 area
1/16 area
1/4 area
1/8 area
1/16 area
⎯
−25～85℃
⎯
CE1 = V
DD
CE2 = 0.2 V
− 0.2 V
Partial Standby Current(MOS)
µA
µA
I
I
DDSP
80
70
65
⎯
Ta=40℃
⎯
⎯
Deep Power-down Standby Current CE2 = 0.2 V
3
DDSD
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
TEST CONDITION
= GND
MAX
UNIT
C
C
Input Capacitance
Output Capacitance
V
IN
10
10
pF
pF
IN
V
OUT
= GND
OUT
Note: This parameter is sampled periodically and is not 100% tested.
2004-07-06 3/13
TC51WHM716AXBN70
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = −25°C to 85°C, V = 2.6 to 3.3 V) (See Note 5 to 11)
DD
SYMBOL
PARAMETER
Read Cycle Time
MIN
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
70
⎯
⎯
⎯
⎯
10
0
10000
70
70
25
25
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ms
ns
µs
ns
RC
Address Access Time
ACC
CO
Chip Enable ( CE1 ) Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
OE
BA
COE
OEE
BE
⎯
0
⎯
⎯
⎯
⎯
5
20
20
20
⎯
OD
ODO
BD
OH
Page Mode Time
70
25
⎯
5
10000
⎯
PM
Page Mode Read Cycle Time
Page Mode Address Access Time
Page Mode Output Data Hold Time
Write Cycle Time
PRC
AA
25
⎯
AOH
WC
70
50
70
60
60
0
10000
⎯
Write Pulse Width
WP
Chip Enable to End of Write
Data Byte Control to End of Write
Address Valid to End of Write
Address Set-up Time
⎯
CW
⎯
BW
⎯
AW
⎯
AS
Write Recovery Time
0
⎯
WR
Write Enable High Pulse Width
Chip Enable High Pulse Width
Data Byte Control High Pulse Width
WE Low to Output High-Z
WE High to Output Active
Data Set-up Time
10
10
10
⎯
0
⎯
WEHA
CEHA
BEHA
ODW
OEW
DS
⎯
⎯
15
⎯
30
0
⎯
Data Hold Time
⎯
DH
Page Mode Write Bigin Cycle Time
Page Mode Write Cycle Time
Page Mode Write End Cycle Time
Page Mode Write Data Set-up Time
Page Mode Write Pulse Width(/WE toggle)
Page Mode Write High Pulse Width
Page Mode Write Recovery Time
CE2 Set-up Time
70
30
30
15
15
10
10
0
⎯
PWC1
PWC2
PWC3
DSP
WPPM
WHP
WRP
CS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
CE2 Hold Time from Deep Power Down
CE2 Hold Time from Partial Refresh
CE2 Pulse Width
300
5
⎯
CH
⎯
CHR
DPD
CHC
CHP
MH
10
0
⎯
CE2 Hold from CE1
⎯
CE2 Hold from Power On
30
10
⎯
Mode Resister Set Hold Time
⎯
2004-07-06 4/13
TC51WHM716AXBN70
AC TEST CONDITIONS
PARAMETER
CONDITION
Output load
30 pF + 1 TTL Gate
Input pulse level
Timing measurements
Reference level
V
− 0.2 V, 0.2 V
DD
V
× 0.5
× 0.5
DD
V
DD
t , t
3 ns
R
F
2004-07-06 5/13
TC51WHM716AXBN70
TIMING DIAGRAMS
READ CYCLE
t
RC
Address
A0 to A22
t
t
ACC
OH
t
CO
CE1
Fix-H
CE2
OE
t
t
OD
OE
t
ODO
WE
t
BA
UB , LB
t
BE
t
BD
t
OEE
D
OUT
Hi-Z
VALID DATA OUT
Hi-Z
t
COE
I/O1 to I/O16
INDETERMINATE
PAGE READ CYCLE (8 words access)
t
PM
t
t
t
t
PRC
PRC
PRC
RC
Address
A0 to A2
Address
A3 to A22
CE1
Fix-H
CE2
OE
WE
UB , LB
t
t
OD
OE
t
BD
t
BA
t
t
t
AOH
AOH
AOH
t
t
OEE
OH
t
BE
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O16
t
COE
t
t
t
t
t
ODO
CO
AA
AA
AA
* Maximum 8 words
t
ACC
2004-07-06 6/13
TC51WHM716AXBN70
(See Note 8)
WE
WRITE CYCLE 1 (
CONTROLLED)
t
WC
Address
A0 to A22
t
t
AW
WEHA
t
AS
t
WP
t
WR
WE
t
t
CW
WR
CE1
t
t
CH or CHR
CE2
t
t
BW
WR
UB , LB
t
t
OEW
ODW
D
OUT
(See Note 10)
Hi-Z
(See Note 11)
(See Note 9)
I/O1 to I/O16
t
t
DH
DS
D
IN
(See Note 9)
VALID DATA IN
I/O1 to I/O16
(See Note 8)
CE
WRITE CYCLE 2 (
CONTROLLED)
t
WC
Address
A0 to A22
t
AW
t
t
WP
t
AS
WR
WE
t
CEHA
t
t
CW
WR
CE1
t
t
CH or CHR
CE2
t
t
BW
WR
UB , LB
t
t
ODW
BE
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O16
t
COE
t
t
DH
DS
D
IN
(See Note 9)
VALID DATA IN
I/O1 to I/O16
2004-07-06 7/13
TC51WHM716AXBN70
(See Note 8)
UB LB
CONTROLLED)
WRITE CYCLE 3 (
,
t
WC
Address
A0 to A22
t
AW
t
t
t
AS
WP
WR
WE
t
t
CW
WR
CE1
t
t
CH or CHR
t
CE2
BEHA
t
t
BW
WR
UB , LB
t
t
ODW
BE
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O16
t
COE
t
t
DH
DS
D
IN
(See Note 9)
VALID DATA IN
I/O1 to I/O16
PAGE WRITE CYCLE (8 words access )
t
PM
t
t
t
t
PWC3
PWC1
PWC2
PWC2
Address
A0 to A2
t
t
t
AS
AS
AS
t
t
t
WR
WR
WR
Address
A3 to A22
t
WRP
CE1
Fix-H
t
t
t
t t t
WPPM WHP WPPM
WHP
WPPM WHP
CE2
WE
UB , LB
t
BW
t
WP
t
t
t
t
DSP
DH
t
DSP
t
t
t
DSP DH
DH
DSP DH
D
OUT
(See Note 9)
D
IN
D
IN
D
IN
D
IN
I/O1 to I/O16
t
CW
t
AW
* Maximum 8 words
2004-07-06 8/13
TC51WHM716AXBN70
Deep Power-down Timing
CE1
t
DPD
CE2
t
t
CH
CS
In case of exiting from deep power-down standby, mode resister returns to default state.
Partial Refresh Timing
CE1
CE2
t
t
CHR
CS
Power-on Timing
V
min
DD
V
DD
CE1
t
CHC
CE2
t
CH
t
CHP
2004-07-06 9/13
TC51WHM716AXBN70
Provisions of Address Skew
Read
In case, multiple invalid address cycles shorter than t min sustain over 10µs in a active status, as least one
RC
valid address cycle over t min must be needed during 10µs.
RC
over 10µs
CE1
WE
Address
t min
RC
Write
In case, multiple invalid address cycles shorter than t min sustain over 10µs in a active status, as least one
WC
valid address cycle over t
min with t min must be needed during 10µs.
WC
WP
over 10µs
CE1
WE
t min
WP
Address
t min
WC
2004-07-06 10/13
TC51WHM716AXBN70
Notes:
(1)
Stresses greater than listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.
(2)
(3)
(4)
(5)
(6)
All voltages are reference to GND.
I
I
depends on the cycle time.
DDO
DDO
depends on output loading. Specified values are defined with the output open condition.
AC measurements are assumed t , t = 3 ns.
R
F
Parameters t , t
, t
and t
define the time at which the output goes the open condition and
OD ODO BD
ODW
are not output voltage reference levels.
(7)
(8)
Data cannot be retained at deep power-down stand-by mode.
If OE is high during the write cycle, the outputs will remain at high impedance.
During the output state of I/O signals, input signals of reverse polarity must not be applied.
(9)
(10)
If CE1 or LB / UB goes LOW coincident with or after WE goes LOW, the outputs will remain at high
impedance.
(11)
If CE1 or LB / UB goes HIGH coincident with or before WE goes HIGH, the outputs will remain at
high impedance.
2004-07-06 11/13
TC51WHM716AXBN70
PACKAGE DIMENSIONS
Unit:mm
P-FBGA69-0912-0.80B3
12.0
S A
0.20
4
0.15
S
0.10
S
0.10
A
0.47 0.05
S AB
0.08
A
B
C
D
E
F
G H
J
K
L
M
INDEX
1
2
3
4
5
6
7
8
9
10
0.80
0.80
0.40
(7.20)
2.40
Weight:0.25 g (typ)
2004-07-06 12/13
TC51WHM716AXBN70
RESTRICTIONS ON PRODUCT USE
030619EBA
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
2004-07-06 13/13
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