TC554161AFTI-10 [TOSHIBA]
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS; 东芝MOS数字集成电路硅栅CMOS
| 型号： | TC554161AFTI-10 |
| 厂家： | 
TOSHIBA |
| 描述： | TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| 文件： | 总10页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC554161AFTI-70,-85,-10,-70L,-85L,-10L
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOSꢀ
262,144-WORD BY 16-BIT STATIC RAM
DESCRIPTION
The TC554161AFTI is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by
16bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V ±
10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of
10 mA/MHz (typ) and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 2 mA standby
current (typ) when chip enable (CE ) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable (OE ) provides fast memory access. Data byte control pin ( LB ,
UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of -40° to 85°C, the TC554161AFTI can be used in environments exhibiting extreme
temperature conditions. The TC554161AFTI is available in a plastic 54-pin thin -small-outline package (TSOP).
FEATURES
·
Low-power dissipation
·
Access Times (maximum):
Operating: 55 mW/MHz (typical)
TC554161AFTI
·
·
·
·
·
·
Single power supply voltage of 5 V ± 10%
Power down features using CE .
-70,-70L -85,-85L -10,-10L
Data retention supply voltage of 2 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of -40° to 85°C
Standby Current (maximum):
Access Time
CE Access Time
OE Access Time
Package:
70 ns
70 ns
35 ns
85 ns
85 ns
45 ns
100 ns
100 ns
50 ns
TC554161AFTI
·
-70,-85,-10
200 mA
-70L,-85L,-10L
100 mA
TSOP II54-P-400-0.80 (AFTI) (Weight: 0.57 g typ)
5.5 V
3.0 V
100 mA
50 mA
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
NC
A3
1
2
3
4
5
6
7
8
9
54 A4
A0~A17
Address Inputs
53 A5
A2
52 A6
51 A7
I/O1~I/O16 Data Inputs/Outputs
A1
A0
I/O16
I/O15
VDD
GND
I/O14 10
I/O13 11
50 NC
49 I/O1
48 I/O2
47 VDD
46 GND
45 I/O3
44 I/O4
CE
R/W
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Power (+5 V)
Ground
OE
12
13
43
42
UB
CE
LB
OE
LB , UB
OP 14
R/W 15
I/O12 16
I/O11 17
GND 18
VDD 19
41 OP
40 NC
39 I/O5
38 I/O6
37 GND
36 VDD
35 I/O7
34 I/O8
33 A8
V
DD
GND
NC
No Connection
Option
I/O10 20
I/O9 21
NC 22
A17 23
A16 24
A15 25
A14 26
A13 27
OP*
32 A9
*: OP pin must be open of connected to GND.
31 A10
30 A11
29 A12
28 NC
(Normal pinout)
2001-08-17 1/10
TC554161AFTI-70,-85,-10,-70L,-85L,-10L
BLOCK DIAGRAM
CE
A0
A1
A2
A3
V
A11
A12
A13
A14
A15
A16
A17
DD
GND
MEMORY CELL ARRAY
2,048 ´ 128 ´ 16
(4,194,304)
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
SENSE AMP
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
COLUMN ADDRESS
DECODER
COLUMN ADDRESS
REGISTER
COLUMN ADDRESS
BUFFER
CLOCK
CE
GENERATOR
A4 A5 A6 A7 A8 A9A10
R/W
OE
UB
LB
CE
CE
MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
V
V
V
P
Power Supply Voltage
-0.3~7.0
V
V
DD
IN
Input Voltage
-0.3*~7.0
Input/Output Voltage
Power Dissipation
-0.5~V
+ 0.5
V
I/O
D
DD
0.6
W
°C
°C
°C
T
T
T
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
260
solder
stg
opr
-55~150
-40~85
*: -3.0V when measured at a pulse width of 30ns
2001-08-17 2/10
TC554161AFTI-70,-85,-10,-70L,-85L,-10L
DC RECOMMENDED OPERATING CONDITIONS (Ta = -40° to 85°C)
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP
MAX
5.5
UNIT
V
V
V
V
4.5
2.4
5.0
¾
¾
¾
V
V
V
V
DD
Input High Voltage
V
+ 0.3
DD
IH
Input Low Voltage
-0.3*
2.0
0.6
5.5
IL
Data Retention Supply Voltage
DH
*: -3.0V when measured at a pulse width of 30 ns
DC CHARACTERISTICS (Ta = -40° to 85°C, V = 5 V ± 10%)
DD
SYMBOL
PARAMETER
Input Leakage
TEST CONDITION
MIN
TYP MAX UNIT
I
V
= 0 V~V
DD
¾
¾
±1.0
mA
IL
IN
Current
Output Leakage
Current
I
I
I
CE = V or R/W = V or OE = V , V
= 0 V~V
DD
¾
-1.0
2.1
¾
¾
¾
¾
¾
¾
15
¾
¾
10
¾
2
±1.0
¾
mA
mA
mA
LO
OH
OL
IH
IL
IH OUT
Output High Current
Output Low Current
V
V
= 2.4 V
= 0.4 V
OH
OL
¾
t
t
t
t
t
t
= 70 ns
110
100
¾
cycle
cycle
cycle
cycle
cycle
cycle
CE = V and R/W = V
,
IH
IL
I
I
= 0 mA,
OUT
mA
= 85 ns, 100 ns
= 1 ms
¾
DDO1
Other Input = V /V
IH IL
¾
Operating Current
= 70 ns
¾
100
90
CE = 0.2 V and R/W = V - 0.2 V,
DD
I
I
I
= 0 mA,
OUT
mA
mA
= 85 ns, 100 ns
= 1 ms
¾
DDO2
DDS1
Other Input = V
- 0.2 V/0.2 V
DD
¾
¾
CE = V
¾
3
IH
Ta = 25°C
¾
¾
-70,-85,-10
Standby Current
Ta = -40~85°C
Ta = 25°C
¾
¾
2
200
5
CE = V
- 0.2 V,
DD
I
mA
DDS2
V
= 2.0 V~5.5 V
DD
¾
-70L,-85L,-10L
Ta = -40~85°C
¾
¾
100
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
Input Capacitance
Output Capacitance
TEST CONDITION
MAX
UNIT
C
C
V
V
= GND
10
10
pF
pF
IN
IN
= GND
OUT
OUT
Note: This parameter is periodically sampled and is not 100% tested.
2001-08-17 3/10
TC554161AFTI-70,-85,-10,-70L,-85L,-10L
OPERATING MODE
MODE
CE
OE
L
R/W
H
LB
UB
I/O1~I/O8
Output
I/O9~I/O16
Output
POWER
L
H
L
L
H
L
*
L
L
H
L
L
H
*
I
I
I
I
I
I
DDO
DDO
DDO
DDO
DDO
DDO
Read
Write
L
L
High-Z
Output
Input
Output
High-Z
Input
*
L
High-Z
Input
Input
High-Z
L
L
H
*
H
*
Output Deselect
Standby
High-Z
High-Z
High-Z
High-Z
I
DDO
H
*
H
*
H
*
*
I
DDS
* = don't care
H = logic high
L = logic low
2001-08-17 4/10
TC554161AFTI-70,-85,-10,-70L,-85L,-10L
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = -40° to 85°C, V = 5 V ± 10%)
DD
READ CYCLE
TC554161AFTI
SYMBOL
PARAMETER
UNIT
-70,-70L
-85,-85L
-10,-10L
MIN
MAX
¾
MIN
MAX
¾
MIN
MAX
¾
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
70
¾
¾
¾
¾
10
5
85
¾
¾
¾
¾
10
5
100
¾
¾
¾
¾
10
5
RC
Address Access Time
70
70
35
35
¾
85
85
45
45
¾
100
100
50
ACC
CO
Chip Enable Access Time
Output Enable Access Time
OE
Data Byte Control Access Time
Output Data Hold Time
50
BA
¾
OH
ns
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
¾
¾
¾
COE
OEE
BE
0
¾
0
¾
0
¾
0
¾
0
¾
0
¾
¾
¾
¾
30
30
30
¾
¾
¾
35
35
35
¾
¾
¾
40
OD
40
ODO
BD
40
WRITE CYCLE
TC554161AFTI
-85,-85L
SYMBOL
PARAMETER
UNIT
-70,-70L
-10,-10L
MIN
70
50
60
50
0
MAX
¾
MIN
85
55
70
55
0
MAX
¾
MIN
100
60
80
60
0
MAX
¾
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
WC
WP
CW
BW
AS
Write Pulse Width
¾
¾
¾
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
¾
¾
¾
¾
¾
¾
¾
¾
¾
ns
Write Recovery Time
Data Setup Time
0
¾
0
¾
0
¾
WR
DS
30
0
¾
35
0
¾
40
0
¾
Data Hold Time
¾
¾
¾
DH
R/W High to Output Active
R/W Low to Output High-Z
0
¾
0
¾
0
¾
OEW
ODW
¾
30
¾
35
¾
40
AC TEST CONDITIONS
PARAMETER
TEST CONDITION
Output load
100 pF + 1 TTL Gate
Input pulse level
Timing measurements
Reference level
0.4 V, 2.6 V
1.5 V
1.5 V
t , t
R
5 ns
F
2001-08-17 5/10
TC554161AFTI-70,-85,-10,-70L,-85L,-10L
TIMING DIAGRANS
(See Note 1)
READ CYCLE
t
RC
Address
CE
t
t
ACC
OH
t
CO
t
t
OD
OE
OE
t
t
ODO
BA
UB , LB
t
t
BE
BD
t
OEE
D
OUT
Hi-Z
VALID DATA OUT
Hi-Z
t
COE
INDETERMINATE
(See Note 4)
WRITE CYCLE 1 (R/W CONTROLLED)
t
WC
Address
t
t
t
WR
AS
WP
R/W
CE
t
t
CW
BW
UB , LB
t
t
OEW
ODW
D
(See Note 2)
Hi-Z
(See Note 3)
(See Note 5)
OUT
t
t
DH
DS
D
IN
(See Note 5)
VALID DATA IN
2001-08-17 6/10
TC554161AFTI-70,-85,-10,-70L,-85L,-10L
(See Note 4)
CE
WRITE CYCLE 2 (
CONTROLLED)
t
WC
Address
R/W
t
t
t
WR
AS
WP
t
CW
CE
t
BW
UB , LB
t
t
ODW
BE
D
OUT
Hi-Z
Hi-Z
t
COE
t
t
DH
DS
D
IN
(See Note 5)
VALID DATA IN
(See Note 5)
(See Note 4)
UB LB
CONTROLLED)
WRITE CYCLE 3 (
,
t
WC
Address
R/W
t
t
t
WR
AS
WP
t
CW
CE
t
BW
UB , LB
t
t
ODW
COE
D
OUT
Hi-Z
Hi-Z
t
BE
t
t
DH
DS
D
IN
(See Note 5)
VALID DATA IN
(See Note 5)
2001-08-17 7/10
TC554161AFTI-70,-85,-10,-70L,-85L,-10L
Note:
(1)
R/W remains HIGH for the read cycle.
(2)
(3)
(4)
(5)
If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance.
If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance.
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
DATA RETENTION CHARACTERISTICS (Ta = -40° to 85°C)
SYMBOL
PARAMETER
Data Retention Supply Voltage
MIN
TYP
MAX
UNIT
V
V
2.0
¾
¾
¾
¾
0
¾
¾
¾
¾
¾
¾
¾
5.5
100
200
50*
100
¾
DH
V
V
V
V
= 3.0 V
= 5.5 V
= 3.0 V
= 5.5 V
DH
DH
DH
DH
-70,-85,-10
I
Standby Current
mA
DDS2
-70L,-85L,-10L
t
t
Chip Deselect to Data Retention Mode Time
Recovery Time
ns
CDR
R
5
¾
ms
*: 5 mA (max) at Ta = -40° to 40°C
CE
CONTROLLED DATA RETENTION MODE
V
DATA RETENTION MODE
DD
4.5 V
(See Note)
(See Note)
V
IH
t
t
R
CDR
V
- 0.2 V
DD
CE
GND
Note: When CE is operating at the V level (2.4V), the standby current is given by I
IH
during the transition
DDS1
of V
DD
from 4.5 to 2.6V.
2001-08-17 8/10
TC554161AFTI-70,-85,-10,-70L,-85L,-10L
PACKAGE DIMENSIONS
Weight: 0.57 g (typ)
2001-08-17 9/10
TC554161AFTI-70,-85,-10,-70L,-85L,-10L
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
2001-08-17 10/10
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