TC5565AFL-15 [TOSHIBA]
65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology; 65,536位的静态随机存取存储器通过使用CMOS技术的8位， 8192字
| 型号： | TC5565AFL-15 |
| 厂家： | 
TOSHIBA |
| 描述： | 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology |
| 文件： | 总9页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TOSHIBA MOS MEMORY PRODUCTS
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
DESCRIPTION
The TC5565APL/AFL is 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology, and
operates from a single 5V supply. Advanced circuit techniques provide both high speed and low power features with a maximum
operating current of 5mA/MHz and maximum access time of 100ns/120ns/150ns.
When CE2 is a logical low or \CEl is a logical high, the device is placed in low power standby mode in which standby current is 2uA
typically. The TC5565APL/AFL has three control inputs. Two chip enable (\CE1, CE2) allow for device selection and data retention
control, and an output enable input (\OE) provides fast memory access. Thus the TC5565APL/AFL is suitable for use in various
microprocessor application systems where high speed, low power, and battery back up are required.
The TC5565APL also features pin compatibility with the 64K bit EPROM (TMM2764D).
RAM and EPROM are then interchangeable in the same socket, resulting in flexibility in the definition of the quantity of RAM versus
EPROM in microprocessor application systems. The TC5565APL is offered in a dual-in-line 28 pin standard plastic package. The
TC5565AFL is offered in 28 pin mini Flat Package.
FEATURES
·
Directly TTL Compatible
·
Low Power Dissipation
: All Inputs and Outputs
27.5mW/MHz(Max.) operating
Standby Current: 100uA(Max.) Ta=70°C
Access Time
·
·
Pin Compatible with 2764 type EPROM
TC5565APL Family (Package Type)
·
·
TC5565APL/AFL-10 : 100ns(Max.)
TC5565APL/AFL-12 : 120ns(Max.)
TC5565APL/AFL-15 : 150ns(Max.)
Package Type
600 mil DIP
300 mil DIP
(Slim Package)
Flat Package
(SOP)
Device Name
TC5565APL
*TC5563APL
·
·
·
5V Single Power Supply
-
Power Down Features: CE2, \CE1
Fully Static Operation
TC5565AFL
Data Retention Supply Voltage: 2.0-5.5V
* See TC5563APL Technical Data.
BLOCK DIAGRAM
PIN CONNECTION (TOP VIEW)
AO-A12
R/W
Address Inputs
Read/Write Control Input
Output Enable Input
Chip Enable Inputs
Data Input/Output
Power (+5V)
\OE
\CE1, CE2
I/O1 – I/O8
VDD
GND
Ground
N.C.
No Connection
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
OPERATION MODE
Read
Write
Output Deselect
Standby
\CE1
L
L
L
H
CE2
H
H
H
*
\OE
L
*
H
*
*
R/W
H
L
H
*
1/01-T/08
DOUT
POWER
IDDO
IDDO
IDDO
IDDS
DIN
High-Z
High-Z
High-Z
L
*
IDDS
MAXIMUM RATINGS
SYMBOL
ITEM
RATING
UNIT
VDD
VIN
VI/O
PD
Power Supply Voltage
-0.3~7.0
v
v
v
W
Input Voltage
*-0.3~7.0
Input and Output Voltage
Power Dissipation
-0-5-VDD+0.5
1.0/0.6**
Tsolder
Tstg
Topr
Soldering Temperature
Storage Temperature
Operating Temperature
260-10
-55~150
0-70
°C sec
°C
°C
* -3.0V at pulse width 50ns MAX. **Flat package
D.C RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDD
PARAMETER
Power Supply Voltage
Input High Voltage
MIN.
Typ.
5.0
MAX.
5.5
UNIT
v
4.5
2.2
V
IH
-
VDD+0.3
v
V
Input Low Voltage
IL
-0.3
2.0
-
-
0.8
5.5
V
V
VDH
Data-Retention Supply Voltage
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
D.C and OPERATING CHARACTERISTICS (Ta=0~70°C, VDD = 5V±10%)
SYMBOL
PARAMETER
TEST CONDITION
MIN. TYP. MAX. UNIT
Input Leakage
IIL
VIN=O~VDD
-
-
±1.0 uA
Current
IOH
IOL
Output High Current
Output Low Current
VOH-2-4V
VOL-0.4V
-1.0
4.0
-
-
mA
mA
V or CE2-VOL or
IH
\CE1 = V or CE2=VOL 0r R/W = V
IH
IL
ILO
Output Leakage Current
Operating Current
Standby Current
-
-
-
±1.0 uA
or \OE=V
IH
VOUT=0~VDD
tcycle =1.0us
10
45
mA
mA
TC5565APL-10 tcycle
TC556SAFL-10 =100ns
-
VDD =5.5V
\CE1=V
IL
IDDO1
CE2=V
IH
TC5565APL-12 tcycle
-
-
40
mA
Other input=
V /V
TC5565AFL-12 =120ns
IH
IL
TC5565A?L-15 tcycle
TC5565AFL-15 =150ns
-
-
35
mA
tcycle=1.0us
-
-
-
-
5
mA
TC5565APL-10
tcycle =100ns
40
mA
VDD=5.5V
\CEl=O.2V
CE2=VDD –0.2V
Other lnput=
VDD - 0.2V/0.2V
TC5565AFL-10
TC5565AFL-12
TC5565AFL-12
IDD02
tcycle =120ns
tcycle =150ns
-
-
-
-
35
30
mA
mA
TC5565APL-15
TC5565AFL-15
IDDS1
\Cel = V or CE2 = V
3
100
50
mA
uA
uA
IH
IL
VDD = 5.5V
VDD = 3.0V
-
-
2
1
\CE1 = VDD – 0.2V or
CE2 = 0.2V
*IDDS2
Note * In standby mode with \CE1>= VDD – 0.2V, these specification limits are guaranteed under the condition of
CE2 >= VDD – 0.2V or CE2 <= 0.2V.
CAPACITANCE (Ta=25°C)
SYMBOL
CIN
COUT
PARAMETER
Input Capacitance
Output Capacitance
* This parameter periodically sampled is not 100% tested.
TEST CONDITION
VIN = GND
MIN.
-
-
TYP.
MAX. UNIT
-
-
10
10
pF
pF
VOUT = GND
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
A.C. CHARACTERISTICS (Ta=0~70°C, VDD = 5V±10%)
Read Cycle
SYMBOL PARAMETER
TC5565APL-10
TC5565AFL-10
TC5565APL-12 TC5565APL-15
TC5565AFL-12 TC5565AFL-15
MIN. MAX. MIN.
MAX. MIN.
MAX
-
tRC
Read Cycle Time
100
-
120
-
150
tACC
tCOL
tC02
tOE
Address Access Time
\CE1 Access Time
CE2 Access Time
Output Enable to Output Valid
Chip Enable (\CE1, CE2) to
Output in Low-Z
Output Enable to Output in Low-Z
Chip Enable (CE1, CE2) to
Output in High-Z
-
-
-
-
100
100
100
50
-
-
-
-
120
120
120
60
-
-
-
-
150
150
150
70
tCOE
10
5
-
-
10
5
-
-
15
5
-
-
tOEE
tOD
-
35
-
40
-
50
tODO
tOH
Output Enable to Output in High-Z
Output Data Hold Time
-
20
35
-
-
20
40
-
-
20
50
-
Write Cycle
SYMBOL
TC5565APL-10
TC5565AFL-10
TC5565APL-12 TC5565APL- 5
TC5565AFL-12 TC5565AFL- 5
PARAMETER
MIN. MAX. MIN.
MAX. MIN. MAX..
tWC
tWP
tCW
tAS
rWR
tODW
rOEW
tDS
Write Cycle Time
Write Pulse Width
100
60
80
0
0
-
5
40
0
-
-
-
-
-
35
-
-
120
70
85
0
0
0
5
50
0
-
-
-
-
-
40
-
-
150
90
100
0
0
-
10
60
0
-
-
-
-
-
50
-
-
Chip Selection to End of Write
Address Set up Time
Write Recovery Time
R/W to Output High-Z
R/W to Output Low-Z
Data Set up Time
tDH
Data Hold Time
-
-
-
A.C. TEST CONDITION
Output Load
: 100pF + 1 TTL Gate
: 0.6V, 2.4V
: 0.8V, 2.2V
: 0.8V, 2.2V
: 5ns
Input Pulse Level
Timing Measurement
Reference Level
tr, tf
V
VOUT
IN
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
TIMING WAVEFORMS
READ CYCLE (1)
WRITE CYCLE 1 (4) (R/W Controlled Write)
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
WRITE CYCLE 2 (4) (\CE1 Controlled Write)
WRITE CYCLE 3 (4) (CE2 Controlled Write)
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
Note 1. R/W is High for Read Cycle.
2.
3.
4.
Assuming that \CE1 Low transition of CE2 High transition occurs coincident with or after R/W Low transition, Outputs
remain in a high impedance state.
Assuming that \CEl High transition or CE2 Low transition occurs coincident with or prior to R/W High transition, Outputs
remain in a high impedance state.
Assuming that \OE is High for Write Cycle, Outputs are in high impedance state during this period.
DATA RETENTION CHARACTERISTICS (Ta=0~70°C)
SYMBOL
VDH
PARAMETER
Data Retention Supply Voltage
Stand by Supply Current
MIN. TYP. MAX. UNIT
2.0
-
-
-
-
-
5.5
50
100
-
V
VDD=3.0V
VDD=5.5V
-
-
0
IDDS2
uA
tCDR
tR
Chip Deselection to Data Retention Mode
Recovery Mode
us
us
tRC(1)
-
Note (1) : Read cycle Time.
\CE1 Controlled Data Retention Mode (2)
CE2 Controlled Data Retention Mode (4)
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
Note 2 :
In \CE1 controlled data retention mode, minimum standby current mode is achieved under the condition Of CE2<= O.2V Or
CE2>= VDD -0.2V.
3 : If the V of \CE1 is 2.2V in operation, IDDS1 current flows during the period that the VDD voltage is going down from 4.5V to
IH
2.4V,
4 ; In CE2 controlled data retention mode, minimum standby current mode is achieved under the condition of CE2 <= 0.2V.
DEVICE INFORMATION
The TC5565APL/AFL is an synchronous RAM using address activated circuit technology, thus the internal operation is synchronous.
Then once row address change occur, the precharge operation is executed by internal pulse generated from row address transient.
Therefore the peak current flows only after row address change, as shown in the following figure.
This peak current may induce the noise on VDD /GND lines. Thus the use of about 0.1uF decoupling capacitor for every device is
recommended to eliminate such noise.
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
DIP 28 PIN OUTLINE DRAWING (6D28A-P)
Unit in mm
Note) Lead pitch is 2.54 and tolerance is +\-0.25 against theoretical center of each
lead that is obtained on the basis of No.1 and No.28 leads.
MFP 28 PIN OUTLINE DRAWING (F28GC-P)
Unit in mm
Note) Lead pitch is 1.27 and tolerance is +\-0.12 against theoretical center of each
lead that is obtained on the basis of No.1 and N0.28 leads
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