TC58DVG02A5TAI0 [TOSHIBA]
IC 128M X 8 EEPROM 3V, PDSO48, 12 X 20 MM, 0.50 MM PITCH, PLASTIC, TSOP1-48, Programmable ROM;
| 型号： | TC58DVG02A5TAI0 |
| 厂家： | 
TOSHIBA |
| 描述： | IC 128M X 8 EEPROM 3V, PDSO48, 12 X 20 MM, 0.50 MM PITCH, PLASTIC, TSOP1-48, Programmable ROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总38页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC58DVG02A5TAI0
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1-GBIT (128M × 8 BITS) CMOS NAND E2PROM
DESCRIPTION
The TC58DVG02A5 is a 1-Gbit (1,107,296,256 bits) NAND Electrically Erasable and Programmable Read-Only
2
Memory (NAND E PROM) organized as 528 bytes × 32 pages × 8192 blocks. The device has a 528-byte static
register which allows program and read data to be transferred between the register and the memory cell array in
528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes ×
32 pages).
The TC58DVG02A5 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
•
Organization
Memory cell allay
Register
528 × 256K × 8
528 × 8
Page size
528 bytes
Block size
(16K + 512) bytes
•
•
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read
Mode control
Serial input/output
Command control
•
Number of valid blocks
Min 8032 blocks
Max 8192 blocks
•
•
Power supply
V : 2.7 V to 3.6 V
CC
Access time
Cell array to register 25 μs max
Serial Read Cycle
40 ns min
•
•
Program/Erase time
Auto Page Program
Auto Block Erase
300 μs/page typ.
2.5 ms/block typ.
Operating current
Read (40 ns cycle)
Program (avg.)
Erase (avg.)
20 mA max.
20 mA max.
20 mA max.
50 μA max
Standby
•
Package
TSOPI48-P-1220-0.50 (Weight: 0.53g typ.)
1
2010-07-13
TC58DVG02A5TAI0
PIN ASSIGNMENT (TOP VIEW)
NC
NC
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
2
NC
NC
3
NC
NC
NC
4
NC
5
I/O8
I/O7
I/O6
I/O5
NC
NC
6
RY /BY
RE
7
8
CE
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
V
V
V
CC
SS
CC
SS
V
NC
NC
NC
NC
NC
CLE
ALE
WE
WP
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
NC
NC
NC
NC
PINNAMES
I/O1 to I/O8
CE
I/O port
Chip enable
WE
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
RE
CLE
ALE
WP
RY/BY
V
Power supply
Ground
CC
V
SS
NC
No connection
2
2010-07-13
TC58DVG02A5TAI0
BLOCK DIAGRAM
V
V
CC SS
Status register
Address register
Column buffer
Column decoder
Data register
Sense amp
I/O1
I/O Control circuit
to
I/O8
Command register
CE
CLE
ALE
WE
RE
Memory cell array
Logic control
Control
WP
RY/BY
RY/BY
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
V
V
V
P
Power Supply Voltage
−0.6 to 4.6
−0.6 to 4.6
V
V
CC
Input Voltage for Control pins
Input/Output Voltage for I/O pins
Power Dissipation
IN
−0.6 V to V
+ 0.3 V (≤ 4.6 V)
0.3
V
I/O
D
CC
W
°C
°C
°C
T
solder
T
stg
T
a
Soldering Temperature (10s)
Storage Temperature
260
−55 to 125
-40 to 85
Operating Ambient Temperature
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMB0L
PARAMETER
CONDITION
MIN
MAX
UNIT
C
C
*
Input
V
V
= 0 V
⎯
⎯
10
10
pF
pF
IN
IN
Output
= 0 V
OUT
OUT
This parameter is periodically sampled and is not tested for every device.
3
2010-07-13
TC58DVG02A5TAI0
VALID BLOCKS (1)
SYMBOL
PARAMETER
Number of Valid Blocks
MIN
TYP.
MAX
8192
UNIT
N
8032
⎯
Blocks
VB
(1) The device occasionally contains unusable blocks. Refer to Application Note (14) toward the end of this document.
The 1st block (block address #00) is guaranteed to be a valid block at the time of shipment.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
Power Supply Voltage
MIN
2.7
TYP.
MAX
3.6
UNIT
V
V
V
*
⎯
⎯
⎯
V
V
V
CC
High Level input Voltage
Low Level Input Voltage
V
× 0.78
V
+ 0.3
IH
IL
CC
CC
−0.3*
V
× 0.22
CC
−2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS (Ta = -40° to 85°C, V = 2.7 V to 3.6 V )
CC
SYMBOL
PARAMETER
CONDITION
CC
MIN
TYP.
MAX
UNIT
I
I
I
Input Leakage Current
Output Leakage Current
V
V
= 0 V to V
⎯
⎯
⎯
⎯
⎯
⎯
±10
±10
20
μA
μA
IL
IN
= 0 V to V
CC
LO
OUT
Operating Current (Serial Read) CE = V , I
IL OUT
= 0 mA, t
cycle
= 40 ns
mA
CCO1
Operating Current
(Command Input)
I
I
I
t
t
t
= 40 ns
= 40 ns
= 40 ns
⎯
⎯
⎯
⎯
⎯
⎯
20
20
20
mA
mA
mA
CCO3
CCO4
CCO5
cycle
cycle
cycle
Operating Current (Data Input)
Operating Current
(Address Input)
I
I
I
Programming Current
Erasing Current
⎯
⎯
⎯
⎯
⎯
2.4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
8
20
20
50
⎯
mA
mA
μA
V
CCO7
CCO8
CCS
Standby Current
CE = V
CC
− 0.2 V, WP = 0 V/V
CC
V
V
High Level Output Voltage
Low Level Output Voltage
I
I
= −400 μA
= 2.1 mA
OH
OH
OL
0.4
⎯
V
OL
I
( RY/BY ) Output Current of RY/BY pin
V
= 0.4 V
OL
mA
OL
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2010-07-13
TC58DVG02A5TAI0
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = -40° to 85°C, V = 2.7 V to 3.6 V)
CC
SYMBOL
PARAMETER
MIN
MAX
UNIT
NOTES
t
CLE Setup Time (*1)
CLE Hold Time
20
10
30
10
20
20
10
20
5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
30
35
⎯
40
⎯
⎯
30
20
⎯
⎯
⎯
⎯
25
100
⎯
130
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
μs
CLS
t
CLH
t
CE Setup Time (*2)
CE Hold Time
CS
t
CH
t
Write Pulse Width
ALE Setup Time (*1)
ALE Hold Time
WP
t
ALS
ALH
t
t
Data Setup Time
Data Hold Time
DS
DH
t
t
t
Write Cycle Time
WE High Hold Time
WP High to WE Low
40
15
100
20
20
40
⎯
⎯
10
⎯
100
10
⎯
⎯
15
0
WC
WH
t
WW
t
Ready to RE Falling Edge
RR
t
Read Pulse Width
RP
RC
t
Read Cycle Time
t
t
RE Access Time (Serial Data Access)
CE Access Time (Serial Data Access)
CLE Low to RE Low
REA
CEA
t
CLR
t
ALE Access Time (ID Read)
ALEA
t
CE High Time for Last Address in Serial Read Cycle
Data Output Hold Time
(2)
CEH
t
OH
t
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
RHZ
CHZ
REH
t
t
t
IR
Output-High-impedance-to- RE Falling Edge
WE High to CE Low
t
t
30
30
⎯
⎯
10
⎯
⎯
WHC
WHR
WE High to RE Low
t
R
Memory Cell Array to Starting Address
WE High to Busy
t
WB
t
ALE Low to RE Low (Read Cycle)
RE Last Clock Rising Edge to Busy (in Sequential Read)
CE High to Ready (When interrupted by CE in Read Mode)
AR2
t
RB
t
(1) (2)
CRY
5 / 5 / 10 /
500
t
Device Reset Time (Ready/Read/Program/Erase)
⎯
μs
RST
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 10ns.
5
2010-07-13
TC58DVG02A5TAI0
Note:
(1) CE High to Ready time depends on the pull-up resister tied to the RY /BY pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when t
ns , RY /BY signal stays Ready.
is greater than or equal to 100 ns. If the RE to CE delay is less than 30
CEH
t
≧ 100 ns
CEH
*
*: V or V
IH IL
CE
RE
A
A : 0 to 30 ns → Busy signal is not output.
t
525
527
RB
RY/BY
Busy
t
CRY
AC TEST CONDITIONS
CONDITION
2.7V to 3.6V
PARAMETER
Vcc
Input level
V
CC
− 0.2 V, 0.2 V
3 ns
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
Vcc / 2
Vcc / 2
C (100 pF) + 1 TTL
L
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = -40° to 85°C, V = 2.7 V to 3.6 V)
CC
SYMBOL
PARAMETER
Programming Time
MIN
TYP.
300
MAX
700
UNIT
NOTES
(1)
t
⎯
μs
PROG
Number of Programming Cycles on Same
Page
N
⎯
⎯
⎯
3
7
t
Block Erasing Time
2.5
ms
BERASE
(1): Refer to Application Note (12) toward the end of this document.
6
2010-07-13
TC58DVG02A5TAI0
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
CLE
ALE
CE
RE
Setup Time
Hold Time
WE
t
t
DH
DS
I/O
: V or V
IH IL
Command Input Cycle Timing Diagram
CLE
t
t
CLH
CLS
t
CH
t
CS
CE
WE
ALE
I/O
t
WP
t
t
ALH
ALS
t
t
DH
DS
: V or V
IH IL
7
2010-07-13
TC58DVG02A5TAI0
Address Input Cycle Timing Diagram
t
CLS
CLE
CE
t
t
t
CH
CS
CH
t
WC
t
t
t
t
t
t
t
WP
WP
WH
WP
WH
WP
WH
WE
ALE
I/O
t
t
ALH
ALS
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
A0 to A7
A9 to A16
A17 to A24
A25 to A26
: V or V
IH IL
Data Input Cycle Timing Diagram
t
CLH
CLE
t
t
CH
CS
t
CH
t
CS
CE
ALE
WE
I/O
t
ALS
t
WC
t
t
t
t
WP
WP
WH
WP
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
D
IN
0
D
IN
1
D
527
IN
: V or V
IH IL
8
2010-07-13
TC58DVG02A5TAI0
Serial Read Cycle Timing Diagram
t
RC
CE
RE
t
t
t
t
t
t
CHZ
RP
REH
RP
CH
RP
t
t
t
t
RHZ
RHZ
RHZ
t
t
t
REA
t
t
OH
REA
REA
OH
OH
I/O
t
RR
t
CEA
RY/BY
Status Read Cycle Timing Diagram
t
CLR
CLE
t
t
CLH
CLS
t
CS
CE
WE
t
t
CH
WP
t
t
t
CHZ
WHC
CEA
t
WHR
RE
t
OH
t
t
t
IR
DS
DH
t
t
RHZ
REA
Status
output
I/O
70h*
RY/BY
* 70h represents the hexadecimal number
: V or V
IH IL
9
2010-07-13
TC58DVG02A5TAI0
Read Cycle (1) Timing Diagram
CLE
t
t
CLS CLH
t
CEH
t
CH
t
CS
CE
WE
t
t
CRY
WC
t
t
AR2
ALH
t
ALS
t
ALH
ALE
RE
t
RR
t
t
R
RC
t
WB
t
t
t
t
t
t
t
t
t
t
t
REA
DS DH
DS DH
DS DH
DS DH
DS DH
A0
to A7
A9
to A16
A17
to A24
A25
to A26
D
OUT
N
D
OUT
N + 1
D
OUT
N + 2
D
OUT
527
00h
I/O
t
RB
Column address
N*
RY/BY
* Read Operation using 00h Command N: 0 to 255
: V or V
IH IL
Read Cycle (1) Timing Diagram: When Interrupted by CE
CLE
t
t
CLH
CLS
t
CH
t
CS
CE
WE
ALE
RE
t
t
WC
CHZ
t
t
AR2
ALH
t
ALS
t
ALH
t
R
t
t
RC
RR
t
WB
t
OH
t
t
t
t
t
t
t
t
t
t
t
REA
DS DH
DS DH
DS DH
DS DH
DS DH
t
RHZ
A0
to A7
A9
to A16
A17
to A24
A25
to A26
D
OUT
N
D
OUT
N + 1
D
OUT
N + 2
I/O
00h
Column address
N*
RY/BY
*: Read operation using 00h command N: 0 to 255
: V or V
IH IL
10
2010-07-13
TC58DVG02A5TAI0
Read Cycle (2) Timing Diagram
CLE
t
t
CLH
CLS
t
t
CH
CS
CE
WE
t
t
t
ALH
t
AR2
ALH
ALS
ALE
RE
t
R
t
t
RC
RR
t
WB
t
t
t
t
t
REA
DS DH
DS DH
A9
A17
A25
I/O
01h
A0 to A7
D
OUT
D
OUT
D
OUT
to A16 to A24 to A26
256 + N 256 + N + 1
527
Column address
N*
RY/BY
: V or V
IH IL
*: Read operation using 01h command N: 0 to 255
Read Cycle (3) Timing Diagram
CLE
t
t
t
CLH
CLS
t
CS
CH
CE
WE
t
t
t
ALH
t
AR2
ALH
ALS
ALE
RE
t
R
t
t
RC
RR
t
WB
t
t
t
t
t
DS DH
DS DH
REA
A9
A17
A25
50h
A0 to A7
D
OUT
D
OUT
D
OUT
I/O
to A16 to A24 to A26
512 + N 512 + N + 1
527
Column address
N*
RY/BY
: V or V
IH IL
*: Read operation using 50h command N: 0 to 15
11
2010-07-13
TC58DVG02A5TAI0
Sequential Read (1) Timing Diagram
CLE
CE
WE
ALE
RE
A25
to
A26
A0
to
A7 A16
A9
A17
to
I/O1
to I/O8
00h
N
N + 1 N + 2
527
0
1
527
to
A24
Column
address
N
Page
address
M
t
R
t
R
RY/BY
A17
Page M + 1
access
: V or V
IH
IL
Sequential Read (2) Timing Diagram
CLE
CE
WE
ALE
RE
A0
to
A7 A16
A9
A17
to
A25
to
I/O1
to I/O8
to
01h
527
0
1
2
527
A24
A26
Column
address
N
Page
address
M
t
R
t
R
256 + 256 + 256 +
N
N + 1 N + 2
RY/BY
Page M
access
Page M + 1
access
: V or V
IH IL
12
2010-07-13
TC58DVG02A5TAI0
Sequential Read (3) Timing Diagram
CLE
CE
WE
ALE
RE
I/O1
A9 A17 A25
A0
to A7
50h
527
512 513 514
527
to
to
to
A26
to I/O8
A16 A24
Page
Column
address
N
t
R
t
R
512 + 512 + 512 +
N + 1 N + 2
address
M
N
RY/BY
Page M
access
Page M + 1
access
: V or V
IH IL
13
2010-07-13
TC58DVG02A5TAI0
Auto-Program Operation Timing Diagram
t
CLS
CLE
CE
t
t
CLS CLH
t
CS
t
CH
t
CS
WE
t
t
ALH
ALH
t
t
PROG
ALS
t
ALS
t
WB
ALE
RE
t
DS
t
t
t
t
t
t
t
DS DH
DS DH
DH
DS DH
A0 to
A7
A9
A17
A25
D
IN
527
80h
D 0
IN
D 1
IN
10h
70h
I/O
toA16 toA24 to A26
Status
output
RY/BY
: V or V
IH IL
: Do not input data while data is being output.
Auto Block Erase Timing Diagram
CLE
t
CLS
t
CLH
t
t
CLS
CS
CE
WE
t
t
t
t
BERASE
ALS
ALH
WB
ALE
RE
t
t
DS DH
A9
A17
A25
Status
output
60h
D0h
70h
I/O
toA16 toA24 to A26
Auto Block Erase
Setup command
Erase Start
command
Status Read
command
RY/BY
Busy
: V or V
IH IL
: Do not input data while data is being output.
14
2010-07-13
TC58DVG02A5TAI0
ID Read Operation Timing Diagram
CLE
t
CLS
t
CLS
t
t
CH
CS
t
CS
CE
WE
ALE
RE
t
CH
t
CEA
t
t
ALS
t
t
ALEA
ALH
ALH
t
t
t
REA
DS DH
t
REA
I/O
90h
00h
98h
79h
Address
input
Maker code
Device code
: V or V
IH IL
15
2010-07-13
TC58DVG02A5TAI0
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading of either address information or input data into the internal
address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is
latched if ALE is Low.
Chip Enable: CE
The device goes into a low-power Standby mode when CE goes High during a wait state. The CE signal is
ignored when device is in Busy state ( RY/BY = L), such as during a Program or Erase or Read operation, and
will not enter Standby mode even if the CE input goes High.
Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable: RE
The RE signal controls serial data output. Data is available t
after the falling edge of RE .
REA
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
RY/ BY
Ready/Busy:
The RY/BY output signal is used to indicate the operating condition of the device. The RY/BY signal is in
Busy state ( RY/BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY/BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.
16
2010-07-13
TC58DVG02A5TAI0
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
I/O1
I/O8
A page consists of 528 bytes in which 512 bytes are
used for main memory storage and 16 bytes are for
redundancy or for other uses.
512
16
32 pages
1 block
1 page = 528 bytes
1 block = 528 bytes × 32 pages = (16K + 512) bytes
Capacity = 528 bytes × 32 pages × 8192 blocks
262144 pages
8192 blocks
An address is read in via the I/O port over four
consecutive clock cycles, as shown in Table 1.
8I/O
528
Figure 1. Schematic Cell Layout
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A0 to A7: Column address
A9 to A26: Page address
First cycle
A7
A16
A24
*L
A6
A15
A23
*L
A5
A14
A22
*L
A4
A13
A21
*L
A3
A12
A20
*L
A2
A11
A19
*L
A1
A0
A9
Second cycle
Third cycle
Fourth cycle
A10
A18
A26
A14 to A26: Block address
A9 to A13: NAND address in block
A17
A25
* : A8 is automatically set to Low or High by a 00h command or a 01h command.
l/O3-8 must be set to Low in the fourth cycle.
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Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command
operations shown in Table 4. Address input, command input and data input/output are controlled by the CLE,
ALE, CE , WE , RE and WP signals, as shown in Table 2.
Table 2. Logic table
*1
CLE
ALE
CE
WE
RE
WP
Command Input
H
L
L
L
*
L
H
L
L
*
L
L
L
L
*
H
H
H
*
Address Input
*
Data Input
H
Serial Data Output
During Programming (Busy)*2
During Erasing (Busy)*2
Program, Erase Inhibit
Standby
H
*
*
*
*
*
H
*
*
*
*
*
*
*
H
*
*
*
L
*
*
H
0 V/V
CC
H: V , L: V , *: V or V
IH IL IH IL
*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: The CE signal is ignored when device is in Busy state ( RY/BY = L), such as during a Program or Erase or Read operation,
and will not enter Standby mode even if the CE input goes High.
Table 3 shows the operation states for Read mode.
Table 3. Read mode operation states
CLE
ALE
CE
WE
RE
I/O1 to I/O8
Power
Output Select
L
L
L
L
L
L
H
H
L
Data output
Active
Active
Output Deselect
H
High impedance
H: V , L: V
IH IL
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Table 4. Command table (HEX)
First Cycle
Second Cycle Acceptable while Busy
HEX data bit assignment
(Example)
Serial Data Input
Read Mode (1)
Read Mode (2)
Read Mode (3)
Reset
80
00
01
50
FF
10
60
70
90
⎯
⎯
⎯
⎯
Serial data input: 80h
1
0
0
6
0
5
0
4
0
3
0
2
0
⎯
⎯
D0
⎯
⎯
c
c
I/O8 7
I/O1
Auto Program
Auto Block Erase
Status Read
ID Read
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DEVICE OPERATION
Read Mode (1)
Read mode (1) is set when a 00h command is issued to the Command register. Refer to Figure 2 below for
timing details and the block diagram.
CLE
CE
WE
ALE
RE
RY/BY
Busy
N
M
I/O
00h
M
Start-address input
A data transfer operation from the cell array to the register
527
starts on the rising edge of WE in the fourth cycle (after the
address information has been latched). The device will be in
Busy state during this transfer period.
Select page
N
Cell array
After the transfer period the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start pointer designated in the address input cycle.
Figure 2. Read mode (1) operation
Read Mode (2)
CLE
CE
WE
ALE
RE
RY/BY
I/O
Busy
N
M
01h
Start-address input
256
M
527
The operation of the device after input of the 01h command is
the same as that of Read mode (1). If the start pointer is to be
set after column address 256, use Read mode (2).
Select page
N
Cell array
Figure 3. Read mode (2) operation
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TC58DVG02A5TAI0
Read Mode (3)
Read mode (3) has the same timing as Read modes (1) and (2), but it is used to access information in the extra
16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte
527.
CLE
CE
WE
ALE
RE
RY/BY
I/O
Busy
50h
Addresses bits A0 to A3 are used to set the start pointer for
A0 to A3
the redundant memory cells, while A4 to A7 are ignored.
Once a 50h command has been issued, the pointer moves to
the redundant cell locations and only those 16 cells can be
addressed, regardless of the value of the A4 to A7 address. (An
00h or an 01h command is necessary to move the pointer back
to the 0 to 511 main memory cell location.)
512
527
Figure 4. Read mode (3) operation
Sequential Read (1) (2) (3)
This mode allows the sequential reading of pages without additional address input.
00h
01h
Address input
Data output
Data output
50h
t
R
t
R
t
R
RY/BY
Busy
Busy
527
Busy
(00h)
0
527
(01h)
(50h)
512 527
A
A
A
Sequential Read (1)
Sequential Read (2)
Sequential Read (3)
Sequential Read mode (1) and (2) output the contents of addresses 0 to 527 as shown above, while Sequential
Read mode (3) outputs the contents of the redundant address locations only.
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Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result
(pass/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device
status is output via the I/O port on the RE clock after a Status Read command "70h" input. The resulting
information is outlined in Table 5 .
Table 5. Status output table for Status Read (1) command "70h"
STATUS
OUTPUT
Fail: 1
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
Pass/Fail
Not Used
Pass: 0
0
Not Used
0
The Pass/Fail status on I/O1 is only
valid when the device is in the Ready
state.
Not Used
0
Not Used
0
Not Used
0
Ready/Busy
Write Protect
Ready: 1
Protect: 0
Busy: 0
Not Protected: 1
An application example with multiple devices is shown in Figure 5.
CE1
CE2
CE3
CEN
CEN + 1
CLE
ALE
WE
RE
Device
1
Device
2
Device
3
Device
N
Device
N + 1
I/O1
to I/O8
RY/BY
RY/BY
Busy
CLE
ALE
WE
CE1
CEN
RE
I/O
70h
70h
Status on Device 1
Status on Device N
Figure 5. Status Read timing application example
System Design Note: If the RY/BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each
individual device.
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Auto Page Program
The device carries out an Automatic Page Program operation when it receives a “10h” Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
Pass
80
10
70
I/O
Data input Address Data input Program
Status Read
command
Fail
command input
0 to 527 command
RY/BY
RY/BY automatically returns to Ready after
completion of the operation.
Data input
Program
Reading & verification
Selected
page
The data is transferred (programmed) from the register to the selected
page on the rising edge of WE following input of the “10h” command.
After programming, the programmed data is transferred back to the
register to be automatically verified by the device. If the programming
does not succeed, the Program/Verify operation is repeated by the
device until success is achieved or until the maximum loop number set in
the device is reached.
Figure 6. Auto Page Program operation
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
Pass
60
D0
70
I/O
Fail
Block Address Erase Start
input: 3 cycles command
Status Read
command
RY/BY
Busy
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Reset
The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally
generated voltage is discharged to 0 volts and the device enters Wait state.
The response to an “FFh” Reset command input during the various device operations is as follows:
When a Reset (FFh) command is input during programming
Figure 7.
80
10
FF
00
Internal V
PP
RY/BY
t
(max 10 μs)
RST
When a Reset (FFh) command is input during erasing
Figure 8.
00
D0
FF
Internal erase
voltage
RY/BY
t
(max 500 μs)
RST
When a Reset (FFh) command is input during Read operation
Figure 9.
00
00
FF
RY/BY
t
(max 5 μs)
RST
When a Status Read command (70h) is input after a Reset
Figure 10.
FF
70
I/O status: Pass/Fail → Pass
Ready/Busy → Ready
RY/BY
FF
70
I/O status: Ready/Busy → Busy
RY/BY
When two or more Reset commands are input in succession
Figure 11.
(1)
FF
(2)
FF
(3)
FF
RY/BY
The second
FF
command is invalid, but the third
FF command is valid.
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ID Read
ID Read command 90h provides maker code and device code. The ID codes can be read out under the following
timing conditions:
CLE
t
CEA
CE
WE
ALE
RE
t
ALEA
t
REA
I/O
90h
00h
98h
79h
ID Read command
Address
00h
Maker code
Device code
Figure 12. ID Read timing
Table 6. ID Codes read out by ID read command 90h
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
Hex Data
Maker code
Device code
1
0
0
1
0
1
1
1
1
1
0
0
0
0
0
1
98h
79h
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APPLICATION NOTES AND COMMENTS
(1)
Power-on/off sequence:
The WP signal is useful for protecting against data corruption at power-on/off. The following timing
sequence is necessary.
The WP signal may be negated any time after the V
power up sequence.
reaches 2.5 V and CE signal is kept high in
CC
2.7 V
2.5 V
V
CC
0 V
Don’t
care
Don’t
care
CE , WE , RE
CLE, ALE
V
IH
V
IL
V
IL
WP
1 ms max
Operation
100 μs max
Don’t
care
Invalid
Ready/Busy
In order to operate this device stably, after V
becomes 2.5V, it should begin access after about 1 ms.
CC
Figure 13. Power-on/off Sequence
(2)
Status after power-on
The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
Figure 14.
(3)
(4)
Prohibition of unspecified commands
The operation commands are listed in Table 4. Input of a command other than those specified in Table 4 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
Restriction of command while Busy state
During Busy state, do not input any command except 70h and FFh.
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TC58DVG02A5TAI0
(5)
Acceptable commands after Serial Input command “80h”
Once the Serial Input command “80h” has been input, do not input any command other than the Program
Execution command “10h” or the Reset command “FFh”.
If a command other than “10h” or “FFh” is input, the Program operation is not performed.
80
XX
10
For this operation the “FFh” command is needed.
Command other than
“10h” or “FFh”
Programming cannot be
executed.
(6)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (32)
DATA IN: Data (1)
Data (32)
Data register
Data register
Page 0
Page 1
Page 2
Page 0
Page 1
Page 2
(1)
(2)
(3)
(2)
(16)
(3)
Page 15
Page 31
Page 15
(16)
(32)
(1)
Page 31
(32)
Figure 15. page programming within a block
(7)
Status Read during a Read operation
00
[A]
command
CE
00
70
WE
RY/BY
RE
Status Read
Address N
command input
Status Read
Status output
Figure 16.
The device status can be read out by inputting the Status Read command “70h” in Read mode.
Once the device has been set to Status Read mode by a “70h” command, the device will not return to Read
mode.
Therefore, a Status Read during a Read operation is prohibited.
However, when the Read command “00h” is input during [A], Status mode is reset and the device returns
to Read mode. In this case, data output starts automatically from address N and address input is
unnecessary.
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TC58DVG02A5TAI0
(8)
Pointer control for “00h”, “01h” and “50h”
The device has three Read modes which set the destination of the pointer. Table 7 shows the destination of
the pointer, and Figure 17 is a block diagram of their operations.
Table 7. Pointer Destination
Pointer
0
255 256
511 512 527
C
Read Mode
Command
A
B
(1)
(2)
(3)
00h
01h
50h
0 to 255
256 to 511
512 to 527
(1) 00h
Pointer control
(2) 01h
(3) 50h
Figure 17 Pointer control
The pointer is set to region A by the “00h” command, to region B by the “01h” command, and to region C by
the “50h” command.
(Example)
The “00h” command must be input to set the pointer back to region A when the pointer is pointing to
region C.
00h
50h
01h
50h
00h
Add
Add
Add
Start point
A area
Add
Add
Add
Start point
A area
Add
Add
Start point
C area
Start point
C area
Start point
C area
Start point
A area
Start point
B area
Start point
A area
To program region C only, set the start point to region C using the 50h command.
50h
80h
10h
Add
Add
DIN
Start point
C Area
Programming region C only
Programming region B and C
01h
80h
10h
DIN
Start point
B Area
Figure 18. Example of How to Set the Pointer
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TC58DVG02A5TAI0
(9)
RY/BY : termination for the Ready/Busy pin ( RY/BY )
A pull-up resistor needs to be used for termination because the RY/BY buffer consists of an open drain
circuit.
V
CC
Ready
V
CC
R
Device
Busy
RY/BY
C
L
t
f
t
r
V
SS
V
= 3.3 V
CC
Ta = 25°C
= 100 pF
1.5 μs
1.0 μs
0.5 μs
15 ns
10 ns
5 ns
Figure 19.
C
L
t
f
t
r
t
f
t
r
This data may vary from device to device.
We recommend that you use this data as a reference
when selecting a resistor value.
0
1 kΩ
2 kΩ
3 kΩ
4 kΩ
R
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TC58DVG02A5TAI0
(10)
Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:
Enable Programming
WE
DIN
WP
80
10
10
D0
D0
RY/BY
t
(100 ns min)
WW
Disable Programming
WE
DIN
80
WP
RY/BY
t
(100 ns min)
WW
Enable Erasing
WE
DIN
60
WP
RY/BY
t
(100 ns min)
WW
Disable Erasing
WE
DIN
60
WP
RY/BY
t
(100 ns min)
WW
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(11)
When five address cycles are input
Although the device may read in a fifth address, it is ignored inside the chip.
Read operation
CLE
CE
WE
ALE
I/O
00h, 01h or 50h
Address input
ignored
RY/BY
Internal read operation starts when WE goes High in the fourth cycle.
Figure 20.
Program operation
CLE
CE
WE
ALE
I/O
80h
Address input
Data input
ignored
Figure 21.
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TC58DVG02A5TAI0
(12)
Several programming cycles on the same page (Partial Page Program)
A page can be divided into up to 3 segments. Each segment can be programmed individually as follows:
1st programming
2nd programming
3rd programming
Result
All 1 s
Data Pattern 1
All 1 s
All 1 s
Data Pattern 2
All 1 s
Data Pattern 3
Data Pattern 3
Data Pattern 1
Data Pattern 2
Figure 22
Note: The input data for unprogrammed or previously programmed page segments must be “1”
(13)
Note regarding the RE signal
RE The internal column address counter is incremented synchronously with the RE clock in Read
mode. Therefore, once the device has been set to Read mode by a “00h”, “01h” or “50h” command, the
internal column address counter is incremented by the RE clock independently of the address input timing.
If the RE clock input pulses start before the address input, and the pointer reaches the last column
address, an internal read operation (array to register) will occur and the device will enter Busy state. (Refer
to Figure 23.)
Address input
I/O
WE
RE
00h/01h/50h
RY/BY
Figure 23.
Hence the RE clock input must start after the address input.
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(14)
Invalid blocks (bad blocks)
The device contains unusable blocks. Therefore, at the time of use, please check whether a block is bad
and do not use these bad blocks.
At the time of shipment, all data bytes in a Valid Block are FFh. For Bad
Block, all bytes are not in the FFh state. Please don’t perform erase
operation to Bad Block.
Bad Block
Check if the device has any bad blocks after installation into the system.
Figure 25 shows the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
A bad block does not affect the performance of good blocks because it is
isolated from the Bit line by the Select gate
Bad Block
Figure 24
The number of valid blocks over the device lifetime is as follows:
MIN
TYP.
MAX
8192
UNIT
Block
Valid (Good) Block Number
8032
⎯
Bad Block Test Flow
Read Check: Read column 517 of the 1st page
in the block. If the column is not
FFh , define the block as a bad
block.
Start
Block No = 1
Fail
Read Check
Pass
Bad Block *1
Block No. = Block No. + 1
No
Block No. = 8192
Yes
End
*1: No erase operation is allowed to detected bad blocks
Figure 25
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(15)
Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE
Erase Failure
DETECTION AND COUNTERMEASURE SEQUENCE
Status Read after Erase → Block Replacement
Block
Page
Programming
Failure
Status Read after Program → Block Replacement
Programming
Failure
Single Bit
ECC
1 → 0
•
•
ECC: Error Correction Code.1 bit correction per 512 Bytes is necessary.
Block Replacement
Program
Error occurs
When an error happens in Block A, try to
reprogram the data into another Block (Block
B) by loading from an external buffer. Then,
prevent further system accesses to Block A (by
creating a bad block table or by using an
another appropriate scheme).
Buffer
memory
Block A
Block B
Figure 26.
Erase
When an error occurs in an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).
(16)
Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.
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(17)
Reliability Guidance
This reliability guidance is intended to notify some guidance related to using NAND flash with
1 bit ECC for each 512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note.
Although random bit errors may occur during use, it does not necessarily mean that a block is bad.
Generally, a block should be marked as bad when a program status failure or erase status failure is detected.
The other failure modes may be recovered by a block erase.
ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.
•
•
Write/Erase Endurance
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read
after either an auto program or auto block erase operation. The cumulative bad block count will increase
along with the number of write/erase cycles.
Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge
gain. After block erasure and reprogramming, the block may become usable again.
Here is the combined characteristics image of Write/Erase Endurance and Data Retention.
Data
Retention
[Years]
Write/Erase Endurance [Cycles]
•
Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit
errors occur on other pages in the block, not the page being read. After a large number of read cycles
(between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another
state. After block erasure and reprogramming, the block may become usable again.
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Package Dimensions
Weight: 0.53 g (typ.)
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Revision History
Date
Rev.
1.00
1.01
1.02
Description
Original version
Described ECC as 1 bit correction per 512 Bytes.
2009-11-24
2010-04-23
2010-07-13
Deleted TENTATIVE notation.
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RESTRICTIONS ON PRODUCT USE
•
•
•
Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively “Product”) without notice.
This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.
Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.
•
Product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring
equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document.
Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or
reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious
public impact (“Unintended Use”). Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used
in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling
equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric
power, and equipment used in finance-related fields. Do not use Product for Unintended Use unless specifically permitted in this
document.
•
•
Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
•
•
The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR
LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND
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FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
•
Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product
or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations.
•
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Product is subject to foreign exchange and foreign trade control laws.
Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
38
2010-07-13
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