TC58FVT160AFT-10 [TOSHIBA]
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS; 东芝MOS数字集成电路硅栅CMOS
| 型号： | TC58FVT160AFT-10 |
| 厂家： | 
TOSHIBA |
| 描述： | TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| 文件： | 总41页 (文件大小：539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC58FVT160/B160AFT/AXB-70,-10
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
16-MBIT (2M × 8 BITS / 1M × 16 BITS) CMOS FLASH MEMORY
DESCRIPTION
The TC58FVT160/B160A is a 16,777,216-bit, 3.0-V read-only electrically erasable and programmable flash
memory organized as 2,097,152 words × 8 bits or as 1,048,576 words × 16 bits. The TC58FVT160/B160A features
commands for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands
are based on the JEDEC standard. The Program and Erase operations are automatically executed in the chip.
FEATURES
•
•
Block erase architecture
•
•
•
•
Power supply voltage
1 × 16 Kbytes / 2 × 8 Kbytes
1 × 32 Kbytes / 31 × 64 Kbytes
Boot block architecture
V
DD
= 2.7 V~3.6 V
Operating temperature
Ta = −40°C~85°C
TC58FVT160AFT/AXB: top boot block
TC58FVB160AFT/AXB: bottom boot block
Mode control
Organization
2M × 8 bits / 1M × 16 bits
Functions
•
•
•
Compatible with JEDEC standard commands
Erase/Program cycles
Auto Program, Auto Erase
Fast Program Mode
5
10 cycles typ.
Program Suspend/Resume
Erase Suspend/Resume
data polling / Toggle bit
block protection
Access time
70 ns
(C : 30 pF)
L
100 ns
(C : 100 pF)
L
•
•
Power consumption
Automatic Sleep, support for hidden ROM area
common flash memory interface (CFI)
Byte/Word Modes
5 µA
30 mA
15 mA
Package
(Standby)
(Read operation)
(Program/Erase operations)
TC58FVT160/B160AFT:
TSOPI48-P-1220-0.50 (weight: 0.51 g)
TC58FVT160/B160AXB:
P-TFBGA48-0608-0.80AZ (weight: 0.090 g)
000630EBA1
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba products listed in this document
shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.
2002-08-06 1/41
TC58FVT160/B160AFT/AXB-70,-10
PIN ASSIGNMENT (TOP VIEW)
…TC58FVT160/B160AFT
PIN NAMES
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
A-1, A0~A19 Address Input
2
BYTE
3
VSS
DQ0~DQ15 Data Input/Output
4
DQ15/A-1
DQ7
5
CE
OE
Chip Enable Input
Output Enable Input
Word/Byte Select Input
Write Enable Input
Ready/Busy Output
Hardware Reset Input
Not Connected
6
DQ14
DQ6
7
A8
8
DQ13
DQ5
BYTE
WE
A19
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
WE
VDD
RESET
RY/BY
RESET
NC
NC
DQ11
DQ3
NC
DQ10
DQ2
RY/BY
A18
A17
A7
DQ9
V
Power Supply
DQ1
DD
A6
DQ8
V
Ground
SS
A5
DQ0
A4
OE
A3
VSS
A2
CE
A0
A1
PIN ASSIGNMENT (TOP VIEW)…TC58FVT160/B160AXB
1
2
3
4
5
6
A
B
C
D
E
F
A3
A4
A2
A1
A0
CΕ
OE
A7
A17
A6
RY/BY
NC
WE
RESET
NC
A9
A8
A13
A12
A18
A10
A14
A5
NC
A19
A11
A15
DQ0
DQ8
DQ9
DQ1
DQ2
DQ10
DQ11
DQ3
DQ5
DQ7
DQ14
DQ13
DQ6
A16
DQ12
BYTE
DQ15
G
H
V
DD
V
DQ4
V
SS
SS
2002-08-06 2/41
TC58FVT160/B160AFT/AXB-70,-10
BLOCK DIAGRAM
RY /BY
DQ0
DQ15
V
DD
RY /BY
Buffer
V
SS
I/O Buffer
WE
Auto Sequence
Control Circuit
Control Circuit
t
OEHP
Command
Register
RESET
Program Erase
Circuit
Circuit
Data Latch
CE
OE
CE , OE
Control Circuit
Column Decoder & Sense Amp
A0
Memory Cell Array
A19
A-1
Erase Block Decoder
2002-08-06 3/41
TC58FVT160/B160AFT/AXB-70,-10
MODE SELECTION
BYTE MODE
WORD MODE
DQ0~DQ15
(1)
MODE
Read
CE OE WE A9
A6
A6
L
A1
A1
L
A0 RESET
DQ0~DQ7
L
L
L
H
*
L
L
H
H
H
*
A9
A0
L
H
H
H
H
*
D
D
OUT
OUT
ID Read (Manufacturer Code)
ID Read (Device Code)
Standby
V
V
Code
Code
Code
Code
ID
ID
L
L
L
H
*
*
*
*
*
High-Z
High-Z
High-Z
High-Z
Output Disable
H
H
H
*
*
*
*
(2)
Write
L
L
L
*
A9
A6
L
A1
H
H
*
A0
L
H
H
H
D
D
IN
IN
(2)
Block Protect 1
V
V
V
*
*
ID
ID
ID
Verify Block Protect
Temporary Block Unprotect
Hardware Reset / Standby
L
*
*
H
*
L
L
Code
*
Code
*
*
*
*
V
ID
*
*
*
*
*
*
L
High-Z
High-Z
Notes: * = V or V , L = V , H = V
IH
IL
IL
IH
(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.
Addresses are A19~A0 in Word Mode (BYTE = V ), A19~A-1 in Byte Mode (BYTE = V ).
IH
IL
(2) Pulse input
ID CODE TABLE
(1)
CODE TYPE
A19~A12
A6
L
A1
L
A0
CODE (HEX)
Manufacturer Code
Device Code
*
*
*
L
H
H
L
0098H
TC58FVT160A
TC58FVB160A
L
L
00C2H
L
L
0043H
(2)
(3)
Verify Block Protect
BA
L
H
Data
Notes: * = V or V , L = V , H = V
IH
IH
IL
IL
(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.
(2) BA: Block Address
(3) 0001H - Protected Block
0000H - Unprotected Block
2002-08-06 4/41
TC58FVT160/B160AFT/AXB-70,-10
COMMAND SEQUENCES
BUS
FIRST BUS
WRITE CYCLE
SECOND BUS
WRITE CYCLE
THIRD BUS
FOURTH BUS
WRITE CYCLE
FIFTH BUS
SIXTH BUS
COMMAND
SEQUENCE
WRITE
CYCLES
REQ’D
WRITE CYCLE
WRITE CYCLE
WRITE CYCLE
Addr.
Data
F0H
Addr.
Data
Addr.
Data Addr.
Data
Addr.
Data
Addr.
Data
Read/Reset
1
3
XXXH
555H
AAAH
555H
AAAH
555H
AAAH
Word
Byte
Word
Byte
Word
Byte
2AAH
555H
2AAH
555H
2AAH
555H
555H
AAAH
555H
AAAH
555H
AAAH
(1)
(2)
Read/Reset
ID Read
AAH
AAH
AAH
55H
55H
55H
F0H RA
RD
(3)
(4)
3
4
90H
IA
ID
(5)
(6)
Auto-Program
A0H PA
PD
V
IH or
Program Suspend
Program Resume
1
1
6
B0H
30H
AAH
VIL
VIH or
VIL
Word
555H
AAAH
555H
AAAH
2AAH
555H
2AAH
555H
555H
AAAH
555H
AAAH
555H
2AAH
555H
2AAH
555H
555H
Auto Chip
Erase
55H
55H
80H
80H
AAH
AAH
55H
55H
10H
30H
Byte
Word
Byte
AAAH
555H
AAAH
Auto Block
Erase
(7)
6
1
AAH
BA
AAAH
VIH or
VIL
Block Erase Suspend
B0H
30H
VIH or
VIL
Block Erase Resume
Block Protect 2
1
4
(8)
(8)
(9)
XXXH
555H
AAAH
555H
AAAH
XXXH
XXXH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
55H
60H BPA
60H
55H
XXXH 40H BPA
BPD
BPD
Word
Byte
Word
Byte
2AAH
555H
90H BPA
AAAH
Verify Block
Protect
(8)
(9)
3
3
AAH
AAH
555H
2AAH
555H
555H
20H
AAAH
Fast Program
Set
55H
(5)
(6)
Fast Program
2
2
A0H
90H
PA
PD
(12)
Fast Program Reset
XXXH F0H
2AAH
Word
555H
88H
AAAH
Hidden ROM
Mode Entry
3
4
6
4
2
AAH
AAH
AAH
AAH
98H
55H
Byte
Word
Byte
555H
2AAH
555H
2AAH
555H
2AAH
555H
555H
Hidden ROM
Program
(5)
(6)
55H
A0H PA
PD
AAAH
555H
AAAH
555H
AAAH
Word
Byte
555H
2AAH
555H
Hidden ROM
Erase
(7)
55H
55H
80H
AAH
00H
55H
BA
30H
AAAH
Word
Byte
Hidden ROM
Mode Exit
90H XXXH
Word
Byte
Query
(10)
CA
(11)
CD
Command
AAH
Notes: The system should generate the following address patterns:
Word Mode: 555H or 2AAH on address pins A10~A0
Byte Mode: AAAH or 555H on address pins A10~A-1
DQ8~DQ15 are ignored in Word Mode.
(1) RA: Read Address
(7) BA:Block Address = A19~A12
(2) RD: Read Data
(8) BPA: Block Address and ID Read Address (A6, A1, A0)
(3) IA: ID Read Address (A6, A1, A0)
Block Address = A19~A12
Manufacturer Code = (0, 0, 0)
Device Code = (0, 0, 1)
ID Read Address = (0, 1, 0)
(9) BPD:Verify Data
(4) ID: ID Data
(10) CA:CFI Address
(5) PA: Program Address
(11) CD:CFI Data
(6) PD: Program Data
(12) F0H: 00H is valid too
2002-08-06 5/41
TC58FVT160/B160AFT/AXB-70,-10
OPERATION MODES
In addition to the Read, Write and Erase Modes, the TC58FVT160/B160A features many functions including block
protection and data polling. When incorporating the device into a deign, please refer to the timing charts and
flowcharts in combination with the description below.
READ MODE
To read data from the memory cell array, set the device to Read Mode. In Read Mode the device can perform
high-speed random access as asynchronous ROM.
The device is automatically set to Read Mode immediately after power-on or on completion of automatic
operation. A software reset releases ID Read Mode and the lock state which the device enters if automatic
operation ends abnormally, and sets the device to Read Mode. A hardware reset terminates operation of the
device and resets it to Read Mode. When reading data without changing the address immediately after power-on,
either input a hardware Reset or change CE from H to L.
ID Read Mode
ID Read Mode is used to read the device maker code and device code. The mode is useful in that it allows
EPROM programmers to identify the device type automatically.
ID read can be executed in two ways, as follows:
(1) Applying V to A9
ID
This method is used mainly by EPROM programmers. Applying V to A9 sets the device to ID Read Mode,
ID
outputting the maker code from address 00H and the device code from address 01H. Releasing V from A9
ID
returns the device to Read Mode.
(2) Input command sequence
Inputting an ID Read command sets to ID Read Mode. The maker code is output from address 00; the
device code is output from address 01. Inputting a Reset command releases ID Read Mode and returns the
device to Read Mode.
Access time in ID Read Mode is the same as that in Read Mode. For a list of the codes, please refer to the
ID Code Table.
Standby Mode
There are two ways to put the device into Standby Mode.
(1) Control using CE and RESET
With the device in Read Mode, input V
0.3 V to CE and RESET . The device will enter Standby
DD
Mode and the current will be reduced to the standby current (I
(2) Control using RESET only
).
DDS1
With the device in Read Mode, input V
0.3 V to RESET . The device will enter Standby Mode and the
SS
current will be reduced to the standby current (I
).
DDS1
In Standby Mode DQ is put in High-Impedance state.
Auto-Sleep Mode
This function suppresses power dissipation during reading. If the address input does not change for 150 ns, the
device will automatically enter Sleep Mode and the current will be reduced to the standby current (I
).
DDS2
Because the output data is latched, data is output in Sleep Mode. When the address is changed, Sleep Mode is
automatically released, and data from the new address is output.
2002-08-06 6/41
TC58FVT160/B160AFT/AXB-70,-10
Output Disable Mode
Inputting V to OE disables output from the device and sets DQ to High-Impedance.
IH
Command Write
2
The TC58FVT160/B160A uses the standard JEDEC control commands for a single-power supply E PROM. A
Command Write is executed by inputting the address and data into the Command Register. The command is
written by inputting a pulse to WE with CE = V and OE = V ( WE control). The command can also be
IL
IH
written by inputting a pulse to CE with WE = V (CE control). The address is latched on the falling edge of
IL
either WE or CE . The data is latched on the rising edge of either WE or CE . DQ0~DQ7 are valid for data
input and DQ8~DQ15 are ignored.
To abort input of the command sequence use the Reset command. The device will reset the Command Register
and enter Read Mode. If an undefined command is input, the Command Register will be reset and the device will
enter Read Mode.
Software Reset
Apply a software reset by inputting a Read/Reset command. A software reset returns the device from ID Read
Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and clears
the Command Register.
Hardware Reset
A hardware reset initializes the device and sets it to Read Mode. When a pulse is input to RESET for t , the
RP
device abandons the operation which is in progress and enters Read Mode after t
. Note that if a hardware
READY
reset is applied during data overwriting, such as a Write or Erase operation, data at the address or block being
written to at the time of the reset will become undefined.
After a hardware reset the device enters Read Mode if RESET = V or Standby Mode if RESET = V . The
IH
IL
DQ pins are High-Impedance when RESET = V . After the device has entered Read Mode, Read operations
IL
and input of any command are allowed.
Comparison between Software Reset and Hardware Reset
ACTION
SOFTWARE RESET
HARDWARE RESET
Releases ID Read Mode or CFI Mode.
True
True
True
False
True
True
True
True
Clears the Command Register.
Releases the lock state if automatic operation has ended abnormally.
Stops any automatic operation which is in progress.
Stops any operation other than the above and returns the device to
Read Mode.
False
True
BYTE/Word Mode
BYTE is used select Word Mode (16 bits) or Byte Mode (8 bits) for the TC58FVT160/B160A. If V is input to
IH
BYTE , the device will operate in Word Mode. Read data or write commands using DQ0~DQ15. When V is
IL
input to BYTE , read data or write commands using DQ0~DQ7. DQ15/A-1 is used as the lowest address.
DQ8~DQ14 will become High-Impedance.
2002-08-06 7/41
TC58FVT160/B160AFT/AXB-70,-10
Auto-Program Mode
The TC58FVT160/B160A can be programmed in either byte or word units. Auto-Program Mode is set using the
Program command. The program address is latched on the falling edge of the WE signal and data is latched on
the rising edge of the fourth Bus Write cycle (with WE control). Auto programming starts on the rising edge of
the WE signal in the fourth Bus Write cycle. The Program and Program Verify commands are automatically
executed by the chip. The device status during programming is indicated by the Hardware Sequence flag. To read
the Hardware Sequence flag, specify the address to which the Write is being performed.
During Auto-Program execution, a command sequence cannot be accepted. To terminate execution, use a
hardware reset. Note that if the Auto-Program operation is terminated in this manner, the data written so far is
invalid.
Any attempt to program a protected block is ignored. In this case the device enters Read Mode 3 µs after the
rising edge of the WE signal in the fourth Bus Write cycle.
If an Auto-Program operation fails, the device remains in the programming state and does not automatically
return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or
a hardware reset is required to return the device to Read Mode after a failure. If a programming operation fails,
the block which contains the address to which data could not be programmed should not be used.
The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into
cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device
error. A cell containing 0 must be erased in order to set it to 1.
Fast Program Mode
Fast Program is a function which enables execution of the command sequence for the Auto Program to be
completed in two cycles. In this mode the first two cycles of the command sequence, which normally requires four
cycles, are omitted. Writing is performed in the remaining two cycles. To execute Fast Program, input the Fast
Program command. Write in this mode uses the Fast Program command but operation is the same at that for
ordinary Auto-Program. The status of the device is indicated by the Hardware Sequence flag and read operations
can be performed as usual. To exit this mode, the Fast Program Reset command must be input. When the
command is input, the device will return to Read Mode.
Program Suspend/Resume Mode
Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a
Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but
ignores the command in other modes. After input of the command, the device will enter Program Suspend Read
Mode after t
SUSP
.
During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write is
suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are
the same as usual.
After completion of Program Suspend input a Program Resume command to return to Write Mode. On
receiving the Resume command, the device returns to Write Mode and resumes outputting the Hardware
Sequence flag for the bank to which data is being written.
Program Suspend can be run in Fast Program Mode.
2002-08-06 8/41
TC58FVT160/B160AFT/AXB-70,-10
Auto Chip Erase Mode
The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the
rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and
verified as erased by the chip. The device status is indicated by the Hardware Sequence flag.
Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase
operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence an additional
Erase operation must be performed.
Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not
be executed and the device will enter Read mode 100 µs after the rising edge of the WE signal in the sixth bus
cycle.
If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to Read
Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware
reset is required to return the device to Read Mode after a failure.
In this case it cannot be ascertained which block the failure occurred in. Either abandon use of the device
altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host processor
must take measures to prevent subsequent use of the failed block.
Auto Block Erase / Auto Multi-Block Erase Modes
The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The
block address is latched on the falling edge of the WE signal in the sixth bus cycle. The block erase starts as
soon as the Erase Hold Time (t
BEH
) has elapsed after the rising edge of the WE signal. When multiple blocks
are erased, the sixth Bus Write cycle is repeated with each block address and Auto Block Erase command being
input within the Erase Hold Time (this constitutes an Auto Multi-Block Erase operation). If a command other
than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time, the device
will reset the Command Register and enter Read Mode. The Erase Hold Time restarts on each successive rising
edge of WE . Once operation starts, all memory cells in the selected block are automatically preprogrammed to 0,
erased and verified as erased by the chip. The device status is indicated by the setting of the Hardware Sequence
flag. When the Hardware Sequence flag is read, the addresses of the blocks on which auto-erase operation is
being performed must be specified.
All commands (except Erase Suspend) are ignored during an Auto Block Erase or Auto Multi-Block Erase
operation. Either operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it
cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing.
Any attempt to erase a protected block is ignored. If all the selected blocks are protected, the auto-erase
operation is not executed and the device returns to Read Mode 100 µs after the rising edge of the WE signal in
the last bus cycle.
If an auto-erase operation fails, the device remains in Erasing state and does not return to Read Mode. The
device status is indicated by the Hardware Sequence flag. After a failure either a Reset command or a Hardware
Reset is required to return the device to Read Mode. If multiple blocks are selected, it will not be possible to
ascertain the block in which the failure occurred. In this case either abandon use of the device altogether, or
perform a Block Erase on each block, identify the failed block, and stop using it. The host processor must take
measures to prevent subsequent use of the failed block.
2002-08-06 9/41
TC58FVT160/B160AFT/AXB-70,-10
Erase Suspend / Erase Resume Modes
Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block.
The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other oreration
modes .
In Erase Suspend Mode only a Read, Program or Resume command can be accepted. If an Erase Suspend
command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after t
. The
SUSE
device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is
read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output
will stop toggling and RY/BY will be set to High-Impedance.
Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has not
been selected for the Auto Block Erase. Data is written in the usual manner.
To resume the Auto Block Erase, input an Erase Resume command. On receiving an Erase Resume command,
the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend
command is input during the Erase Hold Time, the device will return to the state it was in at the start of the
Erase Hold Time. At this time more blocks can be specified for erasing. If an Erase Resume command is input
during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on
RY/BY .
Block Protection
Block Protection is a function for disabling writing and erasing specific blocks. Block protection can be carried
out in two ways: by supplying a high voltage (V ) to the device (see Block protection 1) or by supplying a high
ID
voltage and a command sequence (see Block protection 2).
(1) Block protection 1
Specify a device block address and make the following signal settings A9 = OE = V , A1 = V and CE
ID
IH
= A0 = A6 = V . Now when a pulse is input to WE for t
, the device will start to write to the block
IL
PPLH
protection circuit. Block protection can be verified using the Verify Block Protect command. Inputting V on
IL
OE sets the device to Verify Mode. 01H is output if the block is protected and 00H is output if the block is
unprotected. If block protection was unsuccessful, the operation must be repeated. Releasing V from A9
ID
and OE terminates this mode.
(2) Block protection 2
Applying V to RESET and inputting the Block Protect 2 command also performs block protection. The
ID
first cycle of the command sequence is the Set-up command. In the second cycle, the Block Protect command
is input, in which a block address and A1 = V and A0 = A6 = V are input. Now the device writes to the
IH
IL
block protection circuit. There is a wait of t
until this write is completed; however, no intervention is
PPLH
necessary during this time. In the third cycle the Verify Block Protect command is input. This command
verifies the write to the block protection circuit. Read is performed in the fourth cycle. If the protection
operation is complete, 01H is output. If a value other than 01H is output, block protection is not complete
and the Block Protect command must be input again. Removing the V input from RESET exits this
ID
mode.
Temporary Block Unprotection
The TC58FVT160/B160A has a temporary block unprotection feature which disables block protection for all
protected blocks. Unprotection is enabled by applying V to the RESET pin. Now Write and Erase operations
ID
can be performed on all blocks. The device returns to its previous state when V is removed from the RESET
ID
pin. That is, previously protected blocks will be protected again.
Verify Block Protect
The Verify Block Protect command is used to ascertain whether a block is protected or unprotected.
Verification is performed either by inputting the Verify Block Protect command or by applying V to the A9 pin,
ID
as for ID Read Mode, and setting the block address = A0 = A6 = V and A1 = V . If the block is protected, 01H is
IL IH
output. If the block is unprotected, 00H is output.
2002-08-06 10/41
TC58FVT160/B160AFT/AXB-70,-10
Hidden ROM Area
The TC58FVT160/B160A features a 64-Kbyte hidden ROM area which is separate from the memory cells. The
area consists of one block. Data Read, Write and Protect can be performed on this block. Because Protect cannot
be released, once the block is protected, data in the block cannot be overwritten.
The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS
TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters
Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations
are the same as auto operations except that the device is in Hidden ROM Mode. To protect the hidden ROM area,
use the block protection function. The operation of Block Protect here is the same as a normal Block Protect
except that V rather than V is input to RESET . Once the block has been protected, protection cannot be
IH
ID
released, even using the temporary block unprotection function. Use Block Protect carefully.
To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read
Mode.
HIDDEN ROM AREA ADDRESS TABLE
BYTE MODE
ADDRESS RANGE
WORD MODE
ADDRESS RANGE
BOOT BLOCK
ARCHITECTURE
TYPE
SIZE
SIZE
TC58FVT160A
TOP BOOT BLOCK
1F0000H~1FFFFFH
000000H~00FFFFH
64 Kbytes
64 Kbytes
F8000H~FFFFFH
32 Kwords
32 Kwords
TC58FVB160A BOTTOM BOOT BLOCK
000000H~007FFFH
2002-08-06 11/41
TC58FVT160/B160AFT/AXB-70,-10
COMMON FLASH MEMORY INTERFACE (CFI)
The TC58FVT160/B160A conforms to the CFI specifications. To read information from the device, input the
Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input the
Reset command.
CFI CODE TABLE
ADDRESS A6~A0
DATA DQ15~DQ0
DESCRIPTION
10H
11H
12H
0051H
0052H
0059H
ASCII string “QRY”
13H
14H
0002H
0000H
Primary OEM command set
2: AMD/FJ standard type
15H
16H
0040H
0000H
Address for primary extended table
17H
18H
0000H
0000H
Alternate OEM command set
0: none exists
19H
1AH
0000H
0000H
Address for alternate OEM extended table
V
(min) (Write/Erase)
DD
1BH
1CH
0027H
0036H
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
V
(max) (Write/Erase)
DD
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
0000H
0000H
0004H
0000H
000AH
0000H
0005H
0000H
0004H
0000H
0015H
V
V
(min) voltage
(max) voltage
PP
PP
N
Typical time-out per single byte/word write (2 µs)
N
Typical time-out for minimum size buffer write (2 µs)
N
Typical time-out per individual block erase (2 ms)
N
Typical time-out for full chip erase (2 ms)
N
Maximum time-out for byte/word write (2 times typical)
N
Maximum time-out for buffer write (2 times typical)
N
Maximum time-out per individual block erase (2 times typical)
N
Maximum time-out for full chip erase (2 times typical)
N
Device Size (2 byte)
28H
29H
0002H
0000H
Flash device interface description
2: ×8/×16
2AH
2BH
0000H
0000H
N
Maximum number of bytes in multi-byte write (2 )
2002-08-06 12/41
TC58FVT160/B160AFT/AXB-70,-10
ADDRESS A6~A0
2CH
DATA DQ15~DQ0
0004H
DESCRIPTION
Number of erase block regions within device
2DH
2EH
2FH
30H
0000H
0000H
0040H
0000H
Erase Block Region 1 information
Bits 0~15: y = block number
Bits 16~31: z = block size
(z × 256 bytes)
31H
32H
33H
34H
0001H
0000H
0020H
0000H
Erase Block Region 2 information
Erase Block Region 3 information
35H
36H
37H
38H
0000H
0000H
0080H
0000H
39H
3AH
3BH
3CH
001EH
0000H
0000H
0001H
Erase Block Region 4 information
40H
41H
42H
0050H
0052H
0049H
ASCII string “PRI”
43H
44H
0031H
0031H
Major version number, ASCII
Minor version number, ASCII
Address-Sensitive Unlock
0: Required
45H
46H
47H
0000H
0002H
0001H
1: Not required
Erase Suspend
0: Not supported
1: For Read-only
2: For Read & Write
Block Protect
0: Not supported
X: Number of blocks per group
Block Temporary Unprotect
0: Not supported
48H
49H
4AH
0001H
0004H
0000H
1: Supported
Block Protect/Unprotect scheme
Simultaneous operation
0: Not supported
1: Supported
Burst Mode
4BH
4CH
0000H
0000H
0: Not supported
Page Mode
0: Not supported
Top/Bottom Boot Block Flag
2: TC58FVB160
4FH
50H
000XH
0001H
3: TC58FVT160
Program suspend
0: Not supported
1: Supported
2002-08-06 13/41
TC58FVT160/B160AFT/AXB-70,-10
HARDWARE SEQUENCE FLAGS
The TC58FVT160A/B160A has a Hardware Sequence flag which allows the device status to be determined during
an auto mode operation. The output data is read out using the same timing as that used when CE = OE = V in
IL
Read Mode. The RY/BY output can be either High or Low.
The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The
Hardware Sequence flag is read to determine the device status and the result of the operation is verified by
comparing the read-out data with the original data.
STATUS
DQ7
DQ7
Data
0
DQ6
Toggle
Data
DQ5
DQ3
DQ2
1
RY/BY
Auto Programming
0
0
0
(1)
Read in Program Suspend
Data
Data
Data
Toggle
1
High-Z
(2)
Selected
Toggle
Toggle
Toggle
Toggle
1
0
0
0
0
0
Erase Hold Time
Auto Erase
Read
(3)
Not-selected
Selected
0
0
In Auto
Erase
0
0
1
Toggle
1
0
In Progress
Not-selected
Selected
0
0
1
0
1
0
0
Toggle
Data
Toggle
1
High-Z
Not-selected
Selected
Data
DQ7
DQ7
DQ7
0
Data
Data
0
Data
0
High-Z
In Erase
Suspend
Toggle
Toggle
Toggle
Toggle
Toggle
0
0
0
0
0
Programming
Not-selected
0
0
Auto Programming
Auto Erase
1
0
1
Time Limit
Exceeded
1
1
NA
Programming in Erase Suspend
DQ7
1
0
NA
Notes: DQ outputs cell data and RY/BY goes High-Impedence when the operation has been completed.
DQ0 and DQ1 pins are reserved for future use.
0 is output on DQ0, DQ1 and DQ4.
(1) Data output from an address to which Write is being performed is undefined.
(2) Output when the block address selected for Auto Block Erase is specified and data is read from there.
During Auto Chip Erase, all blocks are selected.
(3) Output when a block address not selected for Auto Block Erase and data is read from there.
DQ7 (DATA polling)
During an Auto-Program or auto-erase operation, the device status can be determined using the data polling
function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation,
DQ7 outputs inverted data during the programming operation and outputs actual data after programming has
finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase
operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data.
When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE signal.
2002-08-06 14/41
TC58FVT160/B160AFT/AXB-70,-10
DQ6 (Toggle bit 1)
The device status can be determined by the Toggle Bit function during an Auto-Program or auto-erase
operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately
outputs a 0 or a 1 for each OE access while CE = V while the device is busy. When the internal operation
IL
has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the
operation fails, the DQ6 output toggles.
If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around 3
µs. It will then stop toggling. If an attempt is made to execute an auto erase operation on a protected block, DQ6
will toggle for around 100 µs. It will then stop toggling. After toggling has stopped the device will return to Read
Mode.
DQ5 (internal time-out)
If the internal timer times out during a Program or Erase operation, DQ5 outputs a 1. This indicates that the
operation has not been completed within the allotted time.
Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case DQ5
outputs a 1. Either a hardware reset or a software Reset command is required to return the device to Read Mode.
DQ3 (Block Erase timer)
The Block Erase operation starts 50 µs (the Erase Hold Time) after the rising edge of WE in the last
command cycle. DQ3 outputs a 0 for the duration of the Block Erase Hold Time and a 1 when the Block Erase
operation starts. Additional Block Erase commands can only be accepted during the Block Erase Hold Time.
Each Block Erase command input within the hold time resets the timer, allowing additional blocks to be marked
for erasing. DQ3 outputs a 1 if the Program or Erase operation fails.
DQ2 (Toggle bit 2)
DQ2 is used to indicate which blocks have been selected for Auto Block Erase or to indicate whether the device
is in Erase Suspend Mode.
If data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle.
Now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. If data is read
continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ2
output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in Erase
Suspend Mode. If data is read from the address to which data is being written during Erase Suspend in
Programming Mode, DQ2 will output a 1.
RY/BY
BUSY
)
(READY/
The TC58FVT160A/B160A has a RY/BY signal to indicate the device status to the host processor. A 0 (Busy
state) indicates that an Auto-Program or auto-erase operation is in progress. A 1 (Ready state) indicates that the
operation has finished and that the device can now accept a new command. RY/BY outputs a 0 when an
operation has failed.
RY/BY outputs a 0 after the rising edge of WE in the last command cycle.
During an Auto Block Erase operation, commands other than Erase Suspend are ignored. RY/BY outputs a 1
during an Erase Suspend operation. The output buffer for the RY/BY pin is an open-drain type circuit,
allowing a wired-OR connection. A pull-up resistor must be inserted between V
and the RY/BY pin.
DD
2002-08-06 15/41
TC58FVT160/B160AFT/AXB-70,-10
DATA PROTECTION
The TC58FVT160/B160A includes a function which guards against malfunction or data corruption.
Protection against Program/Erase Caused by Low Supply Voltage
To prevent malfunction at power-on or power-down, the device will not accept commands while V
is below
DD
V
LKO
If V
. In this state, command input is ignored.
drops below V
LKO
during an Auto Operation, the device will terminate Auto-Program execution. In this
DD
case, Auto operation is not executed again when VDD return to recommended VDD voltage Therefore, command
need to be input to execute Auto operation again.
When VDD > VLKO, make up countermeasure to be input accurately command in system side please.
Protection against Malfunction Caused by Glitches
To prevent malfunction during operation caused by noise from the system, the device will not accept pulses
shorter than 3 ns (Typ.) input on WE , CE or OE . However, if a glitch exceeding 3 ns (Typ.) occurs and the
glitch is input to the device malfunction may occur.
The device uses standard JEDEC commands. It is conceivable that, in extreme cases, system noise may be
misinterpreted as part of a command sequence input and that the device will acknowledge it. Then, even if a
proper command is input, the device may not operate. To avoid this possibility, clear the Command Register
before command input. In an environment prone to system noise, Toshiba recommend input of a software or
hardware reset before command input.
Protection against Malfunction at Power-on
To prevent damage to data caused by sudden noise at power-on, when power is turned on with WE = CE =
V
IL
and OE = V , the device does not latch the command on the first rising edge of WE or CE . Instead, the
IL
device automatically Resets the Command Register and enters Read Mode.
2002-08-06 16/41
TC58FVT160/B160AFT/AXB-70,-10
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RANGE
UNIT
V
V
V
V
V
P
V
Supply Voltage
DD
−0.6~4.6
DD
Input Voltage
−0.6~V
−0.6~V
+ 0.5 (≤ 4.6)
V
IN
DD
DD
Input/Output Voltage
+ 0.5 (≤ 4.6)
V
DQ
Maximum Input Voltage for A9, OE and RESET
Power Dissipation
13.0
V
IDH
126
260
mW
°C
°C
°C
mA
D
T
T
T
Soldering Temperature (10 s)
Storage Temperature
SOLDER
STG
OPR
OSHORT
−55~150
−40~85
100
Operating Temperature
(1)
I
Output Short-Circuit Current
(1) Outputs should be shorted for no more than one second.
No more than one output should be shorted at a time.
CAPACITANCE (Ta = 25°C, f = 1 MHz)
TSOPI
SYMBOL
PARAMETER
CONDITION
= 0 V
MAX
UNIT
pF
C
C
C
Input Pin Capacitance
Output Pin Capacitance
Control Pin Capacitance
V
4
8
7
IN
IN
V
= 0 V
OUT
pF
OUT
IN2
V
= 0 V
pF
IN
This parameter is periodically sampled and is not tested for every device.
TFBGA
SYMBOL
PARAMETER
CONDITION
= 0 V
MAX
UNIT
pF
C
C
C
Input Pin Capacitance
Output Pin Capacitance
Control Pin Capacitance
V
4
8
7
IN
IN
V
= 0 V
OUT
pF
OUT
IN2
V
= 0 V
pF
IN
This parameter is periodically sampled and is not tested for every device.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
2.7
MAX
3.6
UNIT
V
V
V
V
V
V
Supply Voltage
DD
DD
(2)
Input High-Level Voltage
Input Low-Level Voltage
0.7 × V
V
+ 0.3
DD
IH
IL
DD
(1)
−0.3
11.4
0.2 × V
12.6
85
DD
(3)
High-Level Voltage for A9, OE and RESET
Operating Temperature
ID
Ta
−40
°C
(1) −2 V (pulse width of 20 ns max)
(2) +2 V (pulse width of 20 ns max)
(3) Do not apply V when the supply voltage is not within the device’s recommended operating voltage range.
ID
2002-08-06 17/41
TC58FVT160/B160AFT/AXB-70,-10
DC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITION
MIN
MAX
1
UNIT
I
I
Input Leakage Current
Output Leakage Current
0 V ≤ V ≤ V
LI
LO
IN
DD
µA
0 V ≤ V
≤ V
1
OUT
DD
I
I
I
= −0.1 mA
= −2.5 mA
= 4.0 mA
V
− 0.4
DD
OH
OH
OL
V
V
Output High Voltage
Output Low Voltage
OH
V
0.85 × V
DD
0.4
OL
V
= V /V , I
= 0 mA
IN
IH IL OUT
I
V
Average Read Current
30
DDO1
DD
t
= t
= 100 ns
CYCLE
RC
I
I
V
V
V
Average Program Current
Average Erase Current
Average Program-while-
V
V
= V /V , I
IH IL OUT
= 0 mA
= 0 mA
15
15
DDO2
DDO3
DD
DD
DD
IN
IN
mA
= V /V , I
IH IL OUT
I
I
I
I
V
= V /V , I = 0 mA
IH IL OUT
15
5
DDO4
DDS1
DDS2
ID
IN
Erase-Suspend Current
CE = RESET = V
or RESET = V
DD
V
Standby Current
DD
V
SS
V
Standby Current
V
V
= V
DD
IH
IL
DD
SS
µA
5
(1)
(Automatic Sleep Mode
)
= V
High-Voltage Input Current for
A9, OE and RESET
11.4 V ≤ V ≤ 12.6 V
35
ID
V
Low-V
Lock-out Voltage
DD
2.3
2.5
V
LKO
(1) The device enters Automatic Sleep Mode in which the address remains fixed for during 150 ns.
AC TEST CONDITIONS
PARAMETER
CONDITION
, 0.0 V
Input Pulse Level
V
DD
Input Pulse Rise and Fall Time (10%~90%)
Timing Measurement Reference Level (input)
Timing Measurement Reference Level (output)
Output Load
5 ns
1.5 V, 1.5 V
1.5 V, 1.5 V
C (100 pF) + 1 TTL Gate
L
/
C (30 pF) + 1 TTL Gate
L
2002-08-06 18/41
TC58FVT160/B160AFT/AXB-70,-10
AC CHARACTERISTICS AND OPERATING CONDITIONS
READ CYCLE
PRODUCT NAME
−70
−10
OUTPUT CAPACITANCE LOAD (C )
L
30 pF
100 pF
SYMBOL
PARAMETER
MIN MAX MIN MAX MIN MAX UNIT
t
t
t
t
t
t
t
t
t
Read Cycle Time
70
0
70
70
30
20
20
80
0
80
80
35
25
25
100
0
100
100
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address Access Time
CE Access Time
ACC
CE
OE Access Time
OE
CE to Output Low-Z
OE to Output Low-Z
Output Data Hold Time
CE to Output High-Z
OE to Output High-Z
CEE
OEE
OH
0
0
0
0
0
0
30
DF1
DF2
30
BLOCK PROTECT
SYMBOL
PARAMETER
MIN
MAX
UNIT
t
t
t
t
t
V
V
Transition Time
Set-up Time
4
4
µs
µs
µs
µs
µs
VPT
ID
ID
VPS
CE Set-up Time
4
CESP
VPH
OE Hold Time
4
WE Low-Level Hold Time
100
PPLH
PROGRAM AND ERASE CHARACTERISTICS
SYMBOL
PARAMETER
Auto-Program Time (Byte Mode)
MIN
TYP.
8
MAX
300
300
350
10
UNIT
µs
µs
s
t
PPW
Auto-Program Time (Word Mode)
Auto Chip Erase Time
11
t
t
t
25
0.7
PCEW
PBEW
EW
Auto Block Erase Time
Erase/Program Cycle
s
5
10
Cycles
2002-08-06 19/41
TC58FVT160/B160AFT/AXB-70,-10
COMMAND WRITE/PROGRAM/ERASE CYCLE
−70
−10
SYMBOL
PARAMETER
UNIT
MIN
70
0
MAX
90
300
20
30
1.5
1
MIN
100
0
MAX
90
300
20
30
1.5
1
t
Command Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
µs
ns
ns
ns
ns
µs
µs
µs
µs
CMD
Address Set-up Time / BYTE Set-up Time
Address Hold Time / BYTE Hold Time
Address Hold Time from WE High level
Data Set-up Time
tAS
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
35
20
35
0
50
20
50
0
AH
AHW
DS
Data Hold Time
DH
WE Low-Level Hold Time
( WE Control)
( WE Control)
( WE Control)
( WE Control)
( CE Control)
( CE Control)
35
20
0
50
20
0
WELH
WEHH
CES
WE High-Level Hold Time
CE Set-up Time to WE Active
CE Hold Time from WE High Level
CE Low-Level Hold Time
0
0
CEH
CELH
CEHH
CHW
WES
WEH
OES
OEHP
OEHT
BEH
35
20
20
0
50
20
20
0
CE High-Level Hold Time
CE Hold Time from WE High Level
WE Set-up time to CE Active
WE Hold Time from CE High Level
OE Set-up Time
( CE Control)
( CE Control)
0
0
0
0
OE Hold Time (Toggle, Data Polling)
OE High-Level Hold Time (Toggle)
Erase Hold Time
90
20
50
500
500
0
90
20
50
500
500
0
V
Set-up Time
DD
VDS
Program/Erase Valid to RY/BY Delay
t
BUSY
Program/Erase Valid to RY/BY Delay during Suspend Mode
RESET Low-Level Hold Time
t
t
t
t
t
t
t
t
t
t
RP
RESET Low-Level to Read Mode
RY/BY Recovery Time
READY
RB
RESET Recovery Time
50
5
50
5
RH
CE Set-up time BYTE Transition
BYTE to Output High-Z
CEBTS
BTD
Program Suspend Command to Suspend Mode
Program Resume Command to Program Mode
Erase Suspend Command to Suspend Mode
Erase Resume Command to Erase Mode
SUSP
RESP
SUSE
RESE
15
1
15
1
2002-08-06 20/41
TC58FVT160/B160AFT/AXB-70,-10
TIMING DIAGRAMS
V
or V
Data invalid
IH
IL
Read / ID Read Operation
t
RC
Address
CE
t
t
OH
ACC
t
CE
t
t
t
OE
DF1
DF2
t
OEE
OE
t
t
CEE
AHW
t
OEH
WE
D
OUT
Hi-Z
Output data valid
Hi-Z
ID Read Operation (apply VID to A9)
t
RC
A0
A1
A6
t
ACC
V
V
ID
IH
t
VPS
A9
t
CE
CE
t
OE
OE
WE
Manufacturer
code
Device
code
D
OUT
Hi-Z
Hi-Z
Hi-Z
Read Mode
Read Mode
ID Read Mode
2002-08-06 21/41
TC58FVT160/B160AFT/AXB-70,-10
Command Write Operation
This is the timing of the Command Write Operation. The timing which is described in the following pages is
essentially the same as the timing shown on this page.
•
WE Control
t
CMD
Address
CE
Command address
t
t
AH
AS
t
t
CEH
CES
WE
t
WEHH
t
WELH
t
t
DH
DS
D
IN
Command data
•
CE Control
t
CMD
Address
CE
Command address
t
t
AH
AS
t
t
CEHH
CELH
t
t
WEH
WES
WE
t
t
DH
DS
D
IN
Command data
2002-08-06 22/41
TC58FVT160/B160AFT/AXB-70,-10
ID Read Operation (input command sequence)
Address
CE
555H
2AAH
555H
00H
01H
t
t
RC
CMD
OE
t
OES
WE
D
IN
AAH
90H
55H
Manufacturer code Device code
ID Read Mode
D
OUT
Hi-Z
Read Mode (input of ID Read command sequence)
(Continued)
Address
555H
2AAH
555H
t
CMD
CE
OE
WE
D
IN
AAH
F0H
55H
D
OUT
Hi-Z
ID Read Mode (input of Reset command sequence)
Read Mode
Note: Word Mode address shown.
2002-08-06 23/41
TC58FVT160/B160AFT/AXB-70,-10
WE
Auto-Program Operation (
Control)
Address
CE
555H
2AAH
555H
PA
PA
t
CMD
t
CHW
OE
t
OEHP
t
t
OES
PPW
WE
55H
A0H
PD
D
IN
AAH
D
OUT
Hi-Z
DQ7
D
OUT
t
VDS
V
DD
Note: Word Mode address shown.
PA: Program address
PD: Program data
WE
Auto Chip Erase / Auto Block Erase Operation (
Control)
Address
CE
555H
2AAH
555H
555H
2AAH
555H/BA
t
CMD
OE
t
OES
WE
D
IN
AAH
55H
80H
AAH
55H
10H/30H
t
VDS
V
DD
Note: Word Mode address shown.
BA: Block address for Auto Block Erase operation
2002-08-06 24/41
TC58FVT160/B160AFT/AXB-70,-10
CE
Auto-Program Operation (
Control)
Address
CE
555H
2AAH
555H
PA
PA
t
CMD
t
PPW
OE
t
OEHP
t
OES
WE
D
IN
55H
A0H
PD
AAH
D
OUT
Hi-Z
DQ7
D
OUT
t
VDS
V
DD
Note: Word Mode address shown.
PA: Program address
PD: Program data
CE
Auto Chip Erase / Auto Block Erase Operation (
Control)
Address
555H
2AAH
555H
555H
2AAH
555H/BA
t
CMD
CE
OE
t
OES
WE
D
IN
AAH
55H
80H
AAH
55H
10H/30H
t
VDS
V
DD
Note: Word Mode address shown.
BA: Block address for Auto Block Erase operation
2002-08-06 25/41
TC58FVT160/B160AFT/AXB-70,-10
Program/Erase Suspend Operation
Address
RA
CE
OE
WE
t
OE
D
IN
B0H
t
CE
D
OUT
Hi-Z
D
OUT
Hi-Z
t
/t
SUSP SUSE
RY/BY
Program/Erase Mode
RA: Read address
Suspend Mode
Program/Erase Resume Operation
Address
RA
PA/BA
CE
OE
t
t
/t
RESP RESE
OES
WE
t
DF1
t
t
OE
DF2
D
IN
30H
t
CE
D
OUT
D
OUT
Hi-Z
Flag
Hi-Z
RY/BY
Suspend Mode
Program/Erase Mode
PA: Program address
BA: Block address
RA: Read address
Flag: Hardware Sequence flag
2002-08-06 26/41
TC58FVT160/B160AFT/AXB-70,-10
RY/BY
during Auto Program/Erase Operation
CE
Command input sequence
WE
During operation
t
BUSY
RY /BY
Hardware Reset Operation
WE
t
RB
RESET
RY/BY
t
RP
t
READY
RESET
Read after
t
RC
Address
RESET
t
RH
t
t
OH
ACC
D
OUT
Hi-Z
Output data valid
2002-08-06 27/41
TC58FVT160/B160AFT/AXB-70,-10
BYTE
during Read Operation
CE
t
CEBTS
OE
BYTE
t
BTD
DQ0~DQ7
DQ8~DQ14
DQ15/A-1
Data Output
Data Output
Data Output
Data Output
t
ACC
Address Input
BYTE
during Write Operation
CE
WE
t
AS
BYTE
t
AH
2002-08-06 28/41
TC58FVT160/B160AFT/AXB-70,-10
DATA
Hardware Sequence Flag (
Polling)
Last
Address
CE
Command
PA/BA
Address
t
CMD
t
t
t
CE
DF1
DF2
t
OE
OE
t
OEHP
WE
t
/t
/t
t
t
OH
PPW PCEW PBEW
ACC
Last
D
IN
Command
Data
DQ7
DQ0~DQ6
RY/BY
DQ7
Valid
Valid
Valid
Invalid
Valid
t
BUSY
PA: Program address
BA: Block address
Hardware Sequence Flag (Toggle bit)
Last
Address
Command
PA/BA
Address
t
CMD
CE
t
t
CE
OEHT
OE
t
OEHP
WE
t
/t
/t
PPW PCEW PBEW
t
OE
Last
D
IN
Command
Data
Stop*
Toggle
DQ2/DQ6
RY/BY
Toggle
Toggle
Valid
t
BUSY
PA: Program address
BA: Block address
*DQ2/DQ6 stops toggling when auto operation has been completed.
2002-08-06 29/41
TC58FVT160/B160AFT/AXB-70,-10
Block Protect 1 Operation
Block Protect
Verify Block Protect
Address
A0
BA
A1
t
VPT
A6
V
V
ID
IH
A9
V
V
ID
IH
OE
t
VPS
t
VPH
t
PPLH
t
VPH
WE
t
t
OE
CESP
CE
D
OUT
Hi-Z
01H*
Hi-Z
BA: Block address
*: 01H indicates that block is protected.
2002-08-06 30/41
TC58FVT160/B160AFT/AXB-70,-10
Block Protect 2 Operation
Address
BA
BA
t
BA
BA + 1
t
t
t
RC
CMD
CMD
CMD
A0
A1
A6
CE
OE
t
PPLH
WE
t
VPS
V
V
ID
IH
RESET
D
60H
60H
Hi-Z
40H
60H
IN
t
OE
D
OUT
01H*
BA: Block address
BA + 1: Address of next block
*: 01H indicates that block is protected.
2002-08-06 31/41
TC58FVT160/B160AFT/AXB-70,-10
FLOWCHARTS
Auto Program
Start
Auto-Program Command Sequence
(see below)
DATA Polling or Toggle Bit
No
Last Address?
Address = Address + 1
Yes
Auto Program
Completed
Auto-Program Command Sequence (address/data)
555H/AAH
2AAH/55H
555H/A0H
Program Address/
Program Data
Note: The above command sequence takes place in Word Mode.
2002-08-06 32/41
TC58FVT160/B160AFT/AXB-70,-10
Fast Program
Start
Fast Program Set Command
Sequence (see below)
Fast Program Command Sequence
(see below)
DATA Polling or Toggle Bit
No
Last Address?
Yes
Address = Address + 1
Program Sequence
(see below)
Fast Program
Completed
Fast Program Set Command Sequence
(Address/Data)
Fast Program Command Sequence
(Address/Data)
Fast Program Reset Command Sequence
(Address/Data)
555H/AAH
2AAH/55H
555H/20H
XXXH/A0H
XXXH/90H
XXXH/F0H
Program Address/
Program Data
Note: The above command sequence takes place in word mode.
2002-08-06 33/41
TC58FVT160/B160AFT/AXB-70,-10
Auto Erase
Start
Auto Erase Command Sequence
(see below)
DATA Polling or Toggle Bit
Auto Erase
Completed
Auto Chip Erase Command Sequence
Auto Block / Auto-Multi Block Erase Command Sequence
(address/data)
(address/data)
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
555H/10H
555H/80H
555H/AAH
2AAH/55H
Block Address/30H
Block Address/30H
Additional address
inputs during
Auto Multi-Block Erase
Block Address/30H
Note: The above command sequence takes place in Word Mode.
2002-08-06 34/41
TC58FVT160/B160AFT/AXB-70,-10
DATA
DQ7
Polling
Start
Read Byte (DQ0~DQ7)
Addr. = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
1)
1) : DQ7 must be rechecked even if DQ5 = 1
because DQ7 may change at the same
time as DQ5.
Read Byte (DQ0~DQ7)
Addr. = VA
Yes
DQ7 = Data?
No
Fail
Pass
DQ6 Toggle Bit
Start
Read Byte (DQ0~DQ7)
Addr. = VA
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
1)
1) : DQ6 must be rechecked even if DQ5 = 1
because DQ6 may stop toggling at the
same time that DQ5 changes to 1.
Read Byte (DQ0~DQ7)
Addr. = VA
No
DQ6 = Toggle?
Yes
Fail
Pass
VA: Byte address for programming
Any of the addresses within the block being erased during a Block Erase operation
“Don’t care” during a Chip Erase operation
Any address not within the current block during an Erase Suspend operation
2002-08-06 35/41
TC58FVT160/B160AFT/AXB-70,-10
Block Protect 1
Start
PLSCNT = 1
Set up Block Address
Addr. = BPA
Wait for 4 µs
OE = A9 = V , CE = V
ID
IL
Wait for 4 µs
WE = V
IL
Wait for 100 µs
WE = V
PLSCNT = PLSCNT + 1
IH
Wait for 4 µs
OE = V
IH
Wait for 4 µs
OE = V
IL
Verify Block Protect
No
No
Data = 01H?
PLSCNT = 25?
Yes
Protect Another Block?
No
Yes
Yes
Device Failed
Remove V from A9
ID
Block Protect
Complete
BPA: Block Address and ID Read Address (A6, A1, A0)
ID Read Address = (0, 1, 0)
2002-08-06 36/41
TC58FVT160/B160AFT/AXB-70,-10
Block Protect 2
Start
RESET = V
ID
Wait for 4 µs
PLSCNT = 1
Block Protect 2
Command First Bus Write Cycle
(XXXH/60H)
Set up Address
Addr. = BPA
Block Protect 2
Command Second Bus Write Cycle
(BPA/60H)
Wait for 100 µs
Block Protect 2
Command Third Bus Write Cycle
(XXXH/40H)
PLSCNT = PLSCNT + 1
Verify Block Protect
No
PLSCNT = 25?
Yes
No
Data = 01H?
Yes
Protect Another Block?
No
Yes
Remove V from RESET
ID
Remove V from RESET
ID
Reset Command
Device Failed
Reset Command
Block Protect
Complete
BPA: Block Address and ID Read Address (A6, A1, A0)
ID Read Address = (0, 1, 0)
2002-08-06 37/41
TC58FVT160/B160AFT/AXB-70,-10
BLOCK ERASE ADDRESS TABLES
(1) TC58FVT160A (top boot block)
BLOCK ADDRESS
BLOCK
ADDRESS RANGE
BLOCK SIZE
#
(Kbytes/Kwords)
A19 A18 A17 A16 A15 A14 A13 A12
BYTE MODE
00000h~0FFFFh
10000h~1FFFFh
20000h~2FFFFh
30000h~3FFFFh
40000h~4FFFFh
50000h~5FFFFh
60000h~6FFFFh
70000h~7FFFFh
80000h~8FFFFh
90000h~9FFFFh
A0000h~AFFFFh
B0000h~BFFFFh
C0000h~CFFFFh
D0000h~DFFFFh
E0000h~EFFFFh
F0000h~FFFFFh
100000h~10FFFFh
110000h~11FFFFh
120000h~12FFFFh
130000h~13FFFFh
140000h~14FFFFh
150000h~15FFFFh
160000h~16FFFFh
170000h~17FFFFh
180000h~18FFFFh
190000h~19FFFFh
1A0000h~1AFFFFh
1B0000h~1BFFFFh
1C0000h~1CFFFFh
1D0000h~1DFFFFh
1E0000h~1EFFFFh
1F0000h~1F7FFFh
1F8000h~1F9FFFh
1FA000h~1FBFFFh
1FC000h~1FFFFFh
WORD MODE
00000h~07FFFh
08000h~0FFFFh
10000h~17FFFh
18000h~1FFFFh
20000h~7FFFFh
28000h~2FFFFh
30000h~37FFFh
38000h~3FFFFh
40000h~47FFFh
48000h~4FFFFh
50000h~57FFFh
58000h~5FFFFh
60000h~67FFFh
68000h~6FFFFh
70000h~77FFFh
78000h~7FFFFh
80000h~87FFFh
88000h~8FFFFh
90000h~97FFFh
98000h~9FFFFh
A0000h~A7FFFh
A8000h~AFFFFh
B0000h~B7FFFh
B8000h~BFFFFh
C0000h~C7FFFh
C8000h~CFFFFh
D0000h~D7FFFh
D8000h~DFFFFh
E0000h~E7FFFh
E8000h~EFFFFh
F0000h~F7FFFh
F8000h~FBFFFh
FC000h~FCFFFh
FD000h~FDFFFh
FE000h~FFFFFh
BA0
BA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
1
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
1
×
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
BA2
BA3
BA4
BA5
BA6
BA7
BA8
BA9
BA10
BA11
BA12
BA13
BA14
BA15
BA16
BA17
BA18
BA19
BA20
BA21
BA22
BA23
BA24
BA25
BA26
BA27
BA28
BA29
BA30
BA31
BA32
BA33
BA34
8/4
16/8
2002-08-06 38/41
TC58FVT160/B160AFT/AXB-70,-10
(2) TC58FVB160A (bottom boot block)
BLOCK ADDRESS
BLOCK
ADDRESS RANGE
BLOCK SIZE
#
(Kbytes/Kwords)
A19 A18 A17 A16 A15 A14 A13 A12
BYTE MODE
0000h~3FFFh
WORD MODE
0000h~1FFFh
BA0
BA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
16/8
8/4
4000h~5FFFh
2000h~2FFFh
BA2
8/4
6000h~7FFFh
3000h~3FFFh
BA3
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8000h~FFFFh
4000h~7FFFh
BA4
10000h~1FFFFh
20000h~2FFFFh
30000h~3FFFFh
40000h~4FFFFh
50000h~5FFFFh
60000h~6FFFFh
70000h~7FFFFh
80000h~8FFFFh
90000h~9FFFFh
A0000h~AFFFFh
B0000h~BFFFFh
C0000h~CFFFFh
D0000h~DFFFFh
E0000h~EFFFFh
F0000h~FFFFFh
100000h~10FFFFh
110000h~11FFFFh
120000h~12FFFFh
130000h~13FFFFh
140000h~14FFFFh
150000h~15FFFFh
160000h~16FFFFh
170000h~17FFFFh
180000h~18FFFFh
190000h~19FFFFh
1A0000h~1AFFFFh
1B0000h~1BFFFFh
1C0000h~1CFFFFh
1D0000h~1DFFFFh
1E0000h~1EFFFFh
1F0000h~1EFFFFh
8000h~FFFFh
BA5
10000h~17FFFh
18000h~1FFFFh
20000h~27FFFh
28000h~2FFFFh
30000h~37FFFh
38000h~3FFFFh
40000h~47FFFh
48000h~4FFFFh
50000h~57FFFh
58000h~5FFFFh
60000h~67FFFh
68000h~6FFFFh
70000h~77FFFh
78000h~7FFFFh
80000h~87FFFh
88000h~8FFFFh
90000h~97FFFh
98000h~9FFFFh
A0000h~A7FFFh
A8000h~AFFFFh
B0000h~B7FFFh
B8000h~BFFFFh
C0000h~C7FFFh
C8000h~CFFFFh
D0000h~D7FFFh
D8000h~DFFFFh
E0000h~E7FFFh
E8000h~EFFFFh
F0000h~F7FFFh
F8000h~FFFFFh
BA6
BA7
BA8
BA9
BA10
BA11
BA12
BA13
BA14
BA15
BA16
BA17
BA18
BA19
BA20
BA21
BA22
BA23
BA24
BA25
BA26
BA27
BA28
BA29
BA30
BA31
BA32
BA33
BA34
2002-08-06 39/41
TC58FVT160/B160AFT/AXB-70,-10
PACKAGE DIMENSIONS
Unit: mm
2002-08-06 40/41
TC58FVT160/B160AFT/AXB-70,-10
PACKAGE DIMENSIONS
Unit: mm
2002-08-06 41/41
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