TC58FVT321XB-70_技术文档

TC58FVT321/B321FT/XB-70,-10

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

32-MBIT (4M × 8 BITS / 2M × 16 BITS) CMOS FLASH MEMORY

DESCRIPTION

The TC58FVT321/B321 is a 33,554,432-bit, 3.0-V read-only electrically erasable and programmable flash memory

organized as 4,194,304 words × 8 bits or as 2,097,152 words × 16 bits. The TC58FVT321/B321 features commands

for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands are based on

the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The

TC58FVT321/B321 also features a Simultaneous Read/Write operation so that data can be read during a Write or

Erase operation.

FEATURES

•

Power supply voltage

•

Block erase architecture

V

DD

= 2.7 V~3.6 V

8 × 8 Kbytes / 63 × 64 Kbytes

Boot block architecture

Operating temperature

Ta = −40°C~85°C

TC58FVT321FT/XB: top boot block

TC58FVB321FT/XB: bottom boot block

Mode control

Organization

4M × 8 bits / 2M × 16 bits

Functions

•

Compatible with JEDEC standard commands

Erase/Program cycles

Simultaneous Read/Write

Auto Program, Auto Erase

Fast Program Mode / Acceleration Mode

Program Suspend/Resume

Erase Suspend/Resume

5

10 cycles typ.

Access time

70 ns

(C : 30 pF)

L

100 ns

(C : 100 pF)

L

data polling / Toggle bit

•

Power consumption

block protection, boot block protection

Automatic Sleep, support for hidden ROM area

common flash memory interface (CFI)

Byte/Word Modes

10 µA

30 mA

(Standby)

(Read operation)

15 mA

(Program/Erase operations)

Package

TC58FVT321/B321FT:

TSOPI48-P-1220-0.50 (weight: 0.51 g)

TC58FVT321/B321XB:

P-TFBGA56-0710-0.80AZ (weight: 0.125 g)

000630EBA1

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general

can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,

when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid

situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to

property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most

recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide

for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..

• The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal

equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are

neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or

failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control

instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba products listed in this document

shall be made at the customer’s own risk.

• The products described in this document are subject to the foreign exchange and foreign trade laws.

• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by

TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its

use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or

others.

• The information contained herein is subject to change without notice.

2002-08-06 1/48

TC58FVT321/B321FT/XB-70,-10

PIN ASSIGNMENT (TOP VIEW)

…TC58FVT321/B321FT

PIN NAMES

A15

A14

A13

A12

A11

A10

A9

A16

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A-1, A0~A20 Address Input

BYTE

2

V^SS

3

DQ0~DQ15 Data Input/Output

DQ15/A-1

DQ7

4

CE

OE

Chip Enable Input

5

DQ14

DQ6

6

Output Enable Input

Word/Byte Select Input

Write Enable Input

Ready/Busy Output

Hardware Reset Input

7

A8

DQ13

DQ5

8

BYTE

WE

A19

A20

WE

9

DQ12

DQ4

10

11

V^DD

RESET 12

RY/BY

RESET

NC

DQ11

DQ3

13

14

15

16

17

18

19

20

21

22

23

24

WP/ACC

DQ10

DQ2

RY/BY

A18

A17

A7

Write Protect /

Program Acceleration Input

WP/ACC

NC

DQ9

DQ1

A6

DQ8

Not Connected

Power Supply

Ground

A5

DQ0

A4

V

OE

DD

A3

V^SS

V

A2

SS

CE

A0

A1

PIN ASSIGNMENT (TOP VIEW)…TC58FVT321/B321XB

1

2

3

4

5

6

7

8

A

B

C

D

E

F

NC

A3

A4

A2

A1

A0

CΕ

OE

A7

A17

A6

RY/BY

WP/ACC

A18

WE

RESET

NC

A9

A8

A13

A12

A10

A14

A5

A20

A19

A11

A15

G

H

J

DQ0

DQ8

DQ9

DQ1

DQ2

DQ5

DQ7

DQ14

DQ13

DQ6

A16

DQ10

DQ11

DQ3

DQ12

BYTE

DQ15

V

DD

K

L

V

DQ4

V

SS

NC

M

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TC58FVT321/B321FT/XB-70,-10

BLOCK DIAGRAM

V

DD

V

SS

RY/BY

DQ0

DQ15

RY/BY Buffer

I/O Buffer

WP/ACC

WE

Control Circuit

BYTE

RESET

CE

Data Latch

Command Register

OE

Memory Cell

Array

Memory Cell

Array

Memory Cell

Array

Bank 0

Bank 7

Bank 8

A0

A20

A-1

2002-08-06 3/48

TC58FVT321/B321FT/XB-70,-10

MODE SELECTION

BYTE MODE WORD MODE

(1)

MODE

Read

CE OE WE A9

A6

L

A1

L

A0 RESET WP/ACC DQ0~DQ7

DQ0~DQ15

L

H

*

L

H

*

A9

A0

L

H

*

L

D

OUT

D

OUT

ID Read (Manufacturer Code)

ID Read (Device Code)

Standby

V

Code

ID

L

H

*

High-Z

Output Disable

H

*

(2)

Write

L

*

A9

A6

L

A1

H

*

A0

L

H

D

IN

D

IN

(2)

Block Protect 1

V

*

ID

Verify Block Protect

Temporary Block Unprotect

Hardware Reset / Standby

Boot Block Protect

L

*

H

*

L

Code

*

V

*

High-Z

*

High-Z

*

ID

*

L

*

Notes: * = V or V , L = V , H = V

IH

IL

IH

(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.

Addresses are A20~A0 in Word Mode (BYTE = V ), A20~A-1 in Byte Mode (BYTE = V ).

IH

IL

(2) Pulse input

ID CODE TABLE

(1)

CODE TYPE

A20~A12

A6

L

A1

L

A0

CODE (HEX)

Manufacturer Code

Device Code

*

L

H

L

0098H

TC58FVT321

TC58FVB321

L

009AH

L

009CH

(2)

(3)

Verify Block Protect

BA

L

H

Data

Notes: * = V or V , L = V , H = V

IH

IL

(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.

(2) BA: Block Address

(3) 0001H - Protected Block

0000H - Unprotected Block

2002-08-06 4/48

TC58FVT321/B321FT/XB-70,-10

COMMAND SEQUENCES

BUS

FIRST BUS

WRITE CYCLE

SECOND BUS

WRITE CYCLE

THIRD BUS

FOURTH BUS

WRITE CYCLE

FIFTH BUS

SIXTH BUS

COMMAND

SEQUENCE

WRITE

CYCLES

REQ’D

WRITE CYCLE

Addr.

Data

F0H

Addr.

Data

55H

Addr.

555H

Data Addr.

Data

Addr.

Data

Addr.

Data

Read/Reset

1

3

XXXH

555H

AAAH

Word

Byte

2AAH

555H

(1)

(2)

Read/Reset

AAH

F0H RA

RD

AAAH

(3)

BK

+

Word

Byte

555H

2AAH

555H

(3)

(4)

(5)

ID Read

3

90H

IA

ID

BK

+

AAAH

Word

Byte

555H

2AAH

555H

(6)

(7)

Auto-Program

4

A0H PA

PD

AAAH

(3)

Program Suspend

Program Resume

1

BK

B0H

30H

(3)

BK

Word

555H

AAAH

555H

AAAH

2AAH

555H

2AAH

555H

AAAH

555H

AAAH

555H

2AAH

555H

2AAH

555H

Auto Chip

Erase

6

AAH

55H

80H

AAH

55H

10H

30H

Byte

Word

Byte

AAAH

555H

AAAH

Auto Block

Erase

(8)

BA

AAAH

(3)

Block Erase Suspend

Block Erase Resume

Block Protect 2

1

4

BK

B0H

30H

(3)

BK

(9)

(10)

XXXH

555H

60H BPA

60H

55H

XXXH 40H BPA

(3)

BPD

BK

555H

(3)

+

Word

2AAH

Verify Block

(9)

(10)

3

AAH

90H BPA

Protect

Byte

BK

+

AAAH

555H

AAAH

Word

Byte

555H

AAAH

XXXH

555H

AAAH

555H

AAAH

555H

AAAH

555H

2AAH

555H

Fast Program

Set

3

AAH

55H

20H

AAAH

(6)

(7)

Fast Program

2

A0H

90H

PA

PD

(13)

Fast Program Reset

XXXH F0H

2AAH

Word

555H

AAAH

555H

AAAH

555H

AAAH

555H

AAAH

Hidden ROM

Mode Entry

3

4

6

4

AAH

55H

88H

Byte

Word

Byte

Word

Byte

Word

Byte

555H

2AAH

555H

2AAH

555H

2AAH

555H

Hidden ROM

Program

(6)

(7)

55H

A0H PA

PD

555H

2AAH

555H

Hidden ROM

Erase

(8)

55H

80H

AAH

55H

BA

30H

AAAH

Hidden ROM

Mode Exit

90H XXXH

00H

AAAH

(3)

BK

+

Word

Byte

55H

(3)

Query

(11)

CA

(12)

2

98H

CD

Command

BK

AAH

+

Notes: The system should generate the following address patterns:

Word Mode: 555H or 2AAH on address pins A10~A0

Byte Mode: AAAH or 555H on address pins A10~A-1

DQ8~DQ15 are ignored in Word Mode.

(1) RA: Read Address

(7) PD:Program Data

(8) BA:Block Address = A20~A12

(2) RD: Read Data

(3) BK: Bank Address = A20~A15

(4) IA: Bank Address and ID Read Address (A6, A1, A0)

Bank Address = A20~A15

(9) BPA: Block Address and ID Read Address (A6, A1, A0)

Block Address = A20~A12

ID Read Address = (0, 1, 0)

(10) BPD:Verify Data

Manufacturer Code = (0, 0, 0)

Device Code = (0, 0, 1)

(5) ID: ID Data

(11) CA:CFI Address

(12) CD:CFI Data

(6) PA: Program Address

(13) F0H: 00H is valid too

2002-08-06 5/48

TC58FVT321/B321FT/XB-70,-10

SIMULTANEOUS READ/WRITE OPERATION

The TC58FVT321/B321 features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation

enables the device to simultaneously write data to or erase data from a bank while reading data from another bank.

The TC58FVT321/B321 has a total of nine banks: 1 bank of 0.5 Mbits, 1 bank of 3.5 Mbits and 7 banks of 4 Mbits.

Banks can be switched between using the bank addresses (A20~A15). For a description of bank blocks and addresses,

please refer to the Block Address Table and Block Size Table.

The Simultaneous Read/Write operation cannot perform multiple operations within a single bank. The table below

shows the operation modes in which simultaneous operation can be performed.

Note that during Auto-Program execution or Auto Block Erase operation, the Simultaneous Read/Write operation

cannot read data from addresses in the same bank which have not been selected for operation. Data from these

addresses can be read using the Program Suspend or Erase Suspend function, however.

SIMULTANEOUS READ/WRITE OPERATION

STATUS OF BANK ON WHICH OPERATION IS BEING

STATUS OF OTHER BANKS

PERFORMED

Read Mode

(1)

ID Read Mode

Auto-Program Mode

(2)

Fast Program Mode

Program Suspend Mode

Read Mode

Auto Block Erase Mode

(3)

Auto Multiple Block Erase Mode

Erase Suspend Mode

Program Suspend during Erase Suspend

CFI Mode

(1) Only Command Mode is valid.

(2) Including times when Acceleration Mode is in use.

(3) If the selected blocks are spread across all nine banks, simultaneous operation cannot be carried out.

OPERATION MODES

In addition to the Read, Write and Erase Modes, the TC58FVT321/B321 features many functions including block

protection and data polling. When incorporating the device into a deign, please refer to the timing charts and

flowcharts in combination with the description below.

READ MODE

To read data from the memory cell array, set the device to Read Mode. In Read Mode the device can perform

high-speed random access as asynchronous ROM.

The device is automatically set to Read Mode immediately after power-on or on completion of automatic

operation. A software reset releases ID Read Mode and the lock state which the device enters if automatic

operation ends abnormally, and sets the device to Read Mode. A hardware reset terminates operation of the

device and resets it to Read Mode. When reading data without changing the address immediately after power-on,

either input a hardware Reset or change CE from H to L.

2002-08-06 6/48

TC58FVT321/B321FT/XB-70,-10

ID Read Mode

ID Read Mode is used to read the device maker code and device code. The mode is useful in that it allows

EPROM programmers to identify the device type automatically.

ID read can be executed in two ways, as follows:

(1) Applying V to A9

ID

This method is used mainly by EPROM programmers. Applying V to A9 sets the device to ID Read Mode,

ID

outputting the maker code from address 00H and the device code from address 01H. Releasing V from A9

ID

returns the device to Read Mode. With this method all banks are set to ID Read Mode; thus, simultaneous

operation cannot be performed.

(2) Input command sequence

With this method simultaneous operation can be performed. Inputting an ID Read command sets the

specified bank to ID Read Mode. Banks are specified by inputting the bank address (BK) in the third Bus

Write cycle of the Command cycle. To read an ID code, the bank address as well as the ID read address must

be specified. The maker code is output from address BK + 00; the device code is output from address BK + 01.

From other banks data are output from the memory cells. Inputting a Reset command releases ID Read

Mode and returns the device to Read Mode.

Access time in ID Read Mode is the same as that in Read Mode. For a list of the codes, please refer to the

ID Code Table.

Standby Mode

There are two ways to put the device into Standby Mode.

(1) Control using CE and RESET

With the device in Read Mode, input V

0.3 V to CE and RESET . The device will enter Standby

DD

Mode and the current will be reduced to the standby current (I

). However, if the device is in the process

DDS1

of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the

operating current to flow.

(2) Control using RESET only

With the device in Read Mode, input V

0.3 V to RESET . The device will enter Standby Mode and the

SS

current will be reduced to the standby current (I

). Even if the device is in the process of performing

DDS1

simultaneous operation, this method will terminate the current operation and set the device to Standby

Mode. This is a hardware reset and is described later.

In Standby Mode DQ is put in High-Impedance state.

Auto-Sleep Mode

This function suppresses power dissipation during reading. If the address input does not change for 150 ns, the

device will automatically enter Sleep Mode and the current will be reduced to the standby current (I

).

DDS2

However, if the device is in the process of performing simultaneous operation, the device will not enter Standby

Mode but will instead cause the operating current to flow. Because the output data is latched, data is output in

Sleep Mode. When the address is changed, Sleep Mode is automatically released, and data from the new address

is output.

Output Disable Mode

Inputting V to OE disables output from the device and sets DQ to High-Impedance.

IH

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TC58FVT321/B321FT/XB-70,-10

Command Write

2

The TC58FVT321/B321 uses the standard JEDEC control commands for a single-power supply E PROM. A

Command Write is executed by inputting the address and data into the Command Register. The command is

written by inputting a pulse to WE with CE = V and OE = V ( WE control). The command can also be

IL

IH

written by inputting a pulse to CE with WE = V (CE control). The address is latched on the falling edge of

IL

either WE or CE . The data is latched on the rising edge of either WE or CE . DQ0~DQ7 are valid for data

input and DQ8~DQ15 are ignored.

To abort input of the command sequence use the Reset command. The device will reset the Command Register

and enter Read Mode. If an undefined command is input, the Command Register will be reset and the device will

enter Read Mode.

Software Reset

Apply a software reset by inputting a Read/Reset command. A software reset returns the device from ID Read

Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and clears

the Command Register.

Hardware Reset

A hardware reset initializes the device and sets it to Read Mode. When a pulse is input to RESET for t , the

RP

device abandons the operation which is in progress and enters Read Mode after t

. Note that if a hardware

READY

reset is applied during data overwriting, such as a Write or Erase operation, data at the address or block being

written to at the time of the reset will become undefined.

After a hardware reset the device enters Read Mode if RESET = V or Standby Mode if RESET = V . The

IH

IL

DQ pins are High-Impedance when RESET = V . After the device has entered Read Mode, Read operations

IL

and input of any command are allowed.

Comparison between Software Reset and Hardware Reset

ACTION

SOFTWARE RESET

HARDWARE RESET

Releases ID Read Mode or CFI Mode.

True

False

True

Clears the Command Register.

Releases the lock state if automatic operation has ended abnormally.

Stops any automatic operation which is in progress.

Stops any operation other than the above and returns the device to

Read Mode.

False

True

BYTE/Word Mode

BYTE is used select Word Mode (16 bits) or Byte Mode (8 bits) for the TC58FVT321/B321. If V is input to

IH

BYTE , the device will operate in Word Mode. Read data or write commands using DQ0~DQ15. When V is

IL

input to BYTE , read data or write commands using DQ0~DQ7. DQ15/A-1 is used as the lowest address.

DQ8~DQ14 will become High-Impedance.

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TC58FVT321/B321FT/XB-70,-10

Auto-Program Mode

The TC58FVT321/B321 can be programmed in either byte or word units. Auto-Program Mode is set using the

Program command. The program address is latched on the falling edge of the WE signal and data is latched on

the rising edge of the fourth Bus Write cycle (with WE control). Auto programming starts on the rising edge of

the WE signal in the fourth Bus Write cycle. The Program and Program Verify commands are automatically

executed by the chip. The device status during programming is indicated by the Hardware Sequence flag. To read

the Hardware Sequence flag, specify the address to which the Write is being performed.

During Auto-Program execution, a command sequence for the bank on which execution is being performed

cannot be accepted. To terminate execution, use a hardware reset. Note that if the Auto-Program operation is

terminated in this manner, the data written so far is invalid.

Any attempt to program a protected block is ignored. In this case the device enters Read Mode 3 µs after the

rising edge of the WE signal in the fourth Bus Write cycle.

If an Auto-Program operation fails, the device remains in the programming state and does not automatically

return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or

a hardware reset is required to return the device to Read Mode after a failure. If a programming operation fails,

the block which contains the address to which data could not be programmed should not be used.

The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into

cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device

error. A cell containing 0 must be erased in order to set it to 1.

Fast Program Mode

Fast Program is a function which enables execution of the command sequence for the Auto Program to be

completed in two cycles. In this mode the first two cycles of the command sequence, which normally requires four

cycles, are omitted. Writing is performed in the remaining two cycles. To execute Fast Program, input the Fast

Program command. Write in this mode uses the Fast Program command but operation is the same at that for

ordinary Auto-Program. The status of the device is indicated by the Hardware Sequence flag and read operations

can be performed as usual. To exit this mode, the Fast Program Reset command must be input. When the

command is input, the device will return to Read Mode.

Acceleration Mode

The TC58FVT321/B321 features Acceleration Mode which allows write time to be reduced. Applying V

to

ACC

WP or ACC automatically sets the device to Acceleration Mode. In Acceleration Mode, Block Protect Mode

changes to Temporary Block Unprotect Mode. Write Mode changes to Fast Program Mode. Modes are switched by

the WP/ACC signal; thus, there is no need for a Temporary Block Unprotect operation or to set or reset Fast

Program Mode. Operation of Write is the same as in Auto-Program Mode. Removing V

terminates Acceleration Mode.

from WP/ACC

ACC

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TC58FVT321/B321FT/XB-70,-10

Program Suspend/Resume Mode

Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a

Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but

ignores the command in other modes. When the command is input, the address of the bank on which Write is

being performed must be specified. After input of the command, the device will enter Program Suspend Read

Mode after t

SUSP

.

During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write is

suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are

the same as usual.

After completion of Program Suspend input a Program Resume command to return to Write Mode. When

inputting the command, specify the address of the bank on which Write is being performed. If the ID Read or CFI

Data Read functions is being used, abort the function before inputting the Resume command. On receiving the

Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag for the

bank to which data is being written.

Program Suspend can be run in Fast Program Mode or Acceleration Mode. However, note that when running

Program Suspend in Acceleration Mode, V

must not be released.

ACC

Auto Chip Erase Mode

The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the

rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and

verified as erased by the chip. The device status is indicated by the Hardware Sequence flag.

Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase

operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence an additional

Erase operation must be performed.

Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not

be executed and the device will enter Read mode 100 µs after the rising edge of the WE signal in the sixth bus

cycle.

If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to Read

Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware

reset is required to return the device to Read Mode after a failure.

In this case it cannot be ascertained which block the failure occurred in. Either abandon use of the device

altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host processor

must take measures to prevent subsequent use of the failed block.

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TC58FVT321/B321FT/XB-70,-10

Auto Block Erase / Auto Multi-Block Erase Modes

The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The

block address is latched on the falling edge of the WE signal in the sixth bus cycle. The block erase starts as

soon as the Erase Hold Time (t

BEH

) has elapsed after the rising edge of the WE signal. When multiple blocks

are erased, the sixth Bus Write cycle is repeated with each block address and Auto Block Erase command being

input within the Erase Hold Time (this constitutes an Auto Multi-Block Erase operation). If a command other

than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time, the device

will reset the Command Register and enter Read Mode. The Erase Hold Time restarts on each successive rising

edge of WE . Once operation starts, all memory cells in the selected block are automatically preprogrammed to 0,

erased and verified as erased by the chip. The device status is indicated by the setting of the Hardware Sequence

flag. When the Hardware Sequence flag is read, the addresses of the blocks on which auto-erase operation is

being performed must be specified. If the selected blocks are spread across all nine banks, simultaneous

operation cannot be carried out.

All commands (except Erase Suspend) are ignored during an Auto Block Erase or Auto Multi-Block Erase

operation. Either operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it

cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing.

Any attempt to erase a protected block is ignored. If all the selected blocks are protected, the auto-erase

operation is not executed and the device returns to Read Mode 100 µs after the rising edge of the WE signal in

the last bus cycle.

If an auto-erase operation fails, the device remains in Erasing state and does not return to Read Mode. The

device status is indicated by the Hardware Sequence flag. After a failure either a Reset command or a Hardware

Reset is required to return the device to Read Mode. If multiple blocks are selected, it will not be possible to

ascertain the block in which the failure occurred. In this case either abandon use of the device altogether, or

perform a Block Erase on each block, identify the failed block, and stop using it. The host processor must take

measures to prevent subsequent use of the failed block.

Erase Suspend / Erase Resume Modes

Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block.

The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other oreration

modes . When the command is input, the address of the bank on which Erase is being performed must be

specified.

In Erase Suspend Mode only a Read, Program or Resume command can be accepted. If an Erase Suspend

command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after t

. The

SUSE

device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is

read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output

will stop toggling and RY/BY will be set to High-Impedance.

Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has not

been selected for the Auto Block Erase. Data is written in the usual manner.

To resume the Auto Block Erase, input an Erase Resume command. On input of the command, the address of

the bank on which the Write was being performed must be specified. On receiving an Erase Resume command,

the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend

command is input during the Erase Hold Time, the device will return to the state it was in at the start of the

Erase Hold Time. At this time more blocks can be specified for erasing. If an Erase Resume command is input

during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on

RY/BY .

2002-08-06 11/48

TC58FVT321/B321FT/XB-70,-10

Block Protection

Block Protection is a function for disabling writing and erasing specific blocks. Block protection can be carried

out in two ways: by supplying a high voltage (V ) to the device (see Block protection 1) or by supplying a high

ID

voltage and a command sequence (see Block protection 2).

(1) Block protection 1

Specify a device block address and make the following signal settings A9 = OE = V , A1 = V and CE

ID

IH

= A0 = A6 = V . Now when a pulse is input to WE for t

, the device will start to write to the block

IL

PPLH

protection circuit. Block protection can be verified using the Verify Block Protect command. Inputting V on

IL

OE sets the device to Verify Mode. 01H is output if the block is protected and 00H is output if the block is

unprotected. If block protection was unsuccessful, the operation must be repeated. Releasing V from A9

ID

and OE terminates this mode.

(2) Block protection 2

Applying V to RESET and inputting the Block Protect 2 command also performs block protection. The

ID

first cycle of the command sequence is the Set-up command. In the second cycle, the Block Protect command

is input, in which a block address and A1 = V and A0 = A6 = V are input. Now the device writes to the

IH

IL

block protection circuit. There is a wait of t

until this write is completed; however, no intervention is

PPLH

necessary during this time. In the third cycle the Verify Block Protect command is input. This command

verifies the write to the block protection circuit. Read is performed in the fourth cycle. If the protection

operation is complete, 01H is output. If a value other than 01H is output, block protection is not complete

and the Block Protect command must be input again. Removing the V input from RESET exits this

ID

mode.

Temporary Block Unprotection

The TC58FVT321/B321 has a temporary block unprotection feature which disables block protection for all

protected blocks. Unprotection is enabled by applying V to the RESET pin. Now Write and Erase operations

ID

can be performed on all blocks except the boot blocks which have been protected by the Boot Block Protect

operation. The device returns to its previous state when V

previously protected blocks will be protected again.

is removed from the RESET pin. That is,

ID

Verify Block Protect

The Verify Block Protect command is used to ascertain whether a block is protected or unprotected.

Verification is performed either by inputting the Verify Block Protect command or by applying V to the A9 pin,

ID

as for ID Read Mode, and setting the block address = A0 = A6 = V and A1 = V . If the block is protected, 01H is

IL

IH

output. If the block is unprotected, 00H is output.

Boot Block Protection

Boot block protection temporarily protects certain boot blocks using a method different from ordinary block

protection. Neither V nor a command sequence is required. Protection is performed simply by inputting V on

I

D

I

L

WP/ACC . The target blocks are the two pairs of boot blocks. The top boot blocks are BA69 and BA70; the bottom

boot blocks are BA0 and BA1. Inputting V on WP/ACC releases the mode. From now on, if it is necessary to

IH

protect these blocks, the ordinary Block Protection Mode must be used.

2002-08-06 12/48

TC58FVT321/B321FT/XB-70,-10

Hidden ROM Area

The TC58FVT321/B321 features a 64-Kbyte hidden ROM area which is separate from the memory cells. The

area consists of one block. Data Read, Write and Protect can be performed on this block. Because Protect cannot

be released, once the block is protected, data in the block cannot be overwritten.

The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS

TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters

Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations

are the same as auto operations except that the device is in Hidden ROM Mode. However, regarding write

operation, Accelaration mode can not be performed during Hidden ROM Mode. To protect the hidden ROM area,

use the block protection function. The operation of Block Protect here is the same as a normal Block Protect

except that V rather than V is input to RESET . Once the block has been protected, protection cannot be

IH

ID

released, even using the temporary block unprotection function. Use Block Protect carefully. Note that in Hidden

ROM Mode, simultaneous operation cannot be performed. Therefore, do not attempt to access areas other than

the hidden ROM area.

To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read

Mode.

HIDDEN ROM AREA ADDRESS TABLE

BYTE MODE

ADDRESS RANGE

WORD MODE

ADDRESS RANGE

BOOT BLOCK

ARCHITECTURE

TYPE

SIZE

TC58FVT321

TC58FVB321

TOP BOOT BLOCK

3F0000H~3FFFFFH

000000H~00FFFFH

64 Kbytes

1F8000H~1FFFFFH

000000H~007FFFH

32 Kwords

BOTTOM BOOT BLOCK

2002-08-06 13/48

TC58FVT321/B321FT/XB-70,-10

COMMON FLASH MEMORY INTERFACE (CFI)

The TC58FVT321/B321 conforms to the CFI specifications. To read information from the device, input the

Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input the

Reset command.

CFI CODE TABLE

ADDRESS A6~A0

DATA DQ15~DQ0

DESCRIPTION

10H

11H

12H

0051H

0052H

0059H

ASCII string “QRY”

13H

14H

0002H

0000H

Primary OEM command set

2: AMD/FJ standard type

15H

16H

0040H

0000H

Address for primary extended table

17H

18H

0000H

Alternate OEM command set

0: none exists

19H

1AH

0000H

Address for alternate OEM extended table

V

(min) (Write/Erase)

DD

1BH

1CH

0027H

0036H

DQ7~DQ4: 1 V

DQ3~DQ0: 100 mV

V

(max) (Write/Erase)

DD

DQ7~DQ4: 1 V

DQ3~DQ0: 100 mV

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

27H

0000H

0004H

0000H

000AH

0000H

0005H

0000H

0004H

0000H

0016H

V

(min) voltage

(max) voltage

PP

N

Typical time-out per single byte/word write (2 µs)

N

Typical time-out for minimum size buffer write (2 µs)

N

Typical time-out per individual block erase (2 ms)

N

Typical time-out for full chip erase (2 ms)

N

Maximum time-out for byte/word write (2 times typical)

N

Maximum time-out for buffer write (2 times typical)

N

Maximum time-out per individual block erase (2 times typical)

N

Maximum time-out for full chip erase (2 times typical)

N

Device Size (2 byte)

28H

29H

0002H

0000H

Flash device interface description

2: ×8/×16

2AH

2BH

0000H

N

Maximum number of bytes in multi-byte write (2 )

2002-08-06 14/48

TC58FVT321/B321FT/XB-70,-10

ADDRESS A6~A0

2CH

DATA DQ15~DQ0

0002H

DESCRIPTION

Number of erase block regions within device

2DH

2EH

2FH

30H

0007H

0000H

0020H

0000H

Erase Block Region 1 information

Bits 0~15: y = block number

Bits 16~31: z = block size

(z × 256 bytes)

31H

32H

33H

34H

003EH

0000H

0001H

Erase Block Region 2 information

40H

41H

42H

0050H

0052H

0049H

ASCII string “PRI”

43H

44H

0031H

Major version number, ASCII

Minor version number, ASCII

Address-Sensitive Unlock

0: Required

45H

46H

47H

0000H

0002H

0001H

1: Not required

Erase Suspend

0: Not supported

1: For Read-only

2: For Read & Write

Block Protect

0: Not supported

X: Number of blocks per group

Block Temporary Unprotect

0: Not supported

48H

49H

4AH

0001H

0004H

0001H

1: Supported

Block Protect/Unprotect scheme

Simultaneous operation

0: Not supported

1: Supported

Burst Mode

4BH

4CH

0000H

0: Not supported

Page Mode

0: Not supported

V

(min) voltage

DQ7~DQ4: 1 V

DQ3~DQ0: 100 mV

ACC

4DH

4EH

4FH

50H

0085H

0095H

000XH

0001H

(max) voltage

DQ7~DQ4: 1 V

DQ3~DQ0: 100 mV

ACC

Top/Bottom Boot Block Flag

2: TC58FVB321

3: TC58FVT321

Program suspend

0: Not supported

1: Supported

2002-08-06 15/48

TC58FVT321/B321FT/XB-70,-10

HARDWARE SEQUENCE FLAGS

The TC58FVT321/B321 has a Hardware Sequence flag which allows the device status to be determined during an

auto mode operation. The output data is read out using the same timing as that used when CE = OE = V in

IL

Read Mode. The RY/BY output can be either High or Low.

The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The

Hardware Sequence flag is read to determine the device status and the result of the operation is verified by

comparing the read-out data with the original data.

STATUS

DQ7

Data

0

DQ6

Toggle

Data

DQ5

DQ3

DQ2

1

RY/BY

Auto Programming

0

(1)

Read in Program Suspend

Data

Toggle

1

High-Z

(2)

Selected

Toggle

1

0

Erase Hold Time

Auto Erase

Read

(3)

Not-selected

Selected

0

In Auto

Erase

0

1

Toggle

1

0

In Progress

Not-selected

Selected

0

1

0

1

0

Toggle

Data

Toggle

1

High-Z

Not-selected

Selected

Data

DQ7

0

Data

0

Data

0

High-Z

In Erase

Suspend

Toggle

0

Programming

Not-selected

0

Auto Programming

Auto Erase

1

0

1

Time Limit

Exceeded

1

NA

Programming in Erase Suspend

DQ7

1

0

NA

Notes: DQ outputs cell data and RY/BY goes High-Impedence when the operation has been completed.

DQ0 and DQ1 pins are reserved for future use.

0 is output on DQ0, DQ1 and DQ4.

(1) Data output from an address to which Write is being performed is undefined.

(2) Output when the block address selected for Auto Block Erase is specified and data is read from there.

During Auto Chip Erase, all blocks are selected.

(3) Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is

read from there.

DQ7 (DATA polling)

During an Auto-Program or auto-erase operation, the device status can be determined using the data polling

function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation,

DQ7 outputs inverted data during the programming operation and outputs actual data after programming has

finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase

operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data.

When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE signal.

2002-08-06 16/48

TC58FVT321/B321FT/XB-70,-10

DQ6 (Toggle bit 1)

The device status can be determined by the Toggle Bit function during an Auto-Program or auto-erase

operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately

outputs a 0 or a 1 for each OE access while CE = V while the device is busy. When the internal operation

IL

has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the

operation fails, the DQ6 output toggles.

If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around 3

µs. It will then stop toggling. If an attempt is made to execute an auto erase operation on a protected block, DQ6

will toggle for around 100 µs. It will then stop toggling. After toggling has stopped the device will return to Read

Mode.

DQ5 (internal time-out)

If the internal timer times out during a Program or Erase operation, DQ5 outputs a 1. This indicates that the

operation has not been completed within the allotted time.

Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case DQ5

outputs a 1. Either a hardware reset or a software Reset command is required to return the device to Read Mode.

DQ3 (Block Erase timer)

The Block Erase operation starts 50 µs (the Erase Hold Time) after the rising edge of WE in the last

command cycle. DQ3 outputs a 0 for the duration of the Block Erase Hold Time and a 1 when the Block Erase

operation starts. Additional Block Erase commands can only be accepted during the Block Erase Hold Time.

Each Block Erase command input within the hold time resets the timer, allowing additional blocks to be marked

for erasing. DQ3 outputs a 1 if the Program or Erase operation fails.

DQ2 (Toggle bit 2)

DQ2 is used to indicate which blocks have been selected for Auto Block Erase or to indicate whether the device

is in Erase Suspend Mode.

If data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle.

Now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. If data is read

continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ2

output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in Erase

Suspend Mode. If data is read from the address to which data is being written during Erase Suspend in

Programming Mode, DQ2 will output a 1.

RY/BY

BUSY

)

(READY/

The TC58FVT321/B321 has a RY/BY signal to indicate the device status to the host processor. A 0 (Busy

state) indicates that an Auto-Program or auto-erase operation is in progress. A 1 (Ready state) indicates that the

operation has finished and that the device can now accept a new command. RY/BY outputs a 0 when an

operation has failed.

RY/BY outputs a 0 after the rising edge of WE in the last command cycle.

During an Auto Block Erase operation, commands other than Erase Suspend are ignored. RY/BY outputs a 1

during an Erase Suspend operation. The output buffer for the RY/BY pin is an open-drain type circuit,

allowing a wired-OR connection. A pull-up resistor must be inserted between V

and the RY/BY pin.

DD

2002-08-06 17/48

TC58FVT321/B321FT/XB-70,-10

DATA PROTECTION

The TC58FVT321/B321 includes a function which guards against malfunction or data corruption.

Protection against Program/Erase Caused by Low Supply Voltage

To prevent malfunction at power-on or power-down, the device will not accept commands while V

is below

DD

V

LKO

If V

. In this state, command input is ignored.

drops below V

LKO

during an Auto Operation, the device will terminate Auto-Program execution. In this

DD

case, Auto operation is not executed again when V_DDreturn to recommended V_DDvoltage Therefore, command

need to be input to execute Auto operation again.

When V_DD> V_LKO, make up countermeasure to be input accurately command in system side please.

Protection against Malfunction Caused by Glitches

To prevent malfunction during operation caused by noise from the system, the device will not accept pulses

shorter than 3 ns (Typ.) input on WE , CE or OE . However, if a glitch exceeding 3 ns (Typ.) occurs and the

glitch is input to the device malfunction may occur.

The device uses standard JEDEC commands. It is conceivable that, in extreme cases, system noise may be

misinterpreted as part of a command sequence input and that the device will acknowledge it. Then, even if a

proper command is input, the device may not operate. To avoid this possibility, clear the Command Register

before command input. In an environment prone to system noise, Toshiba recommend input of a software or

hardware reset before command input.

Protection against Malfunction at Power-on

To prevent damage to data caused by sudden noise at power-on, when power is turned on with WE = CE =

V

IL

the device does not latch the command on the first rising edge of WE or CE . Instead, the device

automatically Resets the Command Register and enters Read Mode.

2002-08-06 18/48

TC58FVT321/B321FT/XB-70,-10

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RANGE

UNIT

V

P

V

Supply Voltage

DD

−0.6~4.6

DD

Input Voltage

−0.6~V

+ 0.5 (≤ 4.6)

V

IN

DD

Input/Output Voltage

+ 0.5 (≤ 4.6)

V

DQ

Maximum Input Voltage for A9, OE and RESET

Maximum Input Voltage for WP/ACC

Power Dissipation

13.0

V

IDH

10.5

126

V

ACCH

D

mW

°C

mA

T

Soldering Temperature (10 s)

Storage Temperature

260

SOLDER

STG

−55~150

−40~85

100

Operating Temperature

OPR

OSHORT

(1)

I

Output Short-Circuit Current

(1) Outputs should be shorted for no more than one second.

No more than one output should be shorted at a time.

CAPACITANCE (Ta = 25°C, f = 1 MHz)

TSOPI

SYMBOL

PARAMETER

CONDITION

= 0 V

MAX

UNIT

pF

C

Input Pin Capacitance

Output Pin Capacitance

Control Pin Capacitance

V

4

8

7

IN

V

= 0 V

OUT

pF

OUT

IN2

V

= 0 V

pF

IN

This parameter is periodically sampled and is not tested for every device.

TFBGA

SYMBOL

PARAMETER

CONDITION

= 0 V

MAX

UNIT

pF

C

Input Pin Capacitance

Output Pin Capacitance

Control Pin Capacitance

V

4

8

7

IN

V

= 0 V

OUT

pF

OUT

IN2

V

= 0 V

pF

IN

This parameter is periodically sampled and is not tested for every device.

RECOMMENDED DC OPERATING CONDITIONS

SYMBOL

PARAMETER

MIN

2.7

MAX

3.6

UNIT

V

Supply Voltage

DD

(2)

Input High-Level Voltage

Input Low-Level Voltage

0.7 × V

V

+ 0.3

DD

IH

DD

(1)

V

−0.3

11.4

0.2 × V

12.6

9.5

IL

DD

(3)

High-Level Voltage for A9, OE and RESET

ID

(3)

High-Level Voltage for WP/ACC

8.5

ACC

Ta

Operating Temperature

−40

85

°C

(1) −2 V (pulse width of 20 ns max)

(2) +2 V (pulse width of 20 ns max)

(3) Do not apply V /V

when the supply voltage is not within the device’s recommended operating voltage range.

ID ACC

2002-08-06 19/48

TC58FVT321/B321FT/XB-70,-10

DC CHARACTERISTICS

SYMBOL

PARAMETER

CONDITION

MIN



MAX

1

UNIT

I

Input Leakage Current

Output Leakage Current

0 V ≤ V ≤ V

LI

LO

IN

DD

µA

0 V ≤ V

≤ V



1

OUT

DD

I

= −0.1 mA

= −2.5 mA

= 4.0 mA

V

− 0.4

DD



OH

OL

V

Output High Voltage

Output Low Voltage

OH

V

0.85 × V



DD



0.4

OL

V

= V /V , I

= 0 mA

IN

IH IL OUT

I

V

Average Read Current



30

DDO1

DD

t

= t

= 100 ns

CYCLE

RC

I

V

Average Program Current

Average Erase Current

Average

V

= V /V , I

IH IL OUT

= 0 mA



15

DDO2

DDO3

DD

IN

= V /V , I

IH IL OUT

= V /V , I

IN

IH IL OUT

mA

I



45

15

10

35

DDO4

DDO5

DDO6

DDS1

DDS2

ID

Read-While-Program Current

t

= t

= 100 ns

RC

CYCLE

V

Average Read-while-Erase

V

t

= V /V , I

= 0 mA

DD

IN

IH IL OUT

Current

= t

= 100 ns

CYCLE

RC

V

Average Program-while-

DD

V

= V /V , I

= 0 mA

IN

IH IL OUT

Erase-Suspend Current

CE = RESET = V

or RESET = V

DD

V

Standby Current

DD

V

SS

V

= V

DD

IH

IL

DD

SS

µA

(1)

(Automatic Sleep Mode

)

High-Voltage Input Current for

A9, OE and RESET

11.4 V ≤ V ≤ 12.6 V

ID

High-Voltage Input Current for

WP/ACC

8.5 V ≤ V

≤ 9.5 V

ACC



20

mA

V

ACC

V

Low-V

Lock-out Voltage

DD



2.3

2.5

LKO

(1) The device enters Automatic Sleep Mode in which the address remains fixed for during 150 ns.

AC TEST CONDITIONS

PARAMETER

CONDITION

, 0.0 V

Input Pulse Level

V

DD

Input Pulse Rise and Fall Time (10%~90%)

Timing Measurement Reference Level (input)

Timing Measurement Reference Level (output)

Output Load

5 ns

1.5 V, 1.5 V

C (100 pF) + 1 TTL Gate

L

/

C (30 pF) + 1 TTL Gate

L

2002-08-06 20/48

TC58FVT321/B321FT/XB-70,-10

AC CHARACTERISTICS AND OPERATING CONDITIONS

READ CYCLE

PRODUCT NAME

-70

-10

OUTPUT CAPACITANCE LOAD (C )

L

30pF

100pF

30pF

100pF

SYMBOL

PARAMETER

MIN MAX MIN MAX MIN MAX MIN MAX UNIT

t

Read Cycle Time

70



0



70

30



25

80



0



80

35



25

90



0



90

35



30

100



0



100

40

ns

RC

Address Access Time

CE Access Time

ACC

CE

OE Access Time

OE

CE to Output Low-Z

OE to Output Low-Z

Output Data Hold Time

CE to Output High-Z

OE to Output High-Z



CEE

OEE

OH

0



0



30

DF1

DF2

30

BLOCK PROTECT

SYMBOL

PARAMETER

MIN

MAX

UNIT

t

V

Transition Time

Set-up Time

4



µs

VPT

ID

VPS

CE Set-up Time

4

CESP

VPH

OE Hold Time

4

WE Low-Level Hold Time

100

PPLH

PROGRAM AND ERASE CHARACTERISTICS

SYMBOL

PARAMETER

Auto-Program Time (Byte Mode)

MIN

TYP.

MAX

UNIT



8

300

710

10

µs

s

t

PPW

Auto-Program Time (Word Mode)

Auto Chip Erase Time

11

50

0.7



t

PCEW

PBEW

EW

Auto Block Erase Time

Erase/Program Cycle

s

5

10



Cycles

2002-08-06 21/48

TC58FVT321/B321FT/XB-70,-10

COMMAND WRITE/PROGRAM/ERASE CYCLE

−70

−10

SYMBOL

PARAMETER

UNIT

MIN

70

0

MAX



90

300



20



30

1.5

1

MIN

100

0

MAX



90

300



20



30

1.5

1

t

Command Write Cycle Time

ns

µs

ns

µs

ns

µs

CMD

Address Set-up Time / BYTE Set-up Time

Address Hold Time / BYTE Hold Time

Address Hold Time from WE High level

Data Set-up Time

tAS

t

40

20

40

0

50

20

50

0

AH

AHW

DS

Data Hold Time

DH

WE Low-Level Hold Time

( WE Control)

( CE Control)

40

20

0

50

20

0

WELH

WEHH

CES

CEH

CELH

CEHH

WES

WEH

OES

OEHP

OEHT

AHT

WE High-Level Hold Time

CE Set-up Time to WE Active

CE Hold Time from WE High Level

CE Low-Level Hold Time

0

40

20

0

50

20

0

CE High-Level Hold Time

WE Set-up time to CE Active

WE Hold Time from CE High Level

OE Set-up Time

0

OE Hold Time (Toggle, Data Polling)

OE High-Level Hold Time (Toggle)

Address Hold Time (Toggle)

Address Set-up Time (Toggle)

Erase Hold Time

90

20

0

90

20

0

AST

50

500



500



0

50

500



500



0

BEH

VDS

V

Set-up Time

DD

Program/Erase Valid to RY/BY Delay

t

BUSY

Program/Erase Valid to RY/BY Delay during Suspend Mode

RESET Low-Level Hold Time

t

RP

RESET Low-Level to Read Mode

RY/BY Recovery Time

READY

RB

RESET Recovery Time

50

5

50

5

RH

CE Set-up time BYTE Transition

BYTE to Output High-Z

CEBTS

BTD



Program Suspend Command to Suspend Mode

Program Resume Command to Program Mode

Erase Suspend Command to Suspend Mode

Erase Resume Command to Erase Mode

SUSP

RESP

SUSE

RESE

15

1

15

1

2002-08-06 22/48

TC58FVT321/B321FT/XB-70,-10

TIMING DIAGRAMS

V

or V

Data invalid

IH

IL

Read / ID Read Operation

t

RC

Address

CE

t

OH

ACC

t

CE

t

OE

DF1

DF2

t

OEE

OE

t

CEE

AHW

t

OEH

WE

D

OUT

Hi-Z

Output data valid

Hi-Z

ID Read Operation (apply V_IDto A9)

t

RC

A0

A1

A6

t

ACC

V

ID

IH

t

VPS

A9

t

CE

t

OE

WE

Manufacturer

code

Device

code

D

OUT

Hi-Z

Read Mode

ID Read Mode

2002-08-06 23/48

TC58FVT321/B321FT/XB-70,-10

Command Write Operation

This is the timing of the Command Write Operation. The timing which is described in the following pages is

essentially the same as the timing shown on this page.

•

WE Control

t

CMD

Address

CE

Command address

t

AH

AS

t

CEH

CES

WE

t

WEHH

WEL

t

DH

DS

D

IN

Command data

•

CE Control

t

CMD

Address

CE

Command address

t

AH

AS

t

CEHH

CELH

t

WEH

WES

WE

t

DH

DS

D

IN

Command data

2002-08-06 24/48

TC58FVT321/B321FT/XB-70,-10

ID Read Operation (input command sequence)

Address

CE

555H

2AAH

BK + 555H

BK + 00H

BK + 01H

t

RC

CMD

OE

t

OES

WE

D

IN

AAH

90H

55H

Manufacturer code Device code

ID Read Mode

D

OUT

Hi-Z

Read Mode (input of ID Read command sequence)

(Continued)

Address

555H

2AAH

555H

t

CMD

CE

OE

WE

D

IN

AAH

F0H

55H

D

OUT

Hi-Z

ID Read Mode (input of Reset command sequence)

Read Mode

Note: Word Mode address shown.

BK: bank address

2002-08-06 25/48

TC58FVT321/B321FT/XB-70,-10

WE

Auto-Program Operation (

Control)

Address

CE

555H

2AAH

555H

PA

t

CMD

OE

t

OEHP

t

OES

t

PPW

WE

55H

A0H

PD

D

IN

AAH

D

OUT

Hi-Z

DQ7

D

OUT

t

VDS

V

DD

Note: Word Mode address shown.

PA: Program address

PD: Program data

WE

Auto Chip Erase / Auto Block Erase Operation (

Control)

Address

CE

555H

2AAH

555H

2AAH

555H/BA

t

CMD

OE

t

OES

WE

D

IN

AAH

55H

80H

AAH

55H

10H/30H

t

VDS

V

DD

Note: Word Mode address shown.

BA: Block address for Auto Block Erase operation

2002-08-06 26/48

TC58FVT321/B321FT/XB-70,-10

CE

Auto-Program Operation (

Control)

Address

CE

555H

2AAH

555H

PA

t

CMD

t

PPW

OE

t

OEHP

t

OES

WE

D

IN

55H

A0H

PD

AAH

D

OUT

Hi-Z

DQ7

D

OUT

t

VDS

V

DD

Note: Word Mode address shown.

PA: Program address

PD: Program data

CE

Auto Chip Erase / Auto Block Erase Operation (

Control)

Address

555H

2AAH

555H

2AAH

555H/BA

t

CMD

CE

OE

t

OES

WE

D

IN

AAH

55H

80H

AAH

55H

10H/30H

t

VDS

V

DD

Note: Word Mode address shown.

BA: Block address for Auto Block Erase operation

2002-08-06 27/48

TC58FVT321/B321FT/XB-70,-10

Program/Erase Suspend Operation

Address

BK

RA

CE

OE

WE

t

OE

D

IN

B0H

t

CE

D

OUT

Hi-Z

D

OUT

Hi-Z

t

/t

SUSP SUSE

RY/BY

Program/Erase Mode

RA: Read address

Suspend Mode

Program/Erase Resume Operation

Address

RA

BK

PA/BA

CE

OE

t

/t

RESP RESE

OES

WE

t

DF1

t

OE

DF2

D

IN

30H

t

CE

D

OUT

D

OUT

Hi-Z

Flag

Hi-Z

RY/BY

Suspend Mode

Program/Erase Mode

PA: Program address

BK: Bank address

BA: Block address

RA: Read address

Flag: Hardware Sequence flag

2002-08-06 28/48

TC58FVT321/B321FT/XB-70,-10

RY/BY

during Auto Program/Erase Operation

CE

Command input sequence

WE

During operation

t

BUSY

RY /BY

Hardware Reset Operation

WE

t

RB

RESET

RY/BY

t

RP

t

READY

RESET

Read after

t

RC

Address

RESET

t

RH

t

OH

ACC

D

OUT

Hi-Z

Output data valid

2002-08-06 29/48

TC58FVT321/B321FT/XB-70,-10

BYTE

during Read Operation

CE

t

CEBTS

OE

BYTE

t

BTD

DQ0~DQ7

DQ8~DQ14

DQ15/A-1

Data Output

t

ACC

Address Input

BYTE

during Write Operation

CE

WE

t

AS

BYTE

t

AH

2002-08-06 30/48

TC58FVT321/B321FT/XB-70,-10

DATA

Hardware Sequence Flag (

Polling)

Last

Address

CE

Command

PA/BA

Address

t

CMD

t

CE

DF1

DF2

t

OE

t

OEHP

WE

t

/t

t

OH

PPW PCEW PBEW

ACC

Last

D

IN

Command

Data

DQ7

DQ0~DQ6

RY/BY

DQ7

Valid

Invalid

Valid

t

BUSY

PA: Program address

BA: Block address

Hardware Sequence Flag (Toggle bit)

Address

t

AST

CE

OE

WE

t

AHT

t

CE

OEHT

t

AHT

t

OEHP

t

OE

Last

D

IN

Command

Data

Stop*

Toggle

DQ2/6

RY/BY

Toggle

Valid

t

BUSY

*DQ2/DQ6 stops toggling when auto operation has been completed.

2002-08-06 31/48

TC58FVT321/B321FT/XB-70,-10

Block Protect 1 Operation

Block Protect

Verify Block Protect

Address

A0

BA

A1

t

VPT

A6

V

ID

IH

A9

V

ID

IH

OE

t

VPS

t

VPH

t

PPLH

t

VPH

WE

t

OE

CESP

CE

D

OUT

Hi-Z

01H*

Hi-Z

BA: Block address

*: 01H indicates that block is protected.

2002-08-06 32/48

TC58FVT321/B321FT/XB-70,-10

Block Protect 2 Operation

Address

BA

t

BA

BA + 1

t

RC

CMD

A0

A1

A6

CE

OE

t

PPLH

WE

t

VPS

V

ID

IH

RESET

D

60H

Hi-Z

40H

60H

IN

t

OE

D

OUT

01H*

BA: Block address

BA + 1: Address of next block

*: 01H indicates that block is protected.

2002-08-06 33/48

TC58FVT321/B321FT/XB-70,-10

FLOWCHARTS

Auto Program

Start

Auto-Program Command Sequence

(see below)

DATA Polling or Toggle Bit

No

Last Address?

Address = Address + 1

Yes

Auto Program

Completed

Auto-Program Command Sequence (address/data)

555H/AAH

2AAH/55H

555H/A0H

Program Address/

Program Data

Note: The above command sequence takes place in Word Mode.

2002-08-06 34/48

TC58FVT321/B321FT/XB-70,-10

Fast Program

Start

Fast Program Set Command

Sequence (see below)

Fast Program Command Sequence

(see below)

DATA Polling or Toggle Bit

No

Last Address?

Yes

Address = Address + 1

Program Sequence

(see below)

Fast Program

Completed

Fast Program Set Command Sequence

(Address/Data)

Fast Program Command Sequence

(Address/Data)

Fast Program Reset Command Sequence

(Address/Data)

555H/AAH

2AAH/55H

555H/20H

XXXH/A0H

XXXH/90H

XXXH/F0H

Program Address/

Program Data

2002-08-06 35/48

TC58FVT321/B321FT/XB-70,-10

Auto Erase

Start

Auto Erase Command Sequence

(see below)

DATA Polling or Toggle Bit

Auto Erase

Completed

Auto Chip Erase Command Sequence

Auto Block / Auto-Multi Block Erase Command Sequence

(address/data)

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/10H

555H/80H

555H/AAH

2AAH/55H

Block Address/30H

Additional address

inputs during

Auto Multi-Block Erase

Block Address/30H

Note: The above command sequence takes place in Word Mode.

2002-08-06 36/48

TC58FVT321/B321FT/XB-70,-10

DATA

DQ7

Polling

Start

Read Byte (DQ0~DQ7)

Addr. = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

1)

1) : DQ7 must be rechecked even if DQ5 = 1

because DQ7 may change at the same

time as DQ5.

Read Byte (DQ0~DQ7)

Addr. = VA

Yes

DQ7 = Data?

No

Fail

Pass

DQ6 Toggle Bit

Start

Read Byte (DQ0~DQ7)

Addr. = VA

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

1)

1) : DQ6 must be rechecked even if DQ5 = 1

because DQ6 may stop toggling at the

same time that DQ5 changes to 1.

Read Byte (DQ0~DQ7)

Addr. = VA

No

DQ6 = Toggle?

Yes

Fail

Pass

VA: Byte address for programming

Any of the addresses within the block being erased during a Block Erase operation

“Don’t care” during a Chip Erase operation

Any address not within the current block during an Erase Suspend operation

2002-08-06 37/48

TC58FVT321/B321FT/XB-70,-10

Block Protect 1

Start

PLSCNT = 1

Set up Block Address

Addr. = BPA

Wait for 4 µs

OE = A9 = V , CE = V

ID

IL

Wait for 4 µs

WE = V

IL

Wait for 100 µs

WE = V

PLSCNT = PLSCNT + 1

IH

Wait for 4 µs

OE = V

IH

Wait for 4 µs

OE = V

IL

Verify Block Protect

No

Data = 01H?

PLSCNT = 25?

Yes

Protect Another Block?

No

Yes

Device Failed

Remove V from A9

ID

Block Protect

Complete

BPA: Block Address and ID Read Address (A6, A1, A0)

ID Read Address = (0, 1, 0)

2002-08-06 38/48

TC58FVT321/B321FT/XB-70,-10

Block Protect 2

Start

RESET = V

ID

Wait for 4 µs

PLSCNT = 1

Block Protect 2

Command First Bus Write Cycle

(XXXH/60H)

Set up Address

Addr. = BPA

Block Protect 2

Command Second Bus Write Cycle

(BPA/60H)

Wait for 100 µs

Block Protect 2

Command Third Bus Write Cycle

(XXXH/40H)

PLSCNT = PLSCNT + 1

Verify Block Protect

No

PLSCNT = 25?

Yes

No

Data = 01H?

Yes

Protect Another Block?

No

Yes

Remove V from RESET

ID

Remove V from RESET

ID

Reset Command

Device Failed

Reset Command

Block Protect

Complete

BPA: Block Address and ID Read Address (A6, A1, A0)

ID Read Address = (0, 1, 0)

2002-08-06 39/48

TC58FVT321/B321FT/XB-70,-10

BLOCK ERASE ADDRESS TABLES

(1) TC58FVT321 (top boot block)

BLOCK ADDRESS

BANK ADDRESS

A20 A19 A18 A17 A16 A15 A14 A13 A12

ADDRESS RANGE

BANK

#

BLOCK

#

BYTE MODE

WORD MODE

BA0

BA1

L

H

L

*

000000H~00FFFFH

010000H~01FFFFH

020000H~02FFFFH

030000H~03FFFFH

040000H~04FFFFH

050000H~05FFFFH

060000H~06FFFFH

070000H~07FFFFH

080000H~08FFFFH

090000H~09FFFFH

0A0000H~0AFFFFH

0B0000H~0BFFFFH

0C0000H~0CFFFFH

0D0000H~0DFFFFH

0E0000H~0EFFFFH

0F0000H~0FFFFFH

100000H~10FFFFH

110000H~11FFFFH

120000H~12FFFFH

130000H~13FFFFH

140000H~14FFFFH

150000H~15FFFFH

160000H~16FFFFH

170000H~17FFFFH

180000H~18FFFFH

190000H~19FFFFH

000000H~007FFFH

008000H~00FFFFH

010000H~017FFFH

018000H~01FFFFH

020000H~027FFFH

028000H~02FFFFH

030000H~037FFFH

038000H~03FFFFH

040000H~047FFFH

048000H~04FFFFH

050000H~057FFFH

058000H~05FFFFH

060000H~067FFFH

068000H~06FFFFH

070000H~077FFFH

078000H~07FFFFH

080000H~087FFFH

088000H~08FFFFH

090000H~097FFFH

098000H~09FFFFH

0A0000H~0A7FFFH

0A8000H~0AFFFFH

0B0000H~0B7FFFH

0B8000H~0BFFFFH

0C0000H~0C7FFFH

0C8000H~0CFFFFH

BA2

L

H

L

BA3

L

H

L

BK0

BK1

BK2

BA4

L

H

L

BA5

L

H

L

BA6

L

H

L

BA7

L

H

L

BA8

L

H

L

BA9

L

H

L

BA10

BA11

BA12

BA13

BA14

BA15

BA16

BA17

BA18

BA19

BA20

BA21

BA22

BA23

BA24

BA25

BA26

BA27

BA28

BA29

BA30

BA31

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

1A0000H~1AFFFFH 0D0000H~0D7FFFH

1B0000H~1BFFFFH 0D8000H~0DFFFFH

1C0000H~1CFFFFH 0E0000H~0E7FFFH

1D0000H~1DFFFFH 0E8000H~0EFFFFH

L

H

L

BK3

H

L

H

L

H

1E0000H~1EFFFFH

1F0000H~1FFFFFH

0F0000H~0F7FFFH

0F8000H~0FFFFFH

H

2002-08-06 40/48

TC58FVT321/B321FT/XB-70,-10

BLOCK ADDRESS

BANK ADDRESS

A20 A19 A18 A17 A16 A15 A14 A13 A12

ADDRESS RANGE

BANK

#

BLOCK

#

BYTE MODE

WORD MODE

BA32

BA33

BA34

BA35

BA36

BA37

BA38

BA39

BA40

BA41

BA42

BA43

BA44

BA45

BA46

BA47

BA48

BA49

BA50

BA51

BA52

BA53

BA54

BA55

BA56

BA57

BA58

BA59

BA60

BA61

BA62

H

L

H

L

*

200000H~20FFFFH

210000H~21FFFFH

220000H~22FFFFH

230000H~23FFFFH

240000H~24FFFFH

250000H~25FFFFH

260000H~26FFFFH

270000H~27FFFFH

280000H~28FFFFH

290000H~29FFFFH

2A0000H~2AFFFFH

2B0000H~2BFFFFH

2C0000H~2CFFFFH

2D0000H~2DFFFFH

2E0000H~2EFFFFH

2F0000H~2FFFFFH

300000H~30FFFFH

310000H~31FFFFH

320000H~32FFFFH

330000H~33FFFFH

340000H~34FFFFH

350000H~35FFFFH

360000H~36FFFFH

370000H~37FFFFH

380000H~38FFFFH

390000H~39FFFFH

100000H~107FFFH

108000H~10FFFFH

110000H~117FFFH

118000H~11FFFFH

120000H~127FFFH

128000H~12FFFFH

130000H~137FFFH

138000H~13FFFFH

140000H~147FFFH

148000H~14FFFFH

150000H~157FFFH

158000H~15FFFFH

160000H~167FFFH

168000H~16FFFFH

170000H~177FFFH

178000H~17FFFFH

180000H~187FFFH

188000H~18FFFFH

190000H~197FFFH

198000H~19FFFFH

1A0000H~1A7FFFH

1A8000H~1AFFFFH

1B0000H~1B7FFFH

1B8000H~1BFFFFH

1C0000H~1C7FFFH

1C8000H~1CFFFFH

L

H

L

H

L

BK4

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

BK5

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

BK6

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

3A0000H~3AFFFFH 1D0000H~1D7FFFH

3B0000H~3BFFFFH 1D8000H~1DFFFFH

3C0000H~3CFFFFH 1E0000H~1E7FFFH

3D0000H~3DFFFFH 1E8000H~1EFFFFH

BK7

L

H

L

H

L

H

L

H

3E0000H~3EFFFFH

1F0000H~1F7FFFH

2002-08-06 41/48

TC58FVT321/B321FT/XB-70,-10

BLOCK ADDRESS

BANK ADDRESS

A20 A19 A18 A17 A16 A15 A14 A13 A12

ADDRESS RANGE

BANK

#

BLOCK

#

BYTE MODE

WORD MODE

BA63

BA64

BA65

BA66

BA67

BA68

BA69

BA70

H

L

H

L

3F0000H~3F1FFFH

3F2000H~3F3FFFH

3F4000H~3F5FFFH

3F6000H~3F7FFFH

1F8000H~1F8FFFH

1F9000H~1F9FFFH

1FA000H~1FAFFFH

1FB000H~1FBFFFH

L

H

L

H

L

BK8

H

3F8000H~3F9FFFH 1FC000H~1FCFFFH

3FA000H~3FBFFFH 1FD000H~1FDFFFH

3FC000H~3FDFFFH 1FE000H~1FEFFFH

3FE000H~3FFFFFH 1FF000H~1FFFFFH

L

H

L

H

2002-08-06 42/48

TC58FVT321/B321FT/XB-70,-10

(2) TC58FVB321 (bottom boot block)

BLOCK ADDRESS

BANK ADDRESS

A20 A19 A18 A17 A16 A15 A14 A13 A12

ADDRESS RANGE

BANK

#

BLOCK

#

BYTE MODE

WORD MODE

BA0

BA1

L

H

L

H

L

H

*

L

H

L

H

*

L

H

L

H

L

H

L

H

*

000000H~001FFFH

002000H~003FFFH

004000H~005FFFH

006000H~007FFFH

008000H~009FFFH

00A000H~00BFFFH

00C000H~00DFFFH

00E000H~00FFFFH

010000H~01FFFFH

020000H~02FFFFH

030000H~03FFFFH

040000H~04FFFFH

050000H~05FFFFH

060000H~06FFFFH

070000H~07FFFFH

080000H~08FFFFH

090000H~09FFFFH

0A0000H~0AFFFFH

0B0000H~0BFFFFH

0C0000H~0CFFFFH

0D0000H~0DFFFFH

0E0000H~0EFFFFH

0F0000H~0FFFFFH

100000H~10FFFFH

110000H~11FFFFH

120000H~12FFFFH

130000H~13FFFFH

140000H~14FFFFH

150000H~15FFFFH

160000H~16FFFFH

170000H~17FFFFH

000000H~000FFFH

001000H~001FFFH

002000H~002FFFH

003000H~003FFFH

004000H~004FFFH

005000H~005FFFH

006000H~006FFFH

007000H~007FFFH

008000H~00FFFFH

010000H~017FFFH

018000H~01FFFFH

020000H~027FFFH

028000H~02FFFFH

030000H~037FFFH

038000H~03FFFFH

040000H~047FFFH

048000H~04FFFFH

050000H~057FFFH

058000H~05FFFFH

060000H~067FFFH

068000H~06FFFFH

070000H~077FFFH

078000H~07FFFFH

080000H~087FFFH

088000H~08FFFFH

090000H~097FFFH

098000H~09FFFFH

0A0000H~0A7FFFH

0A8000H~0AFFFFH

0B0000H~0B7FFFH

0B8000H~0BFFFFH

BA2

L

BA3

L

BK0

BK1

BK2

BA4

L

BA5

L

BA6

L

BA7

L

BA8

L

H

L

BA9

L

H

L

BA10

BA11

BA12

BA13

BA14

BA15

BA16

BA17

BA18

BA19

BA20

BA21

BA22

BA23

BA24

BA25

BA26

BA27

BA28

BA29

BA30

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

BK3

H

L

H

L

H

2002-08-06 43/48

TC58FVT321/B321FT/XB-70,-10

BLOCK ADDRESS

BANK ADDRESS

A20 A19 A18 A17 A16 A15 A14 A13 A12

ADDRESS RANGE

BANK

#

BLOCK

#

BYTE MODE

WORD MODE

BA31

BA32

BA33

BA34

BA35

BA36

BA37

BA38

BA39

BA40

BA41

BA42

BA43

BA44

BA45

BA46

BA47

BA48

BA49

BA50

BA51

BA52

BA53

BA54

BA55

BA56

BA57

BA58

BA59

BA60

BA61

BA62

L

H

L

H

L

H

L

*

180000H~18FFFFH

190000H~19FFFFH

0C0000H~0C7FFFH

0C8000H~0CFFFFH

L

H

L

1A0000H~1AFFFFH 0D0000H~0D7FFFH

1B0000H~1BFFFFH 0D8000H~0DFFFFH

1C0000H~1CFFFFH 0E0000H~0E7FFFH

1D0000H~1DFFFFH 0E8000H~0EFFFFH

L

H

L

BK4

BK5

BK6

BK7

L

H

L

H

L

H

L

1E0000H~1EFFFFH

1F0000H~1FFFFFH

200000H~20FFFFH

210000H~21FFFFH

220000H~22FFFFH

230000H~23FFFFH

240000H~24FFFFH

250000H~25FFFFH

260000H~26FFFFH

270000H~27FFFFH

280000H~28FFFFH

290000H~29FFFFH

2A0000H~2AFFFFH

2B0000H~2BFFFFH

2C0000H~2CFFFFH

2D0000H~2DFFFFH

2E0000H~2EFFFFH

2F0000H~2FFFFFH

300000H~30FFFFH

310000H~31FFFFH

320000H~32FFFFH

330000H~33FFFFH

340000H~34FFFFH

350000H~35FFFFH

360000H~36FFFFH

370000H~37FFFFH

0F0000H~0F7FFFH

0F8000H~0FFFFFH

100000H~107FFFH

108000H~10FFFFH

110000H~117FFFH

118000H~11FFFFH

120000H~127FFFH

128000H~12FFFFH

130000H~137FFFH

138000H~13FFFFH

140000H~147FFFH

148000H~14FFFFH

150000H~157FFFH

158000H~15FFFFH

160000H~167FFFH

168000H~16FFFFH

170000H~177FFFH

178000H~17FFFFH

180000H~187FFFH

188000H~18FFFFH

190000H~197FFFH

198000H~19FFFFH

1A0000H~1A7FFFH

1A8000H~1AFFFFH

1B0000H~1B7FFFH

1B8000H~1BFFFFH

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

2002-08-06 44/48

TC58FVT321/B321FT/XB-70,-10

BLOCK ADDRESS

BANK ADDRESS

A20 A19 A18 A17 A16 A15 A14 A13 A12

ADDRESS RANGE

BANK

#

BLOCK

#

BYTE MODE

WORD MODE

BA63

BA64

BA65

BA66

BA67

BA68

BA69

BA70

H

L

H

L

*

380000H~38FFFFH

390000H~39FFFFH

1C0000H~1C7FFFH

1C8000H~1CFFFFH

L

H

L

3A0000H~3AFFFFH 1D0000H~1D7FFFH

3B0000H~3BFFFFH 1D8000H~1DFFFFH

3C0000H~3CFFFFH 1E0000H~1E7FFFH

3D0000H~3DFFFFH 1E8000H~1EFFFFH

L

H

L

BK8

H

L

H

L

H

3E0000H~3EFFFFH

3F0000H~3FFFFFH

1F0000H~1F7FFFH

1F8000H~1FFFFFH

H

2002-08-06 45/48

TC58FVT321/B321FT/XB-70,-10

BLOCK SIZE TABLE

(1) TC58FVT321 (top boot block)

BLOCK SIZE

BLOCK

BANK SIZE

BANK

#

BLOCK COUNT

#

BYTE MODE

64 Kbytes

8 Kbytes

WORD MODE

BYTE MODE

512 Kbytes

448 Kbytes

64 Kbytes

WORD MODE

256 Kwords

224 Kwords

32 Kwords

BA0~BA7

BA8~BA15

BA16~BA23

BA24~BA31

BA32~BA39

BA40~BA47

BA48~BA55

BA56~BA62

BA63~BA70

32 Kwords

4 Kwords

BK0

BK1

BK2

BK3

BK4

BK5

BK6

BK7

BK8

8

7

8

(2) TC58FVB321 (bottom boot block)

BLOCK SIZE

BLOCK

BANK SIZE

BANK

#

BLOCK COUNT

#

BYTE MODE

8 Kbytes

WORD MODE

4 Kwords

BYTE MODE

64 Kbytes

WORD MODE

32 Kwords

BA0~BA7

BA8~BA14

BA15~BA22

BA23~BA30

BA31~BA38

BA39~BA46

BA47~BA54

BA55~BA62

BA63~BA70

BK0

BK1

BK2

BK3

BK4

BK5

BK6

BK7

BK8

8

7

8

64 Kbytes

32 Kwords

448 Kbytes

512 Kbytes

224 Kwords

256 Kwords

2002-08-06 46/48

TC58FVT321/B321FT/XB-70,-10

PACKAGE DIMENSIONS

Unit: mm

2002-08-06 47/48

TC58FVT321/B321FT/XB-70,-10

PACKAGE DIMENSIONS

Unit: mm

2002-08-06 48/48


型号：	TC58FVT321XB-70
厂家：	TOSHIBA
描述：	TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32-MBIT (4M X 8 BITS / 2M X 16 BITS) CMOS FLASH MEMORY 东芝MOS数字集成电路硅栅CMOS 32兆位（ 4M ×8位/ 2米x 16位） CMOS FLASH MEMORY 闪存存储内存集成电路栅
文件：	总48页 (文件大小：550K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC58FVT321XB-70 [TOSHIBA]

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