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TC58FYM5T3AXB70 [TOSHIBA]

IC 2M X 16 FLASH 3V PROM, 80 ns, PBGA56, 7 X 10 MM, 0.80 MM PITCH, PLASTIC, TFBGA-56, Programmable ROM;
TC58FYM5T3AXB70
型号： TC58FYM5T3AXB70
厂家： TOSHIBA    TOSHIBA
描述：

IC 2M X 16 FLASH 3V PROM, 80 ns, PBGA56, 7 X 10 MM, 0.80 MM PITCH, PLASTIC, TFBGA-56, Programmable ROM

可编程只读存储器 内存集成电路 闪存
文件： 总64页 (文件大小：544K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS  
32MBIT (4M × 8 BITS/2M × 16 BITS) CMOS FLASH MEMORY  
DESCRIPTION  
The TC58FYM5T2A/B2A/T3A/B3A is a 33554432-bit, 3.0-V read-only electrically erasable and programmable  
flash memory organized as 4194304 × 8 bits or as 2097152 × 16 bits. The TC58FYM5T2A/B2A/T3A/B3A features  
commands for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands  
are based on the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The  
TC58FYM5T2A/B2A/T3A/B3A also features a Simultaneous Read/Write operation so that data can be read during a  
Write or Erase operation.  
FEATURES  
•
•
•
•
Power supply voltage  
= 1.7 V~1.95 V  
Operating temperature  
Ta = −40°C~85°C  
Organization  
•
Organization of ４Banks  
V
DD  
Rate of Size  
BK0  
BK1  
BK2  
BK3  
TC58FVM5T2A  
TC58FVM5B2A  
TC58FVM5T3A  
TC58FVM5B3A  
1
1
3
1
3
3
3
1
3
3
1
3
1
1
1
3
4M × 8 bits/2M × 16 bits  
Functions  
Simultaneous Read/Write  
Page Read (8-word/16-byte)  
Auto Program, Auto Page Program  
Auto Block Erase, Auto Chip Erase  
Fast Program Mode/Acceleration Mode  
Program Suspend/Resume  
Erase Suspend/Resume  
•
•
•
Mode control  
Compatible with JEDEC standard commands  
Erase/Program cycles  
5
10 cycles typ.  
Access Time (Random/Page)  
V
CL = 30 pF  
CL = 100 pF  
DD  
Data Polling/Toggle Bit  
1.7~1.95 V  
70 ns/25 ns  
80 ns/35 ns  
Block Protection, Boot Block Protection  
Automatic Sleep, Support for Hidden ROM Area  
Common Flash Memory Interface (CFI)  
Byte/Word Modes  
Block erase architecture  
8 × 8 Kbytes/63 × 64 Kbytes  
Boot block architecture  
•
•
Power consumption  
25 µA (Standby)  
25 mA (Program operation)  
55 mA (Random Read operation)  
5 mA (Page Read operation)  
11 mA (Address Increment Read operation)  
Package  
TC58FYM5**AFT:  
TSOPI48-P-1220-0.50 (weight: 0.51 g)  
TC58FYM5**AXB:  
15 mA (Erase operation)  
•
•
TC58FYM5T2A/3A: top boot block  
TC58FYM5B2A/3A: bottom boot block  
P-TFBGA56-0710-0.80AZ (weight: 0.125 g)  
2004-10-06 1/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Ordering information  
TC58 F Y M5 T2 A FT 70  
Speed version  
70 = 70 ns  
Package  
FT = TSOP  
XB = FBGA  
Design rule  
A = 0.16 µm  
Function/Boot block architecture/Bank ratio  
T2 = Page mode/Top boot block/1:3:3:1  
B2 = Page mode/Bottom boot block/1:3:3:1  
T3 = Page mode/Top boot block/3:3:1:1  
B3 = Page mode/Bottom boot block/1:1:3:3  
Capacity  
M5 = 32Mbits  
Supply Voltage  
Y = 1.8 V system  
Device type  
F = NOR Flash memory  
2
Toshiba CMOS E PROM  
Ordering type  
Boot block  
Bank ratio  
1:3:3:1  
Package  
TC58FYM5T2AFT70  
TC58FYM5B2AFT70  
TC58FYM5T3AFT70  
TC58FYM5B3AFT70  
TC58FYM5T2AXB70  
TC58FYM5B2AXB70  
TC58FYM5T3AXB70  
TC58FYM5B3AXB70  
Top  
Bottom  
Top  
TSOPI48-P-1220-0.50  
3:3:1:1  
1:1:3:3  
Bottom  
Top  
1:3:3:1  
Bottom  
Top  
P-TFBGA56-0710-0.80AZ  
3:3:1:1  
1:1:3:3  
Bottom  
2004-10-06 2/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
PIN ASSIGNMENT (TOP VIEW)…TC58FYM5**AFT PIN NAMES  
A-1, A0~A20 Address Input  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
A16  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
DQ0~DQ15 Data Input/Output  
BYTE  
VSS  
2
3
CE  
OE  
Chip Enable Input  
DQ15/A-1  
DQ7  
4
5
Output Enable Input  
Word/Byte Select Input  
Write Enable Input  
Ready/Busy Output  
Hardware Reset Input  
DQ14  
DQ6  
6
7
BYTE  
WE  
A8  
DQ13  
DQ5  
8
A19  
A20  
WE  
9
DQ12  
DQ4  
10  
11  
RY/BY  
RESET  
VDD  
RESET 12  
NC  
DQ11  
DQ3  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
WP/ACC  
Write Protect/  
Program Acceleration Input  
DQ10  
DQ2  
RY/BY  
A18  
A17  
A7  
WP/ACC  
DQ9  
NC  
Not Connected  
Power Supply  
Ground  
DQ1  
A6  
DQ8  
V
DD  
A5  
DQ0  
A4  
OE  
V
SS  
A3  
VSS  
A2  
CE  
A0  
A1  
PIN ASSIGNMENT (TOP VIEW)…TC58FYM5**AXB  
1
2
3
4
5
6
7
8
A
B
C
D
E
F
NC  
NC  
NC  
NC  
A3  
A4  
A2  
A1  
A0  
CΕ  
OE  
A7  
A17  
A6  
RY/BY  
WP/ACC  
A18  
WE  
RESET  
NC  
A9  
A8  
A13  
A12  
A10  
A14  
A5  
A20  
A19  
A11  
A15  
G
H
J
DQ0  
DQ8  
DQ9  
DQ1  
DQ2  
DQ5  
DQ7  
DQ14  
DQ13  
DQ6  
A16  
DQ10  
DQ11  
DQ3  
DQ12  
BYTE  
DQ15  
V
DD  
DQ4  
K
L
V
V
SS  
SS  
NC  
NC  
NC  
NC  
M
2004-10-06 3/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK DIAGRAM  
V
DD  
SS  
V
RY/BY  
DQ0  
DQ15  
RY/BY Buffer  
I/O Buffer  
WP/ACC  
WE  
Control Circuit  
BYTE  
RESET  
CE  
Data Latch  
Command Register  
OE  
Memory Cell  
Array  
Memory Cell  
Array  
Memory Cell  
Array  
Memory Cell  
Array  
Bank0  
Bank1  
Bank2  
Bank3  
A0  
A20  
A-1  
2004-10-06 4/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
MODE SELECTION  
BYTE MODE WORD MODE  
(1)  
MODE  
CE OE WE A9  
A6  
A1  
A0 RESET WP/ACC DQ0~DQ7  
DQ0~DQ15  
Read/Page Read  
ID Read (Manufacturer Code)  
ID Read (Device Code)  
Standby  
L
L
L
H
*
L
L
H
H
H
*
A9  
A6  
L
A1  
L
A0  
L
H
H
H
H
*
*
*
*
*
*
*
*
*
*
*
*
L
D
D
OUT  
OUT  
V
V
Code  
Code  
Code  
Code  
ID  
ID  
L
L
L
H
*
*
*
*
*
High-Z  
High-Z  
High-Z  
High-Z  
Output Disable  
H
H
H
(2)  
*
*
*
*
Write  
L
L
L
L
*
A9  
A6  
L
A1  
H
H
H
*
A0  
L
H
H
D
D
IN  
IN  
(2)  
Block Protect 1  
V
V
*
*
ID  
ID  
Block Protect 2  
H
L
*
H
H
*
*
L
L
V
*
Code  
*
*
Code  
*
ID  
Verify Block Protect  
Temporary Block Unprotect  
Hardware Reset/Standby  
Boot Block Protect  
V
L
L
H
ID  
*
*
*
V
ID  
*
*
*
*
*
*
*
*
L
High-Z  
*
High-Z  
*
*
*
*
*
*
*
*
Notes: * = V or V , L = V , H = V  
IH IL IL  
IH  
(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.  
Addresses are A20~A0 in Word Mode ( BYTE = V ), A20~A-1 in Byte Mode ( BYTE = V ).  
IH  
IL  
(2) Pulse input  
ID CODE TABLE  
(1)  
CODE TYPE  
A20~A12  
A6  
A1  
A0  
CODE (HEX)  
Manufacturer Code  
Device Code  
*
*
*
*
*
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
H
L
0098h  
0059h  
0069h  
005Ah  
006Ah  
TC58FYM5T2A  
TC58FYM5B2A  
TC58FYM5T3A  
TC58FYM5B3A  
(2)  
(3)  
Verify Block Protect  
BA  
Data  
Notes: * = V or V , L = V , H = V  
IH IL IL  
IH  
(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.  
(2) BA: Block Address  
(3) 0001h - Protected Block  
0000h - Unprotected Block  
2004-10-06 5/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
COMMAND SEQUENCES  
BUS  
FIRST BUS  
WRITE CYCLE  
SECOND BUS  
WRITE CYCLE  
THIRD BUS  
WRITE CYCLE  
FOURTH BUS  
WRITE CYCLE  
FIFTH BUS  
WRITE CYCLE  
SIXTH BUS  
WRITE CYCLE  
COMMAND  
SEQUENCE  
WRITE  
CYCLES  
REQ’D  
Addr.  
Data Addr.  
Data  
55h  
55h  
Addr. Data  
Addr.  
Data  
Addr.  
Data  
Addr.  
Data  
Read/Reset  
1
XXXh  
555h  
F0h  
Word  
Byte  
2AAh  
555h  
555h  
F0h  
(1)  
(2)  
Read/Reset  
3
AAh  
RA  
RD  
AAAh  
AAAh  
(3)  
BK  
+
Word  
Byte  
555h  
2AAh  
555h  
555h  
(4)  
IA  
(5)  
ID  
ID Read  
3
4
AAh  
90h  
(3)  
BK  
+
AAAh  
AAAh  
555h  
AAAh  
555h  
AAAh  
Word  
Byte  
Word  
Byte  
555h  
AAAh  
555h  
AAAh  
2AAh  
555h  
2AAh  
555h  
(6)  
(7)  
Auto-Program  
AAh  
AAh  
55h  
55h  
A0h  
E6h  
PA  
PD  
11  
19  
1
Auto  
(6)  
(7)  
(6)  
(7)  
(6)  
(7)  
PA  
PD  
PA  
PD  
PA  
PD  
PageProgram  
(3)  
Program Suspend  
Program Resume  
BK  
(3)  
B0h  
30h  
1
BK  
Auto Chip  
Erase  
Word  
555h  
AAAh  
555h  
AAAh  
2AAh  
555h  
2AAh  
555h  
555h  
AAAh  
555h  
AAAh  
555h  
AAAh  
555h  
AAAh  
2AAh  
555h  
2AAh  
555h  
555h  
6
6
AAh  
AAh  
55h  
55h  
80h  
80h  
AAh  
AAh  
55h  
55h  
10h  
30h  
Byte  
Word  
Byte  
AAAh  
Auto Block  
Erase  
(8)  
BA  
(3)  
Block Erase Suspend  
Block Erase Resume  
Block Protect 2  
1
1
4
BK  
B0h  
30h  
(3)  
BK  
(9)  
(9)  
(10)  
XXXh  
60h BPA  
60h  
55h  
XXXh  
(3)  
40h BPA  
BPD  
BK  
+
Word  
555h  
2AAh  
555h  
Verify Block  
Protect  
(9)  
(10)  
3
AAh  
AAh  
90h BPA  
BPD  
(3)  
BK  
+
Byte  
AAAh  
555h  
AAAh  
Word  
Byte  
555h  
AAAh  
XXXh  
XXXh  
555h  
AAAh  
555h  
AAAh  
555h  
AAAh  
555h  
AAAh  
2AAh  
555h  
Fast Program  
Set  
3
55h  
20h  
88h  
555h  
(6)  
AAAh  
(7)  
Fast Program  
2
2
A0h PA  
PD  
(13)  
Fast Program Reset  
90h XXXh F0h  
2AAh  
Word  
555h  
AAAh  
555h  
AAAh  
555h  
AAAh  
555h  
AAAh  
Hidden ROM  
Mode Entry  
3
4
6
4
2
AAh  
AAh  
AAh  
AAh  
55h  
Byte  
Word  
Byte  
Word  
Byte  
Word  
Byte  
Word  
Byte  
555h  
2AAh  
555h  
2AAh  
555h  
2AAh  
555h  
Hidden ROM  
Program  
(6)  
PA  
(7)  
PD  
55h  
A0h  
80h  
90h  
555h  
2AAh  
555h  
Hidden ROM  
Erase  
(8)  
55h  
55h  
AAh  
00h  
55h  
BA  
30h  
AAAh  
Hidden ROM  
Mode Exit  
XXXh  
(3)  
BK + 55h  
Query  
Command  
(11)  
(12)  
CD  
98h CA  
(3)  
BK +AAh  
Notes: The system should generate the following address patterns:  
Word Mode: 555h or 2AAh on address pins A10~A0  
Byte Mode: AAAh or 555h on address pins A10~A-1  
(1) RA: Read Address  
(2) RD: Read Data  
(3) BK: Bank Address = A20~A18  
(4) IA: Bank Address and ID Read Address (A6, A1, A0)  
Bank Address = A20~A18  
Manufacturer Code = (0, 0, 0)  
Device Code = (0, 0, 1)  
(5) ID: ID Data  
(6) PA: Program Address  
DQ8~DQ15 are ignored in Word Mode.  
(7) PD: Program Data  
(8) BA: Block Address = A20~A12  
(9) BPA: Block Address and ID Read Address (A6, A1, A0)  
Block Address = A20~A12  
ID Read Address = (0, 1, 0)  
(10) BPD: Verify Data  
(11) CA: CFI Address  
(12) CD: CFI Data  
(13) F0h: 00h is valid too  
(Input continuous 8 address from (A0, A1, A2) = (0, 0, 0) to (A0, A1, A2) = (1, 1, 1) in Page program.)  
2004-10-06 6/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
SIMULTANEOUS READ/WRITE OPERATION  
The TC58FYM5T2A/B2A/T3A/B3A features a Simultaneous Read/Write operation. The Simultaneous Read/Write  
operation enables the device to simultaneously write data to or erase data from one bank while reading data from  
another bank.  
The TC58FYM5T2A/B2A/T3A/B3A has a total of four banks (4Mbits: 12Mbits: 12Mbits: 4Mbits). It is possible to  
switch between banks using the bank addresses (A20~A18). For a description of bank blocks and addresses, refer to  
the Block Address Table and Block Size Table.  
The Simultaneous Read/Write operation cannot perform multiple operations within a single bank. The table  
below shows the operation modes in which simultaneous operation can be performed.  
Note that during Auto-Program execution or Auto Block Erase operation, the Simultaneous Read/Write  
operation cannot read data from addresses in the same bank which have not been selected for operation. However,  
data from these addresses can be read using the Program Suspend or Erase Suspend function.  
SIMULTANEOUS READ/WRITE OPERATION  
STATUS OF BANK ON WHICH OPERATION IS BEING  
STATUS OF OTHER BANKS  
PERFORMED  
Read Mode  
(1)  
ID Read Mode  
Auto-Program Mode  
Auto-Page Program Mode  
(2)  
Fast Program Mode  
Program Suspend Mode  
Read Mode  
Auto Block Erase Mode  
(3)  
Auto Multiple Block Erase Mode  
Erase Suspend Mode  
Program during Erase Suspend  
Program Suspend during Erase Suspend  
CFI Mode  
(1) Only Command Mode is valid.  
(2) Including times when Acceleration Mode is in use.  
(3) If the selected blocks are spread across all four banks, simultaneous operation cannot be carried out.  
OPERATION MODES  
In addition to the Read, Write and Erase Modes, the TC58FYM5T2A/B2A/T3A/B3A features many functions  
including block protection and data polling. When incorporating the device into a design, refer to the timing charts  
and flowcharts in combination with the description below.  
READ MODE (PAGE READ)  
To read data from the memory cell array, set the device to Read Mode. In Read Mode, the device can perform  
high-speed random access and Page Read as an asynchronous ROM. The page size of the device is 8 words or 16  
bytes, with the appropriate page address being selected using address A0-A2 (and A-1 in byte mode).  
The device is automatically set to Read Mode immediately after power-on or on completion of automatic  
operation. A software reset releases ID Read Mode and the lock state which the device enters if an automatic  
operation ends abnormally, and sets the device to Read Mode. A hardware reset terminates operation of the  
device and resets it to Read Mode. When reading data without changing the address immediately after  
power-on, either input a hardware reset or change CE from H to L.  
2004-10-06 7/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
ID Read Mode  
ID Read Mode is used to read the device maker code and device code. The mode is useful in that it allows  
EPROM programmers to identify the device type automatically.  
ID read can be executed in two ways, as follows:  
(1) Applying V to A9  
ID  
This method is used mainly by EPROM programmers. Applying V to A9 sets the device to ID Read  
ID  
Mode, outputting the maker code from address 00H and the device code from address 01H. Releasing V  
from A9 returns the device to Read Mode. With this method, all banks are set to ID Read Mode; thus,  
simultaneous operation cannot be performed.  
ID  
(2) Input command sequence  
With this method, simultaneous operation can be performed. Inputting an ID Read command sets the  
specified bank to ID Read Mode. Banks are specified by inputting the bank address (BK) in the third Bus  
Write cycle of the Command cycle. To read an ID code, the bank address as well as the ID read address must  
be specified (with WP/ACC = V or V ). The maker code is output from address BK + 00; the device code  
IH  
IL  
is output from address BK + 01. From other banks data is output from the memory cells. Inputting a Reset  
command releases ID Read Mode and returns the device to Read Mode.  
Access time in ID Read Mode is the same as that in Read Mode. For a list of the codes, refer to the ID  
Code Table.  
Standby Mode  
There are two ways to put the device into Standby Mode.  
(1) Control using CE and RESET  
With the device in Read Mode, input V  
± 0.3 V to CE and RESET . The device will enter Standby  
DD  
Mode and the current will be reduced to the standby current (I ). However, if the device is in the  
DDS1  
process of performing simultaneous operation, the device will not enter Standby Mode but will instead  
cause the operating current to flow.  
(2) Control using RESET only  
With the device in Read Mode, input V ± 0.3 V to RESET . The device will enter Standby Mode and the  
SS  
current will be reduced to the standby current (I ). Even if the device is in the process of performing  
DDS1  
simultaneous operation, this method will terminate the current operation and set the device to Standby  
Mode. This is a hardware reset and is described later.  
In Standby Mode DQ is put in High-Impedance state.  
Auto-Sleep Mode  
This function suppresses power dissipation during reading. If the address input does not change for 150 ns,  
the device will automatically enter Sleep Mode and the current will be reduced to the standby current (I  
).  
DDS2  
However, if the device is in the process of performing simultaneous operation, the device will not enter Standby  
Mode but will instead cause the operating current to flow. Because the output data is latched, data is output in  
Sleep Mode. When the address is changed, Sleep Mode is automatically released, and data from the new  
address is output.  
Output Disable Mode  
Inputting V to OE disables output from the device and sets DQ to High-Impedance.  
IH  
2004-10-06 8/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Command Write  
The TC58FYM5T2A/B2A/T3A/B3A uses the standard JEDEC control commands for a single-power supply  
2
E PROM. A Command Write is executed by inputting the address and data into the Command Register. The  
command is written by inputting a pulse to WE with CE = V and OE = V ( WE control). The command  
IL  
IH  
can also be written by inputting a pulse to CE with WE = V (CE control). The address is latched on the  
IL  
falling edge of either WE or CE . The data is latched on the rising edge of either WE or CE . DQ0~DQ7 are  
valid for data input and DQ8~DQ15 are ignored.  
To abort input of the command sequence, use the Reset command. The device will reset the Command  
Register and enter Read Mode. If an undefined command is input, the Command Register will be reset and the  
device will enter Read Mode.  
Software Reset  
Apply a software reset by inputting a Read/Reset command. A software reset returns the device from ID Read  
Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and  
clears the Command Register.  
Hardware Reset  
A hardware reset initializes the device and sets it to Read Mode. When a pulse is input to RESET for t  
,
RP  
the device abandons the operation which is in progress and enters Read Mode after t  
. Note that if a  
READY  
hardware reset is applied during data overwriting, such as a Write or Erase operation, data at the address or  
block being written to at the time of the reset will become undefined.  
After a hardware reset the device enters Read Mode if RESET = V or Standby Mode if RESET = V  
.
IH  
IL  
The DQ pins are High-Impedance when RESET = V . After the device has entered Read Mode, Read  
IL  
operations and input of any command are allowed.  
Comparison between Software Reset and Hardware Reset  
ACTION  
SOFTWARE RESET  
HARDWARE RESET  
Releases ID Read Mode or CFI Mode.  
True  
True  
True  
False  
True  
True  
True  
True  
Clears the Command Register.  
Releases the lock state if automatic operation has ended abnormally.  
Stops any automatic operation which is in progress.  
Stops any operation other than the above and returns the device to  
Read Mode.  
False  
True  
BYTE/Word Mode  
BYTE is used to select Word Mode (16 bits) or Byte Mode (8 bits) for the TC58FYM5T2A/B2A/T3A/B3A. If  
is input to BYTE , the device will operate in Word Mode. Read data or write commands using DQ0~DQ15.  
V
IH  
When V is input to BYTE , read data or write commands using DQ0~DQ7. DQ15/A-1 is used as the lowest  
IL  
address. DQ8~DQ14 will become High-Impedance.  
2004-10-06 9/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Auto-Program Mode  
The TC58FYM5T2A/B2A/T3A/B3A can be programmed in either byte or word units. Auto-Program Mode is  
set using the Program command. The program address is latched on the falling edge of the WE signal and  
data is latched on the rising edge of the fourth Bus Write cycle (with WE control). Auto programming starts on  
the rising edge of the WE signal in the fourth Bus Write cycle. The Program and Program Verify commands  
are automatically executed by the chip. The device status during programming is indicated by the Hardware  
Sequence flag. To read the Hardware Sequence flag, specify the address to which the Write is being performed.  
During Auto Program execution, a command sequence for the bank on which execution is being performed  
cannot be accepted. To terminate execution, use a hardware reset. Note that if the Auto-Program operation is  
terminated in this manner, the data written so far is invalid.  
Any attempt to program a protected block is ignored. In this case the device enters Read Mode 3 µs after the  
rising edge of the WE signal in the fourth bus write cycle.  
If an Auto-Program operation fails, the device remains in the programming state and does not automatically  
return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or  
a hardware reset is required to return the device to Read Mode after a failure. If a programming operation fails,  
the block which contains the address to which data could not be programmed should not be used. To build a  
more reliable system, the host processor should take measures to prevent subsequent use of failed blocks.  
The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into  
cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device  
error. A cell containing 0 must be erased in order to set it to 1.  
Auto-Page Program Mode  
Auto-Page Program is a function which enables simultaneous programming of 8-word or 16-byte data.  
In this mode, the Program time for 32 Mbits is less than 60% compared with Auto program mode. In word  
mode, input the page program command during the first bus write cycle to the third bus write cycle. Input the  
program data and address of (A0, A1, A2) = (0, 0, 0) in the fourth bus write cycle. Input the increment address  
and program data in the period from the fifth bus write cycle to the eleventh bus write cycle. After input of the  
eleventh bus write cycle, this operation starts. In byte mode, input the increment address and program data of  
(A-1, A0, A1, A2) = (0, 0, 0, 0) … (A-1, A0, A1, A2) = (1, 1, 1, 1) in the period from the fifth bus write cycle to the  
nineteenth bus write cycle.  
Fast Program Mode  
Fast Program is a function which enables execution of the command sequence for the Auto Program to be  
completed in two cycles. In this mode the first two cycles of the command sequence, which normally requires  
four cycles, are omitted. Writing is performed in the remaining two cycles. To execute Fast Program, input the  
Fast Program command. Write in this mode uses the Fast Program command but operation is the same at that  
for ordinary Auto-Program. The status of the device is indicated by the Hardware Sequence flag and read  
operations can be performed as usual. To exit this mode, the Fast Program Reset command must be input.  
When the command is input, the device will return to Read Mode.  
Acceleration Mode  
The TC58FYM5T2A/B2A/T3A/B3A features Acceleration Mode which allows write time to be reduced.  
Applying V  
to WP or ACC automatically sets the device to Acceleration Mode. In Acceleration Mode, Block  
ACC  
Protect Mode changes to Temporary Block Unprotect Mode. Write Mode changes to Fast Program Mode. Modes  
are switched by the WP/ACC signal; thus, there is no need for a Temporary Block Unprotect operation or to set  
or reset Fast Program Mode. Operation of Write is the same as in Auto-Program Mode. Removing V  
WP/ACC terminates Acceleration Mode.  
from  
ACC  
2004-10-06 10/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Program Suspend/Resume Mode  
Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a  
Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but  
ignores the command in other modes. When the command is input, the address of the bank on which Write is  
being performed must be specified. After input of the command, the device will enter Program Suspend Read  
Mode after t  
.
SUSP  
During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write  
is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read  
are the same as usual.  
After completion of Program Suspend input a Program Resume command to return to Write Mode. When  
inputting the command, specify the address of the bank on which Write is being performed. If the ID Read or  
CFI Data Read functions is being used, abort the function before inputting the Resume command. On receiving  
the Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag  
for the bank to which data is being written.  
Program Suspend can be run in Fast Program Mode or Acceleration Mode. However, note that when running  
Program Suspend in Acceleration Mode, V  
must not be released.  
ACC  
Auto Chip Erase Mode  
The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the  
rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and  
verified as erased by the chip. The device status is indicated by the Hardware Sequence flag.  
Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase  
operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence an additional  
Erase operation must be performed.  
Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not  
be executed and the device will enter Read mode 250µs after the rising edge of the WE signal in the sixth bus  
cycle.  
If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to Read  
Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware  
reset is required to return the device to Read Mode after a failure.  
In this case it cannot be ascertained which block the failure occurred in. Either abandon use of the device  
altogether, or perform a Block Erase on each block, identify the failed blocks, and stop using them. To build a  
more reliable system, the host processor should take measures to prevent subsequent use of failed blocks.  
2004-10-06 11/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Auto Block Erase/Auto Multi-Block Erase Modes  
The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The  
block address is latched on the falling edge of the WE signal in the sixth bus cycle. The block erase starts as  
soon as the Erase Hold Time (t  
) has elapsed after the rising edge of the WE signal. When multiple blocks  
BEH  
are erased, the sixth Bus Write cycle is repeated with each block address and Auto Block Erase command being  
input within the Erase Hold Time (this constitutes an Auto Multi-Block Erase operation). If a command other  
than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time, the  
device will reset the Command Register and enter Read Mode. The Erase Hold Time restarts on each successive  
rising edge of WE . Once operation starts, all memory cells in the selected block are automatically  
preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the setting of  
the Hardware Sequence flag. When the Hardware Sequence flag is read, the addresses of the blocks on which  
auto-erase operation is being performed must be specified. If the selected blocks are spread across all nine  
banks, simultaneous operation cannot be carried out.  
All commands (except Erase Suspend) are ignored during an Auto Block Erase or Auto Multi-Block Erase  
operation. Either operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it  
cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing.  
Any attempt to erase a protected block is ignored. If all the selected blocks are protected, the auto-erase  
operation is not executed and the device returns to Read Mode 250µs after the rising edge of the WE signal in  
the last bus cycle.  
If an auto-erase operation fails, the device remains in Erasing state and does not return to Read Mode. The  
device status is indicated by the Hardware Sequence flag. After a failure either a Reset command or a Hardware  
Reset is required to return the device to Read Mode. If multiple blocks are selected, it will not be possible to  
ascertain the block in which the failure occurred. In this case either abandon use of the device altogether, or  
perform a Block Erase on each block, identify the failed blocks, and stop using them. To build a more reliable  
system, the host processor should take measures to prevent subsequent use of failed blocks.  
Erase Suspend/Erase Resume Modes  
Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block.  
The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other  
operation modes. When the command is input, the address of the bank on which Erase is being performed must  
be specified.  
In Erase Suspend Mode only a Read, Program or Resume command can be accepted. If an Erase Suspend  
command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after t  
. The  
SUSE  
device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is  
read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output  
will stop toggling and RY/BY will be set to High-Impedance.  
Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has  
not been selected for the Auto Block Erase. Data is written in the usual manner.  
To resume the Auto Block Erase, input an Erase Resume command. On input of the command, the address of  
the bank on which the Write was being performed must be specified. On receiving an Erase Resume command,  
the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend  
command is input during the Erase Hold Time, the device will return to the state it was in at the start of the  
Erase Hold Time. At this time, more blocks can be specified for erasing. If an Erase Resume command is input  
during an Auto Block Erase, Erase resumes. At this time, toggle output of DQ6 resumes and 0 is output on  
RY/BY .  
2004-10-06 12/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK PROTECTION  
Block protection is a function for disabling writing and erasing specific blocks. Block protection can be carried  
out in two ways: by supplying a high voltage (V ) to the device (see Block Protect 1) or by supplying a high  
ID  
voltage and a command sequence (see Block Protect 2).  
(1) Block Protect 1  
Specify a device block address and make the following signal settings A9 = OE = V , A1 = V and CE  
ID  
IH  
= A0 = A6 = V . Now when a pulse is input to WE for t  
, the device will start to write to the block  
IL  
PPLH  
protection circuit. Block protection can be verified using the Verify Block Protect command. Inputting V  
IL  
on OE sets the device to Verify Mode. 01h is output if the block is protected and 00h is output if the block  
is unprotected. If block protection was unsuccessful, the operation must be repeated. Releasing V from A9  
ID  
and OE terminates this mode.  
(2) Block Protect 2  
Applying V to RESET and inputting the Block Protect 2 command also performs block protection. The  
ID  
first cycle of the command sequence is the Set-up command. In the second cycle, the Block Protect command  
is input, in which a block address and A1 = V and A0 = A6 = V are specified. Now the device writes to  
IH  
IL  
the block protection circuit. There is a wait of t  
until this write is completed; however, no intervention  
PPLH  
is necessary during this time. In the third cycle the Verify Block Protect command is input. This command  
verifies the write to the block protection circuit. Read is performed in the fourth cycle. If the protection  
operation is complete, 01h is output. If a value other than 01h is output, block protection is not complete  
and the Block Protect command must be input again. Removing the V input from RESET exits this  
ID  
mode.  
Temporary Block Unprotection  
The TC58FYM5T2A/B2A/T3A/B3A has a temporary block unprotection feature which disables block  
protection for all protected blocks. Unprotection is enabled by applying V to the RESET pin. Now Write and  
ID  
Erase operations can be performed on all blocks except the boot blocks which have been protected by the Boot  
Block Protect operation. The device returns to its previous state when V is removed from the RESET pin.  
ID  
That is, previously protected blocks will be protected again.  
Verify Block Protect  
The Verify Block Protect command is used to ascertain whether a block is protected or unprotected.  
Verification is performed either by inputting the Verify Block Protect command or by applying V to the A9 pin.  
ID  
The Verify Block Protect command, which can be performed simultaneously with operations in another bank, is  
performed by setting the block address with A0 = A6 = V and A1 = V . If the block is protected, 01h is output.  
IL  
IH  
If the block is unprotected, 00h is output.  
Inputting the verify block protect command sequence sets the specified bank to the Verify Block Protect mode.  
Inputting a Reset command releases this mode and returns the device to Read Mode. In the verifying of block  
protect across a bank boundary, a Reset command is needed when a bank is changed.  
Boot Block Protection  
Boot block protection temporarily protects certain boot blocks using a method different from ordinary block  
protection. Neither V nor a command sequence is required. Protection is performed simply by inputting V  
ID  
IL  
on WP/ACC . The target blocks are the two pairs of boot blocks. The top boot blocks are BA69 and BA70; the  
bottom boot blocks are BA0 and BA1. Inputting V on WP/ACC releases the mode. From now on, if it is  
IH  
necessary to protect these blocks, the ordinary Block Protection Mode must be used.  
2004-10-06 13/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Hidden ROM Area  
The TC58FYM5T2A/B2A/T3A/B3A features a 64-Kbyte hidden ROM area, which is separate from the memory  
cells. The area consists of one block. Data Read, Write and Protect can be performed on this block. Because  
Protect cannot be released, data in the block cannot be overwritten once the block is protected.  
The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS  
TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters  
Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations  
are the same as auto operations except that the device is in Hidden ROM Mode. To protect the hidden ROM  
area, use the block protection function. The operation of Block Protect here is the same as a normal Block  
Protect except that V rather than V is input to RESET . Once the block has been protected, protection  
IH  
ID  
cannot be released, even using the temporary block unprotection function. Use Block Protect carefully. Note that  
in Hidden ROM Mode, simultaneous operation cannot be performed for BANK3 in top boot type and for BANK0  
in bottom boot type.  
To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read  
Mode.  
HIDDEN ROM AREA ADDRESS TABLE  
BYTE MODE  
ADDRESS RANGE  
WORD MODE  
ADDRESS RANGE  
BOOT BLOCK  
ARCHITECTURE  
TYPE  
SIZE  
SIZE  
TC58FYM5T2A  
TC58FYM5T3A  
TOP BOOT BLOCK  
3F0000h~3FFFFFh  
000000h~00FFFFh  
64 Kbytes  
1F8000h~1FFFFFh  
000000h~007FFFh  
32 Kwords  
TC58FYM5B2A  
TC58FYM5B3A  
BOTTOM BOOT BLOCK  
64 Kbytes  
32 Kwords  
2004-10-06 14/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
COMMON FLASH MEMORY INTERFACE (CFI)  
The TC58FYM5T2A/B2A/T3A/B3A conforms to the CFI specifications. To read information from the device,  
input the Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode,  
input the Reset command.  
CFI CODE TABLE  
ADDRESS A6~A0  
DATA DQ15~DQ0  
DESCRIPTION  
10h  
11h  
12h  
0051h  
0052h  
0059h  
ASCII string “QRY”  
13h  
14h  
0002h  
0000h  
Primary OEM command set  
2: AMD/FJ standard type  
15h  
16h  
0040h  
0000h  
Address for primary extended table  
17h  
18h  
0000h  
0000h  
Alternate OEM command set  
0: none exists  
19h  
1Ah  
0000h  
0000h  
Address for alternate OEM extended table  
V
(min) (Write/Erase)  
DD  
1Bh  
1Ch  
0017h  
0019h  
DQ7~DQ4: 1 V  
DQ3~DQ0: 100 mV  
V
(max) (Write/Erase)  
DD  
DQ7~DQ4: 1 V  
DQ3~DQ0: 100 mV  
1Dh  
1Eh  
1Fh  
20h  
21h  
22h  
23h  
24h  
25h  
26h  
27h  
0000h  
0000h  
0004h  
0000h  
000Ah  
0000h  
0005h  
0000h  
0004h  
0000h  
0016h  
V
V
(min) voltage  
(max) voltage  
PP  
PP  
N
Typical time-out per single byte/word write (2 µs)  
N
Typical time-out for minimum size buffer write (2 µs)  
N
Typical time-out per individual block erase (2 ms)  
N
Typical time-out for full chip erase (2 ms)  
N
Maximum time-out for byte/word write (2 times typical)  
N
Maximum time-out for buffer write (2 times typical)  
N
Maximum time-out per individual block erase (2 times typical)  
N
Maximum time-out for full chip erase (2 times typical)  
N
Device Size (2 byte)  
28h  
29h  
0002h  
0000h  
Flash device interface description  
2: ×8/×16  
2Ah  
2Bh  
0004h  
0000h  
N
Maximum number of bytes in multi-byte write (2 )  
2004-10-06 15/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
ADDRESS A6~A0  
2Ch  
DATA DQ15~DQ0  
0002h  
DESCRIPTION  
Number of erase block regions within device  
2Dh  
2Eh  
2Fh  
30h  
0007h  
0000h  
0020h  
0000h  
Erase Block Region 1 information  
Bits 0~15: y = block number  
Bits 16~31: z = block size  
(z × 256 bytes)  
31h  
32h  
33h  
34h  
003Eh  
0000h  
0000h  
0001h  
Erase Block Region 2 information  
ASCII string “PRI”  
40h  
41h  
42h  
0050h  
0052h  
0049h  
43h  
44h  
0031h  
0031h  
Major version number, ASCII  
Minor version number, ASCII  
Address-Sensitive Unlock  
0: Required  
45h  
46h  
47h  
0000h  
0002h  
0001h  
1: Not required  
Erase Suspend  
0: Not supported  
1: For Read-only  
2: For Read & Write  
Block Protect  
0: Not supported  
X: Number of blocks per group  
Block Temporary Unprotect  
0: Not supported  
48h  
49h  
4Ah  
0001h  
0004h  
0001h  
1: Supported  
Block Protect/Unprotect scheme  
Simultaneous operation  
0: Not supported  
1: Supported  
Burst Mode  
4Bh  
4Ch  
0000h  
0001h  
0: Not supported  
Page Mode  
0: Not supported  
1: Supported  
V
V
(min) voltage  
ACC  
4Dh  
4Eh  
4Fh  
50h  
0085h  
00C6h  
000Xh  
0001h  
DQ7~DQ4: 1 V  
DQ3~DQ0: 100 mV  
(max) voltage  
ACC  
DQ7~DQ4: 1 V  
DQ3~DQ0: 100 mV  
Top/Bottom Boot Block Flag  
2: TC58FYM5B2A  
3: TC58FYM5T2A  
Program Suspend  
0: Not supported  
1: Supported  
2004-10-06 16/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
ADDRESS A6~A0  
57h  
DATA DQ15~DQ0  
0004h  
DESCRIPTION  
Bank Organization  
00h: Data at 4Ah is zero  
X: Number of Banks  
Bank0 Region information  
X = Number of blocks in Bank0  
58h  
59h  
5Ah  
5Bh  
00XXh  
00XXh  
00XXh  
00XXh  
TC58FYM5T2A: 08h  
TC58FYM5T3A: 18h  
TC58FYM5B2A: 0Fh  
TC58FYM5B3A: 0Fh  
Bank1 Region information  
X = Number of blocks in Bank1  
TC58FYM5T2A: 18h  
TC58FYM5T3A: 18h  
TC58FYM5B2A: 18h  
TC58FYM5B3A: 08h  
Bank2 Region information  
X = Number of blocks in Bank2  
TC58FYM5T2A: 18h  
TC58FYM5T3A: 08h  
TC58FYM5B2A: 18h  
TC58FYM5B3A: 18h  
Bank3 Region information  
X = Number of blocks in Bank3  
TC58FYM5T2A: 0Fh  
TC58FYM5T3A: 0Fh  
TC58FYM5B2A: 08h  
TC58FYM5B3A: 18h  
2004-10-06 17/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
HARDWARE SEQUENCE FLAGS  
The TC58FYM5T2A/B2A/T3A/B3A has a Hardware Sequence flag which allows the device status to be  
determined during an auto mode operation. The output data is read out using the same timing as that used when  
CE = OE = V in Read Mode. The RY/BY output can be either High or Low.  
IL  
The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The  
Hardware Sequence flag is read to determine the device status and the result of the operation is verified by  
comparing the read-out data with the original data.  
STATUS  
DQ7  
(4)  
DQ6  
DQ5  
DQ3  
DQ2  
RY/BY  
Auto Programming/Auto Page Programming  
DQ7  
Toggle  
Data  
0
0
1
Data  
Toggle  
1
0
(1)  
Read in Program Suspend  
Data  
Data  
Data  
High-Z  
(2)  
Selected  
0
0
Toggle  
Toggle  
Toggle  
Toggle  
1
0
0
0
0
0
Erase Hold Time  
(3)  
Not-selected  
Selected  
0
In Auto  
Erase  
0
0
1
Toggle  
1
0
In Progress  
Auto Erase  
Read  
Not-selected  
Selected  
0
0
1
0
1
0
0
Toggle  
Data  
Toggle  
1
High-Z  
Not-selected  
Selected  
Data  
Data  
Data  
0
Data  
0
High-Z  
In Erase  
Suspend  
(4)  
DQ7  
DQ7  
DQ7  
0
Toggle  
Toggle  
Toggle  
Toggle  
Toggle  
0
0
0
0
0
Programming  
(4)  
(4)  
Not-selected  
0
0
Auto Programming/Auto Page Programming  
Auto Erase  
1
0
1
Time Limit  
Exceeded  
1
1
NA  
(4)  
Programming in Erase Suspend  
DQ7  
1
0
NA  
Notes: DQ outputs cell data and RY/BY goes High-Impedance when the operation has been completed.  
DQ0 and DQ1 pins are reserved for future use.  
0 is output on DQ0, DQ1 and DQ4.  
(1) Data output from an address to which Write is being performed is undefined.  
(2) Output when the block address selected for Auto Block Erase is specified and data is read from there.  
During Auto Chip Erase, all blocks are selected.  
(3) Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is  
read from there.  
(4) For the Page program: program data of (A0, A1, A2) = (1, 1, 1) in eleventh bus write cycle in word mode; program data  
of (A-1, A0, A1, A2) = (1, 1, 1, 1) in nineteenth bus write cycle in byte mode.  
DQ7 (D
ATA
 
polling)  
During an Auto-Program or auto-erase operation, the device status can be determined using the data polling  
function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation,  
DQ7 outputs inverted data during the programming operation and outputs actual data after programming has  
finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase  
operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data.  
When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE  
signal.  
2004-10-06 18/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
DQ6 (Toggle bit 1)  
The device status can be determined by the Toggle Bit function during an Auto-Program or auto-erase  
operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately  
outputs a 0 or a 1 for each OE access while CE = V while the device is busy. When the internal operation  
IL  
has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the  
operation fails, the DQ6 output toggles.  
If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around  
3 µs. It will then stop toggling. If an attempt is made to execute an auto erase operation on a protected block,  
DQ6 will toggle for around 250 µs. It will then stop toggling. After toggling has stopped the device will return to  
Read Mode.  
DQ5 (internal time-out)  
If the internal timer times out during a Program or Erase operation, DQ5 outputs a 1. This indicates that the  
operation has not been completed within the allotted time.  
Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case DQ5  
outputs a 1. Either a hardware reset or a software reset command is required to return the device to Read  
Mode.  
DQ3 (Block Erase timer)  
The Block Erase operation starts 50 µs (the Erase Hold Time) after the rising edge of WE in the last  
command cycle. DQ3 outputs a 0 for the duration of the Block Erase Hold Time and a 1 when the Block Erase  
operation starts. Additional Block Erase commands can only be accepted during the Block Erase Hold Time.  
Each Block Erase command input within the hold time resets the timer, allowing additional blocks to be marked  
for erasing. DQ3 outputs a 1 if the Program or Erase operation fails.  
DQ2 (Toggle bit 2)  
DQ2 is used to indicate which blocks have been selected for Auto Block Erase or to indicate whether the  
device is in Erase Suspend Mode.  
If data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle.  
Now 1 will be output from non-selected blocks, allowing the selected block to be ascertained. If data is read  
continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ2  
output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in Erase  
Suspend Mode. If data is read from the address to which data is being written during Erase Suspend in  
Programming Mode, DQ2 will output a 1.  
RY/BY  
BUSY  
)
(READY/  
The TC58FYM5T2A/B2A/T3A/B3A has a RY/BY signal to indicate the device status to the host processor. A  
0 (Busy state) indicates that an Auto-Program or auto-erase operation is in progress. A 1 (Ready state) indicates  
that the operation has finished and that the device can now accept a new command. RY/BY outputs a 0 when  
an operation has failed.  
RY/BY outputs a 0 after the rising edge of WE in the last command cycle.  
During an Auto Block Erase operation, commands other than Erase Suspend are ignored. RY/BY outputs a  
1 during an Erase Suspend operation. The output buffer for the RY/BY pin is an open-drain type circuit,  
allowing a wired-OR connection. A pull-up resistor must be inserted between V  
and the RY/BY pin.  
DD  
2004-10-06 19/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
DATA PROTECTION  
The TC58FYM5T2A/B2A/T3A/B3A includes a function which guards against malfunction or data corruption.  
Protection against Program/Erase Caused by Low Supply Voltage  
To prevent malfunction at power-on or power-down, the device will not accept commands while V  
is below  
DD  
V
LKO  
If V  
. In this state, command input is ignored.  
drops below V  
during an Auto Operation, the device will terminate Auto-Program execution. In  
DD  
LKO  
this case, Auto operation is not executed again when V  
return to recommended V  
voltage Therefore  
DD  
DD  
command input is necessary to execute Auto operation again.  
If VDD > VLKO, take corrective action to ensure that commands may be accurately input on the system side.  
Protection against Malfunction Caused by Glitches  
To prevent malfunction during operation caused by noise from the system, the device will not accept pulses  
shorter than 3 ns (Typ.) input on WE , CE or OE . However, if a glitch exceeding 3 ns (Typ.) occurs and the  
glitch is input to the device malfunction may occur.  
The device uses standard JEDEC commands. It is conceivable that, in extreme cases, system noise may be  
misinterpreted as part of a command sequence input and that the device will acknowledge it. In this case, even  
if a proper command is input, the device may not operate. To avoid this possibility, clear the Command Register  
before command input. In an environment prone to system noise, Toshiba recommend input of a software or  
hardware reset before command input.  
Protection against Malfunction at Power-on  
To prevent damage to data caused by sudden noise at power-on, when power is turned on with WE = CE =  
V
IL  
the device does not latch the command on the first rising edge of WE or CE . Instead, the device  
automatically resets the Command Register and enters Read Mode.  
2004-10-06 20/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
ABSOLUTE MAXIMUM RATINGS  
SYMBOL  
PARAMETER  
RANGE  
UNIT  
V
V
V
V
V
P
V
Supply Voltage  
DD  
−0.6~2.5  
V
V
DD  
(1)  
(1)  
Input Voltage  
−0.5~V  
+ 0.5  
IN  
DD  
DD  
Input/Output Voltage  
−0.5~V  
+ 0.5  
V
DQ  
(2)  
Maximum Input Voltage for A9, OE and RESET  
13.0  
13.0  
600  
260  
V
IDH  
(2)  
Maximum Input Voltage for WP/ACC  
V
ACCH  
D
Power Dissipation  
mW  
°C  
°C  
°C  
mA  
T
T
T
Soldering Temperature (10s)  
Storage Temperature  
Operating Temperature  
solder  
stg  
−55~150  
−40~85  
100  
opr  
(3)  
I
Output Short-Circuit Current  
OSHORT  
(1) This level may undershoot to −2.0 V for periods < 20 ns, and may overshoot to +2.0 V for periods < 20 ns.  
(2) Do not apply VID/VACC when the supply voltage is not within the recommended operating voltage range of the device.  
(3) Outputs should be shorted for no more than one second.  
No more than one output should be shorted at a time.  
CAPACITANCE (Ta = 25°C, f = 1 MHz)  
TSOPI  
SYMBOL  
PARAMETER  
CONDITION  
MAX  
UNIT  
C
C
C
Input Pin Capacitance  
Output Pin Capacitance  
Control Pin Capacitance  
V
V
V
= 0 V  
IN  
4
8
8
pF  
pF  
pF  
IN  
= 0 V  
OUT  
IN2  
OUT  
= 0 V  
IN  
This parameter is periodically sampled and is not tested for every device.  
TFBGA  
SYMBOL  
PARAMETER  
CONDITION  
MAX  
UNIT  
C
C
C
Input Pin Capacitance  
Output Pin Capacitance  
Control Pin Capacitance  
V
V
V
= 0 V  
IN  
4
8
9
pF  
pF  
pF  
IN  
= 0 V  
OUT  
IN2  
OUT  
= 0 V  
IN  
This parameter is periodically sampled and is not tested for every device.  
RECOMMENDED DC OPERATING CONDITIONS  
SYMBOL  
PARAMETER  
MIN  
1.7  
MAX  
1.95  
UNIT  
V
V
V
V
V
V
Supply Voltage  
DD  
DD  
Input High-Level Voltage  
Input Low-Level Voltage  
0.8 × V  
−0.3  
11.4  
8.5  
V
+ 0.3  
DD  
IH  
DD  
V
0.2 × V  
12.6  
12.6  
85  
IL  
DD  
High-Level Voltage for A9, OE and RESET  
High-Level Voltage for WP/ACC  
Operating Temperature  
ID  
ACC  
Ta  
−40  
°C  
2004-10-06 21/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
DC CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITION  
MIN  
TYP.  
MAX  
UNIT  
I
I
Input Leakage Current  
Output Leakage Current  
Output High Voltage  
Output Low Voltage  
0 V ≤ V ≤ V  
±1  
±1  
LI  
LO  
IN  
DD  
µA  
0 V ≤ V  
≤ V  
OUT  
DD  
V
V
I
= −0.1 mA  
= 0.1 mA  
V
− 0.1  
DD  
OH  
OL  
OH  
OL  
V
I
0.1  
V
Average Random Read  
V
= V /V , I = 0 mA  
IH IL OUT  
DD  
Current  
IN  
I
42  
55  
DDO1  
t
= t = 100 ns (MIN)  
CYCLE  
RC  
I
I
V
V
V
Average Program Current  
Average Erase Current  
Average  
V
V
V
= V /V , I  
IH IL OUT  
= 0 mA  
= 0 mA  
= 0 mA  
19  
13  
25  
15  
DDO2  
DDO3  
DD  
DD  
DD  
IN  
= V /V , I  
IH IL OUT  
IN  
= V /V , I  
IH IL OUT  
IN  
I
I
I
I
61  
55  
19  
1
80  
70  
25  
5
DDO4  
DDO5  
DDO6  
DDO7  
Read-While-Program Current  
t
= t  
= 100 ns (MIN)  
RC  
CYCLE  
V
Average  
V
= V /V , I  
IH IL OUT  
= 0 mA  
DD  
Read-while-Erase Current  
IN  
mA  
t
= t  
= 100 ns (MIN)  
RC  
CYCLE  
V
Average Program-While-  
DD  
Erase-Suspend Current  
V
V
= V /V , I  
IH IL OUT  
= 0 mA  
IN  
V
Average Page Read  
DD  
Current  
= V /V , I  
IH IL OUT  
= 0 mA  
= 0 mA  
IN  
IN  
V
t
= V /V , I  
IH IL OUT  
V
Average Address  
DD  
Increment Read Current  
I
= 100 ns (MIN)  
7
11  
(2)  
DDO8  
RC  
PRC  
t
= 100 ns (MIN)  
CE = RESET = V  
DD  
I
I
I
I
V
V
Standby Current  
Standby Current  
2
2
25  
25  
35  
DDS1  
DDS2  
ID  
DD  
DD  
or RESET = V  
SS  
V
V
= V  
IH  
IL  
DD  
SS  
µA  
(1)  
(Automatic Sleep Mode  
)
= V  
High-Voltage Input Current for  
A9, OE and RESET  
11.4 V ≤ V ≤ 12.6 V  
ID  
High-Voltage Input Current for  
WP/ACC  
8.5 V ≤ V  
≤ 12.6 V  
ACC  
20  
mA  
V
ACC  
V
Low-V  
Lock-out Voltage  
DD  
1.0  
1.55  
LKO  
(1) The device enters Automatic Sleep Mode in which the address remains fixed for during 150 ns.  
(2) (I + I × 7)/8words  
DDO1  
DDO7  
AC TEST CONDITIONS  
PARAMETER  
CONDITION  
Input Pulse Level  
V
, 0.0 V  
DD  
Input Pulse Rise and Fall Time (10%~90%)  
Timing Measurement Reference Level (input)  
Timing Measurement Reference Level (output)  
Output Load  
5 ns  
VDD/2, VDD/2  
VDD/2, VDD/2  
C (100 pF) + 1 TTL Gate/C (30 pF) + 1 TTL Gate  
L
L
2004-10-06 22/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
AC CHARACTERISTICS AND OPERATING CONDITIONS  
READ CYCLE  
Product name  
TC58FYM5T2A/B2A/T3A/B3A  
VDD = 1.7-1.95 V  
30 pF 100 pF  
VDD voltage (V)  
Output load capacitance (CL)  
UNIT  
SYMBOL  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
t
Read Cycle Time  
70  
25  
0
70  
70  
25  
25  
25  
25  
80  
35  
0
80  
80  
35  
35  
25  
25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
t
t
t
t
t
t
t
t
t
t
t
Page Read Cycle Time  
Address Access Time  
CE Access Time  
PRC  
ACC  
CE  
OE Access Time  
OE  
Page Access Time  
PACC  
OEH  
CEE  
OEE  
OH  
OE High-Level Hold Time (read)  
CE to Output Low-Z  
OE to Output Low-Z  
Output Data Hold Time  
CE to Output High-Z  
OE to Output High-Z  
0
0
0
0
0
0
DF1  
DF2  
BLOCK PROTECT  
SYMBOL  
PARAMETER  
MIN  
MAX  
UNIT  
t
t
t
t
t
V
V
Transition Time  
Set-up Time  
4
4
µs  
µs  
µs  
µs  
µs  
VPT  
ID  
ID  
VPS  
CE Set-up Time  
4
CESP  
VPH  
OE Hold Time  
4
WE Low-Level Hold Time  
100  
PPLH  
PROGRAM AND ERASE CHARACTERISTICS  
SYMBOL  
PARAMETER  
Auto-Program Time (Byte Mode)  
MIN  
TYP.  
MAX  
UNIT  
10  
11  
400  
400  
3000  
µs  
t
PPW  
Auto-Program Time (Word Mode)  
Auto-Page program time  
µs  
t
t
t
t
57  
50  
0.7  
µs  
PPAW  
PCEW  
PBEW  
EW  
(1)  
Auto Chip Erase Time  
s
s
(1)  
(2)  
13  
Auto Block Erase Time  
5
Erase/Program Cycle  
10  
Cycles  
(1) Auto Chip Erase Time and Auto Block Erase Time include internal pre program time.  
(2) Minimum interval between resume and the following suspend command is 8 ms. If this is shorter than 8 ms, auto block erase  
time is expanded to more than maximum (13 s).  
2004-10-06 23/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
COMMAND WRITE/PROGRAM/ERASE CYCLE  
SYMBOL  
PARAMETER  
UNIT  
MIN  
65  
0
MAX  
90  
350  
20  
30  
4.0  
6.5  
1
t
Command Write Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
ns  
ns  
ns  
µs  
ns  
ns  
ns  
ns  
µs  
µs  
µs  
µs  
µs  
CMD  
Address Set-up Time/ BYTE Set-up Time  
Address Hold Time/ BYTE Hold Time  
Data Set-up Time  
tAS  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
30  
30  
0
AH  
DS  
Data Hold Time  
DH  
WE Low-Level Hold Time  
( WE Control)  
( WE Control)  
( WE Control)  
( WE Control)  
( CE Control)  
( CE Control)  
( CE Control)  
( CE Control)  
30  
20  
0
WELH  
WEHH  
CES  
WE High-Level Hold Time  
CE Set-up Time to WE Active  
CE Hold Time from WE High Level  
CE Low-Level Hold Time  
0
CEH  
CELH  
CEHH  
WES  
WEH  
OES  
OEHP  
OEHT  
CEHT  
AHT  
30  
20  
0
CE High-Level Hold Time  
WE Set-up time to CE Active  
WE Hold Time from CE High Level  
OE Set-up Time  
0
0
OE Hold Time (Toggle, Data Polling)  
OE High-Level Hold Time (Toggle)  
CE High-Level Hold Time (Toggle)  
Address Hold Time (Toggle)  
Address Set-up Time (Toggle)  
Erase Hold Time  
10  
20  
20  
0
0
AST  
50  
500  
500  
0
BEH  
VDS  
V
Set-up Time  
DD  
Program/Erase Valid to RY/BY Delay  
t
BUSY  
Program/Erase Valid to RY/BY Delay during Suspend Mode  
RESET Low-Level Hold Time  
t
t
t
t
t
t
t
t
t
t
t
RP  
RESET Low-Level to Read Mode  
READY  
RB  
RY/BY Recovery Time  
RESET Recovery Time  
50  
5
RH  
CE Set-up time BYTE Transition  
CEBTS  
BTD  
BYTE to Output High-Z  
Program Suspend Command to Suspend Mode  
Page Program Suspend Command to Suspend Mode  
Program Resume Command to Program Mode  
Erase Suspend Command to Suspend Mode  
Erase Resume Command to Erase Mode  
SUSP  
SUSPA  
RESP  
SUSE  
RESE  
20  
1
2004-10-06 24/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
TIMING DIAGRAMS  
V
or V  
IL  
Data invalid  
IH  
Read/ID Read Operation  
t
RC  
Address  
CE  
t
t
OH  
ACC  
t
CE  
t
t
t
OE  
DF1  
DF2  
t
OEE  
OE  
t
CEE  
t
OEH  
WE  
D
OUT  
Hi-Z  
Output data Valid  
Hi-Z  
ID Read Operation (apply VID to A9)  
t
RC  
A0  
A1  
A6  
t
ACC  
V
V
ID  
IH  
t
VPS  
A9  
CE  
OE  
WE  
t
CE  
t
OE  
Manufacturer  
code  
Device  
code  
D
OUT  
Hi-Z  
Hi-Z  
Hi-Z  
Read Mode  
Read Mode  
ID Read Mode  
Page Read Operation  
2004-10-06 25/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Address(A3-20)
Address(0-2)  
t
t
PRC  
RC  
t
ACC  
t
CE  
CE  
OE  
WE  
t
OE  
t
PACC  
D
OUT  
Hi-Z  
DOUT  
DOUT DOUT DOUT DOUT DOUT DOUT DOUT  
Hi-Z  
Read after command input (Only Hidden Rom/CFI Read)  
Last command address  
Address  
CE  
OE  
WE  
tWEHH+tACC  
Hi-Z  
Command data  
D
OUT  
D
OUT  
valid  
Hi-Z  
2004-10-06 26/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Command Write Operation  
This is the timing of the Command Write Operation. The timing which is described in the following pages is  
essentially the same as the timing shown on this page.  
•
WE Control  
t
CMD  
Address  
CE  
Command address  
t
t
AH  
AS  
t
t
CEH  
CES  
WE  
t
t
WEHH  
WEL  
t
t
DH  
DS  
D
IN  
Command data  
•
CE Control  
t
CMD  
Address  
CE  
Command address  
t
t
AH  
AS  
t
t
CEHH  
CELH  
t
t
WEH  
WES  
WE  
t
t
DH  
DS  
D
IN  
Command data  
2004-10-06 27/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
ID Read Operation (input command sequence)  
Address  
CE  
555h  
2AAh  
BK + 555h  
BK + 00h  
BK + 01h  
t
t
RC  
CMD  
OE  
t
OES  
WE  
D
IN  
AAh  
90h  
55h  
Manufacturer code Device code  
ID Read Mode  
D
OUT  
Hi-Z  
Read Mode (input of ID Read command sequence)  
(Continued)  
Address  
555h  
2AAh  
555h  
t
CMD  
CE  
OE  
WE  
D
IN  
AAh  
F0h  
55h  
D
OUT  
Hi-Z  
ID Read Mode (input of Reset command sequence)  
Read Mode  
Note: Word Mode address shown.  
BK: Bank address  
2004-10-06 28/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
WE  
Auto-Program Operation (  
Control)  
Address  
CE  
555h  
2AAh  
555h  
PA  
PA  
t
CMD  
OE  
t
OEHP  
t
OES  
t
PPW  
WE  
55h  
A0h  
PD  
D
IN  
AAh  
D
OUT  
Hi-Z  
DQ7  
D
OUT  
t
VDS  
V
DD  
Note: Word Mode address shown.  
PA: Program address  
PD: Program data  
2004-10-06 29/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
WE  
Auto Page Program Operation (  
Control)  
PA  
PA  
7h  
Address (A3-20)  
t
CMD  
555h  
2AAh  
0h  
1h  
2h  
3h  
4h  
5h  
6h  
7h  
555h  
Address (A0-2)  
CE  
OE  
WE  
t
OEHP  
t
OES  
t
PPAW  
AAh  
55h  
E6h  
PD1  
PD2  
PD3  
PD4  
PD5  
PD6  
PD7  
PD8  
D
IN  
D
OUT  
DQ7 DOUT  
Hi-Z  
t
VDS  
V
DD  
Note: Word Mode address shown.  
PA: Program address  
PD: Program Data  
2004-10-06 30/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Auto Chip Erase/Auto Block Erase Operation (  
Control)  
WE  
Address  
CE  
555h  
2AAh  
555h  
555h  
2AAh  
555h/BA  
t
CMD  
OE  
t
OES  
WE  
D
IN  
AAh  
55h  
80h  
AAh  
55h  
10h/30h  
t
VDS  
V
DD  
Note: Word Mode address shown.  
BA: Block address for Auto Block Erase operation  
Auto-Program Operation (  
Control)  
CE  
Address  
CE  
555h  
2AAh  
555h  
PA  
PA  
t
CMD  
t
PPW  
OE  
t
OEHP  
t
OES  
WE  
D
IN  
55h  
A0h  
PD  
AAh  
D
OUT  
Hi-Z  
DQ7  
D
OUT  
t
VDS  
V
DD  
Note: Word Mode address shown.  
PA: Program address  
PD: Program data  
2004-10-06 31/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Auto Page Program Operation (  
Control)  
CE  
PA  
PA  
7h  
Address (A3-20)  
t
CMD  
555h  
2AAh  
555h  
0h  
1h  
2h  
3h  
4h  
5h  
6h  
7h  
Address (A0-2)  
CE  
OE  
WE  
t
OEHP  
t
OES  
t
PPAW  
AAh  
55h  
E6h  
PD1  
PD2  
PD3  
PD4  
PD5  
PD6  
PD7  
PD8  
D
IN  
D
OUT  
DQ7 DOUT  
Hi-Z  
t
VDS  
V
DD  
Note: Word Mode address shown.  
PA: Program address  
PD: Program data  
2004-10-06 32/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Auto Chip Erase/Auto Block Erase Operation (CE Control)  
Address  
555h  
2AAh  
555h  
555h  
2AAh  
555h/BA  
t
CMD  
CE  
OE  
t
OES  
WE  
D
IN  
AAh  
55h  
80h  
AAh  
55h  
10h/30h  
t
VDS  
V
DD  
Note: Word Mode address shown.  
BA: Block address for Auto Block Erase operation  
2004-10-06 33/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Program/Erase Suspend Operation  
Address  
BK  
RA  
CE  
OE  
WE  
t
OE  
D
IN  
B0h  
t
CE  
D
OUT  
Hi-Z  
D
OUT  
Hi-Z  
t
/t  
SUSP SUSE  
RY/BY  
Program/Erase Mode  
RA: Read address  
Suspend Mode  
Program/Erase Resume Operation  
Address  
RA  
BK  
PA/BA  
CE  
OE  
t
t
/t  
RESP RESE  
OES  
WE  
t
DF1  
t
t
OE  
DF2  
D
IN  
30h  
t
CE  
D
OUT  
D
OUT  
Hi-Z  
Flag  
Hi-Z  
RY/BY  
Suspend Mode  
Program/Erase Mode  
PA: Program address  
BK: Bank address  
BA: Block address  
RA: Read address  
Flag: Hardware Sequence flag  
2004-10-06 34/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
RY/BY  
during Auto Program/Erase Operation  
CE  
Command input sequence  
WE  
During operation  
t
BUSY  
RY /BY  
Hardware Reset Operation  
WE  
t
RB  
RESET  
RY/BY  
t
RP  
t
READY  
RESET  
Read after  
t
RC  
Address  
RESET  
t
RH  
t
t
OH  
ACC  
D
OUT  
Hi-Z  
Output data valid  
2004-10-06 35/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BYTE  
during Read Operation  
CE  
t
CEBTS  
OE  
BYTE  
t
BTD  
DQ0~DQ7  
DQ8~DQ14  
DQ15/A-1  
Address  
Data Output  
Data Output  
Data Output  
Data Output  
t
ACC  
Address Input  
Address Input  
•
Byte → Word  
CE  
t
CEBTS  
OE  
BYTE  
t
BTD  
DQ0~DQ7  
DQ8~DQ14  
DQ15/A-1  
Address  
Data Output  
Data Output  
Data Output  
Data Output  
t
ACC  
Address Input  
2004-10-06 36/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BYTE  
during Write Operation  
CE  
WE  
t
AS  
BYTE  
t
AH  
2004-10-06 37/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
DATA  
Hardware Sequence Flag (  
Polling)  
Last  
Address  
CE  
Command  
Address  
PA/BA  
t
CMD  
t
t
t
CE  
t
DF1  
DF2  
OE  
OE  
t
OEHP  
WE  
t
/t  
/t  
t
t
OH  
PPW PCEW PBEW  
ACC  
Last  
D
IN  
Command  
Data  
DQ7  
DQ0~DQ6  
RY/BY  
DQ7  
Valid  
Valid  
Valid  
Invalid  
Valid  
t
BUSY  
PA: Program address  
BA: Block address  
Hardware Sequence Flag (Toggle bit)  
Address  
t
t
AST  
AST  
CE  
OE  
WE  
t
AHT  
t
t
CE  
OEHT  
t
CEHT  
t
AHT  
t
OEHP  
t
OE  
Last  
D
IN  
Command  
Data  
Stop*  
DQ2/6  
RY/BY  
Toggle  
Toggle  
Toggle  
Valid  
Toggle  
t
BUSY  
*DQ2/DQ6 stops toggling when auto operation has been completed.  
2004-10-06 38/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Block Protect 1 Operation  
Block Protect  
Verify Block Protect  
Address  
A0  
BA  
A1  
t
VPT  
A6  
V
ID  
IH  
V
A9  
V
V
ID  
IH  
OE  
t
VPS  
t
VPH  
t
PPLH  
t
VPH  
WE  
t
t
OE  
CESP  
CE  
D
OUT  
Hi-Z  
01h*  
Hi-Z  
BA: Block address  
*: 01h indicates that the block is protected.  
2004-10-06 39/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Block Protect 2 Operation  
Address  
BA  
BA  
t
BA  
BA + 1  
t
t
t
RC  
CMD  
CMD  
CMD  
A0  
A1  
A6  
CE  
OE  
WE  
t
PPLH  
t
VPS  
V
V
ID  
IH  
RESET  
D
IN  
60h  
60h  
40h  
60h  
t
OE  
D
OUT  
Hi-Z  
01h*  
BA: Block address  
BA + 1: Address of next block  
*: 01h indicates that the block is protected.  
2004-10-06 40/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
FLOWCHARTS  
Auto-Program  
Start  
Auto-Program Command Sequence  
(see below)  
DATA Polling or Toggle Bit  
No  
Last Address?  
Yes  
Address = Address + 1  
Auto-Program  
Completed  
Auto-Program Command Sequence (address/data)  
555h/AAh  
2AAh/55h  
555h/A0h  
Program Address/  
Program Data  
Note: The above command sequence takes place in Word Mode.  
2004-10-06 41/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Auto-Page Program  
START  
Auto page program command sequence  
(see below)  
DATA Polling or Toggle Bit  
No  
Last address ?  
Yes  
Address = Address + 1  
Auto-Program  
Completed  
555h/AAh  
2AAh/55h  
555h/E6h  
Program address (A2=0,A1=0,A0=0)  
/ Program data  
Program address (A2=1,A1=0,A0=0)  
/ Program data  
Program address (A2=0,A1=0,A0=1)  
/ Program data  
Program address (A2=1,A1=0,A0=1)  
/ Program data  
Program address (A2=0,A1=1,A0=0)  
/ Program data  
Program address (A2=1,A1=1,A0=0)  
/ Program data  
Program address (A2=0,A1=1,A0=1)  
/ Program data  
Program address (A2=1,A1=1,A0=1)  
/ Program data  
2004-10-06 42/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Fast Program  
Start  
Fast Program Set Command  
Sequence (see below)  
Fast Program Command Sequence  
(see below)  
DATA Polling or Toggle Bit  
No  
Last Address?  
Yes  
Address = Address + 1  
Program Sequence  
(see below)  
Fast Program  
Completed  
Fast Program Set Command Sequence  
(address/data)  
Fast Program Command Sequence  
(address/data)  
Fast Program Reset Command Sequence  
(address/data)  
555h/AAh  
2AAh/55h  
555h/20h  
XXXh/A0h  
XXXh/90h  
XXXh/F0h  
Program Address/  
Program Data  
2004-10-06 43/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Auto Erase  
Start  
Auto Erase Command Sequence  
(see below)  
DATA Polling or Toggle Bit  
Auto Erase  
Completed  
Auto Chip Erase Command Sequence  
Auto Block/Auto Multi-Block Erase Command Sequence  
(address/data)  
(address/data)  
555h/AAh  
555h/AAh  
2AAh/55h  
2AAh/55h  
555h/80h  
555h/AAh  
2AAh/55h  
555h/10h  
555h/80h  
555h/AAh  
2AAh/55h  
Block Address/30h  
Block Address/30h  
Additional address  
inputs during  
Auto Multi-Block Erase  
Block Address/30h  
Note: The above command sequence takes place in Word Mode.  
2004-10-06 44/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
DATA  
DQ7  
Polling  
Start  
Read Byte (DQ0~DQ7)  
Addr. = VA  
Yes  
Yes  
DQ7 = Data?  
No  
No  
DQ5 = 1?  
Yes  
1)  
1) : DQ7 must be rechecked even if DQ5 = 1  
because DQ7 may change at the same  
time as DQ5.  
Read Byte (DQ0~DQ7)  
Addr. = VA  
DQ7 = Data?  
No  
Fail  
Pass  
DQ6 Toggle Bit  
Start  
Read Byte (DQ0~DQ7)  
Addr. = VA  
No  
DQ6 = Toggle?  
Yes  
No  
DQ5 = 1?  
Yes  
1)  
1) : DQ6 must be rechecked even if DQ5 = 1  
because DQ6 may stop toggling at the  
same time that DQ5 changes to 1.  
Read Byte (DQ0~DQ7)  
Addr. = VA  
No  
DQ6 = Toggle?  
Yes  
Fail  
Pass  
VA: Valid address for programming  
Any of the addresses within the block being erased during a Block Erase operation  
“Don’t care” during a Chip Erase operation  
2004-10-06 45/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Block Protect 1  
Start  
PLSCNT = 1  
Set up Block Address  
Addr. = BPA  
Wait for 4 µs  
OE = A9 = V , CE = V  
ID  
IL  
Wait for 4 µs  
WE = V  
IL  
Wait for 100 µs  
WE = V  
PLSCNT = PLSCNT + 1  
IH  
Wait for 4 µs  
OE = V  
IH  
Wait for 4 µs  
OE = V  
IL  
Verify Block Protect  
No  
No  
Data = 01h?  
PLSCNT = 25?  
Yes  
Protect Another Block?  
No  
Yes  
Yes  
Device Failed  
Remove V from A9  
ID  
Block Protect  
Complete  
BPA: Block Address and ID Read Address (A6, A1, A0)  
ID Read Address = (0, 1, 0)  
2004-10-06 46/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Block Protect 2  
Start  
RESET = V  
ID  
Wait for 4 µs  
PLSCNT = 1  
Block Protect 2  
Command First Bus Write Cycle  
(XXXh/60h)  
Set up Address  
Addr. = BPA  
Block Protect 2  
Command Second Bus Write Cycle  
(BPA/60h)  
Wait for 100 µs  
Block Protect 2  
Command Third Bus Write Cycle  
(XXXh/40h)  
PLSCNT = PLSCNT + 1  
Verify Block Protect  
No  
PLSCNT = 25?  
Yes  
No  
Data = 01h?  
Yes  
Protect Another Block?  
No  
Yes  
Remove V from RESET  
ID  
Remove V from RESET  
ID  
Reset Command  
Device Failed  
Reset Command  
Block Protect  
Complete  
BPA: Block Address and ID Read Address (A6, A1, A0)  
ID Read Address = (0, 1, 0)  
2004-10-06 47/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK ADDRESS TABLES  
(1) TC58FYM5T2A (top boot block)  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA0  
BA1  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
000000h~00FFFFh  
010000h~01FFFFh  
020000h~02FFFFh  
030000h~03FFFFh  
040000h~04FFFFh  
050000h~05FFFFh  
060000h~06FFFFh  
070000h~07FFFFh  
080000h~08FFFFh  
090000h~09FFFFh  
0A0000h~0AFFFFh  
0B0000h~0BFFFFh  
0C0000h~0CFFFFh  
0D0000h~0DFFFFh  
0E0000h~0EFFFFh  
0F0000h~0FFFFFh  
100000h~10FFFFh  
110000h~11FFFFh  
120000h~12FFFFh  
130000h~13FFFFh  
140000h~14FFFFh  
150000h~15FFFFh  
160000h~16FFFFh  
170000h~17FFFFh  
180000h~18FFFFh  
190000h~19FFFFh  
1A0000h~1AFFFFh  
1B0000h~1BFFFFh  
1C0000h~1CFFFFh  
1D0000h~1DFFFFh  
1E0000h~1EFFFFh  
1F0000h~1FFFFFh  
000000h~007FFFh  
008000h~00FFFFh  
010000h~017FFFh  
018000h~01FFFFh  
020000h~027FFFh  
028000h~02FFFFh  
030000h~037FFFh  
038000h~03FFFFh  
040000h~047FFFh  
048000h~04FFFFh  
050000h~057FFFh  
058000h~05FFFFh  
060000h~067FFFh  
068000h~06FFFFh  
070000h~077FFFh  
078000h~07FFFFh  
080000h~087FFFh  
088000h~08FFFFh  
090000h~097FFFh  
098000h~09FFFFh  
0A0000h~0A7FFFh  
0A8000h~0AFFFFh  
0B0000h~0B7FFFh  
0B8000h~0BFFFFh  
0C0000h~0C7FFFh  
0C8000h~0CFFFFh  
0D0000h~0D7FFFh  
0D8000h~0DFFFFh  
0E0000h~0E7FFFh  
0E8000h~0EFFFFh  
0F0000h~0F7FFFh  
0F8000h~0FFFFFh  
BA2  
L
L
L
H
H
L
BA3  
L
L
L
H
L
BK0  
BA4  
L
L
H
H
H
H
L
BA5  
L
L
L
H
L
BA6  
L
L
H
H
L
BA7  
L
L
H
L
BA8  
L
H
H
H
H
H
H
H
H
L
BA9  
L
L
L
H
L
BA10  
BA11  
BA12  
BA13  
BA14  
BA15  
BA16  
BA17  
BA18  
BA19  
BA20  
BA21  
BA22  
BA23  
BA24  
BA25  
BA26  
BA27  
BA28  
BA29  
BA30  
BA31  
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
H
H
L
L
L
H
L
BK1  
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
2004-10-06 48/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA32  
BA33  
BA34  
BA35  
BA36  
BA37  
BA38  
BA39  
BA40  
BA41  
BA42  
BA43  
BA44  
BA45  
BA46  
BA47  
BA48  
BA49  
BA50  
BA51  
BA52  
BA53  
BA54  
BA55  
BA56  
BA57  
BA58  
BA59  
BA60  
BA61  
BA62  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
200000h~20FFFFh  
210000h~21FFFFh  
220000h~22FFFFh  
230000h~23FFFFh  
240000h~24FFFFh  
250000h~25FFFFh  
260000h~26FFFFh  
270000h~27FFFFh  
280000h~28FFFFh  
290000h~29FFFFh  
2A0000h~2AFFFFh  
2B0000h~2BFFFFh  
2C0000h~2CFFFFh  
2D0000h~2DFFFFh  
2E0000h~2EFFFFh  
2F0000h~2FFFFFh  
300000h~30FFFFh  
310000h~31FFFFh  
320000h~32FFFFh  
330000h~33FFFFh  
340000h~34FFFFh  
350000h~35FFFFh  
360000h~36FFFFh  
370000h~37FFFFh  
380000h~38FFFFh  
390000h~39FFFFh  
3A0000h~3AFFFFh  
3B0000h~3BFFFFh  
3C0000h~3CFFFFh  
3D0000h~3DFFFFh  
3E0000h~3EFFFFh  
100000h~107FFFh  
108000h~10FFFFh  
110000h~117FFFh  
118000h~11FFFFh  
120000h~127FFFh  
128000h~12FFFFh  
130000h~137FFFh  
138000h~13FFFFh  
140000h~147FFFh  
148000h~14FFFFh  
150000h~157FFFh  
158000h~15FFFFh  
160000h~167FFFh  
168000h~16FFFFh  
170000h~177FFFh  
178000h~17FFFFh  
180000h~187FFFh  
188000h~18FFFFh  
190000h~197FFFh  
198000h~19FFFFh  
1A0000h~1A7FFFh  
1A8000h~1AFFFFh  
1B0000h~1B7FFFh  
1B8000h~1BFFFFh  
1C0000h~1C7FFFh  
1C8000h~1CFFFFh  
1D0000h~1D7FFFh  
1D8000h~1DFFFFh  
1E0000h~1E7FFFh  
1E8000h~1EFFFFh  
1F0000h~1F7FFFh  
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
BK2  
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
BK3  
L
H
L
H
H
H
L
H
L
H
2004-10-06 49/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA63  
BA64  
BA65  
BA66  
BA67  
BA68  
BA69  
BA70  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Ｈ
Ｈ
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Ｈ
Ｈ
H
H
H
H
H
H
L
L
L
L
L
Ｈ
L
3F0000h~3F1FFFh  
3F2000h~3F3FFFh  
3F4000h~3F5FFFh  
3F6000h~3F7FFFh  
3F8000h~3F9FFFh  
3FA000h~3FBFFFh  
3FC000h~3FDFFFh  
3FE000h~3FFFFFh  
1F8000h~1F8FFFh  
1F9000h~1F9FFFh  
1FA000h~1FAFFFh  
1FB000h~1FBFFFh  
1FC000h~1FCFFFh  
1FD000h~1FDFFFh  
1FE000h~1FEFFFh  
1FF000h~1FFFFFh  
L
H
H
L
L
H
L
BK3  
H
H
H
H
L
H
L
H
H
H
2004-10-06 50/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
(2) TC58FYM5B2A (bottom boot block)  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA0  
BA1  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
L
H
H
L
L
H
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
H
L
H
L
H
L
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
000000h~001FFFh  
002000h~003FFFh  
004000h~005FFFh  
006000h~007FFFh  
008000h~009FFFh  
00A000h~00BFFFh  
00C000h~00DFFFh  
00E000h~00FFFFh  
010000h~01FFFFh  
020000h~02FFFFh  
030000h~03FFFFh  
040000h~04FFFFh  
050000h~05FFFFh  
060000h~06FFFFh  
070000h~07FFFFh  
080000h~08FFFFh  
090000h~09FFFFh  
0A0000h~0AFFFFh  
0B0000h~0BFFFFh  
0C0000h~0CFFFFh  
0D0000h~0DFFFFh  
0E0000h~0EFFFFh  
0F0000h~0FFFFFh  
100000h~10FFFFh  
110000h~11FFFFh  
120000h~12FFFFh  
130000h~13FFFFh  
140000h~14FFFFh  
150000h~15FFFFh  
160000h~16FFFFh  
170000h~17FFFFh  
000000h~000FFFh  
001000h~001FFFh  
002000h~002FFFh  
003000h~003FFFh  
004000h~004FFFh  
005000h~005FFFh  
006000h~006FFFh  
007000h~007FFFh  
008000h~00FFFFh  
010000h~017FFFh  
018000h~01FFFFh  
020000h~027FFFh  
028000h~02FFFFh  
030000h~037FFFh  
038000h~03FFFFh  
040000h~047FFFh  
048000h~04FFFFh  
050000h~057FFFh  
058000h~05FFFFh  
060000h~067FFFh  
068000h~06FFFFh  
070000h~077FFFh  
078000h~07FFFFh  
080000h~087FFFh  
088000h~08FFFFh  
090000h~097FFFh  
098000h~09FFFFh  
0A0000h~0A7FFFh  
0A8000h~0AFFFFh  
0B0000h~0B7FFFh  
0B8000h~0BFFFFh  
BA2  
L
L
L
BA3  
L
L
L
BA4  
L
L
L
BA5  
L
L
L
BA6  
L
L
L
BK0  
BA7  
L
L
L
BA8  
L
L
H
L
BA9  
L
H
H
L
BA10  
BA11  
BA12  
BA13  
BA14  
BA15  
BA16  
BA17  
BA18  
BA19  
BA20  
BA21  
BA22  
BA23  
BA24  
BA25  
BA26  
BA27  
BA28  
BA29  
BA30  
L
H
L
H
H
H
H
L
L
H
L
H
H
L
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
L
H
L
H
H
L
H
L
BK1  
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
2004-10-06 51/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA31  
BA32  
BA33  
BA34  
BA35  
BA36  
BA37  
BA38  
BA39  
BA40  
BA41  
BA42  
BA43  
BA44  
BA45  
BA46  
BA47  
BA48  
BA49  
BA50  
BA51  
BA52  
BA53  
BA54  
BA55  
BA56  
BA57  
BA58  
BA59  
BA60  
BA61  
BA62  
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
L
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
180000h~18FFFFh  
190000h~19FFFFh  
1A0000h~1AFFFFh  
1B0000h~1BFFFFh  
1C0000h~1CFFFFh  
1D0000h~1DFFFFh  
1E0000h~1EFFFFh  
1F0000h~1FFFFFh  
200000h~20FFFFh  
210000h~21FFFFh  
220000h~22FFFFh  
230000h~23FFFFh  
240000h~24FFFFh  
250000h~25FFFFh  
260000h~26FFFFh  
270000h~27FFFFh  
280000h~28FFFFh  
290000h~29FFFFh  
2A0000h~2AFFFFh  
2B0000h~2BFFFFh  
2C0000h~2CFFFFh  
2D0000h~2DFFFFh  
2E0000h~2EFFFFh  
2F0000h~2FFFFFh  
300000h~30FFFFh  
310000h~31FFFFh  
320000h~32FFFFh  
330000h~33FFFFh  
340000h~34FFFFh  
350000h~35FFFFh  
360000h~36FFFFh  
370000h~37FFFFh  
0C0000h~0C7FFFh  
0C8000h~0CFFFFh  
0D0000h~0D7FFFh  
0D8000h~0DFFFFh  
0E0000h~0E7FFFh  
0E8000h~0EFFFFh  
0F0000h~0F7FFFh  
0F8000h~0FFFFFh  
100000h~107FFFh  
108000h~10FFFFh  
110000h~117FFFh  
118000h~11FFFFh  
120000h~127FFFh  
128000h~12FFFFh  
130000h~137FFFh  
138000h~13FFFFh  
140000h~147FFFh  
148000h~14FFFFh  
150000h~157FFFh  
158000h~15FFFFh  
160000h~167FFFh  
168000h~16FFFFh  
170000h~177FFFh  
178000h~17FFFFh  
180000h~187FFFh  
188000h~18FFFFh  
190000h~197FFFh  
198000h~19FFFFh  
1A0000h~1A7FFFh  
1A8000h~1AFFFFh  
1B0000h~1B7FFFh  
1B8000h~1BFFFFh  
L
L
H
H
L
L
L
H
L
BK1  
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
BK2  
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
H
L
L
H
H
L
H
2004-10-06 52/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA63  
BA64  
BA65  
BA66  
BA67  
BA68  
BA69  
BA70  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
380000h~38FFFFh  
390000h~39FFFFh  
3A0000h~3AFFFFh  
3B0000h~3BFFFFh  
3C0000h~3CFFFFh  
3D0000h~3DFFFFh  
3E0000h~3EFFFFh  
3F0000h~3FFFFFh  
1C0000h~1C7FFFh  
1C8000h~1CFFFFh  
1D0000h~1D7FFFh  
1D8000h~1DFFFFh  
1E0000h~1E7FFFh  
1E8000h~1EFFFFh  
1F0000h~1F7FFFh  
1F8000h~1FFFFFh  
L
H
H
L
L
H
L
BK3  
H
H
H
H
L
H
L
H
H
H
2004-10-06 53/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
(3) TC58FYM5T3A (top boot block)  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA0  
BA1  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
000000h~00FFFFh  
010000h~01FFFFh  
020000h~02FFFFh  
030000h~03FFFFh  
040000h~04FFFFh  
050000h~05FFFFh  
060000h~06FFFFh  
070000h~07FFFFh  
080000h~08FFFFh  
090000h~09FFFFh  
0A0000h~0AFFFFh  
0B0000h~0BFFFFh  
0C0000h~0CFFFFh  
0D0000h~0DFFFFh  
0E0000h~0EFFFFh  
0F0000h~0FFFFFh  
100000h~10FFFFh  
110000h~11FFFFh  
120000h~12FFFFh  
130000h~13FFFFh  
140000h~14FFFFh  
150000h~15FFFFh  
160000h~16FFFFh  
170000h~17FFFFh  
180000h~18FFFFh  
190000h~19FFFFh  
1A0000h~1AFFFFh  
1B0000h~1BFFFFh  
1C0000h~1CFFFFh  
1D0000h~1DFFFFh  
1E0000h~1EFFFFh  
1F0000h~1FFFFFh  
000000h~007FFFh  
008000h~00FFFFh  
010000h~017FFFh  
018000h~01FFFFh  
020000h~027FFFh  
028000h~02FFFFh  
030000h~037FFFh  
038000h~03FFFFh  
040000h~047FFFh  
048000h~04FFFFh  
050000h~057FFFh  
058000h~05FFFFh  
060000h~067FFFh  
068000h~06FFFFh  
070000h~077FFFh  
078000h~07FFFFh  
080000h~087FFFh  
088000h~08FFFFh  
090000h~097FFFh  
098000h~09FFFFh  
0A0000h~0A7FFFh  
0A8000h~0AFFFFh  
0B0000h~0B7FFFh  
0B8000h~0BFFFFh  
0C0000h~0C7FFFh  
0C8000h~0CFFFFh  
0D0000h~0D7FFFh  
0D8000h~0DFFFFh  
0E0000h~0E7FFFh  
0E8000h~0EFFFFh  
0F0000h~0F7FFFh  
0F8000h~0FFFFFh  
BA2  
L
L
L
H
H
L
BA3  
L
L
L
H
L
BA4  
L
L
H
H
H
H
L
BA5  
L
L
L
H
L
BA6  
L
L
H
H
L
BA7  
L
L
H
L
BA8  
L
H
H
H
H
H
H
H
H
L
BA9  
L
L
L
H
L
BA10  
BA11  
BA12  
BA13  
BA14  
BA15  
BA16  
BA17  
BA18  
BA19  
BA20  
BA21  
BA22  
BA23  
BA24  
BA25  
BA26  
BA27  
BA28  
BA29  
BA30  
BA31  
L
L
H
H
L
L
L
H
L
BK0  
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
L
H
L
BK1  
H
H
H
H
L
H
L
H
H
H
2004-10-06 54/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA32  
BA33  
BA34  
BA35  
BA36  
BA37  
BA38  
BA39  
BA40  
BA41  
BA42  
BA43  
BA44  
BA45  
BA46  
BA47  
BA48  
BA49  
BA50  
BA51  
BA52  
BA53  
BA54  
BA55  
BA56  
BA57  
BA58  
BA59  
BA60  
BA61  
BA62  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
200000h~20FFFFh  
210000h~21FFFFh  
220000h~22FFFFh  
230000h~23FFFFh  
240000h~24FFFFh  
250000h~25FFFFh  
260000h~26FFFFh  
270000h~27FFFFh  
280000h~28FFFFh  
290000h~29FFFFh  
2A0000h~2AFFFFh  
2B0000h~2BFFFFh  
2C0000h~2CFFFFh  
2D0000h~2DFFFFh  
2E0000h~2EFFFFh  
2F0000h~2FFFFFh  
300000h~30FFFFh  
310000h~31FFFFh  
320000h~32FFFFh  
330000h~33FFFFh  
340000h~34FFFFh  
350000h~35FFFFh  
360000h~36FFFFh  
370000h~37FFFFh  
380000h~38FFFFh  
390000h~39FFFFh  
3A0000h~3AFFFFh  
3B0000h~3BFFFFh  
3C0000h~3CFFFFh  
3D0000h~3DFFFFh  
3E0000h~3EFFFFh  
100000h~107FFFh  
108000h~10FFFFh  
110000h~117FFFh  
118000h~11FFFFh  
120000h~127FFFh  
128000h~12FFFFh  
130000h~137FFFh  
138000h~13FFFFh  
140000h~147FFFh  
148000h~14FFFFh  
150000h~157FFFh  
158000h~15FFFFh  
160000h~167FFFh  
168000h~16FFFFh  
170000h~177FFFh  
178000h~17FFFFh  
180000h~187FFFh  
188000h~18FFFFh  
190000h~197FFFh  
198000h~19FFFFh  
1A0000h~1A7FFFh  
1A8000h~1AFFFFh  
1B0000h~1B7FFFh  
1B8000h~1BFFFFh  
1C0000h~1C7FFFh  
1C8000h~1CFFFFh  
1D0000h~1D7FFFh  
1D8000h~1DFFFFh  
1E0000h~1E7FFFh  
1E8000h~1EFFFFh  
1F0000h~1F7FFFh  
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
BK1  
L
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
H
H
L
L
L
H
L
BK2  
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
BK3  
L
H
L
H
H
H
L
H
L
H
2004-10-06 55/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA63  
BA64  
BA65  
BA66  
BA67  
BA68  
BA69  
BA70  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Ｈ
Ｈ
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Ｈ
Ｈ
H
H
H
H
H
H
L
L
L
L
L
Ｈ
L
3F0000h~3F1FFFh  
3F2000h~3F3FFFh  
3F4000h~3F5FFFh  
3F6000h~3F7FFFh  
3F8000h~3F9FFFh  
3FA000h~3FBFFFh  
3FC000h~3FDFFFh  
3FE000h~3FFFFFh  
1F8000h~1F8FFFh  
1F9000h~1F9FFFh  
1FA000h~1FAFFFh  
1FB000h~1FBFFFh  
1FC000h~1FCFFFh  
1FD000h~1FDFFFh  
1FE000h~1FEFFFh  
1FF000h~1FFFFFh  
L
H
H
L
L
H
L
BK3  
H
H
H
H
L
H
L
H
H
H
2004-10-06 56/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
(4) TC58FYM5B3A (bottom boot block)  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA0  
BA1  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
L
H
H
L
L
H
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
H
L
H
L
H
L
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
000000h~001FFFh  
002000h~003FFFh  
004000h~005FFFh  
006000h~007FFFh  
008000h~009FFFh  
00A000h~00BFFFh  
00C000h~00DFFFh  
00E000h~00FFFFh  
010000h~01FFFFh  
020000h~02FFFFh  
030000h~03FFFFh  
040000h~04FFFFh  
050000h~05FFFFh  
060000h~06FFFFh  
070000h~07FFFFh  
080000h~08FFFFh  
090000h~09FFFFh  
0A0000h~0AFFFFh  
0B0000h~0BFFFFh  
0C0000h~0CFFFFh  
0D0000h~0DFFFFh  
0E0000h~0EFFFFh  
0F0000h~0FFFFFh  
100000h~10FFFFh  
110000h~11FFFFh  
120000h~12FFFFh  
130000h~13FFFFh  
140000h~14FFFFh  
150000h~15FFFFh  
160000h~16FFFFh  
170000h~17FFFFh  
000000h~000FFFh  
001000h~001FFFh  
002000h~002FFFh  
003000h~003FFFh  
004000h~004FFFh  
005000h~005FFFh  
006000h~006FFFh  
007000h~007FFFh  
008000h~00FFFFh  
010000h~017FFFh  
018000h~01FFFFh  
020000h~027FFFh  
028000h~02FFFFh  
030000h~037FFFh  
038000h~03FFFFh  
040000h~047FFFh  
048000h~04FFFFh  
050000h~057FFFh  
058000h~05FFFFh  
060000h~067FFFh  
068000h~06FFFFh  
070000h~077FFFh  
078000h~07FFFFh  
080000h~087FFFh  
088000h~08FFFFh  
090000h~097FFFh  
098000h~09FFFFh  
0A0000h~0A7FFFh  
0A8000h~0AFFFFh  
0B0000h~0B7FFFh  
0B8000h~0BFFFFh  
BA2  
L
L
L
BA3  
L
L
L
BA4  
L
L
L
BA5  
L
L
L
BA6  
L
L
L
BK0  
BA7  
L
L
L
BA8  
L
L
H
L
BA9  
L
H
H
L
BA10  
BA11  
BA12  
BA13  
BA14  
BA15  
BA16  
BA17  
BA18  
BA19  
BA20  
BA21  
BA22  
BA23  
BA24  
BA25  
BA26  
BA27  
BA28  
BA29  
BA30  
L
H
L
H
H
H
H
L
L
H
L
H
H
L
H
L
L
L
H
L
L
H
H
L
L
H
L
BK1  
H
H
H
H
L
L
H
L
H
H
L
H
L
L
L
H
L
L
H
H
L
L
H
L
BK2  
H
H
H
H
L
H
L
H
H
H
2004-10-06 57/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA31  
BA32  
BA33  
BA34  
BA35  
BA36  
BA37  
BA38  
BA39  
BA40  
BA41  
BA42  
BA43  
BA44  
BA45  
BA46  
BA47  
BA48  
BA49  
BA50  
BA51  
BA52  
BA53  
BA54  
BA55  
BA56  
BA57  
BA58  
BA59  
BA60  
BA61  
BA62  
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
L
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
180000h~18FFFFh  
190000h~19FFFFh  
1A0000h~1AFFFFh  
1B0000h~1BFFFFh  
1C0000h~1CFFFFh  
1D0000h~1DFFFFh  
1E0000h~1EFFFFh  
1F0000h~1FFFFFh  
200000h~20FFFFh  
210000h~21FFFFh  
220000h~22FFFFh  
230000h~23FFFFh  
240000h~24FFFFh  
250000h~25FFFFh  
260000h~26FFFFh  
270000h~27FFFFh  
280000h~28FFFFh  
290000h~29FFFFh  
2A0000h~2AFFFFh  
2B0000h~2BFFFFh  
2C0000h~2CFFFFh  
2D0000h~2DFFFFh  
2E0000h~2EFFFFh  
2F0000h~2FFFFFh  
300000h~30FFFFh  
310000h~31FFFFh  
320000h~32FFFFh  
330000h~33FFFFh  
340000h~34FFFFh  
350000h~35FFFFh  
360000h~36FFFFh  
370000h~37FFFFh  
0C0000h~0C7FFFh  
0C8000h~0CFFFFh  
0D0000h~0D7FFFh  
0D8000h~0DFFFFh  
0E0000h~0E7FFFh  
0E8000h~0EFFFFh  
0F0000h~0F7FFFh  
0F8000h~0FFFFFh  
100000h~107FFFh  
108000h~10FFFFh  
110000h~117FFFh  
118000h~11FFFFh  
120000h~127FFFh  
128000h~12FFFFh  
130000h~137FFFh  
138000h~13FFFFh  
140000h~147FFFh  
148000h~14FFFFh  
150000h~157FFFh  
158000h~15FFFFh  
160000h~167FFFh  
168000h~16FFFFh  
170000h~177FFFh  
178000h~17FFFFh  
180000h~187FFFh  
188000h~18FFFFh  
190000h~197FFFh  
198000h~19FFFFh  
1A0000h~1A7FFFh  
1A8000h~1AFFFFh  
1B0000h~1B7FFFh  
1B8000h~1BFFFFh  
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
BK2  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
BK3  
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
H
L
L
H
H
L
H
2004-10-06 58/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK ADDRESS  
ADDRESS RANGE  
BANK  
#
BLOCK  
#
BANK  
ADDRESS  
A20 A19 A18 A17 A16 A15 A14 A13 A12  
BYTE MODE  
WORD MODE  
BA63  
BA64  
BA65  
BA66  
BA67  
BA68  
BA69  
BA70  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
380000h~38FFFFh  
390000h~39FFFFh  
3A0000h~3AFFFFh  
3B0000h~3BFFFFh  
3C0000h~3CFFFFh  
3D0000h~3DFFFFh  
3E0000h~3EFFFFh  
3F0000h~3FFFFFh  
1C0000h~1C7FFFh  
1C8000h~1CFFFFh  
1D0000h~1D7FFFh  
1D8000h~1DFFFFh  
1E0000h~1E7FFFh  
1E8000h~1EFFFFh  
1F0000h~1F7FFFh  
1F8000h~1FFFFFh  
L
H
H
L
L
H
L
BK3  
H
H
H
H
L
H
L
H
H
H
2004-10-06 59/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
BLOCK SIZE TABLE  
(1) TC58FYM5T2A (top boot block)  
BLOCK SIZE  
BANK SIZE  
BLOCK  
BANK  
#
BLOCK COUNT  
#
BYTE MODE  
64 Kbytes  
64 Kbytes  
64 Kbytes  
64 Kbytes  
8 Kbytes  
WORD MODE  
BYTE MODE  
512 Kbytes  
1536 Kbytes  
1536 Kbytes  
448 Kbytes  
64 Kbytes  
WORD MODE  
256 Kwords  
768 Kwords  
768 Kwords  
224 Kwords  
32 Kwords  
BA0~BA7  
BA8~BA31  
BA32~BA55  
BA56~BA62  
BA63~BA70  
32 Kwords  
32 Kwords  
32 Kwords  
32 Kwords  
4 Kwords  
BK0  
BK1  
BK2  
BK3  
BK3  
8
24  
24  
7
8
(2) TC58FYM5B2A (bottom boot block)  
BLOCK SIZE  
BANK SIZE  
BLOCK  
BANK  
#
BLOCK COUNT  
#
BYTE MODE  
8 Kbytes  
WORD MODE  
4 Kwords  
BYTE MODE  
64 Kbytes  
WORD MODE  
32 Kwords  
BA0~BA7  
BA8~BA14  
BA15~BA38  
BA39~BA62  
BA63~BA70  
BK0  
BK0  
BK1  
BK2  
BK3  
8
7
64 Kbytes  
64 Kbytes  
64 Kbytes  
64 Kbytes  
32 Kwords  
32 Kwords  
32 Kwords  
32 Kwords  
448 Kbytes  
1536 Kbytes  
1536 Kbytes  
512 Kbytes  
224 Kwords  
768 Kwords  
768 Kwords  
256 Kwords  
24  
24  
8
(3) TC58FYM5T3A (top boot block)  
BLOCK SIZE  
BANK SIZE  
BLOCK  
BANK  
#
BLOCK COUNT  
#
BYTE MODE  
64 Kbytes  
64 Kbytes  
64 Kbytes  
64 Kbytes  
8 Kbytes  
WORD MODE  
BYTE MODE  
1536 Kbytes  
1536 Kbytes  
512 Kbytes  
448 Kbytes  
64 Kbytes  
WORD MODE  
768 Kwords  
768 Kwords  
256 Kwords  
224 Kwords  
32 Kwords  
BA0~BA23  
BA24~BA47  
BA48~BA55  
BA56~BA62  
BA63~BA70  
32 Kwords  
32 Kwords  
32 Kwords  
32 Kwords  
4 Kwords  
BK0  
BK1  
BK2  
BK3  
BK3  
24  
24  
8
7
8
(4) TC58FYM5B3A (bottom boot block)  
BLOCK SIZE  
BANK SIZE  
BLOCK  
BANK  
#
BLOCK COUNT  
#
BYTE MODE  
8 Kbytes  
WORD MODE  
4 Kwords  
BYTE MODE  
64 Kbytes  
WORD MODE  
32 Kwords  
BA0~BA7  
BA8~BA14  
BA15~BA22  
BA23~BA46  
BA47~BA70  
BK0  
BK0  
BK1  
BK2  
BK3  
8
7
64 Kbytes  
64 Kbytes  
64 Kbytes  
64 Kbytes  
32 Kwords  
32 Kwords  
32 Kwords  
32 Kwords  
448 Kbytes  
512 Kbytes  
1536 Kbytes  
1536 Kbytes  
224 Kwords  
256 Kwords  
768 Kwords  
768 Kwords  
8
24  
24  
2004-10-06 60/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
PACKAGE DIMENSIONS  
Unit: mm  
2004-10-06 61/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
PACKAGE DIMENSIONS  
Unit: mm  
2004-10-06 62/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
Revision History  
Date  
Version  
Description  
2003- 02-03  
2003-05-10  
1.00  
1.01  
Original version  
Added the minimum interval between resume and the following suspend command.  
Changed the CFI code (Page.15)  
Changed Vdd spec from 1.65V-2.2V to 1.7V-1.95V (Page.21)  
Changed VLKO spec from 1.4V to 1.55V (Page.22)  
2003-06-02  
1.02  
Changed tPPAW spec from 48us to 57us (Page.23)  
Changed tSUSP spec from 2.5us to 4us (Page.24)  
Changed tSUSPA spec from 3.0us to 6.5us (Page.24)  
Changed the product name from TC58FYM5(T/B)(2/3)A(FT/XB)65 to TC58FYM5(T/B)(2/3)A(FT/XB)70  
Modified the timing diagrams ( BYTE during Read Operation).  
Add the spec of t  
OEH.  
2003-08-20  
2004-10-06  
1.03  
1.04  
P13 Modified the comment of Verify Block Protect.  
P10-12 Modified the comment for host processor.  
Add the spec of t  
CEHT.  
Generalize  
2004-10-06 63/64  
TC58FYM5 (T/B) (2/3) A (FT/XB) 70  
RESTRICTIONS ON PRODUCT USE  
030619EBA  
• The information contained herein is subject to change without notice.  
• The information contained herein is presented only as a guide for the applications of our products. No  
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which  
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of  
TOSHIBA or others.  
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor  
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical  
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of  
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of  
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.  
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as  
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and  
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability  
Handbook” etc..  
• The TOSHIBA products listed in this document are intended for usage in general electronics applications  
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,  
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires  
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or  
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or  
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,  
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this  
document shall be made at the customer’s own risk.  
• The products described in this document are subject to the foreign exchange and foreign trade laws.  
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced  
and sold, under any law and regulations.  
2004-10-06 64/64  

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