TC59LM914AMG-50_技术文档

TC59LM914/06AMG-37,-50

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

512Mbits Network FCRAM1 (SSTL_18 / HSTL_Interface)

− 4,194,304-WORDS × 8 BANKS × 16-BITS

− 8,388,608-WORDS × 8 BANKS × 8-BITS

DESCRIPTION

Network FCRAM^TMis Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG is Fast Cycle

Random Access Memory (Network FCRAM^TM) containing 536,870,912 memory cells. TC59LM914AMG is organized

as 4,194,304-words × 8 banks × 16 bits, TC59LM906AMG is organized as 8,388,608-words × 8 banks × 8 bits.

TC59LM914/06AMG feature a fully synchronous operation referenced to clock edge whereby all operations are

synchronized at a clock input which enables high performance and simple user interface coexistence.

TC59LM914/06AMG can operate fast core cycle compared with regular DDR SDRAM.

TC59LM914/06AMG is suitable for Network, Server and other applications where large memory density and low

power consumption are required. The Output Driver for Network FCRAM^TMis capable of high quality fast data

transfer under light loading condition.

FEATURES

TC59LM914/06

PARAMETER

-37

-50

CL = 3

CL = 4

CL = 5

5.5 ns

4.5 ns

3.75 ns

22.5 ns

22.0 ns

280 mA

90 mA

20 mA

6.0 ns

5.5 ns

5.0 ns

27.5 ns

24.0 ns

240 mA

80 mA

20 mA

t

Clock Cycle Time (min)

CK

t

I

Random Read/Write Cycle Time (min)

Random Access Time (max)

RC

RAC

DD1S

DD2P

DD6

Operating Current (single bank) (max)

Power Down Current (max)

l

Self-Refresh Current (max)

•

Fully Synchronous Operation

Double Data Rate (DDR)

•

Data input/output are synchronized with both edges of DQS.

Differential Clock (CLK and CLK ) inputs

CS , FN and all address input signals are sampled on the positive edge of CLK.

Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .

Fast clock cycle time of 3.75 ns minimum

Clock: 266 MHz maximum

Data: 533 Mbps/pin maximum

•

Fast cycle and Short Latency

Eight independent banks operation

When BA2 input assign to A14 input, TC59LM914/06AMG can function as 4 bank device

(Keep backward compatibility to 256Mb)

•

Bidirectional differential data strobe signal : TC59LM906AMG

Bidirectional data strobe signal per byte

Distributed Auto-Refresh cycle in 3.9 µs

Self-Refresh

: TC59LM914AMG

Power Down Mode

Variable Write Length Control

Write Latency = CAS Latency-1

Programable CAS Latency and Burst Length

CAS Latency = 3, 4, 5

Burst Length = 2, 4

•

Organization: TC59LM914AMG : 4,194,304 words × 8 banks × 16 bits

TC59LM906AMG : 8,388,608 words × 8 banks × 8 bits

Power Supply Voltage

V

DD

V

:

2.5 V ± 0.125V

: 1.4 V ∼ 1.9 V

DDQ

•

1.8 V CMOS I/O comply with SSTL_18 and HSTL

Package:

60Ball BGA, 1mm × 1mm Ball pitch (P−BGA64−1317−1.00AZ)

Notice : FCRAM is trademark of Fujitsu Limited, Japan.

Rev 1.0

2004-08-20 1/59

TC59LM914/06AMG-37,-50

TC59LM906AMG

PIN NAMES

NAME

A0~A13

Address Input

Bank Address

DQS / DQS Write/Read Data Strobe

BA0~BA2

DQ0~DQ7

V

DD

V

SS

Power (+2.5 V)

Data Input / Output

Chip Select

Ground

Power (+1.5 V / +1.8 V)

(for I/O buffer)

CS

V

DDQ

FN

Function Control

Power Down Control

Clock Input

V

Ground (for I/O buffer)

Reference Voltage

Not Connected

SSQ

REF

PD

CLK, CLK

NC

4 bank operation can be performed using BA2 as A14.

PIN ASSIGNMENT (TOP VIEW)

ball pitch=1.0 x 1.0mm

x 8

1

2

3

4

5

6

A

B

V

DD

V

DQ7

DQ0

Index

SS

NC

DQ1

NC

V

SS

Q

V Q

DD

C

D

E

F

V Q

DD

DQ6

NC

V

SS

Q

DQ5

DQ2

NC

V

SS

Q

NC

V Q

DD

NC

DQ4

NC

V

Q

DQ3

NC

V

Q

NC

DD

SS

DD

V

G

H

J

V

Q

SS

NC

DQS

NC

DQS

V

SS

VREF

V

DD

BA2

CLK

NC

A13

NC

CLK

A12

FN

CS

K

L

PD

A9

A11

A8

BA1

BA0

A10

A1

M

N

P

R

A7

A6

A4

A0

A2

A3

A5

V

SS

V

DD

: Depopulated ball

Rev 1.0

2004-08-20 2/59

TC59LM914/06AMG-37,-50

TC59LM914AMG

PIN NAMES

NAME

A0~A13

Address Input

Bank Address

UDQS/LDQS Write/Read Data Strobe

BA0~BA2

DQ0~DQ15

V

DD

V

SS

Power (+2.5 V)

Data Input / Output

Chip Select

Gorund

Power (+1.5 V / +1.8 V)

(for I/O buffer)

CS

FN

V

DDQ

Power

Function Control

V

SSQ

REF

(for I/O buffer)

PD

Power Down Control

Clock Input

Reference Voltage

Not Conneted

CLK, CLK

NC

4 bank operation can be performed using BA2 as A14.

PIN ASSIGNMENT (TOP VIEW)

ball pitch=1.0 x 1.0mm

x 16

1

2

3

4

5

6

A

B

V

DQ15

DQ0

Index

DD

SS

DQ1

DQ2

DQ3

DQ5

DQ14

DQ13

V

Q

V Q

DD

SS

C

D

E

F

V

SS

Q

DD

DQ12 DQ11

DQ4

DQ10

DQ9

DQ8

NC

V

Q

V Q

DD

SS

V

DD

NC

DQ6

DQ7

NC

V

Q

SS

DD

V

SS

Q

G

H

J

V

Q

UDQS

LDQS

V

SS

VREF

V

DD

BA2

A13

NC

CLK

NC

CLK

A12

FN

CS

K

L

PD

A9

A11

A8

BA1

BA0

A10

A1

M

N

P

R

A7

A6

A4

A0

A2

A3

A5

V

SS

V

DD

: Depopulated ball

Rev 1.0

2004-08-20 3/59

TC59LM914/06AMG-37,-50

BLOCK DIAGRAM

CLK

PD

DLL

CLOCK

BUFFER

To each block

BANK #7

BANK #6

BANK #5

BANK #4

CS

FN

CONTROL

SIGNAL

COMMAND

DECODER

BANK #3

BANK #2

GENERATOR

BANK #1

BANK #0

MODE

REGISTER

MEMORY

A0~A13

ADDRESS

BUFFER

CELL ARRAY

UPPER ADDRESS

LATCH

BA0~BA2

LOWER ADDRESS

LATCH

COLUMN DECODER

READ

DATA

WRITE

DATA

WRITE ADDRESS

REFRESH

COUNTER

LATCH/

ADDRESS

BUFFER

COMPARATOR

BURST

COUNTER

DQS

DQ BUFFER

DQ0~DQn

Note: The TC59LM906AMG configuration is 8 Banks of 16384 × 512 × 8 of cell array with the DQ pins numbered DQ0~DQ7.

The TC59LM914AMG configuration is 8 Banks of 16384 × 256 × 16 of cell array with the DQ pins numbered DQ0~DQ15.

TC59LM906AMG has DQS, DQS pin for Differential Data Strobe.

TC59LM914AMG has UDQS and LDQS.

Rev 1.0

2004-08-20 4/59

TC59LM914/06AMG-37,-50

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Power Supply Voltage

RATING

UNIT

NOTES

V

−0.3~ 3.3

V

DD

Power Supply Voltage (for I/O buffer)

Input Voltage

−0.3~V + 0.3

DD

DDQ

IN

−0.3~V + 0.3

DD

V

Output and I/O pin Voltage

Input Reference Voltage

Operating Temperature (case)

Storage Temperature

−0.3~V

+ 0.3

DDQ

V

OUT

REF

opr

−0.3~V + 0.3

V

DD

T

0~85

−55~150

260

°C

W

mA

stg

Soldering Temperature (10 s)

Power Dissipation

solder

P

2

D

I

Short Circuit Output Current

±50

OUT

Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.

The device is not meant to be operated under conditions outside the limits described in the operational section of this

specification.

Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.

RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(T

= 0~85°C)

CASE

SYMBOL

PARAMETER

Power Supply Voltage

MIN

TYP.

MAX

UNIT

NOTES

V

2.375

1.4

2.5

2.625

1.9

V

DD

Power Supply Voltage (for I/O buffer)

Input Reference Voltage

⎯

DDQ

REF

V

/2 × 95%

+ 0.125

V

/2

V

/2 × 105%

DDQ

V

2

DDQ

(DC)

Input DC High Voltage

V

⎯

V

+ 0.2

5

IH

IL

REF

DDQ

(DC)

Input DC Low Voltage

−0.1

0.4

⎯

V

− 0.125

5

REF

Differential DC Input Voltage

Input DC Differential Voltage.

Input AC High Voltage

V

+ 0.1

+ 0.2

− 0.2

+ 0.2

10

ICK

DDQ

(DC)

7, 10

3, 6

4, 6

7, 10

8, 10

9, 10

ID

IH

IL

ID

X

(AC)

V

+ 0.2

REF

(AC)

Input AC Low Voltage

−0.1

V

REF

Input AC Differential Voltage

Differential AC Input Cross Point Voltage

Differential AC Middle Level

0.5

V

DDQ

V

/2 − 0.125

V

/2 + 0.125

DDQ

(AC)

ISO

DDQ

Rev 1.0

2004-08-20 5/59

TC59LM914/06AMG-37,-50

Note:

(1) All voltages referenced to V , V

.

SS SSQ

(2) V

is expected to track variations in V

DC level of the transmitting device.

REF

DDQ

Peak to peak AC noise on V

may not exceed ±2% V

(DC).

REF

(3) Overshoot limit: V

= V

+ 0.7 V with a pulse width ≤ 5 ns.

IH (max)

DDQ

(4) Undershoot limit: V

= −0.7 V with a pulse width ≤ 5 ns.

IL (min)

(5) V (DC) and V (DC) are levels to maintain the current logic state.

IH

IL

(6) V (AC) and V (AC) are levels to change to the new logic state.

IH

IL

(7) V is magnitude of the difference between V_TRinput level and V_CPinput level.

ID

(8) The value of V (AC) is expected to equal V

/2 of the transmitting device.

DDQ

X

(9) V

means {V

(V ) + V

(V )} /2.

ICK CP

ISO

ICK

TR

(10) Refer to the figure below. VTR is the true input (such as CLK, DQS) level and VCP is the complementary

input (such as CLK , DQS ) level.

CLK

V

V (AC)

ID

x

CLK

V

ICK

V

SS

|V (AC)|

ID

0 V Differential

V

ISO

V

ISO (max)

ISO (min)

V

SS

(11) In the case of external termination, VTT (termination voltage) should be gone in the range of V

0.04 V.

(DC) ±

REF

CAPACITANCE (V = 2.5V, V

= 1.8 V, f = 1 MHz, Ta = 25°C)

DD

DDQ

SYMBOL

PARAMETER

MIN

MAX

Delta

UNIT

C

Input pin Capacitance

1.5

2.5

⎯

2.5

4

0.25

0.5

pF

IN

Clock pin (CLK, CLK ) Capacitance

DQ, DQS, UDQS, LDQS, DQS Capacitance

NC pin Capacitance

INC

I/O

NC

4

⎯

Note: These parameters are periodically sampled and not 100% tested.

Rev 1.0

2004-08-20 6/59

TC59LM914/06AMG-37,-50

RECOMMENDED DC OPERATING CONDITIONS

(V =2.5V ± 0.125V, V

=1.4V ~ 1.9V, T

= 0~85°C)

DD

DDQ

CASE

MAX

SYMBOL

PARAMETER

UNIT

NOTES

-37

-50

Operating Current

= min, I = min ;

t

CK

RC

Read/Write command cycling ;

0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V

I

280

240

1, 2

DD1S

;

IN IL IH IN

DDQ

1 bank operation, Burst length = 4 ;

Address change up to 2 times during minimum I

.

RC

Standby Current

t

= min, CS = V , PD = V

IH

;

IH

CK

I

120

90

100

80

1, 2

DD2N

0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V

IN IL IH IN

All banks: inactive state ;

Other input signals are changed one time during 4 × t

.

CK

Standby (Power Down) Current

t

= min, CS = V , PD = V (Power Down) ;

IH IL

CK

DD2P

0 V ≤ V ≤ V

;

IN

All banks: inactive state

DDQ

Write Operating Current (4 Banks)

8 Bank Interleaved continuos burst wirte operation ;

t

= min, I = min

RC

CK

I

DD4W

450

350

1, 2

Burst Length = 4, CAS Latency = 5

0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V

mA

;

IN IL IH IN

DDQ

Address inputs change once per clock cycle ;

DQ and DQS inputs change twice per clock cycle.

Read Operating Current (4 Banks)

8 Bank Interleaved continuos burst wirte operation ;

t

= min, I

RC

= min, I = 0mA ;

OUT

CK

I

DD4R

450

350

1, 2

Burst Length = 4, CAS Latency = 5 ;

0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V

;

IN IL IH IN

Address inputs change once per clock cycle ;

Read data change twice per clock cycle.

Burst Auto Refresh Current

Refresh command at every I

at interval ;

REFC

t

= min、I = min

REFC

CK

I

280

20

250

20

1, 2, 3

DD5B

CAS Latency = 5

0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V

;

IN IL IH IN

Address inputs change up to 2 times during minimum I

DQ and DQS inputs change twice per clock cycle.

REFC.

Self-Refresh Current

Self-Refresh mode

2

DD6

PD = 0.2 V, 0 V ≤ V ≤ V

IN

DDQ

Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of

, t and I

t

.

RC

CK RC

2. These parameters define the current between V

and V

.

DD

is specified under burst refresh condition. Actual system should use distributed refresh that meet t

SS

3.

I

DD5B

specification.

REFI

Rev 1.0

2004-08-20 7/59

TC59LM914/06AMG-37,-50

RECOMMENDED DC OPERATING CONDITIONS (continued)

(V =2.5V ± 0.125V, V

=1.4V ~ 1.9V, T

= 0~85°C)

DD

DDQ

CASE

SYMBOL

PARAMETER

MIN

MAX

5

UNIT

NOTES

Input Leakage Current

( 0 V ≤ V ≤ V , all other pins not under test = 0 V)

I

−5

µA

LI

IN DDQ

Output Leakage Current

(Output disabled, 0 V ≤ V

−5

5

µA

LO

≤ V

)

DDQ

OUT

I

V

Current

REF

−5

−5.6

5.6

−9.8

9.8

−2.8

2.8

−13.4

13.4

−4

5

REF

V

= 1.420V

= 0.280V

= 1.420V

= 0.280V

= 1.420V

= 0.280V

= 1.420V

= 0.280V

(DC)

⎯

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

Normal Output Driver

Strong Output Driver

Weak Output Driver

(DC)

1

Output Source DC Current

(V = 1.7V ~ 1.9V)

mA

DDQ

Full Strength Output

Driver

1, 2

= V

−0.4V

DDQ

Normal Output Driver

Strong Output Driver

Weak Output Driver

= 0.4V

= V

4

−0.4V

−8

DDQ

1

Output Source DC Current

(V = 1.4V ~ 1.6V)

= 0.4V

8

mA

Not defined

⎯

DDQ

⎯

V

= V

−0.4V

−10

10

OH

OL

DDQ

Full Strength Output

Driver

1, 2

= 0.4V

Notes: 1. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.

2. In case of Full Strength Output Driver, OCD calibration (Off chip Driver impedance adjustment) can be used. The

specification of Full Strength Output Driver defines the default value after power-up.

Rev 1.0

2004-08-20 8/59

TC59LM914/06AMG-37,-50

AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)

-37

-50

SYMBOL

PARAMETER

UNIT NOTES

MIN

MAX

MIN

MAX

t

Random Cycle Time

22.5

5.5

⎯

27.5

6.0

⎯

3

RC

CK

C

L

C

L

C

L

= 3

= 4

= 5

8.5

t

Clock Cycle Time

4.5

5.5

3.75

⎯

8.5

22.0

⎯

5.0

⎯

8.5

24

3

t

Random Access Time

Clock High Time

RAC

0.45 × t

−0.6

⎯

3

CH

CK

Clock Low Time

⎯

3

CL

CK

DQS Access Time from CLK

Data Output Skew from DQS

Data Access Time from CLK

−0.45

⎯

0.45

0.25

0.5

0.6

0.35

0.65

3,8,10

4

CKQS

QSQ

AC

⎯

−0.5

−0.65

3,8,10

3, 8

Data Output Hold Time from CLK

DQS (read) Preamble Pulse Width

CLK half period (minimum of Actual t

0.5

OH

0.9 × t

CK

1.1 × t

0.9 × t

CK

1.1 × t

CK

QSPRE

CK

,

CH

t

min(t , t

)

⎯

min(t , t

)

⎯

3

HP

CH CL

t )

CL

t

DQS (read) Pulse Width

t

−t

HP QHS

⎯

t

−t

HP QHS

⎯

4, 8

QSP

Data Output Valid Time from DQS

t

−t

t

−t

QSQV

HP QHS

0.055 × t

CK

+0.17

0.055 × t

CK

+0.17

t

DQ, DQS Hold Skew factor

⎯

QHS

t

DQS (write) Low to High Setup Time

DQS (write) Preamble Pulse Width

DQS First Input Setup Time

0.75 × t

CK

1.25 × t

⎯

0.75 × t

CK

1.25 × t

⎯

3

DQSS

CK

ns

0.25 × t

4

3

4

DSPRE

DSPRES

DSPREH

DSP

CK

0

⎯

0

⎯

DQS First Low Input Hold Time

DQS High or Low Input Pulse Width

0.25 × t

0.35 × t

⎯

0.25 × t

0.35 × t

⎯

CK

0.65 × t

CK

C

L

C

L

C

L

= 3

0.75

⎯

1.0

⎯

3, 4

DQS Input Falling Edge to

Clock Setup Time

t

= 4

= 5

DSS

DQS Input Falling Edge Hold Time from

CLK

t

0.55

⎯

0.75

⎯

3, 4

DSH

DQS (write) Postamble Pulse Width

0.4 × t

⎯

0.4 × t

1.0

⎯

4

DSPST

CK

C

L

C

L

C

L

= 3

= 4

= 5

0.75

3, 4

DQS (write) Postamble Hold

Time

t

1.0

DSPSTH

1.0

t

UDQS – LDQS Skew (×16)

−0.5× t

CK

0.5× t

⎯

−0.5× t

CK

0.5× t

⎯

DSSK

DS

DH

IS

CK

Data Input Setup Time from DQS

Data Input Hold Time from DQS

0.35

0.5

0.45

0.7

4

3

⎯

Command/Address Input Setup Time

Command/Address Input Hold Time

⎯

0.5

⎯

0.7

⎯

IH

Rev 1.0

2004-08-20 9/59

TC59LM914/06AMG-37,-50

AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)

-37

-50

SYMBOL

PARAMETER

UNIT NOTES

MIN

MAX

MIN

MAX

t

Data-out Low Impedance Time from CLK

Data-out High Impedance Time from CLK

−0.5

⎯

−0.65

⎯

3,6,8

3,7,8

LZ

⎯

0.5

⎯

0.65

HZ

t

DQS-out Low Impedance Time from CLK

−0.5

⎯

−0.65

⎯

3,6,8

3,7,8

QSLZ

t

DQS-out High Impedance Time from CLK

Last output to PD High Hold Time

Power Down Exit Time

−0.5

0

0.5

⎯

1

−0.65

0

0.65

⎯

QSHZ

QPDH

PDEX

T

0.6

0.1

0.8

0.1

⎯

3

5

ns

Input Transition Time

1

PD Low Input Window for Self-Refresh

Entry

t

−0.5 × t

5

−0.5 × t

CK

5

FPDL

CK

t

OCD drive mode output delay time

Auto-Refresh Average Interval

Pause Time after Power-up

0

0.4

200

5

12

3.9

⎯

0

0.4

200

5

12

3.9

⎯

OIT

REFI

PAUSE

µs

C

L

C

L

C

L

= 3

= 4

= 5

⎯

Random Read/Write Cycle

Time

(applicable to same bank)

I

5

⎯

5

⎯

RC

6

⎯

6

⎯

RDA/WRA to LAL Command Input Delay

(applicable to same bank)

1

RCD

RAS

C

L

C

L

C

L

= 3

= 4

= 5

4

5

⎯

4

5

⎯

LAL to RDA/WRA Command

Input Delay

(applicable to same bank)

Random Bank Access Delay

(applicable to other bank)

I

2

⎯

2

⎯

RBD

RWD

WRD

LAL following RDA to WRA

Delay

(applicable to other bank)

B

= 2

= 4

2

3

⎯

2

3

⎯

L

LAL following WRA to RDA Delay

(applicable to other bank)

1

⎯

1

⎯

cycle

C

= 3

= 4

= 5

5

⎯

1

5

⎯

1

L

Mode Register Set Cycle

Time

I

5

RSC

6

I

PD Low to Inactive State of Input Buffer

PD High to Active State of Input Buffer

⎯

15

18

22

15

18

22

⎯

15

18

22

15

18

22

PD

1

PDA

C

L

C

L

C

L

C

L

C

L

C

L

= 3

= 4

= 5

= 3

= 4

= 5

⎯

Power down mode valid from

REF command

I

PDV

I

Auto-Refresh Cycle Time

REFC

REF Command to Clock Input Disable at

Self-Refresh Entry

I

⎯

I

REFC

⎯

CKD

REFC

DLL Lock-on Time (applicable to RDA

command)

200

LOCK

Rev 1.0

2004-08-20 10/59

TC59LM914/06AMG-37,-50

AC TEST CONDITIONS

SYMBOL

PARAMETER

Input High Voltage (minimum)

VALUE

UNIT

NOTES

V

+ 0.2

V

IH (min)

IL (max)

REF

Input Low Voltage (maximum)

Input Reference Voltage

− 0.2

/2

V

DDQ

Termination Voltage

V

TT

REF

0.7

(AC)

Input Signal Peak to Peak Swing

Differential Clock Input Reference Level

Input Differential Voltage

V

SWING

Vr

V

X

V

(AC)

1.0

2.5

V

ID

SLEW

Input Signal Minimum Slew Rate

Output Timing Measurement Reference Voltage

V/ns

V

/2

9

OTR

DDQ

V

DDQ

V

(AC)

IH min

REF

V

TT

SWING

25 Ω

V

IL max

Output

V

SS

Measurement point

∆T

(AC))/∆T

SLEW = (V

(AC) − V

IL max

AC Test Load

IH min

Note:

(1)

Transition times are measured between V

(DC) and V

(DC).

IH min

IL max

Transition (rise and fall) of input signals have a fixed slope.

(2)

If the result of nominal calculation with regard to t contains more than one decimal place, the result is

CK

rounded up to the nearest decimal place.

(i.e., t

= 0.75 × t , t

= 5 ns, 0.75 × 5 ns = 3.75 ns is rounded up to 3.8 ns.)

DQSS

CK CK

(3)

(4)

These parameters are measured from the differential clock (CLK and CLK ) AC cross point.

These parameters are measured from signal transition point of DQS crossing V level.

REF

In case of DQS enable mode, these parameters are measured from the crossing point of DQS and DQS .

(5)

The t

applies to equally distributed refresh method.

applies to both burst refresh method and distributed refresh method.

REFI (max)

REFI (min)

In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns

always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns)

is to 8 times in the maximum.

(6)

(7)

(8)

(9)

Low Impedance State is specified at V

/2 ± 0.2 V from steady state.

DDQ

High Impedance State is specified where output buffer is no longer driven.

These parameters depend on the clock jitter. These parameters are measured at stable clock.

Output timing is measured by using Normal driver strength at V

= 1.7V∼1.9V.

DDQ

Output timing is measured by using Strong driver strength at V

= 1.4V∼1.6V.

DDQ

(10)

These parameters are measured at t

= minimum∼6.0ns. When t

is longer than 6.0ns, these parameters

CK

are specified as below for all Speed version

t

(MIN/MAX) = −0.6ns / 0.6ns, t (MIN/MAX) = −0.65ns / 0.65ns

CKQS

AC

Rev 1.0

2004-08-20 11/59

TC59LM914/06AMG-37,-50

POWER UP SEQUENCE

(1)

(2)

(3)

(4)

(5)

(6)

As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.

Apply V

before or at the same time as V

.

DD

DDQ

before or at the same time as V

.

DDQ

REF

Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).

After stable power and clock, apply DESL and take PD =H.

Issue EMRS to enable DLL and to define driver strength with OCD calibration mode exit command

(A7∼A9=0). (Note: 1, 2)

(7)

(8)

Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)

Issue two or more Auto-Refresh commands (Note: 1).

(9)

Ready for normal operation after 200 clocks from Extended Mode Register programming.

If OCD calibration (Off Chip Driver impedance adjustment) is used, execute OCD calibration sequence.

(10)

Notes:

(1)

Sequence 6, 7 and 8 can be issued in random order.

Set DQS mode for TC59LM906AMG.

(2)

(3)

(4)

L = Logic Low, H = Logic High

All DQs output level are high impedance state during power up sequence.

2.5V(TYP)

V

DD

1.5V or 1.8V(TYP)

V

DDQ

1/2 V

(TYP)

DDQ

V

REF

CLK

t

PDEX

l

REFC

200us(min)

PDA

RSC

REFC

PD

Command

Address

DQ

200clock cycle(min)

DESL RDA MRS DESL RDA MRS

DESL WRA REF DESL

WRA REF DESL

op-code

EMRS

op-code

MRS

Hi-Z

DQS

Normal Operation

EMRS

MRS

Auto Refresh cycle

Rev 1.0

2004-08-20 12/59

TC59LM914/06AMG-37,-50

TIMING DIAGRAMS

Input Timing

Command and Address

t

CL

CK

CH

t

CK

CLK

t

IS

IH

IS

IH

CS

FN

1st

2nd

IS

2nd

LA

t

IS

IH

IS

IH

A0~A13

BA0∼BA2

UA, BA

Data

• TC59LM906AMG DQS enable mode

DQS

t

DS DH

DQ (input)

Data

• TC59LM906AMG DQS disable mode

• TC59LM914AMG

DQS

t

DS DH

DQ (input)

Refer to the Command Truth Table.

Timing of the CLK, CLK

t

CL

CH

V

IH

CLK

(AC)

V

IL

V

IL

t

T

t

T

t

CK

CLK

V

IH

V

ID

(AC)

IL

V

X

V

X

V

X

Rev 1.0

2004-08-20 13/59

TC59LM914/06AMG-37,-50

Read Timing (Burst Length = 4)

t

CK

CH

CL

CLK

t

IS IH

LAL (after RDA)

Input

(control &

addresses)

DESL

CKQS

t

CKQS

t

QSLZ

t

QSHZ

CKQS

QSP QSP

CAS latency = 3

t

QSPRE

DQS/ DQS

(output)

Hi-Z

Preamble

Postamble

t

QSQV

LZ

QSQ

t

QSQ

t

QSQV

HZ

QSQ

DQ

Hi-Z

Q0

Q1

Q2

Q3

(output)

t

AC

t

OH

t

CKQS

t

CKQS

t

QSLZ

t

CKQS

t

QSHZ

QSP QSP

CAS latency = 4

t

QSPRE

DQS/ DQS

(output)

Hi-Z

Preamble

Postamble

t

QSQ

LZ

QSQV

t

HZ

QSQ

QSQV

DQ

Q0

Q1

Q2

t

Q3

(output)

t

AC

t

OH

t

CKQS

t

CKQS

t

QSLZ

t

CKQS

t

QSHZ

QSP QSP

CAS latency = 5

t

QSPRE

DQS/ DQS

(output)

Hi-Z

Preamble

Postamble

t

LZ

QSQV

QSQ

Q3

t

HZ

QSQ

QSQV

Q2

DQ

Q0

Q1

(output)

t

AC

t

OH

Note: TC59LM914AMG doesn’t have DQS .

The correspondence of LDQS, UDQS to DQ. (TC59LM914AMG)

LDQS

UDQS

DQ0∼DQ7

DQ8∼DQ15

DQS is Hi-Z in DQS disable mode.

DQS mode is chosen by EMRS. (TC59LM906AMG)

When DQS is enable, the condition of DQS is changed from Hi-Z to “High at Preamble and the

condition of DQS is changed from “High” to Hi-Z at Postamble.

Rev 1.0

2004-08-20 14/59

TC59LM914/06AMG-37,-50

Write Timing (Burst Length = 4)

t

CK

CH

CL

CLK

t

IS IH

LAL (after WRA)

Input

(control &

addresses)

DESL

t

DSPSTH

DQSS

t

DSS

DSPRES

t

DSPREH DSP DSP DSP DSPST

CAS latency = 3

DQS/ DQS

(input)

t

Preamble

Postamble

DSS

t

DSPRE

t

DS

t

DS

t

DH

t

DH

DQ

D0

D1

D2

D3

(input)

t

DQSS

t

DSS

t

DSPRES

t

DSPSTH

DSS

t

t t

DSP DSP DSPST

DSPREH

CAS latency = 4

DSP

DQS/ DQS

(input)

Preamble

Postamble

t

DSPRE

t

DS

t

DH

DQ

D3

D0

D1

D2

(input)

t

DQS

t

DSS

t

DSPRES

t

DSS

t

DSPSTH

t

DSPREH

DSP DSP DSP DSPST

CAS latency = 5

DQS/ DQS

(input)

Preamble

Postamble

t

DSPRE

t

DS

t

DS

t

DH

DQ

D3

D0

D1

t

D2

(input)

t

DQSS

Note: TC59LM914AMG doesn’t have DQS .

The correspondence of LDQS, UDQS to DQ. (TC59LM914AMG)

LDQS

UDQS

DQ0∼DQ7

DQ8∼DQ15

DQS is ignored in DQS disable mode.

DQS mode is chosen by EMRS. (TC59LM906AMG)

Rev 1.0

2004-08-20 15/59

TC59LM914/06AMG-37,-50

t

, t

, Ixxxx Timing

REFI PAUSE

CLK

t

, t

, I

REFI PAUSE XXXX

t

IS IH

Input

(control &

addresses)

Command

Note: “I

” means “I ”, “I

RC

”, “I

RCD

”, etc.

RAS

XXXX

Rev 1.0

2004-08-20 16/59

TC59LM914/06AMG-37,-50

Write Timing (x16 device) (Burst Length =4)

CLK

Input

(control &

WRA

LAL

DESL

addresses)

t

DSSK DSSK DSSK DSSK

CAS latency = 3

LDQS

Preamble

t

Postamble

t

DS

t

DH

t

DH

DQ0~DQ7

UDQS

D0

D1

D2

D3

Preamble

Postamble

DH

t

DS

t

DH

D0

D1

D2

D3

DQ8~DQ15

t

DSSK DSSK DSSK DSSK

CAS latency = 4

LDQS

Preamble

t

Postamble

t

DS

t

DH

DQ0~DQ7

UDQS

D0

D1

D2

D3

Preamble

t

Postamble

t

DS

t

DH

t

DH

D0

D1

D2

D3

DQ8~DQ15

t

DSSK DSSK DSSK DSSK

CAS latency = 5

LDQS

Preamble

t

Postamble

t

DS

t

DH

DQ0~DQ7

UDQS

D0

D1

D2

D3

Preamble

t

Postamble

t

DS

t

DH

D0

D1

D2

D3

DQ8~DQ15

Rev 1.0

2004-08-20 17/59

TC59LM914/06AMG-37,-50

FUNCTION TRUTH TABLE (Notes: 1, 2, 3)

Command Truth Table (Notes: 4)

• The First Command

SYMBOL

FUNCTION

Device Deselect

CS

FN

BA2~BA0

A13~A9

A8

A7

A6~A0

DESL

RDA

H

L

×

H

L

×

Read with Auto-close

Write with Auto-close

BA

UA

WRA

• The Second Command (The next clock of RDA or WRA command)

BA1~

A12~ A10~A

SYMBOL

FUNCTION

CS

FN

BA2

A13

A8

A7

A6~A0

BA0

A11

9

LAL

Lower Address Latch (x16)

Lower Address Latch (x8)

Auto-Refresh

H

L

×

V

×

V

×

V

×

L

×

L

×

LA

×

LA

×

LA

×

REF

MRS

Mode Register Set

L

V

Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address,

LA = Lower Address

2. All commands are assumed to issue at a valid state.

3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where

CLK goes to High.

4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and

the command table below.

Read Command Table

COMMAND (SYMBOL)

CS

FN

BA2~BA0

A13~A9

A8

A7

A6~A0

NOTES

5

RDA (1st)

LAL (2nd)

L

H

BA

UA

LA

UA

LA

UA

LA

H

×

Note 5 : For x16 device, A8 is “X” (either L or H).

Write Command Table

• TC59LM914AMG

BA1~

A10~

A9

COMMAND(SYMBOL)

CS

FN

BA2

UA

A13

UA

A12

UA

A11

A8

A7

A6~A0

BA0

WRA (1st)

LAL (2nd)

L

BA

UA

LA

UA

LA

H

×

LVW0 LVW1 UVW0 UVW1

×

• TC59LM906AMG

BA1~

BA0

A10~

A9

COMMAND(SYMBOL)

CS

FN

BA2

A13

A12

A11

A8

A7

A6~A0

WRA (1st)

LAL (2nd)

L

BA

UA

LA

UA

LA

UA

LA

H

×

VW0

VW1

×

Notes: 6. BA2, A13 ∼ A11 are used for Variable Write Length (VW) control at Write Operation.

Rev 1.0

2004-08-20 18/59

TC59LM914/06AMG-37,-50

FUNCTION TRUTH TABLE (continued)

VW Truth Table

Burst Length

Function

Write All Words

VW0

VW1

L

H

L

×

BL=2

Write First One Word

Reserved

L

Write All Words

H

L

BL=4

Write First Two Words

Write First One Word

H

Note 7 : For x16 device, LVW0 and LVW1 control DQ0~DQ7.

UVW0 and UVW1 control DQ8~DQ15.

Mode Register Set Command Table

COMMAND (SYMBOL)

CS

FN

BA2~BA0

A13~A9

A8

A7

A6~A0

NOTES

8

RDA (1st)

L

H

×

MRS (2nd)

×

V

Notes: 8. Refer to “MODE REGISTER TABLE”.

Auto-Refresh Command Table

PD

COMMAND CURRENT

FUNCTION

CS

FN BA2~BA0 A13~A9 A8

A7 A6~A0 NOTES

(SYMBOL)

STATE

n − 1

H

n

H

Active

WRA (1st)

REF (2nd)

Standby

Active

L

×

Auto-Refresh

H

×

Self-Refresh Command Table

PD

COMMAND CURRENT

FUNCTION

CS

FN BA2~BA0 A13~A9 A8

A7 A6~A0 NOTES

(SYMBOL)

STATE

n − 1

H

n

H

L

Active

WRA (1st)

REF (2nd)

⎯

Standby

Active

L

×

Self-Refresh Entry

Self-Refresh Continue

Self-Refresh Exit

H

9, 10

11

Self-Refresh

L

×

SELFX

L

H

Power Down Table

PD

COMMAND CURRENT

FUNCTION

CS

FN BA2~BA0 A13~A9 A8

A7 A6~A0 NOTES

(SYMBOL)

STATE

n − 1

n

L

Power Down Entry

Power Down Continue

Power Down Exit

PDEN

⎯

Standby

H

L

H

×

10

11

Power Down

L

PDEX

H

Notes: 9. PD has to be brought to Low within t

from REF command.

FPDL

10. PD should be brought to Low after DQ’s state turned high impedance.

11. When PD is brought to High from Low, this function is executed asynchronously.

Rev 1.0

2004-08-20 19/59

TC59LM914/06AMG-37,-50

FUNCTION TRUTH TABLE (continued)

PD

CURRENT STATE

CS

FN

ADDRESS COMMAND

ACTION

NOTES

n − 1

H

L

n

H

L

H

L

×

H

L

×

H

L

×

DESL

RDA

WRA

PDEN

⎯

NOP

BA, UA

Row activate for Read

Row activate for Write

Power Down Entry

Illegal

L

BA, UA

Idle

H

L

×

12

L

×

⎯

Refer to Power Down State

Begin Read

H

L

H

L

H

L

LA

LAL

Op-code

MRS/EMRS Access to Mode Register

PDEN Illegal

MRS/EMRS Illegal

Row Active for Read

Row Active for Write

H

L

×

L

×

⎯

Invalid

H

L

H

L

H

L

LA

LAL

Begin Write

Auto-Refresh

Illegal

×

REF

PDEN

H

L

REF (self) Self-Refresh Entry

×

⎯

DESL

RDA

WRA

PDEN

⎯

Invalid

H

L

H

L

H

L

×

Continue Burst Read to End

BA, UA

Illegal

Invalid

13

L

BA, UA

Read

H

L

×

L

×

⎯

Data Write & Continue Burst Write to

End

H

×

DESL

H

L

H

L

H

L

×

H

L

H

L

×

H

L

H

L

×

H

L

×

H

L

×

H

L

×

BA, UA

RDA

WRA

PDEN

⎯

Illegal

Invalid

13

BA, UA

Write

×

L

×

⎯

H

L

H

L

×

DESL

RDA

WRA

PDEN

⎯

NOP → Idle after I

Illegal

REFC

BA, UA

Illegal

Auto-Refreshing

×

Self-Refresh Entry

Illegal

14

L

×

⎯

Refer to Self-Refreshing State

H

L

H

L

×

DESL

RDA

WRA

PDEN

⎯

NOP → Idle after I

Illegal

RSC

BA, UA

Illegal

Mode Register

Accessing

×

Illegal

L

Illegal

×

⎯

Invalid

H

L

×

L

⎯

Invalid

Maintain Power Down Mode

Power Down

Exit Power Down Mode → Idle after

PDEX

L

H

×

PDEX

t

L

H

L

H

×

L

×

H

L

×

⎯

SELFX

⎯

Illegal

Invalid

Maintain Self-Refresh

Exit Self-Refresh → Idle after I

Illegal

Self-Refreshing

H

REFC

Notes: 12. Illegal if any bank is not idle.

13. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA).

14. Illegal if t is not satisfied.

FPDL

Rev 1.0

2004-08-20 20/59

TC59LM914/06AMG-37,-50

MODE REGISTER TABLE

Regular Mode Register (Notes: 1)

*1

*3

A7

ADDRESS

Register

BA1

BA0

BA2, A13~A8

0

A6~A4

CL

A3

BT

A2~A0

BL

0

TE

A7

TEST MODE (TE)

A3

BURST TYPE (BT)

0

1

Regular (default)

Test Mode Entry

0

1

Sequential

Interleave

A6

A5

A4

CAS LATENCY (CL)

A2

A1

A0

BURST LENGTH (BL)

*2

0

1

0

1

0

1

×

0

1

0

1

0

1

Reserved

0

1

0

1

×

0

1

0

1

×

Reserved

2

4

3

4

5

*2

Reserved

*2

Reserved

Extended Mode Register (Notes: 4)

*4

BA2,

A13~A12

*6

*7

A10

*5

ADDRESS

Register

BA1

BA0

A11

A9~A7

OCD

A6

A5~A2

0

A1

A0

0

1

0

DQS

DIC

DS

OUTPUT DRIVE IMPEDANCE CONTROL

(DIC)

A9 A8 A7 Driver Impedance Adjustment

A6 A1

0

1

OCD Calibration mode exit

Drive (1)

0

Normal Output Driver

0

1

0

1

Strong Output Driver

Weak Output Driver

0

1

0

1

0

1

Drive (0)

Adjust mode

Full strength Output Driver

OCD Calibration default

A10

DQS Enable

A0

DLL SWITCH (DS)

0

1

Disable

Enable

0

1

DLL Enable

DLL Disable

Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0.

2. “Reserved” places in Regular Mode Register should not be set.

3. A7 in Regular Mode Register must be set to “0” (low state).

Because Test Mode is specific mode for supplier.

4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0.

5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.

6. A11 in Extended Mode Register must be set to “0”.

7. TC59LM914AMG, A10 in Extended Mode Register is ignored. DQS is available only TC59LM906AMG.

Rev 1.0

2004-08-20 21/59

TC59LM914/06AMG-37,-50

STATE DIAGRAM

SELF-

POWER

DOWN

REFRESH

SELFX

PDEX

( PD = H)

PD = L

PDEN

( PD = L)

STANDBY

(IDLE)

PD = H

AUTO-

MODE

REFRESH

REGISTER

WRA

RDA

REF

MRS

ACTIVE

LAL

(RESTORE)

LAL

WRITE

(BUFFER)

READ

Command input

Automatic return

The second command at Active state

must be issued 1 clock after RDA or

WRA command input.

Rev 1.0

2004-08-20 22/59

TC59LM914/06AMG-37,-50

TIMING DIAGRAMS

SINGLE BANK READ TIMING (CL = 3)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 5 cycles

I

= 5 cycles

I

= 5 cycles

RC

Command RDA LAL

DESL

RDA LAL

DESL

RDA LAL

DESL

RDA

I =1 cycle

RCD

I

= 4 cycles

I =1 cycle

RCD

I

= 4 cycles

I =1 cycle

RCD

I

= 4 cycles

RAS

Address

UA

LA

UA

#0

LA

UA

LA

UA

#0

Bank Add.

#0

BL = 2

Hi-Z

DQS/ DQS

(output)

CL = 3

DQ

Hi-Z

Q0 Q1

(output)

BL = 4

DQS/ DQS

(output)

CL = 3

DQ

Q0 Q1 Q2 Q3

Q0 Q1 Q2

(output)

Note : TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 23/59

TC59LM914/06AMG-37,-50

SINGLE BANK READ TIMING (CL = 4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 5 cycles

I

= 5 cycles

RC

I

= 5 cycles

RC

Command RDA LAL

DESL

RDA LAL

DESL

RDA LAL

DESL

RDA

I

=1 cycle

RCD

I

= 4 cycles

I

=1 cycle

RCD

I

= 4 cycles

I

=1 cycle

RCD

I

= 4 cycles

RAS

Address

UA

LA

UA

LA

UA

LA

UA

#0

Bank Add.

#0

BL = 2

Hi-Z

DQS/ DQS

(output)

CL = 4

DQ

Hi-Z

Q0 Q1

Q0

(output)

BL = 4

DQS/ DQS

(output)

CL = 4

DQ

Q0 Q1 Q2 Q3

Q0

(output)

Note : TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 24/59

TC59LM914/06AMG-37,-50

SINGLE BANK READ TIMING (CL = 5)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 6 cycles

I

= 6 cycles

RC

Command RDA LAL

DESL

RDA LAL

DESL

RDA LAL

DESL

I

=1 cycle

RCD

I

= 5 cycles

I

=1 cycle

RCD

I

= 5 cycles

I

=1 cycle

RCD

RAS

Address

UA

LA

UA

LA

UA

LA

Bank Add.

#0

BL = 2

Hi-Z

DQS/ DQS

(output)

CL = 5

DQ

Hi-Z

Q0 Q1

(output)

BL = 4

DQS/ DQS

(output)

CL = 5

DQ

Q0 Q1 Q2 Q3

(output)

Note : TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 25/59

TC59LM914/06AMG-37,-50

SINGLE BANK WRITE TIMING (CL = 3)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 5 cycles

I

= 5 cycles

RC

I

= 5 cycles

RC

Command

Address

WRA LAL

DESL

WRA LAL

DESL

WRA LAL

DESL

WRA

I

=1 cycle

RCD

I

= 4 cycles

I

=1 cycle

RCD

I

= 4 cycles

I

=1 cycle

RCD

I = 4 cycles

RAS

UA

LA

UA

#0

LA

UA

#0

LA

UA

#0

Bank Add.

#0

BL = 2

DQS/ DQS

(input)

WL = 2

DQ

D0 D1

(input)

BL = 4

DQS/ DQS

(input)

WL = 2

DQ

D0 D1 D2 D3

(input)

Note : TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 26/59

TC59LM914/06AMG-37,-50

SINGLE BANK WRITE TIMING (CL = 4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 5 cycles

I

= 5 cycles

RC

I

= 5 cycles

RC

Command

WRA LAL

DESL

WRA LAL

DESL

WRA LAL

DESL

WRA

I

=1 cycle

RCD

I

= 4 cycles

I

=1 cycle

RCD

I

= 4 cycles

I

=1 cycle

RCD

I

= 4 cycles

RAS

Address

UA

LA

UA

LA

UA

LA

UA

#0

Bank Add.

#0

BL = 2

DQS/ DQS

(input)

WL = 3

DQ

D0 D1

(input)

BL = 4

DQS/ DQS

(input)

WL = 3

DQ

D0 D1 D2 D3

(input)

Note : TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 27/59

TC59LM914/06AMG-37,-50

SINGLE BANK WRITE TIMING (CL = 5)

0

1

2

3

4

5

6

7

8

I

9

10

11

12

13

14

15

CLK

= 6 cycles

I

= 6 cycles

RC

Command

WRA LAL

DESL

WRA LAL

DESL

WRA LAL

DESL

I

=1 cycle

RCD

I

= 5 cycles

I

=1 cycle

RCD

I

= 5 cycles

I

=1 cycle

RCD

RAS

Address

UA

LA

UA

LA

UA

LA

Bank Add.

#0

BL = 2

DQS/ DQS

(input)

WL = 4

DQ

D0 D1

(input)

BL = 4

DQS/ DQS

(input)

WL = 4

DQ

D0 D1 D2 D3

(input)

Note : TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 28/59

TC59LM914/06AMG-37,-50

SINGLE BANK READ-WRITE TIMING (CL = 3)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 5 cycles

I

= 5 cycles

I

= 5 cycles

RC

Command

Address

RDA LAL

DESL

WRA LAL

DESL

RDA LAL

DESL

WRA

UA

#0

LA

UA

#0

LA

UA

#0

LA

Bank Add.

#0

BL = 2

Hi-Z

DQS

Hi-Z

DQS

DQ

CL = 3

WL = 2

CL = 3

Q0 Q1

D0 D1

Q0 Q1

BL = 4

Hi-Z

DQS

DQ

CL = 3

WL = 2

CL = 3

Hi-Z

Q0 Q1 Q2 Q3

D0 D1 D2 D3

Q0 Q1 Q2

Note : TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 29/59

TC59LM914/06AMG-37,-50

SINGLE BANK READ-WRITE TIMING (CL = 4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 5 cycles

I

= 5 cycles

RC

I

= 5 cycles

RC

Command

Address

RDA LAL

DESL

WRA LAL

DESL

RDA LAL

DESL

WRA

UA

#0

LA

UA

#0

LA

UA

#0

LA

Bank Add.

#0

BL = 2

Hi-Z

DQS

Hi-Z

DQS

DQ

CL = 4

WL = 3

CL = 4

Q0 Q1

D0 D1

Q0

BL = 4

Hi-Z

DQS

DQ

CL = 4

WL = 3

CL = 4

Hi-Z

Q0 Q1 Q2 Q3

D0 D1 D2 D3

Q0

Note : TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 30/59

TC59LM914/06AMG-37,-50

SINGLE BANK READ-WRITE TIMING (CL = 5)

0

1

2

3

4

5

6

7

8

I

9

10

11

12

13

14

15

CLK

= 6 cycles

I

= 6 cycles

RC

Command

Address

RDA LAL

DESL

WRA LAL

DESL

RDA LAL

DESL

UA

#0

LA

UA

#0

LA

UA

#0

LA

Bank Add.

BL = 2

Hi-Z

DQS

Hi-Z

DQS

DQ

CL = 5

WL = 4

Q0 Q1

D0 D1

BL = 4

Hi-Z

DQS

DQ

WL = 4

CL = 5

Hi-Z

Q0 Q1 Q2 Q3

D0 D1 D2 D3

Note : TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 31/59

TC59LM914/06AMG-37,-50

MULTIPLE BANK READ TIMING (CL = 3)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 2 cycles

I

= 2 cycles I

= 2 cycles

RBD

Command

Address

RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank Add.

I

(Bank"a") = 5 cycles

RC

I

(Bank"b") = 5 cycles

RC

BL = 2

Hi-Z

DQS/ DQS

(output)

CL = 3

DQ

Hi-Z

Qa0Qa1

Qb0Qb1

Qa0Qa1

Qb0Qb1

Qc0Qc1

Qd0Qd1

(output)

BL = 4

DQS/ DQS

(output)

CL = 3

DQ

Hi-Z

Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3

Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2Qc3Qd0Qd1

(output)

Note: l

to the same bank must be satisfied.

RC

TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 32/59

TC59LM914/06AMG-37,-50

MULTIPLE BANK READ TIMING (CL = 4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 2 cycles

I

= 2 cycles I

= 2 cycles

RBD

Command RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA

Address

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank Add.

I

(Bank"a") = 5 cycles

RC

I

(Bank"b") = 5 cycles

RC

BL = 2

Hi-Z

DQS/ DQS

(output)

CL = 4

DQ

Hi-Z

Qa0Qa1

Qb0Qb1

Qa0Qa1

Qb0Qb1

Qc0Qc1

(output)

BL = 4

Hi-Z

DQS/ DQS

(output)

CL = 4

DQ

Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3

Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2

(output)

Note: l

to the same bank must be satisfied.

RC

TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 33/59

TC59LM914/06AMG-37,-50

MULTIPLE BANK READ TIMING (CL = 5)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 2 cycles

I

= 2 cycles I

= 2 cycles

RBD

Command RDA LAL RDA LAL

DESL

RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL

Address

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank Add.

I

(Bank"a") = 6 cycles

RC

I

(Bank"b") = 6 cycles

RC

BL = 2

Hi-Z

DQS/ DQS

(output)

CL = 5

DQ

Hi-Z

Qa0Qa1

Qb0Qb1

Qa0Qa1

Qb0Qb1

(output)

BL = 4

DQS/ DQS

(output)

CL = 5

DQ

Hi-Z

Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3

Qa0Qa1Qa2Qa3Qb0Qb1Qb2

(output)

Note: l

to the same bank must be satisfied.

RC

TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 34/59

TC59LM914/06AMG-37,-50

MULTIPLE BANK WRITE TIMING (CL = 3)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 2 cycles

I

= 2 cycles I

= 2 cycles

RBD

Command WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA

Address

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank

"b"

Bank Add.

I

(Bank"a") = 5 cycles

RC

I

(Bank"b") = 5 cycles

RC

BL = 2

DQS/ DQS

(input)

WL = 2

DQ

Da0Da1

Db0Db1

Da0Da1

Db0Db1

Dc0Dc1

Dd0Dd1

(input)

BL = 4

DQS/ DQS

(input)

WL = 2

DQ

Da0Da1Da2Da3Db0Db1Db2Db3

Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1Dc2Dc3Dd0Dd1Dd2Dd3

(input)

Note: l

to the same bank must be satisfied.

RC

TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 35/59

TC59LM914/06AMG-37,-50

MULTIPLE BANK WRITE TIMING (CL = 4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 2 cycles

I

= 2 cycles I

= 2 cycles

RBD

Command WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA

Address

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank

"b"

Bank Add.

I

(Bank"a") = 5 cycles

RC

I

(Bank"b") = 5 cycles

RC

BL = 2

DQS/ DQS

(input)

WL = 3

DQ

Da0Da1

Db0Db1

Da0Da1

Db0Db1

Dc0Dc1

Dd0Dd1

(input)

BL = 4

DQS/ DQS

(input)

WL = 3

DQ

Da0Da1Da2Da3Db0Db1Db2Db3

Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1Dc2Dc3Dd0Dd1

(input)

Note: l

to the same bank must be satisfied.

RC

TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 36/59

TC59LM914/06AMG-37,-50

MULTIPLE BANK WRITE TIMING (CL = 5)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 2 cycles

I

= 2 cycles I

= 2 cycles

RBD

Command WRA LAL WRA LAL

DESL

WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL

Address

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank Add.

I

(Bank"a") = 6 cycles

RC

I

(Bank"b") = 6 cycles

RC

BL = 2

DQS/ DQS

(input)

WL = 4

DQ

Da0Da1

Db0Db1

Da0Da1

Db0Db1

Dc0Dc1

(input)

BL = 4

DQS DQS

(input)

WL = 4

DQ

Da0Da1Da2Da3Db0Db1Db2Db3

Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1

(input)

Note: l

to the same bank must be satisfied.

RC

TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 37/59

TC59LM914/06AMG-37,-50

MULTIPLE BANK READ-WRITE TIMING (BL = 2)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

= 2 cycles

RBD

I

= 1 cycle

I

= 2 cycles

Command WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA

WRD

RWD

I

= 1 cycle

I

= 2 cycles

I

= 1 cycle

I

= 2 cycles

UA

WRD

RWD

WRD

RWD

Address

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"d"

Bank

"a"

Bank

"b"

Bank

"c"

Bank Add.

I

(Bank"a")

RC

I

(Bank"b")

RC

CL = 3

Hi-Z

DQS

CL = 3

WL = 2

Hi-Z

DQ

Da0Da1

Qb0Qb1

Dc0Dc1

Qd0Qd1

Da0Da1

CL = 4

DQS

CL = 4

WL = 3

Hi-Z

Da0Da1

Qb0Qb1

Dc0Dc1

Qd0Qd1

Da0Da1

DQ

CL = 5

DQS

Hi-Z

DQS

DQ

CL = 5

WL = 4

Hi-Z

Da0Da1

Qb0Qb1

Dc0Dc1

Qd0Qd1

Da0Da1

Note: l

to the same bank must be satisfied.

RC

TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 38/59

TC59LM914/06AMG-37,-50

MULTIPLE BANK READ-WRITE TIMING (BL = 4)

0

1

2

3

4

5

6

7

8

I

9

10

11

12

13

14

15

CLK

I

= 2 cycles

RBD

I

= 1 cycle

= 2 cycles

DESL

RWD

Command

WRA LAL RDA LAL

DESL

= 3 cycles

WRA LAL RDA LAL

WRD

I

= 1 cycle

I

= 1 cycle

I

= 3 cycles

I

= 1 cycle

WRD

RWD

WRD

RWD

WRD

Address

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

UA

LA

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank

"b"

Bank Add.

I

(Bank"a")

RC

I

(Bank"b")

RC

CL = 3

Hi-Z

DQS

CL = 3

WL = 2

Hi-Z

Da0Da1Da2Da3

Qb0Qb1Qb2Qb3

Dc0Dc1Dc2Dc3

Qd0Qd1Qd2Qd3

DQ

CL = 4

Hi-Z

DQS

CL = 4

WL = 3

Hi-Z

Da0Da1Da2Da3

Qb0Qb1Qb2Qb3

Dc0Dc1Dc2Dc3

Qd0Qd1Qd2Qd3

DQ

CL = 5

Hi-Z

DQS

DQ

CL = 5

WL = 4

Hi-Z

Da0Da1Da2Da3

Qb0Qb1Qb2Qb3

Dc0Dc1Dc2Dc3

Qd0Qd1Qd2Qd3

Note: l

to the same bank must be satisfied.

RC

TC59LM914AMG doesn’t have DQS .

Rev 1.0

2004-08-20 39/59

TC59LM914/06AMG-37,-50

WRITE with VARIAVLE WRITE LENGTH (VW) CONTROL (CL = 4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

BL = 2, SEQUENTIAL MODE

Command

WRA LAL

DESL

WRA LAL

DESL

LA=#3

VW=All

LA=#1

VW=1

Address

UA

VW0 = Low

VW1 = don't care

VW0 = High

VW1 = don't care

Bank

"a"

Bank

"a"

Bank Add.

DQS/ DQS

(input)

DQ

D0 D1

D0

(input)

Lower Address #3 #2

#1 (#0)

Last one data is masked.

BL = 4, SEQUENTIAL MODE

Command

Address

WRA LAL

DESL

WRA LAL

DESL

WRA LAL

DESL

LA=#3

LA=#1

LA=#2

UA

VW=All

VW=1

VW=2

VW0 = High

VW1 = Low

VW0 = High

VW1 = High

VW0 = Low

VW1 = High

Bank

"a"

Bank

"a"

Bank

"a"

Bank Add.

DQS/ DQS

(input)

DQ

D0 D1 D2 D3

D0

D0 D1

#2 #3 (#0)(#1)

(input)

Lower Address #3 #0 #1 #2

#1(#2)(#3)(#0)

Last three data are masked. Last two data are masked.

Note: DQS ( DQS ) input must be continued till end of burst count even if some of laster data is masked.

Rev 1.0

2004-08-20 40/59

TC59LM914/06AMG-37,-50

POWER DOWN TIMING (CL = 4, BL = 4)

Read cycle to Power Down Mode

0

1

2

3

4

5

6

7

8

9

10

n-1

n

n+1

n+2

n+3

CLK

I

PDA

RDA

or

Command

Address

RDA LAL

DESL

WRA

UA

LA

UA

t

I

= 1 cycle

PD

IS

t

IH

PD

t

QPDH

PDEX

l

, t

RC(min) REFI(max)

Hi-Z

DQS

(output)

Hi-Z

DQS

(output)

CL = 4

DQ

(output)

Q0 Q1 Q2 Q3

Power Down Entry

Power Down Exit

cycles later.

Note: PD must be kept "High" level until end of Burst data output.

PD should be brought to "High" within t

(max.) to maintain the data written into cell.

REFI

In Power Down Mode, PD "Low" and a stable clock signal must be maintained.

When PD is brought to "High", a valid executable command may be applied l

TC59LM914AMG doesn’t have DQS .

PDA

Rev 1.0

2004-08-20 41/59

TC59LM914/06AMG-37,-50

POWER DOWN TIMING (CL = 4, BL = 4)

Write cycle to Power Down Mode

0

1

2

3

4

5

6

7

8

9

10

n-1

n

n+1

n+2

PDA

n+3

CLK

I

RDA

or

Command

Address

WRA LAL

DESL

WRA

UA

LA

UA

t

IS

I

= 1 cycle

PD

t

IH

PD

WL = 3

2 clock cycles

t

PDEX

l

, t

RC(min) REFI(max)

DQS

(input)

DQS

(input)

WL = 3

DQ

(input)

D0 D1 D2 D3

Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.

PD should be brought to "High" within t (max.) to maintain the data written into cell.

REFI

In Power Down Mode, PD "Low" and a stable clock signal must be maintained.

When PD is brought to "High", a valid executable command may be applied l

TC59LM914AMG doesn’t have DQS .

cycles later.

PDA

Rev 1.0

2004-08-20 42/59

TC59LM914/06AMG-37,-50

MODE REGISTER SET TIMING (CL = 4, BL = 2)

From Read operation to Mode Register Set operation.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

RSC

RDA

or

Command

A13~A0

RDA LAL

DESL

RDA MRS

DESL

LAL

LA

WRA

Valid

(opcode)

UA

BA

LA

UA

BA

BA0="0"

BA1="0"

BA2="0"

BA0~BA2

CL + BL/2

Hi-Z

DQS

(output)

Hi-Z

DQS

DQ

Q0 Q1

(output)

Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.

TC59LM914AMG doesn’t have DQS .

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TC59LM914/06AMG-37,-50

MODE REGISTER SET TIMING (CL = 4, BL = 4)

From Write operation to Mode Register Set operation.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

RSC

RDA

or

Command

A13~A0

WRA LAL

DESL

RDA MRS

DESL

LAL

LA

WRA

Valid

(opcode)

UA

BA

LA

UA

BA

BA0="0"

BA1="0"

BA2="0"

BA0~BA2

WL+BL/2

DQS

(input)

DQS

(input)

DQ

D0 D1 D2 D3

(input)

Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.

TC59LM914AMG doesn’t have DQS .

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TC59LM914/06AMG-37,-50

EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2)

From Read operation to Extended Mode Register Set operation.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

RSC

RDA

or

Command

A13~A0

RDA LAL

DESL

RDA MRS

DESL

LAL

LA

WRA

Valid

(opcode)

UA

BA

LA

UA

BA

BA0="1"

BA1="0"

BA2="0"

BA0~BA2

CL + BL/2

Hi-Z

DQS

(output)

Hi-Z

DQS

(output)

DQ

Q0 Q1

(output)

Note: Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.

DLL switch in Extended Mode Register must be set to enable mode for normal operation.

DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.

TC59LM914AMG doesn’t have DQS .

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TC59LM914/06AMG-37,-50

EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4)

From Write operation to Extended Mode Register Set operation.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

I

RSC

RDA

or

Command

A13~A0

WRA LAL

DESL

RDA MRS

DESL

LAL

LA

WRA

Valid

(opcode)

UA

BA

LA

UA

BA

BA0="1"

BA1="0"

BA2="0"

BA0~BA2

WL+BL/2

DQS

(input)

DQS

(input)

DQ

D0 D1 D2 D3

(input)

Note: DLL switch in Extended Mode Register must be set to enable mode for normal operation.

DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.

Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.

TC59LM914AMG doesn’t have DQS .

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TC59LM914/06AMG-37,-50

AUTO-REFRESH TIMING (CL = 4, BL = 4)

0

1

2

3

4

5

6

7

n − 1

n

n + 1

n + 2

CLK

I

= 5 cycles

I

= 18 cycles

RC

REFC

RDA LAL or

or MRS or

WRA REF

Command

RDA

LAL

DESL

WRA

REF

DESL

Bank,

UA

Bank, Address

LA

I

= 1 cycle

I

= 4 cycles

I = 1 cycle

RCD

RAS

DQS/ DQS

(output)

Hi-Z

CL = 4

DQ

Hi-Z

Q0 Q1 Q2 Q3

(output)

Note: In case of CL = 4, I

REFC

must be meet 18 clock cycles.

When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh

command specified by t must be satisfied.

REFI

is average interval time in 8 Refresh cycles that is sampled randomly.

t

REFI

TC59LM914AMG doesn’t have DQS .

t

1

t

2

t

3

t

7

t

8

CLK

WRA REF

8 Refresh cycle

Total time of 8 Refresh cycle

8

t + t + t + t + t + t + t + t

1 2 3 4 5 6 7 8

t

=

REFI

8

t

is specified to avoid partly concentrated current of Refresh operation that is activated larger area

REFI

than Read / Write operation.

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TC59LM914/06AMG-37,-50

SELF-REFRESH ENTRY TIMING

0

1

2

3

4

5

m − 1

m

m + 1

CLK

I

= 1 cycle

RCD

I

REFC

Command

PD

WRA

REF

DESL

t

FPDL (min) FPDL (max)

Auto Refresh

Self Refresh Entry

*2

I

PDV

t

QPDH

I

CKD

Hi-Z

DQS/ DQS

(output)

DQ

Qx

(output)

Notes: 1.

is don’t care.

2. PD must be brought to "Low" within the timing between t

(min) and t

(max) to Self Refresh

FPDL

mode. When PD is brought to "Low" after l

, FCRAM perform Auto Refresh and enter Power

PDV

down mode. In case of PD fall between t

(max) and l

, FCRAM will either entry

PDV

FPDL

Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be specified which

mode FCRAM operates.

3. It is desirable that clock input is continued at least l

brought to “Low” for Self-Refresh Entry.

from REF command even though PD is

CKD

4. TC59LM914AMG doesn’t have DQS .

5. In the case of Self-Refresh entry after Write Operation, the delay time from the LAL command

following WRA to the REF command is Write Latency (WL) +3 clock cycles minimum.

SELF-REFRESH EXIT TIMING

0

1

2

m − 1

m

m + 1

m + 2

n − 1

n

n + 1

p − 1

p

CLK

*6

Command (1st)

*2

*6

I

REFC

Command (2nd)

*7

*3

*5

*7

Command

PD

DESL

WRA

REF

DESL

RDA

LAL

*4

I

= 1 cycle

I

= 1 cycle

I

= 1 cycles

RCD

PDA

t

PDEX

I

LOCK

DQS/ DQS

(output)

Hi-Z

DQ

Hi-Z

(output)

Self-Refresh Exit

Notes: 1. is don’t care.

2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.

3. DESL command must be asserted during I after PD is brought to “High”.

REFC

is defined from the first clock rising edge after PD is brought to “High”.

4.

I

PDA

5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any

other operation.

6. Any command (except Read command) can be issued after I

.

REFC

7. Read command (RDA + LAL) can be issued after I

.

LOCK

8. TC59LM914AMG doesn’t have DQS .

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TC59LM914/06AMG-37,-50

FUNCTIONAL DESCRIPTION

TM

Network FCRAM

FCRAM^TMis an acronym of Fast Cycle Random Access Memory. The Network FCRAM^TMis competent to

perform fast random core access, low latency and high-speed data transfer.

PIN FUNCTIONS

CLOCK INPUTS: CLK & CLK

The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The

CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative

edge of CLK . The DQS and DQ output are aligned to the crossing point of CLK and CLK . The timing reference

point for the differential clock is when the CLK and CLK signals cross during a transition.

POWER DOWN: PD

The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock

Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if

any Read or Write operation is being performed.

CS

CHIP SELECT & FUNCTION CONTROL:

& FN

The CS and FN inputs are a control signal for forming the operation commands on FCRAM^TM. Each operation

mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs.

BANK ADDRESSES: BA0~BA2

The BA0 to BA2 inputs are latched at the time of assertion of the RDA or WRA command and are selected the

bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register

Set command (MRS or EMRS).

BA0

BA1

BA2

Bank #0

Bank #1

Bank #2

Bank #3

Bank #4

Bank #5

Bank #6

Bank #7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Also, when BA2 input assign to A14 input, TC59LM914/06AMG can function as 4 bank devices and can keep

backward compatibility to 256Mb (4bank) Network FCRAM.

ADDRESS INPUTS: A0~A13

Address inputs are used to access the arbitrary address of the memory cell array within each bank. The

Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are

latched at the LAL command. The A0 to A13 inputs are also used for setting the data in the Regular or

Extended Mode Register set cycle.

I/O organization

UPPER ADDRESS

LOWER ADDRESS

8 bits

16 bits

8 bits

A0~A13

A0~A8

A0~A7

A0~A8

A0~A7

8 bank operation

4 bank operation

A0~A13

A0~A13, BA2(A14)

16 bits

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TC59LM914/06AMG-37,-50

DATA INPUT/OUTPUT: DQ0~DQ7 or DQ15

The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The output

data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal.

DATA STROBE: DQS, DQS

The DQS is bi-directional signal. Both edge of DQS are used as the reference of data input or output. In write

operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS is an

output signal provides the read data strobe.

TC59LM906AMG has differential data strobe pin ( DQS ). When DQS is enable mode, DQS is differential

output signal for DQS in read operation, data input are latched at the crossing point of DQS and DQS in Write

operation. When DQS is disable mode, DQS is always Hi-Z, and data input are latched at the crossing point of

DQS and VREF level. DQS mode is set at Extended Mode Register Set Cycle.

TC59LM914AMG doesn’t have DQS pin. Data input are latched at the crossing point of L/UDQS and VREF

level in Write operation. LDQS is strobe signal for DQ0-DQ7. UDQS is strobe signal for DQ8-DQ15.

POWER SUPPLY: V , V

, V , V

DD DDQ SS SSQ

V

and V are power supply pins for memory core and peripheral circuits.

DD

SS

and V

are power supply pins for the output buffer.

DDQ

SSQ

REFERENCE VOLTAGE: V

REF

V

REF

is reference voltage for all input signals.

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TC59LM914/06AMG-37,-50

COMMAND FUNCTIONS and OPERATIONS

TC59LM914/06AMG are introduced the two consecutive command input method. Therefore, except for Power

Down mode, each operation mode decided by the combination of the first command and the second command from

stand-by states of the bank to be accessed.

Read Operation (1st command + 2nd command = RDA + LAL)

Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank

designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next

clock of the RDA command, the data is read out sequentially synchronizing with the both edges of DQS/ DQS

output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing of

the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read

data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back

automatically to the idle state after l . DQS is differential data strobe signal supported TC59LM906AMG.

RC

Write Operation (1st command + 2nd command = WRA + LAL)

Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank

designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the

next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of

DQS/ DQS input signal (Burst Write Operation). The data and DQS/ DQS inputs have to be asserted in keeping

with clock input after CAS latency-1 from the issuing of the LAL command. The DQS/ DQS has to be provided

for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write

operated bank goes back automatically to the idle state after l . Write Burst Length is controlled by VW0 and

RC

VW1 inputs with LAL command. See VW truth table. DQS is differential data strobe signal supported

TC59LM906AMG.

Auto-Refresh Operation (1st command + 2nd command = WRA + REF)

TC59LM914/06AMG are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with

the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks

are in the idle state. In a point to notice, the write mode started with the WRA command is canceled by the REF

command having gone into the next clock of the WRA command instead of the LAL command. The minimum

period between the Auto-Refresh command and the next command is specified by l . However, about a

REFC

synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh,

Auto-Refresh command has to be issued within once for every 3.9 µs by the maximum. In case of burst refresh or

random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than

400 ns always. In other words, the number of Auto-Refresh cycles that be performed within 3.2 µs (8 × 400 ns) is

to 8 times in the maximum.

PD

= “L”)

Self-Refresh Operation (1st command + 2nd command = WRA + REF with

In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer.

When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM914/06AMG become

Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within t

from the

FPDL

REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh

period, the Self-Refresh entry command should be asserted within 3.9 µs after the latest Auto-Refresh command.

Once the device enters Self-Refresh mode, the DESL command must be continued for l

period. In addition, it

REFC

is desirable that clock input is kept in l

period. The device is in Self-Refresh mode as long as PD held “Low”.

CKD

During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power

dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along

with the DESL command, and the DESL command has to be continuously issued in the number of clocks specified

by l . The Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh

REFC

command is issued to avoid the violation of the refresh period just after l

from Self-Refresh exit.

REFC

PD

= “L”)

Power Down Mode (

When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM914/06AMG become Power

Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output

buffers are disabled after specified time except for PD . Therefore, the power dissipation lowers. To exit the

Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for two clock cycle

after PD goes high. The Power Down exit function is asynchronous operation.

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TC59LM914/06AMG-37,-50

Mode Register Set (MRS) and Extended Mode Register Set (EMRS)

(1st command + 2nd command = RDA + MRS)

When all banks are in the idle state, issuing the MRS command following to the RDA command can program

the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS

command having gone into the next clock of the RDA command instead of the LAL command. The data to be set

in the Mode Register is transferred using A0 to A13, BA0 to BA2 address inputs. The TC59LM914/06AMG have

two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is

chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a

read or write cycle. The Regular Mode Register has four function fields.

The four fields are as follows:

(R-1) Burst Length field to set the length of burst data

(R-2) Burst Type field to designate the lower address access sequence in a burst cycle

(R-3) CAS Latency field to set the access time in clock cycle

(R-4) Test Mode field to use for supplier only.

The Extended Mode Register has four function fields.

The five fields are as follows:

(E-1) DLL Switch field to choose either DLL enable or DLL disable.

(E-2) Output Driver Impedance Control field.

(E-3) Off-Chip Driver (OCD) Impedance Adjustment for full strength output driver.

(E-4) DQS enable field.

Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register

is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended

Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before

proper operation.

•

Regular Mode Register/Extended Mode Register change bits (BA0, BA1)

These bits are used to choose either Regular MRS or Extended MRS

BA1

BA0

Mode Register Set

0

1

0

1

×

Regular MRS

Extended MRS

Reserved

Regular Mode Register Fields

(R-1) Burst Length field (A2 to A0), (BL)

This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length

to be 2 or 4 words.

A2

A1

A0

BURST LENGTH

0

1

0

1

×

0

1

0

1

×

Reserved

2 words

4 words

Reserved

(R-2) Burst Type field (A3), (BT)

The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”, Sequential

mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst

length of 2 and 4 words.

A3

BURST TYPE

0

1

Sequential

Interleave

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TC59LM914/06AMG-37,-50

•

Addressing sequence of Sequential mode

A column access is started from the inputted lower address and is performed by incrementing the lower

address input to the device.

CAS Latency = 4

CLK

Command

RDA

LAL

DQS/

DQS

DQ

Data Data Data Data

0

1

2

3

Addressing sequence for Sequential mode

DATA

ACCESS ADDRESS

BURST LENGTH

Data 0

Data 1

Data 2

Data 3

n

2 words (address bits is LA0)

not carried from LA0~LA1

n + 1

n + 2

n + 3

4 words (address bits is LA1, LA0)

not carried from LA1~LA2

•

Addressing sequence of Interleave mode

A column access is started from the inputted lower address and is performed by interleaving the address bits

in the sequence shown as the following.

Addressing sequence for Interleave mode

DATA

ACCESS ADDRESS

BURST LENGTH

Data 0

Data 1

Data 2

Data 3

ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0

2 words

4 words

(R-3) CAS Latency field (A6 to A4), (CL)

This field specifies the number of clock cycles from the assertion of the LAL command following the

RDA command to the first data read. The minimum values of CAS Latency depends on the frequency

of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.

A6

A5

A4

CAS LATENCY

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

3

4

5

Reserved

(R-4) Test Mode field (A7), (TE)

This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.

(R-5) Reserved field in the Regular Mode Register

•

Reserved bits (A8 to A13, BA2)

These bits are reserved for future operations. They must be set to “0” for normal operation.

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TC59LM914/06AMG-37,-50

Extended Mode Register fields

(E-1) DLL Switch field (A0), (DS)

This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. This bit must set to “0” for

normal operation.

(E-2) Output Driver Impedance Control field (A1, A6) (DIC)

This field is used to choose Output Driver Strength. Four types of Driver Strength are supported.

Output Driver Strength can be set by field in EMRS with OCD calibration default (A7~A9=1 at EMRS).

A6

A1

OUTPUT DRIVER IMPEDANCE CONTROL

0

1

0

1

0

1

Normal Output Driver

Strong Output Driver

Weak Output Driver

Full Strength Output Driver

(E-3) Off-Chip Driver (OCD) Impedance Adjustment for full strength output driver (A7 to A9) (OCD)

Output Driver Strength can be set by DIC field (E-2). In case of choosing Full strength Output Driver,

OCD calibration is available. The driver strength set by DIC field is the initial driver level at OCD

Impedance Adjustment. When OCD calibration is performed, A1 and A6 inputs at EMRS must be “1” for

Full Strength Output Driver.

The Network FCRAM^TMsupports driver calibration feature and the flow chart below is an example of

sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before

any other command being issued. MRS should be set before entering OCD impedance adjustment.

MRS should be set before entering OCD impedance adjustment.

Start

EMRS: OCD calibration mode exit

EMRS: Drive(1)

EMRS: Drive(0)

DQ &DQS High; DQS Low

DQ &DQS Low; DQS High

ALL OK

Test

Need Calibration

EMRS: OCD calibration mode exit

EMRS:

Enter Adjust Mode

BL=4 code Input to all DQs

Inc, Dec, or NOP

BL=4 code Input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

End

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TC59LM914/06AMG-37,-50

Extended Mode Register Set for OCD Impedance adjustment

OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are

driven out by Network FCRAM. In drive (1) mode, all DQ, DQS signals are driven high and DQS signals are

driven low. In drive (0) mode, all DQ, DQS signals are driven low and DQS signals are driven high. In adjust

mode, BL=4 of operation code data must be used

A9

A8

A7

Operation

0

1

0

1

0

1

0

1

0

1

OCD calibration mode exit

Drive (1) DQ, DQS high and DQS low

Drive (0) DQ, DQS low and DQS high

Adjust mode

OCD calibration default

OCD impedance adjust

To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit

burst code to Network FCRAM. For this operation, Burst Length has to be set to BL=4 via MRS command

before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 means all

DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DQs

simultaneously and after OCD calibration, all DQs of a given Network FCRAM will be adjusted to the same

driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further

increment or decrement code has no effect.

Off-Chip Driver Program

4bit burst code inputs to all DQs

Operation

Pull-down driver strength

D

T0

D

T1

D

T2

D

T3

Pull-up driver strength

0

1

0

1

0

1

0

1

0

1

0

NOP (No operation)

Increase by 1 step

Decrease by 1 step

NOP

NOP (No operation)

NOP

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

NOP

1

0

1

0

1

0

1

0

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

Other Combinations

Reserved

For proper operation of adjust mode, WL=CL-1 clocks and t_DS/ t_DHshould be met as the following timing

diagram. For input data pattern for adjustment, DT0~DT3 is a fixed order and “not affected by MRS addressing

mode (i.e. Sequential or interleave).

Driver strength is controlled within the following range by OCD impedance adjustment.

SYMBOL

PARAMETER

MIN

MAX

UNIT

mA

NOTES

Output Source DC Current for V Q = 1.7V~1.9V

DD

I

(DC)

−14.0

−18.7

OH

V

Q = 1.7V

DD

V

= 1.420V

OH

Full Strength

Output Driver

Output Sink DC Current for V Q = 1.7V~1.9V

DD

I

14.0

18.7

OL

V

Q = 1.7V

DD

V

= 0.280V

OL

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TC59LM914/06AMG-37,-50

OCD adjust mode

EMRS

OCD calibration mode exit

Command

RDA

NOP

RDA

EMRS

NOP

CLK

WL

1clock

DQS

DQS_in

DQ_in

t

DS DH

D

T1

D

T2

D

T3

T0

Drive mode

Drive mode, both Drive (1) and Drive (0), is used for controllers to measure Network FCRAM Driver

impedance. In this mode, all outputs are driven out t_OITafter “enter drive mode” command and all output

drivers are turned-off t_OITafter “OCD calibration mode exit” command as the following timing diagram.

OCD calibration mode exit

EMRS

Enter Drive mode

EMRS

Command

RDA

NOP

RDA

NOP

CLK

DQS,

DQS

DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0)

DQs high for Drive (1), DQs low for Drive (0)

DQ

t

OIT

0∼12ns

(E-4) DQS enable field (A10), ( DQS )

This bit is used to enable Differential Data strobe.

DQS is available on TC59LM906AMG. This field of TC59LM914AMG is ignored.

A10

DQS Enable

0

1

Disable

Enable

(E-5) Interface mode select (A11)

This bit must be always set “0”.

(E-6) Reserved field (A2 to A5, A12 to A13, BA2)

These bits are reserved for future operations and must be set to “0” for normal operation.

Rev 1.0

2004-08-20 56/59

TC59LM914/06AMG-37,-50

PACKAGE DIMENSIONS

P-BGA64-1317-1.00AZ

16.5

0

13.086_-0.15

0.2 S

0.5 0.05

1.25

0.08

S

AB

B

1.0

2.0

Note: In order to support a package, four outer balls located on F and K row are required to assembly to board.

These four ball is not connected to any electrical level.

Weight: 0.23g (typ.)

Rev 1.0

2004-08-20 57/59

TC59LM914/06AMG-37,-50

REVISION HISTORY

− Rev.0.9 (Feb. 27 ’2004)

− Rev0.91 (Mar. 16 ‘2004)

• Corrected TYPO (page57). Pin name is changed from “Q” to “R”.

− Rev0.92 (Apr. 21 ‘2004)

• Parameter definition in Recommended DC, AC Operating Conditions Table are changed (page 5).

− V (DC): Differential Clock DC Input Voltage

ICK

− V (DC): Input DC Differential Voltage. CLK and /CLK inputs (DC)

ID

− V (AC): Input AC Differential Voltage. CLK and /CLK inputs (AC)

ID

− V (AC),min is changed from 0.55V to 0.5V.

ID

− V (AC): Differential Clock AC Middle Level.

ISO

• CLK is changed to V and CLK is changed to V (page 6).

TR

CP

• Below comment is added in Note(10) (page 6).

VTR is the true input (such as CLK, DQS) level and VCP is the complementary input (such as CLK , DQS )

level.

− Rev0.93 (Jun. 9 ‘2004)

• Package name (P−BGA64−1317−1.00AZ) added (page 1).

• t

(Auto-Refresh Average Interval) spec changed from 7.8µs to 3.9µs (page 1, 10, 51).

REFI

• V

range changed from 2.5V ± 0.15V to 2.5V ± 0.125V.

DD

• Corrected TYPO (page 9, 10, 14, 15, 17)

• t spec changed for all speed bin as below (page 9)

DSP

t

= 0.4 × t

= 0.6 × t

→ 0.35 × t

→ 0.65 × t

CK

DSP(min)

DSP(max)

CK CK

CK

• t and t spec changed for all speed bin as below (page 9)

IS

IH

“−37”:

“−45”:

“−50”:

t

= 0.6ns → 0.5ns

= 0.7ns → 0.6ns

= 0.8ns → 0.7ns

,

t

IH

t

IH

t

IH

= 0.6ns → 0.5ns

= 0.7ns → 0.6ns

= 0.8ns → 0.7ns

IS

• t

(DQS Input Falling Edge Hold Time from CLK) added (page 9).

(OCD drive mode output delay time) added (page 10, 56).

DSH

OIT

• OCD definition at power up sequence added (page 12).

• Note (4) added at power up sequence (page 12).

• OCD setting on Extended Mode Register table changed as below (page 21, 54, 55)

(A9, A8, A7) = (0, 0, 0): OCD Calibration default → OCD Calibration mode exit.

(A9, A8, A7) = (1, 1, 1): OCD Calibration mode exit → OCD Calibration mode default.

• Full strength Output Driver added on DIC (page 21, 54).

(A6, A1) = (1, 1): Reserved → Full Strength Output Driver.

• Note (5) added on Self-Refresh Entry Timing (page 48).

• Explanation for OCD Impedance Adjustment modified (page 54).

• I

/ I

table added (page 55).

OH OL

− Rev1.0 (Aug. 20 ‘2004)

• “-45” version dropped.

• Some notes in the page 8 moved to page 7 (page 7, 8).

• Note 2 changed as below (page 7).

Before: These parameters depend on the output loading. The specified values are obtained with the

output open

After: These parameters define the current between V_DDand V_SS

.

• Corrected TYPO (page 2, 3, 14, 15, 17).

• Package weight (0.23g) added (page 57).

Rev 1.0

2004-08-20 58/59

TC59LM914/06AMG-37,-50

RESTRICTIONS ON PRODUCT USE

030619EBA

•

The information contained herein is subject to change without notice.

The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of

TOSHIBA or others.

•

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical

stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of

safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of

such TOSHIBA products could cause loss of human life, bodily injury or damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as

set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and

conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability

Handbook” etc..

•

The TOSHIBA products listed in this document are intended for usage in general electronics applications

(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,

etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires

extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or

bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or

spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,

medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this

document shall be made at the customer’s own risk.

•

The products described in this document are subject to the foreign exchange and foreign trade laws.

TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced

and sold, under any law and regulations.

Rev 1.0

2004-08-20 59/59


型号：	TC59LM914AMG-50
厂家：	TOSHIBA
描述：	MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC MOS数字集成电路硅单片
文件：	总59页 (文件大小：700K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC59LM914AMG-50 [TOSHIBA]

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