TC59SM708ASL-75 [TOSHIBA]
IC 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54, 0.400 INCH, 0.40 MM PITCH. PLASTIC, TSOP2-54, Dynamic RAM;
| 型号： | TC59SM708ASL-75 |
| 厂家： | 
TOSHIBA |
| 描述： | IC 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54, 0.400 INCH, 0.40 MM PITCH. PLASTIC, TSOP2-54, Dynamic RAM 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总49页 (文件大小：2425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC59SM716/08/04AS/ASL-70,-75,-80
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
2,097,152-WORDS × 4 BANKS × 16-BITS SYNCHRONOUS DYNAMIC RAM
4,194,304-WORDS × 4 BANKS × 8-BITS SYNCHRONOUS DYNAMIC RAM
8,388,608-WORDS × 4 BANKS × 4-BITS SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
TC59SM716AS/ASL is a CMOS synchronous dynamic random access memory organized as 2,097,152-words × 4
banks × 16 bits and TC59SM708AS/ASL is organized as 4,194,304 words × 4 banks × 8 bits and
TC59SM704AS/ASL is organized as 8,388,608 words × 4 banks × 4 bits. Fully synchronous operations are
referenced to the positive edges of clock input and can transfer data up to 143M words per second. These devices
are controlled by commands setting. Each bank are kept active so that DRAM core sense amplifiers can be used as
a cache. The refresh functions, either Auto Refresh or Self Refresh are easy to use. By having a programmable
Mode Register, the system can choose the most suitable modes which will maximize its performance. These devices
are ideal for main memory in applications such as work-stations.
FEATURES
TC59SM716/M708/M704
PARAMETER
-70
-75
-80
8 ns
t
t
t
t
I
I
I
Clock Cycle Time (min)
7 ns
7.5 ns
45 ns
5.4 ns
65 ns
75 mA
95 mA
2 mA
CK
Active to Precharge Command Period (min)
Access Time from CLK (max)
40 ns
5.4 ns
56 ns
80 mA
100 mA
2 mA
48 ns
6 ns
RAS
AC
Ref/Active to Ref/Active Command Period (min)
Operation Current (max) (Single bank)
Burst Operation Current (max)
68 ns
70 mA
90 mA
2 mA
RC
CC1
CC4
CC6
Self-Refresh Current (max)
•
•
•
•
•
Single power supply of 3.3 V 0.3 V
Up to 143 MHz clock frequency
Synchronous operations: All signals referenced to the positive edges of clock
Architecture:
Pipeline
Organization
TC59SM716AS/ASL:
TC59SM708AS/ASL:
TC59SM704AS/ASL:
2,097,152 words × 4 banks × 16 bits
4,194,304 words × 4 banks × 8 bits
8,388,608 words × 4 banks × 4 bits
•
•
•
•
•
•
•
•
•
•
Programmable Mode register
Auto Refresh and Self Refresh
Burst Length:
1, 2, 4, 8, Full page
2, 3
CAS Latency:
Single Write Mode
Burst Stop Function
Byte Data Controlled by L-DQM, U-DQM (TC59SM716)
4K Refresh cycles/64 ms
Interface:
LVTTL
Package
TC59SM716AS/ASL:
TC59SM708AS/ASL:
TC59SM704AS/ASL:
TSOPII54-P-400-0.4F
TSOPII54-P-400-0.4F
TSOPII54-P-400-0.4F
000707EBA2
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
2001-06-11 1/49
TC59SM716/08/04AS/ASL-70,-75,-80
PIN NAMES
PIN ASSIGNMENT (TOP VIEW)
A0~A11
Address
TC59SM716AS/ASL
TC59SM708AS/ASL
TC59SM704AS/ASL
BS0, BS1
Bank Select
DQ0~DQ3
(TC59SM704)
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
VCC
DQ0
VCCQ
NC
VCC
NC
1
2
3
4
5
6
7
8
9
54 VSS
53 NC
52 VSSQ
51 NC
VSS
VSS
DQ7 DQ15
DQ0~DQ7
(TC59SM708)
VCCQ
NC
VSSQ
NC
VSSQ
DQ14
Data Input/Output
DQ1
VSSQ
NC
DQ0
VSSQ
NC
50 DQ3 DQ6 DQ13
49 VCCQ
48 NC
47 NC
46 VSSQ
45 NC
VCCQ
NC
VCCQ
DQ12
DQ0~DQ15
(TC59SM716)
DQ2
VCCQ
NC
NC
DQ5 DQ11
VCCQ
VSSQ
NC
VSSQ
DQ10
CS
Chip Select
NC 10
DQ1 11
VSSQ 12
NC 13
VCC 14
NC 15
DQ3
VSSQ
NC
44 DQ2 DQ4 DQ9
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Write Enable
43 VCCQ
42 NC
41 VSS
40 NC
VCCQ
NC
VSS
NC
VCCQ
DQ8
VSS
VCC
NC
LDQM
NC
16
17
18
19
39 DQM DQM UDQM
38 CLK CLK CLK
37 CKE CKE CKE
WE
CAS
RAS
CS
WE
CAS
RAS
CS
WE
CAS
RAS
CS
DQM
(TC59SM708/M704)
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
NC
A11
A9
A8
A7
A6
A5
A4
VSS
NC
A11
A9
A8
A7
A6
A5
A4
VSS
BS0
BS1
BS0
BS1
BS0 20
BS1 21
Output Disable/Write Mask
A10/AP A10/AP A10/AP 22
UDQM/LDQM
(TC59SM716)
A0
A1
A0
A1
A0 23
A1 24
A2 25
A3 26
VCC 27
A2
A2
CLK
CKE
Clock inputs
Clock enable
Power (+3.3 V)
Ground
A3
A3
VCC
VCC
V
V
CC
SS
Power (+3.3 V)
(for DQ buffer)
V
V
CCQ
SSQ
Ground
(for DQ buffer)
NC
No Connection
000707EBA2
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.
2001-06-11 2/49
TC59SM716/08/04AS/ASL-70,-75,-80
BLOCK DIAGRAM
CLK
CKE
CLOCK
BUFFER
CONTROL
SIGNAL
GENERATOR
CS
RAS
CAS
WE
COMMAND
DECODER
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A10
MODE
SENSE AMPLIFIER
SENSE AMPLIFIER
REGISTER
ADDRESS
BUFFER
A0~A9
A11
BS0
DATA CONTROL
CIRCUIT
BS1
DQ0~DQn
DQM
DQ BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The TC59SM704AS/ASL configuration is 4096 × 2048 × 4 of cell array with the DQ pins numbered DQ0~DQ3.
The TC59SM708AS/ASL configuration is 4096 × 1024 × 8 of cell array with the DQ pins numbered DQ0~DQ7.
The TC59SM716AS/ASL configuration is 4096 × 512 × 16 of cell array with the DQ pins numbered DQ0~DQ15.
2001-06-11 3/49
TC59SM716/08/04AS/ASL-70,-75,-80
ABSOLUTE MAXIMUM RATINGS
SYMBOL
, V
PARAMETER
Input, Output Voltage
RATING
UNIT
NOTES
V
V
−0.3~V
+ 0.3
V
V
1
1
1
1
1
1
1
IN OUT
CC
, V
CC CCQ
Power Supply Voltage
Operating Temperature
Storage Temperature
−0.3~4.6
T
T
T
0~70
−55~150
260
°C
°C
°C
W
opr
stg
Soldering Temperature (10s)
Power Dissipation
solder
P
1
D
I
Short-Circuit Output Current
50
mA
OUT
RECOMMENDED DC OPERATING CONDITIONS (Ta = 0°~70°C)
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP.
MAX
UNIT
NOTES
V
V
V
V
3
3
3.3
3.3
3.6
3.6
V
V
V
V
2
2
2
2
CC
Power Supply Voltage (for DQ Buffer)
LVTTL Input High Voltage
CCQ
IH
2
V
+ 0.3
CC
LVTTL Input Low Voltage
−0.3
0.8
IL
Note: V (max) = V /V
+ 1.2 V for pulse width ≤ 5 ns
− 1.2 V for pulse width ≤ 5 ns
IH
CC CCQ
VIL (min) = V /V
SS SSQ
V
must be less than or equal to V
.
CCQ
CC
CAPACITANCE (V = 3.3 V, f = 1 MHz, Ta = 25°C)
CC
SYMBOL
PARAMETER
MIN
MAX
UNIT
pF
Input Capacitance
4
(A0~A11, BS0, BS1, CS , RAS , CAS , WE , DQM*, CKE)
C
C
I
Input Capacitance (CLK)
5
pF
pF
Input/Output Capacitance
6.5
O
Note: These parameters are periodically sampled and not 100% tested.
LDQM, UDQM (TC59SM716)
*
2001-06-11 4/49
TC59SM716/08/04AS/ASL-70,-75,-80
DC CHARACTERISTICS (V = 3.3 V 0.3 V, Ta = 0°~70°C)
CC
-70
-75
-80
PARAMETER
SYMBOL
UNITS NOTES
MIN MAX MIN MAX MIN MAX
OPERATING CURRENT
= min, t = min
Active Precharge command cycling
without burst operation
t
CK
RC
1 bank operation
I
80
75
70
3
CC1
STANDBY CURRENT
CKE = V
CKE = V
I
I
I
I
I
I
40
1
35
1
30
1
3
3
IH
IL
CC2
t
= min, CS = V ,
CK
IH
V
= V (min) / V (max),
IH IL
IH/L
CC2P
CC2S
CC2PS
CC3
Bank: Inactive state
(Power Down mode)
STANDBY CURRENT
CLK = V , CS = V
CKE = V
CKE = V
10
1
10
1
10
1
IH
,
IH
IL
V
= V (min) / V (max),
IH/L
IH IL
IL
Bank: Inactive state
(Power Down mode)
mA
CKE = V
CKE = V
60
10
55
10
50
10
IH
NO OPERATING CURRENT
= min, CS = V (min),
t
CK
IH
Bank: Active state (4 banks)
IL
CC3P
(Power Down mode)
BURST OPERATING CURRENT
t
= min
I
I
100
170
95
90
3, 4
3
CK
CC4
CC5
Read/Write command cycling
AUTO REFRESH CURRENT
t
= min, t
= min
RC
160
150
CK
Auto Refresh command cycling
Standard Products
(AFT)
2
2
2
SELF REFRESH CURRENT
Self Refresh mode
CKE = 0.2 V
I
CC6
Low Power Version
(AFTL)
800
800
800
µA
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
INPUT LEAKAGE CURRENT
(0 V ≤ V ≤ V , all other pins not under test = 0 V)
I (L)
−5
−5
5
5
µA
µA
I
IN
CC
OUTPUT LEAKAGE CURRENT
(Output disable, 0 V ≤ V ≤ V
I (L)
O
)
CCQ
OUT
LVTTL OUTPUT H LEVEL VOLTAGE (I
= −2 mA)
= 2 mA)
V
2.4
V
V
OUT
OH
LVTTL OUTPUT L LEVEL VOLTAGE (I
V
0.4
OUT
OL
2001-06-11 5/49
TC59SM716/08/04AS/ASL-70,-75,-80
AC CHARACTERISTICS AND OPERATING CONDITIONS
(V = 3.3 V 0.3 V, Ta = 0°~70°C) (Notes: 5, 6, 7)
CC
-70
-75
-80
SYMBOL
PARAMETER
UNITS NOTES
MIN
56
40
15
1
MAX
MIN
65
45
20
1
MAX
MIN
68
48
20
1
MAX
t
t
t
t
t
t
Ref/Active to Ref/Active Command Period
Active to Precharge Command Period
Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b) Command Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
RC
ns
100000
100000
100000
RAS
RCD
CCD
RP
8
Cycle
15
15
7.5
7
20
15
10
7.5
10
7.5
2.5
2.5
20
20
10
8
RRD
CL* = 2
Write-Recovery Time
t
WR
CK
CL* = 3
CL* = 2
7.5
7
1000
1000
1000
1000
10
8
1000
1000
t
CLK Cycle Time
CL* = 3
t
t
CLK High-Level Width
CLK Low-Level Width
2.5
2.5
3
CH
CL
3
CL* = 2
Access Time from CLK
5.4
5.4
6
3
6
t
AC
CL* = 3
5.4
6
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output Data Hold Time
Output Data High-Impedance Time
Output Data Low-Impedance Time
Power-Down Mode Entry Time
Transition Time of CLK (rise and fall)
Data-In Set-up Time
3
3
OH
HZ
ns
3
7
3
7.5
3
8
7
0
0
0
LZ
0
7
0
7.5
10
0
8
SB
0.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
10
0.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
0.5
2
10
t
DS
Data-In Hold Time
1
DH
Address Set-up Time
2
AS
Address Hold Time
1
AH
CKE Set-up Time
2
CKS
CKH
CMS
CMH
REF
RSC
CKE Hold Time
1
Command Set-up Time
Command Hold Time
2
1
Refresh Time
64
64
16
64
ms
ns
Mode Register Set Cycle Time
14
15
8
*
CL means CAS latency.
2001-06-11 6/49
TC59SM716/08/04AS/ASL-70,-75,-80
NOTES:
(1)
Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent
damage to the device.
(2)
(3)
All voltages are referenced to V
.
SS
These parameters depend on the cycle rate and these values are measured at a cycle rate with the
minimum values of t and t . Input signals are changed one time during t
.
CK RC CK
(4)
(5)
(6)
These parameters depend on the output loading. Specified values are obtained with the output open.
Power-up sequence is described in Note 9.
AC TEST CONDITIONS
Output Reference Level
Output Load
1.4 V, 1.4 V
See diagram B below
2.4 V, 0.4 V
2 ns
Input Signal Levels
Transition Time (rise and fall) of Input Signals
Input Reference Level
1.4 V
3.3 V
1.4 V
1.2 kΩ
50 Ω
Z = 50 Ω
Output
Output
50 pF
870 Ω
50 pF
AC test load (A)
AC test load (B)
(7)
t
HZ
defines the time at which the outputs achieve the open circuit condition and is not referenced to
output voltage levels.
2001-06-11 7/49
TC59SM716/08/04AS/ASL-70,-75,-80
(8)
(9)
These parameters account for the number of clock cycles and depend on the operating frequency of the
clock, as follows:
the number of clock cycles = specified value of timing / clock period
(count fractions as a whole number)
Power-up Sequence
Power-up must be performed in the following sequence.
1)
Power must be applied to V
and V (simultaneously) while all input signals are held in the
CCQ
CC
“NOP” state. The CLK signals must be started at the same time.
2)
After power-up a pause of at least 200 µs is required. It is required that DQM and CKE signals
must be held “High” (V
CC
levels) to ensure that the DQ output is in High-impedance state.
3)
4)
5)
All banks must be precharged.
The Mode Register Set command must be asserted to initialize the Mode Register.
A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of
the device.
The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles.
AC Latency Characteristics
(10)
CKE to clock disable (CKE Latency)
1
DQM to output in High-Z (Read DQM Latency)
DQM to input data delay (Write DQM Latency)
Write command to input data (Write Data Latency)
CS to Command input ( CS Latency)
2
0
0
0
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
2
Precharge to DQ Hi-Z Lead time
Cycle
3
1
2
Precharge to Last Valid data out
2
Burst Stop Command to DQ Hi-Z Lead time
Burst Stop Command to Last Valid data out
Read with Autoprecharge Command to Active/Ref Command
Write with Autoprecharge Command to Active/Ref Command
3
1
2
BL + t
BL + t
BL + t
BL + t
RP
RP
RP
RP
Cycle + ns
2001-06-11 8/49
TC59SM716/08/04AS/ASL-70,-75,-80
TIMING DIAGRAMS
Command Input Timing
t
t
t
CK
CL
CH
t
V
IH
CLK
V
IL
t
t
t
t
t
t
t
t
t
t
CMS
CMS CMH
CMH
CS
t
CMS CMH
RAS
CAS
t
CMS CMH
t
CMS CMH
WE
t
t
AH
AS
A0~A11
BS0, BS1
t
t
t
t
t
t
CKH
CKS
CKH
CKS CKH
CKS
CKE
2001-06-11 9/49
TC59SM716/08/04AS/ASL-70,-75,-80
Read Timing
Read CAS latency
CLK
CS
RAS
CAS
WE
A0~A11
BS0, BS1
t
t
t
HZ
AC
AC
t
t
t
OH
LZ
OH
Output
data valid
Output
data valid
DQ
Read command
Burst length
2001-06-11 10/49
TC59SM716/08/04AS/ASL-70,-75,-80
Control Timing of Input Data (TC59SM708/M704)
(Word Mask)
CLK
t
t
t
t
CMS
CMH
CMS
CMH
DQM
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DQ0~DQ7
(DQ0~DQ3)*
Input
data valid
Input
data valid
Input
data valid
Input
data valid
(Clock Mask)
CLK
t
t
t
t
CKS
CKH
CKS
CKH
CKE
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DQ0~DQ7
(DQ0~DQ3)*
Input
data valid
Input
data valid
Input
data valid
Input
data valid
Control Timing of Output Data (TC59SM708/M704)
(Output Enable)
CLK
t
t
t
t
CMS
CMH
CMS
CMH
DQM
t
t
t
t
t
AC
AC
HZ
AC
AC
t
t
t
t
t
OH
OH
OH
LZ
OH
DQ0~DQ7
(DQ0~DQ3)*
Output
data valid
Output
data valid
Output
data valid
Open
(Clock Mask)
CLK
t
t
t
t
CKS
CKH
CKS
CKH
CKE
t
t
t
t
AC
AC
AC
AC
t
t
t
t
OH
OH
OH
OH
DQ0~DQ7
(DQ0~DQ3)*
Output
data valid
Output
data valid
Output data valid
*: TC59SM704
2001-06-11 11/49
TC59SM716/08/04AS/ASL-70,-75,-80
Control Timing of Input Data (TC59SM716)
(Word Mask)
CLK
t
t
t
t
CMS
CMH
CMS
CMH
LDQM
UDQM
t
t
t
t
CMS
CMH
CMS
CMH
t
t
t
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
Input
data valid
Input
data valid
Input
data valid
Input
data valid
DQ0~DQ7
DQ8~DQ15
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
Input
data valid
Input
data valid
Input
data valid
Input
data valid
(Clock Mask)
CLK
t
t
t
t
CKS
CKH
CKS
CKH
CKE
DQ0~DQ7
DQ8~DQ15
t
t
t
t
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
Input
data valid
Input
data valid
Input
data valid
Input
data valid
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
Input
data valid
Input
data valid
Input
data valid
Input
data valid
2001-06-11 12/49
TC59SM716/08/04AS/ASL-70,-75,-80
Control Timing of Output Data (TC59SM716)
(Output Enable)
CLK
t
t
t
t
t
t
CMH
CMS
CMH
CMH
CMS
LDQM
UDQM
t
t
CMS
CMS
CMH
t
t
t
t
t
AC
AC
HZ
AC
AC
t
t
t
t
t
t
OH
OH
OH
LZ
OH
Output
data valid
Output
data valid
Output
data valid
DQ0~DQ7
DQ8~DQ15
Open
t
t
t
t
t
AC
AC
AC
HZ
AC
t
t
t
t
LZ
OH
OH
OH
OH
Output
data valid
Output
data valid
Output
data valid
Open
(Clock Mask)
CLK
t
t
t
t
CKH
CKS
CKH
CKS
CKE
DQ0~DQ7
DQ8~DQ15
t
t
t
t
AC
AC
AC
AC
t
t
t
t
t
t
OH
OH
OH
OH
Output
data valid
Output
data valid
Output data valid
Output data valid
t
t
t
t
AC
AC
AC
AC
t
t
OH
OH
OH
OH
Output
data valid
Output
data valid
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TC59SM716/08/04AS/ASL-70,-75,-80
Mode Register Set Cycle
t
RSC
CLK
t
t
t
t
t
CMS CMH
CS
RAS
CAS
WE
t
CMS CMH
t
CMS CMH
t
CMS CMH
t
t
AH
AS
A0~A11
BS0, BS1
Set Register
data
Next command
Burst Length
A0
A2
0
A1
0
A0
0
Sequential
Interleaved
Burst Length
1
2
4
8
1
2
4
8
A1
A2
0
0
1
0
1
0
0
1
1
A3 Addressing Mode
A4
1
0
0
Reserved
Full Page
1
0
1
Reserved
1
1
0
CAS Latency
A5
A6
1
1
1
A3
Addressing Mode
0
1
Sequential
Interleaved
A7
0
(Test Mode)
Reserved
A8
0
A6
A5
A4
CAS Latency
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Reserved
A9
Write Mode
Reserved
2
3
A10
A11
BS0
BS1
0
0
0
0
Reserved
Reserved
A9
Single Write Mode
0
1
Burst read and Burst write
Burst read and Single write
2001-06-11 14/49
TC59SM716/08/04AS/ASL-70,-75,-80
OPERATING TIMING EXAMPLE
Figure 1. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RC
t
RC
t
t
RC
RC
RAS
t
t
t
t
RP
RAS
RP
RAS
t
t
t
RAS
RAS
RP
CAS
WE
BS0
BS1
t
t
t
t
RCD
RCD
RCD
RCD
A10
RAa
RAa
RBb
RBb
RAc
RAc
RBd
RAe
RAe
A0~A9, A11
DQM
CAw
CBx
CAy
RBd
CBz
CKE
t
t
t
t
AC
AC
AC
AC
DQ
aw0 aw1 aw2 aw3
bx0 bx1 bx2 bx3
cy0 cy1 cy2 cy3
t
t
t
t
RRD
RRD
RRD
RRD
Bank#0
Bank#1
Bank#2
Bank#3
Active
Read
Precharge
Read
Active
Read
Precharge
Precharge
Read
Active
Active
Active
Idle
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 2. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RC
t
RC
t
t
RC
RC
RAS
t
t
t
t
RP
RAS
RP
RAS
t
t
t
RAS
RAS
RP
CAS
WE
BS0
BS1
t
t
t
t
RCD
RCD
RCD
RCD
A10
RAa
RAa
RBb
RAc
RBd
RAe
A0~A9, A11
DQM
CAw RBb
CBx
RAc
CAy
RBd
CBz
RAe
CKE
t
t
t
AC
t
AC
AC
AC
DQ
aw0 aw1 aw2 aw3
bx0 bx1 bx2 bx3
cy0 cy1 cy2 cy3
dz0
t
t
t
t
RRD
RRD
RRD
RRD
Bank#0
Bank#1
Bank#2
Bank#3
Active
Read
AP*
Active
AP*
Active
Active
Read
AP* Read
Active
Read
Idle
*: AP shows internal precharge start timing.
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 3. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RC
t
RC
t
RC
RAS
t
t
t
RAS
RAS
t
RP
t
t
RP
RP
RAS
CAS
WE
BS0
BS1
t
t
t
RCD
RCD
RCD
A10
RAa
RAa
RBb
RBb
RAc
RAc
A0~A9, A11
DQM
CAx
CBy
CAz
CKE
t
AC
t
t
AC
AC
DQ
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1
by4 by5 by6 by7
cz0
t
t
RRD
RRD
Bank#0
Bank#1
Bank#2
Bank#3
Active
Read
Precharge
Precharge
Active
Read
Active
Read
Precharge
Idle
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 4. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RC
t
RC
RAS
t
t
t
RAS
RAS
RP
t
t
RP
RAS
CAS
WE
BS0
BS1
t
t
t
RCD
RCD
RCD
A10
RAa
RAa
RBb
RBb
RAc
RAc
A0~A9, A11
DQM
CAx
CBy
CAz
CKE
t
t
t
AC
AC
AC
DQ
ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1
by4 by5 by6
cz0
t
t
RRD
RRD
Bank#0
Bank#1
Bank#2
Bank#3
Active
Read
AP*
Active
Read
Active
Read
AP*
Idle
*: AP shows the internal precharge start timing.
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 5. Interleaved Bank Write (Burst Length = 8)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RC
RAS
t
t
RP
RAS
t
t
RP
RAS
CAS
WE
t
t
t
RCD
RCD
RCD
BS0
BS1
A10
RAa
RAa
RBb
RBb
RAc
RAc
A0~A9, A11
DQM
CAx
CBy
CAz
CKE
DQ
ax0 ax1
ax4 ax5 ax6 ax7 by0 by1 by2 by3
by4 by5 by6 by7 cz0 cz1
cz2
t
t
RRD
RRD
Bank#0
Bank#1
Bank#2
Bank#3
Active
Write
Precharge
Write
Active
Write
Precharge
Active
Idle
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 6. Interleaved Bank Write (Burst Length = 8, Auto Precharge)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RC
RAS
t
t
t
RAS
RAS
RP
t
t
RP
RAS
CAS
WE
BS0
BS1
t
t
t
RCD
RCD
RCD
A10
RAa
RAa
RBb
RBb
RAb
RAc
A0~A9, A11
DQM
CAx
CBy
CAz
CKE
DQ
ax0 ax1
ax4 ax5 ax6 ax7 by0 by1 by2 by3
by4 by5 by6 by7 cz0 cz1
cz2
t
t
RRD
RRD
Bank#0
Bank#1
Bank#2
Bank#3
Active
Write
AP*
Active
Write
Active
Write
AP*
Idle
*: AP shows the internal precharge start timing.
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 7. Page Mode Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
t
t
CCD
CCD
CCD
t
t
RP
RAS
t
t
RP
RAS
RAS
CAS
WE
BS0
BS1
t
t
RCD
RCD
A10
RAa
RAa
RBb
A0~A9, A11
DQM
CKE
CAl RBb
CBx
CAy
CAm
CBz
t
t
t
t
t
AC
AC
AC
AC
AC
DQ
al0 al1 al2 al3 bx0 bx1 Ay0 Ay1 Ay2 am0 am1 am2 bz0 bz1 bz2 bz3
t
RRD
Bank#0
Bank#1
Bank#2
Bank#3
Active
Read
Read
Read
Precharge
Active
Read
Read
AP*
Idle
*: AP shows the internal precharge start timing.
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 8. Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
t
RP
RAS
RAS
CAS
WE
BS0
BS1
t
RCD
A10
RAa
RAa
A0~A9, A11
DQM
CKE
CAx
CAy
t
AC
t
WR
DQ
ax0 ax1 ax2 ax3 ax4 ax5
ay0 ay1 ay2 ay3 ay4
Q
Q
Q
Q
Q
Q
D
D
D
D
D
Bank#0
Bank#1
Bank#2
Bank#3
Active
Read
Write
Precharge
Idle
Note): See Figure 17, 20
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 9. Auto Precharge Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RC
t
RC
RAS
t
t
t
t
RP
RAS
RP
RAS
CAS
WE
BS0
BS1
t
t
RCD
RCD
A10
RAa
RAa
RAb
RAb
A0~A9, A11
DQM
CKE
CAw
CAx
t
t
AC
AC
DQ
aw0 aw1 aw2 aw3
bx0
bx1
bx2 bx3
Bank#0
Bank#1
Bank#2
Bank#3
Active
Read
AP*
Active
Read
AP*
Idle
*:
AP shows the internal precharge start timing.
Note): See Figure 15
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 10. Auto Precharge Write (Burst Length = 4)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RC
t
RC
RAS
t
t
t
t
RP
RAS
RP
RAS
CAS
WE
BS0
BS1
t
t
RCD
RCD
A10
RAa
RAa
RAb
RAb
RAc
RAc
A0~A9, A11
DQM
CKE
CAw
CAx
DQ
aw0 aw1 aw2 aw3
bx0
bx1 bx2 bx3
Bank#0
Bank#1
Bank#2
Bank#3
Active
Write
AP*
Active
Write
AP*
Active
Idle
*:
AP shows the internal precharge start timing.
Note): See Figure 16
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 11. Auto Refresh Cycle
0
1
2
3
4
5
6
7
t
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
t
RC
RP
RC
RAS
CAS
WE
BS0, BS1
A10
A0~A9, A11
DQM
CKE
DQ
All Banks Precharge Auto Refresh
Auto Refresh (Arbitrary Cycle)
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 12. Self Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RP
RAS
CAS
WE
BS0, BS1
A10
A0~A9, A11
DQM
t
t
t
CKS
SB
CKS
CKE
t
CKS
DQ
t
RC
No Operation Cycle
All Banks Precharge
Self Refresh Entry
Self Refresh Exit
Arbitrary Cycle
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 13. Power Down Mode
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
WE
BS
A10
RAa
RAa
RAa
A0~A9, A11
DQM
CKE
CAa
RAa
CAx
t
t
SB
SB
t
t
t
t
CKS
CKS
CKS
CKS
DQ
ax0 ax1
ax2
ax3
Active
NOP
NOP Active
Precharge
&
Power Down Mode Entry Power Down Mode Exit
Power Down Mode Exit
Power Down Mode
Entry
Note): The Power Down mode is invoked by asserting CKE “low”.
All Input/Output buffers (except the CKE buffer) are turned off in Power Down mode.
When CKE goes high, the No-operation command input must be at next CLK rising edge and CKE should be set high at least
1CLK + t at Power Down Mode Exit.
CKS
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TC59SM716/08/04AS/ASL-70,-75,-80
Figure 14. Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
t
RCD
WE
BS0
BS1
A10
RBa
RBa
A0~A9, A11
DQM
CKE
CBv
CBw
CBx CBy CBz
t
t
AC
AC
DQ
av0 av1 av2 av3
aw0
ax0 ay0
az0 az1 az2 az3
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
Bank#0
Bank#1
Bank#2
Bank#3
Active
Read
Single Write Read
Idle
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TC59SM716/08/04AS/ASL-70,-75,-80
PIN FUNCTIONS
CLOCK INPUT: CLK
The CLK input is used as the reference for SDRAM operations. Operations are synchronized to the positive
edges of CLK.
CLOCK ENABLE: CKE
The CKE input is used to suspend the internal CLK. When the CKE signal is asserted “low”, the internal
CLK is suspended and output data is held intact while CKE is asserted “low”. When the device is not running a
Burst cycle, the CKE input controls the entry to the Power Down and Self Refresh modes. When the Self
Refresh command is issued, the device must be in the idle state.
BANK SELECT: BS0, BS1
The TC59SM716AS/ASL, TC59SM708AS/ASL and the TC59SM704AS/ASL are organized as four-bank
memory cell arrays. The BS0, BS1 inputs are latched at the time of assertion of the operation commands and
selects the bank to be used for the operation.
BS0
BS1
0
1
0
1
0
0
1
1
Bank#0
Bank#1
Bank#2
Bank#3
ADDRESS INPUTS: A0~A11
The A0~A11 inputs are address to access the memory cell array, as following table.
Row Address
Column Address
TC59SM716AS/ASL
TC59SM708AS/ASL
TC59SM704AS/ASL
A0~A11
A0~A11
A0~A11
A0~A8
A0~A9
A0~A9, A11
The row address bits are latched at the Bank Activate command and column address bits are latched on the
Read or Write command. Also, the A0~A11 inputs are used to set the data in the Mode register in a Mode
Register Set cycle.
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TC59SM716/08/04AS/ASL-70,-75,-80
CS
CHIP SELECT:
The CS input controls the latching of the commands on the positive edges of CLK when CS is asserted
“low”. No commands are latched as long as CS is held “high”.
RAS
ROW ADDRESS STROBE:
The RAS input defines the operation commands in conjunction with the CAS and WE inputs, and is
latched at the positive edges of CLK. When RAS and CS are asserted “low” and CAS is asserted “high”,
either the Bank Activate command or the Precharge command is selected by the WE signal. When WE is
asserted “high”, the Bank Activate command is selected and the bank designated by BS0, BS1 are turned on so
that it is in the active state. When WE is asserted “low”, the Precharge command is selected and the bank
designated by BS0, BS1 are switched to the idle state after Precharge operation.
CAS
COLUMN ADDRESS STROBE:
The CAS input defines the operation commands in conjunction with the RAS and WE inputs, and is
latched at the positive edges of CLK. When RAS is held “high” and CS is asserted “low”, column access is
started by asserting CAS “low”. Then, the Read or Write command is selected by asserting WE “low” or
“high”.
WRITE ENABLE:
WE
The WE input defines the operation commands in conjunction with the RAS and CAS inputs, and is
latched at the positive edges of CLK. The WE input is used to select the Bank Activate or Precharge command
and Read or Write command.
DATA INPUT/OUTPUT MASK: DQM or L-DQM and U-DQM
The DQM input enables output in a Read cycle and functions as the input data mask in a Write cycle. When
DQM is asserted “high” at the positive edges of CLK, output data is disabled after two clock cycles during a
Read cycle, and input data is masked at the same clock cycle during a Write cycle.
In the case of the TC59SM716AS/ASL, the LDQM and UDQM inputs function as byte data control. The
LDQM input can control DQ0~DQ7 in a Read or Write cycle and the UDQM can control DQ8~DQ15 in a Read
or Write cycle.
DATA INPUT/OUTPUT: DQ0~DQ15
The DQ0~DQ15 input and output data are synchronized with the positive edges of CLK. In the case of
TC59SM708AS/ASL and TC59SM704AS/ASL, these pins are DQ0~DQ7 and DQ0~DQ3 respectively.
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TC59SM716/08/04AS/ASL-70,-75,-80
Operation Mode
Table 1 shows the truth table for the operation commands.
Table 1. Truth Table (Note (1) and (2) )
BS0,
BS1
A11,
A9~A0
(5)
Command
Bank Activate
Device State CKE
(3)
CKE DQM
A10
CS
RAS
CAS
WE
n-1
n
Idle
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
V
X
X
X
X
X
V
L
V
X
X
V
V
V
V
V
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
X
L
L
H
H
H
L
H
L
Bank Precharge
Precharge All
Any
Any
Active
Active
Active
Active
Idle
H
L
L
L
(3)
(3)
(3)
(3)
Write
H
H
H
H
L
L
Write with Auto Precharge
Read
H
L
L
L
L
H
H
L
Read with Auto Precharge
Mode Register Set
No-Operation
H
V
X
X
X
X
X
L
L
Any
H
H
X
L
H
H
X
L
H
L
(4)
Burst stop
Active
Any
Device Deselect
Auto-Refresh
X
H
H
X
X
X
X
X
X
X
X
X
X
Idle
Self-Refresh Entry
Idle
L
L
X
H
X
X
H
X
X
H
X
X
X
H
X
X
H
X
X
H
X
X
Idle
(Self Refresh)
Self-Refresh Exit
L
H
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Clock Suspend Mode Entry
Power Down Mode Entry
Clock Suspend Mode Exit
Power Down Mode Exit
Active
(6)
Idle/Active
L
Active
H
H
Any
(Power Down)
L
Data Write/Output Enable
Data Write/Output Disable
Active
Active
H
H
X
X
L
X
X
X
X
X
X
H
Note 1. V = Valid, X = Don’t Care, L = Low level, H = High level
2. CKE signal is input level when commands are issued.
n
CKE
signal is input level one clock cycle before the commands are issued.
n-1
3. These are state designated by the BS0, BS1 signals.
4. Device state is Full Page Burst operation.
5. LDQM, UDQM (TC59SM716AS/ASL)
6. Power Down Mode can not entry in the burst cycle.
When this command assert in the burst cycle, device state is clock suspend mode.
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TC59SM716/08/04AS/ASL-70,-75,-80
1. Command Function
1-1
Bank Activate command
( RAS = L, CAS = H, WE = H, BS = Bank, A0~A11 = Row Address)
The Bank Activate command activates the bank designated by the BS (Bank Select) signal.
Row addresses are latched on A0~A11 when this command is issued and the cell data is read out to the
sense amplifiers. The maximum time that each bank can be held in the active state is specified as t
(max).
RAS
1-2
1-3
1-4
Bank Precharge command
( RAS = L, CAS = H, WE = L, BS = Bank, A10 = L, A0~A9, A11 = Don’t care)
The Bank Precharge command precharges the bank designated by BS. The precharged bank is
switched from the active state to the idle state.
Precharge All command
( RAS = L, CAS = H, WE = L, BS = Don’t care, A10 = H, A0~A9, A11 = Don’t care)
The Precharge All command precharges all banks simultaneously. All banks are then switched to the
idle state.
Write command
( RAS = H, CAS = L, WE = L, BS = Bank, A10 = L, A0~A9, A11 = Column Address)
The Write command performs a Write operation to the bank designated by BS. The write data is
latched at the positive edges of CLK. The length of the write data (Burst Length) and column access
sequence (Addressing Mode) must be programmed in the Mode Resister at power-up prior to the Write
operation.
The A11 input is “Don’t care” on the TC59SM708AS/ASL and the A9 and A11 inputs are “Don’t care” on
the TC59SM716AS/ASL.
1-5
1-6
Write with Auto Precharge command
( RAS = H, CAS = L, WE = L, BS = Bank, A10 = H, A0~A9, A11 = Column Address)
The Write with Auto Precharge command performs the Precharge operation automatically after the
Write operation. The internal precharge starts in the cycles immediately following the cycle in which the
last data is written independent of CAS Latency (Figure 16). This command must not be interrupted by
any other commands.
The A11 input is “Don’t care” at the TC59SM708AS/ASL and the A9 and A11 inputs are “Don’t care” on
the TC59SM716AS/ASL.
Read command
( RAS = H, CAS = L, WE = H, BS = Bank, A10 = L, A0~A9, A11 = Column Address)
The Read command performs a Read operation to the bank designated by BS. The read data is issued
sequentially synchronized to the positive edges of CLK. The length of read data (Burst Length),
Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be
programmed in the Mode Register at power-up prior to the Write operation.
The A11 input is “Don’t care” on the TC59SM708AS/ASL and the A9 and A11 inputs are “Don’t care” on
the TC59SM716AS/ASL.
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1-7
Read with Auto Precharge command
( RAS = H, CAS = L, WE = H, BS = Bank, A10 = H, A0~A9, A11 = Column Address)
The Read with Auto Precharge command automatically performs the Precharge operation after the
Read operation. When the CAS Latency = 3, the internal precharge starts two cycles before the last
data is output. When the CAS Latency = 2, the internal precharge starts one cycle before the last data
is output (Figure 15). This command must not be interrupted by any other command.
The A11 input is “Don’t care” on the TC59SM708AS/ASL and the A9 and A11 inputs are “Don’t care” on
the TC59SM716AS/ASL.
1-8
1-9
Mode Register Set command
( RAS = L, CAS = L, WE = L, BS, A0~A11 = Register Data)
The Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst
Length in the Mode Register. The default values in the Mode Register after power-up are undefined,
therefore this command must be issued during the power-up sequence. Also, this command can be issued
while all banks are in the idle state.
No-Operation command
( RAS = H, CAS = H, WE = H)
The No-Operation command simply performs no operation.
1-10 Burst stop command
( RAS = H, CAS = H, WE = L)
The Burst stop command is used to stop the burst operation. This command is valid during a Full Page
Burst operation. During other types of Burst operation, the command is illegal.
1-11 Device Deselect command
(CS = H)
The Device Deselect command disables the command decoder so that the RAS , CAS , WE and
Address inputs are ignored. This command is similar to the No-Operation command.
1-12 Auto Refresh command
( RAS = L, CAS = L, WE = H, CKE = H, BS, A0~A11 = Don’t care)
The Auto Refresh command is used to refresh the row address provided by the internal refresh counter.
The Refresh operation must be performed 4096 times within 64 ms. The next command can be issued
after t
RC
from the end of the Auto Refresh command. When the Auto Refresh command is issued, All
banks must be in the idle state. The Auto Refresh operation is equivalent to the CAS -before- RAS
operation in a conventional DRAM.
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1-13 Self Refresh Entry command
( RAS = L, CAS = L, WE = H, CKE = L, BS, A0~A11 = Don’t care)
The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self Refresh
mode, all input and output buffers (except the CKE buffer) are disabled and the Refresh operation is
automatically performed. Self Refresh mode is exited by taking CKE “high” (the Self Refresh Exit
command).
1-14 Self Refresh Exit command
(CKE = H, CS = H or CKE = H, RAS = H, CAS = H)
This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after
t
RC
from the end of this command.
1-15 Clock Suspend Mode Entry/Power Down Mode Entry command
(CKE = L)
The internal CLK is suspended for one cycle when this command is issued (when CKE is asserted
“low”). The device state is held intact while the CLK is suspended. On the other hand, when the device is
not operating the Burst cycle, this command performs entry into Power Down mode. All input and output
buffers (except the CKE buffer) are turned off in Power Down mode.
1-16 Clock Suspend Mode Exit/Power Down Mode Exit command
(CKE = H)
When the internal CLK has been suspended, operation of the internal CLK is resumed by providing
this command (asserting CKE “high”). When the device is in Power Down mode, the device exits this
mode and all disabled buffers are turned on to the active state. Any subsequent commands can be issued
after one clock cycle from the end of this command.
1-17 Data Write/Output Enable, Data Mask/Output Disable command
(DQM = L/H or LDQM, UDQM = L/H)
During a Write cycle, the DQM or LDQM, UDQM signal functions as Data Mask and can control every
word of the input data. During a Read cycle, the DQM or LDQM, UDQM signal functions as the control
of output buffers.
The LDQM signal controls DQ0~DQ7 and the UDQM signal controls DQ8~DQ15.
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2. Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is
issued after t from the Bank Activate command, the data is read out sequentially, synchronized to the
RCD
positive edges of CLK (a Burst Read operation). The initial read data becomes available after CAS Latency
from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. In
addition, the burst length of read data and Addressing Mode must be set. Each bank is held in the active state
unless the Precharge command is issued, so that the sense amplifiers can be used as secondary cache.
When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically
after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any
other commands. Also, when the Burst Length is 1 and t
(min), the timing from the RAS command to the
(min) must be satisfied by
RCD
start of the Auto Precharge operation is shorter than t
RAS
(min). In this case, t
RAS
extending t
RCD
(Figure 9, 15).
When the Precharge operation is performed on a bank during a Burst Read operation, the Burst operation is
terminated (Figure 20).
When the Burst Length is full-page, column data is repeatedly read out until the Burst Stop command or
Precharge command is issued.
3. Write Operation
Issuing the Write command after t
from the Bank Activate command, the input data is latched
RCD
sequentially, synchronizing with the positive edges of CLK after the Write command (Burst Write operation).
The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at
power-up.
When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically
after the Write cycle, then the bank is switched to the idle state. This command cannot be interrupted by any
other command for the entire burst data duration. Also, when the Burst Length is 1 and t
(min), the timing
RCD
(min). In this case,
from the RAS command to the start of the Auto Precharge operation is shorter than t
RAS
t
(min) must be satisfied by extending t (Figure 10, 16).
RCD
RAS
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is
terminated (Figure 20).
When the Burst Length is full-page, the input data is repeatedly latched until the Burst Stop command or the
Precharge command is issued.
When the Burst Read and Single Write mode is selected, the write burst length is 1 regardless of the read
burst length.
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4. Precharge
There are two commands which perform the Precharge operation: Bank Precharge and Precharge All. When
the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle
state. The Bank Precharge command can precharge one bank independently of the other bank and hold the
unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified
as t
RAS
(max). Therefore, each bank must be precharged within t (max) from the Bank Activate command.
RAS
The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the
active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed
only for the active bank and the precharged bank is then switched to the idle state.
5. Page Mode
The Read or Write command can be issued on any clock cycle.
Whenever a Read operation is to be interrupted by a Write command, the output data must be masked by
DQM to avoid I/O conflict. Also, when a Write operation is to be interrupted by a Read command, only the input
data before the Read command is enable and the input data after the Read command is disabled.
6. Burst Termination
When the Precharge command is issued for a bank in a Burst cycle, the Burst operation is terminated. When
the Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of
(CAS latency-1) from the Precharge command (Figure 20). When the Burst Write cycle is interrupted by the
Precharge command, the input circuit is reset at the same clock cycle at which the Precharge command is issued.
In this case, the DQM signal must be asserted “High” to prevent writing the invalid data to the cell array
(Figure 20).
When the Burst Stop command is issued for the bank in a Full-page Burst cycle, the Burst operation is
terminated. When the Burst Stop command is issued during Full-page Burst Read cycle, read operation is
disabled after clock cycle of (CAS latency-1) from the Burst Stop command. When the Burst Stop command is
issued during a Full-page Burst Write cycle, write operation is disabled at the same clock cycle at which the
Burst Stop command is issued. (Figure 19)
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7. Mode Register Operation
The Mode register designates the operation mode for the Read or Write cycle. This register is divided into
three fields; A Burst Length field to set the length of burst data, an Addressing Mode selected bits to designate
the column access sequence in a Burst cycle, and a CAS Latency field to set the access time in clock cycle.
The Mode Register is programmed by the Mode Register Set command when all banks are in the idle state.
The data to be set in the Mode Register is transferred using the A0~A11, BS0, BS1 address inputs. The initial
value of the Mode Register after power-up is undefined; therefore the Mode Register Set command must be
issued before proper operation.
•
Burst Length field (A2~A0)
This field specifies the data length for column access using the A2~A0 pins and sets the Burst Length to be
1, 2, 4, 8, words, or full-page.
A2
A1
A0
Burst Length
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
1 word
2 words
4 words
8 words
Full-Page
•
Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential mode. When the A3 bit is 0,
Sequential mode is selected. When the A3 bit is 1, Interleave mode is selected.
Both Addressing modes support burst length of 1, 2, 4 and 8 words. Additionally, Sequential mode supports
the full-page burst.
A3
Addressing Mode
0
1
Sequential
Interleave
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•
Addressing sequence of Sequential mode
A column access is performed by incrementing the column address input to the device. The address is
varied by the Burst Length as shown in Table 2.
Table 2. Addressing sequence for Sequential mode
DATA
Access Address
Burst Length
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
n
2 words (Address bits is A0)
not carried from A0 to A1
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
4 words (Address bits is A1, A0)
not carried from A1 to A2
8 words (Address bits is A2, A1, A0)
not carried from A2 to A3
•
Addressing sequence of Interleave mode
A column access is started from the input column address and is performed by inverting the address bits
in the sequence shown in Table 3.
Table 3. Addressing sequence for Interleave mode
DATA
Access Address
Burst Length
2 words
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
A8
A8
A8
A8
A8
A8
A8
A8
A7
A7
A7
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A6
A6
A6
A5
A5
A5
A5
A5
A5
A5
A5
A4
A4
A4
A4
A4
A4
A4
A4
A3
A3
A3
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A1
A1
A1
A0
A0
A0
A0
A0
A0
A0
A0
4 words
8 words
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Addressing sequence example (Burst Length = 8 and input address is 13.)
Interleave Mode
Sequential Mode
DATA
A8
0
A7
0
A6
0
A5
0
A4
0
A3
1
A2
1
A1
0
A0 ADD
ADD
13
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
1
0
1
0
1
0
1
0
13
12
15
14
9
13
0
0
0
0
0
1
1
0
13 + 1
13 + 2
13 + 3
13 + 4
13 + 5
13 + 6
13 + 7
14
calculated using
A2, A1 and A0 bits
0
0
0
0
0
1
1
1
15
8
0
0
0
0
0
1
1
1
not carry from
A2 to A3 bit.
0
0
0
0
0
1
0
0
9
0
0
0
0
0
1
0
0
8
10
11
12
0
0
0
0
0
1
0
1
11
10
0
0
0
0
0
1
0
1
Read Cycle CAS Latency = 3
0
1
2
3
4
5
6
7
8
9
10
11
Command
Address
Read
13
DQ0~DQ7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Data
Address
Interleave mode
Sequential mode
13
13
12
14
15
15
14
8
9
9
8
11
11
10
12
10
•
CAS Latency field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first data
read. The minimum values of CAS Latency depends on the frequency of CLK. The minimum value must be
set in this field.
A6
A5
A4
CAS Latency
0
0
1
1
0
1
2 clock
3 clock
•
•
•
Test mode entry bit (A7)
This bit is used to enter Test mode and must be set to 0 for normal operation.
Reserved bits (A8, A10, A11, BS0, BS1)
These bits are reserved for future operations. They must be set to 0 for normal operation.
Single Write mode (A9)
This bit is used to select the write mode. When the A9 bit is 0, Burst Read and Burst Write mode are
selected. When the A9 bit is 1, Burst Read and Single Write mode are selected.
A9
Write Mode
0
1
Burst Read and Burst Write
Burst Read and Single Write
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8. Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. Auto Refresh is
similar to the CAS -before- RAS refresh of conventional DRAMs and is performed by issuing the Auto Refresh
command while all banks are in the idle state. By repeating the Auto Refresh cycle, each bank refreshed
automatically. The Refresh operation must be performed 4096 times (rows) within 64 ms (Figure 11). The period
between the Auto Refresh command and the next command is specified by t
.
RC
Self Refresh mode is entered by issuing the Self Refresh command (CKE asserted “low”) while all banks are in
the idle state. The device is in Self Refresh mode for as long as CKE is held “low”. In Self Refresh mode, all
input/output buffers (except the CKE buffer) are disabled to lower power dissipation (Figure 12).
In the case of 4096 burst Auto Refresh commands, 4096 burst Auto Refresh commands must be performed
within 15.6 µs before entering and after exiting the Self Refresh mode.
In the case of distributed Auto Refresh commands, distributed Auto Refresh commands must be issued every
15.6 µs and the last distributed Auto Refresh command must be performed within 15.6 µs before entering the
Self Refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within
15.6 µs.
9. Power Down Mode
When the device enters the Power Down mode, all input/output buffers (except CKE buffer) are disabled to
lower power dissipation in the idle state. Power Down mode is entered by asserting CKE “low” while the device
is not running a Burst cycle. Taking CKE “high” exit this mode. When CKE goes high, a No-operation command
must be input at next CLK rising edge of CLK (Figure 13) and CKE should be set high at least 1CLK + t
at
CKS
Power Down Mode Exit.
10. CLK suspension and Input/Output Mask
When the device is running a Burst cycle, the internal CLK is suspended by asserting CKE “low” and the
burst operation is frozen from the next cycle. A Read/Write operation is held intact until the CKE signal is taken
“high”.
The Output Disable/Write Mask signal (DQM) has two functions, controlling the output data in a Read cycle
and performing word mask in a Write cycle. When the DQM is asserted “high” at the positive edge of CLK, the
output data is disabled after two clock cycles in the case of a Read operation and the write data is masked at the
same clock cycle in the case of a Write operation. The timing relations between the CKE timing and DQM are
described in Figure 21 (a) and 21 (b).
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Figure 15. Auto Precharge timing (Read cycle)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
(1) CAS Latency = 2
(a) Burst Length = 1
Command
Read AP
Act
t
RP
DQ
Q0
AP
(b) Burst Length = 2
Command
Read
Act
t
RP
DQ
Q0
Q0
Q0
Q1
Q1
Q1
(c) Burst Length = 4
Command
Read
AP
Q2
Act
t
RP
DQ
Q3
(d) Burst Length = 8
Command
Read
AP
Q6
Act
t
RP
DQ
Q2
Act
Q3
Q4
Q5
Q7
(2) CAS Latency = 3
(a) Burst Length = 1
Command
Read AP
t
RP
DQ
Q0
Q0
Q0
Q0
(b) Burst Length = 2
Command
Read
AP
Act
t
RP
DQ
Q1
AP
(c) Burst Length = 4
Command
Read
Act
t
RP
DQ
Q1
Q2
Q2
Q3
Q3
(d) Burst Length = 8
Command
Read
AP
Q5
Act
t
RP
DQ
Q1
Q4
Q6
Q7
Note) •
Read represents the Read with Auto Precharge command.
AP represents the start of internal precharging.
Act represents the Bank Activate command.
•
•
•
When the Auto Precharge command is asserted, the period from the Bank Activate command to the start of internal
precharging must be at least t (min).
RAS
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Figure 16. Auto Precharge timing (Write cycle)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
(1) CAS Latency = 2
(a) Burst Length = 1
Command
Write AP
Act
t
t
WR
RP
DQ
D0
(b) Burst Length = 2
Command
Write
AP
Act
AP
t
t
WR
RP
DQ
D0
D1
(c) Burst Length = 4
Command
Write
Act
t
t
RP
WR
DQ
D0
D1
D1
D2
D2
D3
(d) Burst Length = 8
Command
Write
AP
Act
t
t
RP
WR
DQ
D0
D3
D4
D5
D6
D7
(2) CAS Latency = 3
(a) Burst Length = 1
Command
Write AP
Act
t
t
RP
WR
DQ
D0
(b) Burst Length = 2
Command
Write
AP
Act
t
t
RP
WR
DQ
D0
D1
(c) Burst Length = 4
Command
Write
AP
Act
t
t
RP
WR
DQ
D0
D1
D2
D2
D3
(d) Burst Length = 8
Command
Write
AP
Act
t
t
RP
WR
DQ
D0
D1
D3
D4
D5
D6
D7
Note) •
Write represents the Write with Auto Precharge command.
AP represents the start of internal precharging.
Act represents the Bank Activate command.
•
•
•
When the Auto Precharge command is asserted, the period from the Bank Activate command to the start of internal
precharging must be at least t (min).
RAS
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Figure 17. Timing chart for Read-to-Write cycle
In the case of Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
(1) CAS Latency = 2
(a) Command
Read Write
DQM
DQ
D0
D1
D2
D3
(b) Command
DQM
Read
Write
DQ
D0
D1
D2
D3
(2) CAS Latency = 3
(a) Command
Read Write
DQM
DQ
D0
D1
D2
D3
(b) Command
DQM
Read
Write
DQ
D0
D1
D2
D3
Note)
•
The output data must be masked by DQM to avoid I/O conflict.
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Figure 18. Timing chart for Write-to-Read cycle
In the case of Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
(1) CAS Latency = 2
(a) Command
Write Read
DQM
DQ
D0
Q0
Q1
Q2
Q3
(b) Command
DQM
Write
Read
DQ
D0
D1
Q0
Q1
Q2
Q3
(2) CAS Latency = 3
(a) Command
Write Read
DQM
DQ
D0
Q0
Q1
Q2
Q3
(b) Command
DQM
Write
Read
DQ
D0
D1
Q0
Q1
Q2
Q3
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Figure 19. Timing chart for Burst Stop cycle (Burst stop command)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
(1) Read Cycle
(a)
Latency = 2
CAS
Command
Read
BST
Q3
DQ
Q0
Q1
Q0
Q2
Q1
Q4
Q3
(b)
Latency = 3
Command
CAS
Read
BST
Q2
DQ
Q4
(2) Write Cycle
Command
Write
D0
BST
DQ
D1
D2
D3
D4
Note)
•
BST represents the Burst stop command.
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Figure 20. Timing chart for Burst Stop cycle (Precharge command)
In the case of Burst Length = 8
0
1
2
3
4
5
6
7
8
9
10
11
12
(1) Read Cycle
(a)
Latency = 2
CAS
Command
Read
PRCG
Q3
DQ
Q0
Q1
Q0
Q2
Q1
Q4
Q3
(b)
Latency = 3
Command
CAS
Read
PRCG
Q2
DQ
Q4
(2) Write Cycle
(a)
Latency = 2
CAS
Command
Write
PRCG
t
WR
DQM
DQ
D0
D1
D2
D3
D4
(b)
Latency = 3
CAS
Command
Write
PRCG
t
WR
DQM
DQ
D0
D1
D2
D3
D4
Note)
•
PRCG represents the Precharge command.
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Figure 21 (a). CKE/DQM Input timing (Write cycle)
CLK Cycle No.
1
2
3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
D1
1
D2
2
D3
3
D5
5
D6
7
DQM MASK
(1)
CKE MASK
6
CLK Cycle No.
4
External
CLK
Internal
CKE
DQM
DQ
D1
1
D2
2
D3
3
D5
6
D6
7
DQM MASK CKE MASK
(2)
CLK Cycle No.
4
5
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D4
D5
D6
CKE MASK
(3)
2001-06-11 47/49
TC59SM716/08/04AS/ASL-70,-75,-80
Figure 21 (b). CKE/DQM Input timing (Read cycle)
CLK Cycle No.
1
2
3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q1
1
Q2
2
Q3
3
Q4
Open
Open
Q6
7
(1)
CLK Cycle No.
4
5
6
External
CLK
Internal
CKE
DQM
DQ
Q1
1
Q2
2
Q3
3
Q4
Open
Q6
7
(2)
CLK Cycle No.
4
5
6
External
CLK
Internal
CKE
DQM
DQ
Q1
Q2
Q3
Q4
Q5
Q6
(3)
2001-06-11 48/49
TC59SM716/08/04AS/ASL-70,-75,-80
PACKAGE DIMENSIONS
Unit: mm
2001-06-11 49/49
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