TC59YM916AMG24A_技术文档

TC59YM916AMG24A,32A,32B,40B

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

Lead Free

Overview

The Rambus XDR^TMDRAM device is a general purpose high-performance memory device suitable for use in a

broad range of applications including computer memory, graphics, video, and any other application where high

bandwidth and low latency are required.

The 512Mb Rambus XDR DRAM device is a CMOS DRAM organized as 32M words by 16 bits. The use of

Differential Rambus Signaling Level (DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using

conventional system and board design technologies. XDR DRAM devices are capable of sustained data transfers of

8000/6400/4800 MB/s.

XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly

addressed memory transactions. The highly efficient protocol yields over 95% utilization while allowing fine access

granularity. The device's 8 banks support up to four interleaved transactions.

Features

•

Highest pin bandwidth available

• 4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling

• Bi-directional differential RSL (DRSL)

- Flexible read/write bandwidth allocation

- Minimum pin count

• Programmable on-chip termination

-Adaptive impedance matching

-Reduced system cost and routing complexity

•

Highest sustained bandwidth per DRAM device

• 8000/6400/4800 MB/s sustained data rate

• 8 banks: bank-interleaved transactions at full bandwidth

• Dynamic request scheduling

• Early-Read-after-Write support for maximum efficiency

• Zero overhead refresh

•

Low latency

• 2.0/2.5/3.33 ns request packets

• Point-to-point data interconnect for fastest possible flight time

• Support for low-latency, fast-cycle cores

Low power

• 1.8V V

DD

• Programmable small-swing I/O signaling (DRSL)

• Low power PLL/DLL design

• Power Down Self Refresh support

• Dynamic clock gating and per pin I/O Power Down

•

Lead Free

Note: XDR is a trademark or a registered trademark in Japan and/or other countries.

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Pin Assignment (top view)

XDR DRAM CSP x16

L

K

J

H

G

F

E

D

C

B

A

DQN3 DQN9

V

SDI

DQN8 DQN2

1

2

V

DD

GND

DD

DQ3

DQN15

DQ15

DQ9

DQN5

DQ5

V

GND

RQ0

DQ8

DQN4

DQ4

DQ2

DQN14

DQ14

DD

RQ10 CFM

RSRV

RQ4

RQ3

3

DD

4

CFMN

GND RQ11

VTERM

GND

VTERM

V

5

V

DD

VTERM

GND GND

GND GND GND

V

GND GND

6

DD

7

8

9

10

11

12

13

14

15

16

VTERM

GND VTERM GND GND

V

GND GND

V

GND

DD

V

GND

DQN13

DQ13

GND

V

GND

DQN12

DQ12

DD

DQN7

V

RQ9

RQ7

VREF

RQ5

RQ1

RQ2

V

DQN6

DQ6

DD

DQ7

CMD RQ8 RQ6

GND

RST

SDO

DQN11

DQN1 SCK

DQN0

DQ0

DQN10

DQ10

DQ11 DQ1

GND

V

GND

V

DD

Note:

•

RSRV: Reserved pin

DQ8…DQ15, DQN8…DQN15 are RSRV’s for ×8

DQ4…DQ15, DQN4…DQN15 are RSRV’s for ×4

Key Timing Parameters/Part Numbers

a

b

c

d

Organization

Bandwidth (1/t

)

Latency (t

)

RAC

Bin

Part Number

BIT

8 × 4K × 1K × 16

2400

3200

4000

36

27

35

28

A

B

TC59YM916AMG24A

TC59YM916AMG32A

TC59YM916AMG32B

TC59YM916AMG40B

a. Bank × Row × Column × Width

b. Data rate measured in Mbit/s per DQ differential pair. See “Timing Conditions” on page 57 and “Timing Characteristics” on page

59. Note that t

= t

/ 8.

CYCLE

BIT

c. Read access time t

(=t

+ t

) measured in ns. See “Timing Parameters” on page 60.

CAC

RAC

RCD−R

d. Timing parameter bin. See “Timing Parameters” on page 60. This is a measure of the number of interleaved read transactions

needed for maximum efficiency (the value Ceiling (t /t ).

RC-R RR-D

For bin A, t

/ t

= 4, and for bin B, t

/ t

= 5

RC−A RR−D

RC−R RR−D

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General Description

The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets

of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11…RQ0 request pins, and

DQ15…DQ0/DQN15...DQN0 data pins. The “N” appended to a signal name denotes the complementary signal of a

differential pair.

A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on the

signals of a bus. There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus uses a

set of 2 bit-windows on each signal, while the DQ bus uses a set of 16 bit-windows on each signal.

In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T contains an activate

0

(ACT) command. This causes row Ra of bank Ba in the memory component to be loaded into the sense amp array

for the bank. A second request packet at clock edge T contains a write (WR) command. This causes the data packet

1

D (a1) at edge T to be written to column Ca1 of the sense amp array for bank Ba. A third request packet at clock

4

edge T contains another write (WR) command. This causes the data packet D (a2) at edge T to be also be written

3

6

to column Ca2. A final request packet at clock edge T contains a precharge (PRE) command.

13

The spacing between the request packets are constrained by the following timing parameters in the diagram: t

,

RCD

t , and t . In addition, the spacing between the request packets and data packets are constrained by the

CC WRP

t

arameter. The spacing of the CFM/CFMN clock edges is constrained by t

CWRD CYCLE

.

Figure 1. XDR DRAM Device Write and Read Transactions

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

ACT WR

WR

a2

PRE

a3

a0

a1

…RQ0

t

CC

WRP

RCD-W

DQ15…0

D(a1)

D(a2)

DQN15…0

t

CWD

Transaction a: WR

a0 = {Ba, Ra}

a1 = {Ba, Ca1}

a2 = {Ba, Ca2}

a3 = {Ba}

Write Transaction

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

ACT

a0

RD

a1

RD

a2

PRE

a3

…RQ0

t

RCD-R

t

CC

RDP

DQ15…0

Q(a1)

Q(a2)

DQN15…0

t

CAC

Transaction a: RD

a0 = {Ba, Ra}

a1 = {Ba, Ca1}

a2 = {Ba, Ca2}

a3 = {Ba}

Read Transaction

The read transaction shows a request packet at clock edge T containing an ACT command. This causes row Ra of

0

bank Ba of the memory component to load into the sense amp array for the bank. A second request packet at clock

edge T contains a read (RD) command. This causes the data packet Q (a1) at edge T to be read from column Ca1

11

5

of the sense amp array for bank Ba. A third request packet at clock edge T contains another RD command. This

7

causes the data packet Q (a2) at edge T to also be read from column Ca2. A final request packet at clock edge T

13

10

contains a PRE command.

The spacing between the request packets are constrained by the following timing parameters in the diagram:

t , t , and t

RCD CC RDP

. In addition, the spacing between the request and data packets is constrained by the t

CAC

parameter.

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Table of Contents

Overview------------------------------------------------------------------------------------------------------------------------------- 1

Features-------------------------------------------------------------------------------------------------------------------------------- 1

Pin Assignment (top view) ------------------------------------------------------------------------------------------------------ 2

Key Timing Parameters/Part Numbers---------------------------------------------------------------------------------------2

Related Documentation----------------------------------------------------------------------------------------------------------- 2

General Description---------------------------------------------------------------------------------------------------------------- 3

Table of Contents------------------------------------------------------------------------------------------------------------------- 4

Table of Tables----------------------------------------------------------------------------------------------------------------------- 5

Table of Figures----------------------------------------------------------------------------------------------------------------------6

Pin Description-----------------------------------------------------------------------------------------------------------------------7

Block Diagram------------------------------------------------------------------------------------------------------------------------8

Request Packets-------------------------------------------------------------------------------------------------------------------10

Request Packet Formats--------------------------------------------------------------------------------------------------------10

Request Field Encoding---------------------------------------------------------------------------------------------------------12

Request Field Interactions----------------------------------------------------------------------------------------------------- 14

Request Interactions Cases--------------------------------------------------------------------------------------------------- 15

Dynamic Request Scheduling-------------------------------------------------------------------------------------------------20

Memory Operations---------------------------------------------------------------------------------------------------------------22

Write Transactions--------------------------------------------------------------------------------------------------------------- 22

Read Transactions---------------------------------------------------------------------------------------------------------------24

Interleaved Transactions--------------------------------------------------------------------------------------------------------26

Read/Write Interaction-----------------------------------------------------------------------------------------------------------28

Propagation Delay-----------------------------------------------------------------------------------------------------------------30

Register Operations-------------------------------------------------------------------------------------------------------------- 32

Serial Transactions-------------------------------------------------------------------------------------------------------------- 32

Serial Write Transaction--------------------------------------------------------------------------------------------------------32

Serial Read Transaction--------------------------------------------------------------------------------------------------------32

Register Summary---------------------------------------------------------------------------------------------------------------- 34

Maintenance Operations--------------------------------------------------------------------------------------------------------40

Refresh Transactions----------------------------------------------------------------------------------------------------------- 40

Interleaved Refresh Transactions--------------------------------------------------------------------------------------------40

Calibration Transactions--------------------------------------------------------------------------------------------------------42

Power State Management-------------------------------------------------------------------------------------------------------43

Initialization------------------------------------------------------------------------------------------------------------------------- 45

XDR DRAM Initialization Overview------------------------------------------------------------------------------------------47

XDR DRAM Pattern Load with WDSL Register-------------------------------------------------------------------------- 47

Special Feature Description--------------------------------------------------------------------------------------------------- 49

Dynamic Width Control--------------------------------------------------------------------------------------------------------- 49

Write Masking-----------------------------------------------------------------------------------------------------------------------51

Multiple Bank Sets and the ERAW Feature------------------------------------------------------------------------------- 53

Simultaneous Precharge--------------------------------------------------------------------------------------------------------55

Operating Conditions------------------------------------------------------------------------------------------------------------ 56

Electrical Conditions-------------------------------------------------------------------------------------------------------------56

Timing Conditions---------------------------------------------------------------------------------------------------------------- 57

Operating Characteristics------------------------------------------------------------------------------------------------------ 58

Electrical Characteristics-------------------------------------------------------------------------------------------------------58

Supply Current Profile-----------------------------------------------------------------------------------------------------------59

Timing Characteristics---------------------------------------------------------------------------------------------------------- 59

Timing Parameters----------------------------------------------------------------------------------------------------------------60

Receive/Transmit Timing--------------------------------------------------------------------------------------------------------61

Clocking---------------------------------------------------------------------------------------------------------------------------- 61

RSL RQ Receive Timing---------------------------------------------------------------------------------------------------------62

DRSL DQ Receive Timing-------------------------------------------------------------------------------------------------------63

DRSL DQ Transmit Timing----------------------------------------------------------------------------------------------------- 65

Serial Interface Receive Timing-----------------------------------------------------------------------------------------------67

Serial Interface Transmit Timing--------------------------------------------------------------------------------------------- 68

Package Description------------------------------------------------------------------------------------------------------------- 69

Package Parasitic Summary-------------------------------------------------------------------------------------------------- 69

Package Mechanical Drawing-------------------------------------------------------------------------------------------------71

Package Pin Numbering---------------------------------------------------------------------------------------------------------72

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Table of Tables

Table 1. Pin Descriptions------------------------------------------------------------------------------------------------------ 7

Table 2. Request Field Description----------------------------------------------------------------------------------------10

Table 3. OP Field Encoding Summary------------------------------------------------------------------------------------12

Table 4. ROP Field Encoding Summary----------------------------------------------------------------------------------12

Table 5. POP Field Encoding Summary----------------------------------------------------------------------------------13

Table 6. XOP Field Encoding Summary----------------------------------------------------------------------------------13

Table 7. Packet Interaction Summary------------------------------------------------------------------------------------ 14

Table 8. SCMD Field Encoding Summary------------------------------------------------------------------------------- 32

Table 9. Initialization Timing Parameters--------------------------------------------------------------------------------46

Table 10. WDSL-to-Core Mapping (First Generation ×16/×8/×4 XDR DRAM, BL = 16)-------------------47

Table 11. DQ Bit to WDSL Bit Transfer Order Mapping

(First Generation ×16/×8/×4 XDR DRAM, BL = 16) ------------------48

Table 12. Electrical Conditions--------------------------------------------------------------------------------------------- 56

Table 13. Timing Conditions-------------------------------------------------------------------------------------------------57

Table 14. Electrical Characteristics--------------------------------------------------------------------------------------- 58

Table 15. Supply Current Profile------------------------------------------------------------------------------------------- 59

Table 16. Timing Characteristics-------------------------------------------------------------------------------------------59

Table 17. Timing Parameters------------------------------------------------------------------------------------------------ 60

Table 18. Package RSL Parasitic Summary---------------------------------------------------------------------------- 69

Table 19. CSP x16 Package Mechanical Parameters----------------------------------------------------------------71

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Table of Figures

Figure 1. XDR DRAM Device Write and Read Transactions-------------------------------------------------------- 3

Figure 2. 512Mb (8x4Mx16) XDR DRAM Block Diagram--------------------------------------------------------------9

Figure 3. Request Packet Formats-----------------------------------------------------------------------------------------11

Figure 4. ACT-, RD-, WR-, PRE-to-ACT Packet Interactions-------------------------------------------------------16

Figure 5. ACT-, RD-, WR-, PRE-to-RD Packet Interactions---------------------------------------------------------17

Figure 6. ACT-, RD-, WR-, PRE-to-WR Packet Interactions-------------------------------------------------------- 18

Figure 7. ACT-, RD-, WR-, PRE-to-PRE Packet Interactions-------------------------------------------------------19

Figure 8. Request Scheduling Examples-------------------------------------------------------------------------------- 21

Figure 9. Write Transactions-------------------------------------------------------------------------------------------------23

Figure 10. Read Transactions------------------------------------------------------------------------------------------------25

Figure 11. Interleaved Transactions--------------------------------------------------------------------------------------- 27

Figure 12. Write/Read Interaction------------------------------------------------------------------------------------------ 29

Figure 13. Propagation Delay------------------------------------------------------------------------------------------------31

Figure 14. Serial Write Transaction---------------------------------------------------------------------------------------- 33

Figure 15. Serial Read Transaction – Selected DRAM---------------------------------------------------------------33

Figure 16. Serial Read Transaction – Non-Selected DRAM--------------------------------------------------------33

Figure 17. Serial Identification (SID) Register--------------------------------------------------------------------------35

Figure 18. Configuration (CFG) Register---------------------------------------------------------------------------------35

Figure 19. Power Management (PM) Register--------------------------------------------------------------------------35

Figure 20. Write Data Serial Load (WDSL) Control Register------------------------------------------------------ 36

Figure 21. RQ Scan High (RQH) Register--------------------------------------------------------------------------------36

Figure 22. RQ Scan Low (RQL) Register---------------------------------------------------------------------------------36

Figure 23. Refresh Bank (REFB) Control Register--------------------------------------------------------------------36

Figure 24. Refresh High (REFH) Row Register-------------------------------------------------------------------------36

Figure 25. Refresh Middle (REFM) Row Register--------------------------------------------------------------------- 37

Figure 26. Refresh Low (REFL) Row Register--------------------------------------------------------------------------37

Figure 27. Current Calibration 0 (CC0) Register-----------------------------------------------------------------------37

Figure 28. Current Calibration 1 (CC1) Register-----------------------------------------------------------------------37

Figure 29. Impedance Calibration 0 (ZC0) Register------------------------------------------------------------------ 37

Figure 30. Impedance Calibration 1 (ZC1) Register------------------------------------------------------------------ 38

Figure 31. Read Only Memory 0 (ROM0) Register-------------------------------------------------------------------- 38

Figure 32. Read Only Memory 1 (ROM1) Register-------------------------------------------------------------------- 38

Figure 33. Test Register------------------------------------------------------------------------------------------------------- 38

Figure 34. DLL Register--------------------------------------------------------------------------------------------------------38

Figure 35. PLL0 Register------------------------------------------------------------------------------------------------------39

Figure 36. PLL1 Register------------------------------------------------------------------------------------------------------39

Figure 37. IFT Register---------------------------------------------------------------------------------------------------------39

Figure 38. DA Register--------------------------------------------------------------------------------------------------------- 39

Figure 39. Partner-Definable (PART) Register--------------------------------------------------------------------------39

Figure 40. Delay (DLY) Control Register--------------------------------------------------------------------------------- 39

Figure 41. Refresh Transactions--------------------------------------------------------------------------------------------41

Figure 42. Calibration Transactions--------------------------------------------------------------------------------------- 42

Figure 43. Power State Management--------------------------------------------------------------------------------------44

Figure 44. Serial Interface Systems Topology------------------------------------------------------------------------- 45

Figure 45. Initialization Timing for XDR DRAM [ k ] Device--------------------------------------------------------45

Figure 46. Multiplexes for Dynamic Width Control------------------------------------------------------------------- 49

Figure 47. D-to-S and S-to-Q Mapping for Dynamic Width Control--------------------------------------------- 50

Figure 48. Byte Mask Logic---------------------------------------------------------------------------------------------------51

Figure 49. Write-Masked (WRM) Transaction Example--------------------------------------------------------------52

Figure 50. Write/Read Interaction – No ERAW Feature--------------------------------------------------------------53

Figure 51. Write/Read Interaction – ERAW Feature------------------------------------------------------------------ 53

Figure 52. XDR DRAM Block Diagram with Bank Sets-------------------------------------------------------------- 54

Figure 53. Simultaneous Precharge – tPP-D Cases------------------------------------------------------------------55

Figure 54. Clocking Waveforms---------------------------------------------------------------------------------------------61

Figure 55. RSL RQ Receive Waveform------------------------------------------------------------------------------------62

Figure 56. DRSL DQ Receive Waveform--------------------------------------------------------------------------------- 64

Figure 57. RSL DQ Transmit Waveforms---------------------------------------------------------------------------------66

Figure 58. Serial Interface Receive Waveforms------------------------------------------------------------------------67

Figure 59. Serial Interface Transmit Waveforms---------------------------------------------------------------------- 68

Figure 60. Equivalent Circuits for Package Parasitic----------------------------------------------------------------70

Figure 61. CSP x16 Package Mechanical Drawing--------------------------------------------------------------------71

Figure 62. CSP x16 Package - Pin Numbering (top view) ----------------------------------------------------------72

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Pin Description

Table 1 summarizes the pin functionality of the XDR DRAM device. The first group of pins provides the necessary

supply voltages. These include VDD and GND for the core and interface logic, VREF for receiving input signals,

and VTERM for driving output signals.

The next group of pins is used for high bandwidth memory accesses. These include DQ15…DQ0 and

DQN15...DQN0 for carrying read and write data signals, RQ11...RQ0 for carrying request signals, and CFM and

CFMN for carrying timing information used by the DQ, DQN, and RQ signals.

The final set of pins comprises the serial interface that is used for control register accesses. These include RST for

initializing the state of the device, CMD for carrying command signals, SDI and SDO for carrying register read

data, and SCK for carrying the timing information used by the RST, SDI, SDO, and CMD signals.

Table 1. Pin Descriptions

Signal

I/O

Type

No. of Pins

Description

VDD

GND

22

26

1

Supply voltage for the core and interface of the device.

Ground reference for the core and interface logic of the device.

Logic threshold reference voltage for RSL signals.

VREF

VTERM

6

Termination voltage for DRSL signals.

a

DQ15…DQ0

DQN15…DQN0

RQ11…RQ0

I/O

I

DRSL

16

12

Positive data signals that carry write or read data to and from the device.

Negative data signals that carry write or read data to and from the device.

Request signals that carry control and address information to the device.

b

RSL

Clock from master – Positive interface clock used for receiving RSL signals,

and receiving and transmitting DRSL signals from the Channel.

c

CFM

I

DIFFCLK

1

Clock from master – Negative interface clock used for receiving RSL signals,

and receiving and transmitting DRSL signals from the Channel.

CFMN

RST

I

1

d

RSL

Request input – This pin is used to initialize the device.

Command input – This pin carries command, address, and control register

write data into the device.

d

CMD

RSL

Serial clock input – Clock source used for reading from and writing to the

control registers.

d

SCK

SDI

I

RSL

1

Serial data input – This pin carries control register read data through the

device. This pin is also used to initialize the device.

d

RSL

Serial data output – This pin carries control register read data from the

device. This pin also used to initialize the device.

e

SDO

O

CMOS

RSRV

2

Reserved pins – do not connect

Total pin count per package

108

a. All DQ signals are high-true; low voltage is logic 0 and high voltage is logic 1.

All DQN signals are low-true; high voltage is logic 0 and low voltage is logic 1.

b. All RQ signals are low-true; high voltage is a logic 0 and a low voltage is logic 1.

c. All CFM signals are high-true; low voltage is a logic 0 and a high voltage is logic 1.

All CFMN signals are low-true; high voltage is a logic 0 and a low voltage is logic 1.

d. All serial RSL signals are low-true; high voltage is a logic 0 and a low voltage is logic 1.

e. All serial CMOS signals are low-true; high voltage is a logic 0 and a low voltage is logic 1.

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Block Diagram

A block diagram of the XDR DRAM device is shown in Figure 2. It shows all interface pins and major internal

blocks.

The CFM and CFMN clock signals are received and used by the clock generation logic to produce three virtual

clock signals: 1/t , 2/t , and 16/t . The frequencies of these signals are 1x, 2x, and 8x that of the CFM

CYCLE CYCLE CC

and CFMN signals. These virtual signals show the effective data rate of the logic blocks to which they connect; they

are not necessarily present in the actual memory component.

The RQ11...RQ0 pins receive the request packet. Two 12-bit words are received in one t

indicated by the 2/t

CYCLE

interval. This is

clocking signal connected to the 1: 2 Demux Block that assembles the 24-bit request

CYCLE

packet. These 24 bits are loaded into a register (clocked by the 1/t

CYCLE

clocking signal) and decoded by the Decode

Block. The VREF pin supplies a reference voltage used by the RQ receivers.

The Decode Block produces three sets of control signals. These include the bank (BA) and row (R) addresses for

an activate (ACT) command, the bank (BR) and row (REFr) addresses for a refresh activate (REFA) command, the

bank (BP) address for a precharge (PRE) command, the bank (BR) address for a refresh precharge (REFP)

command, and the bank (BC) and column (C and SC) addresses for a read (RD) or write (WR or WRM) command. In

addition, a mask (M) is used for a masked write (WRM) command.

These commands can all be optionally delayed in increments of t

CYCLE

under control of delay fields in the

request. The control signals of the commands are loaded into registers and presented to the memory core. These

registers are clocked at maximum rates determined by core timing parameters, in this case 1/t , 1/t , and 1/t

RR PP CC

(1/4, 1/4, and 1/2 the frequency of CFM in the −3200 component). These registers may be loaded at any t

CYCLE

rising edge. Once loaded, they should not be changed until a t , t , or t

RR PP

time later because timing paths of the

CC

memory core need time to settle.

A bank address is decoded for an ACT command. The indicated row of the selected bank is sensed and placed into

the associated sense amp array for the bank. Sensing a row is also referred to as “opening a page” for the bank.

Another bank address is decoded for a PRE command. The indicated bank and associated sense amp array are

precharged to a state in which a subsequent ACT command can be applied. Precharging a bank is also called

“closing the page” for the bank.

After a bank is given an ACT command and before it is given a PRE command, it may receive read (RD) and

write (WR) column commands. These commands permit the data in the bank’s associated sense amp array to be

accessed.

For a WR command, the bank address is decoded. The indicated column of the associated sense amp array of the

selected bank is written with the data received from the DQ15…DQ0 pins.

The bank address is decoded for a RD command. The indicated column of the selected bank’s associated sense

amp array is read. The data is transmitted onto the DQ15...DQ0 pins.

The DQ15...DQ0 pins receive the write data packet (D) for a write transaction. 16 sixteen-bit words are received

in one t

CC

interval. This is indicated by the 16/t clocking signal connected to the 1:16 Demux Block that

CC

assembles the 16x16-bit write data packet. The write data is then driven to the selected Sense Amp Array Bank.

16 sixteen-bit words are accessed in the selected Sense Amp Array Bank for a read transaction. The DQ15…0

pins transmit this read data packet (Q) in one t

CC

interval. This is indicated by the 16/t clocking signal

CC

connected to the 16:1 Mux Block. The VTERM pin supplies a termination voltage for the DQ pins.

The RST, SCK, and CMD pins connect to the Control Register block. These pins supply the data, address and

control needed to write the control registers. The read data for these registers is accessed through the SDO/SDI

pins. These pins are also used to initialize the device.

The controls registers are used to transition between power modes, and are also used for calibrating the high speed

transmit and receive circuits of the device. The control registers also supply bank (REFB) and row (REFr)

addresses for refresh operations.

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Figure 2. 512Mb (8x4Mx16) XDR DRAM Block Diagram

RQ11...RQ0

12

VREF

1

CFM CFMN RST,SCK,CMD,SDI SDO

4

1

2/t

1/t

2/t

CYCLE

16/t

CC

1:2 Demux

Reg

Control Registers

12

1/t

CYCLE

Power Mode Logic

Calibration Logic

Refresh Logic

WIDTH

Decode

REFB,REFr

Initialization Logic

COL logic

PRE logic

ACT logic

7

6+4

3

12

3

RD,WR

delay

PRE delay

ACT delay

(0..3)*t

(0..1)*t

CYCLE

3

1/t

RR

2

(0..1)*t

CYCLE

1

Bank Array

16x16*2⁶*2¹²

ACT

3

BA,BR,REFB

R,REFr

ACT

ROW

12

ROW

RR

2

1

PRE

3

Bank 0

BA,BR,REFB

PRE

3

Bank (2 -1)

6

16x16*2

1/t

RR

3

2

1

R/W

COL

Sense Amp Array

3

BC

16x16*2⁶

R/W

COL

Sense Amp 0

6

4

C

3

SC

Sense Amp (2 -1)

16x16

8

M

S[15:0] [15:0]

16x16

Byte Mask (WR)

WIDTH

Dynamic Width Demux (WR)

16x16 D[15:0] [15:0]

Dynamic Width Demux (RD)

Q[15:0] [15:0]

16x16

16

1:16 Demux

16

16:1 mux

16/t

CC

16

termination

6

16

VTERM

DQ15…DQ0

DQN15…DQN0

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TC59YM916AMG24A,32A,32B,40B

Request Packets

A request packet carries address and control information to the memory device. This section contains tables and

diagrams for packet formats, field encoding and packet interactions.

Request Packet Formats

There are five types of request packets:

1. ROWA - specifies an ACT command

2. COL - specifies RD and WR commands

3. COLM - specifies a WRM command

4. ROWP - specifies PRE and REF commands

5. COLX - specifies the remaining commands

Table 2 describes fields within different request packet types. Various request packet type formats are illustrated

in Figure 3.

Each packet type consists of 24 bits sampled on the RQ11..RQ0 pins on two successive edges of the CFM/CFMN

clock. The request packet formats are distinguished by the OP3..OP0 field. This field also specifies the operation

code of the desired command.

In the ROWA packet, a bank address (BA), row address (R), and command delay (DELA) are specified for the

activate (ACT) command.

In the COL packet, a bank address (BC), column address (C), sub-column address (SC), command delay (DELC),

and sub-opcode (WRX) are specified for the read (RD) and write (WR) commands.

In the COLM packet, a bank address (BC), column address (C), sub-column address (SC), command delay (DELC),

and mask field (M) are specified for the masked write (WRM) command.

In the ROWP packet, two independent commands may be specified. A bank address (BP) and sub-opcode (POP)

are specified for the precharge (PRE) commands. An address field (RA) and sub-opcode (ROP) are specified for the

refresh (REF) commands.

In the COLX packet, a sub-operation code field (XOP) is specified for the remaining commands.

Table 2. Request Field Description

Field

Packet Types

Description

ROWA/ROWP/CO 4-bit operation code that specifies packet format.

OP3..OP0

L/COLM/COLX

(Encoded commands are in a Table 3 on page 12.)

DELA

BA2..BA0

R11..R0

ROWA

Delay the associated row activate command by 0 or 1 t

3-bit bank address for row activate command.

12-bit row address for row activate command.

.

CYCLE

WRX

DELC

COL

Specifies RD (=0) or WR (=1) command.

COL/COLM

COLM

Delay the column read or write command by 0 or 1 t

.

CYCLE

BC2..BC0

C9..C4

3-bit bank address for column read or write command.

6-bit column address for column read or write command.

SC3..SC0

M7..M0

4-bit sub-column address for dynamic width (see “Dynamic Width Control” on page 49).

8-bit mask for masked-write command WRM.

3-bit operation code that specifies row precharge command with a delay of 0 to 3 t

(Encoded commands are in Table 5 on page 13).

.

CYCLE

POP2..POP0

BP2..BP0

ROWP

3-bit bank address for row precharge command.

3-bit operation code that specifies refresh commands.

(Encoded commands are in Table 4 on page 12).

ROP2..ROP0

RA7..RA0

8-bit refresh address field (specifies BR bank address, delay value, and REFr load value)

4-bit extended operation code that specifies column preload, calibration and Power Down

commands. (Encoded commands are in Table 6 on page13).

XOP3..XOP0

COLX

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Figure 3. Request Packet Formats

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

ACT

a0

RD

a1

WRM

a2

PRE

a3

PDN

…RQ0

DQ15…0

DQN15…0

ROWA Packet

COL Packet

COLM Packet

ROWP Packet

COLX Packet

t

CYCLE

CFM

CFMN

OP DEL

OP

3

M

7

OP POP

OP rsrv

3

RQ11

RQ10

RQ9

RQ8

RQ7

RQ6

RQ5

RQ4

RQ3

RQ2

RQ1

RQ0

3

A

3

C

3

2

OP

2

R

8

OP rsrv

2

M

3

M

6

OP ROP

OP rsrv

2

R

9

R

7

OP rsrv

1

M

2

M

5

OP ROP

OP rsrv

1

R

10

R

6

OP rsrv

0

M

1

M

4

OP ROP

OP rsrv

0

R

11

R

5

WR

X

C

7

M

0

C

7

RA

7

rsrv

POP

1

rsrv

R

4

C

8

C

6

C

8

C

6

POP RA

rsrv rsrv

0

6

R

3

C

9

C

5

C

9

C

5

rsrv RA

5

R

2

rsrv

C

4

rsrv

C

4

rsrv RA

4

XOP

3

R

1

rsrv SC

3

rsrv SC

3

rsrv RA

3

rsrv

BA

2

R

0

BC SC

2

BP RA

XOP rsrv

2

BA rsrv

1

BC SC

1

BP RA

XOP rsrv

1

BA rsrv

0

BC SC

0

BP RA

XOP rsrv

0

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Request Field Encoding

Operation-code fields are encoded within different packet types to specify commands. Table 3 through Table 6

provides packet type and encoding summaries.

Table 3 shows the OP field encoding for the five packet types. The COLM and ROWA packets each specify a

single command: ACT and WRM. The COL, COLX, and ROWP packets each use additional fields to specify

multiple commands: WRX, XOP, and POP/ROP, respectively. The COLM packet specifies the masked write

command WRM. This is like the WR unmasked write command, except that a mask field M7...M0 indicates

whether each byte of the write data packet is written or not written. The ROWA packet specifies the row activate

command ACT. The COL packet uses the WRX field to specify the column read and column write (unmasked)

commands

Table 3. OP Field Encoding Summary

OP [3:0] Packet

0000

Command

NOP

Description

No operation

Column read (WRX = 0). Column C9…C4 of sense amp in bank BC2…BC0 is read to DQ bus after

DELC*t

RD

.

CYCLE

0001

COL

Column write (WRX = 1). Write DQ bus to column C9…C4 of sense amp in bank BC2…BC0 after

DELC*t

WR

.

CYCLE

0010

0011

COLX

CALy

PREx

XOP3…XOP0 specifies a calibrate or Power Down command – see Table 6 on page 13.

POP2…POP0 specifies a row precharge command – see Table 5 on page 13.

ROWP

REFy, LRRr

ROP2…ROP0 specifies a row refresh command or load REFr register command – see Table 4 on page 12.

Row activate command. Row R11…R0 of bank BA2…BA0 is placed into the sense amp of the bank after

01xx

1xxx

ROWA

COLM

ACT

DELA*t

CYCLE

.

WRM

Column write command (masked) – mask M7…M0 specifies which bytes are written.

Encoding of the ROP field in the ROWP packet is shown in Table 4. The first encoding specifies a NOPR (no

operation) command. The REFP command uses the RA field to select a bank to be precharged. The REFA and REFI

commands use the RA field and REFH/M/L registers to select a bank and row to be activated for refresh. The REFI

command also increments the REFH/M/L register. The REFP, REFA, and REFI commands may also be delayed by

up to 3*t

using the RA [7:6] field. The LRR0, LRR1, and LRR2 commands load the REFH/M/L registers from

the RA [7:0] field.

CYCLE

Table 4. ROP Field Encoding Summary

ROP [2:0]

000

Command

Description

NOPR

REFP

No operation

Refresh precharge command. Bank RA2…RA0 is precharged.

This command is delayed by {0, 1, 2, 3}*t (the value is given by the expression (2*RA [7] + RA [6]).

001

010

CYCLE

Refresh activate command. Row R [11:0] (from REFH/M/L register) of bank RA2…RA0 is placed into sense amp.

This command is delayed by {0, 1, 2, 3}*t (the value is given by the expression (2*RA [7] + RA [6]).

REFA

REFI

CYCLE

Refresh activate command. Row R [11:0] (from REFH/M/L register) of bank RA2…RA0 is placed into sense amp.

This command is delayed by {0, 1, 2, 3}*t (the value is given by the expression (2*RA [7] + RA [6]).

011

CYCLE

R[11 : 0] field of REFH/M/L register is incremented after the activate command has completed.

100

101

110

111

LRR0

LRR1

LRR2

Load Refresh Low Row register (REFL). RA [7:0] is stored in R [7:0] field.

4 cycle spacing required

between ROWP packets with

LRRn commands

Load Refresh Middle Row register (REFM). RA [3:0] is stored in R [11:8] field.

Load Refresh High Row register – not used with this device

Reserved

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The REFH/M/L registers are also referred to as the REFr registers. Note that only the bits that are needed for

specifying the refresh row (12 bits in all) are implemented in the REFr registers - the rest are reserved. Note also

that the RA2…RA0 field that specifies the refresh bank address is also referred to as BR2…BR0. See “Refresh

Transactions” on page 40.

Table 5 shows the POP field encoding in the ROWP packet. The first encoding specifies a NOPP (no operation)

command. There are four variations of PRE (precharge) command. Each uses the BP field to specify the bank to be

precharged. Each also specifies a different delay of up to 3*t

using the POP [1:0] field. A precharge command

CYCLE

may be specified in addition to a refresh command using the ROP field.

Table 5. POP Field Encoding Summary

POP [2:0]

Command

NOPP

Description

000

001

010

011

100

101

110

111

No operation

Reserved.

PRE0

PRE1

PRE2

PRE3

Row precharge command – Bank BP2… BP0 is precharged. This command is delayed by 0*t

Row precharge command – Bank BP2… BP0 is precharged. This command is delayed by 1*t

Row precharge command – Bank BP2… BP0 is precharged. This command is delayed by 2*t

Row precharge command – Bank BP2… BP0 is precharged. This command is delayed by 3*t

.

CYCLE

Table 6 shows the XOP field encoding in the COLX packet. This field encodes the remaining commands.

The CALC and CALE commands perform calibration operations to ensure signal integrity on the Channel. See

“Calibration Transactions” on page 42.

The PDN command causes the device to enter a power-down state. See “Power State Management” on page 43.

Table 6. XOP Field Encoding Summary

XOP [3:0] Command

Command and Description

Reserved

XOP [3:0] Command

Command and Description

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

CALC

CALE

PDN

Current calibration command.

Reserved

Reserved.

Reserved

End calibration command (CALC).

Reserved.

Enter Power Down power state.

Reserved

Reserved.

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Request Field Interactions

A summary of request packet interactions is shown in Table 7. Each case is limited to request packets with

commands that perform memory operations (including refresh commands). This includes all commands in ROWA,

ROWP, COL, and COLM packets. The commands in COLX packets are described in later sections. See

“Maintenance Operations” on page 40.

Request packet/command “a” is followed by request packet/command “b”. The minimum possible spacing between

these two packet/commands is 0*t . However, a larger time interval may be needed because of a resource

CYCLE

interaction between the two packet/commands. If the minimum possible spacing is 0*t

, then an entry of “No

CYCLE

limit” is shown in the table.

Note that the spacing values shown in the table are relative to the effective beginning of a packet/command. The

use of the delay field with a command will delay the position of the effective packet/command from the position of

the actual packet/command. See “Dynamic Request Scheduling” on page 20.

Any of the packet/command encoding under one of the four operation types is equivalent in terms of the resource

constraints. Therefore, both the horizontal columns (packet “a”) and vertical rows (packet “b”) of the interaction

table are divided into four major groups.

The four possible operation types for request packets a and b include:

:

[A] Activate Row

•

ROWA/ACT

ROWP/REFA

ROWP/REFI

COL/RD

;

[R] Read Column

[W] Write Column

COL/WR

COLM/WRM

ROWP/PRE

ROWP/REFP

;

[P] Precharge Row

Table 7. Packet Interaction Summary

Second packet/command to bank Bb

Activate Row [A]

Read Column [R]

Write Column [W]

Precharge Row[P]

First packet command to bank Ba

ROWA – ACT Bb

ROWP – REFA Bb

ROWP – REFI Ba

COL – RD Bb

COL – WR Bb

ROWP – PRE Bb

ROWP – REFP Bb

COLM – WRM Bb

Activate Row [A]

Ba, Bb different

Case AAd: t

Case ARd: No limit

Case AWd: No limit

Case APd: No limit

RR

RC

ROWA – ACT Ba

ROWP – REFA Ba

Ba, Bb same

ROWP – REFI Ba

Case AAs: t

Case ARs: t

RCD-R

Case AWs: t

RCD-W

Case APs: t

RAS

a

Ba, Bb different

Case RAd: No limit

b

Case RRd: t

Case RRs: t

Case RWd : t

Case RPd: No limit

Case RRs: t

CC

∆RW

Read Column [R]

a

COL – RD Ba

Ba, Bb same

Ba, Bb different

Ba, Bb same

Ba, Bb different

Ba, Bb same

Case RAs : t

+ t

Case RWs : t

RDP RP

CC

∆RW

RDP

Case WPd: No limit

c

Write Column [W]

Case WAd: No limit

b

Case WRd : t

Case WWd: t

Case WWs: t

∆WR

CC

COL – WR Ba

c

Case WAs : t

+t

Case WRs : t

Case WPs: t

WRP RP

∆WR

CC

WRP

COLM – WRM Ba

Precharge Row [P]

Case PAd: No limit

Case PRd: No limit

d

Case PWd: No limit

d

Case PPd: t

PP

ROWP – PRE Ba

ROWP – REFP Ba

Case PAs: t

Figure 4

Case PRs : t +t

Case PWs : t +t

Case PPs: t

Figure 7

RP

RP RCD-R

RP RCD-W

RC

See Examples:

Figure 5

Figure 6

a. t

is equal to t

+ t

−

+ t

− t

and is defined in Table 15. This also depends upon propagation

CWD

∆RW

CC

RW BUB,XDR DRAM

CAC

delay – See “Propagation Delay” on page 30.

b. A PRE command is needed between the RD and ACT/REFA commands or the WR/WRM and ACT/REFA commands.

c. t is defined in Table 15.

∆WR

d. An ACT command is needed between the PRE/REFP and RD commands or the PRE/REFP and WR/WRM commands.

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TC59YM916AMG24A,32A,32B,40B

The first request is shown along the vertical axis on the left of the table. The second request is shown along the

horizontal axis at the top of the table. Each request includes a bank specification “Ba” and “Bb”. The first and

second banks may be the same, or they may be different. These two sub cases for each interaction are shown along

the vertical axis on the left.

There are 32 possible interaction cases altogether. The table gives each case a label of the form “xyz”, where “x”

and “y” are one of the four operation types (“A” for Activate, “R” for Read, “W” for Write, or “P” for Precharge) for

the first and second request, respectively, and “z” indicates the same bank (“s”) or different bank (“d”).

Along the horizontal axis at the bottom of the table are cross-references to four figures (Figure 4 through Figure

7). Each figure illustrates the eight cases in the corresponding vertical column. Thus, Figure 4 shows the eight

cases when the second request is an activate operation (“A”). In the following discussion of the cases, only those in

which the interaction interval is greater than t

will be described.

CYCLE

Request Interactions Cases

In Figure 4, the interaction interval for the AAd case is t . This parameter is the row-to-row time and is the

RR

minimum interval between activate commands to different banks of a device.

The interaction interval for the AAs case is t . This is the row cycle time parameter and is the minimum

RC

interval between activate commands to same banks of a device. A precharge operation must be inserted between

the two activate operations.

The interaction interval for the RAs case is t

+ t . A precharge operation must be inserted between the read

RP

RDP

and activate operation. The minimum interval between a read and a precharge operation to a bank is t

RDP

. The

minimum interval between a precharge and an activate operation to a bank is t

RP

.

The interaction interval for the WAs case is t

WRD

+ t . A precharge operation must be inserted between the

RP

read and the activate operation. The minimum interval between a write and a precharge operation to a bank is

t . The minimum interval between a precharge and an activate operation to a bank is t

WRD RP

.

The interaction interval for the PAs case is t . The minimum interval between a precharge and an activate

RP

operation to a bank is t

RP

.

In Figure 5, the interaction interval for the ARs case is t

. This is the row-to-column-read time parameter

RCD-R

and represents the minimum interval between an activate operation and a read operation to a bank.

The interaction interval for the RRd and RRs cases is t . This is the column-to-column time parameter and

CC

represents the minimum interval between two read operations.

The interaction interval for the WRd and WRs cases is t∆ . This is the write-to-read time parameter and

WR

represents the minimum interval between a write and a read operation to any banks. See “Read/Write Interaction”

on page 28.

The interaction interval for the PRs case is t

+ t . An activate operation must be inserted between the

RCD-R

RP

precharge and the read operation. The minimum interval between a precharge and an activate operation to a bank

is t . The minimum interval between an activate and read operation to a bank is t

.

RP RCD-R

In Figure 6, the interaction interval for the AWs case is t

. This is the row-to-column-write timing

RCD-W

parameter and represents the minimum interval between an activate operation and a write operation to a bank.

The interaction interval for the RWd and RWs cases is t∆ . This is the read-to-write time parameter and

RW

represents the minimum interval between a read and a write operation to any banks. See “Read/Write Interaction”

on page 28.

The interaction interval for the WWd and WWs cases is t . This is the column-to-column time parameter and

CC

represents the minimum interval between two write operations.

The interaction interval for the PWs case is t

RP

+ t . An activate operation must be inserted between the

RCD-W

precharge and the write operation. The minimum interval between a precharge and an activate operation to a bank

is t . The minimum interval between an activate and a write operation to a bank is t

.

RP RCD-W

In Figure 7, the interaction interval for the APs case is t

- precharge time to a bank.

. This parameter is the minimum activate – to

RAS

The interaction intervals for the RPs and WPs cases are t

write-to-precharge time parameters to a bank.

and t , respectively. These are the read- or

WRD

RDP

The interaction interval for the PPd case is t . This parameter is the precharge-to-precharge time and the

PP

minimum interval between precharge commands to different banks of a device.

The interaction interval for the PPs case is t . This is the row cycle time parameter and the minimum interval

RC

between precharge commands to same banks of a device. An activate operation must be inserted between the two

activate operations. This activate operation must be placed a time t

second precharge.

after the first, and a time t before the

RAS

RP

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TC59YM916AMG24A,32A,32B,40B

Figure 4. ACT-, RD-, WR-, PRE-to-ACT Packet Interactions

T₀

T₁

T₂

T₃

T₄

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

RP

RAS

RQ11

ACT

a

ACT

b

ACT

a

PRE

a

ACT

b

…RQ0

t

RR

RC

DQ15…0

DQN15…0

AAd Case (activate-activate-different bank)

AAs Case (activate-activate-same bank)

a: ROWA Packet with ACT,Ba,Ra

b: ROWA Packet with ACT,Bb,Rb

a: ROWA Packet with ACT,Ba,Ra

Ba ≠ Bb

Ba = Bb

b: ROWA Packet with ACT,Bb,Rb

T₀

T₁

T₂

T₃

T₄

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

RP

RDP

RQ11

RD ACT

RD

a

PRE

a

ACT

b

a

b

…RQ0

t

RDP + RP

No limit

DQ15…0

DQN15…0

RAd Case (read-activate-different bank)

RAs Case (read-activate-same bank)

a: COL Packet with RD,Ba,Ra

a: COL Packet with RD, Ba,Ra

Ba ≠ Bb

Ba = Bb

b: ROWA Packet with ACT,Bb,Rb

T₀

T₁

T₂

T₃

T₄

T₅T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

RP

t

WRP

RQ11

WR ACT

WR

a

PRE

a

ACT

b

a

b

…RQ0

t

WRP + RP

No limit

DQ15…0

DQN15…0

WAd Case (write-activate-different bank)

WAs Case (write-activate-same bank)

a: COL Packet with WR,Ba,Ra

a: COL Packet with WR, Ba,Ra

Ba ≠ Bb

Ba = Bb

b: ROWA Packet with ACT,Bb,Rb

T₀

T₁

T₂

T₃

T₄

T₅T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

RQ11

PRE ACT

PRE

a

ACT

b

a

b

…RQ0

t

RP

No limit

DQ15…0

DQN15…0

PAd Case (precharge-activate-different bank)

PAs Case (precharge-activate-same bank)

a: ROWP Packet with PRE, Ba

Ba ≠ Bb

a: ROWP Packet with PRE,Ba

Ba = Bb

b: ROWA Packet with ACT,Bb,Rb

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TC59YM916AMG24A,32A,32B,40B

Figure 5. ACT-, RD-, WR-, PRE-to-RD Packet Interactions

T₀

T₁

T₂

T₃

T₄

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

RQ11

ACT RD

ACT

a

RD

b

a

b

…RQ0

t

RCD-R

No limit

DQ15…0

DQN15…0

ARd Case (activate-read different bank)

ARs Case (activate-read same bank)

a: ROWA Packet with ACT,Ba,Ra

b: COL Packet with RD,Bb,Cb

a: ROWA Packet with ACT,Ba,Ra

Ba ≠ Bb

Ba = Bb

b: COL Packet with RD,Bb,Cb

T₀

T₁

T₂

T₃

T₄

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

RQ11

RD

a

RD

b

RD

a

RD

b

…RQ0

t

CC

DQ15…0

DQN15…0

RRd Case (read-read different bank)

a: COL Packet with RD, Ba, Ca

b: COL Packet with RD, Bb, Cb

RRs Case (read-read same bank)

a: COL Packet with RD, Ba, Ca

b: COL Packet with RD, Bb, Cb

Ba ≠ Bb

Ba = Bb

T₀

T₁

T₂

T₃

T₄

T₅T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

RQ11

WR

a

RD

b

WR

a

RD

b

…RQ0

t

∆WR

DQ15…0

DQN15…0

WRd Case (write-read different bank)

a: COL Packet with WR, Ba, Ca

b: COL Packet with RD, Bb, Cb

WRs Case (write-read same bank)

a: COL Packet with WR, Ba, Ca

b: COL Packet with RD, Bb, Cb

Ba ≠ Bb

Ba = Bb

T₀

T₁

T₂

T₃

T₄

T₅T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

RCD-R

RP

RQ11

PRE RD

PRE

a

ACT

B

RD

b

a

b

…RQ0

t

+ t

RCD-R

RP

No limit

DQ15…0

DQN15…0

PRd Case (precharge-read different bank)

PRs Case (precharge-read same bank)

a: ROWP Packet with PRE, Ba

Ba ≠ Bb

Ba = Bb

b: COL Packet with RD, Bb, Cb

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TC59YM916AMG24A,32A,32B,40B

Figure 6. ACT-, RD-, WR-, PRE-to-WR Packet Interactions

T₀

T₁

T₂

T₃

T₄

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

RQ11

ACT WR

ACT

a

WR

b

a

b

…RQ0

No limit

t

RCD-W

DQ15…0

DQN15…0

AWd Case (activate-write different bank)

AWs Case (activate-write same bank)

a: ROWA Packet with ACT, Ba, Ra

b: COL Packet with WR, Bb, Cb

a: ROWA Packet with ACT, Ba, Ra

Ba ≠ Bb

Ba = Bb

b: COL Packet with WR, Bb,Cb

T₀

T₁

T₂

T₃

T₄

T₅T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

∆RW

RQ11

RD

a

WR

a

RD

a

WR

b

…RQ0

t

CWD

DQ15…0

Q (a)

D (b)

Q (a)

D (b)

DQN15…0

t

CYCLE

CAC

CC

CYCLE

CAC

CC

RWd Case (read-write different bank)

a: COL Packet with RD, Ba,Ra

RWs Case (read-activate same bank)

a: COL Packet with RD, Ba, Ca

b: COL Packet with WR, Bb, Cb

Ba ≠ Bb

Ba = Bb

b: COL Packet with WR, Bb, Cb

T₀

T₁

T₂

T₃

T₄

T₅T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

RQ11

WR

a

WR

b

WR

a

WR

b

…RQ0

t

CC

DQ15…0

DQN15…0

WWd Case (write-write different bank)

a: COL Packet with WR, Ba, Ca

b: COL Packet with WR,Bb,Cb

WWs Case (write-write same bank)

a: COP Packet with WR,Ba, Ca

b: COL Packet with WR, Bb, Cb

Ba ≠ Bb

Ba = Bb

T₀

T₁

T₂

T₃

T₄

T₅T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

RCD-W

RP

RQ11

PRE WR

PRE

a

ACT

B

WR

b

a

b

…RQ0

t

+ t

RCD-W

RP

No limit

DQ15…0

DQN15…0

PWd Case (precharge-write different bank)

PWs Case (precharge-write same bank)

a: ROWP Packet with PRE, Ba

a: ROWP Packet with PRR, Ba

Ba ≠ Bb

Ba = Bb

b: COL Packet with WR, Bb,Cb

b: COP Packet with WR, Bb, Cb

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TC59YM916AMG24A,32A,32B,40B

Figure 7. ACT-, RD-, WR-, PRE-to-PRE Packet Interactions

T₀

T₁

T₂

T₃

T₄

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

RQ11

ACT PRE

ACT

a

PRE

b

a

b

…RQ0

t

RAS

No limit

DQ15…0

DQN15…0

APd Case (activate-precharge different bank)

APs Case (activate-precharge same bank)

a: ROWA Packet with ACT, Ba, Ra

Ba ≠ Bb

a: ROWA Packet with ACT, Ba, Ra

Ba = Bb

b: ROWP Packet with PRE, Bb

b: ROWP Packet with PRR, Bb

T₀

T₁

T₂

T₃

T₄

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

RQ11

RD PRE

a

RD

a

PRE

b

…RQ0

t

RDP

No limit

DQ15…0

DQN15…0

RPd Case (read-precharge different bank)

RPs Case (read-precharge same bank)

a: COL Packet with RD, Ba, Ca

Ba ≠ Bb

Ba = Bb

b: ROWP Packet with PRE, Bb

b: ROWP Packet with PRR, Bb

T₀

T₁

T₂

T₃

T₄

T₅T₆

T₇

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

RQ11

WR PRE

a

WR

a

PRE

b

…RQ0

t

WRP

No limit

DQ15…0

DQN15…0

WPd Case (write-precharge different bank)

WPs Case (write-precharge same bank)

a: COL Packet with WR, Ba, Ca

Ba ≠ Bb

Ba = Bb

b: ROWP Packet with PRE, Bb

T₀

T₁

T₂

T₃

T₄

T₅T₆

T₇

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

RAS

RP

RQ11

PRE

a

PRE

b

PRE

a

ACT

b

PRE

b

…RQ0

t

RC

PP

DQ15…0

DQN15…0

PPd Case (precharge-precharge different bank)

PPs Case (precharge-precharge same bank)

a: ROWP Packet with PRE, Ba

Ba ≠ Bb

a: ROWP Packet with PRE, Ba

Ba = Bb

b: ROWP Packet with PRE, Bb

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Dynamic Request Scheduling

Delay fields are present in the ROWA, COL, and ROWP packets. They permit the associated command to

optionally wait for a time of one (or more) t before taking effect. This allows a memory controller more

CYCLE

scheduling flexibility when issuing request packets. Figure 8 illustrates the use of the delay fields.

In the first timing diagram, a ROWA packet with an ACT command is present at cycle T . The DELA field is set

0

to “1”. This request packet will be equivalent to a ROWA packet with an ACT command at cycle T with the DELA

1

field is set to “0”. This equivalence should be used when analyzing request packet interactions.

In the second timing diagram, a COL packet with a RD command is present at cycle T . The DELC field is set to

0

“1”. This request packet will be equivalent to a COL packet with an RD command at cycle T with the DELC field is

1

set to “0”. This equivalence should be used when analyzing request packet interactions.

In a similar fashion, a COL packet with a WR command is present at cycle T . The DELC field is set to “1”. This

12

request packet will be equivalent to a COL packet with a WR command at cycle T with the DELC field is set to

13

“0”. This equivalence should be used when analyzing request packet interactions.

In the COL packet with a RD command example, the read data delay. t

CAC

is measured between the Q read data

packet and the virtual COL packet at cycle T .

1

Likewise, for the example with the COL packet with a WR command, the write data delay. t

CWD

is measured

between the D write data packet and the virtual COL packet at cycle T

.

13

In the third timing diagram, a ROWP packet with a PRE command is present at cycle T . The DEL field (POP

0

[1:0]) is set to “11”. This request packet will be equivalent to a ROWP packet with a PRE command at cycle T with

1

the DEL field is set to “10”, it will be equivalent to a ROWP packet with a PRE command at cycle T with the DEL

2

field is set to “01”, and it will be equivalent to a ROWP packet with a PRE command at cycle T with the DEL field

3

is set to “00”. This equivalence should be used when analyzing request packet interactions.

In the fourth timing diagram, a ROWP packet with a REFP command is present at cycle T . The DEL field (RA

0

[7:6]) is set to “11”. This request packet will be equivalent to a ROWP packet with a REFP command at cycle T

1

with the DEL field is set to “10”, it will be equivalent to a ROWP packet with a REFP command at cycle T with the

2

DEL field is set to “01”, and it will be equivalent to a ROWP packet with a REFP command at cycle T with the

3

DEL field is set to “00”. This equivalence should be used when analyzing request packet interactions.

The two examples for the REFA and REFI commands are identical to the example just described for the REFP

command.

The ROWP packet allows two independent operations to be specified. A PRE precharge command uses the POP

and BP fields, and the REFP, REFA, or REFI commands uses the ROP and RA fields. Both operations have an

optional delay field (the POP field for the PRE command and the RA field with the REFP, REFA, or REFI

commands). The two delay mechanisms are independent of one another. The POP field does not affect the timing of

the REFP, REFA, or REFI commands, and the RA field does not affect the timing of the PRE command.

When the interactions of a ROWP packet are analyzed, it must be remembered that there are two independent

commands specified, both of which may affect how soon the next request packet can be issued. The constraints from

both commands in a ROWP packet must be considered, and the one that requires the longer time interval to the

next request packet must be used by the memory controller. Furthermore, the two commands within a ROWP

packet may not reference the same bank in the BP and RA fields.

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Figure 8. Request Scheduling Examples

ACT w/DEL=1 at T is equivalent

0

T₀toTACT wT/DELT=0 atTT₄₁. T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

1

2

3

CFM

CFMN

t

CYCLE

RQ11

ACT ACT

DEL1 DEL0

…RQ0

DQ15…0

DQN15…0

Note: DEL value is specified by DELA field.

ROWA/ACT Command

RD w/DEL=1 at T is equivalent

0

WRM w/DEL=1 at T is equivalent

12

to RD w/DEL=0 at T .

1

to WRM w/DEL=0 at T

.

13

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

RD RD

DEL1 DEL0

WR WR

DEL1 DEL1

…RQ0

DQ15…0

Q

D

DQN15…0

t

CWD

CAC

Note: DEL value is specified by DELA field.

COL/RD and COL/WRACT Commands

PRE w/DEL=3 at T is equivalent to PRE w/DEL=2 at T

0

1

or PRE w/DEL=1 at T or REFP w/DEL=0 at T .

2

3

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

PRE PRE PRE PRE

DEL3 DEL2 DEL1 DEL0

…RQ0

DQ15…0

DQN15…0

Note: DEL value is specified by {POP1, POP0} field.

ROWP/PRE Command

REFP w/DEL=3 at T is equivalent to REFP w/DEL=2 at T

REFI w/DEL=3 at T is equivalent to REFI w/DEL=2 at T

13 14

0

1

or REFP w/DEL=1 at T or REFP w/DEL=0 at T .

or REFI w/DEL=1 at T or REFI w/DEL=0 at T

15

.

16

2

3

T₀

T₁

T₂

T₃

T₄T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

REFP REFP REFP REFP

DEL3 DEL2 DEL1 DEL0

REFA REFA REFA REFA

DEL3 DEL2 DEL1 DEL0

REFI REFI REFI REFI

DEL3 DEL2 DEL1 DEL0

…RQ0

DQ15…0

REFA w/DEL=3 at T is equivalent to REFI w/DEL=2 at T

6

7

DQN15…0

or REFI w/DEL=1 at T or PRE w/DEL=0 at T .

8

9

ROWP/REFP, REFA, REFI Commands

Note: DEL value is specified by {RA7, RA6} field.

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Memory Operations

Write Transactions

Figure 9 shows four examples of memory write transactions. A transaction is one or more request packets (and

the associated data packets) needed to perform a memory access. The state of the memory core and the address of

the memory access determine how many request packets are needed to perform the access.

The first timing diagram shows a page-hit write transaction. In this case, the selected bank is already open (a

row is already present in the sense amp array for the bank). In addition, the selected row for the memory access

matches the address of the row already sensed (a page hit). This comparison must be done in the memory controller.

In this example, the access is made to row Ra of bank Ba.

In this case, write data may be directly written into the sense amp array for the bank, and row operations

(activate or precharge) are not needed. A COL packet with WR command to column Ca1 of bank Ba is presented on

edge T , and a second COL packet with WR command to column Ca1 of bank Ba is presented on edge T . Two write

0

2

data packets D (a1) and D (a2) follow these COL packets after the write data delay t . The two COL packets are

CWD

separated by the column-cycle time t . This is also the length of each write data packet.

CC

The second timing diagram shows an example of a page-miss write transaction. In this case, the selected bank is

already open (a row is already present in the sense amp array for the bank). However, the selected row for the

memory access does not match the address of the row already sensed (a page miss). This comparison must be done

in the memory controller. In this example, the access is made to row Ra of bank Ba, and the bank contains a row

other than Ra.

In this case, write data may be not be directly written into the sense amp array for the bank. It is necessary to

close the present row (precharge) and access the requested row (activate). A precharge command (PRE to bank Ba)

is presented on edge T . An activate command (ACT to row Ra of bank Ba) is presented on edge T a time t

later.

0

6

RP

later. A second

A COL packet with WR command to column Ca1 of bank Ba is presented on edge T a time t

7

RCD-W

COL packet with WR command to column Ca2 of bank Ba is presented on edge T . Two write data packets D (a1)

9

and D (a2) follow these COL packets after the write data delay t . The two COL packets are separated by the

CWD

column-cycle time t . This is also the length of each write data packet.

CC

The third timing diagram shows an example of a page-empty write transaction. In this case, the selected bank is

already closed (no row is present in the sense amp array for the bank). No row comparison is necessary for this

case; however, the memory controller must still remember that bank Ba has been left closed. In this example, the

access is made to row Ra of bank Ba.

In this case, write data may be not be directly written into the sense amp array for the bank. It is necessary to

access the requested row (activate). An activate command (ACT to row Ra of bank Ba) is presented on edge T . A

0

COL packet with WR command to column Ca1 of bank Ba is presented on edge T a time t

later. A second

COL packet with WR command to column Ca2 of bank Ba is presented on edge T . Two write data packets D (a1)

1

RCD-W

3

and D (a2) follow these COL packets after the write data delay t . The two COL packets are separated by the

CWD

column-cycle time t . This is also the length of each write data packet. After the final write command, it may be

CC

necessary to close the present row (precharge). A precharge command (PRE to bank Ba) is presented on edge T

time t

WRP

a

14

after the last COL packet with a WR command. The decision whether to close the bank or leave it open

is made by the memory controller and its page policy.

The fourth timing diagram shows another example of a page-empty write transaction. This is similar to the

previous example except that only a single write command is presented, rather than two write commands. This

example shows that even with a minimum length write transaction, the t parameter will not be a constraint.

RAS

measures the minimum time between an activate command and a precharge command to a bank. This

The t

RAS

time interval is also constrained by the sum t

+ t

which will be larger for a write transaction. These two

) will be a function of the memory device’s speed bin and the data transfer

RCD-W

WRP

constraints (t

RAS

and t

RCD-W

+ t

WRP

length (the number of write commands issued between the activate and precharge commands), and the t

RAS

parameter could become a constraint for write transactions for future speed bins. In this example, the sum t

RCD-W

+ t

WRPs

is greater than t

RAS

by the amount ∆t .

RAS

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Figure 9. Write Transactions

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

WR

a1

WR

a2

…RQ0

t

CC

DQ15…0

D(a1)

D(a2)

DQN15…0

t

CWD

Page-hit Write Example

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

PRE

a3

ACT WR

a0 a1

WR

a2

…RQ0

t

CC

RP

RCD-W

DQ15…0

D(a1)

D(a2)

DQN15…0

t

CWD

Transaction a: WR

a0 = {Ba, Ra}

a1 = {Ba, Ca1}

a2 = {Ba, Ca2}

a3 = {Ba}

Page-miss Write Example

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

ACT WR

a0 a1

WR

a2

PRE

a3

…RQ0

t

WRP

t

RCD-W

CC

DQ15…0

D(a1)

D(a2)

DQN15…0

t

DP

CWD

Transaction a: WR

a0 = {Ba, Ra}

a1 = {Ba, Ca1}

a2 = {Ba, Ca2}

a3 = {Ba}

Page-empty Write Example

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

∆t

RAS

t

RP

RAS

t

CYCLE

RQ11

ACT WR

a0 a1

PRE

a3

ACT

b0

…RQ0

t

WRP

t

RCD-W

DQ15…0

D(a1)

DQN15…0

t

DP

CWD

Transaction a: WR

Transaction b: WR

a0 = {Ba, Ra}

b0 = {Bb, Rb}

a1 = {Ba, Ca1}

b1 = {Bb, Cb1}

a2 = {Ba, Ca2}

b2 = {Bb, Cb2}

a3 = {Ba}

b3 = {Bb}

Bb=Ba

Page-empty Write Example – Core Limited

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Read Transactions

Figure 10 shows four examples of memory read transactions. A transaction is one or more request packets (and

the associated data packets) needed to perform a memory access. The state of the memory core and the address of

the memory access determine how many request packets are needed to perform the access.

The first timing diagram shows a page-hit read transaction. In this case, the selected bank is already open (a row

is already present in the sense amp array for the bank). In addition, the selected row for the memory access

matches the address of the row already sensed (a page hit). This comparison must be done in the memory controller.

In this example, the access is made to row Ra of bank Ba.

In this case, read data may be directly read from the sense amp array for the bank, and no row operations

(activate or precharge) are needed. A COL packet with RD command to column Ca1 of bank Ba is presented on

edge T , and a second COL packet with RD command to column Ca2 of bank Ba is presented on edge T . Two read

0

2

data packets Q (a1) and Q (a2) follow these COL packets after the read data delay t . The two COL packets are

CAC

separated by the column-cycle time t . This is also the length of each read data packet.

CC

The second timing diagram shows an example of a page-miss read transaction. In this case, the selected bank is

already open (a row is already present in the sense amp array for the bank). However, the selected row for the

memory access does not match the address of the row already sensed (a page miss). This comparison must be done

in the memory controller. In this example, the access is made to row Ra of bank Ba, and the bank contains a row

other than Ra.

In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to close the

present row (precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is

presented on edge T . An activate command (ACT to row Ra of bank Ba) is presented on edge T a time t

later.

RP

later. A second

0

6

A COL packet with RD command to column Ca1 of bank Ba is presented on edge T a time t

11

RCD-R

COL packet with RD command to column Ca2 of bank Ba is presented on edge T . Two read data packets Q(a1)

13

and Q(a2) follow these COL packets after the read data delay t . The two COL packets are separated by the

CAC

column-cycle time t . This is also the length of each read data packet.

CC

The third timing diagram shows an example of a page-empty write transaction. In this case, the selected bank is

already closed (no row is present in the sense amp array for the bank). No row comparison is necessary for this

case; however, the memory controller must still remember that bank Ba has been left closed. In this example, the

access is made to row Ra of bank Ba.

In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to access

the requested row (activate). An activate command (ACT to row Ra of bank Ba) is presented on edge T . A COL

0

packet with RD command to column Ca1 of bank Ba is presented on edge T a time t

later. A second COL

packet with RD command to column Ca2 of bank Ba is presented on edge T . Two read data packets Q (a1) and Q

5

RCD-R

7

(a2) follow these COL packets after the read data delay t . The two COL packets are separated by the

CAC

column-cycle time t . This is also the length of each read data packet. After the final read command, it may be

CC

necessary to close the present row (precharge). A precharge command — PRE to bank Ba — is presented on edge

T

10

a time t after the last COL packet with a RD command. Whether the bank is closed or left open depends on

RDP

the memory controller and its page policy.

The fourth timing diagram shows another example of a page-empty read transaction. This is similar to the

previous example except that it uses one read command instead of two read commands. In this case, the core

parameter t

may also be a constraint upon when the precharge command may be issued.

RAS

The t

RAS

measures the minimum time between an activate command and a precharge command to a bank. This

time interval is also constrained by the sum t

+ t

and must be set to whichever is larger. These two

) will be a function of the memory device’s speed bin and the data transfer

RCD-R

RDP

constraints (t

RAS

and t

RCD-R

+ t

RDP

length (the number of read commands issued between the activate and precharge commands). In this example, the

is greater than the sum t + t by the amount ∆t

t

.

RAS

RCD-R RDP RDP

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Figure 10. Read Transactions

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

RD

a1

RD

a2

…RQ0

t

CC

DQ15…0

Q(a1)

Q(a2)

DQN15…0

t

CAC

Transaction a: RD

a0 = {Ba, Ra}

a1 = {Ba, Ca1}

a2 = {Ba, Ca2}

a3 = {Ba}

Page-hit Read Example

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

PRE

a3

ACT

a0

RD

a1

RD

a2

…RQ0

t

CC

RP

RCD-R

DQ15…0

Q(a1)

Q(a2)

DQN15…0

t

CAC

Transaction a: RD

a0 = {Ba, Ra}

a1 = {Ba, Ca1}

a2 = {Ba, Ca2}

a3 = {Ba}

Page-miss Read Example

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

ACT

a0

RD

a1

RD

a2

PRE

a3

…RQ0

t

RDP

RCD-R

CC

DQ15…0

Q(a1)

Q(a2)

DQN15…0

t

CAC

Transaction a: RD

a0 = {Ba, Ra}

a1 = {Ba, Ca1}

a2 = {Ba, Ca2}

a3 = {Ba}

Page-empty Read Example

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

RP

RAS

t

CYCLE

RQ11

ACT

a0

RD

a1

PRE

a3

ACT

b0

…RQ0

t

RCD-R

t

RDP

∆t

RDP

DQ15…0

Q(a1)

DQN15…0

t

CAC

Transaction a: RD

Transaction b: RD

a0 = {Ba, Ra}

b0 = {Bb, Rb}

a1 = {Ba, Ca1}

b1 = {Bb, Cb1}

a2 = {Ba, Ca2}

b2 = {Bb, Cb2}

a3 = {Ba}

b3 = {Bb}

Bb=Ba

Page-empty Read Example – Core Limited

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TC59YM916AMG24A,32A,32B,40B

Interleaved Transactions

Figure 11 shows two examples of interleaved transactions. Interleaved transactions are overlapped with one

another; a transaction is started before an earlier one is completed.

The timing diagram at the top of the figure shows interleaved write transactions. Each transaction assumes a

page-empty access; that is, a bank is in a closed state prior to an access, and is precharged after the access. With

this assumption, each transaction requires the same number of request packets at the same relative positions. If

banks were allowed to be in an open state, then each transaction would require a different number of request

packets depending upon whether the transaction was page-empty, page-hit, or page-miss. This situation is more

complicated for the memory controller, and will not be analyzed in this document.

In the interleaved page-empty write example, there are four sets of request pins RQ11…RQ0 shown along the left

side of the timing diagram. The first three show the timing slots used by each of the three requests packet types

(ACT, COL and PRE), and the fourth set (ALL) shows the previous three merged together. This allows the pattern

used for allocating request slots for the different packets to be seen more clearly.

The slots at {T , T , T , T , ...} are used for ROWA packets with ACT commands. This spacing is determined by

12

0

4

8

the t

RR

parameter. There should not be interference between the interleaved transactions due to resource conflicts

because each bank address — Ba, Bb, Bc, Bd, and Be — is assumed to be different from another. If two of the bank

addresses are the same, the later transaction would need to wait until the earlier transaction had completed its

precharge operation. Five different banks are needed because the effective t

(t

+ ∆t ) is 20 × t .

RC CYCLE

RC RC

The slots at {T , T , T , T , T , T , ...} are used for COL packets with WR commands. This frequency of the COL

11

1

3

5

7

9

packet spacing is determined by the t

parameter and by the fact that there are two column accesses per row

CC

access. The phasing of the COL packet spacing is determined by the t

parameter. If the value of t

RCD-W

required the COL packets to occupy the same request slots as the ROWA packets (this case is not shown), the

DELC field in the COL packet could be used to place the COL packet one t earlier.

CYCLE

The DQ bus slots at {T , T , T , T , ...} carry the write data packets { D (a1), D (a2), D (b1), D (b2), .... }. Two

7

9

11 13

write data packets are written to a bank in each transaction. The DQ bus is completely filled with write data; no

idle cycles need to be introduced because there are no resource conflicts in this example.

The slots at {T , T , T , ...} are used for ROWP packets with PRE commands. This frequency of ROWP packet

14 18 22

spacing is determined by the t parameter. The phasing of the ROWP packet spacing is determined by the t

PP

WRP

required the ROWP packets to occupy the same request slots as the ROWA or COL

parameter. If the value of t

WRP

packets already assigned (this case is not shown), the delay field in the ROWP packet could be used to place the

ROWP packet one or more t earlier.

CYCLE

There is an example of an interleaved page-empty read at the bottom of the figure. As before, there are four sets

of request pins RQ11…RQ0 shown along the left side of the timing diagram, allowing the pattern used for

allocating request slots for the different packets to be seen more clearly.

The slots at {T , T , T , T , ...} are used for ROWA packets with ACT commands. This spacing is determined by

12

0

4

8

the t

RR

parameter. There should not be interference between the interleaved transactions due to resource conflicts

because each bank address — Ba, Bb, Bc, and Bd — is assumed to be different from another. Four different banks

are needed because the effective t is 16 × t

.

RC CYCLE

The slots at {T , T , T , T , ...} are used for COL packets with RD commands. This frequency of the COL packet

11

5

7

9

spacing is determined by the t

CC

phasing of the COL packet spacing is determined by the t

RCD-R

parameter and by the fact that there are two column accesses per row access. The

parameter. If the value of t required the

RCD-R

COL packets to occupy the same request slots as the ROWA packets (this case is not shown), the DELC field in the

COL packet could be used to place the packet one t earlier.

CYCLE

The DQ bus slots at {T , T , T , T , ...} carry the read data packets { Q (a1), Q (a2), Q (b1), Q (b2), ...}. Two

11 13 15 17

read data packets are read from a bank in each transaction. The DQ bus is completely filled with read data — that

is, no idle cycles need to be introduced because there are no resource conflicts in this example.

The slots at {T , T , T , T , ...} are used for ROWP packets with PRE commands. This frequency of the

10 14 18 22

ROWP packet spacing is determined by the t parameter. The phasing of the ROWP packet spacing is determined

PP

by the t

RDP

parameter. If the value of t required the ROWP packets to occupy the same request slots as the

RDP

ROWA or COL packets already assigned (this case is not shown), the delay field in the ROWP packet could be used

to place the ROWP packet one or more t earlier.

CYCLE

2003-07-10 26/74

TC59YM916AMG24A,32A,32B,40B

Figure 11. Interleaved Transactions

The effective t

time is increased by 4 t .

CYCLE

RC

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

∆RC

RC

t

CYCLE

RQ11…RQ0

(ACT)

ACT

a0

ACT

b0

ACT

c0

ACT

d0

ACT

e0

ACT

f0

t

RR

RQ11…RQ0

(COL)

WR

a1

WR

a2

WR

b1

WR

b2

WR

c1

WR

c2

WR

d1

WR

d2

WR

e1

WR

e2

WR

f1

WR

f2

t

CC

t

RCD-W

DQ15…0

D(a1)

D(a2)

D(b1)

WRP

D(b2)

D(c1)

t

D(c2)

D(d1)

D(d2)

D(e1)

DQN15…0

t

∆WRP

RP

t

CWD

RQ11…RQ0

(PRE)

PRE

a3

PRE

b3

PRE

c3

RQ11…RQ0

(ALL)

ACT WR

a0 a1

WR ACT WR

a2 b0 b1

WR ACT WR

b2 c0 c1

WR ACT WR PRE WR ACT WR PRE WR ACT WR PRE WR

c2 d0 d1 a3 d2 c0 e1 b3 e2 f0 f1 c3 f2

Transaction a: WR

Transaction b: WR

Transaction c: WR

Transaction d: WR

Transaction e: WR

Transaction f: WR

a0 = {Ba, Ra}

b0 = {Bb, Rb}

c0 = {Bc, Rc}

d0 = {Bd, Rd}

e0 = {Be, Re}

f0 = {Bf, Rf}

a1 = {Ba, Ca1}

b1 = {Bb, Cb1}

c1 = {Bc, Cc1}

d1 = {Bd, Cd1}

e1 = {Be, Ce1}

f1 = {Bf, Cf1}

a2 = {Ba, Ca2}

b2 = {Bb, Cb2}

c2 = {Bc, Cc2}

d2 = {Bd, Cd2}

e2 = {Be, Ce2}

f2 = {Bf, Cf2}

a3 = {Ba}

b3 = {Bb}

c3 = {Bc}

d3 = {Bd}

e3 = {Be}

f3 = {Bf}

Ba,Bb,Bc,Bd,Be

are different

banks.

Bf = Ba

Interleaved Page-empty Write Example

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

RC

t

CYCLE

RQ11…RQ0

(ACT)

ACT

a0

ACT

b0

ACT

c0

ACT

d0

ACT

e0

ACT

f0

t

RR

RQ11…RQ0

(COL)

RD

a1

RD

a2

RD

b1

RD

b2

RD

c1

RD

c2

RD

d1

RD

d2

RD

e1

RD

e2

t

CAC

RCD-R

DQ15…0

Q(a1)

Q(a2)

Q(b1)

Q(b2)

Q(c1)

Q(c2)

DQN15…0

t

RDP

t

RP

CC

RQ11…RQ0

(PRE)

PRE

a3

PRE

b3

PRE

c3

PRE

d3

RQ11…RQ0

(ALL)

ACT

a0

ACT RD

b0 a1

RD ACT RD PRE RD ACT RD PRE RD ACT RD PRE RD ACT RD PRE RD

a2 c0 b1 a3 b2 d0 c1 b3 c2 e0 d1 c3 d2 f0 e1 d3 e2

Transaction a: RD

Transaction b: RD

Transaction c: RD

Transaction d: RD

Transaction e: RD

a0 = {Ba, Ra}

a1 = {Ba, Ca1}

b1 = {Bb, Cb1}

c1 = {Bc, Cc1}

d1 = {Bd, Cd1}

e1 = {Be, Ce1}

a2 = {Ba, Ca2}

b2 = {Bb, Cb2}

c2 = {Bc, Cc2}

d2 = {Bd, Cd2}

e2 = {Be, Ce2}

a3 = {Ba}

b3 = {Bb}

c3 = {Bc}

d3 = {Bd}

e3 = {Be}

b0 = {Bb, Rb}

c0 = {Bc, Rc}

d0 = {Bd, Rd}

e0 = {Be, Re}

Ba,Bb,Bc,Bd

are different

banks.

Be = Ba

Interleaved Page-empty Read Example

2003-07-10 27/74

TC59YM916AMG24A,32A,32B,40B

Read/Write Interaction

The previous section described overlapped read transactions and overlapped write transactions in isolation. This

section will describe the interaction of read and write transactions and the spacing required to avoid channel and

core resource conflicts.

Figure 12 shows a timing diagram (top) for the first case, a write transaction followed by a read transaction. Two

COL packets with WR commands are presented on cycles T and T . The write data packets are presented a time

0

2

t

later on cycles T and T . The device requires a time t after the second COL packet with a WR command

WR

∆

CWD

4

6

before a COL packet with a RD command may be presented. Two COL packets with RD commands are presented

on cycles T and T . The read data packets are returned a time t later on cycles T and T . The time t

11 13 CAC 17 19

WR

∆

is required for turning around internal bi-directional interconnections (inside the device). This time must be

observed regardless of whether the write and read commands are directed to the same bank or different banks. A

gap t will appear on the DQ bus between the end of the D (a2) packet and the beginning of the

WR-BUB, XDR DRAM

Q (b1) packet (measured at the appropriate packet reference points). The size of this gap can be evaluated by

calculating the difference between cycles T and T using the two timing paths:

2

17

t

= t

+ t

CAC

− t

WR-BUB, XDR DRAM

WR

∆

CWD

CC

In this example, the value of t

WR-BUB, XDR DRAM

is greater than its minimum value of t

WR-BUB, XDR DRAM,

. The values of t

, t

, and t

are equal to their minimum values.

MIN

RW CAC CWD CC

∆

In the second case, the timing diagram displayed at the bottom of Figure 12 illustrates a read transaction followed

by a write transaction. Two COL packets with RD commands are presented on cycles T and T . The read data

0

2

packets are returned a time t

CAC

later on cycles T and T . The device requires a time t after the second COL

RW

∆

6

8

packet with a RD command before a COL packet with a WR command may be presented. Two COL packets with

WR commands are presented on cycles T and T . The write data packets are presented a time t later on

10 12 CWD

cycles T and T . The time t

13 15

is required for turning around the external DQ bi-directional interconnections

RW

∆

(outside the device). This time must be observed regardless whether the read and write commands are directed to

the same bank or different banks. The time t depends upon four timing parameters, and may be evaluated by

RW

∆

calculating the difference between cycles T and T using the two timing paths:

11

2

t

+ t

CWD

= t

+ t

CC

+ t

RW-BUB, XDR DRAM

RW

CAC

∆

or

t

= (t

CAC

− t

) + t

CWD CC

+ t

RW-BUB, XDR DRAM

RW

In this example, the values of t

, t

, t , and t t

WR-BUB, XDR DRAM

are equal to their minimum

RW CAC CWD CC

∆

values.

2003-07-10 28/74

TC59YM916AMG24A,32A,32B,40B

Figure 12. Write/Read Interaction

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

WR

a1

WR

a2

RD

b1

RD

b2

…RQ0

t

CAC

∆WR

DQ15…0

D(a1)

D(a2)

Q(b1)

Q(b2)

DQN15…0

t

CWD

t

CC

t

WR-BUB, XDR DRAM

t

DR

Transaction a: WR

Transaction b: RD

a0 = {Ba, Ra}

b0 = {Bb, Rb}

a1 = {Ba, Ca1}

b1 = {Bb, Cb1}

a2 = {Ba, Ca2}

b2 = {Bb, Cb2}

a3 = {Ba}

b3 = {Bb}

Write/Read Turnaround Example

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

WR

b1

WR

b2

RD

a1

RD

a2

…RQ0

t

∆RW

CWD

DQ15…0

Q(a1)

Q(a2)

D(b1)

D(b2)

DQN15…0

t

RW-BUB,XDR DRAM

CAC

CC

Transaction a: RD

Transaction b: WR

a0 = {Ba, Ra}

b0 = {Bb, Rb}

a1 = {Ba, Ca1}

b1 = {Bb, Cb1}

a2 = {Ba, Ca2}

b2 = {Bb, Cb2}

a3 = {Ba}

b3 = {Bb}

Read/Write Turnaround Example

2003-07-10 29/74

TC59YM916AMG24A,32A,32B,40B

Propagation Delay

Figure 13 shows two timing diagrams that display the system-level timing relationships between the memory

component and the memory controller.

The timing diagram at the top of the figure shows the case of a write-read-write command and data at the

memory component. In this case, the timing will be identical to what has already been shown in the previous

sections; i.e. with all timing measured at the pins of the memory component. This timing diagram was produced by

merging portions of the top and bottom timing diagrams in Figure 12.

The example shown is that of a single COL packet with a write command, followed by a single COL packet with a

read command, followed by a second COL packet with a write command. These accesses all assume a page-hit to an

open bank.

A timing interval t

is required between the first WR command and the RD command, and a timing interval

WR

∆

t

∆

is required between the RD command and the second WR command. There is a write data delay t

CWD

RW

between each WR command and the associated write data packet D. There is a read data delay t

CAC

between the

RD command and the associated read data packet Q. In this example, all timing parameters have assumed their

minimum values except t

.

WR-BUB, XDR DRAM

The lower timing diagram in the figure shows the case where timing skew is present between the memory

controller and the memory component. This skew is the result of the propagation delay of signal wavefronts on the

wires carrying the signals.

The example in the lower diagram assumes that there is a propagation delay of t

PD-RQ

along both the RQ wires

and the CFM/CFMN clock wires between the memory controller and the memory component (the value of t

PD-RQ

used here is 1*t ). Note that in an actual system the t value will be different for each memory

CYCLE PD-RQ

component connected to the RQ wires.

In addition, it is assumed that there is a propagation delay t

along the DQ/DQN wires between the memory

PD-D

controller and the memory component (the direction in which write data travels, and it is assumed that there is the

same propagation delay t along the DQ/DQN wires between the memory component and the memory

PD-Q

controller (the direction in which read data travels). The sum of these two propagation delays is also denoted by the

timing parameter t = t + t

.

PD,CYC PD-D PD-Q

As a result of these propagation delays, the position of packets will have timing skews that depend upon whether

they are measured at the pins of the memory controller or the pins of the memory component. For example, the

CFM/CFMN signals at the pins of the memory component are t

PD-RQ

later than at the pins of the memory

controller. This is shown by the cycle numbering of the CFM/CFMN signals at the two locations — in this example

cycle T at the memory controller aligns with cycle T at the memory component.

1

0

All the request packets on the RQ wires will have a t

PD-RQ

skew at the memory component relative to the

memory controller in this example. Because the t

propagation delay of write data matches the t

PD-RQ

PD-D

propagation delay of the write command, the controller may issue the write data packet D(a0) relative to the COL

packet with the first write command “WR a0” with the normal write data delay t . If the propagation delays

CWD

between the memory controller and memory component were different for the RQ and DQ buses (not shown in this

example), the write data delay at the memory controller would need to be adjusted.

A propagation delay is seen by the read command — that is, the read command will be delayed by a t

skew

at the memory component relative to the memory controller. The memory component will return the read data

PD-RQ

packet Q(b0) relative to this read command with the normal read data delay t

component).

(at the pins of the memory

CAC

The read data packet will be skewed by an additional propagation delay of t

as it travels from the memory

PD-Q

component back to the memory controller. The effective read data delay measured between the read command and

the read data at the memory controller will be t + t + t

.

CAC PD-RQ PD-Q

The t

factor is caused by the propagation delay of the request packets as they travel from memory

factor is caused by the propagation delay of the read data packets as

they travel from memory component to memory controller.

PD-RQ

controller to memory component. The t

PD-Q

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TC59YM916AMG24A,32A,32B,40B

Propagation Delay (continue)

All timing parameters will be equal to their minimum values except t

(as in the top diagram),

. These will be larger than their minimum values by the

WR-BUB, XDR DRAM

and the timing parameters t

RW-BUB, XDR DRAM

and t

RW

∆

amount (t

-t

), where t = t

+ t . This may be seen by evaluating the two timing

PD-Q

PD,CYC PD,CYC,MIN

PD,CYC

PD-D

paths between cycle T at the Controller and cycle T 1at the XDR DRAM:

9

2

t

∆

+ t

= t

+ t

+ t + t

CC RW-BUB, XDR DRAM

RW

PD-RQ CWD

PD-RQ CAC

or

t

∆

= (t

- t

) + t + t

CC RW-BUB,XDR DRAM

RW

CAC CWD

The following relationship was shown for Figure 12.

t

∆

= (t

- t

)+ t + t

CC RW-BUB, XDR DRAM,MIN

RW, MIN

CAC CWD

or

(t

∆

- t

) = (t

- t

)

RW

RW, MIN

∆

RW-BUB, XDR DRAM RW-BUB, XDR DRAM,MIN

In other words, the two timing parameters t

RW-BUB, XDR DRAM

and t

will change together. The relationship

RW

∆

of this change to the propagation delay t

PD,CYC

( = t

+ t

) can be derived by looking at the two timing

PD-D PD-Q

paths from T to T at the XDR DRAM:

15

21

t

+ t + t

+ t

PD-D

= t + t

CC RW-BUB,XDR DRAM

PD-Q

CC

RW-BUB,YRAC

or

= t

+ t + t

PD-D PD-Q

RW-BUB, XDR DRAM

RW-BUB,YRAC

+ t

RW-BUB,YRAC

PD,CYC

in a system with minimum propagation delays:

= t

t

+ t

PD,CYC,MIN

RW-BUB,XDR DRAM,MIN

RW-BUB,YRAC

and since t

is equal to t

in both cases, the following is true:

) = (t - t ) =

RW,MIN

∆

RW-BUB,YRAC

RW-BUB,YRAC,MIN

(t

PD,CYC PD,CYC,MIN

- t

) = (t

- t

RW-BUB,XDR DRAM RW-BUB,XDR DRAM,MIN

RW

∆

In other words, the values of the t and t timing parameters correspond to the

RW-BUB,XDR DRAM,MIN

RW,MIN

∆

value of t

for the system (this is equal to one t

). As t is increased from this minimum

PD,CYC

PD,CYC,MIN

CYCLE

increase from their minimum values by an equivalent amount.

value, t

and t

RW

∆

RW-BUB,XDR DRAM

2003-07-10 31/74

TC59YM916AMG24A,32A,32B,40B

Figure 13. Propagation Delay

XDR DRAM

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

WR

a0

RD

b0

WR

c0

…RQ0

t

CWD

∆WR

∆RW

DQ15…0

D(a0)

Q(b1)

D(c1)

t

DQN15…0

CAC

t

CWD

CC

RW-BUB,XDR DRAM

WR-BUB,XDR DRAM

Transaction a: WR

Transaction b: RD

Transaction c: WR

a0 = {Ba, Ca0}

b0 = {Bb, Cb0}

c0 = {Bc, Cc0}

Write-Read-Write at XDR DRAM

(portions of top and bottom timing diagrams of Figure 12 merged)

Controller

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

t

∆RW

RQ11

WR

a0

RD

b0

WR

c0

…RQ0

t

CC

RW-BUB,YRAC

∆WR

DQ15…0

D(a0)

Q(b0)

D(c0)

DQN15…0

t

PD-Q

XDR DRAM

T_-1T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂

CFM

CFMN

t

PD-D

PD-RQ

t

CYCLE

RQ11

WR

a0

RD

b0

WR

c0

…RQ0

t

PD-D

t

CWD

PD-RQ

DQ15…0

D(a0)

Q(b0)

D(c0)

DQN15…0

t

CWD

t

RW-BUB,XDR DRAM

CAC

CC

Transaction a: WR

Transaction b: RD

Transaction c: WR

a0 = {Ba, Ca0}

b0 = {Bb, Cb0}

c0 = {Bc, Cc0}

Write-Read-Write at Controller and XDR DRAM

w/t = t = t = 1*t

CYCLE

PD-RQ

PD-Q

PD-D

t

PD-RQ

RQ

DQ

Controller

RQ

DQ

t

PD-D

XDR DRAM

t

PD-Q

2003-07-10 32/74

TC59YM916AMG24A,32A,32B,40B

Register Operations

Serial Transactions

The serial interface consists of five pins. This includes RST, SCK, CMD, SDI, and SDO. SDO uses CMOS

signaling levels. The other four pins use RSL signaling levels. RST, CMD, SDI, and SDO use a timing window,

which surrounds the falling edge of SCK). The RST pin is used for initialization.

Figure 14 and Figure 15 show examples of a serial write transaction and a serial read transaction. Each

transaction starts on cycle S and requires 32 SCK edges. The next serial transaction can begin on cycle S . SCK

4

36

does not need to be asserted if there is no transaction.

Serial Write Transaction

The serial device write transaction in Figure 14 begins with the Start [3:0] field. This consists of bits “1100” on

the CMD pin. This indicates to the XDR DRAM that the remaining 28 bits constitute a serial transaction.

The next two bits are the SCMD [1:0] field. This field contains the serial command, the bits 00 in the case of a

serial device write transaction.

The next eight bits are “00” and the SID [5:0] field. This field contains the serial identification of the device being

accessed.

The next eight bits are the SADR [7:0] field. This field contains the serial address of the control register being

accessed.

A single bit “0” follows next. This bit allows one cycle for the access time to the control register.

The next eight bits on the CMD pin is the SWD [7:0] field. This is the write data that is placed into the selected

control register.

A final bit “0” is driven on the CMD pin to finish the serial write transaction.

A serial broadcast write is identical except that the contents of the SID [5:0] field in the transaction is ignored

and all devices perform the register write. The SDI and SDO pins are not used during either serial write

transaction.

Serial Read Transaction

The serial device read transaction in Figure 15 begins with the Start [3:0] field. This consists of bits “1100” on the

CMD pin. This indicates that the remaining 28 bits constitute a serial transaction.

The next two bits are the SCMD [1:0] field. This field contains the serial command, and the bits “10” in the case of

a serial device read transaction.

The next eight bits are “00” and the SID [5:0] field. This field contains the serial identification of the device being

accessed.

The next eight bits are the SADR [7:0] field and contain the serial address of the control register being accessed.

A single bit “0” follows next. This bit allows one cycle for the access time to the control register and time to turn

on the SDO output driver.

The next eight bits on the CMD pin are the sequence “00000000”. At the same time, the eight bits on the SDO pin

are the SRD [7:0] field. This is the read data that is accessed from the selected control register. Note the output

timing convention here: bit SRD [7] is driven from a time t

Q, SI, MAX

after edge S to a time t after edge

26 Q, SI, MIN

S

. The bit is sampled in the controller by the edge S

27 27

.

A final bit “0” is driven on the CMD pin to finish the serial read transaction.

A serial forced read is identical except that the contents of the SID [5:0] field in the transaction is ignored and all

devices perform the register read. This is used for device testing.

Figure 16 shows the response of a DRAM to a serial device read transaction when its internal SID [5:0] register

field doesn’t match the SID [5:0] field of the transaction. Instead of driving read data from an internal register for

cycle edges S through S on the SDO output pin, it passes the input data from the SDI input pin to the SDO

27 34

output pin during this same period.

Table 8. SCMD Field Encoding Summary

SCMD

Command

[1:0]

DESCRIPTION

00

01

SDW

SBW

Serial device write-one device is written, the one whose SID[5:0] register matches the SID [5:0] filed of the transaction.

Serial broadcast write – all devices are written, regardless of the contents of the SID [5:0] register and the SID [5:0] transaction

field.

10

11

SDR

SFR

Serial device read – one device is read, the one whose SID[5:0] register matches the SID [5:0] field of the transaction.

Serial forced read – all devices are read, regardless of the contents of the SID [5:0] register and the SID [5:0] transaction field.

2003-07-10 33/74

TC59YM916AMG24A,32A,32B,40B

Figure 14. Serial Write Transaction

S₀

S₂

S₄S₆

S₈S₁₀S₁₂S₁₄S₁₆S₁₈S₂₀S₂₂S₂₄S₂₆S₂₈S₃₀S₃₂S₃₄S₃₆S₃₈S₄₀S₄₂S₄₄

S₄₆

S₄₈

SCK

RST

t

CYC,SCK

transaction

SCMD

Start

’1’ ’1’ ’0’ ’0’

2’h0, SID[5:0]

’0’ ’0’ 5

SADR [7:0]

SWD [7:0]

CMD

’0’ ’0’

4

3

2

1

0

7 6 5 4 3 2 1 0 ‘0' 7 6 5 4 3 2 1 0 ‘0'

SDI

(input)

SDO

(output)

Figure 15. Serial Read Transaction – Selected DRAM

S₀S₂

S₄S₆

S₈S₁₀S₁₂S₁₄S₁₆S₁₈S₂₀S₂₂S₂₄S₂₆S₂₈S₃₀S₃₂S₃₄S₃₆S₃₈S₄₀S₄₂S₄₄

S₄₆

S₄₈

SCK

RST

t

CYC,SCK

transaction

SCMD

Start

’1’ ’1’ ’0’ ’0’

2’h0, SID[5:0]

’0’ ’0’ 5 3 2

SADR [7:0]

7 6 5 4

8’h00

CMD

’1’ ’0’

4

1

0

3

2

1 0 ‘0' ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0'

SDI

(input)

SDO

SRD [7:0]

(output)

7

6 5 4 3 2 1 0

Figure 16. Serial Read Transaction – Non-Selected DRAM

S₀

S₂

S₄S₆

S₈S₁₀S₁₂S₁₄S₁₆S₁₈S₂₀S₂₂S₂₄S₂₆S₂₈S₃₀S₃₂S₃₄S₃₆S₃₈S₄₀S₄₂S₄₄

S₄₆

S₄₈

SCK

RST

t

CYC,SCK

S₂₈

transaction

SDI

SCMD

Start

’1’ ’1’ ’0’ ’0’

2’h0, SID[5:0]

’0’ ’0’ 5 3 2

SADR [7:0]

8’h00

CMD

t

P,SI

’0’ ’0’

4

1

0

7 6

5

4

3

2

1 0 ‘0' ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0'

SDO

SDI

(input)

SRD [7:0]

7

6 5 4 3 2 1 0

combinational

propagation from

SDI to SDO

SDO

(output)

SRD [7:0]

7 6 5 4 2 1 0

3

2003-07-10 34/74

TC59YM916AMG24A,32A,32B,40B

Register Summary

Figure 17 through Figure 40 show the control registers in the memory component. The control registers are

responsible for configuring the component’s operating mode, for managing power state transitions, for managing

refresh, and for managing calibration operations.

A control register may contain up to eight bits. Each figure shows defined bits in white and reserved bits in gray.

Reserved bits must be written as 0 and must be ignored when read. Write-only fields must be ignored when read

Each figure displays the following register information:

1. Register name

2. Register mnemonic

3. Register address (SADR [7:0] value needed to access it)

4. Read-only, write-only or read-write

5. Initialization state

6. Description of each defined register field

Figure 17 shows the Serial Identification register. This register contains the SID [5:0] (serial identification field).

This field contains the serial identification value for the device. The value is compared to the SID [5:0] field of a

serial transaction to determine if the serial transaction is directed to this device. The serial identification value is

set during the initialization sequence.

Figure 18 shows the Configuration Register. It contains three fields. The first is the WIDTH field. This field

allows the number of DQ/DQN pins used for memory read and write accesses to be adjusted. The SLE field enables

data to be written into the memory through the serial interface using the WDSL register.

Figure 19 shows the Power Management Register. It contains two fields. The first is the PX field. When this field

is written with a 1, the memory component transitions from powerdown to active state. It is usually unnecessary to

write a 0 into this field; this is done automatically by the PDN command in a COLX packet. The PST field indicates

the current power state of the memory component.

Figure 20 shows the Write Data Serial Load Register. It permits data to be written into memory via the Serial

Interface.

Figure 23 shows the Refresh Bank Control Register. It contains two fields: BANK and MBR. The BANK field is

read-write and contains the bank address used by self-refresh during the powerdown state. The MBR field controls

how many banks are refreshed during each refresh operation. Figure 24, Figure 25 and Figure 26 show different

fields of the Refresh Row Register (high, middle, and low). This read-write field contains the row address used by

self- and auto-refresh. See “Refresh Transactions” on page 40 for more details.

Figure 27 and Figure 28 show the Current Calibration 0 and 1 registers. They contain the CCVALUE0 and

CCVALUE1 fields, respectively. These are read-write fields which control the amount of IOL current driven by the

DQ and DQN pins during a read transaction. The Current Calibration 0 Register controls the even-numbered DQ

and DQN pins, and the Current Calibration 1 controls the odd-numbered DQ and DQN pins.

Figure 29 and Figure 30 shows the Impedance Calibration 0 and 1 registers. They contain the ZCVALUE0 and

ZCVALUE1 fields, respectively. These are read-write fields that control the impedance of the on-chip termination

components in the DQ and DQN pins. The Impedance Calibration 0 Register controls the even-numbered DQ and

DQN pins, and the Impedance Calibration 1 controls the odd-numbered DQ and DQN pins.

Figure 33 through Figure 39 shows the test registers. This includes the TEST, DLL, PLL0, PLL1, IFT, DA, and

PART registers. These are used during device testing. They are not to be read or written during normal operation.

Figure 40 shows the DLY register. This is used to set the value of t

“Timing Parameters” on page 60.

and t

CWD

used by the component. See

CAC

2003-07-10 35/74

TC59YM916AMG24A,32A,32B,40B

Figure 17. Serial Identification (SID) Register

Serial Identification Register

SADR [7:0]: 00000001

Read-only register

SID [7:0] resets to 00000000

7

6

5

4

3

2

1

0

2

reserved

SID [5:0]

SID [5:0] - Serial Identification field.

This field contains the serial identification value for the device.

The value is compared to the SID [5:0] field of a serial transaction

to determine if the serial transaction is directed to this device. The

serial identification value is set during the initialization sequence.

Figure 18. Configuration (CFG) Register

Configuration Register

SADR [7:0]: 00000010

Read/write register

CFG [7:0] resets to 00000100

7

6

5

4

3

2

1

0

2

SP [1:0]

rsrv

SLE

rsrv

WIDTH [2:0]

WIDTH [2:0] - Device interface width field.

000 - Reserved

2

001 - Reserved

2

010 - ×4 device width

2

011 - ×8 device width

2

100 - ×16 device width

2

101 , 110 , 111 - Reserved

2

SLE - Serial Load enable field.

0 - WDSL-path-to-memory disabled

2

1 - WDSL-path-to-memory enabled

2

SP [1:0] - Sub-page activation field

00 - Full-page activation

2

10 - Reserved

2

01 - Reserved

2

11 - Reserved

2

Figure 19. Power Management (PM) Register

Power Management Register

SADR [7:0]: 00000011

Read/write register

PM [7:0] resets to 00000000

7

6

5

4

3

2

1

0

2

PST [1:0]

reserved

PX

PX - Power down exit field. (write-one-only read = zero)

0 - Power down entry do not write zero – use PDN command.

2

1 - Power down exit – write one to exit

2

PST [1:0] - Power state field (read-only).

00 - Power down (with self-refresh).

2

01 - Active/active-idle

2

10 - Reserved

2

11 - Reserved

2

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TC59YM916AMG24A,32A,32B,40B

Figure 20. Write Data Serial Load (WDSL) Control Register

Write Data Serial Load Control Register

Read/write register

7

6

5

4

3

2

1

0

SADR [7:0]: 00000100 WDSL [7:0] resets to 00000000

2

WDSL [7:0]

WDSL [7:0] - Writing to this register places eight bits of data into

the serial-to-parallel conversion logic (the “Demux” block of Figure

2). Writing to this register “2x16” times accumulates a full “t

”

CC

worth of write data. A subsequent WR command (with SLE = 1 in

CFG register in Figure 18) will write this data (rather than DQ data)

to the sense amps of a memory bank. The shifting order of the write

data is shown in Table 10.

Figure 21. RQ Scan High (RQH) Register

RQ Scan High Register

SADR [7:0]: 00000110

Read/write register

RQH [7:0] resets to 00000000

7

6

5

4

3

2

1

0

2

reserved

RQH [3:0]

RQH [3:0] - Latched value of RQ [11:8] in RQ wire test mode.

Figure 22. RQ Scan Low (RQL) Register

RQ Scan Low Register

SADR [7:0]: 00000111

Read/write register

7

6

5

4

3

2

1

0

RQL [7:0] resets to 00000000

2

RQL [7:0]

RQH [7:0] - Latched value of RQ [7:0] in RQ wire test mode.

Figure 23. Refresh Bank (REFB) Control Register

Refresh Bank Control Register

SADR [7:0]: 00001000

Read/write register

7

6

5

4

3

2

1

0

REFB [7:0] resets to 00000000

2

MBR [1:0]

reserved

BANK [2:0]

BANK [2:0] - Refresh bank field.

This field returns the bank address for the next self-refresh

operation when in powerdown power state.

MBR [1:0] - Multiple-bank and multi-row refresh control field.

00 - Single-bank refresh

2

10 - Reserved

2

01 - Reserved

2

11 - Reserved

2

Figure 24. Refresh High (REFH) Row Register

Refresh High Row Register

SADR [7:0]: 00001001

Read/write register

REFH [7:0] resets to 00000000

7

6

5

4

3

2

1

0

2

reserved

Reserved - Refresh row field.

This field contains the high-order bits of the row address that will

be refreshed during the next refresh interval. This row address will

be incremented after a REFI command for auto-refresh, or when

the BANK [2:0] field for the REFB register equals the maximum

bank address for self-refresh.

2003-07-10 37/74

TC59YM916AMG24A,32A,32B,40B

Figure 25. Refresh Middle (REFM) Row Register

Refresh Middle Row Register

SADR [7:0]: 00001010

Read/write register

REFM [7:0] resets to 00000000

7

6

5

4

3

2

1

0

2

reserved

R [11:8]

R [11:8] - Refresh row field.

This field contains the middle-order bits of the row address that

will be refreshed during the next refresh interval. This row address

will be incremented after a REFI command for auto-refresh, or

when the BANK [2:0] field for the REFB register equals the

maximum bank address for self-refresh.

Figure 26. Refresh Low (REFL) Row Register

Refresh Low Row Register

SADR [7:0]: 00001011

Read/write register

REFL [7:0] resets to 00000000

7

6

5

4

3

2

1

0

2

R [7:0]

R [7:0] - Refresh row field.

This field contains the low-order bits of the row address that will

be refreshed during the next refresh interval. This row address will

be incremented after a REFI command for auto-refresh, or when

the BANK [2:0] field for the REFB register equals the maximum

bank address for self-refresh.

Figure 27. Current Calibration 0 (CC0) Register

Current Calibration 0 Register

SADR [7:0]: 00010000

Read/write register

7

6

5

4

3

2

1

0

CC0 [7:0] resets to 00001111

2

reserved

CCVALUE0 [5:0]

CCVALUE0 [5:0] - Current calibration value field.

This field controls the amount of current drive for the

even-numbered DQ and DQN pins.

Figure 28. Current Calibration 1 (CC1) Register

Current Calibration 1 Register

SADR [7:0]: 00010001

Read/write register

7

6

5

4

3

2

1

0

CC1 [7:0] resets to 00001111

2

reserved

CCVALUE1 [5:0]

CCVALUE1 [5:0] - Current calibration value field.

This field controls the amount of current drive for the

odd-numbered DQ and DQN pins.

Figure 29. Impedance Calibration 0 (ZC0) Register

Impedance Calibration 0 Register

SADR [7:0]: 00010010

Read/write register

7

6

5

4

3

2

1

0

ZC0 [7:0] resets to 00000000

2

reserved

ZCVALUE0 [5:0]

ZCVALUE0 [5:0] - Impedance calibration value field.

This field controls the impedance of the on-chip termination

components for the even-numbered DQ and DQN pins.

2003-07-10 38/74

TC59YM916AMG24A,32A,32B,40B

Figure 30. Impedance Calibration 1 (ZC1) Register

Impedance Calibration 1 Register

SADR [7:0]: 00010011

Read/write register

7

6

5

4

3

2

1

0

ZC1 [7:0] resets to 00000000

2

reserved

ZCVALUE1 [5:0]

ZCVALUE1 [5:0] - Impedance calibration value field.

This field controls the impedance of the on-chip termination

components for the odd-numbered DQ and DQN pins.

Figure 31. Read Only Memory 0 (ROM0) Register

Read Only Memory 0 Register

SADR [7:0]: 00010110

Read-only register

7

6

5

4

3

2

1

0

ROM0 [7:0] resets to vvvvmmmm

2

VENDOR [3:0]

MASK [3:0]

MASK [3:0] - Version number of mask (0001 is first version).

2

VENDOR [3:0] - Vendor number for component:

0000 - Reserved

0001 - Toshiba

0010 - Elpida

0011 - 1111 - Reserved

Figure 32. Read Only Memory 1 (ROM1) Register

Read Only Memory 1 Register

SADR [7:0]: 00010111

Read-only register

7

6

5

4

3

2

1

0

ROM1 [7:0] resets to 0000cccc

2

reserved

CONFIG [3:0]

CONFIG [3:0] - Configuration number for component:

0000 - Reserved

0001 - 8 × 4M × 16 configuration

0010 - 1111 - Reserved

Figure 33. Test Register

Test Register

Read/write register

TEST [7:0] resets to 00000000

7

6

5

4

3

2

1

0

SADR [7:0]: 00011000

2

WTL WTE

reserved

WTE - Wire Test Enable

WTL - Wire Test Latch

Figure 34. DLL Register

DLL Register

Read/write register

DLL [7:0] resets to 00000000

7

6

5

4

3

2

1

0

SADR [7:0]: 00011001

2

reserved

TBD

2003-07-10 39/74

TC59YM916AMG24A,32A,32B,40B

Figure 35. PLL0 Register

PLL0 Register

Read/write register

PLL0 [7:0] resets to 00000000

7

6

5

4

3

2

1

0

SADR [7:0]: 00011010

2

reserved

TBD

Figure 36. PLL1 Register

PLL1 Register

Read/write register

PLL1 [7:0] resets to 00000000

7

6

5

4

3

SADR [7:0]: 00011011

2

reserved

TBD

Figure 37. IFT Register

IFT Register

Read/write register

IFT [7:0] resets to 00000000

7

6

5

4

3

SADR [7:0]: 00011100

2

reserved

TBD

Figure 38. DA Register

DA Register

Read/write register

DA [7:0] resets to 00000000

7

6

5

4

3

SADR [7:0]: 00011101

2

reserved

TBD

Figure 39. Partner-Definable (PART) Register

PART Register

Read/write register

PART [7:0] resets to 00000000

7

6

5

4

3

2

1

0

SADR [7:0]: 00011110

2

reserved

TBD

Figure 40. Delay (DLY) Control Register

DLY Register

Read/write register

DLY [7:0] resets to 01000110

7

6

5

4

3

2

1

0

SADR [7:0]: 00011111

2

CWD [3:0]

CAC [3:0]

CAC [3:0] - Programmed value of t

timing parameter:

CAC

0110 - t

= 6*t

= 7*t

1000 - t

= 8*t

CAC CYCLE

2

CAC

CYCLE

2

0111 - t

others - Reserved

2

CWD [3:0] - Programmed value of t

timing parameter:

CWD

0011 - t

= 3*t

= 4*t

2

CWD

CYCLE

0100 - t

others - Reserved

2

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TC59YM916AMG24A,32A,32B,40B

Maintenance Operations

Refresh Transactions

Figure 41 contains two timing diagrams showing examples of refresh transactions. The top timing diagram shows

a single refresh operation. Bank Ba is assumed to be closed (in a precharged state) when a REFA command is

received in a ROWP packet on clock edge T . The REFA command causes the row addressed by the REFr register

0

(REFH/REFM/REFL) to be opened (sensed) and placed in the sense amp array for the bank.

Note that the REFA and REFI commands are similar to the ACT command functionally; both specify a bank

address and delay value, and both cause the selected bank to open (to become sensed.) The difference is that the

ACT command is accompanied by a row address in the ROWA packet, while the REFA and REFI commands use a

row address in the REFr register (REFH/REFM/REFL).

After a time t , a ROWP packet with REFP command to bank Ba is presented. This causes the bank to be

RAS

closed (precharged), leaving the bank in the same state as when the refresh transaction began.

Note that the REFP command is equivalent to the PRE command functionally; both specify a bank address and

delay value, and both cause the selected bank to close (to become precharged).

After a time t , another ROWP packet with REFA command to bank Bb is presented (banks Ba and Bb are the

RP

same in this example). This starts a second refresh cycle. Each refresh transaction requires a total time t

= t

RAS

RX

+ t , but refresh transactions to different banks may be interleaved like normal read and write transactions.

RP

Each row of each bank must be refreshed once in every t

with a REFA command in the top timing diagram.

interval. This is shown with the fourth ROWP packet

RP

Interleaved Refresh Transactions

The lower timing diagram in Figure 41 represents one way a memory controller might handle refresh

maintenance in a real system.

A series of eight ROWP packets with REFA commands (except for the last which is a REFI command) are

presented starting at edge T _.The packets are spaced with intervals of t . Each REFA or REFI command is

RR

0

addressed to a different bank (Ba through Bh) but uses the same row address from the REFr (REFH/REFM/REFL)

register. The eighth REFI command uses this address and then increments it so the next set of eight REFA/REFI

commands will refresh the next set of rows in each bank.

A series of eight ROWP packets with REFP commands are presented effectively at edge T (a time t

10

after

RAS

the first ROWP packet with a REFA command). The packets are spaced with intervals of t . Like the REFA/REFI

PP

commands, each REFP command is addressed to a different bank (Ba through Bh).

This burst of eight refresh transactions fully utilizes the memory component. However, other read and writes

transactions may be interleaved with the refresh transactions before and after the burst to prevent any loss of bus

efficiency. In other words, a ROWA packet with ACT command for a read or write could have been presented at

edge T (a time t

RR

before the first refresh transaction starts at edge T ). Also, a ROWA packet with ACT

0

4

command for a read or write could have been presented at edge T (a time t

36 RR

after the last refresh transaction

starts at edge T ). In both cases, the other request packets for the interleaved read or write accesses (the

32

precharge commands and the read or write commands) could be slotted in among the request packets for the

refresh transactions.

2003-07-10 41/74

TC59YM916AMG24A,32A,32B,40B

Figure 41. Refresh Transactions

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇

CFM

CFMN

t

RP

RAS

t

CYCLE

RQ11

REFA

a0

REFP

a1

REFA

b0

REFA

c0

…RQ0

t

RC

DQ15…0

DQN15…0

t

REF

Transaction a: REF

Transaction b: REF

Transaction c: REF

a0 = {Ba, REFR}

b0 = {Bb, REFR}

c0 = {Bc, REFR}

a1 = {Ba }

b1 = {Bb }

c1 = {Bc }

Bb = Ba

Refresh Transaction

Bc/Rc = Ba/Ra

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

RR

REFA

a0

REFA

b0

REFA

c0

REFA

d0

REFA

e0

REFA

f0

RQ11…RQ0

(ACT)

REFP

a1

REFP

b1

REFP

c1

REFP

d1

RQ11…RQ0

(PRE)

REFA

a0

REFA

b0

REFA

c0

REFP

a1

REFA

d0

REFP

b1

REFA

e0

REFP

c1

REFA

f0

REFP

d1

RQ11…RQ0

(ALL)

DQ15…0

DQN15…0

T₂₄T₂₅T₂₆T₂₇T₂₈T₂₉T₃₀T₃₁T₃₂T₃₃T₃₄T₃₅T₃₆T₃₇T₃₈T₃₉T₄₀T₄₁T₄₂T₄₃T₄₄T₄₅T₄₆T₄₇

CFM

This REFI increments REFR.

CFMN

t

CYCLE

RQ11…RQ0

(ACT)

REFA

g0

REFA

h0

REFA

j0

RQ11…RQ0

(PRE)

REFP

e1

REFP

f1

REFP

g1

REFP

h1

RQ11…RQ0

(ALL)

REFA

g0

REFA

h0

REFA

j0

REFP

g1

REFP

h1

REFP

e1

REFP

f1

DQ15…0

DQN15…0

Transaction a: REF

Transaction b: REF

Transaction c: REF

Transaction d: REF

Transaction e: REF

Transaction f: REF

Transaction g: REF

Transaction h: REF

Transaction i: REF

a0 = {Ba, REFR}

b0 = {Bb, REFR}

c0 = {Bc, REFR}

d0 = {Bd, REFR}

e0 = {Be, REFR}

f0 = {Bc, REFR}

g0 = {Bg, REFR}

h0 = {Bh, REFR}

i0 = {Bi, REFR + 1}

a1 = {Ba}

b1 = {Bb}

c1 = {Bc}

d1 = {Bd}

e1 = {Be}

f1 = {Bf}

Ba,Bb,Bc,Bd,Be,

Bf,Bg and Bh are

different banks.

g1 = {Bg}

h1 = {Bh}

i1 = {Bi}

Interleaved Refresh Example

Bi = Ba

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TC59YM916AMG24A,32A,32B,40B

Calibration Transactions

Figure 42 shows the calibration transaction diagrams for the XDR DRAM device. There is one calibration

operation supported: calibration of the output current level I , each DQi and DQNi pin.

OL

The output current calibration sequence is shown in Figure 42. It begins when a period of t

is observed

CMD-CALC

after the last RQ packet (with command “CMD a” in this example). No request packets should be issued in this

period.

A COLX packet with a “CALC b” command is then issued to start the current calibration sequence. A period of

t

is observed after this packet. No request packets should be issued during this period.

CALCE

A COLX packet with a “CALE c” command is then issued to end the current calibration sequence. A period of

is observed after this packet. No request packets should be issued during this period. The first request

t

CALE-CMD

packet may then be issued (with command “CMD d” in this example).

A second current calibration sequence must be started within an interval of t

COLX packet with a “CALC e” command starts a subsequent sequence.

. In this example, the next

CALC

Figure 42. Calibration Transactions

CFM

CFMN

t

CALE-CMD

CALCE

t

CYCLE

RQ11

…RQ0

CMD

a

CALC

b

CALE

c

CMD

d

CALC

e

t

CMD-CALC

DQ15…0

DQN15…0

t

CALC

Packet a: Any CMD

Packet b: CALC

Packet c: CALE

Current Calibration Transaction

Packet d: Any CMD

Packet e: CALC

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TC59YM916AMG24A,32A,32B,40B

Power State Management

Figure 43 shows power state transition diagrams for the XDR DRAM device. There are two power states in the

XDR DRAM: Powerdown and Active. Powerdown state is to be used in applications in which it is necessary to shut

down the CFM/CFMN clock signals. In this state, the contents of the storage cells of the XDR DRAM will be

retained by an internal state machine which performs periodic refresh operations using the REFB and REFr

control registers.

The upper diagram shows the sequence needed for Powerdown entry. Prior to starting the sequence, all banks of

the XDR DRAM must be precharged so they are left in a closed state. Also, all 2³banks must be refreshed using the

current value of the REFr registers, and the REFr registers must NOT be incremented with the REFI command at

the end of this special set of refresh transactions. This ensures that no matter what value has been left in the

REFB register, no row of any bank will be skipped when automatic refresh is first started in Powerdown. There

may be some banks at the current row value in the REFr registers that are refreshed twice during the Powerdown

entry process.

After the last request packet (with the command CMDa in the upper diagram of the figure), an interval of

t

is observed. No request packets should be issued during this period.

CMD-PDN

A COLX packet with the PDN command is issued after this interval, causing the XDR DRAM to enter

Powerdown state after an interval of t has elapsed (this is the parameter that should be used for

PDN-ENTRY

calculating the power dissipation of the XDR DRAM). The CFM/CFMN clock signals may be removed a time

after the COLX packet with the PDN comman.

t

PDN-CFM

When the XDR DRAM is in Powerdown, an internal frequency source and state machine will automatically

generate internal refresh transactions. It will cycle through all 2³state combinations of the REFB register. When

the largest value is reached and the REFB value wraps around, the REFr register is incremented to the next value.

The REFB and REFr values select which bank and which row are refreshed during the next automatic refresh

transaction.

The lower diagram shows the sequence needed for Powerdown exit. The sequence is started with a serial

broadcast write (SBW command) tranasaction using the serial bus of the XDR DRAM. This transaction writes the

value “00000001” to the Power Management (PM) register (SADR = “00000011”) of all XDR DRAMs connected to

the serial bus. This sets the PX bit of the PM register, causing the XDR DRAMs to return to Active power state.

The CFM/CFMN clock signals must be stable a time t

CFM-PDN

before the end of the SBW transaction.

has elapsed from the end of the SBW

The XDR DRAM will enter Active state after an interval of t

PDN-EXIT

transaction (this is the parameter that should be used for calculating the power dissipation of the XDR DRAM).

The first request packet may be issued after an interval of t has elapsed from the end of the SBW

PDN-CMD

transaction, and must contain a “REFA” command in a ROWP packet. In this example, this packet is denoted with

the command “REFA 1”. No other request packets should be issued during this t interval.

PDN-CMD

All “n” banks (in the example, n = 2³) must be refreshed using the current value of the REFr registers. The “nth”

refresh transaction will use a “REFI” command to increment the REFr register (instead of a “REFR” command).

This ensures that no matter what value has been left in the REFB register, no row of any bank will be skipped

when normal refresh is restarted in Active state. There may be some banks at the current row value in the REFr

registers that are refreshed twice during the Powerdown exit process.

Note that during the Powerdown state an internal time source keeps the device refreshed. However, during the

t

interval, no internal refresh operations are performed. As a result, an additional burst of refresh

PDN-CMD

transactions must be issued after the burst of “n” transactions described above. This second burst consists of “m”

refresh transactions:

m = ceiling [2³*2¹²*t

]

PDN-CMD REF

/t

Where “2¹²” is the number of rows per bank, and “2³” is the number of banks. Every “nth” refresh transaction

(where n = 2³) will use a “REFI” command (to increment the REFr register) instead of a “REFR” command.

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TC59YM916AMG24A,32A,32B,40B

Figure 43. Power State Management

CFM

No Signal

CFMN

t

PDN-CFM

t

CYCLE

RQ11

…RQ0

CMD

a

PDN

b

Power Down State…

DQ15…0

DQN15…0

t

CMD-PDN

t

PDN-ENTRY

Transaction a: Last precharge command

Transaction b: PDN

Power Down Entry

S₀S₂S₄S₆S₈S₁₀S₁₂S₁₄S₁₆S₁₈S₂₀S₂₂S₂₄S₂₆S₂₈S₃₀S₃₂S₃₄

SCK

t

CYC,SCK

RST

Power-up transaction

SCMD

Start

2’h0, SID[5:0]

SADR [7:0]

SWD [7:0]

’0’ ’0’

’1’ ’1’ ’0’ ’0’

’0’ ’0’ 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ‘0' 7 6 5 4 3 2 1 0 ‘0’

SDI

(input)

SDO

(output)

CFM

No Signal

CFMN

t

PDN-EXIT

CFM-PDN

t

CYCLE

RQ11

…RQ0

...Power Down State

DQ15…0

DQN15…0

t

PDN-CMD

CFM

CFMN

t

CYCLE

RQ11

REFA

1

REFA

2

REFP

n-2

REFP

n-1

REFP

n

REFI

n

…RQ0

DQ15…0

DQN15…0

t

PDN-CMD

The final REFA/REFI command increments the REFr register.

Power Down Exit

Transaction 1: REFA

Transaction 2: REFA

Transaction n-1: REFA

Transaction n: REFI

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TC59YM916AMG24A,32A,32B,40B

Initialization

Figure 44 shows the topology of the serial interface signals of a XDR DRAM system. The three signals RST, CMD,

and SCK are transmitted by the controller and are received by each XDR DRAM device along the bus. The signals

are terminated to the VTERM supply through termination components at the end farthest from the controller. The

SDI input of the XDR DRAM device furthest from the controller is also terminated to VTERM. The SDO output of

each XDR DRAM device is transmitted to the SDI input of the next XDR DRAM device (in the direction of the

controller). This SDO/SDI daisy-chain topology continues to the controller, where it ends at the SRD input of the

controller. All the serial interface signals are low-true. All the signals use RSL signaling circuits, except for the

SDO output which uses CMOS signaling circuits.

Figure 44. Serial Interface Systems Topology

VTERM

RST

CMD SCK

SRD

RST

SDO

CMD SCK

SDI

RST

SDO

CMD SCK

SDI

RST

SDO

CMD SCK

SDI

Controller

XDR DRAM [63]

XDR DRAM [ j ]

XDR DRAM [ 0 ]

Figure 45 shows the initialization timing of the serial interface for the XDR DRAM [k] device in the system shown

above. Prior to initialization, the RST is held at zero. The CMD input is not used here, and should also be held at

zero. Note that the inputs are all sampled by the negative edge of the SCK clock input. The SDI input for the XDR

DRAM [0] device is zero, and is unknown for the remaining devices.

On negative SCK edge S the RST input is sampled one. It is sampled one on the next four edges, and is sampled

8

zero on edge S a time t

12 RST-10

after it was first sampled one. The state of the control registers in the XDR DRAM

device are set to their reset values after the first edge (S ) in which RST is sampled one.

8

Figure 45. Initialization Timing for XDR DRAM [ k ] Device

S₀S₂

S₄S₆

S₈S₁₀S₁₂S₁₄S₁₆S₁₈S₂₀S₂₂S₂₄S₂₆S₂₈S₃₀S₃₂S₃₄S₃₆S₃₈S₄₀S₄₂S₄₄

S₄₆

S₄₈

SCK

t

RST-10

t

CYC,SCK

RST

‘0' ‘0' ‘0' ‘0' ‘1' ‘1' ‘1' ‘1' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0'

t

RST,SDI,00 = k * CYC,SCK

CMD

SDI

(input)

‘x' ‘x' ‘x' ‘x' ‘X' ‘1' ‘1' ‘1' ‘1' ‘1' ‘1' ‘1' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0'

t

SDI-SDO,00

RST-SDO,11

SDO

(output)

‘x' ‘x' ‘x' ‘x' ‘X' ‘1' ‘1' ‘1' ‘1' ‘1' ‘1' ‘1' ‘1' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0'

The SDI inputs will be sampled one within a time t

after RST is first sampled one in all the XDR

DRAMs except for XDR DRAM [0]. XDR DRAM [0]’s SDI input will always be sampled zero.

RST-SDO, 11

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TC59YM916AMG24A,32A,32B,40B

XDR DRAM [k] will see its RST input sampled zero at S , and will then see its SDI input sampled zero at S

12

16

(after SDI had previously been sampled one). This interval (measured in t

CYC, SCK

units) will be equal to the index

[k] of the XDR DRAM device along the serial interface bus. In this example, k is equal to 4.

This is because each XDR DRAM device will drive its SDO output zero around the SCK edge a time t

after its SDI input is sampled zero.

SDI-SDO,00

In other words, the XDR DRAM [0] device will see RST and SDI both sampled zero on the same edge S

12

(t

RST-SDI, 00

will be 0 × t

CYC, SCK

units), and will drive its SDO to zero around the subsequent edge (S ).

13

The XDR DRAM [1] device will see SDI sampled zero on edge S (t

13 RST-SDI, 00

will drive its SDO to zero around the subsequent edge (S ).

14

will be 1 × t

units), and

CYC, SCK

The XDR DRAM [2] device will see SDI sampled zero on edge S (t

14 RST-SDI, 00

will be 2 × t

units), and

will drive its SDO to zero around the subsequent edge (S ).

15

This continues until the last XDR DRAM device drives the SRD input of the controller. Each XDR DRAM device

contains a state machine which measures the interval t between the edges in which RST and SDI are

RST-SDI, 00

both sampled zero, and uses this value to set the SID [5:0] field of the SID (Serial Identification) register. This

value allows directed read and write transactions to be made to the individual XDR DRAM devices.

Table 9 summarizes the range of the timing parameters used for initialization by the serial interface bus.

Table 9. Initialization Timing Parameters

Symbol

Parameter

Min

2

Max

Unit

Figure (s)

Number of cycles between RST being sampled one and RST

being sampled zero.

t

RST, 10

CYC,SCK

Number of cycles between RST being sampled one and SDO

being driven to one.

1

0

1

RST-SDO, 11

RST, SDI, 00

Number of cycles between RST being sampled zero (after

being sampled one for t

or more cycles) and SDI

RST, 10, MIN

t

63

t

CYC,SCK

being sampled zero. This will be equal to the index [k] of the

XDR DRAM device along the serial interface bus.

Number of cycles between SDI being sampled one (after RST

t

has been sampled one for t

or more cycles and is

1

SDI-SDO, 00

RST-SCK

RST, 10, MIN

CYC,SCK

ns

then sampled zero) and SDO being driven to zero.

Asynchronous reset interval.

20

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TC59YM916AMG24A,32A,32B,40B

XDR DRAM Initialization Overview

[1] Power-on reset circuit in XDR DRAM places XDR DRAM into low-power state.

[2] Assert RST, SCK, SDI and CMD to logical zero. Then:

- Assert RST to logical one. XDR DRAM enters PDN state.

- Wait interval t

.

RST-SCK

- Pulse SCK to logical one, then to logical zero four times.

- Perform initialization sequence in Figure 45.

[3] XDR DRAM has valid Serial ID and all registers have default values that are defined in Figure 17 through

Figure 40.

[4] Perform broadcast or directed register writes to adjust registers which need a value different from their default

value.

[5] Perform Powerdown Exit sequence shown in Figure 43. This includes the activity from SCK cycle S₀through the

final REFP command.

[6] Perform current calibration. The CALC/CALE sequence shown in Figure 42 is issued 128 times. After this, each

sequence is issued once every t

CALC

interval.

[7] Condition the XDR DRAM banks by performing a REFA/REFI activate and REFP precharge operation to each

bank eight times. This can be interleaved to save time. The row address for the activate operation will step

through eight successive values of the REFr registers. The sequence between cycles T and T in the

32

0

Interleaved Refresh Example in Figure 41 could be performed eight times to satisfy this conditioning

requirement.

XDR DRAM Pattern Load with WDSL Register

The Yellowstone memory system requires a method of deterministically loading pattern data to XDR DRAMs

before beginning Receive Timing Calibration (RX TCAL). The method employed by the XDR DRAMs to achieve this

is called Write Data Serial Load (WDSL). A WDSL packet sends one-byte of serial data which is serially shifted

into a holding register within the XDR DRAM. Initialization software sends a sequence of WDSL packets, each of

which shifts the new byte in and advances the shifter by 8 positions. In this way, XDR DRAMs of varying widths

can be loaded with a single command type.

Each sequence of WDSL packets will load one full column of data to the internal holding register of the target

XDR DRAM. Depending upon the ratio of native device width to programmed width, there may be more than one

sub-column per column. After loading a full column, a series of WR commands will be issued to sequentially

transfer each sub-column of the column to the XDR DRAM core (s), based upon the SC [3:0] bits.

Table 10. WDSL-to-Core Mapping (First Generation ×16/×8/×4 XDR DRAM, BL = 16)

WDSL Word

Order to DQ

Transfer Map

Word Written (1 = Written, 0 = Not Written)

×8 ×4

SC [3:2] SC [3:2] SC [3:2] SC [3:2] SC [3:2] SC [3:2] SC [3:2]

XDR DRAM DQ Pin

Used

×16

Core Word

×4

×8

×16

WD [n] [15:0]

= xx

= 0x

= 1x

= 00

= 01

= 10

= 11

LOGICAL VIEW OF XDR DRAM

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

WD [0] [15:0]

WD [1] [15:0]

WD [2] [15:0]

WD [3] [15:0]

WD [4] [15:0]

WD [5] [15:0]

WD [6] [15:0]

WD [7] [15:0]

WDSL Word 8

WDSL Word 0

WDSL Word 12

WDSL Word 4

WDSL Word 10

WDSL Word 2

WDSL Word 14

WDSL Word 6

1

0

1

0

1

0

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TC59YM916AMG24A,32A,32B,40B

WDSL Word

Order to DQ

Transfer Map

Word Written (1 = Written, 0 = Not Written)

XDR DRAM DQ Pin

Used

×16

×8

×4

Core Word

SC [3:2] SC [3:2] SC [3:2] SC [3:2] SC [3:2] SC [3:2] SC [3:2]

×4

×8

×16

WD [n] [15:0]

= xx

1

= 0x

0

= 1x

1

= 00

0

= 01

0

= 10

1

= 11

0

DQ8

DQ9

WD [8] [15:0]

WD [9] [15:0]

WDSL Word 9

WDSL Word 1

1

0

1

0

1

0

DQ10 WD [10] [15:0] WDSL Word 13

1

0

1

0

1

0

DQ11 WD [11] [15:0]

DQ12 WD [12] [15:0]

DQ13 WD [13] [15:0]

WDSL Word 5

WDSL Word 11

WDSL Word 3

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DQ14 WD [14] [15:0] WDSL Word 15

DQ15 WD [15] [15:0] WDSL Word 7

1

0

1

0

1

0

1

0

1

PHYSICAL VIEW OF XDR DRAM

DQ14 WD [14] [15:0] WDSL Word 15

DQ6 WD [6] [15:0] WDSL Word 14

DQ10 WD [10] [15:0] WDSL Word 13

DQ2 WD [2] [15:0]

DQ12 WD [12] [15:0]

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DQ6

DQ2

DQ4

DQ2

WDSL Word 12

WDSL Word 11

WDSL Word 10

WDSL Word 9

WDSL Word 8

WDSL Word 0

WDSL Word 1

WDSL Word 2

WDSL Word 3

WDSL Word 4

WDSL Word 5

WDSL Word 6

WDSL Word 7

DQ4

DQ8

DQ0

DQ1

DQ9

DQ5

WD [4] [15:0]

WD [8] [15:0]

WD [0] [15:0]

WD [1] [15:0]

WD [9] [15:0]

WD [5] [15:0]

DQ0

DQ1

DQ0

DQ1

DQ5

DQ3

DQ7

DQ13 WD [13] [15:0]

DQ3 WD [3] [15:0]

DQ11 WD [11] [15:0]

DQ7 WD [7] [15:0]

DQ15 WD [15] [15:0]

DQ3

Table 11. DQ Bit to WDSL Bit Transfer Order Mapping (First Generation ×16/×8/×4 XDR DRAM, BL = 16)

DQ Transfer Order

Symbol (Bit) Time

Bit Transmitted on DQ pins

WDSL Transfer Order

WDSL Word

t0

t1

t2

t3

t4

t5

t6

t7

t8

t9

t10 t11

t12 t13 t14 t15

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9 D10 D11 D12 D13 D14 D15

WDSL Word n

WDSL Byte Order

SWD

WDSL Byte [2n]

WDSL Byte [2n + 1]

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Bit Transmitted on CMD pin D0

D4

D8 D12 D1

D5

D9 D13 D2

D6 D10 D14 D3

D7 D11 D15

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Special Feature Description

Dynamic Width Control

This XDR DRAM device includes a feature called dynamic width control. This permits the device to be configured

so that read and write data can be accessed through differing widths of DQ pins. Figure 46 shows a diagram of the

logic in the path of the read data (Q) and write data (D) that accomplishes this.

The read path is on the right of the figure. There are 16 sets of S signals (the internal data bus connecting to the

sense amps of the memory core), with 16 signals in each set. When the XDR DRAM device is configured for

maximum width operation (using the WIDTH [2:0] field in the CFG register), each set of 16 S signals goes to one of

the 16 DQ pins (via the Q [15:0] [15:0] read bus) and are driven out in the 16 time slots for a read data packet.

When the XDR DRAM device is configured for a width that is less than the maximum, some of the DQ pins are

used and the rest are not used. The SC [3:0] field of the COL request packets selects which S [15:0] [15:0] signals

are passed to the Q [15:0] [15:0] read bus and driven as read data.

Figure 47 shows the mapping from the S bus to the Q bus as a function of the WIDTH [2:0] register field and the

SC [3:0] field of the COL request packet. There is a separate table for each valid value of WIDTH [2:0]. In each

table, there is an entry in the left column for each valid value of SC [3:0]. This field should be treated as an

extension of the C [9:4] column address field. The right hand column shows which sets of S [15:0] [15:0] signals are

mapped to the Q read data bus for a particular value of SC [3:0].

For example, assume that the WIDTH [2:0] value is “010”, indicating a device width of x4. Looking at the

appropriate table in Figure 47, it may be seen that in the SC [3:0] field, the SC [1:0] sub-column address bits are

not used. The remaining SC [3:0] address bit(s) selects one of the 64-bit blocks of S bus signals, causing them to be

driven onto the Q [3:0] [15:0] read data bus, which in turn is driven to the DQ3…DQ0/DQN3…DQN0 data pins.

The Q [15:4] [15:0] signals and DQ15…DQ4/DQN15...DQN4 data pins are not used for a device width of x4.

The write path is shown on the left side of Figure 46. As before, there are 16 sets of S signals (the internal data

bus connecting to the sense amps of the memory core), with 16 signals in each set. When the XDR DRAM device is

configured for maximum width operation (using the WIDTH [2:0] field in the CFG register), each set of 16 S signals

is driven from one of the 16 DQ pins (via the D [15:0] [15:0] write bus) from each of the 16 time slots for a write

data packet.

Figure 47 also shows the mapping from the D bus to the S bus as a function of the WIDTH [2:0] register field and

the SC [3:0] field of the COL request packet. There is a separate table for each valid value of WIDTH [2:0]. In each

table, there is an entry in the left column for each valid value of SC [3:0]. This field should be treated as an

extension of the C [9:4] column address field. The right hand column shows which set of S [15:0] [15:0] signals are

mapped from the D read data bus for a particular value of SC [3:0].

For example, assume that the WIDTH [2:0] value is “001”, indicating a device width of x2. Looking at the

appropriate table in Figure 47, it may be seen that in the SC [3:0] field, the SC [0] sub-column address bit is not

used. The remaining SC [3:0] address bit(s) selects one of the 32-bit blocks of S bus signals, causing them to be

driven from the D [1:0] [15:0] write data bus, which in turn is driven from the DQ1…DQ0/DQN1...DQN0 data pins.

The D [15:2] [15:0] signals and DQ15…DQ2/DQN15…DQN2 data pins are not used for a device width of x2.

Figure 46. Multiplexes for Dynamic Width Control

S [15:0] [15:0]

16x16

Byte Mask (WR)

8

M [7 : 0]

16x16

D1 [15:0] [15:0]

4+3

WIDTH [2 : 0]

SC [3 : 0]

WIDTH [2 : 0]

SC [3 : 0]

Dynamic Width Demux (WR)

Dynamic Width Mux (RD)

16x16

D [15:0] [15:0]

Q [15:0] [15:0]

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TC59YM916AMG24A,32A,32B,40B

The block diagram in Figure 46 indicates that the Dynamic Width logic is positioned after the serial-to-parallel

conversion (demux block) in the data receiver block and before the parallel-to-serial conversion (mux block) in the

data transmitter block (see the block diagram in Figure 2 also). The block diagram is shown in this manner so the

functionality of the logic can be made as clear as possible. Some implementations may place this logic in the data

receiver and transmitter blocks, performing the mapping in Figure 47 on the serial data rather than the parallel

data. However, this design choice will not affect the functionality of the Dynamic Width logic; it is strictly an

implementation decision.

Figure 47. D-to-S and S-to-Q Mapping for Dynamic Width Control

WIDTH [2:0] = 000 (×1 device width)

WIDTH [2:0] = 001 (×2 device width)

WIDTH [2:0] = 011 (×8 device width)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

S [0] [15:0]

S [1] [15:0]

S [2] [15:0]

S [3] [15:0]

S [4] [15:0]

S [5] [15:0]

S [6] [15:0]

S [7] [15:0]

S [8] [15:0]

S [9] [15:0]

S [10] [15:0]

S [11] [15:0]

S [12] [15:0]

S [13] [15:0]

S [14] [15:0]

S [15] [15:0]

000x

001x

010x

011x

100x

101x

110x

111x

S [1:0] [15:0]

S [3:2] [15:0]

S [5:4] [15:0]

S [7:6] [15:0]

S [9:8] [15:0]

S [11:10] [15:0]

S [13:12] [15:0]

S [15:14] [15:0]

0xxx

1xxx

S [7:0] [15:0]

S [15:8] [15:0]

D [1:0] [15:0]

Q [1:0] [15:0]

D [7:0] [15:0]

Q [7:0] [15:0]

SC [3:0]

WIDTH [2:0] = 010 (×4 device width)

WIDTH [2:0] = 100 (×16 device width)

00xx

01xx

10xx

11xx

S [3:0] [15:0]

S [7:4] [15:0]

S [11:8] [15:0]

S [15:12] [15:0]

xxxx

S [15:0] [15:0]

D [0] [15:0]

Q [0] [15:0]

D [3:0] [15:0]

Q [3:0] [15:0]

D [15:0] [15:0]

Q [15:0] [15:0]

SC [3:0]

Note: “A” die does not support ×1 and ×2 device widths.

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Write Masking

Figure 48 shows the logic used by the XDR DRAM device when a write-masked command (WRM) is specified in a

COLM packet. This masking logic permits individual bytes of a write data packet to be written or not written

according to the value of an eight bit write mask M [7:0].

In Figure 48, there are 16 sets of 16 bit signals forming the D1 [15:0] [15:0] input bus for the Byte Mask block.

These are treated as 2x16 8-bit bytes:

D1 [15] [15:8]

D1 [15] [7:0]

...

D1 [1] [15:8]

D1 [1] [7:0]

D1 [0] [15:8]

D1 [0] [7:0]

The eight bits of each byte is compared to the value in the byte mask field (M [7:0]). If they are not equal (NE),

then the corresponding write enable signal (WE) is asserted and the byte is written into the sense amplifier. If they

are equal, then the corresponding write enable signal (WE) is deserted and the byte is not written into the sense

amplifier.

In the example of Figure 48, a WRM command performs a masked write of a 64-byte data packet to all the

memory devices connected to the RQ bus (and receiving the command). It is the job of the memory controller to

search the 64-bytes to find an eight bit data value that is not used and place it into the M [7:0] field. This will

always be possible because there are 256 possible 8-bit values and there are only 64 possible values used in the

bytes in the data packet.

Figure 48. Byte Mask Logic

S [15] [15:8]

8

S [15] [7:0]

8

S [15] [15:8]

8

S [0] [7:0]

8

WE-MSB

[15]

WE-LSB

[15]

WE-MSB

[0]

WE-LSB

[0]

1

NE

Compare

8

D1 [15] [15:8]

D1 [15] [7:0]

D1 [0] [15:8]

D1 [0] [7:0]

M [7:0]

8

D1 [15] [15:8]

D1 [15] [7:0]

D1 [0] [15:8]

D1 [0] [7:0]

S [15:0] [15:0]

16x16

7

Byte Mask (WR)

M [7:0]

16x16

D1 [15:0] [15:0]

4+3

WIDTH [2:0]

SC [3:0]

WIDTH [2:0]

SC [3:0]

Dynamic Width Demux (WR)

Dynamic Width Mux (RD)

16x16

D [15:0] [15:0]

Q [15:0] [15:0]

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Note that other systems might use a data transfer size that is different than the 64 bytes per t

bus that is used in the example in Figure 48.

interval per RQ

CC

Figure 49 shows the timing of two successive WRM commands in COLM packets. The timing is identical to that of

two successive WR commands in COL packets. The one difference is that the COLM packet includes a M [7:0] field

that indicates the reserved bit pattern (for the eight bits of each byte) that indicates that the byte is not to be

written. This requires that the alignment of bytes within the data packet be defined, and also that the bit

numbering within each byte be defined (note that this was not necessary for the unmasked WR command). In the

figure, bytes are contained within a single DQ/DQN pin pair - this is necessary so the dynamic width feature can be

supported. Thus, each pin pair carries two bytes of each data packet. Byte [0] is transferred earlier than byte [1],

and bit [0] of each byte (corresponding to M [0]) is transferred first, followed by the remaining bits in succession).

Figure 49. Write-Masked (WRM) Transaction Example

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

WRM

a2

RD

a1

WRM

a1

…RQ0

t

CC

DQ15…0

D(a1)

D(a2)

Q(a1)

DQN15…0

t

CAC

CWD

Bit-and Byte-numbering

convention for write

and read data packets.

Byte [0]

Byte [16+0]

DQ0

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

DQN0

Byte [1]

Byte [16+1]

DQ1

[3]

[4]

[6]

[8]

[11]

[12]

DQN1

Byte [15]

Byte [16+15]

DQ15

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

DQN15

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Multiple Bank Sets and the ERAW Feature

Figure 52 shows a block diagram of a XDR DRAM in which the banks are divided into two sets (called the even

bank set and the odd bank set) according to the least significant bit of the bank address field. This XDR DRAM

supports a feature called “Early Read After Write” (hereafter called “ERAW”).

The logic that accepts commands on the RQ11…RQ0 signals is capable of operating these two bank sets

independently. In addition, each bank set connects to its own internal “S” data bus (called S0 and S1). The receive

interface is able to drive write data onto either of these internal data buses, and the transmit interface is able to

sample read data from either of these internal data buses. These capabilities will permit the delay between a write

column operation and a read column operation to be reduced, thereby improving performance.

Figure 50 shows the timing previously presented in Figure 12, but with the activity on the internal S data bus

included. The write-to-read parameter t

D (a2) and Q (c1).

ensures that there is adequate turnaround time on the S bus between

WR

∆

When ERAW is supported with odd and even bank sets, the t

parameter must be obeyed when the write

WR, MIN

∆

and read column operations are to the same bank set, but a second parameter t

permits earlier column

WR-D

∆

operations to the opposite bank set. Figure 51 shows how this is possible because there are two internal data buses

S0 and S1. In this example, the four columns read operations are made to the same bank Bb, but they could use

different banks as long as they all belonged to the bank set that was different from the bank set containing Ba (for

the column write operations).

Figure 50. Write/Read Interaction – No ERAW Feature

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

WR

a1

WR

a2

RD

c1

RD

c2

…RQ0

t

CAC

∆WR

DQ15…0

D(a1)

D(a2)

Q(c1)

Q(c2)

DQN15…0

t

DQ gap

CWD

t

turnaround

t

CC

S0[15:0]

[15:0]

D(a1)

D(a2)

Q(c1)

Transaction a: WR

Transaction c: RD

a1 = {Ba, Ca1}

c1 = {Bc, Cc1}

a2 = {Ba, Ca2}

c2 = {Bc, Cc2}

Figure 51. Write/Read Interaction – ERAW Feature

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

WR

a1

WR

a2

RD

b1

RD

b2

RD

b3

RD

b4

RD

c1

…RQ0

t

∆WR-D

CAC

DQ15…0

D(a1)

CWD

D(a2)

Q(b1)

Q(b2)

Q(b3)

Q(b4)

Q(c1)

DQN15…0

t

DQ gap

t

turnaround

CC

t

CC

S0[15:0]

[15:0]

D(a1)

D(a2)

Q(b2)

S0[15:0]

[15:0]

Q(b1)

Q(b3)

Transaction a: WR

Transaction b: RD

Transaction c: RD

a1 = {Ba, Ca1}

b1 = {Bb, Cb1}

c1 = {Bc, Cc1}

a2 = {Ba, Ca2}

b2 = {Bb, Cb2}

c2 = {Bc, Cc2}

Bank Restrictions

Bb is in different bank set than Ba

Be is in same bank set as Ba

B3 = {Bb, Cb3}

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TC59YM916AMG24A,32A,32B,40B

Figure 52. XDR DRAM Block Diagram with Bank Sets

RQ11...RQ0

12

1:2 Demux

Reg

COL

PRE

ACT

decode

6

3

12

3

BA,BR,REFB

Odd

Even

Bank Array

16x16*2⁶*2¹²

1

ACT

ACT logic

12

ROW

12

1

Bank 1

Bank (2 -1)

16x16*2

Bank 0

PRE

PRE logic

3

PRE

6

Bank (2 -1)

Bank (2 -2)

6

16x16*2

Sense Amp Array

16x16*2⁶

1

16x16*2⁶

1

R/W

COL logic

R/W

6

COL

Sense Amp 1

Sense Amp 0

3

COL

3

6

Sense Amp (2 -1)

Sense Amp (2 -2)

16x16

S1[15:0] [15:0]

16x16

S0[15:0] [15:0]

16x16

WR odd

WR even

RD odd

RD even

16x16

Byte Mask (WR)

16x16

Dynamic Width Demux (WR)

Dynamic Width Mux (RD)

Q[15:0] [15:0] 16x16

16x16 D[15:0] [15:0]

16

1:16 Demux

16

16:1 mux

16/t

CC

16

DQ15…DQ0

DQN15…DQN0

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Simultaneous Precharge

When the XDR DRAM supports multiple bank sets as in Figure 52, another feature may be supported, in

addition to ERAW. This feature is simultaneous precharge, and the timing of several cases is shown in Figure 53.

The t parameter specifies the minimum spacing between packets with precharge commands in XDR DRAMs

PP

with a single bank set, or between packets to the same bank set in a XDR DRAM with multiple bank sets. The

t

parameter specifies the minimum spacing between packets with precharge commands to different bank sets

PP-D

in a XDR DRAM with multiple bank sets.

In Figure 53, Case 4 shows an example when both t and t

PP PP-D

must be at least 4 × t . In such a case,

CYCLE

precharge commands to different bank sets satisfy the same constraint as precharge commands to the same bank

set.

In Figure 53, Case 2 shows an example when t must be at least 4 × t

PP CYCLE

and t must be at least 2 ×

PP-D

t . In such a case, a precharge command to one bank set may be inserted between two precharge commands

CYCLE

to a different bank set.

In Figure 53, Case 1 shows an example when t must be at least 4 × t

and t must be at least 1 ×

PP-D

PP CYCLE

t . As in the previous case, a precharge command to one bank set may be inserted between two precharge

CYCLE

commands to a different bank set. In this case, the middle precharge command will not be symmetrically placed

relative to the two outer precharge commands.

In Figure 53, Case 0 shows an example when t must be at least 4 × t

PP CYCLE

and t must be at least 0 ×

PP-D

t . This means that two precharge commands may be issued on the same CFM clock edge. This is only

CYCLE

possible by using the delay mechanism in one of the two commands. See “Dynamic Request Scheduling” on page 20.

It is also possible by taking advantage of the fact that two independent precharge commands may be encoded

within a single ROWP packet. In the example shown, the ROWP packet contains both a REFP command and a

PRE command. Both precharge commands will be issued internally to different bank sets on the same CFM clock

edge.

Figure 53. Simultaneous Precharge – tPP-D Cases

Case 4: t

= 4*t

Case 2: t

= 2*t

PP-D

CYCLE

PP-D

CYCLE

REFP & PRE have same t

REFP fits between two PRE

RR.

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

CFM

CFMN

t

CYCLE

RQ11

PRE

REFP

PRE

t

REFP

PRE

…RQ0

t

PP-D

Note – REFP is directed to bank

set different from two PRE

DQ15…0

t

PP

DQN15…0

Case 1: t

= 1*t

Case 0: t

= 0*t

PP-D CYCLE

PP-D

CYCLE

REFP fits between two PRE

REFP simultaneous with PRE

T₉T₁₀T₁₁T₁₂T₁₃T₁₄T₁₅T₁₆T₁₇T₁₈T₁₉T₂₀T₂₁T₂₂T₂₃

T₀

T₁

T₂

T₃

T₄

T₅

T₆

T₇

T₈

CFM

CFMN

t

CYCLE

RQ11

PRE REFP

PRE

REFP

…RQ0

t

PP-D

Note – REFP is directed to bank

set different from two PRE

Note – REFP is directed to bank

set different from PRE at T

t

12

PP-D

DQ15…0

t

PP

t

PP

DQN15…0

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Operating Conditions

Electrical Conditions

Table 12 summarizes all electrical conditions (temperature and voltage conditions) that may be applied to the

memory component. The first section of parameters is concerned with absolute voltages, storage and operating

temperatures, and the power supply, reference, and termination voltages.

The second section of parameters determines the input voltage levels for the RSL RQ signals. The high and low

voltages must satisfy a symmetry parameter with respect to the V

.

REF, RSL

The third section of parameters determines the input voltage levels for the RSL SI (serial interface) signals. The

high and low voltages must satisfy a symmetry parameter with respect to the V

.

REF, RSL

The fourth section of parameters determines the input voltage levels for the CFM clock signals. The high and low

voltages are specified by a common-mode value and a swing value.

The fifth section of parameters determines the input voltage levels for the write data signals on the DRSL DQ

pins. The high and low voltages are specified by a common-mode value and a swing value.

Table 12. Electrical Conditions

SYMBOL

IN, ABS

PARAMETER

Voltage applied to any pin (except V ) with respect to GND

MIN

MAX

UNIT

V

−0.300

−0.500

−50

V

+ 0.300

+ 0.500

100

V

DD

,

Voltage on V

with respect to GND

DD

DD ABS

T

Storage temperature

°C

V

STORE

C

Case temperature under bias during normal operation

TBD

V

Supply voltage applied to V

pins during normal operation

DD

1.80 − 0.060

1.80 + 0.060

DD

V

a

TERM, RSL

− 0.450 − 0.025

TERM, RSL

− 0.450 + 0.025

RSL − Reference voltage applied to V

REF

V

REF, RSL

V

RSL − Termination voltage applied to V

RSL RQ inputs − low voltage

pins

1.200 − 0.060

1.200 + 0.060

V

TERM, DRSL

IL, RQ

TERM

V

− 0.450

+ 0.150

V

− 0.150

+ 0.450

REF, RSL

b

RSL RQ inputs − high voltage

IH, RQ

RSL RQ inputs − data asymmetry:

R

A, RQ

TBD

V

R

A, RQ

= (V

− V

)/(V

REF, RSL

− V

)

IL, RQ

IH, RQ

REF, RSL

V

RSL Serial Interface inputs − low voltage

RSL Serial Interface inputs − high voltage

RSL RQ inputs − data asymmetry:

V

− TBD

+ TBD

V

− TBD

+ TBD

V

IL, SI

IH, SI

REF, RSL

V

REF, RSL

b

V

R

TBD

V

A, SI

R

A, SI

= (V

− V

)/(V

REF, RSL

− V

)

IL, RQ

IH, RQ

REF, RSL

CFM/CFMN input − common mode:

V

−

V

−

TERM, DRSL

0.150

TERM, DRSL

0.075

V

b

ICM, CFM

ISW, CFM

ICM, DQ

ISW, DQ

V

= (V

+ V

)/2

IL, CFM

ICM, CFM

IH, CFM

CFM/CFMN input − high-low swing:

V

0.150

0.300

b

V

= (V

− V

)

IL, CFM

ISW, CFM

IH, CFM

DRSL DQ inputs − common mode:

V

TERM, DRSL

− 0.150

b

V

= (V

+ V )/2

IL, DQ

− 0.025

ICM, DQ

IH, DQ

DRSL DQ inputs − high-low swing:

0.050

0.300

b

V

= (V

− V

)

IL, DQ

ISW, DQ

IH, DQ

a

b

V

is typically 1.2000 V ± 0.060 V. It connects to the RSL termination components, not to this DRAM component.

TERM, DRSL

is typically equal to V

or V

(whichever is appropriate) under DC conditions in an system.

TERM, DRSL

IH

TERM, RSL

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Timing Conditions

Table 13 summarizes all timing conditions that may be applied to the memory component. The first section of

parameters is concerned with parameters for the clock signals. The second section of parameters is concerned with

parameters for the request signals. The third section of parameters is concerned with parameters for the write data

signals. The fourth section of parameters is concerned with parameters for the serial interface signals. The fifth

section is concerned with all other parameters, including those for refresh, calibration, power state transitions, and

initialization

Table 13. Timing Conditions

SYMBOL

PARAMETER

MIN

MAX

3.830

UNITS

ns

Figure (s)

Figure 54

−4000

−3200

−2400

2.000

2.500

t

CYCLE

or

CFM RSL clock - cycle time

ns

CYC, CFM

3.333

0.080

40%

3.830

0.200

60%

ns

t

, t

CFM/CFMN input - rise and fall time - use minimum for test.

CFM/CFMN input − high and low times

t

Figure 54

Figure 55

R, CFM F, CFM

CYCLE

, t

t

H, CFM L, CFM

, t

RSL RQ input - rise/fall times (20% - 80%) - use minimum for test.

0.080

TBD

0.260

R, RQ F, RQ

CYCLE

ns

@ 2.500 ns > t

@ 3.333 ns > t

@ 3.830 ns ≥ t

≥ 2.000 ns

≥ 2.500 ns

≥ 3.333 ns

CYCLE

RSL RQ input to sample

points (set/hold)

t

, t

Figure 55

0.200

TBD

ns

S, RQ H, RQ

t

, t

DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test.

0.020

TBD

0.074

0.080

t

Figure 56

IR, DQ IF, DQ

CYCLE

ns

@ 2.500 ns > t

@ 3.333 ns > t

@ 3.830 ns ≥ t

≥ 2.000 ns

≥ 2.500 ns

≥ 3.333 ns

CYCLE

DRSL DQ input to sample

points (set/hold)

, t

0.0625

TBD

ns

S, DQ H, DQ

t

DRSL DQ input delay offset (fixed) to sample points

Serial Interface SCK input - cycle time

−0.080

20

t

Figure 56

Figure 58

DOFF, DQ

CYC, SCK

CYCLE

ns

, t

Serial Interface SCK input - rise and fall times

Serial Interface SCK input - high and low times

5.0

60%

5.0

ns

R, SCK F, SCK

, t

40%

5

H, SCK L, SCK

CYCLE

ns

t

Serial Interface CMD, RST, SDI input - rise and fall times

IR, SI, IF, SI

, t

Serial Interface CMD, SDI input to SCK clock edge - set/hold time

ns

S, SI H, SI

Delay from last SCK clock edge for register write to first CFM edge

with RQ packet containing a command which uses the value in the

register. Also, delay from first CFM edge with RQ packet containing

a command which modifies register value to the first SCK clock

edge for register read to this register.

t

10

t

CYCLE

DLY, SI-RQ

REF

Refresh interval. Every row of every bank must be accessed at

least once in this interval with a ROW-ACT, ROWP-REF or

ROWP-REFI command.

16

ms

Figure 41

Average refresh command interval. ROWP-REFA or ROWP-REFI

commands must be issued at this average rate. This depends upon

t

=488

ns

REFA-REFA,AVG

REFI-REFI

REFA-REFA,AVG

t

and the number of banks and the number of rows: t

=

REF

REFI

3

12

/(N *N ) = t /(2 *2 ).

B

R

REF

Refresh/increment command interval. The interval between two

ROWP-REFI commands.

16

t

CYCLE

Refresh burst limit. The number of ROWP-REFA or ROWP-REFI

commands which can be issued consecutively at the minimum

command spacing.

N

128

commands

REFA, BURST

Refresh burst interval. The interval between a burst of

t

N

_{REFA,BURST,MAX}ROWP-REFA or ROWP-REFI commands and the

TBD

100

t

BURST-REFA

CYCLE

ms

next ROWP-REFA or ROWP-REFI command.

t

, t

Current calibration interval

Figure 42

CALC CALZ

w/ PRE or REFP command

w/ any other command

4

16

30

6

Delay between packet with any

command and CALC packet

t

CMD-CALC

CYCLE

t

Delay between CALC packet and CALE packet

Delay between CALE packet and packet with any command

Last command before PDN entry

t

Figure 42

Figure 43

CALCE

CYCLE

CALE-CMD

CMD-PDN

PDN-CFM

CFM-PDN

PDN-CMD

16

4096

RSL CFM/CFMN stable after PDN entry

RSL CFM/CFMN stable before PDN exit

First command after PDN exit (includes lock time for CFM/CFMN)

a: Maximum of 128 ROWP-REFA / ROWP-REFI commands can be posted to XDR DRAM.

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TC59YM916AMG24A,32A,32B,40B

Operating Characteristics

Electrical Characteristics

Table 14 summarizes all electrical parameters (temperature, current and voltage) that characterize this memory

component. The only exception is the supply current values (I ) under different operating conditions covered in

DD

the Supply Current Profile section.

The first section of parameters is concerned with the thermal characteristics of the memory component.

The second section of parameters is concerned with the current needed by the RQ pins and VREF pin.

The third section of parameters is concerned with the current needed by the DQ pins and voltage levels produced

by the DQ pins when driving read data. This section is also concerned with the current needed by the VTERM pin,

and with the resistance levels produced for the internal termination components that attach to the DQ pins.

The fourth section of parameters determines the output voltage levels and the current needed for the serial

interface signals

Table 14. Electrical Characteristics

SYMBOL

PARAMETER

MIN

MAX

UNIT

Θ

Junction-to-case thermal resistance

TBD

°C/Watt

µA

JC

I

RSL RQ or Serial Interface input current @ (0 ≤ V ≤ V )

DD

−10

10

I, RSL

IN

V

current @ V flowing into VREF pin

REF, RSL, MAX

µA

REF, RSL

DRSL DQ input current @ (0 ≤ V ≤ V

)

µA

I, DRSL

IN

DD

V

current @ V

flowing into VTERM

TERM, DQ, MAX

TERM, DRSL

I

TBD

mA

TERM, DRSL

pins

DRSL DQ output low current – specified @

= 0.2V w/current control tolerance

I

8 − TBD

8 + TBD

50

mA

µA

OL, DQ

V

OSW, DQ

DRSL DQ output high current

−50

OH, DQ

DRSL DQ outputs – I w/all segments on @

OL

8

16

mA

ALL, DQ

(V =0.9v, V

OL

, T , _MAX

)

DD, MIN

Q

DRSL DQ outputs – I low current resolution step

OL

0.5

OL, STEP, DQ

DRSL DQ outputs – termination conductance

-1

G

0.018

0.025

0.022

Ω

-1

TERM, DQ

(note: G

= 0.020Ω → R

= 50 Ω)

TERM

DRSL DQ outputs – G

w/all segments on @

-1

TERM

G

Ω

ALL, DQ

(V = 0.9 V, V

OL

, T

)

DD, MIN Q, MAX

-1

DRSL DQ outputs – termination conductance resolution step

RSL serial interface SDO output – low voltage

0.015

Ω

TERM, STEP, DQ

OL, SI

V

−

REF, RSL

TBD

V

0.0

V

+

REF, RSL

TBD

RSL serial interface SDO output – high voltage

V

TERM, RSL

OH, SI

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TC59YM916AMG24A,32A,32B,40B

Supply Current Profile

In this section, Table 15 summarizes the supply current (I ) that characterizes this memory component. This

DD

parameter is shown under different operating conditions.

Table 15. Supply Current Profile

Max

Symbol

Parameter

Min

@t

=

@t

=

Unit

CYCLE

2.50 ns

x.xxns

I

TBD

µA

mA

Device in PDN, Self Refresh enabled

DD, PDN

DD, STBY

DD, REF

DD, WR

Device in STBY. This is for a device in STBY with no packets

on the Channel.

TBD

Device in STBY and refreshing rows at the t

period.

REF,MAX

ACT command every t , PRE command every t , WR

RR

PP

command every t

.

CC

ACT command every t , PRE command every t , RD

RR

PP

I

TBD

mA

a

DD, RD

command every t

.

CC

a. This does not include the I

sink current. The device dissipates I

V

in each DQ/DQN pair when driving data.

OL, DQ

OL, DQ* TERM, DQ

Timing Characteristics

Table 16 summarizes all timing parameters that characterize this memory component. The only exceptions are

the core timing parameters that are speed-bin dependent. Refer to the Timing Parameters section for more

information.

The first section of parameters pertains to the timing of the DQ pins when driving read data.

The second section of parameters is concerned with the timing for the serial interface signals when driving

register read data.

The third section of parameters is concerned with the time intervals needed by the interface to transition between

power states.

Table 16. Timing Characteristics

Symbol

Parameter and Other Conditions

Min

Max

Unit

ns

Figure (s)

Figure 57

DRSL DQ output delay

@ 2.500 ns > t

@ 3.333 ns > t

@ 3.830 ns ≥ t

≥ 2.000 ns

≥ 2.500 ns

≥ 3.333 ns

TBD

−0.0625

TBD

+0.0625

TBD

CYCLE

(variation across 16 Q bits

on each DQ pin) from

drive points – output

delay

t

Q, DQ

DRSL DQ output delay offset (a fixed value for all 16 Q bits on

each DQ pin) from drive points – output delay

−0.080

+0.080

t

Figure 57

QOFF, DQ

CYCLE

t

,

OR, DQ

DRSL DQ output – rise and fall times (20% – 80%)

0.020

0.040

OF, DQ

t

Serial SDI-to-SDO propagation delay @ C

= 20 pF

15

12

15

ns

Figure 59

P, SI

Q, SI

P, SI

LOAD, MAX

Serial SCK-to-SDO output delay @ C

= 20 pF

2

LOAD, MAX

Serial SDI-to-SDO propagation delay @ C

= 20 pF

LOAD, MAX

t

,

Serial SDO output rise/fall (20% – 80%)

OR, SI

5

ns

Figure 59

@ C

= 20 pF

OF, SI

LOAD, MAX

t

Time for power state to change after PDN entry

Time for power state to change after PDN exit

16

t

Figure 43

PDN-ENTRY

PDN-EXIT

CYCLE

0

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Timing Parameters

Table 17 summarizes the timing parameters that characterize the core logic of this memory component. These

timing parameters will vary as a function of the component’s speed bin. The four sections deal with the timing

intervals between packets with, respectively, row-row commands, row-column commands, column-column

commands, and column-row commons.

Table 17. Timing Parameters

Min

(A)

Min

(B)

Symbol

Parameter and Other Conditions

Max Unit

Figure(s)

t

16

19

23

20

24

28

Row-cycle time: interval between

successive ROWA-ACT or

ROWP-REFA or ROWP-REFI

activate commands to the same

bank.

RC

a

= t

RCD-R

+ t

CC

+ t

RC-R, 2tCC

RDP RP

Figure 4

Figure 7

t

RC

CYCLE

a

= t

RCD-W

+ t

RC-W, 2tCC, noERAW

RC-W, 2tCC, ERAW

CC WRP RP

a

= t

RCD-W

+ t

CC

+ t

WRP RP

Row-asserted time: interval between a ROWA-ACT or ROWP-REFA or ROWP-REFI activate

command and a ROWP-PRE or ROWP-REFP precharge command to the same bank.

Figure 4

Figure 7

t

10

6

13

7

64µs

t

RAS

CYCLE

Row-precharge time: interval between a ROWP-PRE or ROWP-REFP precharge command

and a ROWA-ACT or ROWP-REFA or ROWP-REFI activate command to the same bank.

Figure 4

Figure 7

RP

CYCLE

t

4

1

4

1

t

PP

CYCLE

Precharge-to-precharge time: interval between successive ROWP-PRE or

ROWP-REFP precharge commands to different banks.

Figure 4

Figure 7

t

PP

b

PP-D

CYCLE

Row-to-row time: interval between ROWA-ACT or ROWP-REFA or ROWP-REFI activate

commands to different banks.

Figure 4

Figure 7

t

4

5

1

4

7

3

t

RR

CYCLE

Row-to-column-read delay: interval between a ROWA-ACT activate command and a

COL-RD read command to the same bank.

Figure 4

Figure 7

RCD-R

RCD-W

Row-to-column-write delay: interval between a ROWA-ACT activate command and a

COL-WR or COL-WRM write command to the same bank.

Figure 4

Figure 7

t

Column access delay: interval from COL-RD read command to Q read data

6

3

7

3

t

Figure 10

Figure 9

CAC

CYCLE

Column write delay: interval from a COL-WR or COLM-WRM write command to D write data.

CWD

CYCLE

Column-to-column time: interval between successive COL-RD commands, or between

successive COL-WR or COLM-WRM commands.

Figure 4

Figure 7

t

2

3

8

2

3

9

t

CC

CYCLE

t

Read-to-write bubble time: interval between the end of a Q read data packet and the start of

RW-BUB,

Figure 13

Figure 12

D write data packet (the end of a data packet is the time interval t

after its start).

XDRDRAM

CC

Write-to-read bubble time: interval between the end of a D writed data packet and the start of

Q read data packet (the end of a data packet is the time interval t after its start).

t

WR-BUB,

XDRDRAM

CC

Read-to-write time: interval between a COL-RD read command and a COL-WR or

t

c

∆RW

COLM-WRM write command.

t

9

2

10

2

t

∆WR

CYCLE

Write-to-read time: interval between a COL-WR or COLM-WRM write command

and a COL-RD read command.

t

Figure 12

∆WR

d

∆WR–D

CYCLE

Read-to-precharge time: interval between a COL-RD read command and a ROWP-PRE

precharge command to the same bank.

Figure 4

Figure 7

3

10

7

4

12

9

t

RDP

CYCLE

Write-to-precharge time: interval between a COL-WR or COLM-WRM write command and a

ROWP-PRE precharge command to the same bank.

Figure 4

Figure 7

t

WRP

Data-to-precharge time : interval between a D write data and a ROWP-PRE precharge

command to the same bank.

t

Figure 9

DP

Data-to-read time : interval between a D write data and a COL-RD read command to the

same bank.

Figure 12

Figure 13

t

6

7

DR

a. The t

parameter is applicable to all transaction types (read, write, refresh, etc). Read and write transactions may have an

RC,MIN

additional limitation, depending upon how many column accesses (each requiring t ) are performed in each row access (t ).

CC

RC

The table lists the special cases (t

, t

) in which two column accesses are

RC-R, 2tCC RC-W, 2tCC, noERAW RC-W, 2tCC, ERAW

performed in each row access. Note that t

parameters are minimum.

uses a relaxed value of t

that is equal to t

. All other

RCD-R,MIN

RC-W, 2tCC, ERAW

RCD-W

b.

t

is the t parameter for precharges to different bank sets. See “Simultaneous Precharge” on page 55.

PP-D PP

c. t RW-PD = t RW + t

+ t . See “Propagation Delay” on page 30.

PD-Q

∆

PD-Q

d. t WR-D is the t WR parameter for write-read accesses to different bank sets. See “Multiple Bank Sets and the ERAW Feature” on

∆

page 53. Also, note that the value of t WR-D may not take on the values {3,5,7} within the range{t WR-D,MIN, ... t WR,MIN-1}.

∆

t WR-D may assume any value ≥ t WR,MIN.

∆

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Receive/Transmit Timing

Clocking

Figure 54 shows a timing diagram for the CFM/CFMN clock pins of the memory component. This diagram

represents a magnified view of these pins. This diagram shows only one clock cycle.

CFM and CFMN are differential signals: one signal is the complement of the other. They are also high-true

signals — a low voltage represents a logical zero and a high voltage represents a logical one. There are two crossing

points in each clock cycle. The primary crossing point includes the high-voltage-to-low-voltage transition of CFM

(indicated with the arrowhead in the diagram). The secondary crossing point includes the

low-voltage-to-high-voltage transition of CFM. All timing events on the RSL signals are referenced to the first set of

edges.

Timing events are measured to and from the crossing point of the CFM and CFMN signals. In the timing diagram,

this is how the clock-cycle time (t

measured.

or t ), clock-low time (t ) and clock-high time (t ) are

CYC, CFM L, CFM H, CFM

CYCLE

Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals.

The rise (t ) and fall time (t ) of the signals are measured from the 20% and 80% points of the

R, CFM F, CFM

full-swing levels.

20% = V

80% = V

+ 0.2*(V

-V

)

IL, CFM

IH, CFM IL, CFM

+ 0.8*(V -V

IH, CFM IL, CFM

Figure 54. Clocking Waveforms

t

or t

CYC,CFM

CYCLE

t

H,CFM

L,CFM

Logic 1

V

IH,CFM

CFM

80%

20%

CFMN

V

IL,CFM

Logic 0

t

F,CFM

R,CFM

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TC59YM916AMG24A,32A,32B,40B

RSL RQ Receive Timing

Figure 55 shows a timing diagram for the RQ11…RQ0 request pins of the memory component. This diagram

represents a magnified view of the pins and only a few clock cycles (CFM and CFMN are the clock signals). Timing

events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its

high-voltage-to-low-voltage transition. The RQ11…RQ0 signals are low true: a high voltage represents a logical

zero and a low voltage represents a logical one. Timing events on the RQ11…RQ0 pins are measured to and from

the point that the signal reaches the level of the reference voltage V

REF, RSL

.

Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals.

The rise (t ) and fall time (t ) of the signals are measured from the 20% and 80% points of the full-swing

R, RQ F, RQ

levels.

20% = V

80% = V

+ 0.2*(V

+ 0.8*(V

-V

)

IL, RQ

IH, RQ IL, RQ

-V

IH, RQ IL, RQ

IL, RQ

There are two data receiving windows defined for each RQ11…RQ0 signal. The first of these (labeled “0”) has a set

time, t , and a hold time, t , measured around the primary CFM/CFMN crossing point. The second

S, RQ H, RQ

(labeled “1”) has a set time (t ) and a hold time (t

) measured around a point 0.5 × t after the

H, RQ CYCLE

S, R Q

primary CFM/CFMN crossing point.

Figure 55. RSL RQ Receive Waveform

t

CYCLE

CFM

CFMN

[1/2]*t

CYCLE

t

H,RQ

S,RQ

H,RQ

S,RQ

Logic 0

V

IH,RQ

80%

RQ0

0

1

V

REF,RSL

20%

V

IL,RQ

t

Logic 1

R,RQ

F,RQ

[1/2]*t

CYCLE

t

H,RQ

S,RQ

H,RQ

S,RQ

Logic 0

V

IH,RQ

80%

RQ11

0

1

V

REF,RSL

20%

V

IL,RQ

t

Logic 1

R,RQ

F,RQ

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DRSL DQ Receive Timing

Figure 57 shows a timing diagram for receiving write data on the DQ/DQN data pins of the memory component.

This diagram represents a magnified view of the pins and shows only a few clock cycles are shown (CFM and

CFMN are the clock signals). Timing events are measured to and from the primary CFM/CFMN crossing point in

which CFM makes its high-voltage-to-low-voltage transition. The DQ15…DQ0/DQN15…DQN0 signals are

high-true: a low voltage represents a logical zero and a high voltage represents a logical one. They are also

differential—timing events on the DQ15…DQ0/DQN15...DQN0 pins are measured to and from the point that each

differential pair crosses.

Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals.

The rise time (t ) and fall time (t ) of the signals are measured from the 20% and 80% points of the

IR, DQ IF, DQ

full-swing levels.

20% = V

80% = V

+ 0.2 × (V

-V

)

IL, DQ

IH, DQ IL, DQ

+ 0.8 × (V -V

IH, DQ IL, DQ

There are 16 data receiving windows defined for each DQ15…DQ0/DQN15…DQN0 pin pair. The receiving

windows for a particular DQi/DQNi pin pair is referenced to an offset parameter t (the index “i” may take

DOFF, DQi

on the values {0, 1, ..15} and refers to each of the DQ15…DQ0/DQN15…DQN0 pin pairs).

The t

DOFF, DQi

parameter determines the time between the primary CFM/CFMN crossing point and the offset

point for the DQi/DQNi pin pair. The 16 receiving windows are placed at times t

+ (j/8) × t (the

CYCLE

DOFF, DQi

index “j” may take on the values {1, 2, ..16} and refers to each of the receiving windows for the DQi/DQNi pin pair).

The offset values t

DOFF, DQi

for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained

to lie inside the range {t

_,t

}. Furthermore, each offset value t is static and will not

DOFF, DQi

DOFF, MIN DOFF, MAX

change during system operation. Its value can be determined at initialization.

The 16 receiving windows (j = 1…16) for the first pair DQ0/DQN0 are labeled “1” through “16”. Each window has a

set time (t ) and a hold time (t ) measured around a point t + (j/8) × t after the primary

S, DQ H, DQ DOFF, DQ0 CYCLE

CFM/CFMN crossing point.

The 16 receiving windows (j = 1…16) for the each of the other pairs DQi/DQNi are also labeled “1” through “16”.

Each window has a set time (t ) and a hold time (t ) measured around a point t + (j/8) × t

S, DQ H, DQ DOFF, DQi CYCLE

after the primary CFM/CFMN crossing point.

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TC59YM916AMG24A,32A,32B,40B

Figure 56. DRSL DQ Receive Waveform

t

CYCLE

CFM

CFMN

i = {0,1,2,3,4,5,…15}

t

DOFF,MAX

j = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}

t

DOFF,MIN

[( j )/8]*t

CYCLE

t

DOFF,DQ0

S,DQ H,DQ

Logic 1

V

IH,DQ

DQ0

80%

1

2

3

4

5

6

7

j

15

16

20%

DQN0

V

IL,DQ

Logic 0

t

FI,DQ

RI,DQ

[( j )/8]*t

CYCLE

t

DOFF,DQi

S,DQ H,DQ

Logic 1

V

IH,DQ

DQi

80%

1

2

3

4

5

6

7

j

15

16

20%

DQNi

V

IL,DQ

Logic 0

t

FI,DQ

RI,DQ

[( j )/8]*t

CYCLE

t

DOFF,DQ15

S,DQ H,DQ

Logic 1

V

80%

IH,DQ

DQ15

1

2

3

4

5

6

7

j

15

16

20%

DQN15

V

IL,DQ

Logic 0

t

FI,DQ

RI,DQ

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DRSL DQ Transmit Timing

Figure 57 shows a timing diagram for transmitting read data on the DQ15…DQ0/DQN15…DQN0 data pins of the

memory component. This diagram represents a magnified view of these pins and only a few clock cycles are shown

(CFM and CFMN are the clock signals). Timing events are measured to and from the primary CFM/CFMN crossing

point in which CFM makes its high-voltage-to-low-voltage transition. The DQ15…DQ0/DQN15…DQN0 signals are

high-true: a low voltage represents a logical zero and a high voltage represents a logical one. They are also

differential — timing events on the DQ15…DQ0/DQN15…DQN0 pins are measured to and from the point that each

differential pair crosses.

Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals.

The rise (t ) and fall time (t ) of the signals are measured from the 20% and 80% points of the

OR, DQ OF, DQ

full-swing levels.

20% = V

80% = V

+ 0.2 × (V

-V

)

OL, DQ

OH, DQ OL, DQ

+ 0.8 × (V -V

OH, DQ OL, DQ

There are 16 data transmit windows defined for each DQ15…DQ0/DQN15…DQN0 pin pair. The transmitting

windows for a particular DQi/DQNi pin pair is referenced to an offset parameter t (the index “i” may take

QOFF, DQi

on the values {0, 1, ..15} and refers to each of the DQ15…DQ0/DQN15…DQN0 pin pairs).

The t + t expression determines the time between the primary CFM/CFMN crossing point

QOFF, DQi Q, DQ, MAX

and the offset point for the DQi/DQNi pin pair. The 16 receiving windows are placed at times t

QOFF,DQi

+ t

Q,DQ,

+ (j/ 8) × t

CYCLE

(the index “j” may take on the values {1, 2, ..16} and refers to each of the transmit windows

MAX

for the DQi/DQNi pin pair).

The offset values t

to lie inside the range {t

for each of the 15 DQi/DQNi pin pairs can be different. However, each is constrained

}. Furthermore, each offset value t is static; its value will

QOFF, DQi

t

QOFF, MIN, QOFF, MAX

QOFF,DQi

not change during system operation. Its value can be determined at initialization time.

The 16 transmit windows (j = 1…16) for the first pair DQ0/DQN0 are labeled “1” through “16”. Each window

begins at the time (t + t + (j/8) × t ) and ends at the time (t + t

+ ((j

QOFF, DQ0 Q, DQ, MAX CYCLE QOFF, DQ0 Q, DQ, MIN

+ 1)/8) × t

CYCLE

) measured after the primary CFM/CFMN crossing point.

The 16 transmit windows (j=1…16) for the other pairs DQi/DQNi are also labeled “1” through “16”. Each window

begins at the time (t + t + (j/8) × t ) and ends at the time (t + t + ((j +

QOFF, DQi Q, DQ, MAX CYCLE QOFF, DQi Q, DQ, MIN

1)/8) × t

CYCLE

) measured after the primary CFM/CFMN crossing point.

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TC59YM916AMG24A,32A,32B,40B

Figure 57. RSL DQ Transmit Waveforms

t

CYCLE

CFM

CFMN

i = {0,1,2,3,4,5,…15}

t

QOFF,MAX

j = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}

t

QOFF,MIN

[ ( j )/8 ]*t

CYCLE

[ (j-1)/8 ]*t

CYCLE

Logic 1

t

Q,DQ,MIN

Q,DQ,MAX

V

OH,DQ

DQ0

80%

t

QOFF,DQ0

1

2

3

4

5

6

7

8

j

15

16

20%

DQN0

V

OL,DQ

Logic 0

t

RO,DQ

FO,DQ

[ ( j )/8 ]*t

CYCLE

[ (j-1)/8 ]*t

CYCLE

Logic 1

t

Q,DQ,MIN

Q,DQ,MAX

V

OH,DQ

DQi

80%

t

QOFF,DQi

1

2

3

4

5

6

7

8

j

15

16

20%

DQNi

V

OL,DQ

Logic 0

t

RO,DQ

FO,DQ

[ ( j )/8 ]*t

CYCLE

[ (j-1)/8 ]*t

CYCLE

Logic 1

t

Q,DQ,MIN

Q,DQ,MAX

V

OH,DQ

DQ15

80%

t

QOFF,DQ7

1

2

3

4

5

6

7

8

j

15

16

20%

DQN15

V

OL,DQ

Logic 0

t

FO,DQ

RO,DQ

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TC59YM916AMG24A,32A,32B,40B

Serial Interface Receive Timing

Figure 58 shows a timing diagram for the serial interface pins of the memory component. This diagram represents

a magnified view of the pins only a few clock cycles.

The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage

represents a logical one. Timing events are measured to and from the V

REF, RSL

measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (t

level. Because timing intervals are

and t

)

RI, SI

R, SCK

and fall time (t

and t ) of the signals are measured from the 20% and 80% points of the full-swing levels.

IF, SI

F, SCK

20% = V

+ 0.2 × (V

+ 0.5 × (V

+ 0.8 × (V

- V

)

IL, SI

IH, SI

IL, SI

50% = V

80% = V

There is one receiving window defined for each serial interface signal (RST, CMD and SDI pins). This window has

a set time (t ) and a hold time (t ) measured around the falling edge of the SCK clock signal.

S, RQ H, RQ

Figure 58. Serial Interface Receive Waveforms

t

CYC,SCK

t

H,SCK

L,SCK

Logic 0

V

IH,SI

80%

SCK

V

REF,RSL

20%

V

IL,SI

Logic 1

t

R,SCK

F,SCK

t

H,SI

S,SI

Logic 0

V

IH,SI

80%

RST

SMD

SDI

V

REF,RSL

20%

V

IL,SI

Logic 1

t

FI,SI

RI,SI

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TC59YM916AMG24A,32A,32B,40B

Serial Interface Transmit Timing

Figure 59 shows a timing diagram for the serial interface pins of the memory component. This diagram represents

a magnified view of the pins and only a few clock cycles are shown.

The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage

represents a logical one. Timing events are measured to and from the V

REF, RSL

measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (t

OR, SI

level. Because timing intervals are

) and fall

time (t ) of the signals are measured from the 20% and 80% points of the full-swing levels.

OF, SI

20% = V

50% = V

80% = V

+ 0.2 × (V

+ 0.5 × (V

+ 0.8 × (V

-V

)

OL, SI

OH, SI OL, SI

-V

OH, SI OL, SI

-V

OH, SI OL, SI

There is one transmit window defined for the serial interface data signal (SDO pins). This window has a

maximum delay time (t ) from the falling edge of the SCK clock signal and a minimum delay time (t

Q, SI, MAX Q, SI,

) from the next falling edge of the SCK clock signal.

MIN

When the memory component is not selected during a serial device read transaction, it will simply pass the

information on the SDI input to the SDO output. This combinational propagation delay parameter is t . The

P, SI

value for a serial

t

will need to be increased during a serial read transaction (relative to the t

CYC, SCK

write transaction) because of the accumulated propagation delay through all of the XDR DRAM devices on the

serial interface.

During Initialization, when the serial identification is determined, the SDI-to-SDO path is registered, so the t

CYC,

value can be set to the same value as for serial write transactions. See ”Initialization” on page 45.

SCK

Figure 59. Serial Interface Transmit Waveforms

t

CYC,SCK

t

H,SCK

L,SCK

Logic 0

V

IH,SI

80%

SCK

V

REF,RSL

20%

V

IL,SI

Logic 1

t

R,SCK

F,SCK

t

Q,SI,MIN

Q,SI,MAX

Logic 0

V

OH,SI

80%

t

P,SI

SDO

V

REF,RSL

20%

V

OL,SI

Logic 1

t

FO,SI

RO

Combinational propagation from SDI to

SDO when the device is not selected

during a serial device read transaction.

Logic 0

V

IH,SI

80%

SDI

V

REF,RSL

20%

V

IL,SI

Logic 1

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TC59YM916AMG24A,32A,32B,40B

Package Description

Package Parasitic Summary

Table 18 summarizes inductance, capacitance, and resistance values associated with each pin group for the

memory component. Most of the parameters have maximum values only, however some have both maximum and

minimum values.

The first group of parameters are for the CFM/CFMN clock pair pins. They include inductance, capacitance, and

resistance values.

The second group of parameters are for the RQ request pins. They include inductance, mutual inductance,

capacitance, and resistance values. There are also limits on the spread in inductance and capacitance values

allowed in any one memory component.

The third group of parameters are specific to the DQ data pins and include inductance, mutual inductance,

capacitance, and resistance values. There are also limits on the spread in inductance and capacitance values

allowed in any one memory component.

The fourth group of parameters are for the serial interface pins. They include inductance and capacitance values.

Table 18. Package RSL Parasitic Summary

Symbol

VTERM

Parameter and Other Conditions

pin – effective input inductance per for bits

Min

80

Max

Units

L

V

1.2

120

TBD

2.4

nH

TERM

Z

CFM/CFMN pins – package difference impedance

Ω

PKG, CFM

−2400

−3200

−4000

a

C

R

L

CFM/CFMN pins – effective input capacitance

pF

Ω

I, CFM

TBD

15

CFM/CFMN pins – effective input resistance

RSL RQ pins – effective input inductance

4

−2400

−3200

−4000

−2400

−3200

−4000

TBD

4.0

nH

I, RQ

TBD

2.4

TBD

2.0

TBD

4

a

C

I, RQ

RSL RQ pins – effective input capacitance

pF

TBD

15

R

I, RQ

RSL RQ pins – effective input resistance

Ω

L

Mutual inductance between adjacent RSL RQ signals

0.6

nH

12, RQ

∆L

Difference in L

between any RSL RQ pins of a single device

1.8

I, RQ

K1

RQ-CFM/CFMN pins – effective RQ to CFM/CFMN differential inductive coupling coefficient.

TBD

+0.06

120

TBD

2.0

RQ, CFM

∆C

Difference in C between CFM/CFMN average and RSL RQ pins of single device

I

−0.06

pF

I, RQ

Z

DRSL DQ pins – package differential impedance

80

Ω

PKG, DQ

−2400

−3200

−4000

−2400

−3200

−4000

a

C

I, DQ

DRSL DQ pins – effective input capacitance

pF

TBD

0.06

TBD

15

a

∆C

Difference in C between DQi and DQNi of each DRSL pair

I

I, DQ

R

I, RQ

DRSL DQ pins – effective input resistance

4

Ω

b

V

S

Package near end differential crosstalk

−30

−45

−0.8

8.0

dB

nH

NEXT, DQ

FEXT, DQ

12, DQ

b

Package near end differential crosstalk

Differential mode insertion loss

L

I, SI

Serial Interface effective input inductance

c

(RST, SCK, CMD)

(SDI, SDO)

1.7

2.1

C

I, SI

Serial Interface effective input capacitance

pF

7.0

a. These values are dependent upon the interface speed bin of the component. See “Key Timing parameters /Part Numbers” on

page 1. This is the effective die input capacitance, and does not include package capacitance.

b.

V

and V

are measured when package signals are terminated at differential impedance of 100 Ω

FEXT

2003-07-10 70/74

TC59YM916AMG24A,32A,32B,40B

Figure 60. Equivalent Circuits for Package Parasitic

Pad

RQ Pin

L

I,RQ

L

12,RQ

C

R

I,RQ

12,RQ

RQ Pin

I,RQ

GND Pin

Pad

Z

/2

DQ Pin

PKG,DQ

C

R

DQN Pin

Z

I,DQ

PKG,DQ

C

R

I,DQ

GND Pin

Pad

Z

/2

CFM Pin

PKG,CFM

CFMN Pin

C

I,CFM

PKG,CFM

C

R

I,CFM

R

I,CFM

GND Pin

Pad

L

I,SI

SCK, CMD, RST Pin

C

I,SI

GND Pin

2003-07-10 71/74

TC59YM916AMG24A,32A,32B,40B

Package Mechanical Drawing

Figure 61 illustrates the x16 XDR DRAM device package and Table 19 summarizes the mechanical parameters

for that package.

Table 19. CSP x16 Package Mechanical Parameters

Symbol

Parameter

Min

Max

Unit

e1

e2

A

Ball pitch (x-axis)

1.27

0.80

TBD

1.27

0.80

TBD

1.20

0.45

0.55

mm

Ball pitch (y-axis)

Package body length

Package body width

D

E

Package total thickness

Ball height

mm

E1

d

0.35

0.45

Ball diameter

Note:

Package length (A) and width (D) vary with die size for chip-scale package.

Figure 61. CSP x16 Package Mechanical Drawing

E1

A16

A8

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

L

K

J

D

H

G

F

d

Top

e1

E

D

C

B

A

Bottom

e2

A

E

Bottom

2003-07-10 72/74

TC59YM916AMG24A,32A,32B,40B

Package Pin Numbering

Figure 62 summarizes the device package’s pin assignments.

Figure 62. CSP x16 Package - Pin Numbering (top view)

L

K

J

H

G

F

E

D

C

B

A

1

2

DQN3 DQN9

VDD

GND

VDD

GND

VDD

SDI

DQN8 DQN2

DQ8 DQ2

DQN4 DQN14

DQ3

DQN15

DQ15

VDD

DQ9

DQ5

VDD

GND

RQ0

GND

3

RQ10

RQ11

CFM

RSRV

RQ4

RQ3

4

DQN5

CFMN

DQ4

DQ14

VDD

GND

5

VDD VTERM

GND VTERM GND

VDD

GND

VTERM VDD

VDD VTERM GND

6

GND

VDD

7

8

9

10

11

12

13

14

15

16

GND VTERN GND

GND

VDD

GND

VDD

GND

VDD

GND VTERM GND

VDD

DQN7 DQN13

DQ7 DQ13

DQN11 DQN1

DQ11 DQ1

GND

VDD

CMD

SCK

GND

VDD

GND

RST

SDO

GND

DQN12 DQN6

DQ12 DQ6

DQN0 DQN10

DQ0 DQ10

VDD

RQ9

RQ8

RQ7

RQ6

VREF

RQ5

RQ1

RQ2

VDD

GND

VDD

Note:

•

RSRV: Reserved pin

DQ8…DQ15, DQN8…DQN15 are RSRV’s for ×8

DQ4…DQ15, DQN4…DQN15 are RSRV’s for ×4

2003-07-10 73/74

TC59YM916AMG24A,32A,32B,40B

RESTRICTIONS ON PRODUCT USE

030619EBA

• The information contained herein is subject to change without notice.

• The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of

TOSHIBA or others.

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical

stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of

safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of

such TOSHIBA products could cause loss of human life, bodily injury or damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as

set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and

conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability

Handbook” etc..

• The TOSHIBA products listed in this document are intended for usage in general electronics applications

(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,

etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires

extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or

bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or

spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,

medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this

document shall be made at the customer’s own risk.

• The products described in this document are subject to the foreign exchange and foreign trade laws.

• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced

and sold, under any law and regulations.

2003-07-10 74/74


型号：	TC59YM916AMG24A
厂家：	TOSHIBA
描述：	IC 32M X 16 RAMBUS, PBGA108, LEAD FREE, CSP-108, Dynamic RAM 动态存储器内存集成电路
文件：	总74页 (文件大小：1202K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC59YM916AMG24A [TOSHIBA]

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