TC74HC652AP_07 [TOSHIBA]

CMOS Digital Integrated Circuit Silicon Monolithic Octal Bus Transceiver/Register (3-state); CMOS数字集成电路硅单片八路总线收发器/寄存器(三态)
TC74HC652AP_07
型号: TC74HC652AP_07
厂家: TOSHIBA    TOSHIBA
描述:

CMOS Digital Integrated Circuit Silicon Monolithic Octal Bus Transceiver/Register (3-state)
CMOS数字集成电路硅单片八路总线收发器/寄存器(三态)

总线收发器
文件: 总9页 (文件大小:323K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TC74HC652AP  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74HC652AP  
Octal Bus Transceiver/Register (3-state)  
The TC74HC652A is high speed CMOS OCTAL BUS  
TRANSCEIVER/REGISTER fabricated with silicon gate CMOS  
technology.  
It achieves the high speed operation similar to equivalent  
LSTTL while maintaining the CMOS low power dissipation.  
This device is bus transceiver with 3-state outputs, D-type  
flip-flops, and control circuitry arranged for multiplexed  
transmission of data directly from the internal registers.  
When the enable input GAB and GBA are held high, the A1  
thru A8 become inputs and the B1 thru B8 become outputs. When  
the GAB and GBA are held low, the A1 thru A8 become output  
and the B1 thru B8 become inputs. When GAB is low and GBA  
is high, the outputs functions of the A and B Busses are disabled.  
Weight  
: 1.50 g (typ.)  
The select inputs (SAB, SBA) can multiplex sort and real-time (transparent mode) data.  
Data on the A Bus or B Bus can be clocked into the registers on the positive going transition of either CAB or  
CBA clock inputs, respectively.  
All inputs are equipped with protection circuits against static discharge or transient excess voltage.  
Features (Note 1) (Note 2)  
High speed: f  
= 73 MHz (typ.) at V  
= 5 V  
max  
CC  
Low power dissipation: I  
= 4 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Output drive capability: 15 LSTTL loads  
Symmetrical output impedance: |I | = I  
= 6 mA (min)  
OL  
OH  
Balanced propagation delays: t  
t
pHL  
pLH  
Wide operating voltage range: V  
(opr) = 2 to 6 V  
CC  
Pin and function compatible with 74LS652  
Note 1: Do not apply a signal to any bus terminal when it is in the output mode. Damage may result.  
Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull  
down resistors.  
1
2007-10-01  
TC74HC652AP  
Pin Assignment  
IEC Logic Symbol  
2
2007-10-01  
TC74HC652AP  
Truth Table  
GAB GBA  
CAB  
X
CBA  
X
SAB  
X
SBA  
X
A
B
Function  
Inputs  
Z
Inputs  
Z
The output functions of A and B busses are  
disabled.  
(Note)  
(Note)  
L
H
Both A and B busses are used as inputs to the  
internal flip-flops. Data on the Bus will be stored  
on the rising edge of the clock.  
X
X
X
L
X
X
Outputs  
Inputs  
X
X
L
L
The data on the B bus are displayed on the A bus.  
(Note)  
(Note)  
H
H
The data on the B bus are displayed on the A bus,  
and are stored into the B storage flip-flops on the  
rising edge of CBA.  
X
L
L
X
X
X
L
H
H
(Note)  
H
H
L
L
X
X
The data in the B storage flip-flops are displayed  
on the A bus.  
Qn  
X
(Note)  
(Note)  
The data on the B bus are stored into the B  
storage flip-flops on the rising edge of CBA, and  
the stored data propagate directly onto the A bus.  
X
L
L
(Note)  
H
H
Inputs  
Outputs  
X
X
L
X
L
L
The data on the A bus are displayed on the B bus.  
(Note)  
(Note)  
H
H
The data on the A bus are displayed on the B bus,  
and are stored into the A storage flip-flops on the  
rising edge of CAB.  
X
L
L
L
H
H
X
X
X
(Note)  
H
H
H
H
X
X
The data in the A storage flip-flops are displayed  
on the B bus.  
X
Qn  
(Note)  
(Note)  
The data on the A bus are stored into the A  
storage flip-flops on the rising edge of CAB, and  
the stored data propagate directly onto the B bus.  
X
L
L
(Note)  
H
H
The data in the A storage flip-flops are displayed  
on the B bus, and the data in the B storage  
flip-flops are displayed onthe A.  
X
X
Outputs  
Qn  
Outputs  
Qn  
H
L
H
H
(Note)  
(Note)  
X: Don’t care  
Qn: The data stored into the internal flip-flops by most recent low to high transition of the clock inputs.  
Z: High impedance  
Note:  
The clocks are not internally gated with either output enable or select inputs. Therefore, data on the A  
and/or B busses may be clocked into the storage flip-flops at any time.  
3
2007-10-01  
TC74HC652AP  
Timing Chart  
System Diagram  
4
2007-10-01  
TC74HC652AP  
Absolute Maximum Ratings (Note 1)  
Characteristics  
Supply voltage range  
Symbol  
Rating  
Unit  
V
0.5 to 7  
V
V
CC  
DC input voltage  
V
0.5 to V  
+ 0.5  
IN  
CC  
CC  
DC output voltage  
Input diode current  
Output diode current  
DC output current  
V
0.5 to V  
+ 0.5  
V
OUT  
I
±20  
mA  
mA  
mA  
mA  
mW  
°C  
IK  
I
±20  
±35  
±75  
500  
OK  
I
OUT  
DC V /ground current  
CC  
I
CC  
Power dissipation  
P
(Note 2)  
D
Storage temperature  
T
stg  
65 to 150  
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or  
even destruction.  
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the  
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly  
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute  
maximum ratings and the operating ranges.  
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook  
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test  
report and estimated failure rate, etc).  
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of 10 mW/°C shall be  
applied until 300 mW.  
Operating Ranges (Note)  
Characteristics  
Supply voltage  
Symbol  
Rating  
2 to 6  
Unit  
V
V
V
CC  
Input voltage  
V
0 to V  
0 to V  
IN  
CC  
CC  
Output voltage  
V
OUT  
V
Operating temperature  
T
opr  
40 to 85  
°C  
0 to 1000 (V  
= 2.0 V)  
CC  
CC  
CC  
Input rise and fall time  
t , t  
0 to 500 (V  
0 to 400 (V  
= 4.5 V)  
= 6.0 V)  
ns  
r
f
Note:  
The operating ranges must be maintained to ensure the normal operation of the device.  
Unused inputs must be tied to either VCC or GND.  
5
2007-10-01  
TC74HC652AP  
Electrical Characteristics  
DC Characteristics  
Ta = −40 to  
Test Condition  
Ta = 25°C  
85°C  
Characteristics  
Symbol  
Unit  
V
(V)  
CC  
Min  
Typ.  
Max  
Min  
Max  
2.0  
1.50  
3.15  
4.20  
1.50  
3.15  
4.20  
High-level input  
voltage  
V
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
4.5  
6.0  
2.0  
4.5  
6.0  
4.5  
6.0  
V
V
IH  
0.50  
1.35  
1.80  
0.50  
1.35  
1.80  
Low-level input  
voltage  
V
IL  
1.9  
4.4  
5.9  
4.18  
5.68  
2.0  
4.5  
6.0  
4.31  
5.80  
0.0  
0.0  
0.0  
0.17  
0.18  
1.9  
4.4  
5.9  
4.13  
5.63  
I
= −20 μA  
OH  
V
IN  
= V or  
High-level output  
voltage  
V
OH  
V
IH  
V
IL  
I
I
= −6 mA  
OH  
= −7.8 mA  
OH  
0.1  
0.1  
0.1  
0.26  
0.26  
0.1  
0.1  
0.1  
0.33  
0.33  
I
= 20 μA  
OL  
V
IN  
Low-level output  
voltage  
V
OL  
= V or  
IL  
V
IH  
V
I
I
= 6 mA  
OL  
= 7.8 mA  
OL  
V
V
= V or V  
IH  
IN  
IL  
3-state output  
off-state current  
I
6.0  
±0.5  
±5.0  
μA  
OZ  
= V  
CC  
or GND  
OUT  
Input leakage  
current  
I
V
= V  
or GND  
6.0  
6.0  
±0.1  
±1.0  
μA  
μA  
IN  
IN  
IN  
CC  
Quiescent supply  
current  
I
V
= V  
or GND  
4.0  
40.0  
CC  
CC  
Timing Requirements (input: t = t = 6 ns)  
r
f
Ta =  
40 to  
85°C  
Test Condition  
Ta = 25°C  
Characteristics  
Symbol  
Unit  
ns  
V
CC  
(V)  
Typ.  
Limit  
75  
15  
13  
50  
10  
9
Limit  
95  
19  
16  
65  
13  
11  
5
2.0  
Minimum pulse width  
(CK)  
t
W (L)  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
t
W (H)  
Minimum set-up time  
Minimum hold time  
Clock frequency  
t
ns  
s
5
t
5
5
ns  
h
5
5
6
5
f
31  
36  
25  
29  
MHz  
6
2007-10-01  
TC74HC652AP  
AC Characteristics (input: t = t = 6 ns)  
r
f
Ta = −40 to  
Test Condition  
Ta = 25°C  
85°C  
Characteristics  
Symbol  
Unit  
CL  
(pF)  
V
CC  
(V)  
Min  
Typ.  
Max  
Min  
Max  
2.0  
6
25  
7
60  
12  
5
75  
15  
t
t
TLH  
Output transition time  
50  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
ns  
ns  
THL  
6
10  
13  
74  
21  
18  
91  
26  
22  
98  
28  
24  
116  
33  
28  
81  
23  
20  
98  
28  
24  
74  
21  
18  
91  
26  
22  
50  
21  
18  
19  
67  
79  
5
150  
30  
190  
38  
50  
150  
50  
Propagation delay  
time  
t
t
26  
32  
pLH  
190  
38  
240  
48  
pHL  
(BUS-bus)  
32  
41  
210  
42  
265  
53  
Propagation delay  
time  
t
t
36  
45  
pLH  
ns  
ns  
ns  
250  
50  
315  
63  
pHL  
(CAB, CBA-bus)  
150  
50  
43  
54  
170  
34  
215  
43  
Propagation delay  
time  
t
t
29  
37  
pLH  
210  
42  
265  
53  
pHL  
(SAB, SBA-bus)  
150  
50  
36  
45  
175  
35  
220  
44  
Propagation enable  
time  
t
t
30  
37  
pZL  
R
= 1 kΩ  
L
215  
43  
270  
54  
pZH  
(GAB, GBA -bus)  
150  
50  
37  
46  
175  
35  
220  
44  
Output disable time  
(GAB, GBA -bus)  
t
pLZ  
R
L
= 1 kΩ  
ns  
t
pHZ  
30  
37  
Maximum clock  
frequency  
f
50  
31  
36  
25  
29  
MHz  
max  
Input capacitance  
Output capacitance  
C
10  
10  
pF  
pF  
IN  
C
13  
OUT  
C
PD  
Power dissipation  
capacitance  
39  
pF  
(Note)  
Note:  
C
is defined as the value of the internal equivalent capacitance which is calculated from the operating  
PD  
current consumption without load.  
Average operating current can be obtained by the equation:  
I
(opr) = C V f + I /8 (per bit)  
PD CC IN CC  
CC  
7
2007-10-01  
TC74HC652AP  
Package Dimensions  
Weight: 1.50 g (typ.)  
8
2007-10-01  
TC74HC652AP  
RESTRICTIONS ON PRODUCT USE  
20070701-EN GENERAL  
The information contained herein is subject to change without notice.  
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor  
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical  
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of  
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of  
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.  
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as  
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and  
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability  
Handbook” etc.  
The TOSHIBA products listed in this document are intended for usage in general electronics applications  
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,  
etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires  
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or  
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or  
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,  
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his  
document shall be made at the customer’s own risk.  
The products described in this document shall not be used or embedded to any downstream products of which  
manufacture, use and/or sale are prohibited under any applicable laws and regulations.  
The information contained herein is presented only as a guide for the applications of our products. No  
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which  
may result from its use. No license is granted by implication or otherwise under any patents or other rights of  
TOSHIBA or the third parties.  
Please contact your sales representative for product-by-product details in this document regarding RoHS  
compatibility. Please use these products in this document in compliance with all applicable laws and regulations  
that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses  
occurring as a result of noncompliance with applicable laws and regulations.  
9
2007-10-01  

相关型号:

TC74HC670

4 WORDx4 BIT REGISTER FILE(3-STATE)
TOSHIBA

TC74HC670AF

4 WORDx4 BIT REGISTER FILE(3-STATE)
TOSHIBA

TC74HC670AF(EL)

IC 4 X 4 STANDARD SRAM, 34 ns, PDSO16, 0.300 INCH, PLASTIC, SOP-16, Static RAM
TOSHIBA

TC74HC670AF(EL,F)

IC,REGISTER FILE,HC-CMOS,SOP,16PIN,PLASTIC
TOSHIBA

TC74HC670AF(F)

IC,REGISTER FILE,HC-CMOS,SOP,16PIN,PLASTIC
TOSHIBA

TC74HC670AF(TP1)

IC 4 X 4 STANDARD SRAM, 34 ns, PDSO16, 0.300 INCH, PLASTIC, SOP-16, Static RAM
TOSHIBA

TC74HC670AF(TP2)

IC 4 X 4 STANDARD SRAM, 34 ns, PDSO16, 0.300 INCH, PLASTIC, SOP-16, Static RAM
TOSHIBA

TC74HC670AF-TP2EL

IC 4 X 4 STANDARD SRAM, 49 ns, PDSO16, 0.200 INCH, PLASTIC, SOIC-16, Static RAM
TOSHIBA

TC74HC670AP

4 WORDx4 BIT REGISTER FILE(3-STATE)
TOSHIBA

TC74HC670AP(F)

暂无描述
TOSHIBA

TC74HC670AP_07

CMOS Digital Integrated Circuit Silicon Monolithic 4 Word 】 4 Bit Register File (3-state)
TOSHIBA

TC74HC670P

IC SPECIALTY MEMORY CIRCUIT, PDIP16, PLASTIC, DIP-16, Memory IC:Other
TOSHIBA