TC74LVX573F_07 [TOSHIBA]

Octal D-Type Latch with 3-State Output; 八D型锁存器具有三态输出
TC74LVX573F_07
型号: TC74LVX573F_07
厂家: TOSHIBA    TOSHIBA
描述:

Octal D-Type Latch with 3-State Output
八D型锁存器具有三态输出

锁存器
文件: 总9页 (文件大小:211K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TC74LVX573F/FT  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74LVX573F,TC74LVX573FT  
Octal D-Type Latch with 3-State Output  
TC74LVX573F  
The TC74LVX573F/ FT is a high-speed CMOS octal latch with  
3-state output fabricated with silicon gate CMOS technology.  
Designed for use in 3-V systems, it achieves high-speed operation  
while maintaining the CMOS low power dissipation.  
This device is suitable for low-voltage and battery operated  
systems.  
This 8 bit D-type latch is controlled by a latch enable input  
(LE) and an output enable input ( OE ). When the OE input is  
high, the eight outputs are in a high-impedance state.  
An input protection circuit ensures that 0 to 5.5V can be  
applied to the input pins without regard to the supply voltage.  
This device can be used to interface 5V to 3V systems and two  
supply systems such as battery back up. This circuit prevents  
device destruction due to mismatched supply and input voltages.  
TC74LVX573FT  
Features  
High speed: t = 6.4 ns (typ.) (V  
= 3.3 V)  
pd  
CC  
Low-power dissipation: I  
= 4 μA (max) (Ta = 25°C)  
CC  
Input voltage level: V = 0.8 V (max) (V  
= 3 V)  
= 3 V)  
Weight  
SOP20-P-300-1.27A  
TSSOP20-P-0044-0.65A  
IL  
CC  
CC  
: 0.22 g (typ.)  
: 0.08 g (typ.)  
V
IH  
= 2.0 V (min) (V  
Power-down protection provided on all inputs  
Balanced propagation delays: t  
t
pHL  
pLH  
Low noise: V  
= 0.8 V (max)  
OLP  
Pin and function compatible with 74HC573  
1
2007-10-17  
TC74LVX573F/FT  
Pin Assignment (top view)  
IEC Logic Symbol  
(1)  
OE  
LE  
EN  
C1  
(11)  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1
2
3
4
5
6
7
8
9
20  
V
CC  
19 Q0  
18 Q1  
17 Q2  
16 Q3  
15 Q4  
14 Q5  
13 Q6  
12 Q7  
11 LE  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
(8)  
(9)  
(19)  
Q0  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1D  
(18)  
Q1  
(17)  
Q2  
(16)  
Q3  
(15)  
Q4  
(14)  
Q5  
(13)  
Q6  
(12)  
Q7  
GND 10  
Truth Table  
Inputs  
Outputs  
OE  
H
L
LE  
X
D
X
X
L
Z
Qn  
L
L
L
H
H
L
H
H
X: Don’t care  
Z: High impedance  
Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.  
System Diagram  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
2
3
4
5
6
7
8
9
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
L
L
L
L
L
L
L
L
11  
1
LE  
OE  
19  
Q0  
18  
Q1  
17  
Q2  
16  
Q3  
15  
Q4  
14  
Q5  
13  
Q6  
12  
Q7  
2
2007-10-17  
TC74LVX573F/FT  
Absolute Maximum Ratings (Note)  
Characteristics  
Supply voltage range  
Symbol  
Rating  
Unit  
V
0.5 to 7.0  
0.5 to 7.0  
V
V
CC  
DC input voltage  
V
IN  
DC output voltage  
Input diode current  
Output diode current  
DC output current  
V
0.5 to V  
CC  
+ 0.5  
V
OUT  
I
20  
mA  
mA  
mA  
mA  
mW  
°C  
IK  
I
±20  
±25  
OK  
I
OUT  
DC V /ground current  
CC  
I
±75  
CC  
Power dissipation  
P
180  
D
Storage temperature  
T
65 to 150  
stg  
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even  
destruction.  
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the  
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even  
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum  
ratings and the operating ranges.  
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook  
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test  
report and estimated failure rate, etc).  
Operating Ranges (Note)  
Characteristics  
Supply voltage  
Symbol  
Rating  
Unit  
V
2.0 to 3.6  
0 to 5.5  
V
V
CC  
Input voltage  
V
IN  
Output voltage  
V
OUT  
0 to V  
CC  
V
Operating temperature  
Input rise and fall time  
T
40 to 85  
°C  
ns/V  
opr  
dt/dv  
0 to 100  
Note: The operating ranges must be maintained to ensure the normal operation of the device.  
Unused inputs must be tied to either VCC or GND.  
3
2007-10-17  
TC74LVX573F/FT  
Electrical Characteristics  
DC Characteristics  
Ta = −40 to  
Ta = 25°C  
Sym-  
bol  
85°C  
Characteristics  
Test Condition  
Unit  
V
CC  
(V)  
Min  
1.5  
2.0  
2.4  
Typ.  
2.0  
3.0  
0
Max  
Min  
1.5  
2.0  
2.4  
Max  
2.0  
H-level  
V
IH  
3.0  
3.6  
2.0  
3.0  
3.6  
2.0  
3.0  
3.0  
2.0  
3.0  
3.0  
Input voltage  
V
0.5  
0.8  
0.8  
0.5  
0.8  
0.8  
L-level  
H-level  
L-level  
V
IL  
I
I
I
I
I
I
= −50 μA  
= −50 μA  
= −4 mA  
= 50 μA  
= 50 μA  
= 4 mA  
1.9  
2.9  
2.58  
1.9  
2.9  
2.48  
OH  
OH  
OH  
OL  
OL  
OL  
V
= V  
IL  
IN  
or V  
IH  
V
OH  
Output voltage  
V
0.1  
0.1  
0.36  
0.1  
0.1  
0.44  
V
IN  
or V  
= V  
IH  
V
0
OL  
IL  
3-state output  
V
V
V
V
= V or V  
IH IL  
IN  
I
3.6  
±0.25  
±2.5  
μA  
OZ  
Off-state current  
Input leakage current  
= V or GND  
OUT  
CC  
I
= 5.5 V or GND  
3.6  
3.6  
±0.1  
±1.0  
μA  
μA  
IN  
IN  
IN  
Quiescent supply current  
I
= V  
CC  
or GND  
4.0  
40.0  
CC  
Timing Requirements (input: t = t = 3 ns)  
r
f
Ta = −40 to  
Ta = 25°C  
85°C  
Characteristics  
Symbol  
Test Condition  
Unit  
V
(V)  
Limit  
6.5  
5.0  
5.0  
3.5  
1.5  
1.5  
Limit  
7.5  
5.0  
5.0  
3.5  
1.5  
1.5  
CC  
Minimum pulse width  
(LE)  
2.7  
t
ns  
ns  
ns  
W (H)  
3.3 ± 0.3  
2.7  
Minimum set-up time  
Minimum hold time  
t
s
3.3 ± 0.3  
2.7  
t
h
3.3 ± 0.3  
4
2007-10-17  
TC74LVX573F/FT  
AC Characteristics (input: t = t = 3 ns)  
r
f
Ta = −40 to  
Ta = 25°C  
85°C  
Characteristics  
Symbol Test Condition  
Unit  
ns  
V
(V)  
C
(pF)  
Min  
Typ.  
8.2  
10.7  
6.4  
8.9  
7.6  
10.1  
5.9  
8.4  
7.8  
10.3  
6.1  
8.6  
12.1  
10.1  
Max  
15.6  
19.1  
10.1  
13.6  
14.5  
18.0  
9.3  
Min  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
Max  
CC  
L
15  
18.5  
22.0  
12.0  
15.5  
17.5  
21.0  
11.0  
14.5  
18.5  
22.0  
12.0  
15.5  
22.0  
15.5  
1.5  
t
t
t
t
2.7  
pLH  
pHL  
pLH  
pHL  
Propagation delay time  
(LE-Q)  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
50  
50  
50  
50  
3.3 ± 0.3  
2.7  
Propagation delay time  
(D-Q)  
ns  
ns  
3.3 ± 0.3  
2.7  
12.8  
15.0  
18.5  
9.7  
t
pZL  
pZH  
R
R
= 1 kΩ  
= 1 kΩ  
Output enable time  
L
t
3.3 ± 0.3  
13.2  
19.1  
13.6  
1.5  
t
2.7  
pLZ  
ns  
ns  
Output disable time  
L
t
3.3 ± 0.3  
2.7  
pHZ  
t
t
osLH  
Output to output skew  
(Note 1)  
3.3 ± 0.3  
1.5  
1.5  
osHL  
Input capacitance  
C
IN  
(Note 2)  
4
10  
10  
pF  
pF  
pF  
Output capacitance  
C
OUT  
6
Power dissipation capacitance  
C
(Note 3)  
29  
PD  
Note 1: Parameter guaranteed by design.  
(t = |t t |, t = |t  
t |)  
pHLn  
osLH  
pLHm  
pLHn osHL  
Note 2: Parameter guaranteed by design.  
Note 3: is defined as the value of the internal equivalent capacitance which is calculated from the operating  
pHLm  
C
PD  
current consumption.  
Average operating current can be obtained by the equation:  
I
= C V f + I /8 (per latch)  
PD CC IN CC  
CC (opr)  
And the total C when n pcs. of Latch operate can be gained by the following equation:  
PD  
(total) = 21 + 8n  
C
PD  
5
2007-10-17  
TC74LVX573F/FT  
Noise Characteristics (Ta = 25°C, input: t = t = 3 ns, C = 50 pF)  
r
f
L
Limit  
Characteristics  
Symbol  
Test Condition  
Typ.  
Unit  
V
CC  
(V)  
Quiet output maximum dynamic V  
V
V
3.3  
0.5  
0.5  
0.8  
0.8  
2.0  
V
V
V
V
OL  
OLP  
Quiet output minimum dynamic V  
3.3  
3.3  
3.3  
OL  
OLV  
Minimum high level dynamic input voltage V  
V
IHD  
IH  
Maximum low level dynamic input voltage V  
V
0.8  
IL  
ILD  
Input Equivalent Circuit  
INPUT  
6
2007-10-17  
TC74LVX573F/FT  
Package Dimensions  
Weight: 0.22 g (typ.)  
7
2007-10-17  
TC74LVX573F/FT  
Package Dimensions  
Weight: 0.08 g (typ.)  
8
2007-10-17  
TC74LVX573F/FT  
RESTRICTIONS ON PRODUCT USE  
20070701-EN GENERAL  
The information contained herein is subject to change without notice.  
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor  
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical  
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of  
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of  
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.  
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as  
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and  
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability  
Handbook” etc.  
The TOSHIBA products listed in this document are intended for usage in general electronics applications  
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,  
etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires  
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or  
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or  
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,  
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his  
document shall be made at the customer’s own risk.  
The products described in this document shall not be used or embedded to any downstream products of which  
manufacture, use and/or sale are prohibited under any applicable laws and regulations.  
The information contained herein is presented only as a guide for the applications of our products. No  
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which  
may result from its use. No license is granted by implication or otherwise under any patents or other rights of  
TOSHIBA or the third parties.  
Please contact your sales representative for product-by-product details in this document regarding RoHS  
compatibility. Please use these products in this document in compliance with all applicable laws and regulations  
that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses  
occurring as a result of noncompliance with applicable laws and regulations.  
9
2007-10-17  

相关型号:

TC74LVX74F

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
TOSHIBA

TC74LVX74F(EL)

暂无描述
TOSHIBA

TC74LVX74F(EL,F)

TC74LVX74F(EL,F)
TOSHIBA

TC74LVX74F(ELP)

IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 0.300 INCH, EIAJ TYPE2, PLASTIC, SOP-14, FF/Latch
TOSHIBA

TC74LVX74F(F)

TC74LVX74F(F)
TOSHIBA

TC74LVX74FEL

暂无描述
TOSHIBA

TC74LVX74FELP

暂无描述
TOSHIBA

TC74LVX74FN

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
TOSHIBA

TC74LVX74FN(EL)

IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 0.150 INCH, PLASTIC, SOP-14, FF/Latch
TOSHIBA

TC74LVX74FN(ELP)

IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 0.150 INCH, PLASTIC, SOP-14, FF/Latch
TOSHIBA

TC74LVX74FNEL

IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 0.150 INCH, PLASTIC, MS-012AB, SOP-14, FF/Latch
TOSHIBA

TC74LVX74FNELP

IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 0.150 INCH, PLASTIC, MS-012AB, SOP-14, FF/Latch
TOSHIBA