TC90101FG [TOSHIBA]
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic; 东芝CMOS数字集成电路硅单片
| 型号： | TC90101FG |
| 厂家： | 
TOSHIBA |
| 描述： | TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic |
| 文件： | 总36页 (文件大小：393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC90101FG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
ＴＣ９０１０１ＦＧ
Y/C separation & Video Decoder
TC90101FG is a 1chip LSI of multi 3line comb and multi color decoder.
TC90101FG has 10bit ADC and 2channels 8bit ADC for analog Video signal interface
and also include Y/C separation, color decode, and signal processing circuit.
The output interface of TC90101FG is a selectable for ITUR-601 & 656.
Featurｓ
• Multi color system
• Input I/F： CVBS, Y/C, YcbCr(1H & 525p/625p)
• Multi 3 line comb (SECAM: BPF)
• Component signal frequency detection (525i/525p/625i/625p)
• AGC circuit
• Output format : 656/601
• Picture improvement
LQFP100-P-1414-0.5C
Weight：0.65g(Typ)
Ｙ： Vertical enhance/LTI/Contrast/Setup adjust
C： TOF/ACC/Color decode/color gain/CTI/offset adjust
• Noise level detection/ID1(525I & 525p) data slice/
CCD data slice/WSS data slice/ Macrovision detection
• I2C bus control
• Read data superposition on ITUR-656 output
• Package： LQFP 100 （0.5mm pitch）
• Power supply： 3.3 V， 2.5V，1.5V
Version 4.2
(note1)Thesedevices areeasy to bedamagedby high voltageor electric fields.
In regards tothis, pleasehandle with care.
●
TOSHIBA is continually working to improve the quality and the reliability of its product.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a
malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used
within specified operating ranges as set forth in the most recent products specifications. Also,
please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor
Reliability Handbook.
Feb./2005
1
TC90101FG
１．Block Diagram
42M
X'tal
HD/VD
D/A
Clock
Gene.
reference
clock
Sync Sep.
× 8
Timing
Clamp
S/N detection
macrovision
CCD slice
ID1
SW
WSS
Y
27M
10bit ADC
AGC
Vertical
enhance
LTI
CVBS
contrast adust
delay adjust
ITU-R656
encodｅ
656/601
Format
3line
27M
8bit ADC
C
27M
→ 4fsc
comb
ＡＣＣ
Cb
color decord
ＴＩＮＴ adjust
Color adjust
Cr
27M
8bit ADC
IIC-BUS
SCL SDA
２．Pin Layout
Output I/F
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76 BIASYAD
77 VRTYAD
78 YIN
1.5
TESTM5
3.3
50
49
48
1.5
VDDIO1
CKOUT
VSSYAD
VRMYAD
79
80
YOUT0 47
3.3
46
YOUT1
2.5
81 CVBS IN
82 VDDYAD
45
VSSIO1
YOUT2 44
TC90101FG
OutputI/F
Analog Input I/F
83 VRBYAD
43
42
41
YOUT3
BIASCAD
84
DVSS3
YOUT4
Top view
85 VRTCAD
86 CIN
1.5
YOUT5 40
39
87 VSSCAD
88 Cb IN
DVDD3
2.5
YOUT6 38
YOUT7 37
VDDCAD
VRBCAD
89
90
36
YOUT8
91 BIASRAD
92 VRTRAD
35
YOUT9
34
33
DVSS2
VSSRAD
93
94 Cr IN
1.5 CSYNC IN
DVDD2
2.5
32
31
30
29
28
27
26
VDDRAD
VRBRAD
95
96
TESTM4
TESTM3
97 VDDDA
TESTM2
TESTM1
SCL
98
DAOUT 2.5
99
VSSDA
1.5
3.3
100
BIASDA
2.5
SDA
3.3
NCO
DAC
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
42M
XO
X8PLL
Feb./2005
2
TC90101FG
３．Terminals discription
Piｎ
No
Piｎ
Function
Durable I/O
ｖoltage
Circuit
(Analog or Digital)
DC at
Analog signal
Amplitude
（Vp-p）
Name
（ ）：Condition at normal operation
normal
Oparation
（Ｖ）
(V)
1
2
3
VREFDA
The reference voltage terminal of DAC
2.5
2.5
2.5
Bypass
VDD
IN
1.5
-
VDDPLL
PLLIN
Power supply for X8 PLL circuit
Input terminal of X8 PLL circuit
2.5
-
Analog
1.25
0.5～
VDDPLL*0.8
4
5
6
7
8
9
VCOFIL
VSSPLL
VDDXO
XOIN
Filter terminal for X8 PLL circuit
GND for X8 PLL circuit
2.5
0
Bypass
GND
VDD
IN
1.2
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Power supply for X’ tal OSC circuit
X’ tal OSC circuit input terminal
X’ tal OSC circuit output terminal
GND for X’ tal OSC circuit
3.3
3.3
3.3
0
3.3
-
XOOUT
VSSXO
OUT
GND
I/O
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
GND
I/O
I/O
IN
-
0
10 TDIO9
11 TDIO8
12 TDIO7
13 TDIO6
14 TDIO5
15 DVDD1
16 TDIO4
17 TDIO3
18 TDIO2
19 DVSS1
20 TDIO1
21 TDIO0
22 TDCLK
23 VDDIO3
24 BUSSEL
25 RESET
26 SDA
3.3
3.3
3.3
3.3
3.3
1.5
3.3
3.3
3.3
0
-
-
Terminal for Test mode
（Normaly Open）
-
-
-
Power supply for Logic circuit
1.5
-
Terminal for Test mode
（Normaly Open）
-
-
GND for Logic circuit
0
3.3
3.3
3.3
3.3
3.3
3.3
5
-
Terminal for Test mode
（Normaly Open）
Digital
-
-
Power supply for I/O
VDD
IN
3.3
-
IICBUS slave address selection(L:B0､Hi:B2)
Reset terminal (Low :Reset Hi :normal)
IN
3.3
-
ＩＩＣ ＳＤＡ terminal (5V input possible）
ＩＩＣ ＳＣＬ terminal (5V input possible)
I/O
IN
27 SCL
5
-
28 TESTM1
29 TESTM2
30 TESTM3
31 TESTM4
32 DVDD2
33 CSYNCIN
3.3
3.3
3.3
3.3
1.5
5
IN
0
Terminal for Test mode
IN
0
（Normaly connect to GND）
IN
0
IN
0
Power supply for Logic circuit
External composite Sync signal input
（In case not use external CSYNC, conect to ＧＮＤ）
GND for Logic circuit
VDD
IN
1.5
0
34 DVSS2
35 YOUT9
0
GND
OUT
0
-
-
-
Digital video port output 9 （MSB）
（656/ 601 mode：YCbCr, 601：Y）
Digital video port output 8
3.3
36 YOUT8
37 YOUT7
38 YOUT6
39 DVDD3
40 YOUT5
41 YOUT4
42 DVSS3
43 YOUT3
44 YOUT2
45 VSSIO1
46 YOUT1
3.3
3.3
3.3
1.5
3.3
3.3
0
OUT
OUT
OUT
VDD
OUT
OUT
GND
OUT
OUT
GND
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
Digital video port output 7
Digital video port output 6
-
Power supply for Logic circuit
Digital video port output 5
1.5
-
Digital video port output 4
-
GND for Logic circuit
0
Digital video port output 3
3.3
3.3
0
-
Digital video port output 2
-
GND for I/O
0
Digital video port output 1
3.3
-
(In case 8bit output mode : fixed to Low)
Digital video port output 0
47 YOUT0
48 CKOUT
3.3
3.3
OUT
OUT
-
-
-
-
(In case 8bit output mode : fixed to Low)
System Clock output terminal for digital video signal output.
656 : 27MHz 601 : 13.5MHz
Power supply for I/O
49 VDDIO1
50 TESTM5
3.3
3.3
VDD
IN
3.3
0
-
-
Terminal for Test mode（Normaly connect to GND）
Feb./2005
3
TC90101FG
Piｎ
No
Piｎ
Function
Durable I/O
ｖoltage
Circuit
(Analog or Digital)
DC at
Analog signal
Amplitude
（Vp-p）
Name
（ ）：Condition at normal operation
normal
(V)
Oparation
（Ｖ）
51 TESTM6
52 COUT0
Terminal for Test mode（Normaly connect to GND）
ＣbＣr digital video signal output (LSB）
（656：COUT0-9 are fixed Low 601：CbCr）
（In case 16bit mode: This terminal is fixed Low)
ＣbＣr digital video signal output (2’nd LSB）
（In case 16bit mode: This terminal is fixed Low)
Power supply for Logic circuit
3.3
3.3
IN
0
-
-
-
OUT
53 COUT1
3.3
OUT
-
-
54 DVDD4
55 COUT2
56 COUT3
57 DVSS4
58 COUT4
59 COUT5
60 VDDIO2
61 COUT6
62 COUT7
63 VSSIO2
64 COUT8
65 COUT9
66 DVDD5
67 UVFLAG
68 HDOUT
69 DVSS5
70 VDOUT
71 ODD/EVEN
72 VBIREADY
1.5
3.3
3.3
0
VDD
OUT
OUT
GND
OUT
OUT
VDD
OUT
OUT
GND
OUT
OUT
VDD
OUT
OUT
GND
OUT
OUT
OUT
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ＣbＣr digital video signal output 2
ＣbＣr digital video signal output 3
-
GND for Logic circuit
0
ＣbＣr digital video signal output 4
3.3
3.3
3.3
3.3
3.3
0
-
Digital
ＣbＣr digital video signal output 5
-
Power supply for I/O
3.3
-
ＣbＣr digital video signal output 6
ＣbＣr digital video signal output 7
-
GND for I/O
0
ＣbＣr digital video signal output 8
3.3
3.3
1.5
3.3
3.3
0
-
ＣbＣr digital video signal output 9 (MSB)
Power supply for Logic circuit
-
1.5
-
Reference timing pulse for multiplexed Cb/Cr signal
Horizontal reference timing pulse
-
GND for Logic circuit
0
Vertical reference timing pulse
3.3
3.3
3.3
-
Field index output
-
Reference timing pulse of IIC read for VBI data slice
Function (Hi level at 23 line and 286 line)
Clamp gate timing pulse
-
73 CGP
3.3
3.3
3.3
2.5
2.5
2.5
0
OUT
OUT
-
-
-
74 YCLAMPP1
75 YCLAMPP2
76 BIASYAD
77 VRTYAD
78 YIN
Clamp signal output for CVBSIN
-
Clamp signal output for YIN
OUT
-
-
Bias terminal for internal 10bit ADC
Reference top voltage terminal for internal 10bit ADC
Analog Y signal input terminal (10bit ADC)
GND for internal 10bit ADC
Bypass
Bypass
IN
0.8
1.75
-
-
-
VDDYADx0.4
79 VSSYAD
80 VRMYAD
GND
0
-
-
The reference middle voltage terminal for
Internal 10bit ADC
2.5
Bypass
1.25
81 CVBSIN
82 VDDYAD
83 VRBYAD
84 BIASCAD
85 VRTCAD
86 CIN
Analog CVBS signal input terminal (10bit ADC)
Power supply for internal 10bit ADC
Reference bottom voltage terminal for internal 10bit ADC
Bias terminal for internal 8bit C/Cb-ADC
Reference top voltage terminal for internal 8bit C/Cb-ADC
Analog C signal input terminal (8bit ADC)
GND for internal 8bit C/Cb-ADC
2.5
2.5
2.5
2.5
2.5
2.5
0
IN
-
2.5
0.75
0.8
1.75
1.25
0
VDDYADx0.4
VDD
-
-
-
Bypass
Bypass
Bypass
IN
Analog
VDDCADx0.4
87 VSSCAD
88 CbIN
GND
-
Analog Cb signal input terminal (8bit ADC)
Power supply for internal 8bit C/Cb-ADC
Reference bottom voltage terminal for 8bit C/Cb-ADC
Bias terminal for internal 8bit Cｒ-ADC
Reference top voltage terminal for 8bit Cr-ADC
GND for internal 8bit Cr-ADC
2.5
2.5
2.5
2.5
2.5
0
IN
-
VDDCADx0.4
-
89 VDDCAD
90 VRBCAD
91 BIASRAD
92 VRTRAD
93 VSSRAD
94 CrIN
VDD
2.5
0.75
0.8
1.75
0
Bypass
Bypass
Bypass
GND
-
-
-
Analog Cb signal input terminal (8bit ADC)
Power supply for internal 8bit Cr-ADC
Reference bottom voltage terminal 8bit Cr-ADC
Power supply for internal DAC of NCO
Output terminal of DAC of NCO
2.5
2.5
2.5
2.5
2.5
IN
-
VDDRADx0.4
95 VDDRAD
96 VRBRAD
97 VDDDA
98 DAOUT
VDD
2.5
0.75
2.5
2
-
Bypass
VDD
-
-
OUT
VDDDA-VDDD
A*0.6
99 VSSDA
100 BIASDA
GND for internal DAC of NCO
Bias terminal for internal DAC
0
GND
0
-
-
2.5
Bypass
0.9
(Note) Please place the capacitor at near the terminal.
Please take care Surge for the IIC I/F terminals.
Feb./2005
4
TC90101FG
４．Functional Description
4.1 General Description
TC90101FG is a Video decoder device for multi color system (525i. 625i).
TC90101FG also has a through mode and sync processing for 525p & 625p component signal.
1.TC90101FG has input interface for CVBS，S-Video, YＣbＣr. For RGB signal it needs some
external circuit as below.
CVBS
LPF
Y
G
SCART
AMP/LPF
AMP/LPF
TC90101FG
RGB → YCbCr
Ｃb
Ｃr
Ｂ
R
AMP/LPF
CGP
2. Automatic clamp control circuit.
3. Multi 3line comb filter.
4. Multi color decoder and sync processing.
5. Color system detection circuit. (Selectable auto detection and manual setting.)
Result of color system dtection can be read via IIC.
6. Frequncy detection circuit for 525i/525p/625i/625p for component signal.
7. AGC circuit circuit at after stage of ADC.
8. Picture processing circuit for CVBS, S-Video, 525i/625I component signal.
9. Selectable ITUR-601, ITUR-656 output interface.
10. VBI data slice function (525i ID-1/525p ID-1/ CCD/ WSS). It can be read via IIC.
11. Macrovision detection circuit.
12. Noise level detection circuit.
13. Superposition function for IIC read data on ITUR-656 ouitput.
4.2 Fanctional Discription
1. Clock System
TC90101FG has a digital VCO circuit which uses 42MHz free run X’tal OSC.
Digital VCO circuit generates 27MHz fH clock for input stage, 4fsc clock for internal comb block
And 13.5MHz for output stage.
2.0 Input interface
Input signal
CVBS
Y(S-Video & Component )
Pin name
CVBS IN
YIN
CIN
Cb IN
Cr IN
Terminal
81
78
86
88
94
C(S-Video & Component )
Cb
Cr
2.1 Selection input signal
Input signal can be set via INSEL at sub address 00hex.
INSEL : 00 : CVBS 01: S-Video 10: YCbCr 11: SCART( ** )
( * ) : it’s not available to input RGB signal dilectlly.
It’s needs RGB to YCbCr conversion circuit at the before stage of TC90101FG.
In this mode CVBS must be inputted to CVBIN for sync processing, noise dtection and
VBI data slice.
Feb./2005
5
TC90101FG
2.2 Input signal amplitude
TC90101FG has a 10bit ADC for CVBS & Y signal and 2ch 8bit ADC for C & Cb/Cr.
The Dynamic range of ADC is desgned as AVDD *0.4 (Normally 1Vpp at AVDD = 2.5V).
The recomemdation amplitude of the input signal : 0.7Vpp at 140IRE (CVBS/Y) . refer to fig-1.
* in case of AGC ON, recommendation input signal amplitude is 0.6Vpp (140IRE).
(AGC control range is from - 6dB to +3dB.)
<Lsb>
1023
<IRE>
100
80
767
AVDD×0.4V
60
40
20
0.7Vp-p
0
256
-20
-40
51
0
Fig-1. Amlitude of CVBS input
<Lsb>
255
〈IRE〉
20
0
153
128
0.2Vp-p
-20
103
0
Fig-2. Amlitude of C input
<Lsb>
255
217
0.7Vp-p
128
39
0
Fig-3. Amlitude of base band C signal input
Feb./2005
6
TC90101FG
The amplitude of input signal for 10bit ADC is 0.7Vp-p as 140IRE. in case of C signal for S-video.
The amplitude of input signal for C ADC is 0.2Vp-p as 40IRE. (Refer to Fig-2.)
The amplitude of input signal for Cb/Cr is 0.7Vp-p as 100% level. (Refer to Fig-3.) (VDD = 2.5V)
Input signal vs output signal level
Input signal
Input signal amplitude：
Vp-p（※）
Ouput signal level（LSB）
CVBS
Ｙ
16-235(pedestal to white 100%) （8bit mode）
16-235(pedestal to white 100%) （8bit mode）
16-240（8bit mode）
0.7Vp-p（500mVp-p）
0.7Vp-p（500mVp-p）
0.2Vp-p（Burst）
C
Cb
Cr
0.7Vp-p (100% color)
0.7Vp-p (100% color)
16-240（8bit mode）
16-240（8bit mode）
※ Input signal amplitude： For CVBS and Y, it means 100% level (140IRE).
(500mVp-p: pedestal to white 100%.)
Cb/Cr, it means 100% color bar Signal.
Notice: Ｔｈｅｓｅ amplitude of output signal have done by initial value of IIC registers related with gain.
3. Clamping
The clam control circuit controls the corect clamping for input signals.
TC90101FG has a feed back clamp for H-Sync portion of CVBS/Y input signal to clamp 256LSB(10bit unit).
It is selectable to use the 2 types of the feed back clamp (internal circuit or external circuit) via
IIC bus. (FBCLMPEX at sub address 03 hex.)
In case use external, the clamp signal from YCLAMP1,YCLAMP2(pin 74,75) to be connected with input
Terminals. (refer to application circuit.)
For C signal, it is biased to 128 LSB. For Cb and Cr signal, it is used keed clamping control to 128 LSB.
Pin
number
Input mode Input signal
ADC
Clamping function
Feed back clamp
Comment
Time constant is selectable for
internalClamping mode via BUS
FBCLMOD atSub address 32hex.
Biased to 128LSB
10bit
10bit
CVBS
CVBS
Y
81
78
S- Video/
YCbCr
8bit
8bit
8bit
－
C
86
88/94
81
78
88/94
Keed clamp
Sync chip clamp
Feed back clamp
Cb/Cr
CVBS
Y
CVBS+
YCbCr
(1H)
10bit
8bit(ＭＰＸ) Keed clamp
Cb/Cr
4. TV system detection for CVBS and S- Video input
TC90101FG has 4 types of detection mode and it is selectable via AUTDET at sub address 00hex.
AUTODET
00
Mode
Manual setting
Fsc detection
-
Commemt
TV system is set via TV0 – TV3 at sub address 00hex.
Priority : 4.43MHz PAL→ NTSC→ SECAM
(it’s not available to detect 3.58MHz PAL signal.)
4.4336MHz
3.57954MHz
3.57954MHz
3.5756MHz
3.5820MHz
4.4336MHz
3.57954MHz
3.5756MHz
3.5820MHz
EU
01
Priority : 3.58MHz PAL→ 3.58MHz NTSC
(it’s not available to detect 4.43MHz fsc signal.)
10
South America
Full multi
Priority : PAL→ NTSC→ SECAM
11
There is not priority for 50Hz/60Hz(Vertical frequency) detection.
VD output (pin 70) is controled via VD.DET at sub address 23hex.
[00] : free run.
[01] : fixed mode when it detects no signal (The frequency of VDOUT is depends on TVM2.)
[10]: Fixed Frequency at Manual setting mode.
[11]: VDOUT is depends on TVM2 at all of TV system detection mode.
Feb./2005
7
TC90101FG
5. H/V Sync processing
TC90101FG has H/V sync separation circuit and regenrates HD/VD pulse.
The phase and width of HD/VD pulse are controled via THRHV at sub address 22hex.
[0] : 656 format.
[1] : Syncronized with input signal.
6. D2 signal (525p/525p component) processing
TC90101FG has D1 and D2 detection circuit and Sync processing for D2 signal.
D2 signal is converted as 4:2:2 digital signal by internal ADC. (Sampling rate of Y ADC is 27MHz.)
ID-1 data slice for 525p is available but It’s not available to use picture implrovement function and
Noise level detection, (The sliced data of ID-1 can be read via IIC.)
7. T.O.F (Take Off filter)
TC90101FG has Take Off filiter which is in front of color decoder.
Characteristic of T.O.F is set via TOF at sub address 0C hex.
[000] : Off [001] : type 1- [111] : type 7
(Type 1 : BPF.)
8. Y process
a) Vertical enhancement : adjustable coring, gain, and non-linear performance
b) LTI function
The performance of this function is controlled via Iregisters at 04 and 05 hex.
f0 : 3.3MHz / 2.2MHz
Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE
Gain : Off / 1/8 / 1/4 / 1/2
c) Sharpness
The performance of this function is controlled via Iregisters at 02 and 03 hex.
f0 : 4.2MHz / 3.3MHz
Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE
Gain : -1/4 - Off - 1/2
LTI
＋
Sharpness/
Noise canceｌ
ｆ0/Gain/Coring
ｆ0/Gain/Coring
d) Noise canceller
The performance of this function is controlled via Iregisters at 04 hex.
f0 : 4.2MHz / 3.3MHz ( It uses same register with f0 of sharpness control.)
Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE
Gain : -1/4 - Off - 1/2
e) Contrast
Control range : ×(1/2) - ×2.4
f) Brightness
it’s effective at the periode of picture signal portion.
Control range : -128LSB - 128LSB ( 10bit unit)
9. C process
a) ACC control : A reference level is set up by register ACC LEVEL.
b) Killer control : sensitivity of killer is set via [BUS KILLV] at sub address 37 hex.
In case Killer detection, comb filter for Y becomes off.
c) HUE control : Hue control is available for CVBS and C signal of NTSC system.
Hue bias : 0 --- +45degree
Hue range : -45 degree --- +43.6degree
d) Sub color gain control
Amplitude of Cb and Cr signals are controlled via IIC.
Control range is –6dB --- +2.8dB
Feb./2005
8
TC90101FG
e) CTI function
f0 is selectable (1.7MHz/ 3.3MHz).
Coring level is selectable (0.4IRE/ 0.8IRE/ 1.6IRE/ 3.2IRE).
Gain is selectable (OFF/ x1/8 / x1/4 / x1/2).
f) Offset control of the period of picture area
The DC level of the Cb and Cr signals are controlled via IIC independently.
Control range : -8LSB ---- +7LSB (10bit unit)
10. Output format
Output format (data format/clock/phase) is controlled via IIC Bus.
Y：The Pedestal level is 16LSB at 8bit output format and 64LSB at 10bit output format.
C：The signal level is 128LSB except for picture periode at 8bit output mode. (10bit mode: 512LSB)
The output format (656/601) is set via FORMATO (01h,D3) and the Dynamic range is set via OUTBITS(01h､D2)
Picture periode of Y output can be controlled by CLP (20h,D0).
CLP = [1] : the signal of under 16LSB (8bit mode) is sliced at 16LSB. (standard mode.)
CLP = [0] : It’s available to output the signal of under 16LSB.
Normaly it must be set [1].
Output Terminals
YOUT [0-9] (note)
COUT [0-9] (note)
Bit
10
10
Data rate
13.5MHz/27MHz
(601/656)
Comment
Y/YCｂCr（601/656）
6.75MHz
Cｂ/Cｒ（CLK：13.5MHz）
Reference timing pulse for Cb/Cr
Polarity : Cr = High(Initial value)
864fH/1728fH：625line source
858fH/1716fH：525line source
Polarity : Reversal(Initial value)
Re-generated HD
Re- generated VD
Field indication
Flag after VBI data slicing
UVFLAG
1
1
(13.5/2)MHｚ
13.5MHz/27MHz(/54M
Hz)
CKOUT (note)
HDOUT
VDOUT
ODDEVEN
VBIREADY
1
1
1
1
ｆH
ｆV
ｆV
ｆＶ
Note : YOUT, COUT, CKOUT has Hi impeadance mode. (01h,D1)
a) 525ｉ/60Hz CVBS input mode
５２５ꢀꢀꢀ１ꢀꢀꢀꢀ２ꢀꢀꢀꢀꢀ３ꢀꢀꢀꢀꢀ４ꢀꢀꢀꢀ５ꢀꢀꢀꢀꢀ６ꢀꢀꢀꢀ７ꢀꢀꢀꢀ８ꢀꢀꢀꢀꢀ９ꢀꢀꢀꢀꢀ１０ ꢀꢀ…ꢀꢀꢀꢀ１９ꢀꢀꢀꢀꢀ２０
ＣＶＢＳ
ＨＤＯＵＴ
ＶＤＯＵＴ
Sync Through
Mode
ＯＤＤ/ＥＶＥＮ
FIELD 1
ＶＤＯＵＴ
656
拠
Mode
FIELD 1
ＯＤＤ/ＥＶＥＮ
（1ｓｔ Field）
Selectable Sync through mode and 656 mode via THRHV at sub address 22hex.
656： Field１： Line 4 EAV
Ｆｉｅｌｄ Ｂｌａｎｋｉｎｇ ； Ｓｔａｒｔ→ Line 1 EAV、 Ｆｉｎｉｓｈ→ Line 10 EAV
VBI READY： High level output → from Line 23 SAV to Line 24 EAV
Feb./2005
9
TC90101FG
（2nd Field）
２６３
２６４ ２６５
２６６
２６７ ２６８
２６９ ２７０ ２７１
２７２
２７３
…
２８２
ＣＶＢＳ
ＨＤＯＵＴ
ＶＤＯＵＴ
Sync Through
Mode
ＯＤＤ/ＥＶＥＮ
FIELD 2
ＶＤＯＵＴ
656
Mode
ＯＤＤ/ＥＶＥＮ
FIELD 2
Selectable Sync through mode and 656 mode via THRHV at sub address 22hex.
656： Field 2： Line 266 EAV
Ｆｉｅｌｄ Ｂｌａｎｋｉｎｇ ； Ｓｔａｒｔ→ Line 264 EAV、 Ｆｉｎｉｓｈ→ Line 273 EAV
VBI READY： High level output → from Line 286 SAV to Line 287 EAV
b) 625ｉ/50Hz CVBS input mode
（1ｓｔ, 3rd Field）
６２１
６２２
６２３
６２４ ６２５
１
２
３
４
５
６
…
２２
２３
ＣＶＢＳ
ＨＤＯＵＴ
ＶＤＯＵＴ
Sync Through
ﾞ
Mode
FIELD 1
ＯＤＤ/ＥＶＥＮ
ＶＤＯＵＴ
656
Mode
ＯＤＤ/ＥＶＥＮ
FIELD 1
Selectable Sync through mode and 656 mode via THRHV at sub address 22hex.
656： Field１： Line 1 EAV
Ｆｉｅｌｄ Ｂｌａｎｋｉｎｇ ； Ｓｔａｒｔ→ Line 624 EAV、 Ｆｉｎｉｓｈ→ Line 23 EAV
VBI READY： High level output → from Line 64 SAV to Line 65 EAV
Feb./2005
10
TC90101FG
（2nd ,4th Field）
ＣＶＢＳ
３０９ꢀꢀꢀ３１０ꢀꢀ ３１１ꢀꢀ３１２ꢀꢀ ３１３ꢀꢀ ３１４ꢀꢀ ３１５ꢀꢀ３１６ꢀꢀꢀ３１７ꢀꢀ３１８ꢀꢀ ３１９ ꢀꢀ …ꢀꢀꢀꢀ３３５ꢀꢀ３３６
ＨＤＯＵＴ
ＶＤＯＵＴ
Sync Through
Mode
FIELD 2
ＯＤＤ/ＥＶＥＮ
656
ＶＤＯＵＴ
Mode
拠
ﾓｰﾄﾞ
ＯＤＤ/ＥＶＥＮ
FIELD 2
Selectable Sync through mode and 656 mode via THRHV at sub address 22hex.
656： Field 2： Line 313 EAV
Ｆｉｅｌｄ Ｂｌａｎｋｉｎｇ ； Ｓｔａｒｔ→ Line 311 EAV、 Ｆｉｎｉｓｈ→ Line 336 EAV
VBI READY： High level output → from Line 377 SAV to Line 378 EAV
The pulse width of HD/VD output at Sync through mode
525i
625i
HD pulse width
4.74μｓ
(128 cycle (unit: 27MHz clock)
３Ｈ 2.5H
VD pulse width
Notice： 656 output mode
The width of HD pulse is same as the period of between EAV and SAV.
In case of input non standard signal, it may not be above value.
Feb./2005
11
TC90101FG
11. Feature function
a) S/N detection (noise level detection)
Noise level detection is performed in the vertical blanking period. The result of noise level detection is
stored to IIC read register and it is performed at every field.
The related write registers are as follows.
EN NOISEV S (sub address 1B hex) : Setup of start line for noise detection.
EN NOISEV W (sub address 1A hex) : Setup of the numbers of lines for noise detection .
EN NOISEH S (sub address 1A hex) : Setup of start position for noise detection at selected line.
EN NOISEH W(sub address 1A hex) : Setup of the period for noise detection at selected line.
Reference position
5.3μs
EN NOISEH W
EN NOISEH S
b-1) Video ID (ID-1) data slice function for NTSC 525i signal (CVBS/S-video/Component)
ID-1 data slicing is performed at line 20 and 283 in the vertical blanking period.
The sliced data is stored to IIC read register and it is performed at every field.
b-2) Video ID (ID-1) data slice function for NTSC 525p signal (Component)
ID-1 data slicing is performed at line 41 in the vertical blanking period for NTSC 525p signal.
The sliced data is stored to IIC read register and it is performed at every vertical blanking periode.
c) CCD data slice function for US area(NTSC 525i signal (CVBS))
CCD data slicing is performed at line 21 and 284 in the vertical blanking period.
The sliced data is stored to IIC read register and it is performed at every field.
CRI detection, start bit detection and sliced data can be read via IIC bus.
d) WSS data slice function for EU area (PAL 625i signal (CVBS))
WSS data slicing is performed at line 23 and 336 in the vertical blanking period.
The sliced data is stored to IIC read register and it is performed at every field.
RUN-IN detection, start ｃｏｄｅ detection and sliced data can be read via IIC bus.
e) Macrovision detection
TC90101FG can detect a pseudo sync, AGC pulse and color stripe.
The result of Macrovision detection can be read via IIC bus.
ｆ） AGC function
TC90101FG has an AGC function for CVBS and Y signal (S-video).
The related write registers are as follows.
PAGCON (sub address 2B hex) : Setup for PEAK AGC function.
PKLIM (sub address 2B hex) : Setup for limit level for PEAK AGC function.
SAGCON (sub address 2B hex) : Setup for SYNC AGC function.
(Through mode : Both registers (PAGCON & SAGCON) must be set [0]. )
Feb./2005
12
TC90101FG
12. Insertion of IIC read data for output
TC90101FG has IIC read data insert mode for ITU-656 out put format.
It’s also available for ITU-601 mode. These functions are based on ARIB STD-B6.
Selection of the line for IIC read data insertion is set via register at sub address 25hex and 26hex .
①25H D7：Insertion ON / OFF control for Horisontal blanking periode.
②25H D6：Insertion ON / OFF control for Vertical blanking periode.
③25H D5：Selection of insertion for ITU-601 mode
④25H D4-D0：Line selection of insertion for Horizontal blanking periode.
⑤26H D7-D4：Line selection of insertion for Vertical blanking periode.
TC90101FG uses “the 2nd form of ARIB "
ADF ：Auxiliary signal flag word （Fixation） 3 word
DID ：For discernment （set by register）
SDID ：For discernment 2nd data（set by register）
DC ：Data count code（the numbers of UDW word）
UDW ：User data word （main data）
ADF
DID SDID DC
UDW
CS
CS ：Check sum (DID～UDW)
●ＡＤＦ
ADF uses fixed value.
1) at the 10bit mode
000h 3FFh 3FFh
2) at the 8 bit mode
00h
FFh
FFh
●ＤＩＤ
DID has 4bit control registers （26H：D3-D0）.
1) For 10bit mode.
D9(MSB)
D8
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0(LSB)
DID0
D[7:0]の偶数パリティビット
DID3
DID2
DID1
D8
2) For 8bit mode.
D7(MSB)
0
D6
D5
0
D4
0
D3
DID3
D2
DID2
D1
0
D0(LSB)
0 定
0
（Notice） DID[3:2]＝00 is not available when use 8bit mode.
●SDID
SDID has 4bit control registers （27H）.
1) For 10bit mode.
D9(MSB)
D8
D7
D6
SDID6
D5
SDID5
D4
SDID4
D3
SDID3
D2
SDID2
D1
SDID1
D0(LSB)
SDID0
SDID7
D[7:0]の偶数パリティビット
D8
2) For 8bit mode.
D7(MSB)
SDID7
D6
SDID6
D5
SDID5
D4
SDID4
D3
SDID3
D2
SDID2
D1
0
D0(LSB)
0
（Notice） DID[7:2]＝0000 00 is not available when use 8bit mode.
●ＤＣ
DC uses Fixed value.
1) For 10bit mode.
D9(MSB)
0
D8
1
D7
0
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0(LSB)
0
2) For 8bit mode.
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
0
1
0
0
1
0
0
0
Feb./2005
13
TC90101FG
●ＵＷＤ
＜I2C Read Bus → ６５６ insertion specification.＞
In case of 1byte Read register (RD[7:0]), it is superposed as below
・Read register 1 byte.
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
・６５６ insertion： 1st word.
D7
D6
D5
D4
D3
D2
D1
0
D0
0
D(-1)
D(-2)
0,0
0
1
RD7
RD6
RD5
RD4
(10bit mode)
・６５６ insertion： 2nd word
D7
0
D6
0
D5
D4
D3
D2
D1
D0
0
D(-1)
0,0
(10bit mode)
D(-2)
RD3
RD2
RD1
RD0
1
●ＣＳ
Check sum means total value of ＤＩＤ to ＵＷＤ as below.
１）10bit mode
It calculates total value of the 9bits low ranks of DID, SDID, DC and all of UDW.
MSB(D9) means D8 of calculated valu. (it ignores the over flow.)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Total value of the 9bits low ranks of DID, SDID, DC and all of UDW.
(it ignores the over flow.)
D8
２）８ｂｉｔ mode
It calculates total value of the 7bits low ranks of DID, SDID, DC and all of UDW.
MSB(D7) means D6 of calculated valu. (it ignores the over flow.)
D7
D6
D5
D4
D3
D2
D1
D0
Total value of the 9bits low ranks of DID, SDID, DC
and all of UDW.(it ignores the over flow.)
D6
Feb./2005
14
TC90101FG
4. IIC BUS
TC90101FG has two slave address (B2 hexand B0hex). A slave address is chosen by BUSSEL
Terminal which is pin 24. (BUSSEL=L：B0hex , BUSSEL=H：B2hex）。
R/
A6 A5 A4 A3 A2 A1 A0
W
1
0
1
1
0
0
X
X
・Data transmission format
S
Slave Address 0 A
Sub Address
8bit
A
Data
8bit
A P
7bit
S: Start condition
P: Stop condition
A: Acknowledgement
MSB
MSB
MSB
(1) Start condition, Stop condition
(2) Bit transmission
SDA
SDA
SCL
SCL
S
P
Start conditions
Stop conditions
SDA is not changed. SDA is changed.
(3) Acknowledgement
SDA from
Master
High impedance
High impedance
SCL from
Master
1
8
9
S
Start conditions
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these
componentsinanI2Csystem,providedthatthesystemconformstotheI2CStandardSpecificationasdefined
by Philips.
Feb./2005
15
TC90101FG
IIC BUS MAP
Sub
D7
D6
D5
D4
TVM2
D3
D2
D1
D0
INSEL
AUTODET
00H
TVM3
TVM1
TVM0
Input signal selection
00：CVBS
Color system detection mode
00：Manual （00h-D5･･D2 : Active）
01：EU mode
FSC selection
0：3.58MHz
1：4.43MHz
0000：NT358
FV selection
0：60Hz
PAL selection SECAM selection
0：Not PAL
1：PAL
0：Not SECAM
1：SECAM
01：Y/C（S-Video）
１：50Hz
10：YCbCr（D1or D2 Component）
11：CVBS+ＹCbCr(for SCART）
10：South America
0100：NT50
1000：NT443
1001：SEC60
1010：PAL60
1011：don't use
FORMATO
1100：don't use
1101：SECAM
1110：PAL
11：Full detection mode
0001：don't use 0101：don't use
0010：PAL-M 0110：PAL-N
INIT:03H
01H
0011：don't use 0111：don't use
SELCK
1111：don't use
OUTBITS
YCS Mode
HIZMODE
ADPWD
Frequency of CKOUT(pin48) selection
3LYCS selection
0：3line
Fixed to [0]
setting of output Stand by mode
10：54MHz
00：13.5MHz
01：27MHz
0：Rec601
1：Rec656
0：8bit
0：Normal
1：Open
0：ADC-OFF
1：Normal
INIT:33H
02H
1:BPF
11：13.5MHz
1：10bit
V ENH GAIN
V Enhance Gain
V ENH MAX POINT
V Enhance Non-linear
V ENH SLICE LEVEL
Ｖ Enhance Coring
FENH
PRENH
Sharpness fo
0：4.2MHz
1：3.3MHｚ
FBCLAMP
F/B CLAMP
0：Auto mode
1：Always ON
Pre Enhance
0:OFF
00：OFF
10：×1/4
11：×1/2
00： 6IRE
01： 9IRE
10：13IRE
11：16IRE
00：ＯＦＦ
01：0.8IRE
10：1.6IRE
11：2.3IRE
INIT:34H
03H
01：×1/8
1:ON
SHARPNESS GAIN
Sharpness Gain Adjustment
SHARPNESS SLICE LEVEL
Shrpness coring
FBCLMPEX
FB CLAMP mode
0: External
1: Internal
1000:(don't use)
1001:(don't use)
1010:(don't use)
1011:-4/16
1100:-3/16
1101:-2/16
1110:-1/16
1111:OFF
0000:1/16
0001:2/16
0010:3/16
0011:4/16
FLTI
0100:5/16
0101:6/16
0110:7/16
0111:8/16
FCTI
00：0.8IRE
01：1.6IRE
10：3.2IRE
11：6.4IRE
INIT:F0H
04H
NOISE CANCEL GAIN
Gain Adjustment
SET DELAY
Cb and Cr Delay Adjustment
0000：-296nsꢀ～ꢀ1000：Center ～ 1111：259ｎｓ（37ns unit）
LTI fo
CTI fo
00：OFF
01：×1/4
10：×1/2
11：×1
0：3.3MHz
1：2.2MHｚ
0：1.7MHz
1：3.4MHz
INIT:08H
05H
LTI GAIN
ＬＴＩ Gain Adjustment
LTI SLICE LEVEL
ＬＴＩ Coring
00：0.8IRE
01：1.6IRE
CTI GAIN
CＴＩ Gain
CTI SLICE LEVEL
CＴＩ Coring
00：OFF
01：×1/8
10：×1/4
11：×1/2
10：3.2IRE
11：6.4IRE
00：OFF
10：×1/2
11：×3/4
00：0.4IRE
01：0.8IRE
10：1.6IRE
11：3.2IRE
INIT:00H
06H
01：×1/4
CONTRAST
Contrast Adjustment
00h：ｘ１/2ꢀ～ꢀ40h：ｘ1 ～ FFh：ｘ2.4
BRIGHTNESS
INIT:40H
07H
Brightness Control
10000000：-128LSBꢀ～ꢀ 00000000：0LSBꢀ～ꢀ01111111：+128LSB（１０ｂｉｔ）
CR OUTPUT GAIN CB OUTPUT GAIN
INIT:00H
08H
Ｃｒ Gain Adjustment
1000：×1/2ꢀ～ꢀ0000：×１ꢀ～ꢀ0111：×1.4
CR OUTPUT OFFSET
Ｃｂ Gain Adjustment
1000：×1/2ꢀ～ꢀ0000：×１ꢀ～ꢀ0111：×1.4
CB OUTPUT OFFSET
INIT:00H
09H
Ｃｒ Output Offset Adjustment
Ｃｂ Output Offset Adjustment
1000：-8LSBꢀ～ꢀ0000：０ꢀ～ꢀ0111：+7LSB （１０ｂｉｔ）
HUE
1000：-8LSBꢀ～ꢀ0000：０ꢀ～ꢀ0111：+7LSB （１０ｂｉｔ）
FP_FIL
INIT:00H
0AH
filter for Feed
back
HUE adjustment ( for NTSC signal)
1000000：－４５°ꢀ～ꢀ0000000：０°ꢀ～ꢀ0111111：＋４３．６°
０：OFF
INIT:01H
0BH
１：ON
HUE BIAS
CLPFOF
DCLAMP_VMASK
HUE bias adjustment (Adjustment for the demodulation phase of R-Y ( NTSC only)
000000：０°ꢀ～ꢀ111111：＋４５°
C Trap (burst ) V mask of digital
clamp
(for degital clamp)
0：OFF
１：ON
ＴＯＦ
0：OFF
1：ON
INIT:03H
0CH
Y INPUT OFFSET
BUS_DCOMTRP2
DCOMB out
C Trap
Offset adjustment for clamp Y input
1000：-31mVꢀ～ꢀ0000：0mVꢀ～ꢀ0111：+27mV
Take off filter selection
000：OFF , 001：BPF,
0：OFF
010：MINꢀ～ꢀ111：MAX
INIT:00H
0DH
1：ON
INIT:00H
0EH
YꢀClampPulse_F
YꢀClampPulse_W
DIGITAL Y CLAMP
Time constant of Y digital clamp
Phase adjustment of digital clamp for Y
000：1.19μｓꢀ～ꢀ111：3.26μｓ
Adjustment of Clamp widthfor Y digital clamp
000：0.9μｓꢀ～ꢀ111：2.96μｓ
00：OFF
01：small
10：mediam
11：large
INIT:00H
0FH
CR INPUT OFFSET
CB INPUT OFFSET
Offset adjustment for Cb input
1000：-31mVꢀ～ꢀ0000：0mVꢀ～ꢀ0111：+27mV
Offset adjustment for Cr input
1000：-31mVꢀ～ꢀ0000：0mVꢀ～ꢀ0111：+27mV
INIT:00H
* : Every blank register must be set “0”.
Feb./2005
16
TC90101FG
Sub
10H
D7
D6
D5
D4
D3
D2
D1
D0
CICLMPP_S
CICLMPP_W
Adjustment of input clamp phase for analog Cb/Cr
1000：-1.185μｓꢀ～ꢀ0000：±０ꢀ～ꢀ0111：+1.04μｓ
CꢀClampPulse_F
Adjustment of input clamp width for analog Cb/Cr
1000：-1.185μｓꢀ～ꢀ0000：±０ꢀ～ꢀ0111：+1.04μｓ
INIT:00H
11H
CꢀClampPulse_W
DIGITAL C CLAMP
Adjustment of digital clamp phase for Cb/Cr
000：1.19μｓꢀ～ꢀ111：3.26μｓ
Adjustment of digital clamp width for Cb/Cr
000：0.9μｓꢀ～ꢀ111：2.96μｓ
Time constant of Cb/Cr digital clamp
00：OFF
01：small
10：mediam
11：large
INIT:00H
12H
COLOR KILLER LEVEL
ACC LEVEL
CONFIX
Killer function
0：normal
Adjustment the sensitivity of the killer detection
000：Maxꢀ～ꢀ111：Ｍｉｎ
Adjustment ＡＣＣꢀreference level
0000：Ｍｉｎꢀ～ꢀ1111：Ｍａｘꢀ〔Initial：1000〕
INIT:08H
13H
1：killer off
DOT DIST
Reduse dot ( Horizontal)
CGAIN
COMB+
1LINE DOT
COM443N
Comb selection
for 443NTSC
ＳＥＣＡＭ用ꢀＹ trap performance
000：ＯＦＦꢀ～ꢀ１１１：×0.875（Intial：011）
00：OFF
10：ｘ0.17
11：ｘ0.18
0：OFF
1：ON
0：OFF
1：ON
01：ｘ0.16
0:1H Comb
1:2H Comb
INIT:5BH
14H
EXTERNAL SYNC
Mode selection for external sync
SYNC TIP CLAMP１
Sync tip clamp mode for CVBS
SEPA LVL
Sync sepa. Level
0:30%
VSEPLVL
VLMT
V sepa limit
0： 1/8
HHKIL
V sepa mode
AFC V mask
0：OFF
00：OFF(internal)
01：CsyncH
10：CsyncL
11：VsyncH
00：ON
10：AUTO１
11：AUTO２
1:40%
01：OFF
0：5/16
1：1/2
1： 1/16
1：ON
INIT:1CH
15H
SHCTRL
Adjustment Horizontal phase reference
MUTE
picture mute
0：OFF
C MUTE
Cb/Cr out mute
0：OFF
100000：-4.74μｓꢀ～ꢀ000000：±０μｓꢀ～ꢀ011111：+4.46μｓ（1/6.75MHzｽﾃｯﾌﾟ）
INIT:00H
16H
1：ON
1：ON
HDAMP1
HD GAIN1
Time constant 1 fpr H PLL(Phase difference: big)
000：largeꢀ～ꢀ111：small
Loop gain 1 for H PLL(Phase difference: big)
00000：smallꢀ～ꢀ11111：large
HDGAIN2
INIT:4EH
17H
HDAMP2
Time constant 2 fpr H PLL(Phase difference: middle)
000：largeꢀ～ꢀ111：small
Loop gain 1 for H PLL(Phase difference: middle)
00000：smallꢀ～ꢀ11111：large
HDGAIN3
INIT:85H
18H
HDAMP3
Time constant 3 fpr H PLL(Phase difference: small)
000：largeꢀ～ꢀ111：small
Loop gain 1 for H PLL(Phase difference: small)
00000：smallꢀ～ꢀ11111：large
HGCON21
INIT:A6H
19H
HGCON12
Threshold level at the phase diffrence large to middle
0000:OFF ～ 1111:High
Threshold level at the phase diffrence middle to big
0000:OFF ～ 1111:High
INIT:48H
1AH
EN_NOISEH_S
EN_NOISEH_W
EN_NOISEV_W
Adjustment start phase for noise detection
000：32.2uSꢀ～ꢀ100：36.9uSꢀ～ꢀ111：40.5uS
Adjustment the width for noise detection
Noise detection line numbers
000：9.4uSꢀ～ꢀ100：14.1uSꢀ～ꢀ111：17.7uS
00：1H
01：2H
10：3H
11：4H
INIT:90H
1BH
EN_NOISEV_S
Adjustment start line for noise detection
000：0Hꢀ～ꢀ１11：+15H
VSRACH
fsc lock period
FLOCK
HPLL Gain at lock
0：1/2
00：3V
10：5V
01：4V
11：6V
60Hz：line ７ is as 0H
1：no change
50Hz：line ４ is as ０Ｈ
INIT:00H
1CH
HDPH
VDPH
Adjustment horizontal phase for digital output
1000：-1.185uSꢀ～ꢀ0000：0uSꢀ～ꢀ1111：+1.04uS
EN_PIXH_S
Adjustment Vertical phase for digital output
0000：0Hꢀ～ꢀ1111：+15H
INIT:00H
1DH
EN_PIXH_W
Adjustment start phase of horizontal signal processing
1000：-1.185μｓꢀ～ꢀ0000：cemterꢀ～ꢀ0111：+1.04μｓ
EN_PIXV_S
Adjustment width of horizontal signal processing
1000：-1.185μｓꢀ～ꢀ0000：center～ꢀ0111：+1.04μｓ
INIT:00H
1EH
COMB KILL
011：1～23H
100：1～24H
101：1～25H
EN_PIXV_A
Adjustment start phase of vertical signal processing
0000：line 10ꢀ～ꢀ1111： line 25
000：OFF
001：１～21H
010：1～22H
110：1～26H
111：Auto
0：Manual
1：Auto
INIT:07H
1FH
(60:22H,50:23H)
HBLK_S
HBLK_W
Adjustment width of horizontal BLK
1000：-2.37μｓꢀ～ꢀ0000：±０ꢀ～ꢀ0111：+2.27μｓ
Adjustment start phase of horizontal BLK
1000：-2.37μｓꢀ～ꢀ0000：±０ꢀ～ꢀ0111：+2.27μｓ
INIT:00H
* : Every blank register must be set “0”.
Feb./2005
17
TC90101FG
Sub
20H
D7
D6
D5
D4
D3
D2
D1
D0
BFP_S
VBIVAD[2:0]
CLP
Adjustment start phase of burst gate
0000：centerꢀ～ꢀ1111：+4.44μs
（0.296μs step）
Adjustment the pase of VBI data slice
100:-4H～000:center ～111:3H
16LSB limit
0：OFF
1：ON
INIT:00H
21H
VPHS
HDST
Delay adjustment of HDOUT
BYFOFF
BSRY filter
BCFOFF
BSRC filter
Adjustment start phase of V at THRHV=1
110：384W
011：192W
100：256W
101：320W
000：0W
10：40w
11：44w
00：32w
01：36w
(1W:27MHz)
INVCK
111：don't use
(1W:27MHz)
PHPOLE
001：64W
010：128W
PFPOLE
0：ON
1：OFF
0：ON
1：OFF
INIT:03H
22H
PVPOLE
THRHV
SEL_BLK
YOLEVEL
1/1.71875
Y output amplitude
0：1.71875
1：1.0
HDOUT polarity
VDOUT polarity
Field polarity
H,V-OUT through CKOUT polarity V.BLK processing
0：active
1：negative
0：active
1：negative
RBCHG
0：active
1：negative
0: 656
1： through
0：active
1：negative
FIELD_DET
0：normal
1：through
INIT:18H
23H
VD_DET
Control VDOUT
00：Free run
01:Fixed mode 50/60 （ on TVM2）
10：Fixed mode at MANUAL mode
11：Fixed mode for MANUAL mode &
no sig at AUTO mode
EXVDF
Adjustment Ext VD phase
011：+5.96us
Cb/Cr phase
0：normal
1：change
Field Det.
at no -sig.
0：AUTO
000：center
001：+1.99us
010：+3.97us
110：-3.97us
111：-1.99us
100：-7.94us
101：-5.96us
1：Fixed Low
INIT:00H
24H
FLDTMSEL
SEL_RDATA
VCTOLE
VCRESET
AFC_Cont
Adjustment horizontal phase for field detection
Start phase of IIC read registers
V count
V count reset
AFC control
000：-5.7μｓ
001：-8.2μｓ
011：-13.2μｓ
100：-15.7μｓ
101：-18.4μｓ
AXD_VON
110：-20.9μｓ
111：-23.2μｓ
0:-H/8 ～ +H/4
1:±H/8
0：OFF
1：ON
0：OFF
1：ON
AXD_HSEL[4:0]
00：CDEC
10：ID1
01：CCD
11：WSS
INIT:80H 010：-10.7μｓ
25H
AXD_HON
data insert of H data insert of V
AXD_SSEL
data incert
for 601 format
0：incert to CbCr
1：incert to Ｙ
Line number for incert data
NTSC :ꢀ21/284 line + AXD_HSEL
PAL時 :ꢀ24/337 line + AXD_HSEL
0：OFF
1：ON
0：OFF
1：ON
INIT:00H
26H
AXD_VSEL[3:0]
DID[3:0]
For DID code
Line number for incert data to field BLK
NTSC : ꢀ1line+AXD_VSEL
PAL :ꢀ1line+AXD_VSEL
INIT:00H
27H
SDID[7:0]
For DID code
INIT:00H
28H
CSONTIM
Ａｄｊｕｓｔｍｅｎｔ histerisis for
Color stripe detect ON
CSOFTIM
Ａｄｊｕｓｔｍｅｎｔ histerisis for
Color stripe detect ON
strp_idg_wd[1]
Adjustment mask periode
for color stripe detection
strp_idg_wd[0]
strp_idg_lv[1]
strp_idg_lv[0]
Sensitivity of
color stripe detection
00: Lowꢀ～ꢀ11: High
00:OFF
01:1.0s
CPSON
10:2.0s
11:3.0s
00:OFF
01:0.5s
AGCWID
10:1.0s
11:1.4s
PSEWID
00:10clk
01:15clk
10:20clk
11:30clk
PSEMOD
INIT:00H
29H
PSLICEL
Slice level for pseudo H sync
Color syripe
detection
0:OFF
Adjustment AGC Adjustment Pseudo
detection periode periodeof H detect
0:2.3～3.2μS(D1) 0:1.3～2.7μS(D1)
1: 2.0～3.5μS(D1) 1: 1.0～3.0μS(D1)
0:1.1～1.7μS(D2) 0:0.9～1.3μS(D2)
1: 1.0～1.8μS(D2) 1: 0.8～1.4μS(D2)
AGCMOD
Pseudo H sync
detection
00:20%
10:40%
01:25%
11:60%
1:ON
0:OFF
1:ON
INIT:3AH
2AH
ASLICEL
Adjustment of slice level for AGC pulse
AGCHYS
Adjustment of histerisis time
for AGC pulse detection
PALPFON
LPF for AGC
pulse & pseudo
H sync detection
0:OFF
PASEL
AGC
Hsync detection
AGC pulse
detection
0: after AGC
1:befor AGC
0:OFF
1:ON
00:60%
10:80%
01:70%
11:90%
00:OFF
10:0.7s
01:0.4s
11:1.0s
INIT:DAH
2BH
1:ON
PKLIM
Peak AGC limit level
PATTK
Adjustment Peak AGC Atack time
00: fast～11：slow
PSLP
Sesitivity for Peak detection
00：big～11: small
PAGCON
Peak AGC
0：OFF
AGCLPFON
fsc Trap Filter
0：OFF
00：105%
01：110%
10：115%
11：120%
INIT:1AH
2CH
1：ON
1：ON
01：1/4
11：1/8
SATTK
SSLP
SAGCON
Sync AGC
0：OFF
Adjustment Sync AGC Atack time Adjustment Sync AGC recovery time
00: fast～11：slow
00: fast～11：slow
INIT:0FH
２DH
1：ON
CLPFON
LPF for CCD
CSLICEL
Adjustment fixed slice level
CCDMOD
CSLICES
CCD slice
function mode
0：Auto slice
1：fixed slice level
ISLICES
ID1data slice
function mode
0：Auto slice
1：fixed slice level
WSLICES
IRTIMS
Phase for ID1
detection
0:±0.6μs
1:±1.2μｓ
IRWIDON
CSTMOD
sensitivity of CCD Field selection for CCD data slice
start bit
0：OFF
1：ON
ILPFON
LPF for ID1
data slice
0：OFF
00：416LSB
10：296LSB
01：496LSB
11：336LSB
0：big
1：small
IEDGES
00：ODD
10：Both Field
01：EVEN
11：Both Field
INIT:80H
2EH
ISLICEL
IPHASES
Adjustment the sampling pase
for ID1
Adjustment fixed slice level for ID1 Det. for amplitude Phase adjustment
of ID1signal
0:80LSB
1:OFF
forID1det.
0：Adaptive mode
1：Fixed mode
WSTMOD
00：480LSB
10：312LSB
01：592LSB
11：368LSB
0：0
2：+2
1：-1
3：+1
INIT:80H
2FH
1：ON
WSLICEL
Adjustment of the slice level
for WSSdata
WSSMOD
Field selection for
WSS data slice
WLPFON
LPF for WSS1
data slice
0：OFF
WSS data
slice mode
0：Adaptive
1：Fixed mode
WSS SC
det. Mode
0：sensive
1：Slow
00：512LSB
10：320LSB
01：640LSB
11：384LSB
00：ODD
10：Both Field
01：EVEN
11：Both Field
INIT:88H
1：ON
* : Every blank register must be set “0”.
Feb./2005
18
TC90101FG
D7
D6
D5
D4
D3
D2
D1
D0
CCDDLY
ID1DLY
30H
Phase adjustment for CCD data slice
0000:min ～ 1000:center ～ 1111:max
1STEP = 128fh
Phase adjustment for ID1 data slice
0000:min ～ 1000:center ～ 1111:max
1STEP = 128fh
INIT:88H
31H
WSSDLY
CDECEV1[4]
fsc pull in
performance
YADFILON
13.5M trap
for ADC
FILON１
IIR FILTER
selection
FILON0
IIR FILTER
ON/OFF
Phase adjustment for WSS data slice
0000:min ～ 1000:center ～ 1111:max
1STEP = 128fh
0:Nornal
1:Wide
0：OFF
1：ON
0:FIL1
1:FIL2
0:OFF
1:ON
INIT:84H
32H
PROG
BUS_FBCLMOD
Time constant of theInternal
feed back clamping
D1/D2
detection
Manual set
0：Manual
1：Auto det.
MGAINSL
0：D1
1：D2
00：Reference
10：Small
01：Large
11：Mid
INIT:80H
33H
MGAIN
Manual Gain
set for GCA
Adjustment for GCA Gain
0：OFF
1：ON
INIT:00H
34H
CGP_S
CGP_W
Adjustment pulse width of CGP
Adjustment start phase of output pulse of CGP
1000：-1.185μｓꢀ～ꢀ0000：±０ꢀ～ꢀ0111：+1.04μｓ
0000：Sync center + 3.7μs
1000：-1.185μｓꢀ～ꢀ0000：±０ꢀ～ꢀ0111：+1.04μｓ
0000：center ( 2μs)
INIT:00H
35H
DET4VAL
SYNC TIP CLAMP２
Clamp control
00：ON
10：AUTO１
11：AUTO２
Threshold level for DET. 443
［1000:MIN 0000:CEN 0111:MAX]
0
1
01：OFF
INIT:07H
36H
CGPOUTM
BUS_DCOMTRP1
BUS_ENPIXOFF
Mute
CGP OUT
control
DCOMB OUT
C Trap
0:auto
0：OFF
1：ON
0：ON
1：OFF
INIT:00H
37H
1:forced ON
BUS_YNCCK
Y NOISE
BUS_YNCLV
Y NOISE LIM
0:4LSB
BUS_YNCGA
BUS_YNCON
Y NOISE
0:OFF
BUS_CKILLLV
CKILL Gain
0:Center
BUS_CNCLV
C NOISE LIM
0:4LSB
BUS_CNCGA
C NOISE GAIN
0:×1/2
BUS_CNCON
C NOISE
0:OFF
Y NOISE GAIN
0:×1/2
INIT:00H
1:8LSB
1:×1
1:ON
1:+3dB
1:8LSB
1:×1
1:ON
* : Every blank register must be set “0”.
Feb./2005
19
TC90101FG
IIC BUS Read Data
D7
Sub
D6
D5
D4
D3
D2
D1
0
D0
DET50
NOSIG
NOVP
FIELD
UNLOCK
H/VSTD
progressive
D1/D2 det.
0:D1
Field Frequency
0:60Hz
Signal det.
0:Signal det.
1:no signal
PALDET
PAL det.
0:non
V-Sync Sep
0:V sig det
1:no V sig
SECAMDET
SECAM det.
0:non
Field indication HPLL for inpit sig
H-V std. det.
0:std.
A-1
0:ODD
0:LOCK
1:50Hz
1:EVEN
1:UNLOCK
1:non-std.
CKILL
1:D2
FSC_SEL
DET443
FSCLOCK
fsc lock det.
0:unlock
1:lock
fsc detection
4.43MHz det.
0:non
Killer det.
0:Color
A-2
A-3
A-4
A-5
B-1
B-2
B-3
B-4
C-1
C-2
C-3
C-4
D-1
D-2
D-3
00:3.579545MHz 01:3.575611MHz
0
1:Det.
1:Det.
1:Det.
10:3.582056MHz
NOISE_OUT4
11:4.433MHz
NOISE_OUT3
1:White&black
NOISE_OUT2
NOISE_OUT7
NOISE_OUT6
NOISE_OUT5
NOISE_OUT1
NOISE_OUT0
S/N detection
0000_0000:Strong signal → 1111_1111:Weak signal
(MSB)
(LSB)
H_Cont［7］
H_Cont［6］
H_Cont［5］
H_Cont［4］
H_Cont［3］
H_Cont［2］
H_Cont［1］
H_Cont［0］
information of H counter numbers for 1V periode
10000000：Min
00000000：Typ
01111111：Max
COLSTYPE
Color stripe
0：TYPE2
1:TYPE3
COLSDET
Color_ S_DET
AGC DET
Color stripe det. Psuedo Sync det. AGC Pulse det.
0固定
0:non
1:det.
0:non
1:det.
0:non
1:det.
0
0
0
IIR CCD[7]
CCD CRI det.
０：under 3ck
IIR CCD[6]
Start bit det.
0：NG
IIR CCD[5]
IIR CCD[4]
IIR CCD[3]
IIR CCD[2]
IIR CCD[1]
IIR CCD[0]
CCD sliced data
１：upper then 3ck
IIR CCD[15]
1：OK
(LSB)
IIR CCD[14]
IIR CCD[13]
IIR CCD[12]
IIR CCD[11]
IIR CCD[10]
IIR CCD[18]
IIR CCD[26]
IIR ID1[2]
IIR CCD[9]
IIR CCD[8]
CCD sliced data
IIR CCD[23]
IIR CCD[31]
IIR CCD[22]
IIR CCD[21]
Field information
０：ODD
IIR CCD[20]
IIR CCD[19]
IIR CCD[17]
IIR CCD[16]
0
CCD sliced data
Numbers of CRI
(MSB)
１：EVEN
(MSB)
(LSB)
IIR CCD[30]
IIR CCD[29]
IIR CCD[28]
information of CCD slice level
IIR CCD[27]
IIR CCD[25]
IIR CCD[24]
(MSB)
(LSB)
IIR ID1[7]
IIR ID1[6]
IIR ID1[5]
IIR ID1[4]
IIR ID1[3]
IIR ID1[11]
IIR ID1[19]
IIR ID1[27]
IIR ID1[1]
WORD１(sliced data)
IIR ID1[0]
WORD０(sliced data)
Reference sig. det. CRC code det.
0:NG
1:OK
0:NG
1:OK
(LSB)
IIR ID1[15]
IIR ID1[14]
IIR ID1[13]
IIR ID1[12]
IIR ID1[10]
IIR ID1[18]
IIR ID1[26]
IIR_WSS[2]
IIR ID1[9]
IIR ID1[8]
WORD2(sliced data)
IIR ID1[23]
IIR ID1[31]
IIR ID1[22]
IIR ID1[30]
IIR ID1[21]
IIR ID1[20]
IIR ID1[17]
0
IIR ID1[16]
Field information
0:ODD
ＣＲＣＣ(sliced data)
1:EVEN
IIR ID1[29]
IIR_WSS[5]
IIR ID1[28]
information of ID1 slice level
IIR ID1[25]
IIR ID1[24]
(MSB)
IIR_WSS[7]
RUN-IN det.
0:NG
(LSB)
IIR_WSS[6]
START CODE det.
0:NG
IIR_WSS[4]
IIR_WSS[3]
IIR_WSS[11]
IIR_WSS[19]
IIR_WSS[1]
IIR_WSS[9]
IIR_WSS[17]
IIR WSS[0]
WSS(sliced data)
1:OK
1:OK
(LSB)
IIR WSS[15]
IIR_WSS[14]
IIR_WSS[13]
IIR_WSS[12]
IIR_WSS[10]
IIR_WSS[8]
WSS(sliced data)
(MSB)
IIR_WSS[23]
Bi phase det.
0:NG
IIR_WSS[22]
Field information
0:ODD
IIR_WSS[21]
(MSB)
IIR_WSS[20]
IIR_WSS[18]
IIR WSS[16]
information of WSS slice level
1:OK
1:EVEN
(LSB)
IIC read data sequence
ＡＢＣＤ
SEL_RDATA
00h
ＢＣＡＤ
01h
ＣＡＢＤ
10h
ＤＡＢＣ
11h
Feb./2005
20
TC90101FG
●Additional information about IIC registers.
Function
BUS address
00H：D7-D6
Contents
Inputsignalselection.
An input signal is chosen.
00H：D5-D2 Select TVM.
The TV-system is fixed forcibly.
It uses when it is worked in the manual.
00H：D1-D0 Colorsystemdetection Setup Color system detection mode.
mode.
Manual / Europeian / South American / Full auto detection.
3-lineComb or BPF is chosen.
0: 3-line-Comb 1: B.P.F
01H：D7
Setup for YCS.
01H：D5-D4 Select clock
Setup for an output clock frequency.
Select “601：13.5MHz” or “656：27MHz”.
Select OUTPUT FORMAT Setup for an output format (601or656).
01H：D3
01H：D2
01H：D1
Select OUTBITS
Setup for an output bits range (8bit or 10bit).
Each digital output terminals are controlled.
0：Active 1：OPEN (Because it becomes Hi Impedance,
coexistence with other IC's is possible.）
The control of the power supply for ADC.
Digital-Output Control
01H：D0
ADC-Power Control
0：The power supply of ADC is turned off.
1：Normal (It usually uses by this setup.)
Gain (off, 1/8, 1/4 and 1/2) is set up.
02H：D7-D6 Set V Enhance Gain
02H：D5-D4 Set V Enhance non-
liner point.
Setup the characteristic of V-enhance gain for non- correlation
Component. Choose it from 4 point
02H：D3-D2 Set V Enhance coring Choose Coring(No response level).
02H：D1
Set “f0” of sharpness Set f0 of Sharpness.
It works with f0 of Noise-canceler as well together.
Pre-Enhance makes it control the part Edgy of Sharpness.
02H：D0
Select Pre-Enhance
03H：D7-D4 Adjustment Sharpness Control the Gain of Sharpness.
Gain. 1011：-1/4 ～ 1111：OFF ～ 0111：8/16
1000, 1001 and 1010 can't be used.
03H：D3-D2 Set Sharpness-coring Choose Coring(No response level).
-Level.
Set the Feed-Back CLAMP.
03H：D1
Set the Feed-Back
CLAMP
0: Auto. It becomes a diode clamp when TC90101FG detects a
non-signal. 1：Feed-Back Clamp is active.
Select Internal-Feed-Back or External-Feed-Back.
0: External mode (Pin74, 75 outputs clamp signal).
1: Internal mode (Pin74, 75 : Open). The time-constant for
internalfeedbackclampissetviaBUS_FBCLMODatsubaddress32hex.
Set the Gain of NOISE-CANCEL.
03H：D0
Change the Feed-Back
CLAMP
04H：D7-D6 Set Noise canceler
Gain
04H：D5
04H：D4
Set LTI f0
Set CTI f0
Set the f0 of LTI.
Set the f0 of CTI.
04H：D3-D0 Cb & Cr delay adjust. Fine tune for delay of Cb & Cr.
Step is 37[ns] between -296ns～259ns.
But step is 74[ns] at YCbCr input mode.
05H：D7-D6 LTI Gain adjustment
05H：D5-D4 LTI coring Level
It set the Gain of LTI.
It set the Coring(No response level) of LTI.
Use after you confirm a picture.
It set the Gain of CTI.
05H：D3-D2 CTI Gain adjustment
05H：D1-D0 CTI coring Level
It set the Coring(No response level) of CTI.
Feb./2005
21
TC90101FG
BUS address
Function
Contents
06H：D7-D0 Contrast Adjustment
It set the Contrast. (Reference value: [01000000])
Variability is ×0.5～×2.4.
（When use big value and inputs big amplitude signal,
It takes place over range of internal circuit.)
It set the Brightness.
07H：D7-D0 Brightness Adjustment
08H：D7-D4 Cr Gain Adjustment
Variability is -128LSB ～ +128LSB.
It set Gain of Cr. (Refrence value:[0000])
Variability is ×0.5～×1.4.
（When use big value and inputs big amplitude signal,
It takes place over range of internal circuit.)
It set Gain of Cb. (Refrence value:[0000])
Variability is ×0.5～×1.4.
08H：D3-D0 Cb Gain Adjustment
（When use big value and inputs big amplitude signal,
It takes place over range of internal circuit.)
09H：D7-D4 Cr Output OFFSET adjust. Fine tune for offset of the Cr at output stage.
09H：D3-D0 Cb Output OFFSET adjust. Fine tune for offset of the Cr at output stage.
0AH：D7-D1 HUE adjustment
HUE adjustment at the NTSC input mode.
Variable is -45°-+43.6 °.
Setup BPF for feed-back-clamp. [1]:ON [0]:OFF
0AH：D0
Filter for feed-back
Normaly It must be set [1].
0BH：D7-D2 HUE Bias adjustment
Fine tune HUE-Bias at the NTSC input mode.
Variable is 0°～+45°.
CTrapfordiritalclamp. It is C-Trap for Digital-clamp of Y. [1]:ON [0]:OFF
0BH：D1
0BH：D0
Use [1] at the digital-clamp-mode.
V-mask of digital clamp Setup of the digital clamping at V-Blk period.
[1]: Clamp OFF [0]: Clamp ON. It usually uses on [1].
0CH：D7-D4 Offset adjustment for
clamp Y-input
Offset adjustment for Y signal at Analog-input.
Use with 0[mV] when you use with digita-clamp.
Setup C-trap for Y at Digital-COMB-block.
0CH：D3
C-trap of D-COMB
[1]: ON [0]: OFF. This setup can reduce Cross-color and beat.
0CH：D2-D0 Take off Filter select Setup Take-off-Filter.
Take-off-Filter is put in front of Decoder. 000：OFF、001：
BPF、010～111：TOF（TOF1～TOF6）
When BPF is set up, it can't get the effect of TOF.
Digital-clamp is put by input-Y-signal
0EH：D7-D5 Phase adjustment of
Digital-clamp for Y.
Adjustment of the phase of Digital-clamp-pulse for Y.
Reference value:[011].The variable is about 0.3[μs] step.
Adjustment of the width of Digital-clamp-pulse for Y.
Reference value: [011].Variable is about 0.3[μs] step.
OEH：D4-D2 Adjustment of clamp-
width for Y-digital
-clamp
0EH：D1-D0 Time constant of Y-
Digital-clamp
It can select ON/OFF of Digital-clamp-Y. And adjustment of
time constant of Digital-clamp-Y.
0FH：D7-D4 Offset adjustment for
Cr-Input
Adjust the offset of the Cr at input by YCbCr signal.
Use with 0[mv] at the time of Digital-clamp.
Variable is -31[mV] ～ +27[mV].
OFH：D3-D0 Offset adjustment for
Cb-Input
Adjust the offset of the Cb at input by YCbCr signal.
Use [0000] at the Digital-clamp mode.
Variable is -31[mV] ～ +27[mV].
10H：D7-D4 Adjustment of input
clamp phase for Cb/Cr
Adjust the clamp-phase of Cb/Cr at YCbCr signals.
It usually uses on BUS:[0000].
Feb./2005
22
TC90101FG
BUS address
Function
Contents
10H：D3-D0 Adjustment of input
clamp width for Cb/Cr
Adjust the clamp pulse width of Cb/Cr at YCbCr signals.
It usually uses on BUS:[0000].
11H：D7-D5 Adjustment of digital
Adjust the digital-clamp-phase for C/Cb/Cr.
-clamp-Pulse-phase for (S-Video/YCbCr inputs.)
C/Cb/Cr
11H：D4-D2 Adjustment of digital
Clamp-pulse-width for
C/Cb/Cr
It usually uses on BUS:[011].
Fine tune the digital-clamp-pulse-width for C/Cb/Cr.
(S-Video/YCbCr inputs.)
It usually uses on BUS:[011].
11H：D1-D0 Time constant of C-
Digital-clamp
This is adjustment of time constant of Digital-clamp-C.
It can set ON/OFF and three-kinds.
12H：D7
Setup killer function
Setup color killer function.
[0]: Active (normal) [1]: Killer become OFF always.
Level of color-killer-ON is set up. [000]:killer sensitivity is
max.[111]: killer sensitivity is minimum.
12H：D6-D4 Level of color-killer
12H：D3-D0 ACC reference Level
13H：D7-D6 Reduce H-dot
Reference-level of ACC(auto color control) is set up.
Level by ACC becomes smallest when it is set up in 000.
Setup of dot-reducer at the horizontal edge.
When it is turned on, dot of the part of H is reduced.
It has an effect as below for PAL system.
13H：D5
Setup Comb+
When the horizontal lines of the front and the rear have color
andedgeelement,andthehorizontallineofcenterhasnocolor,
it drops Y signal level for calculated result. Therefore it
occurs dots of black in spite of white and gray picture.When
COMB+ is on, it can decrease this noise.
It usually uses ON, when PAL signal.
13H：D4
13H：D3
1 LINE DOT
Setup of 1LINE-DOT-improver in the YCS block. [1]:ON [0]:OFF
It can reduce the dot,when only 1-line has a color signal.
Comb control in 443NTSC is changed. [1]:2H comb [0]:1H comb
Cross-color will reduce when 2H-Comb is selected.
Setup Y-trap performance for SECAM.
443NTSC Comb control
13H：D2-D0 SECAM Y trap setup
TC90101FGSECAMTrap FrequencyResponse
1 0
0
- 1 0
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
B U S
B U S
B U S
B U S
B U S
B U S
B U S
B U S
=
=
=
=
=
=
=
=
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
1 0
F re q u e n c y
[ M H z ]
Feb./2005
23
TC90101FG
BUS address
Function
Contents
14H：D7-D6 Selection for
external-sync
It select the input signal of Composite-SYNC-in of Pin-33.
[00]: OFF(Internal) Pin33 must be connect to GND.
[01]: External composite Sync mode (polarity: High)
[10]: External composite Sync mode (polarity: Low)
[11]: External V-Sync mode (polarity: High)
Level of Sync-sepa is set up.
14H：D5
Sync Separation level
Initial value is [0]:30%.
14H：D4-D3 Sync-tip-clamp-mode for It set the control of clamp.
CVBS
[00]: Sync tip clamp ON [01]: Sync tip clamp OFF
[10]: AUTO1(Sync-tip-clamping becomes activity, When it
detect non-signal or pedestal has a big difference.
[11]: AUTO2 (Sync-tip-clamping becomes activity, When it
detect non-signal.
14H：D2
14H：D1
14H：D0
Setup for V-sepa
V-sepa limit
Setup for V-sepa
0: Type 1
1: Type 2 (Type 2 is more effective than Type1.)
Limit of V-sepa is set up.
V-sepa becomes easy, when it is set up in 1/16.
But,Usually use with 0(1/8）.
Setup of Half-H-killer It count Half-H at the V period.
[0]: OFF (Initial value)
[1]: ON (It is effective for top-curl problem of non-standard
signal.(VCR trick mode etc･･)
Reference-Horizontal-counter of internal is set up.
This register is reference timing for all of internal
function. Usually, it uses with 0[µs].
[0]: Normal [1]: Picture Mute ON
15H：D7-D2 Horizontal phase
reference
15H：D1
15H：D0
Picture MUTE
Cb and Cr MUTE
[0]: Normal [1]: Color signal Mute ON
16H：D7-D5 Time constant 1 for HPLL It is time-constant of PLL.
(Phase difference:big) It becomes active when the phase difference has big value.
Reference value: [010]
16H：D4-D0 Loop Gain 1 for HPLL
It is Loop-Gain of PLL.
(Phase difference:big) It becomes active when the phase difference has big value.
Reference value: [01110]
17H：D7-D5 Time constant 2 for HPLL It is time-constant of PLL.
(Phase difference:middle)
It becomes active when the phase difference has middle value.
Reference value: [100]
17H：D4-D0 Loop Gain 2 for HPLL
(Phase difference:middle)
It is Loop-Gain of PLL.
It becomes active when the phase difference has middle value.
Reference value: [01101]
18H：D7-D5 Time constant 3 for HPLL It is time-constant of PLL.
(Phase difference:small)
It becomes active when the phase difference has small value.
(it means under stable.)
Reference value: [101]
18H：D4-D0 Loop Gain 3 for HPLL
(Phase difference:small)
It is Loop-Gain of PLL.
It becomes active when the phase difference has small value.
Reference value: [00110]
Feb./2005
24
TC90101FG
BUS address
Function
Contents
19H：D7-D4 Threshold level at the Threshold level that Phase-diffrent changes from Big to middle
phase difference big
to middle
is set up.
Recommendation value: [0100]
19H：D3-D0 Threshold level at the Threshold level that Phase-diffrent changes from middle to
phase difference middle Big is set up.
to big
1AH：D7-D5 Start phase for noise
detection
Recommendation value: [01000]
Thehorizontal-start-phaseofthedetectionofNoiseissetup.
“Point of 5.3µs from sync” is center.
1AH：D4-D2 Width for noise
detection
The horizontal-width of the detection of Noise is set up.
The amount of noise-detection changes by Width.
When width is widened, detection sensitivity rises.
1AH：D1-D0 The number of horizontal It is the numbers of lines which Noise is detected in.
lines which Noise is
detected in
The number of line's can be set up from 1H to 4H.
1BH：D7-D4 Start line for Noise
detection
The vertical start line of the Noise detection is set up.
60Hz：7-lines as 0H.It is set up in 1 line unit.
50Hz：4-lines as 0H.It is set up in 1 line unit.
The fsc Lock-Gain is set up.
1BH：D2
HPLL-Lock-Gain
Usually used with 1/2.
1BH：D1-D0 fsc lock period
Lock-period of fsc is set up.
Search-time becomes long, when it is set up ～6V.
But, it is easy to pull in.
1CH：D7-D4 Horizontal phase for
digital format
The position of EAV&SAV is set up.
Usually, it uses with initial-value:0[us].
V-phase of VD is set up when "H/V OUT through".
Variability of V-phase is the 1H unit.
Thehorizontalstartphaseofthepicture-processing-periodis
set up. The picture-processing is set up with COMBKILL
(1EH D2～D0).
1CH：D3-D0 Vertical phase for
digital format
1DH：D7-D4 Start phase of
Horizontal signal
processing
1DH：D3-D0 Width of Horizontal
signal processing
The horizontal width of the picture-processing-period is
set up. The start reference is a horizontal start phase.
Make adjustment after start-setup.
1EH：D7-D4 Start phase of vertical Theverticalstartlineofthepicture-processing-periodisset
signal processing up.It becomes MUTE to the setup from the vertical start line.
Thesetupofthevertical AUTO or MANUAL is selected.
picture processing MANUAL: Itbecomes thevalue that it is setupwith 1EH(D7-D4).
1EH：D3
AUTO: 60Hz= from 10th line / 50Hz= from 23th line
Picture-processing is started from each line.
1EH：D2-D0 Setup of COMBKILL period The period of COMBKILL is set up.
This period doesn't do picture processing.
AUTO:60Hz=1～22H、50Hz=1～23H
But, it is a mask period to 21H by the Y/C input of 60Hz and
the YCbCr input of 60Hz.
1FH：D7-D4 Start phase of
Horizontal BLK
The start phase of H-BLANK-PULSE is set up.
Usually, it uses with initial-value:0[us].
1FH：D3-D0 Width of Horizontal BLK The width of H-BLANK-PULSE is set up.
Usually, it uses with initial-value:0[us].
20H：D7-D4 Startphaseofburstgate The start phase of BURST-GATE-PULSE is set up.
Feb./2005
25
TC90101FG
BUS address Function
20H：D3-D1 Set line of VBI data
slice
Contents
The line of VBI-data-slice is set up.
Usually used with center.
When it uses at the outside synchronism, it uses for the
adjustment,whenthephaseoftheoutsideVD-pulseandtheinput
signal are shifted. VBI and Macrovision detection line move at
the same time, too.
20H：D0
16LSB limit
It limit less than 16LSB at the Digital output.
Use by ON, when you use with 601/656 output.
The phase of VD is set up.
21H：D7-D5 Start phase of V at
THR-V
21H：D4-D3 Delay adjustment of
HD-OUT
Bus:111 can't be set up.
When Thru of V, Set the delay of HD-Pulse.The variability is
32W～44W (1W=27MHz).
21H：D1
21H：D0
22H：D7
22H：D6
22H：D5
22H：D4
BSRY filter
It usually uses on ON.
BSRC filter
It usually uses on ON.
HD-OUT of polarity
VD-OUT of polarity
Polatity of Field
H/V-OUT through
The polarity of the HD output is chosen.
The polarity of the VD output is chosen.
The polarity of the Field output is chosen.
H/V-OUT in 601 output is chosen.
656：H/V-pulse equal to 656.
Through：H/V-pulse equal to the input signal.
The polarity of the CKOUT is chosen.
Processing of V-Blanking is chosen.
It usually uses on O:NORMAL.
22H：D3
22H：D2
Polarity of CKOUT
V.BLK processing
The period of blanking in NORMAL are Y=16LSB (8bit) and
C=128LSB (8bit). Through is for the test.
The amplitude of the Digital output is changed.
It usually uses on O:1.71875. “1” is for the test.
The output of Cb and Cr can change.
0：Digital Format Normal
22H：D1
23H：D6
Y output Amplitude
Cb/Cr phase
1：change
23H：D5-D4 50/60Hz VD cotrol
VD output is controlled. (It becomes effective when it is set
up in 601 output.）
00：Free run
01：It is fixed on 50 or 60 on non-signal.
Frequency to fix depends on TVM2.
10：WhenVideo-systemisMANUALcontrol,asetupisalwaysfixed
on TVM2.
11：It is always fixed on TVM2 at MANUAL.
It is fixed on TVM2 at non-signals.
23H：D3
Field Det on non-signal The detection of Field is set up on non-signals.
23H：D2-D0 Ext VD phase
It is A phase in the external-VD-input.
Variable is -7.94[μs] ～ 5.96[μs].
It is H-phase of Field-detection.
24H：D7-D5 Horizontal phase for
field detection
It is the phase margin. Use with Bus:100.
24H：D4
24H：D3
V count
It is the allowable range of V-counter.
It can set margin of "V-Sep phase and H-counter".
It usually uses on 0.
V count reset
It is the specifications of reset of V-counter.
When ON, It can reduce field-miss-detection.
It usually uses on ON.
Feb./2005
26
TC90101FG
BUS address
24H：D2
Function
Contents
It is Leak-control in the AFC circuit.
It usually uses on OFF.
AFC leak control
24H：D1-D0 The order of read Data It can change order that Read-data.
00: ABCD
A：Detection、B：CCD、C：ID1、D：WSS
BUS：01=BCAD、BUS：10=CABD、BUS：11=DABC
25H：D7
25H：D6
25H：D5
Data insert of H
Data insert of V
Data insert for 601
It insert Read-data to the H period of the output.
Data is inserted after EAV at 656.
Data is inserted same place with 656 at 601.
It insert Read-data to the V period of the output.
Data is inserted after EAV at 656.
Data is inserted same place with 656 at 601.
Data can insert on either of Y or CbCr at 601 output.
Data cannot insert both line.
25H：D4-D0 Line number for insert Set line which Read-Data insert.
Data. It can set each 1-line for 1bit.
26H：D7-D4 Line number for insert Set line(in Field-Blanking) which Read-Data insert.
Data in field blank.
26H：D3-D0 For DID code
27H：D7-D0 For DID code
28H：D7-6 Histerisis for color
stripe detection
It can set each 1-line for 1bit.
This setup is DID code.
This setup is DID code.
It is Histerisis of the Color-stripe-detection.
If takes the long time, detection-time increase.
But, miss-detection decreases.
28H：D5-D4 Histerisis for color
stripe detection
It is Histerisis of the Color stripe detection-OFF.
If takes the long time, detection-OFF-time increase.
But, miss-detection decreases.
28H：D3-D2 Mask period for color
stripe detection
It is the detection period of color-stripe.
It is judged in more than the setup period.
It is the detection sensitivity of color-stripe.
It is judged in more than the setup.
28H：D1-D0 Sensitivity for color
stripe detection
29H：D7
29H：D5
29H：D4
Color stripe detection It set ON/OFF of color stripe detection.
AGC detection periode
Pulse width of Pseudo
sync
It is the Pulse width of the AGC detection.
It is the Pulse width of the pseudo-sync pulse.
29H：D2
Pseudo H sync detection It set ON/OFF of pseudo H sync detection.
29H：D1-D0 Slice level for pseudo H It set slice level of pseudo H sync.
sync
2AH：D7
2AH：D6
2AH：D4
LPF for AGC pulse &
pseudo H sync detection
It set ON/OFF of LPF for AGC pulse & pseudo H sync detection
RoutechangeofAGCpulse It is Route of “AGC pulse & pseudo H sync”.
& pseudo H sync
Switching of Route is before and after the AGC circuit.
AGC Pulse detection
It set ON/OFF of AGC Pulse detection.
2AH：D3-D2 SlicelevelforAGCpulse It set slice level of AGC pulse.
2AH：D1-D0 Histerisis time for AGC It set histerisis-time of AGC pulse detection.
pulse detection
2BH：D7
Peak AGC ON/OFF
It set ON/OFF of peak AGC.
2BH：D6-D5 Limit level of Peak AGC It set Limit level of Peak AGC.
2BH：D4
fsc Trap Filter
It set ON/OFF of fsc Trap Filter.
It set Peak AGC attack time.
2BH：D3-D2 Peak AGC attack time
Feb./2005
27
TC90101FG
BUS address
Function
Contents
2BH：D1-D0 An integral coefficient It is the integral-coefficient of Peak AGC detection.
of Peak AGC detection
2CH：D7
Sync AGC
It set ON/OFF of Sync AGC.
It set Sync AGC attack time.
2CH：D3-D2 Sync AGC attack time
2CH：D1-D0 Peak/Sync AGC recovery It set recovery time of Peak AGC and Sync AGC.
time
2DH：D7
2DH：D6
LPF for CCD
CCD slice function mode It set mode of CCD slice function.
Level changes by the input amplitude,when Auto mode.
It set CCD slice level.
It set ON/OFF of LPF for CCD.
2DH：D5
2DH：D3
2DH：D2
CCD slice level
It is effective when 2DH:D6 is set a fix.
It set phase width of ID1 detection.
Phase width of ID1
detection
CCD Start bit detection It is the detection sensitivity of the start bit of CCD.
2DH：D1-D0 Select CCD field
It set field that detect CCD.
2EH：D7
2EH：D6
LPF for ID1
It set ON/OFF of LPF(Input stage of ID1-detection circuit)
ID1 data slice function It set ID1 data slice function.
When Auto slice,slice level changes by the input amplitude.
It set ID1 slice level.
It is effective when 2EH:D6.
Detection for amplitude It is the reference amplitude of the detection.
of ID1 signal When it is off, Amplitude detection becomes AUTO.
2EH：D5-D4 ID1 slice level
2EH：D3
2EH：D2
Phase of ID1 detection It is the reference phase of the ID1 detection.
When Adaptive , it can search in the range of ±1.1μs
at the D1.
2EH：D1-D0 Sampling phase of ID1
It is the phase of the detection of ID1.
"1" changes in 0.12µs unit at D1, 0.28µs unit at D2.
It usually uses on "0".
2FH：D7
2FH：D6
LPF for WSS1
It set ON/OFF of LPF(Input stage of WSS-detection circuit)
WSS data slice function It set WSS data slice function.
When Adaptive slice,slice level changes by the input
amplitude.
2FH：D5-D4 WSS slice level
It set WSS slice level.
It is effective when 2FH:D6.
It set detection sensitivity of start-code of WSS.
It set field that detect WSS.
2FH：D2
WSS SC Det mode
2FH：D1-D0 Select WSS field
30H：D7-D4 AdjustlinetimingofCCD It is Delay-adjust of LINE-timing for the CCD detection.
It uses when detection start deviates in weak electric density
30H：D3-D0 AdjustlinetimingofID1 It is Delay-adjust of LINE-timing for the ID1 detection.
It uses when detection start deviates in weak electric density
31H：D7-D4 AdjustlinetimingofWSS It is Delay-adjust of LINE-timing for the WSS detection.
It uses when detection start deviates in weak electric density
31H：D3
fsc pull in
It set sensitivity of Pulled-in of fsc.
High: Sensitivity is up.
31H：D2
13.5MHz trap
It set ON/OFF of 13.5MHz Trap at ADC.
It usually uses on "ON".
31H：D1
31H：D0
IIR Filter selection
IIR Filter ON/OFF
Characteristic selecting of C-filter of SECAM.
It set ON/OFF of C-filter of SECAM.
A color beat can be reduced.
It usually uses on "Always ON" in SECAM.
Feb./2005
28
TC90101FG
BUS address
32H：D7
Function
D1/D2 Det
Contents
It is the distinction of D1/D2.
It is effective 32H:D6 when manual set.
Internal control is fixed with D1orD2.
32H：D6
D1/D2 Manual set
32H：D5-D4 Internal feed-back-
clamp
When clamp set internal, it can set time constant.
33H：D7
Manual Gain AGC
It set ON/OFF of Peak-AGC Gain.
It is effective when it is ON.
It gives priority to Manual when this bit is ON. Therefore,
it can't get the effect of AGC.
33H：D6-D0 Manual Gain
It is effective when 33H(D7).
Gain becomes a fix.
34H：D7-D4 CGP start phase
34H：D3-D0 Width of CGP
It set start phase of CGP(Output of Terminal-73).
It set width of CGP(Output of Terminal-73).
It set threshold for DET.443.
35H：D7-D4 Threshold for DET.443
It is easy to distinguish when a MAX side is chosen.
35H：D1-D0 Sync-tip-clamp-mode for It is the control of limit-clamp to add under the input signal
at Y input.
Y-input
Four kinds of switchings are possible.
ON:Always,limitter-clamp to add to Low-level of input is ON.
OFF:Always,limitter-clamp to add to Low-level of input is off.
AUTO1：It is ON in the no-signal and 'When Pedestal-Level
deviated greatly.'
AUTO2：It is ON on no-signal.
36H：D7
CGP OUT control
It set action of CGP.
AUTO: It is output only when an input signal is set 11(D7 and
D6 on 00H).
Forced on: It is output to all the input.
It is ON, when you want reduce Cross-color and beat.
The Blanking period becomes mute.
36H：D6
36H：D0
37H：D7
C Trap of DCOMB
Mute
Y Noise
It set f0 of Y-Noise-Canceler.
It usually uses on "0".
37H：D6
37H：D5
37H：D4
37H：D3
Y Noise Lim
It set Limitter of Y-Noise-Canceler.
It set Gain of Y-Noise-Canceler.
Y Noise Gain
Y Noise canceler
CKILL Gain
It set ON/OFF of Y-Noise-Canceler.
It set the condition of CKILL Gain.
When it is set up in +6dB, Level which color disappears to
grows big. It uses ”0” when weak electric density.
It set Limitter of C-Noise-Canceler.
It set Gain of C-Noise-Canceler.
37H：D2
37H：D1
37H：D0
C Noise lim
C Noise Gain
C Noise canceler
It set ON/OFF of C-Noise-Canceler.
Feb./2005
29
TC90101FG
MAXIMUN RATINGS（Vss=0V, Ta=25℃）
Each item of the maximum rating shows the marginal value of this product. Since a product is sometimes
damaged when rating is exceeded also one item or for a moment again, be sure to use it within rating.
ＣＨＡＲＡＣＴＥＲＩＳＴＩＣ
Power Supply Voltage1（1.5V System）
Power Supply Voltage2（2.5V System）
Power Supply Voltage3（3.3V System）
SYNBOL
VDD１
VDD２
VDD３
VIN
ＲＡＴＩＮＧ
UNIT
Ｖ
-0.3 ～ VSS+2.0
-0.3 ～ VSS+3.5
-0.3 ～ VSS+3.9
-0.3 ～ VDDIO +0.3
Ｖ
Ｖ
Ｖ
Input Voltage
SDA/SCL(Note1) -0.3 ～ VSS + 5.5
Ｖ
A IN
-0.3 ～ VDDAD+0.3
0.3
Ｖ
Potential difference between power supply terminals
（1.5V System）
VDG1（Note2）
Ｖ
Potential difference between power supply terminals
（2.5V System）
VDG2（Note2）
VDG3（Note2）
VDG4（Note2）
VDG5（Note2）
0.3
0.3
0.3
0.3
Ｖ
Ｖ
Ｖ
Ｖ
Potential difference between power supply terminals
（3.3V System）
Potential difference between power supply terminals
（1.5V System＞2.5V System）
Potential difference between power supply terminals
（2.5V System ＞3.3V System）
Power Dissipation
ＰＤ(Note3)
Ｔｓｔｇ
1900
ｍW
℃
Storage Temperature
-40 ～ 125
(Note1) SDA，SCL： 5V tolerance.
(Note2) 1.5V system power supply terminal is made into the same voltage, 2.5V system power
supply terminal is made into the same voltage, and 3.3V system power supply terminal
is made into the same voltage.
The maximum potential difference should not exceed rating for all power supply
terminals then.
(Note3) Derated above Ta=25℃ in the proportion of 19mW/℃.
Operation conditions（Vss=0V）
Cannot guarantee operation of TC90A92F, when the recommendation power supply voltage
range (1.40V-1.65V, 2.3V-2.7V, 3.0V-3.6V) is exceeded.
Once, when it returns from the over range, it differs from a front condition.
ＣＨＡＲＡＣＴＥＲＩＳＴＩＣ
Supply Voltage for digital block
Supply Voltage for I/O block
Supply Voltage for XO block
Supply Voltage for PLL block
Terminal No.
SYNBOL
DVDD1-5
VDDIO1-3
VDDXO
MIN
1.40
3.0
TYP
1.5
3.3
3.3
2.5
2.5
－
MAX
1.65
3.6
UNIT
V
15,32,39,54,66
23,49,60
V
6
2
3.0
3.6
V
VDDPLL
2.3
2.7
V
Supply Voltage for Analog block 82,89,95,97
Ambient operating temperature
VDDAD/VDDDA 2.3
Ｔopr -10
2.7
V
-
75
℃
Feb./2005
30
TC90101FG
The condition of power (VDD=3.3V, 2.5V, 1.5V) rising and falling
(1)Power Supply rising
These contents are the important items which influence the reliability guarantee of the IC.
It is necessary to satisfy the following condition.
(1) Power rising condition
3.3V (power range : 3.0～3.6V)
more than 3.0V
*note1
2.5V (power range : 2.3～2.7V)
VDD=3.3V
more than 0.4V
more than 2.3V
*note1
VDD=2.5V
more than 0.4V
1.5V (power range : 1.4～1.65V)
more than 1.4V
*note1
VDD=1.5V
more than 0.4V
It needs to rise less than 40ms from starting to rise the power of 2.5V.
(reset release)
Terminal 30：RESET
After all powers rising, it is necessary to keep resetting more
than 0.5ms.
And it must not keep the reset conditions more than one
minute.
IIC-Bus IN
Terminal31：SDA
Terminal 32：SCL
After reset release, it is necessary to be more than 100ns for
IIC BUS control starting.
3.3V power
terminal
*note1
Such the power terminal are embedded the protective diode.
It must not send a penetration electric current.
Condition:
Power level of 3.3V line ≧Power level of 2.5V line ≧Power level of 1.5V line
When the power level of 1.5V line is more than 0.4V, 3.3V line and 2.5V line must
reach the level of power more than 0.4V.
2.5V power
terminal
And when the power level of 2.5V line is more than 0.4V, 3.3V line must reach
the level of power more than 0.4V.
1.5V power
terminal
(2) Power falling condition
It is necessary to fall the power of 1.5V line before 3.3V line and 2.5V line are fallen, and to fall the power of
2.5V line before 3.3V line is fallen.
It must not send a penetration electric current too.
Feb./2005
31
TC90101FG
ELECTRICAL CHARACTERRISTICS
(1)DC CHARACTERRISTICS
（Ta=25℃,VDD1=1.50±0.1V,VDD2=2.50±0.2V,VDD3=3.30±0.3V)
ITEM
Terminal No.
Symbol
IDD1
Min.
Typ.
Max.
Unit
mA
Note
Power
Supply
Current
15,32,39,54,66
Sum total current of 1.5V
system power supply terminal
NTSC:Y/C IN, Color Bar Signal
Sum total current of 2.5V
system power supply terminal
NTSC:Y/C IN, Color Bar Signal
Sum total current of 3.3V
system power supply terminal
Changes with the loads of I/O.
I/O input terminal of
30
45
70
2,82,89,95,97
6,23,49,60
IDD2
IDD3
mA
mA
V
80
105
30
135
15
60
Input
10,11,12,13,14,16,17, VIH
VDD3x0.8
VDD3
Voltage 18,20,21,22,24,25,28,
29,30,31,50,51
3.3V system
26,27,33
I/O input terminal of
5.0V system
10,11,12,13,14,16,17, VIL
18,20,21,22,24,25,28,
29,30,31,50,51
VSS
VDD3x0.2
VDD3x0.2
0.3
V
I/O input terminal of
3.3V system
26,27,33
I/O input terminal of
5.0V system
5.0V Pull up use
I/O input terminal of
5.0V system
3.3V Pull up use
3 I/O input terminal of
3.3V system
Input
10,11,12,13,14,16,17, IIH
-10
10
μA
μA
V
Current 18,20,21,22,24,25,28,
29,30,31,50,51
26,27,33
I/O input terminal of
5.0V system
10,11,12,13,14,16,17, IIL
18,20,21,22,24,25,28,
29,30,31,50,51
-10
10
I/O input terminal of
3.3V system
26,27,33
I/O input terminal of
5.0V system
Output
35,36,37,38,40,41,43, VOH
VDD3-0.6
VDD3
0.4
I/O output terminal of
3.3V system
Voltage 44,46,47,48,52,53,55,
56,58,59,61,62,64,65,
67,68,70,71,72,73,74,
75
Load of 4mA outflow
35,36,37,38,40,41,43, VOL
44,46,47,48,52,53,55,
56,58,59,61,62,64,65,
67,68,70,71,72,73,74,
75
VSS
V
I/O output terminal of
3.3V system
Load of 4mA inflow
26
I/O output terminal of
5.0V system
Load of 4mA inflow
Notice : The specifications of VIL is difference in the Pull-up voltage.
When it specially uses for 3.3V with pull-up, do the design which is less than 0.3V securely.
Feb./2005
32
TC90101FG
(2)AC CHARACTERRISTICS
（Ta=25℃,VDD1=1.50V,VDD2=2.50V,VDD3=3.30V)
ITEM
Symbol
VYIN
VCIN
Min.
Typ.
Max.
Unit
Note
AD input level for Y
AD input level for C
0.7 0.8 Vp-p White 100% Signal
0.5 0.8 Vp-p Cb/Cr input
ADCdifferentiationerror DLEa
±4
±4
LSB
LSB
ADC integration error
Output impedance
ILEa
Zy
160 200 240 Ω
(3)PLLCHARACTERRISTICS
（Ta=25℃,VDD1=1.50V,VDD2=2.50V,VDD3=3.30V)
ITEM
Symbol
Min.
Typ.
Max.
Unit
Note
Drawing-infrequencyrange ΔfckN -50
Operation input amplitude Vck
50
kHz Clock Amplitude:0.5Vp-p
0.3 0.5 2.0 Vp-p Standard clock frequency input
Feb./2005
33
TC90101FG
Application
②
1.5V
3.3V
1.5V
18k
18k
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
BIASYAD
TESTM5
VDDIO1
76
1.5
50
49
3.3
1.5
0.01μ
0.01μ
②
3.3V
77 VRTYAD
0.01μ
LPF
YIN
78
79
80
CKOUT 48
YOUT0 47
NP 0.47μ
VSSYAD
3.3
①
VRMYAD
46
YOUT1
2.5
0.01μ
0.1μ
LPF
CVBS IN
VDDYAD
81
82
45
VSSIO1
NP 0.47μ
②
YOUT2 44
2.5V
TC90101FG
83 VRBYAD
43
42
41
40
39
YOUT3
0.01μ
84 BIASCAD
DVSS3
YOUT4
YOUT5
DVDD3
YOUT6
YOUT7
0.01μ
0.01μ
Top view
85 VRTCAD
86 CIN
②
1.5
LPF
0.01μ
87 VSSCAD
88 Cb IN
89 VDDCAD
①
0.01μ
1.5V
LPF
2.5
38
37
36
35
34
33
0.1μ
NP 0.47μ
2.5V
VRBCAD
90
91
YOUT8
YOUT9
DVSS2
0.01μ
0.01μ
BIASRAD
92 VRTRAD
93 VSSRAD
②
0.01μ
1.5 CSYNC IN
①
2.5
LPF
94
95
Cr IN
DVDD2 32
0.1μ
0.01μ
NP 0.47μ
2.5V
1.5V
VDDRAD
31
TESTM4
96 VRBRAD
97 VDDDA
98 DAOUT
99 VSSDA
30
29
28
27
26
TESTM3
0.01μ
22μ 0.1μ
TESTM2
TESTM1
SCL
2.5V
2.5
1.5k
1.5
3.3
100
BIASDA
2.5
SDA
3.3
4p
1.2k
0.01μ
0.01μ
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
25
5V可
0.01μ
①
0.01μ
0.1μ
0.01μ
0.01μ
1500p
42M
22p
①Analog GND
②Digital GND
1.5V
22μ
②
②
3.3V
18p
2.5V
1000p
①
10μ
②
3.3V
Feb./2005
34
TC90101FG
● PACKAGE OUTLINE
LQFP100-P-1414-0.50C
UNIT:mm
Weight：0.65g（center）
Feb./2005
35
TC90101FG
About soloderability, following conditions were confirmed.
● Solderability
(1)Use of Sn-63Pb solder Bath
・solder bath temperature=230℃
・dipping time=5seconds
・the number of times=once
・use of R-type flex
(2)Use of Sn-3.0Ag-0.5Cu solder Bath
・solder bath temperature=245℃
・dipping time=5seconds
・the number of time=once
・use of R-type flex
030619EBA
RESTRICTIONS ON PRODUCT USE
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety
in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and
sold, under any law and regulations.
Feb./2005
36
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