TC9318AFAG_技术文档

TC9318AFAG/AFBG

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC9318AFAG,TC9318AFBG

Single Chip DTS Microcontroller (DTS-21)

The TC9318AFAG and TC9318AFBG are a 4 bit CMOS

microcontroller for signal chip digital tuning systems. It is

capable of functioning at a low voltage of 3 V and features a

built-in prescaler of operating 230 MHz, PLL and LCD drivers.

The CPU has 4 bit parallel addition and subtraction

instructions (e.g., AI, SI), logic operation instructions (e.g., OR,

AN), composite judging and compare instructions (e.g., TM, SL),

and time-base functions.

TC9318AFAG

The package is an pin 64, 0.5/0.65-mm-pitch quad flat pack

package. In addition to various input/output ports and a

dedicated key-input port, which are controlled by powerful

input/output instructions (IN 1, 2, OUT 1, 2), there are many

dedicated LCD pins, a buzzer port, a 6 bit A/D converter, an IF

counter, and other pins.

TC9318AFBG

Low-voltage and low-current consumption make this

microcontroller suitable for portable DTS equipment.

Features

•

4 bit microcontroller for digital tuning systems.

Operating voltage V = 1.8~3.6 V, with low current

DD

consumption because of CMOS circuitry (with only CPU

operating, when V = 3 V, I = 80 µA max)

Weight

P-LQFP64-1010-0.50E: 0.32 g (typ.)

P-LQFP64-1212-0.65A: 0.45 g (typ.)

DD

•

Built-in prescaler (1/2 fixed divider +2 modulus prescaler:

fmax ≥ 230 MHz)

•

Features built-in 1/3-duty, 1/2-bias LCD drivers and a built-in 3 V booster circuit for the display.

Data memory (RAM) and ports are easily backed up.

Program memory (ROM): 16 bit × 4096 steps

Data memory (RAM): 4 bit × 256 words

60-instruction set (all one-word instructions)

Instruction execution time: 40 µs (with 75 kHz crystal) (MVGS, DAL instructions: 80 µs)

Many addition and subtraction instructions (12 types addition, 12 types subtraction)

Powerful composite judging instructions (TMTR, TMFR, TMT, TMF, TMTN, TMFN)

Data can be transmitted between addresses on the same row. (MVSR instruction)

Register indirect transfer available (MVGD, MVGS instruction).

16 powerful general registers (located in RAM)

Stack levels: 2

JUMP or CAL instruction can be used anywhere in the 4096 steps of program memory (ROM) as there are no

pages or fields.

•

16 bit of any address in the 1024 steps in program memory (ROM) can be referenced (DAL instruction).

Features independent frequency input pins (FM and AM ) and two (DO1 and DO2) phase comparison

IN IN

outputs for FM/VHF and AM.

•

Seven reference frequencies can be selected by program.

Powerful input/output instructions (IN 1, 2, OUT 1, 2)

Dedicated input ports (K ~K ) for key input. 26 LCD drive pins (69 segments maximum) available.

0

3

17 I/O ports: 10 with input/output programmable in 1 bit units, and 7 output-only port. The 2 IF , and DO1

IN

pins can be switched by instruction to IN (input-only) or OT (output-only).

•

Three back-up modes available by instruction: Only CPU operation, crystal oscillation only, clock stop.

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TC9318AFAG/AFBG

•

Features a built-in 2 Hz timer F/F and a built-in 10/100 Hz interval pulse output (internal port for time base).

Allows PLL lock status detection.

8 of the LCD segment outputs (S ~S ) can also operate as key return timing outputs (KR ~KR ). The I/O

16 23

0

7

ports are not dedicated key return timing outputs but can have other uses as well.

•

Built-in 20 bit, general-purpose IF counter can detect stations during auto-tuning by counting the intermediate

frequencies of each band.

•

Built-in 8 bit buzzer output circuit can produce 254 different tone signals.

Features a built-in 2-channel, 6 bit A/D converter.

To prevent CPU malfunctions, a built-in supply voltage drop detection circuit shuts down the CPU when voltage

falls below 1.5 V.

Pin Assignment (top view)

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TC9318AFAG/AFBG

Block Diagram

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TC9318AFAG/AFBG

Explanation of Function

Pin No.

1

Symbol

Pin Name

Function and Operation

Remarks

Output common signals to the LCD panel.

COM1

Through a matrix with pins S ~S , a maximum of

1

23

69 segments can be displayed.

Three levels, V

83 Hz every 2 ms.

, V , and GND, are output at

LCD EE

LCD common output

2

3

COM2

COM3

V

EE

is output after SYSTEM RESET and CLOCK

STOP are released, and a common signal is

output after the DISP OFF bit is set to “0”.

Segment signal output pins for the LCD panel.

Together with COM1, COM2, and COM3, a matrix

is formed that can display a maximum of 69

segments.

4~18

S ~S

LCD segment output

1

15

The signals for the key matrix and the segment

LCD segment

output/Key return

timing output

signals from pins S /KR ~S /KR are output on

16

7

23

0

S

16

S

23

/KR ~

7

19~26

a time division basis. 4 × 8 = 32 key matrix can be

/KR

0

created in conjunction with key input ports K ~K .

0

3

4 bit input ports for key matrix input.

Combined in a matrix with key return timing

outputs of the LCD segment pins, data from a

maximum of 4 × 8 = 32 keys can be input and pins

are pulled up. On the key seteutining output pins,

data from 4 × 6 = 24 keys can be input and pins

are pulled down. The WAIT mode is released

when high level is applied to key input ports set to

pull-down.

27~30 K ~K

Key input ports

0

3

These ports output the timing signal for key

matrix. To form the key matrix, load resistance

has been built-in the N-channel side. When the

key matrix combined with push-key, that does not

need a key matrix diode.

Key return timing

output port

31~36 T ~T

0

5

The input and output of these 4 bit I/O ports can

be programmed in 1 bit units.

By altering the input to I/O ports set to input, the

CLOCK STOP and WAIT modes can be released,

and the MUTE bit of the MUTE pin can be set to

“1”.

37~40 P1-0~P1-3

I/O port 1

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TC9318AFAG/AFBG

Pin No.

Symbol

Pin Name

Function and Operation

4 bit I/O ports.

Remarks

Input and output may be programmed in 1 bit

units.

Pins P2-1 through P2-2 can also be used for

analog input to the built-in 6 bit, 2-channel A/D

converter.

P2-0

I/O port 2

P2-1/AD

/AD analog voltage Conversion time of the built-in A/D converter using

IN1

IN2

input

the successive comparison method is 280 µs. The

necessary pin can be programmed to AD analog

input in 1 bit units, and P2-3 can be set to the

reference voltage input. Internal power supply

41~44

P2-2/AD

/AD analog voltage

input

(V ) or constant voltage (V ) can be used as

the reference voltage. In addition, constant

DD

EE

P2-3/

DC-REF

/Reference voltage

input

voltage (V ) can be input to the AD analog input

EE

so battery voltage, etc., can be easily detected.

The reference voltage input, for which a built-in

operational amp is used, has high impedance.

The A/D converter, and their control are all

executed by program.

2 bit I/O ports, whose input/output can be

programmed in 1 bit units.

The P3-1 pin also functions as the output for the

built-in buzzer circuit. The buzzer sound can be

output in 254 different tones between 18.75 kHz

and 147 Hz, and at a duty of 50%.

P3-0

I/O port 3

45~46

P3-1/BUZR

/Buzzer output

The buzzer output, and all associated controls can

be programmed.

1 bit output port. Normally, this port is used for

muting control signal output.

This pin can set the internal MUTE bit to “1”

according to a change in the input of I/O port 1.

MUTE bit output logic can be changed; PLL phase

difference can also be output using this pin.

47

MUTE

Muting output port

Input pin used for controlling TEST mode. High

level indicates TEST mode, while low level

indicates normal operation. The pin is normally

used at low level or no-connection (NC). (a

pull-down resistor is built-in).

TEST mode control

input

48

TEST

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TC9318AFAG/AFBG

Pin No.

Symbol

Pin Name

Function and Operation

Remarks

Input pin for request/release HOLD mode.

Normally, this pin is used to input radio mode

selection signals or battery detection signals.

HOLD mode includes CLOCK STOP mode (stops

crystal oscillation) and WAIT mode (halts CPU).

Setting is implemented with the CKSTP instruction

or the WAIT instruction. When the CKSTP

instruction is executed, request/release of the

HOLD mode depends on the internal MODE bit. If

the MODE bit is “0” (MODE-0), executing the

CKSTP instruction while the HOLD pin is at low

level stops the clock generator and the CPU and

changes to memory back-up mode. If the MODE

bit is “1” (MODE-1), executing the CKSTP

49

HOLD

HOLD mode control

input

instruction enters memory back-up mode

regardless of the level of the HOLD pin. Memory

back-up is released when the HOLD pin goes

high in MODE-0, or when the level of the HOLD

pin level in MODE-1.

When memory back-up mode is entered by

executing a WAIT instruction, any change in the

HOLD pin input releases the mode.

In memory back-up mode, current consumption is

low (below 10 µA), and all the output pins (e.g.,

display output, output ports) are automatically set

to low level.

IF counter’s IF signal input pin for counting the IF

signals of the FM and AM bands and detecting the

automatic stop position.

The input frequency is between 0.35~12 MHz (0.2

V

_p-p(min)). A built-in input amp and C coupling

50

IF /IN

IN

IF signal input/Input

port

allow operation at low-level input.

The IF counter is a 20 bit counter with optional

gate times of 1, 4, 16, and 64 ms. 20 bits of data

can be readily stored in memory.

This input pin can be programmed for use as an

input port (IN port). CMOS input is used when the

pin is set as an IN port.

PLL’s phase comparison tri-state output pins.

When the programmable counter’s prescaler

output is higher than the reference frequency,

output is at high level. When output is lower than

the reference frequency, output is at low level.

When output equals the reference frequency, high

impedance output is obtained.

51

52

DO1/OT

DO2

Phase comparison

output/Output port

Phase comparison

output

Because DO1 and DO2 are output in parallel,

optimal filter constants can be designed for the

FM/VHF and AM bands.

Pin DO1 can be programmed to high impedance

or programmed as an output port (OT). Thus, the

pins can be used to improve lock-up time or used

as output ports.

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TC9318AFAG/AFBG

Pin No.

Symbol

Pin Name

Function and Operation

Remarks

Pins to which power is applied.

Normally, V = 1.8~3.6 V (3.0 V typ.) is applied.

DD

In back-up mode (when CKSTP instructions are

being executed), voltage can be lowered to 1.0 V.

If voltage falls below 1.5 V while the CPU is

operating, the CPU stops to prevent malfunction

(STOP mode). When the voltage rises above 1.5

V, the CPU restarts.

56

V

DD

STOP mode can be detected by checking the

STOP F/F bit. If necessary, execute initialization

or adjust clock by program. When detecting or

preventing CPU malfunctions using an external

circuit, STOP mode can be invalidated and

rendered non-operative by program. In that case,

all four bits of the internal TEST port should be set

to “1”.

Power-supply pins

53

GND

If more than 1.8 V is applied when the pin voltage

is 0, the device's system is reset and the program

starts from address “0”. (power on reset)

Note: To operate the power on reset, the power

supply should start up in 10~100 ms.

Programmable counter input pin for FM, VHF

band.

The 1/2 + pulse swallow system (VHF mode) and

the pulse swallow system (FM mode) are

selectable freely by program.

At the VHF mode, local oscillation output (VCO

output) of 50~230 MHz (0.2V_p-p(min)) is input and

FM mode, 40~130 MHz (0.2V_p-p(min)) is input.

FM programmable

counter input

54

FM

IN

A built-in input amp and C coupling allow

operation at low-level input.

Note: When in the PLL OFF mode or when set to

AM input, the input is pulled down.

IN

Programmable counter input pin for AM band.

The pulse swallow system (HF mode) and direct

dividing system (LF mode) are freely selectable by

program. At the HF mode, local oscillation output

(VCO output) of 1~45 MHz (0.2 V_p-p(min)) is input

and LF mode, 0.5~12 MHz (0.2 V_p-p(min)) is input.

AM local oscillator

signal input

55

AM

IN

Built-in input amp operates with low-level input

using a C coupling.

Note: When in PLL OFF mode or when set to

FM input, the input is pulled down.

IN

Input pin for system reset signals.

RESET takes place while at low level; at high

level, the program starts from address “0”.

Normally, if more than 1.8 V is supplied to V

DD

when the voltage is 0, the system is reset (power

on reset).

57

RESET

Reset input

Accordingly, this pin should be set to high level

during operation.

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TC9318AFAG/AFBG

Pin No.

58

Symbol

Pin Name

Function and Operation

Remarks

X

V

Crystal oscillator pins.

A reference 75 kHz crystal oscillator is connected

OUT

to the X and X pins.

IN

OUT

Crystal oscillator

pins

The oscillator stops oscillating during CKSTP

instruction execution.

59

60

IN

The V pin is the power supply for the crystal

XT

oscillator. A stabilizing capacitor (0.47 µF typ.) is

connected.

XT

Voltage doubler boosting pin for driving the LCD.

A capacitor (0.1 µF typ.) is connected to boost the

61

62

63

V

LCD

voltage.

The V

pin outputs voltage (3.0 V), which has

LCD

been doubled from the constant voltage (V : 1.5

EE

V) using the capacitors connected between C

1

Voltage doubler

boosting pin

C

1

2

and C . That potential is supplied to the LCD

2

drivers. If the internal V

OFF bit is set to “1” by

LCD

program, an external power supply can be input

through the V pin to drive the LCD.

LCD

At this time, the V

voltage is divided using registers, is output from

/2 potential, whose V

LCD

C

the C pin.

2

1.5 V constant voltage supply pin for driving the

LCD.

Constant voltage

supply pin

A stabilizing capacitor (0.1 µF typ.) is connected.

This is a reference voltage for the A/D converter,

key input, and the LCD common output’s bias

potential.

64

V

⎯

EE

Note 1: When the device is reset (voltage higher than 1.8 V, or when RESET = low → high) I/O ports are set to

input, the pins for I/O ports and additional functions (e.g., A/D converter) are set to I/O port input pins, while

the IF /IN pins become IF input pins.

IN

Note 2: When in PLL OFF mode (when the three bits in the internal reference ports all show “1”), the IF and FM

IN

,

IN

AM pins are pulled down, and DO1 and DO2 are at high impedance.

IN

Note 3: When in CLOCK STOP mode (during execution of CKSTP instruction), the output ports and the LCD output

pins are all at low level, while the constant voltage circuit (V ), the voltage doubler circuit (V ), and the

EE LCD

power supply for the crystal oscillator (V ) are all off.

XT

Note 4: When the device is being reset, the contents of the output ports and internal ports are undefined and

initialization by program is necessary.

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TC9318AFAG/AFBG

Explanation of Operation

CPU

CPU is composed of program counter, stack register, ALU, program memory, data memory, G-register, carry

F/F and judging circuit.

1. Program Counter (PC)

Program Counter is a block to designate the address of program memory (ROM), and is composed of 12

bits binary up counter. This is cleared by system reset, and the program starts from zero address.

Usually, it’s increment is made one by one everytime the one instruction is executed, but when JUMP

instruction or CAL instruction is executed, the address designated at operand part of that instruction is

loaded.

Further, when the instruction (AIS, SLTI, TMT, RNS instructions, etc.) having skip function is executed,

two increments of program counter is made if the result is the condition to be skipped, and the succeeding

instruction is skipped.

2. Stack Register (STACK)

This is a register composed of 2 × 12 bits during the execution of subroutine call instruction, the value

obtained by adding +1 to the content of program counter, namely return address, is housed. The content of

stack register is loaded on the program counter by the execution of return instruction. (RN, RNS

instructions)

This stack level is 2 level, and nesting is 2 level.

3. ALU

ALU has binary 4 bits parallel addition and subtraction, logical operation, comparison and plural bit

judge functions.

This CPU has no accumulator, and all operations directly treat the contents of data memory.

4. Program Memory (ROM)

Program memory is composed of 16 bit × 4096 steps and is the address of 000H~FFFH.

Program memory has no concept of page or field, so JUMP instruction and CAL instruction can be freely

used among 4096 steps.

Further, it is possible to use optional address of program memory as data area, and its content, 16 bits,

can be loaded to the data register by executing DAL instruction.

Note 5: Provide the data area at the address outside the program loop in the program memory.

Note 6: In DAL instruction, the address of program memory can be designated as the data area becomes 1024

steps of 000H~3FFH.

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TC9318AFAG/AFBG

5. Data Memory (RAM)

Data memory is composed of 4 bit × 256 words and used for storing data.

This 256 words are expressed with row address (4 bits) and column address (4 bits).

192 words (row address = 4H~FH) among the data memory are indirect addressing by G-register. For

this reason, when carrying out data processing within this territory, it is necessary to designate row

address by G-register beforehand Area of 00H~0FH address in data memory is called general register, and

can be used only by designating column address (4 bits). These 16 general registers can be used for

operation and transfer between data memories. Further, it can also be used as ordinary data memory.

Note 7: The column address (4 bits) to designate general register becomes register number of the general

register.

Note 8: It is also possible to indirectly designate all of row address (= 0H~FH) by G-register.

6. G-Register (G-REG.)

G-register is a 4 bits register for addressing row address (D = 4H~FH) of 192 words in data memory.

R

Content of this register is effective during executing MVGD instruction, MVGS instruction, and is not

related with the execution of other instructions.

This register is treated as one of the port, and its content is set by the execution of OUT1 instruction

among input and output instructions.

(refer to register port item 1)

7. Data Register (DATA REG.)

This is a register composed of 1 × 16 bits. In this register, 16 bits data of optional address among the

program memory in 000H~3FFH is loaded during executing of DAL instruction. This register is treated as

one of the port, and when IN1 instruction among input and output instruction is executed, it’s content is

read in the data memory in 4 bits unit.

(refer to register port item 2)

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TC9318AFAG/AFBG

8. Carry F/F (C･F/F)

This is set when carry or borrow is produced as a result of executing operational instruction, and is reset

when it is not produced. Content of carry F/F changes only when addition and subtraction instruction is

executed, and does not change during the execution of other instructions.

9. Judging Circuit (J)

When a instruction with skip function is executed, this circuit judges it’s skip condition. When skip

condition is satisfied, this circuit makes two increments of program counter, and skips the succeeding

instruction.

It is provided with 29 kinds of instructions having abundant skip function.

(refer to item 11, explanation list of function and operation of instructions, * marked instruction)

10. List of Instruction Set

60 kinds of instruction set are included, all of which consisting of one word instruction.

These instructions are expressed with 6 bits instruction code.

Higher Rank 2 Bits

00

0

01

1

10

2

11

3

Lower Rank 4 Bits

0000

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

AI

M, I

AD

r, M

TMTR

TMFR

SEQ

SNE

r, M

SLTI

SGEI

SEQI

SNEI

TMTN

TMT

TMFN

TMF

IN1

M, I

0001

AIS

M, I

ADS

ADN

AC

r, M

M, r

r, M

M, r

M, I

0010

AIN

M, I

0011

AIC

M, I

0100

AICS

AICN

ORIM

ANIM

SI

ACS

ACN

ORR

ANDR

SU

LD

M, N

M, C

0101

ST

0110

MVGD

MVGS

0111

1000

1001

SIS

SUS

SUN

SB

IN2

CALL ADDR

1

1010

SIN

⎯

1011

SIB

OUT1

OUT2

C, M

1100

SIBS

SIBN

XORI

SBS

SBN

XORR

1101

⎯

JUMP ADDR

1

1110

DAL ADDR , r

2

RN, RNS, WAIT

CKSTP, NOOP

1111

F

MVIM

M, I

MVSR

M , M

1 2

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TC9318AFAG/AFBG

11. Explanation List of Function and Operation of Instructions (explanation of symbols)

M: Data memory address

Normally, one of 00H~3FH address of data memory.

r: General register

One of 00H~0FH address of data memory.

PC: Program counter (12 bit)

STACK: Stack register (12 bit)

G: G-register (4 bit)

DATA: Data register (16 bit)

I: Immediate data (4 bit)

N: Bit position (4 bit)

⎯: All “0”

C: Code No. of port (4 bit)

C : Code No. of port (4 bit)

N

R : General register No. (4 bit)

N

ADDR : Program memory address in page 0 or 1 (12 bit)

1

ADDR : Higher rank 6 bit of program memory address in page 0

2

Ca: Carry

b: Borrow

IN1~IN2: Port treated during the execution of IN1~IN2 instruction

OUT1~OUT2: Port treated during the execution of OUT1~OUT2 instruction

(

[

): Register or data memory content

: Content of port indicated by code No. C (4 bit)

]

C

]: Content of data memory indicated by the content of register or data memory

: Content of program memory (16 bit)

]

P

IC: Instruction code (6 bit)

*: Instruction having skip function

D : Data memory column address (4 bit)

C

D : Data memory row address (2 bit)

R

P: Wait condition

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TC9318AFAG/AFBG

Machine Language (16 bit)

Mnemonic

Explanation of Function Explanation of Operation

IC

A

B

C

(6 bit)

(2 bit)

(4 bit)

Add immediate data to

M ← (M) + I

AI

M, I

000000

D

I

R

C

memory

M ← (M) + I

Add immediate data to

AIS

*

000001

D

I

memory, then skip if carry

Skip if carry

Add immediate data to

memory, then skip if not

carry

M ← (M) + I

AIN

AIC

M, I

000010

000011

000100

D

R

D

R

D

R

D

C

D

C

D

C

I

Skip if not carry

Add immediate data to

memory with carry

M ← (M) + I + ca

Add immediate data to

memory with carry, then

skip if carry

M ← (M) + I + ca

AICS

AICN

M, I

*

Skip if carry

Add immediate data to

memory with carry, then

skip if not carry

M ← (M) + I + ca

000101

D

R

D

C

I

Skip if not carry

Add memory to general

register

AD

r, M

r ← (r) + (M)

010000

010001

D

R

C

N

r ← (r) + (M)

Add memory to general

register, then skip if carry

ADS

*

R

C

N

Skip if carry

Add memory to general

register, then skip if not

carry

r ← (r) + (M)

ADN

AC

r, M

010010

010011

010100

D

R

D

R

D

R

D

C

D

C

D

C

R

N

R

N

R

N

Skip if not carry

Add memory to general

register with carry

r ← (r) + (M) + ca

Add memory to general

register with carry, then

skip if carry

r ← (r) + (M) + ca

ACS

*

Skip if carry

Add memory to general

register with carry, then

skip if not carry

r ← (r) + (M) + ca

ACN

r, M

010101

D

R

D

C

R

N

Skip if not carry

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TC9318AFAG/AFBG

Machine Language (16 bit)

Mnemonic

Explanation of Function Explanation of Operation

IC

A

B

C

(6 bit)

(2 bit)

(4 bit)

Subtract immediate data

M ← (M) − I

SI

M, I

001000

001001

D

I

R

C

from memory

Subtract immediate data

from memory, then skip if

borrow

M ← (M) − I

SIS

*

D

Skip if borrow

Subtract immediate data

from memory, then skip if

not borrow

M ← (M) − I

SIN

SIB

M, I

001010

001011

D

I

R

C

Skip if not borrow

Subtract immediate data

from memory with borrow

M ← (M) − I − b

R

C

Subtract immediate data

from memory with

borrow, then skip if

borrow

M ← (M) − I − b

SIBS

SIBN

M, I

*

001100

001101

D

I

R

C

Skip if borrow

Subtract immediate data

from memory with

borrow, then skip if not

borrow

M ← (M) − I − b

R

C

Skip if not borrow

Subtract memory from

general register

SU

r, M

r ← (r) − (M)

011000

011001

D

R

C

N

Subtract memory from

general register, then

skip if borrow

r ← (r) − (M)

SUS

*

R

C

N

Skip if borrow

Subtract memory from

general register, then

skip if not borrow

r ← (r) − (M)

SUN

SB

r, M

011010

011011

D

R

C

N

Skip if not borrow

Subtract memory from

general register with

borrow

r ← (r) − (M) − b

D

R

Subtract memory from

general register with

borrow, then skip if

borrow

r ← (r) − (M) − b

SBS

SBN

r, M

*

011100

011101

D

R

C

N

Skip if borrow

Subtract memory from

general register with

borrow, then skip if not

borrow

r ← (r) − (M) − b

R

C

Skip if not borrow

Skip if memory is less

than immediate data

SLTI

M, I

*

Skip if (M) < I

110000

110001

D

I

R

C

Skip if memory is greater

than or equal to

immediate data

>

SGEI

Skip if (M)

I

=

R

C

Skip if memory is equal to

immediate data

SEQI

SNEI

SEQ

SNE

M, I

r, M

*

Skip if (M) = I

Skip if (M) ≠ I

Skip if (r) = (M)

Skip if (r) ≠ (M)

110010

110011

100010

100011

D

R

D

R

D

R

D

R

D

C

D

C

D

C

D

C

I

Skip if memory is not

equal to immediate data

Skip if general register is

equal to memory

R

N

Skip if general register is

not equal to memory

R

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Machine Language (16 bit)

Mnemonic

Explanation of Function Explanation of Operation

IC

A

B

C

(6 bit)

(2 bit)

(4 bit)

Load memory to general

r ← (M)

LD

ST

r, M

M, r

100100

100101

011111

001111

D

R

C

N

register

Store general register to

M ← (r)

D

R

memory

Move memory to memory

in the same row

MVSR

MVIM

M , M

1

(D , D ) ← (D , D

)

D

C1

D

C2

2

R

C1

R

C2

Move immediate data to

memory

M, I

r, M

M ← I

D

C

I

Move memory to

destination memory

referring to G-register

and general register

MVGD

MVGS

[(G), (r)] ← (M)

M ← [(G), (r)]

100110

100111

D

C

R

N

R

Move source memory

referring to G-register

and general register to

memory

M, r

D

C

R

N

R

Input IN1 port data to

memory

IN1

M, C

C, M

M, C

C, M

r, M

M ← [IN1]

111000

111011

111001

111100

010110

010111

000110

000111

D

C

R

C

R

C

N

Output contents of

memory to OUT1 port

OUT1

IN2

[OUT1] ← (M)

C

Input IN2 port data to

memory

M ← [IN2]

C

Output contents of

memory to OUT2 port

OUT2

ORR

ANDR

ORIM

ANIM

[OUT2] ← (M)

C

Logical OR of general

register and memory

r ← (r) ∨ (M)

r ← (r) ∧ (M)

M ← (M) ∨ I

M ← (M) ∧ I

Logical AND of general

register and memory

r, M

Logical OR of memory

and immediate data

M, I

I

Logical AND of memory

and immediate data

M, I

I

Logical exclusive OR of

memory and immediate

data

XORIM

XORR

M, I

r, M

M ← (M) ⊕ I

r ← (r) ⊕ (M)

001110

011110

D

R

C

Logical exclusive OR of

general register and

memory

D

R

N

Test general register bits

by memory bits, then skip

if all bits specified are

true

TMTR

TMFR

r, M

*

Skip if r [N (M)] = all “1”

Skip if r [N (M)] = all “0”

100000

100001

D

R

C

N

Test general register bits

by memory bits, then skip

if all bits specified are

false

R

C

N

Test memory bits, then

skip if all bits specified

are true

TMT

M, N

*

Skip if M (N) = all “1"

Skip if M (N) = all “0”

Skip if M (N) = not all “1"

Skip if M (N) = not all “0”

110101

110111

110100

110110

D

R

D

R

D

R

D

R

D

C

D

C

D

C

D

C

N

Test memory bits, then

skip if all bits specified

are false

TMF

N

Test memory bits, then

not skip if all bits

specified are true

TMTN

TMFN

Test memory bits, then

not skip if all bits

specified are false

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Machine Language (16 bit)

Mnemonic

Explanation of Function Explanation of Operation

IC

A

B

C

(6 bit)

(2 bit)

(4 bit)

STACK ← (PC) + 1 and

CALL ADDR

RN

Call subroutine

1010

ADDR (12 bit)

1

PC ← ADDR

1

Return to main routine

PC ← (STACK)

111111

00

01

⎯

Return to main routine

and skip unconditionally

RNS

*

PC ← (STACK) and skip

Jump to the address

specified

JUMP ADDR

PC ← ADDR

1011

ADDR (12 bit)

1

Load program memory in DATA ← [ADDR + (r)]

2

P

DAL ADDR , r

2

111110

R

N

page 0 to DATA register in page 0

At P = “0” H, the condition

is CPU waiting (soft wait

mode)

WAIT P

Wait at condition P

111111

10

0000

P

At P = “1” H, except for

clock generator, all

function is waiting (hard

wait mode)

Stop clock generator at

Clock generator stop

CKSTP

NOOP

111111

10

11

1000

⎯

MODE condition

No operation

⎯

Note 9: Among 10 bits of the program memory address assigned by DAL instruction, the lower rank of 4 bits

become indirect addressing based on the content of general register.

DAL instruction executing time is 80 µs (2 machine cycles).

Note 10: MVGS instruction executing time is 80 µs (2 machine cycles).

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I/O Map

All ports in the device are expressed by matrix of four input and output instruction (OUT1~2 instructions,

IN1~2 instructions) and 4 bits of code No. C. Assignment of these ports is indicated previously as I/O map. In

the I/O map, port names treated in the execution of each input and output instruction are assigned horizontally,

while code No. of port are assigned vertically. G-register and data register are also treated as port.

The OUT1~2 instructions are assigned to output port, and IN1~2 instructions are assigned to input port.

Note 11: The port indicated with oblique line on I/O map is a port not existing in the device. In the execution of output

instruction, when data is output to the non-existing output port, no effect is given to the content of other port

or data memory. When non-existing input port is designated during the execution of input instruction, the

content read into the data memory becomes “1”.

Note 12: Among the output ports on I/O map, * marked port is unused port. The data output here becomes “don’t

care”.

Note 13: Regarding the content of port expressed in 4 bits, Y1 corresponds to the least significant of the data of data

memory, and Y8 to the most significant bit.

Each port assigned by four input and output instruction and code No. C is coded as follows:

(example)

The G-register is set by OUT1 instruction wite code “F”.

Therefore, the notation is “φL1F”.

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Connecting Crystal Oscillator

The following diagram shows the connection of the 75 kHz crystal oscillator to the device’s crystal oscillator

pins (X , X ).

IN OUT

The oscillation signal is supplied to the clock generator, reference frequency divider, and other sub-systems to

generate the various CPU timing signals, reference frequency, and other signals. The power supply for the

crystal oscillator circuit is the voltage (V

= 1.4 V typ.) supplied by the built-in constant voltage circuit. This

XT

stabilizes the crystal oscillation and reduces the current consumption.

Note 14: Use a crystal oscillator with a low CI value and with good startup characteristics.

System Reset

The system is reset when a low level is applied to the RESET pin, or when the voltage supplied to the V

DD

pin goes from 0 V to 1.8 V or more (a power on reset). Following a system reset, the program starts from address

0 after a standby period of 100 ms.

As the power on reset function is typically used, fix the RESET pin to the high level.

Note 15: During a system reset and during the standby period following the reset, the LCD common and segment

outputs are fixed at the low level.

Note 16: After a system reset, the internal ports shown in the following table are fixed at the specified levels. The

states of the other ports after a reset are undefined. Therefore, initialize the ports in the program when

necessary.

Fixed Internal Ports

Ports Set to “0”

Ports Set to “1”

REFERENCE PORT (φL15)

MANUAL bit (φL17)

IO, POL, UNLOCK bit (φL18)

DO1 CONTROL PORT (φL19)

BUZR ON bit (φL1E)

MUTE bit (φL18)

IF/IN bit (φL16)

DISP OFF bit (φL2FF)

TEST PORT (φL1A, φL1D)

CKSTP MODE bit (φL1E)

AD CONTROL PORT (φL20, φL21)

TIMER PORT (φK1A)

KEY RETURN SELECT bit (φL2FF)

IO-1~IO-3 IO CONTROL PORT (φL25~φL27)

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Backup Modes

To enter the three backup modes, execute the CKSTP or WAIT instruction.

1. Clock Stop Mode

Clock stop mode halts the system and maintains the internal state of the system immediately prior to

halting. During a halt, the system is maintained with low current consumption (10 µA or below, at V

=

DD

3.0 V). In clock stop mode, the crystal oscillator halts and the output ports and LCD display output pins are

all automatically set to the low level or the off state. The supply voltage can be reduced to 1.0 V.

When the CKSTP instruction is executed, execution halts at the address of the CKSTP instruction.

Therefore, execution starts again from the next instruction when clock stop mode is released (after a

standby period of around 100 ms).

(1) Setting clock stop mode

Clock stop mode can be set to one of two modes. The CKSTP bit determines which of the two modes

is set. Use the OUT2 instruction with the operand [C = 7H] to access this bit.

N

1)

2)

MODE-0

In mode 0, executing the CKSTP instruction when the HOLD pin is low enters clock stop

mode. Executing the CKSTP instruction when the HOLD pin is high is equivalent to executing

a NOOP instruction.

MODE-1

In mode 1, executing the CKSTP instruction enters clock stop mode regardless of the level of

the HOLD pin.

Note 17: The PLL turns off during execution of the CKSTP instruction.

(2) Releasing clock stop mode

1)

MODE-0

In mode 0, clock stop mode is released when the HOLD pin goes to high, or by a change in

the input state of any I/O port 1 pin (P1-0~P1-3) set as an input port.

2)

MODE-1

In mode 1, clock stop mode is released by a change in the input state of the HOLD pin or in

the input state of any I/O port 1 pin (P1-0~P1-3) set as an input port.

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(3) Clock stop mode timing

1) MODE-0

(executing the CKSTP instruction while the HOLD pin input is low sets the device to clock

stop mode.)

2)

MODE-1

(executing the CKSTP instruction always sets the device to clock stop mode.)

(4) Circuit example (MODE-0)

Example of Backup Circuit Using Battery

Example of Backup Circuit Using

Capacitor

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2. Wait Mode

Wait mode halts the system and maintains, with reduced current consumption, the internal state of the

system immediately prior to halting. Two wait modes are available: “soft wait” and “hard wait”. When the

WAIT instruction is executed, execution halts at the address of the WAIT instruction. Therefore, when wait

mode is released, execution starts again from the next instruction without delaying for the standby time.

(1) Soft wait mode

Executing the WAIT instruction with the operand [P = 0H] stops only the CPU inside the device. In

this mode, the crystal oscillator, display circuit, and other circuitry continue to operate normally.

Using soft wait mode in the program for clock functions reduces the current consumed during clock

operation.

Note 18: The current consumption depends on the program.

(2) Hard wait mode

Executing the WAIT instruction with the operand [P = 1H] stops all operation other than the

crystal oscillator. This reduces current consumption still further than soft wait mode. In this state,

the CPU and display circuits are halted, and the LCD display output pins are all automatically fixed

at the low level. (15 µA typ. at V

= 3 V)

DD

(3) Setting wait mode

Executing the WAIT instruction always sets wait mode.

Note 19: In hard wait mode, the PLL turns off, while in soft wait mode, the PLL does not turn off.

Accordingly, before setting a soft wait, turn the PLL off by software.

(4) Wait mode release conditions

Wait mode is released by the following conditions.

1)

2)

At a change in the input state of the HOLD pin

When a high level is input to a key input pin (K0~K3)

(Note 20: depends on the key input mode)

3)

4)

When the 2 Hz timer flip-flop is set to “1”. (in soft wait mode only)

At a change in the input state of an I/O-1 port (P1-0~P1-3) set as an input port

3.

Input Port

HOLD

The HOLD pin can be used as an input port. Executing the IN1 instruction with the operand [C

BH] reads the data input from this bit to data memory.

=

N

When setting clock stop mode, always access this port prior to executing the CKSTP instruction.

Note that if the CKSTP instruction is executed without first accessing this port, the device may not enter

clock stop mode.

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Programmable Counter

The programmable counter block consists of a 2-modulus prescaler, 4 bit and 13 bit programmable counters,

and the ports used to control the block.

The programmable counters can be turned on and off by the contents of the reference ports.

1. Programmable Counter Control Ports

These ports control the divisor, division method, and the IF correction (IF offset) for the FM band.

Access the division method and the IF offset using the OUT1 instruction with the operand [C = 0H].

N

Access the divisor settings using the OUT1 instruction with the operands [C = 1H~5H]. Set the divisor

N

by writing to bits P0~P16. When the programmable counter data (P16) is set, all the data from P0 to P16

are updated. Therefore, always access P16 to set the data, even when changing only a portion of the data.

And the reference frequency is set at the same time.

2. Setting Division Method

The HF and FM bits select the pulse swallow or direct division method.

As the following table shows, there are four methods. Select the appropriate method in accordance with

the frequency band used.

Operating

Frequency

Range

Example of

Reception Band

Divisior

(Note 20)

Mode HF FM

Division Method

Input Pin

LF

HF

FM

0

1

0

1

Direct division method

(1/15 or 1/16)

MW/LW

SW

0.5~12 MHz

1.0~45 MHz

40~130 MHz

AM

IN

n

Pulse swallow method

FM

1/2 × (1/15 or 1/16)

VHF

1

VHF

50~230 MHz

2n

Pulse swallow method

Note 21: n indicates the programmed divisor.

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3. IF Correction Function for FM Band

When the pulse swallow method is selected, the ∆IF ± 1 ports allow the actual divisor to be varied by ±1

without changing the programmed divisor. This can be used for IF offset in FM.

When the direct division method is selected, the IF offset function does not operate.

∆IF + 1

∆IF − 1

Divisor (at FM )

H

Divisor (at FM , HF)

L

0

1

0

1

0

1

2･n

n

2･(n − 1)

2･(n + 1)

Prohibited

n − 1

n + 1

Prohibited

4. Setting Divisor

Set the divisor of the programmable counter as a binary value in bits P0~P16.

•

Pulse swallow method (17 bits)

•

Direct division method (13 bits)

Note 22: In case of direct dividing mode, Pφ~P3 (φL11) data be comes unrelated and P4 port becomes LSB.

Note 23: In VHF mode, the divisor is double the programmed divisor.

5. Programmable Counter Circuit Structure

•

Pulse swallow method circuit structure

The programmable counter circuit is made up of a 1/15 or 1/16 2-modulus prescaler, a 4 bit swallow

counter, and a 13 bit binary programmable counter. In FM mode, a 1/2 divider is inserted before the

H

prescaler.

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TC9318AFAG/AFBG

•

Direct division method circuit structure

This circuit bypasses the prescaler and uses the 13 bit programmable counter.

Note 24: The FM and AM pins incorporate amps. Connecting a capacitor permits low-amplitude

IN IN

operation. The input pins not selected by the division method are pulled down. In PLL off mode (set

by the reference port), the inputs are also pulled down.

Reference Frequency Divider

The reference frequency divider divides the frequency of the external 75 kHz crystal oscillator to generate

seven PLL reference frequency signals: 1 kHz, 3 kHz, 3.125 kHz, 5 kHz, 6.25 kHz, 12.5 kHz, and 25 kHz. The

frequency signal is selected by the reference port data.

The selected signal is supplied as the reference frequency for the phase comparator, which is described next.

The PLL is turned on or off by the reference port setting.

1. Reference Port

The reference port is an internal port used to select the reference frequency signal (from the seven

frequencies). Use the OUT1 instruction with the operand [C = 5H] (φL15) to access this port. When the

N

contents of the reference port are all “1”, the programmable counter, IF counter, and reference counter are

halted, and the PLL is turned off.

When the reference port are set, the frequency division data of the programmable counter are updated.

Therefore, in case of setting reference port, it is neccesary to set the frequency division data of the

programmable counter.

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Phase Comparator, Clock Detection Port

The phase comparator compares the reference frequency signal supplied by the reference frequency divider

with the divided signal output by the programmable counter, and outputs the phase difference. The output of

the phase comparator is used to control the VCO via the low pass filter so as to eliminate the frequency and

phase difference between the two signals.

Data are output from the phase comparator to the tristate buffered DO1 and DO2 pins in parallel. This

enables the optimal filter constants to be designed for both FM and AM bands.

Also, the DO1 pin can be set for general-purpose output by the DO1 control port. The DO1 pin can also be set

to high impedance. By using the DO1 and DO2 pins, PLL loop characteristics, such as the lockup time, can be

improved.

The lock detection port can be used to detect the PLL lock state.

1. DO2 Control Port, Unlock Detection Port

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TC9318AFAG/AFBG

The OTC, OT, and Hz control bits of the DO1 control port set the DO1 output pin as a general-purpose

output port, and control whether DO1 goes to high impedance instead of outputting the phase difference.

Set these bits to the required values by program.

When the phase is approximately 180°, the unlock flip-flop bit detects the phase difference between the

divided output of the programmable counter and the reference frequency. If the phase difference does not

match, that is, if the PLL is unlocked, the unlock flip-flop is set. Also, setting the unlock reset bit to “1”

resets the unlock flip-flop.

To detect the phase difference during the reference voltage period, reset the unlock flip-flop, then access

the unlock flip-flop after waiting for a time longer than the reference frequency period. An enable bit is

supplied for this purpose. After confirming that the unlock enable bit is set to “1”, access the unlock

flip-flop.

Setting the unlock reset bit to “1” resets the unlock enable bit.

Use the OUT1 and IN1 instructions with the operand [C = 7 or 9H] to control these ports, and to load

N

data.

Note 26: When the PLL is off, the DO output is set to high impedance. However, when DO1 is set as an output

port (OT output), the data are output from the port without change.

2. Phase Comparator, Unlock Port Timing

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3. Phase Comparator, Unlock Port Circuit Structure

When Setting Different Filter Constants

for Each Band

When Using the Same Low Pass Filter

for Both Bands

(set DO1 to high impedance to switch the

filter constant)

Note 27: The filter circuit shown in the above figure is an example for reference, and the actual circuit should be

investigated and designed conforming to the system band construction and the required

characteristics.

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IF Counter

This is a 20 bit general-purpose intermediate frequency (IF) counter used for such purposes as counting the

FM or AM intermediate frequency during auto-tuning or detecting the auto-stop signal.

The IF counter block consists of a 20 bit binary counter and a control port.

1. IF Counter Control Port, Data Port

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Note 28: When the PLL is off, the IF counter is disabled.

(1) IF counter auto mode (frequency measuring)

To use IF counter auto mode, use the IF/IN switching bit to set the IF pin to IF input.

Set the gate time based on the IF input frequency band. Set the MANUAL bit to “0” and the

STA/STP bit to “1” to start the IF counter.

As a result, the clock for the 20 bit binary counter is input from the IF pin for the specified gate

time. The IF counter counts the number of input pulses. To determine when the IF counter has

finished counting, check the BUSY bit. When the count equals or exceeds 2²⁰input pulses, the OVER

bit is set to “1”.

To measure the frequency input to the IF input pin, load the F0~F19 IF data when the BUSY and

OVER bits are both “0”.

(2) IF counter manual mode (frequency measuring)

Use manual mode to measure the frequency using the IF frequency by controlling the gate time

using an internal time base (eg, 10 Hz).

Perform the same IF counter input settings as for auto mode, and set the G0 and G1 bits to other

than “1”. Set the MANUAL bit to “1” and the STA/STP bit to “1” to start the count. Setting the

STA/STP bit to “0” terminates the count and loads the data in binary format.

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2. IF Counter Circuit Structure

The IF counter block consists of an input amp, a gate timer control circuit, and a 20 bit binary counter.

When the PLL is turned off, the IF counter is off. However, the block can still operate when set as a

timer/counter.

Note 29: The IF

IN1

pins incorporate amps. Connecting the pins via a capacitor permits low-amplitude operation.

Frequency Measuring Auto Mode

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LCD Driver

The LCD driver has a 1/3 duty and 1/2 bias drive (frame frequency is 83 Hz).

The common outputs are at three voltages: V , V /2V , and GND. The segment outputs are at two

LCD LCD EE

voltages: V

LCD

and GND.

The combination of three common outputs and 23 segment outputs enables the LCD driver to drive a

maximum of 69 segments.

LCD driver segment output pins S16~S23 are also used for the key return timing signals for loading key

matrix data.

The LCD driver incorporates a constant voltage circuit (V

(V

LCD

= 1.5 V) and voltage double boosting circuit

= 3.0 V) for the display. This maintains an even LCD contrast regardless of fluctuations in the supply

EE

voltage.

1. LCD Driver Port

*: Don’t care

Note 30: The segment data control whether or not the segments corresponding to the common and segment

outputs are lit.

Note 31: The DISP OFF bit is set to “1” at a system reset and at release of clock stop mode.

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The LCD driver control ports consist of a segment data selection port and segment data ports. Use the

OUT2 instruction with the operand [C = DH~FH] to access these ports.

N

Set the LCD driver segment data using the segment data ports (φL2E, φL2F). Set the segment data port

to “0” to turn the LCD display off and set “1” to turn the LCD display on. When FH is specified for the

segment data select port, the DISP OFF and KEY RETURN SELECT bits are selected as segment-2 data

(φL2FF). The DISP OFF bit can turn the whole LCD display off without setting segment data.

Setting this bit to “1” outputs the de-selected waveform from the common outputs and turns off the entire

LCD display. The segment contents are preserved. Setting the DISP OFF bit back to “0” displays the

previous LCD screen.

Segment data can be rewritten during DISP OFF. After a reset, and after CKSTP execution, the DISP

OFF bit is set to “1”.

The KEY RETURN SELECT bit allows an external power supply to be used. This is useful for changing

the LCD drive voltage.

The data are set according to the segment data select port (φL2D). Segment output pins S16~S23 are also

used for the key return timing signals for loading key matrix data. At the timing for loading the key matrix

data, the segment output is set to the GND level.

2. LCD Driver Circuit Structure

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3. LCD Driver Timing Chart

The following chart shows the timing for the COM1~COM3 output waveforms and the eight types of

segment output waveform.

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4. Example of Timing Chart for LCD Driver Output Data and Loading Key Data

The following chart shows the output waveform timing and key return data loading timing when the

common and segment outputs are allocated as shown.

The voltages output in the LCD driver waveform are V , GND, and an intermediate voltage halfway

LCD

between the two. Pins S16~S23 output the key return signals at the timing for switching between these

levels. During key return data loading, the segment outputs are at the V level for 80 µs.

LCD

Note 32: At CKSTP instruction execution or at a system reset, the common and segment pins go to the low

level.

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Key Input, Key Scan Timing

The following are the two basic methods of loading key data.

Select the appropriate method for the system.

1. Key Control Port, Key Scan Data

In case of setting data “1” to the key Return Select bit, the segment output is the output timing as shown

below.

In case of setting “0” to the bit, The key Return signal don’t outputted.

The key Return Select bit is the bit of setting the loading key method.

The data is loading by the digit timing of the key Return Signals from the key scan digit Port.

The key data by key scan is input to the key scan input data port. By accessing this port, the key data is

loading to the data memory.

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2. Key Scan Circuit Structure

The key input block of the key scan circuit consist of key input circuit, latch circuit for loading key data.

The key return timing output block consist of LCD segment driver, decoder and counter block.

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3. Key Matrix Structure

The key matrix can have one of the following two structures.

(1) Key data loading by software

When loading key data by software, use a key matrix with the above structure. For this method, set

to high the key timing output port data (φL28, φL29) for the key line to be loaded. Then to determine

which keys are pressed, load the key input port (φK26) data to memory. At this timing, set the other

key timing output ports to low. If the corresponding key is pressed, the key input port data are “1”; if

not pressed, “0”. This structure allows up to 24 (4 × (6)) keys to be used. The key data can be loaded at

high speed. Also, as the structure has a high resistance in the N channel FETs of pins T0~T5, there is

no need to use a diode to prevent reverse current flow caused by, for example, multiple keys being

pressed.

When loading key data by software, set to “0” to the key return select bit.

∼

Note 33: In case of structuring a diode jumper, the key input voltage is input/ow voltage of VF ( 0.6 V)

−

voltage of diode. It’s necessary the diode for diode jumper malfunction prevention to structure of

double push of a key.

The diode is unnecessary when there is no diode jumper necessity. Therefore, key input

thre-shold level is set up low.

In the mode structure, when executing a wait instruction (in WAIT mode), applying a high level to

a key input pin releases WAIT mode and restarts the CPU.

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TC9318AFAG/AFBG

(2) Key data loading by LCD segment output (hardware scan)

Note 34: A key matrix to 4 × 8 = 32 can be created.

Note 35: The same key line cannot contain both push keys and diode jumpers or alternate switches. Place

diode jumpers or alternate switches on the key return signal output side.

When loading key data by LCD segment output, use a key matrix with the above structure. In this

structure, it’s necessary for a diode to prevent reverse current flow and be careful the direction of

diode and diode jumper.

The V

and GND potential are outputted from a segment pin at the timing of changing LCD

LCD

output.

When loading key data, loading of segment signal becomes to the GND potential and key input pin

is pulled up to the V potential at changing LCD output.

DD

At this timing, if key is not pressed (or without diode jumper), key input pin is inputted V

potential; if key is pressed (or with diode jumper), key input pin is inputted one diode potential ( 0.6

DD

∼

−

V) from GND potential.

Therefore, key input threshold level is set up high.

Inputted key data is load key scan data port corresponding to segment output line of loading the

key. If a key is pressed, the key data is “1”; if not pressed, “0”.

The key data loading time for each one line is 2 ms. Referring the key scan action monitor, key scan

data (φK26) is loaded to the data memory.

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TC9318AFAG/AFBG

Key Return Timing Output Port (T0~T5)

T0~T5 are exclusive output port of 6 bits with N-channel load resostors. Normally, T0~T5 is used as output of

key return timing Signal for Key matrix.

This output port is made access by OUT2 instruction designated the operand part [C = 8 or 9] (φL28 or

N

φL29).

Note 36: During the clock stop mode (excusing CKSTP instruction), T0~T3 and OT0, OT1 output is fixed at “L” level

automatically, but the content of port is held on the previous data.

Buzzer Output (BUZR)

The buzzer output is used for such purposes as audible alarms or to issue confirmation beeps for key-presses

or tuning scan mode. The buzzer frequency can be set as desired. 50% duty waveform is output.

1. BUZR Data Port

The BUZR output can also be used as the P3-1 I/O port. To switch the P3-1 output to BUZR output, set

“1” to BUZR ON bit.

It is necessary to set of the BUZR data before setting the BUZRON bit to “1”.

Setting the data to BUZR data port (φL1C), the BUZR data is transferred to the BUZR data Latch, and

then changed BUZR frequency.

The BUZR output has a frequency of 75 kHz divided by 2 × n (n = B0~B7). The B0~B7 setting range and

<

frequency range is 2

n

255. This can be expressed as a formula as follows.

=

75 kHz

2 × 2

75 kHz

2 × 255

<

= 18.75 kHz

ƒ

= 147 Ηz

=

BUZR

=

Set B0~B7 to 1 or 0 to use the pin for OT1 output. The output states are as follows.

B7 B6 B5 B4 B3 B2 B1 B0

OT1 Output

0

1

Low level output

High level output

To set the above data, use the OUT1 instruction with the operand [C = BH~EH].

N

Note 37: After a system reset, the BUZR data port is reset to “0”.

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TC9318AFAG/AFBG

2. BUZR Circuit Structure

The buzzer circuit consists of an 8 bit programmable counter, a 1/2 counter, a buzzer latch, and a buzzer

data port.

3. BUZR Output Timing (BUZR ON bit is “1”)

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TC9318AFAG/AFBG

A/D Converter

The 2 channel/6 bit resolution A/D converter is used for such purposes as measuring field intensity and

battery voltage.

1. A/D Converter Control Port, Dare Port

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TC9318AFAG/AFBG

The A/D converter is a 6 bit resolution. The reference voltage of A/D conversion can select the external

voltage (DC-REF terminal), supply voltage and 1.5 V constant voltage (V ). The A/D conversion input is a

EE

multiplex method of 2-channel external input terminal (AD

, AD terminal) and also switchable to 1.5

IN1 IN2

V constant voltage (V ) as well.

EE

Normally field strength and volume level are measured by selecting external voltage or supply voltage as

reference voltage and A/D converting the external input level.

The A/D converter can also measure battery and supply voltages. It outputs a battery singal or performes

control for backup mode when battery voltage or supply voltage drop.

The A/D converter does A/D conversion whenever setting “1” to STA bit and the conversion will complete

after 7 machine cycles (280 µs). Whether A/D conversion is completed can be judged by referring to BUSY

bit. After A/D conversion is completed, the data will be loaded into data memory.

These controls are accessed when OUT2/IN2 instruction designated [C = 0H, 1H] in the operand is

N

executed.

2. A/D Converter Circuit Configuration

The A/D converter consists of: 6 bit D/A converter, comparator, A/D conversion latch, control circuit, A/D

data port and 1.5 V constant voltage circuit (supply for LCD driver).

The A/D converter will latch the data to A/D conversion data latch sequentially by means of the 6 bit

sequential comparison method.

Note 38: The DC-REF terminal is built-in an amplifier and is high impedance input.

Note 39: During A/D conversion, a proper data is not obtainable even if referring to the A/D conversion data.

Therefore, make sure to confirm that the conversion has finished by referring to the A/D operation

monitor.

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TC9318AFAG/AFBG

Input and Output Port

1. I/O Port P1-0~P1-3 (φKL22), P2-0~P2-3 (φKL23), P3-0~P3-1 (φKL24)

I/O port (P1-0~P1-3, P2-0~P2-3) are 4 bits and (P3-0~P3-1) are 2 bits CMOS type, and is capable of

making input and output setting with each bit.

Input and output setting of I/O port is made by the content of I/O control internal port.

Setting to input port can be made by setting “0” to the bit of I/O control port corresponding to I/O port,

while setting to output port can be made by setting “1” in the same.

In case of input port setting, the present data input I/O port is read into the data memory by the

execution of IN2 instruction designated the operand part [C = 2~4] (φK22, φK23, φK24).

N

In case of output port setting, output condition of I/O port is controlled execution of OUT2 instruction

designated the operand part [C = 2~4] (φL22, φL23, φL24).

N

I/O port 2~3 are also used for A/D converter and BUZR output.

After system reset, these ports are set to I/O port.

Note 40: I/O control port is made access by OUT2 instruction designated the operand part [C = 5~7].

N

Note 41: During the clock stop mode (executing CKSTP instruction), output condition of I/O port set at output

mode is all fixed at “L” level automatically, but each output latch holds on the data just before the clock

stop mode.

Note 42: At the time of changing input condition of P1-0~P1-3 port set at input mode, it cancels the execution of

WAIT and CKSTP instructions and makes the operation restart. In case of setting “1” to I/O bit of

MUTE control port, MUTE port is made to set to “1” compulsorily by the same condition.

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TC9318AFAG/AFBG

Register Port

The G-register (mentioned in the CPU description) and the data register are treated as internal ports.

1. G-Register (φL1F)

This register sets the row address (D = 4H~FH) in data memory for the MVGD and MVGS instructions.

R

To access this register, execute the OUT1 instruction with the operand [C = FH].

N

Note 43: The register value is only used when the MVGD or MVGS instructions are executed.

The register is ignored for other instructions.

Note 44: Setting data 0H~FH in the G register allows all the data memory row addresses to be specified

indirectly. (D = 0H~FH)

R

2. Data Register (φK1C~φK1F)

This is a 16 bit register to load the program memory data when the DAL instruction is executed. The

contents of the register are read to data memory in units of 4 bits by the IN1 instruction with the operands

[C = CH~FH].

N

This register can be used for such purposes as LCD segment decoding, radio band edge data, or for

coefficient data for binary-to-BCD conversion.

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TC9318AFAG/AFBG

Timer and CPU Stop Function

The timer has 100 Hz, 10 Hz, and 2 Hz flip-flop bits. These are used for counting operations, such as for a

clock or tuning scan mode.

The CPU stop function uses a voltage detector circuit to shut down the CPU when the V

the CPU falls below 1.5 V. This prevents CPU malfunction.

voltage applied to

DD

1. Timer Port, STOP Flip-Flop Bit

To access the timer port and the STOP flip-flop bit, execute the OUT1/IN1 instruction with the operand

[C = AH].

N

2. Timer Port Timing

The 2 Hz timer flip-flop is set by the 2 Hz (500 ms) signal, and reset by setting the RESET port 2 Hz

flip-flop to “1”. This bit can normally be used for the clock count.

The 2 Hz timer flip-flop is only reset by the 2 Hz flip-flop in the RESET port. Therefore, if the flip-flop is

not reset within 500 ms, the next count is missed and the correct time is not obtained.

t < 500 ms

The 10 Hz and 100 Hz timers are output to the 10 Hz and 100 Hz bits with a cycle of 100 ms and 10 ms,

respectively, and a pulse duty of 50%. Whenever the RESET port timer bit is set to “1”, counters below 1

kHz are reset.

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TC9318AFAG/AFBG

3. CPU Stop Function, STOP Flip-Flop Bit

The STOP flip-flop bit is set to “1” when the V

DD

voltage applied to the CPU falls below 1.5 V.

This prevents CPU malfunction by shutting down the CPU. When a voltage of 1.5 V or less is applied to

the V pin, the program counter stops and instruction execution ceases in the CPU.

DD

When a voltage higher than 1.5 V is again applied to the V

pin, the CPU starts up again. As the CPU

DD

was shut down, the clock and other timings are no longer valid. Use the STOP flip-flop to test whether the

CPU stop function operated. Perform initialization or clock correction if required.

The STOP flip-flop bit is reset to “0” whenever the RESET port 2 Hz flip-flop is set to “1”.

Note 45: After a system reset or execution of the CKSTP instruction, the timer port and the STOP flip-flop are

reset to “0”.

Note 46: If the V

DD

voltage falls below 1.5 V when clock-stop mode is set, the CKSTP instruction cannot be

executed. Be careful with the supply voltage timing, for example, when the radio is off.

Note 47: The key scan input data immediately after restarting the CPU are undefined.

Note 48: If the interal Test port from #0 to #3 bit (φL1D) is set to “1”, the CPU stop function is inhibited.

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2006-07-27

TC9318AFAG/AFBG

MUTE Output

This is a 1 bit CMOS-format output-only port for muting control.

1. MUTE Port

Access the MUTE port by executing the OUT1 instruction with the operand [C = 8H]. The MUTE

N

output is used for muting control. At such times as switching bands using the I/O port 1 input, the MUTE

bit can be set to “1”.

When using the I/O port 1 input to switch bands (using a slide switch, for example), this function

prevents linear circuit switching noise. This control is based on I/O bit values.

The POL bit sets the MUTE output logic.

The mute output can also control muting using the phase difference output. A pulse is output to indicate

when the PLL is not locked. By connecting an external low-pass filter to the MUTE output, the output can

be used as a MUTE signal. Use the UNLOCK bit to perform selection.

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2006-07-27

TC9318AFAG/AFBG

2. MUTE Output Structure and Timing

Note 50: When POL bit = 0

Note 51: When using the phase difference output by the phase comparator, externally connect a low-pass filter

to the MUTE output.

Test Ports

These are internal ports for testing the device’s functions. Access the ports by executing the OUT1 instruction

with the operand [C = AH] or [C = DH], or the OUT2 instruction with the operands [C = FFH]. The ports

N

are normally set to “0” by software.

If the data “1” is set to Test port bit from #0 to #3, the CPU stop function is inhibited and the data “0” is set,

the CPU function is operating.

In case of using supply voltage detection externally, set CPU stop function as inhibition.

Note 52: The ports are reset to “0” after a system reset.

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2006-07-27

TC9318AFAG/AFBG

Absolute Maximum Ratings (Ta = 25°C)

Characteristics

Supply voltage

Symbol

Rating

Unit

V

−0.3~4.0

V

DD

Input voltage

V

−0.3~V

+ 0.3

IN

DD

Power dissipation

Operating temperature

Storage temperature

P

100

mW

°C

D

T

opr

−10~60

T

stg

−55~125

Electrical Characteristics (unless otherwise noted, Ta = 25°C, V = 3.0 V)

DD

Test

Circuit

Characteristics

Symbol

Test Condition

Min

1.8

Typ.

3.0

Max

3.6

Unit

V

Range of operating supply voltage

V

⎯

*

DD

HD

Crystal ocillation stopped

Range of memory retention voltage

⎯

1.0

~

3.6

V

(CKSTP instruction executed) *

Under ordinary

operation and

PLL on

operation, no

output load

V

DD

= 3.0 V

⎯

7.0

12

FM = 230 MHz

IN

input

I

⎯

mA

DD1

Under ordinary

operation and

PLL on

operation, no

output load

V

= 3.0 V

⎯

6.0

10

DD

FM = 130 MHz

IN

input

Operating current

Under CPU

operation only

I

⎯

40

25

80

50

DD2

DD

(PLL off, display

turned on)

Soft Wait mode

µA

(crystal oscllator, display circuit

operating, CPU stopped, PLL

off)

I

DD3

DD4

Hard Wait mode

⎯

15

30

10

(crystal oscillator operating

only)

Crystal oscillation stopped

Memory retention current

I

0.1

HD

(CKSTP instruction executed)

Crystal oscillation frequency

Crystal oscillation startup time

f

⎯

*

⎯

75

⎯

kHz

s

XT

t

Crystal oscillation f = 75 kHz

⎯

1.0

ST

XT

Note 53: For conditions marked by an asterisk (*), guaranteed when V

= 1.8~3.6 V, Ta = −10~60°C.

DD

Voltage Doubler Circuit

Test

Circuit

Characteristics

Symbol

Test Condition

Min

1.3

⎯

Typ.

1.5

−5

Max

1.7

⎯

Unit

V

Voltage doubler reference voltage

V

⎯

GND reference (V

)

EE

Constant voltage temperature

characteristics

D

⎯

mV/°C

V

Voltage doubler boosting voltage

V

)

LCD

2.6

3.0

3.4

LCD

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2006-07-27

TC9318AFAG/AFBG

Operating Frequency Ranges for Programmable Counter and IF Counter

Test

Circuit

Characteristics

FM (VHF mode)

Symbol

Test Condition

Min

50

Typ.

~

Max

230

130

45

Unit

MHz

Sine wave input when

f

⎯

IN

VHF

V

= 0.2 V

*

IN

p-p

Sine wave input when

= 0.2 V

FM (FM mode)

f

40

~

IN

FM

V

IN

p-p

Sine wave input when

= 0.2 V

AM (HF mode)

f

1

~

IN

HL

V

IN

p-p

Sine wave input when

= 0.2 V

AM (LF mode)

f

0.5

0.35

0.2

~

12

IN

LF

V

IN

p-p

Sine wave input when

= 0.2 V

IF

IN

f

~

12

IF

V

*

IN

p-p

V

DD

0.8

−

Input amplitude

V

FM , AM , IF input

~

V

p-p

IN

Note 53: For conditions marked by an asterisk (*), guaranteed when V

= 1.8~3.6 V, Ta = −10~60°C.

DD

LCD Common Output/Segment Output (COM1~COM3, S ~S

)

23

1

Test

Circuit

Characteristics

Symbol

Test Condition

= 3 V, V = 2.7 V

Min

Typ.

Max

Unit

“H” level

I

⎯

V

−0.5

0.5

－1.0

1.0

⎯

OH1

LCD

OH

Output current

mA

V

“L” level

I

⎯

= 3 V, V = 0.3 V

OL

OL1

Output voltage 1/2 level

V

⎯

No load

1.3

1.5

1.7

BS

Input Port

HOLD

Test

Circuit

Characteristics

Symbol

Test Condition

Min

Typ.

Max

Unit

Input leak current

Input voltage

I

⎯

V

= 3.0 V, V = 0 V

⎯

2.4

0

⎯

~

±1.0

3.0

µA

LI

IH

IL

“H” level

“L” level

V

IH1

⎯

V

IL1

~

1.2

A/D Converter (A/D , A/D , DC-REF)

IN1

IN2

Test

Circuit

Characteristics

Symbol

Test Condition

Min

0

Typ.

~

Max

Unit

V

Analog input voltage range

V

⎯

AD , AD

V

DD

AD

IN1

IN2

V

×

DD

0.9

Analog reference voltage range

V

DC-REF, V

= 2.0~3.6 V

1.0

~

V

REF

DD

Resolution

⎯

6.0

―

bit

RES

Conversion total error

⎯

V

= 2.0~3.6 V

±1.0

±4.0

±1.0

LSB

DD

= 3.0 V, V = 0 V

IH

IL

Analog input leak

I

⎯

µA

LI

(AD , AD , DC-REF)

IN1

IN2

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2006-07-27

TC9318AFAG/AFBG

Key Input Port (K ~K )

0

3

Test

Circuit

Characteristics

Symbol

Test Condition

Min

75

Typ.

150

~

Max

300

3.0

Unit

N-ch/P-ch input resistance

R

⎯

kΩ

IN1

IH2

When input with pull-down

resistance

“H” level

Input voltage

V

1.8

V

When input with pull-down

resistance

“L” level

V

⎯

0

2.7

0

~

0.3

3.0

IL2

When input with pull-up

resistance

“H” level

Input voltage

V

IH3

V

When input with pull-up

resistance

“L” level

V

IL3

~

1.2

When input resistance off,

Input leak current

I

⎯

±1.0

µA

LI

V

= 3.0 V, V = 0 V

IH

IL

Timing Output Port (T0~T5)

Test

Circuit

Characteristics

Symbol

Test Condition

Min

−0.5

0.5

Typ.

−1.0

1.0

Max

⎯

Unit

“H” level

I

⎯

V

= 2.7 V

= 0.3 V,

OH1

OH

OL

Output current

“L” level

mA

I

⎯

OL1

Use LCD key-return mode

N-ch load resistance

R

ON

No used LCD key-return mode

75

150

300

kΩ

DO1/OT, DO2 Output; MUTE Output

Test

Circuit

Characteristics

Symbol

Test Condition

Min

Typ.

Max

Unit

mA

“H” level

I

⎯

V

= 2.7 V

= 0.3 V

−0.5

−1.0

⎯

OH1

OH

OL

Output current

“L” level

I

0.5

1.0

OL1

= 3.0 V, V

(DO1, DO2)

= 0 V

TLL

TLH

Output off leak current

I

⎯

±100

nA

TL

General-Purpose I/O Ports (P1-0~P3-1)

Test

Circuit

Characteristics

Symbol

Test Condition

= 2.7 V

Min

Typ.

Max

Unit

mA

“H” level

I

⎯

V

−0.5

0.5

⎯

−1.0

1.0

⎯

OH1

OH

OL

Output current

“L” level

I

= 0.3 V

OL1

Input leak current

Input voltage

I

= 3.0 V, V = 0 V

±1.0

3.0

0.6

µA

LI

IH

IL

“H” level

“L” level

V

IH4

⎯

2.4

0

~

V

IL4

~

IN,

Input Port

RESET

Test

Circuit

Characteristics

Symbol

Test Condition

Min

Typ.

Max

Unit

Input leak current

Input voltage

I

⎯

V

= 3.0 V, V = 0 V

⎯

2.4

0

⎯

~

±1.0

3.0

µA

LI

IH

IL

“H” level

“L” level

V

IH4

⎯

V

IL4

~

0.6

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2006-07-27

TC9318AFAG/AFBG

Others

Test

Circuit

Characteristics

Input pull-down resistance

Symbol

Test Condition

Min

Typ.

Max

Unit

R

⎯

(TEST)

(X -X

25

⎯

50

20

100

⎯

kΩ

MΩ

kΩ

IN2

X

IN

amp feedback resistance

)

fXT

IN OUT

X

OUT

output resistance

R

OUT

(X )

OUT

⎯

3

⎯

R

(FM , AM

)

150

500

300

1000

600

2000

fIN1

fIN2

IN

Input amp feedback resistance

kΩ

(IF

IN

)

Voltage used to detect supply voltage

drop

V

⎯

(V

)

1.35

1.55

1.75

V

STP

DD

Supply voltage drop detection

temperature characteristics

D

(V

⎯

−2

⎯

mV/°C

S

53

2006-07-27

TC9318AFAG/AFBG

Package Dimensions

Weight: 0.32 g (typ.)

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2006-07-27

TC9318AFAG/AFBG

Package Dimensions

Note: Pd-plated leads.

Weight: 0.45 g (typ.)

55

2006-07-27

TC9318AFAG/AFBG

RESTRICTIONS ON PRODUCT USE

060116EBA

• The information contained herein is subject to change without notice. 021023_D

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical

stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of

safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of

such TOSHIBA products could cause loss of human life, bodily injury or damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as

set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and

conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability

Handbook” etc. 021023_A

• The TOSHIBA products listed in this document are intended for usage in general electronics applications

(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,

etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires

extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or

bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or

spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,

medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this

document shall be made at the customer’s own risk. 021023_B

• The products described in this document shall not be used or embedded to any downstream products of which

manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q

• The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of

TOSHIBA or others. 021023_C

• The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E

About solderability, following conditions were confirmed

• Solderability

(1) Use of Sn-37Pb solder Bath

· solder bath temperature = 230°C

· dipping time = 5 seconds

· the number of times = once

· use of R-type flux

(2) Use of Sn-3.0Ag-0.5Cu solder Bath

· solder bath temperature = 245°C

· dipping time = 5 seconds

· the number of times = once

· use of R-type flux

56

2006-07-27


型号：	TC9318AFAG
厂家：	TOSHIBA
描述：	Single Chip DTS Microcontroller (DTS-21) 单芯片微控制器DTS （ DTS -21 ）微控制器
文件：	总56页 (文件大小：1176K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC9318AFAG [TOSHIBA]

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