TC9WMC2FU [TOSHIBA]
CMOS Digital Integrated Circuits Silicon Monolithic; CMOS数字集成电路硅单片
| 型号： | TC9WMC2FU |
| 厂家： | 
TOSHIBA |
| 描述： | CMOS Digital Integrated Circuits Silicon Monolithic |
| 文件： | 总16页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC9WMC1FK/FU,TC9WMC2FK/FU
TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic
TC9WMC1FK,TC9WMC1FU,TC9WMC2FK,TC9WMC2FU
TC9WMC1FK/FU: 1024-Bit (64 × 16-Bit) 3-Wire Serial EEPROM
TC9WMC2FK/FU: 2048-Bit (128 × 16-Bit) 3-Wire Serial EEPROM
The TC9WMC1 and TC9WMC2 are electrically
erasable/programmable three-wire serial nonvolatile memories
(EEPROMs).
TC9WMC1FK,TC9WMC2FK
Features
•
•
•
•
•
Three-wire serial interface (MICROWIRE)
Automatic address incrementing during read operation
Hardware and software data protection
US8
READY/BUSY signal during programming
Single power supply and low power consumption
TC9WMC1FU,TC9WMC2FU
Read: V
Write: V
= 1.8 to 3.6 V
= 2.3 to 3.6 V
CC
CC
•
Wide operating temperature range (−40 to 85°C)
SM8
Weight:
SSOP8-P-0.50A: 0.01 g (typ.)
SSOP8-P-0.65: 0.02 g (typ.)
Product Marking
Pin Assignment (top view)
US8
CS SK DI DO
Part number
8
7
6
5
C1 or C2
9WM
xx
US8
Pin 1 index
1
2
3
4
V
V
NC TESTGND
CC
SM8
Part number
NC TEST GND
CC
8
C1 or C2
LotNo.
7
6
5
WMxx
Pin 1 index
SM8
1
2
3
4
CS SK DI DO
1
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
Block Diagram
Test input
TEST
Chip select: CS
Clock input: SK
Timing
Control
circuit
Power supply
V
power supply
CC
generator
(booster circuit)
Command
register
Memory cell
Data input: DI
GND
Address
decoder
Input/output
circuit
Address
register
Data output: DO
Data register
Pin Function
Pin Name
Input/Output
Function
Chip select input
CS
Input
The device receives an instruction set when this pin is driven High.
This pin must be driven Low before execution of an instruction.
Serial clock input
SK
Input
Data is latched on the rising edge of SK. Data is transferred on the rising edge of SK.
This pin is valid when CS is driven High.
DI
Input
Serial data input (start bit, op code, address and data)
Serial data output
DO
Output
Test mode input (internal pull-down resistor)
Normally kept open. (Can be connected to GND.)
TEST
NC
Input
⎯
No connection (not connected internally)
1.8 to 3.6 V (for reading)
2.3 to 3.6 V (for writing)
V
CC
Power supply
GND
0 V (GND)
2
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
1. Instruction Set
Address
Start Bit
Instruction
Op Code
Data
TC9WMC1
A5 to A0
A5 to A0
A5 to A0
01xxxx
TC9WMC2
xA6 to A0
xA6 to A0
xA6 to A0
01xxxxxx
10xxxxxx
11xxxxxx
00xxxxxx
READ (Read)
1
1
1
1
1
1
1
10
01
11
00
00
00
00
D15 to D0 outputs
WRITE (Write)
D15 to D0 inputs
ERASE (Erase)
⎯
WRAL (Write All)
ERAL (Erase All)
EWEN (Program Enable)
EWDS (Program Disable)
D15 to D0 inputs
10xxxx
⎯
⎯
⎯
11xxxx
00xxxx
x: Don’t care
2. Functional Description
All instructions are executed when the DI input is received on the rising edge of SK after the CS input is
driven High. An instruction starts with a start bit followed by an op code, address and data bits. The
instruction transfer is completed when the CS input is driven Low. The CS must be driven Low during the
tCS cycle period between instruction transfers. When the CS is Low, the device is in standby mode. The SK
and DI inputs are disabled and the device does not respond to any instructions.
(1) Start bit
After the CS is driven High, a High on the DI input on the rising edge of SK indicates a start bit. A
start bit is not identified if the DI is driven Low even after the CS is driven High and the SK pulse is
applied.
Refer to (2) Dummy cycle in Section 3, Notes on Use.
(2) Read operation (READ)
The Read instruction reads data at specified addresses. After the CS is driven High, a start bit,
READ instruction and address are transferred to the device. After the least significant bit of address
(A0) is received, the DO output changes from high impedance to logic Low on the 9th rising edge of
SK. On the 10th rising edge of SK, the 16 bits of data appear on the DO output.
(2.1) Sequential read
After the 16 bits of data are driven onto the DO output, the device will automatically increment
the internal address counter and clock out data in the next memory location as long as the CS is
held High and the SK pulse is applied. In this way, data in all the memory locations can be read in
sequence. After the data in the last memory address is read, the address counter rolls over to the
first memory address.
CS
SK
DI
DI
1
2
3
4
5
6
7
8
9 10 11 12
23 24 25 26 27 28
39 40
42
1
1 0 A5 A4 A3 A2 A1 A0
DO
D15 D14 D13
D2 D1 D0 D15D14 D13
D2 D1 D0 D15
Hi-Z
Hi-Z
Figure 1. Read Timing Diagram (TC9WMC1)
3
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
CS
SK
DI
1
2
3
4
5
6
7
8
9 10 11 12 13 14
26 27 28 29
41 42 43 44
1
1 0 x A6 A5 A4 A3 A2 A1 A0
DO
D15D14D13
D1 D0 D15D14
D2 D1 D0 D15
Hi-Z
Hi-Z
Figure 2. Read Timing Diagram (TC9WMC2)
(3) Write operation (WRITE, ERASE, WRAL, ERAL)
The write operation has four modes: Write (WRITE), Erase (ERASE), Write All (WRAL) and Erase
All (ERAL). The write operation is triggered when the CS is driven Low after the SK pulse is applied.
The SK and DI inputs are disabled during the write operation, so no attempt should be made to
transfer instructions at this time.
If 16-bit or longer data is transferred to the device, the first 16 bits of data are valid and the
remaining bits are ignored. The DO output must be held High or in the high-impedance state when a
write instruction is received. A write operation is enabled in program enable mode.
(3.1) Verify operation
A write operation in all write modes is completed within 10 ms (write cycle tPW), but the typical
write cycle is shorter (5 ms). If the completion of the write operation is known, the internal write
cycle can be minimized. To accomplish this, a verify operation is performed.
(a) Operational description
When the CS is brought High following the initiation of a write operation (CS = Low), the
write operation status can be seen by monitoring the DO pin. This is called a verify operation
and the period during which the CS is held High following the initiation of a write operation is
called a verify operation cycle.
• DO pin = Low: A write operation is in progress. (busy)
• DO pin = High: A write operation has been completed. (ready)
After the write operation is completed, and if a start bit is not identified, the DO pin goes to
the high-impedance state if the CS is Low. If the CS is Low, the DO pin is driven High. When
the write operation is in progress (busy), the SK and DI inputs are disabled. Once the write
operation has been completed and a start bit is received, the verify operation is stopped.
(b) Two operation methods
There are two ways to perform a verify operation. One way is to monitor the DO output
successively with the CS driven High until the DO output status changes. The other way is to
monitor the DO output and, if no change is evident, the verify operation is stopped (CS = Low).
The verify operation is then restarted by the CS being pulled High. In this way, when the DO
output is not being monitored, the CPU is free for other operations, thus allowing more efficient
design of electronic systems.
4
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
(3.2) Write (WRITE)
The Write instruction contains the 16 bits of data to be written into the specified memory
location. After the CS is driven High, a start bit is transferred followed by the WRITE instruction,
address and 16 bits of data. After the least significant bit (D0) of data is received on the rising
edge of SK, a write operation is triggered by the CS being pulled Low. It is not necessary to set
every bit in the memory array to “1” before writing data.
CS
SK
DI
Verify
1
2
3
4
5
6
7
8
9 10
25
1
0
1 A5 A4 A3 A2 A1 A0 D15
D0
Busy
Ready
DO
Hi-Z
Hi-Z
t
PW
Figure 3. Write Timing Diagram (TC9WMC1)
CS
SK
DI
Verify
1
2
3
4
5
6
7
8
9 10 11 12
27
1
0
1
x A6 A5 A4 A3 A2 A1 A0 D15
D0
Busy
Ready
DO
Hi-Z
Hi-Z
t
PW
Figure 4. Write Timing Diagram (TC9WMC2)
5
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
(3.3) Erase (ERASE)
The Erase instruction writes all bits in the specified memory location to 1. After the CS is driven
High, a start bit is transferred followed by the ERASE instruction and address. In this mode, data
does not need to be transferred. After the least significant bit (A0) of the address is received on the
falling edge of SK, an erase operation is triggered by the CS being pulled Low.
CS
SK
DI
Verify
1
2 3 4 5 6 7 8 9
1
1 1 A5 A4 A3 A2 A1 A0
Busy
Ready
DO
Hi-Z
Hi-Z
t
PW
Figure 5. Erase Timing Diagram (TC9WMC1)
CS
SK
DI
Verify
1
2 3 4 5 6 7 8 9 10 11
1
1 1 x A6 A5 A4 A3 A2 A1 A0
Busy
Ready
DO
Hi-Z
Hi-Z
t
PW
Figure 6. Erase Timing Diagram (TC9WMC2)
6
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
(3.4) Write All (WRAL)
The Write All instruction writes all memory locations with data patterns specified in the
instruction. The data is 16 bits long. After the CS is driven High, a start bit is transferred followed
by the WRAL instruction, any addresses and 16 bits of data. After the least significant bit (D0) of
data is received on the falling edge of SK, a write operation is triggered by the CS being pulled
Low. It is not necessary to set every bit in the memory array to “1” before writing data.
CS
SK
DI
Verify
1
2
3
4
5
6
7
8
9 10
25
1
0
0
0
1
x
x
x
x
D15
D0
Busy
Ready
DO
Hi-Z
Hi-Z
t
PW
Figure 7. Write Timing Diagram (TC9WMC1)
CS
SK
DI
Verify
1
2
3
4
5
6
7
8
9 10 11 12
27
1
0
0
0
1
x
x
x
x
x
x
D15
D0
Busy
Ready
DO
Hi-Z
Hi-Z
t
PW
Figure 8. Write Timing Diagram (TC9WMC2)
7
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
(3.5) Erase All (ERASE)
The Erase All instruction writes every bit in the memory array to 1. After the CS is driven High,
a start bit is transferred followed by the ERAL instruction and any addresses. In this mode, data
does not need to be transferred. After the least significant bit (A0) of the address is received on the
falling edge of SK, an erase operation is triggered by the CS being pulled Low.
CS
SK
DI
Verify
1
2 3 4 5 6 7 8 9
1
0
0
1
0
x
x
x
x
Busy
Ready
DO
t
PW
Hi-Z
Hi-Z
Figure 9. Erase Timing Diagram (TC9WMC1)
CS
SK
DI
Verify
1
2 3 4 5 6 7 8 9 10 11
1
0
0
1
0
x
x
x
x
x
x
Ready
DO
Busy
t
PW
Hi-Z
Hi-Z
Figure 10. Erase Timing Diagram (TC9WMC2)
8
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
(3.6) Write Enable (EWEN)/Write Disable (EWDS)
The EWEN instruction enables a write operation. In program enable mode, a writing operation
is enabled.
The EWDS instruction disables a write operation. In program disable mode, a writing operation
is disabled.
After power on, the device is in EWDS mode. The EWEN instruction must be executed before
any write instructions can be carried out.
After the CS is driven High, a start bit is transferred followed by the EWEN/EWDS instruction
and any addresses. The mode is enabled on the rising edge of SK after the least significant bit (A0)
of the address is received.
CS
SK
DI
CS
1
2
3
4
5
6
7
8
9
1 2 3 4 5 6 7 8 9
SK
DI
1
0
0
1
1
x
x
x
x
1
0
0
0
0
x
x
x
x
Write enabled
Write disabled
Figure 11. Write Enable/Disable Timing Diagram (TC9WMC1)
CS
SK
DI
CS
1
2 3 4 5 6 7 8 9 10 11
1
2 3 4 5 6 7 8 9 10 11
SK
DI
1
0
0
0
0
x
x
x
x
x
x
1
0
0
1
1
x
x
x
x
x
x
Write enabled
Write disabled
Figure 12. Write Enable/Disable Timing Diagram (TC9WMC2)
9
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
3. Notes on Use
(1) Powering up the device
This device contains a power-on clear circuit, which initializes the internal circuit of the device
when the power is turned on. If initialization fails, the chip may malfunction. When powering up the
device, observe the following precautions to assure that the clear circuit will operate normally:
(a) Pull CS Low.
(b) The power rising time (t ) must be 10 ms or less.
R
(c) After turning off the power, wait at least 100 ms (t
device again.
) before attempting to power up the
OFF
(d) The supply voltage must rise from a voltage lower than 0.1 V.
(e) After turning on the power, wait at least 20 ms before attempting to send an instruction to the
device.
V
CC
V
CC
0.1 V max
0 V
t
t
R
OFF
20 ms
Figure 13
(2) Dummy cycle
When the DI input is driven Low, the SK clock cycles preceding a start bit are called “dummy
cycles”. The device executes dummy cycles when an instruction from the CPU is longer than that for
the device. For example, if the CPU’s instruction is 16 bits long, the TC9WMC1 executes seven
dummy cycles and the TC9WMC2 executes five dummy cycles. Thus, the two instructions take the
same number of clock cycles.
(3) Erroneous detection of a start bit
(a) If the DO output is High during the verify operation, a High on the DI input on the rising edge
of SK causes the device to detect erroneously the start of serial reception. To prevent this, the
DI input must be driven Low during the verify operation.
(b) When the DI and DO pins are configured as a 3-wire interface, data transfer from the CPU and
that from the device can collide with each other during a certain period of time and the device
cannot detect the start of serial reception correctly. To prevent this, a 10- to 100-KΩ resistor
must be inserted between the DI and DO pins, so that the DI input from the CPU takes priority.
(See Figure 14.)
TC9WMC1
CPU
TC9WMC2
Figure 14
DI
DO
SIO
(4) Verify operation
(a) The DI input must be driven Low during the verify operation.
(b) When the DO output is driven High, a High on the DI input on the rising edge of SK causes the
device to detect erroneously the start of serial reception and accepts an instruction. In this case,
the DO pin immediately goes to the high-impedance state.
(5) Instruction cancellation
During an instruction execution, the instruction can be cancelled by pulling the CS pin Low.
However, care must be taken for the timing of canceling a write operation as described below.
(a) The write operation can be cancelled when the CS is pulled Low on the rising edge of SK when
the 15th bit of data is received.
(b) The write operation cannot be cancelled when the CS is pulled Low on the rising edge of SK
after the 17th bit of data is received. In this case, the write instruction writes the 16 bits of data
into the specified memory location.
10
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
Absolute Maximum Ratings (Note) (GND = 0 V)
Characteristic
Power supply voltage
Symbol
Rating
−0.3 to 7.0
Unit
V
V
V
V
CC
Input voltage
V
−0.3 to V
+ 0.3
IN
CC
CC
Output voltage
V
−0.3 to V
+ 0.3
OUT
300 (25°C,SM8)
200 (25°C,US8)
−55 to 125
Power dissipation
P
mW
D
Storage temperature
Operating temperature
T
stg
°C
°C
T
opr
−40 to 85
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Operating Ranges (Note) (GND = 0 V, T
= −40 to 85°C)
opr
Characteristic
Symbol
Test Condition
Min
Max
Unit
Supply voltage (for reading)
Supply voltage (for writing)
V
V
⎯
⎯
1.8
2.3
3.6
3.6
V
V
CC
CC
0.7 ×
CC
2.7V ≤ V
1.8 V ≤ V
2.7V ≤ V
≤ 3.6 V
< 2.7 V
≤ 3.6 V
< 2.7 V
V
V
CC
CC
CC
CC
CC
V
High-level input voltage
V
V
IH
0.8 ×
V
CC
0
0.3 ×
V
CC
Low-level input voltage
Operating frequency
V
V
IL
0.2 ×
V
1.8 V ≤ V
0
CC
CC
2
2.7V ≤ V
1.8 V ≤ V
≤ 3.6 V
< 2.7 V
0
0
CC
fsk
MHz
0.5
CC
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Electrical Characteristics
DC Characteristics (V = 1.8 to 3.6 V, GND = 0 V, T
= −40 to 85°C)
CC
opr
1.8 ≤ V
Min
< 2.3 V
Max
±1
2.3 ≤ V
Min
< 2.7 V
Max
±1
2.7 ≤ V
Min
≤ 3.6 V
CC
CC
CC
Characteristic
Symbol
Test Condition
Unit
Max
Input current
I
⎯
⎯
⎯
±1
μA
μA
LI
Output leakage
current
I
⎯
⎯
±1
⎯
⎯
±1
⎯
±1
LO
I
I
= −400 μA
= −100 μA
= 2.1 mA
= 100 μA
⎯
⎯
⎯
⎯
⎯
⎯
⎯
OH
OH
High-level output
voltage
V
V
V
OH
V
− 0.2
V
− 0.2
V
− 0.2
CC
CC
CC
I
⎯
⎯
⎯
⎯
⎯
⎯
OL
OL
Low-level output
voltage
V
OL
I
⎯
0.2
⎯
0.2
⎯
0.2
Quiescent supply
current
I
I
I
⎯
2
⎯
2
⎯
2
μA
mA
mA
CC1
CC2
CC3
Supply current during
read
f
f
= 2 MHz
SK
SK
⎯
⎯
0.5
⎯
⎯
⎯
1.0
1.0
⎯
⎯
1.5
1.5
(Note)
Supply current during
program
= 2 MHz
Note: V
= 1.8 to 2.3 V @f = 0.5 MHz
SK
CC
11
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
AC Characteristics (V = 1.8 to 3.6 V, GND = 0 V, T
= −40 to 85°C)
CC
opr
1.8 ≤ V
Min
0
< 2.3 V
Max
0.5
⎯
2.3 ≤ V
< 2.7 V
Max
1.5
⎯
2.7 ≤ V
Min
0
≤ 3.6 V
Max
2
CC
CC
CC
Characteristic
Symbol
Unit
Min
0
SK clock frequency
SK clock pulse width
f
MHz
SK
t
2.0
2.0
0.5
1
0.5
0.5
0.3
0.4
0
0.25
0.25
0.2
⎯
SKH
μs
t
⎯
⎯
⎯
SKL
CS Low period
CS setup time
CS hold time
t
⎯
⎯
⎯
μs
μs
μs
μs
μs
CS
t
⎯
⎯
0.2
⎯
CSS
CSH
t
0
⎯
⎯
0
⎯
DI setup time
t
0.4
0.4
⎯
0.2
0.2
⎯
0.1
⎯
DS
DH
DI hold time
t
⎯
⎯
0.1
⎯
Propagation delay time
t
⎯
2.0
⎯
1.0
⎯
0.4
μs
PD
(Note)
Output disable time
Output enable time
t
t
0
0
1.0
1.0
0
0
0.5
0.5
0
0
0.5
0.5
μs
μs
HZ
SV
Note: C = 100 pF, R = 1 kΩ
L
L
2
E PROM Characteristics (GND = 0 V, 2.3 V ≤ V ≤ 3.6 V, T
= −40 to 85°C)
CC
opr
Characteristic
Symbol
Test Condition
Min
Max
Unit
3.0V ≤ V
2.3V ≤ V
≤ 3.6 V
< 3.0 V
⎯
⎯
10
12
⎯
⎯
CC
CC
Program time
t
ms
PW
5
Rewrite cycle
N
1 × 10
10
Times
Year
EW
Data retention time
t
RET
Capacitance Characteristics (Ta = 25°C)
Characteristic
Symbol
Test Condition
Typ.
Unit
V
(V)
CC
3.3
3.3
Input capacitance
Output capacitance
C
4
4
pF
pF
IN
C
O
12
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
AC Characteristics Timing Chart
t
CSS
t
CS
CS
SK
DI
t
t
t
CSH
SKH
SKL
t
t
t
t
DH
DS
DH
DS
t
t
PD
PD
DO
(Read)
t
t
t
HZ
SV
HZ
DO
(Verify)
Input/Output Circuits of Pins
Pin
Type
Input/Output Circuit
Remarks
CS
DI
Input
Hysteresis input
SK
Initial
High Z
DO
Output
13
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
Package Dimensions
Weight: 0.01 g (typ.)
14
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
Package Dimensions
Weight: 0.02 g (typ.)
15
2007-10-19
TC9WMC1FK/FU,TC9WMC2FK/FU
RESTRICTIONS ON PRODUCT USE
20070701-EN GENERAL
• The information contained herein is subject to change without notice.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc.
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his
document shall be made at the customer’s own risk.
• The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patents or other rights of
TOSHIBA or the third parties.
• Please contact your sales representative for product-by-product details in this document regarding RoHS
compatibility. Please use these products in this document in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses
occurring as a result of noncompliance with applicable laws and regulations.
16
2007-10-19
相关型号：
©2020 ICPDF网 联系我们和版权申明