THNCF256MAA_技术文档

Preliminary version

THNCFxxxMAA Series

Product Specifications

Dimensions：

Type I card：

Weight：

36.4mm(L) x 42.8mm (W) x 3.3mm (H)

14.2 g or 0.5 oz

Storage Capacities：

8,16, 32, 48, 64, 96, 128, 160, 192, 256, 320, 384 and up to 512 MB Mbytes (unformatted)

System Compatibility：

Please refer to the compatibility list.

Performance：

Data Transfer Rates: up to 4.1Mbyte/s in ATA PIO mode 4

To/from Flash memory: up to 12.5 Mbytes/s

To/from host:

Sustained write:

Sustained read:

Command to DREQ:

Idle to Read

up to 20Mbytes/s

up to 2.98Mbyte/s in ATA PIO mode 4

up to 5.62Mbyte/s in ATA PIO mode 4

<4ms

<1 µs

Idle to Write

<1 µs

SRAM data buffer

6 KBytes SRAM

Operating Voltage：

3.3V / 5V +/- 10%

Power consumption：

Read mode

30 mA (typ)

100uA (typ)

Write mode

Sleep mode

Environment conditions：

Operating temperature

Storage temperature

Relative humidity

0℃ to 60℃

-20℃ to 65℃

95%(Max)

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Preliminary version

THNCFxxxMAA Series

Electrical Specification

ABSOLUTE MAXIMUM RATINGS

SYMBOL

Vcc

RATING

VALUE

-0.3 to 7

-20 to 65

0 to 60

UNIT

V

Power Supply Voltage

Input Voltage

Vin

V

Tstg

Storage Temperature

Operating Temperature

℃

Topr

DC RECOMMENDED OPERATING CONDITIONS

SYMBOL

Vcc

PARAMETER

MIN

3.0

MAX

5.5

UNIT

V

Power Supply Voltage

High Level Input Voltage

Low Level Input Voltage

ViH

2.2

Vcc+0.3

0.8

V

ViL

-0.3 *

V

Note: - 0.8V (Pulse width <= 10nS)

DC CHARACTERISTICS (Ta = 0℃ to 65℃, Vcc = 3.15V to 5.5V)

SYMBOL

Icco

PARAMETER

MIN

TYP

26

MAX

50

UNIT

mA

uA

V

Operating Current

Iccs

Sleep Mode Current

75

200

VoH

High Level Output Voltage

Low Level Output Voltage

2.4

VoL

0.4

V

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Preliminary version

THNCFxxxMAA Series

Physical Specifications

1.60mm

( .063 in

±

.05

±

.002)

26

50

.99mm

±

.05

. 002)

(.039 in.

±

3.30mm

±

.10

25

1

( .130 in .004 )

±

1.01mm

±

0.7

.003)

1.01mm

±

.003)

0.7

2.44mm

(.096 in.

±

.07

( .039 in

±

( .039 in

±

. 003)

2.15mm

±

.07

(.085 in.

±

. 003)

TOP

2X 3.00mm

(2X .118 in.

±

.07

. 003)

0.76mm

±

.07

(0.30 in.

±

. 003)

41.66mm

42.80mm

(1.685 in.

±

.13(1.640 in.

±. 005)

±

.10)

4XR 0.5mm

(4XR.020 in.

±

.1

0.63mm

±

.07

±. 004)

±

. 004)

(.025 in.

±. 003)

Note: The optional notched configuration was shown in the CF Specification Rev.1.0. In

Specification Rev. 1.2. the notch was removed for ease of tooling. This optional

configuration can be used but it is not recommended.

Type I CompactFlash Storage Card and CF+ Card Dimensions

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Preliminary version

THNCFxxxMAA Series

Electrical Interface

Physical Description

The host is connected to the CompactFlash Storage Card or CF+ Card using a standard

50-pin connector. The connector in the host consists of two rows of 25 male contacts each

on 50 mil (1.27 mm) centers.

Pin Assignments and Pin Type

The signal/pin assignments are listed in Table 4. Low active signals have a “-“ prefix. Pin

types are Input, Output or Input/Output. Section 4.3 defines the DC characteristics for all

input and output type structures.

Electrical Description

The CompactFlash Storage Card functions in three basic modes: 1) PC Card ATA using I/O Mode, 2) PC

Card ATA using Memory Mode and 3) True IDE Mode, which is compatible with most disk drives.

CompactFlash Storage Cards are required to support all three modes. The CF Cards normally function in

the first and second modes, however they can optionally function in True IDE mode. The configuration of

the CompactFlash Card will be controlled using the standard PCMCIA configuration registers starting at

address 200h in the Attribute Memory space of the storage card.or for True IDE Mode, pin 9 being

grounded. The configuration of the CF Card will be controlled using configuration registers. The

configuration registers are starting at the address defined in the Configuration Tuple (CISTPL_CONFIG) in

the Attribute Memory space of the CF Card. Signals whose source is the host are designated as inputs

while signals that the CompactFlash Storage Card sources are outputs. The CompactFlash Storage Card

logic levels conform to those specified in the PCMCIA Release 2.1 specification. Each signal has three

possible operating modes:

1) PC Card Memory mode

2) PC Card I/O mode

3) True IDE mode

True IDE mode is required for CompactFlash Storage cards. All outputs from the card are

totem pole except the data bus signals that are bi-directional tri-state.

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Preliminary version

THNCFxxxMAA Series

Pin Assignments and Pin Type

PC Card Memory Mode

PC Card I/O Mode

True IDE Mode

Signal

In,Out

Signal

In,Out

Type

In,Out Type

Num.

Name

Type

Num.

Name

Type

Num.

Name

Type

1

GND

D03

Ground

I1Z, OZ3

I3U

1

GND

D03

Ground

I1Z, OZ3

I3U

1

GND

D03

Ground

I1Z, OZ3

I3Z

2

I/O

2

I/O

2

I/O

3

D04

I/O

3

D04

I/O

3

D04

I/O

4

D05

I/O

4

D05

I/O

4

D05

I/O

5

D06

I/O

5

D06

I/O

5

D06

I/O

6

D07

I/O

6

D07

I/O

6

D07

I/O

7

-CE1

A10

I

7

-CE1

A10

I

7

-CS0

A10²

-ATA SEL

A09²

A08²

A07²

VCC

A06²

A05²

A04²

A03²

A02

I

8

I1Z

8

I1Z

8

I

I1Z

9

-OE

I3U

9

-OE

I3U

9

I

I3U

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

A09

I1Z

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

A09

I1Z

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

I

I1Z

A08

I1Z

A08

I1Z

I

I1Z

A07

I1Z

A07

I1Z

I

I1Z

VCC

A06

Power

I1Z

VCC

A06

Power

I1Z

Power

I1Z

I

A05

I1Z

A05

I1Z

I

I1Z

A04

I

I1Z

A04

I

I1Z

I

I1Z

A03

I

I1Z

A03

I

I1Z

I

I1Z

A02

I

I1Z

A02

I

I1Z

I

I1Z

A01

I

I1Z

A01

I

I1Z

A01

I

I1Z

A00

I

I1Z

A00

I

I1Z

A00

I

I1Z

D00

I/O

O

I/O

I

I1Z,OZ3

OT3

D00

I/O

O

I/O

I

I1Z,OZ3

OT3

D00

I/O

O

I/O

I

I1Z,OZ3

ON3

D01

D02

WP

-IOIS16

-CD2

-CD1

D11¹

D12¹

D13¹

D14¹

D15¹

-CE2¹

-VS1

-IORD

-IOWR

-WE

-IOCS16

-CD2

-CD1

D11¹

D12¹

D13¹

D14¹

D15¹

-CS¹

-VS1

-IORD

-IOWR

-WE³

-CD2

-CD1

D11¹

D12¹

D13¹

D14¹

D15¹

-CE2¹

-VS1

-IORD

-IOWR

-WE

Ground

I1Z,OZ3

I3U

Ground

I3U

Ground

I1Z,OZ3

I3U

Ground

I3U

Ground

I1Z,OZ3

I1Z

Ground

I3Z

I3U

O

I

O

I

O

I

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Preliminary version

THNCFxxxMAA Series

PC Card Memory Mode

PC Card I/O Mode

True IDE Mode

Signal

In,Out

Type

Signal

In,Out

Type

Signal

In,Out

Type

Num.

Name

Type

Num.

Name

Type

Num.

Name

Type

37

38

39

40

41

42

43

44

45

46

47

48

49

50

RDY/BSY

VCC

-CSEL

-VS2

O

OT1

POWER

I2Z

37

38

39

40

41

42

43

44

45

46

47

48

49

50

IREQ

VCC

-CSEL

-VS2

O

OT1

Power

I2Z

37

38

39

40

41

42

43

44

45

46

47

48

49

50

INTRQ

VCC

-CSEL

-VS2

O

OZ1

Power

I2U

I

O

OPEN

I2Z

O

OPEN

I2Z

O

OPEN

I2Z

RESET

-WAIT

-INPACK

-REG

BVD2

BVD1

D08¹

I

RESET

-WAIT

-INPACK

-REG

I

-RESET

IORDY

-INPACK

-REG³

-DASP

-PDIAG

D08¹

I

O

OT1

O

OT1

O

ON1

O

OT1

O

OT1

O

OZ1

I

I3U

I

I3U

I

I3U

I/O

I1U, OT1

I1Z, OZ3

Ground

-SPKR

-STSCHG

D08¹

I/O

I1U,OT1

I1Z,OZ3

Ground

I/O

I1U,ON1

I1Z,OZ3

Ground

D09¹

D10¹

GND

Note: 1. These signals are required only for 16bit access and not required when installed in 8-bit

systems. Devices should allow for 3-state signals not to consume current.

2. Should be grounded by the host.

3. Should be tied to VCC by the host.

4. Optional for CF+Cards, required for CompactFlash Storage Cards.

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Preliminary version

THNCFxxxMAA Series

Signal Description

Signal Name

Dir.

I

Description

These address lines along with the –REG signal are used to select

A10 - A0

8,10,11,12

(PC Card Memory Mode)

14,15,16,17, the following: The I/O port address registers within the CompactFlash

18,19,20

Storage Card or CF+Card, the memory mapped port address

registers within the CompactFlash Storage Card or CF+Card, a byte

in the card’s information structure and its configuration control and

status registers.

A10 – A0

(PC Card I/O Mode)

This signal is the same as the PC Card Memory Mode signal.

A2 – A0

I

18,19,20

46

In True IDE Mode only A[2:0] are used to select the one of eight

registers in the Task File, the remaining address lines should be

grounded by the host.

(True IDE Mode)

BVD1

I/O

This signal is asserted high as BVD1 is not supported.

(PC Card Memory Mode)

-STSCHG

This signal is asserted low to alert the host to changes in the

RDY/-BSY and Write Protect states, while the I/O interface is

configured. Its use is controlled by the Card Config and Status

Register.

(PC Card I/O Mode)

Status Changed

-PDIAG

(True IDE Mode)

In the True IDE Mode, this input/output is the Pass Diagnostic signal

in the Master/Slave handshake protocol.

BVD2

I/O

45

This signal is asserted high as BVD2 is not supported.

(PC Card Memory Mode)

-SPKR

This line is the Binary Audio output from the card. If the Card does

not support the Binary Audio function, this line should be held

negated.

(PC Card I/O Mode)

-DASP

In the True IDE Mode, this input/output is the Disk Active/Slave

Present signal in the Master/Slave handshake protocol.

(True IDE Mode)

-CD1, -CD2

O

26,25

These Card Detect pins are connected to ground on the

CompactFlash Storage Card or CF+Card. They are used by the

host to determine that the CompactFlash Storage Card or CF+Card is

fully inserted into its socket.

(PC Card Memory Mode)

-CD1, -CD2

This signal is the same for all modes.

(PC Card I/O Mode)

-CD1, -CD2

This signal is the same for all modes.

(True IDE Mode)

-CE1, -CE2

I

7,32

These input signals are used both to select the card and to indicate to

the card whether a byte or a word operation is being performed.

–CE2 always accesses the odd byte of the word, -CE1accesses the

even byte or the Odd byte of the word depending on A0 and –CE2.

A multiplexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to

access all data on D0-D7. See Tables 4-11, 4-12, 4-15, 4-16 and

4-17.

(PC Card Memory Mode)

Card Enable

-CE1, -CE2

This signal is the same as the PC Card Memory Mode signal.

(PC Card I/O Mode)

Card Enable

In the True IDE Mode CS0 is the chip select for the task file registers

while CS2 is used to select the Alternate Status Register and the

Device Control Register.

-CS0, -CS1

(True IDE Mode)

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Preliminary version

THNCFxxxMAA Series

Signal Name

Dir.

I

39

Description

-CSEL

This signal is not used for this mode.

(PC Card Memory Mode)

-CSEL

This signal is not used for this mode.

(PC Card I/O Mode)

-CSEL

This internally pulled up signal is used to configure this device as a

Master or a Slave when configured in the True IDE Mode.

When this pin is grounded, this device is configured as a Master.

When the pin is open, this device is configured as a Slave.

(True IDE Mode)

D15 – D00

I/O

31,30,29,28, These lines carry the Data, Commands and Status information between

27,49,48,47, the host and the controller. D00 is the LSB of the Even Byte of the

6,5,4,3,2,23, Word. D08 is the LSB of the Odd Byte of the Word.

22,21

(PC Card Memory Mode)

This signal is the same as the PC Card Memory Mode signal.

D15 – D00

(PC Card I/O Mode)

In True IDE Mode, all Task File operations occur in byte mode on the

low order bus D00–D07 while all data transfers are 16bit using

D00–D15.

D15 – D00

(True IDE Mode)

GND

-

1, 50

Ground

(PC Card Memory Mode)

GND

This signal is the same for all modes.

This signal is not used in this mode.

(PC Card I/O Mode)

GND

(True IDE Mode)

-INPACK

O

43

(PC Card Memory Mode)

-INPACK

The input Acknowledge signal is asserted by the CompactFlash Storage

Card or CF+ Card when the card is selected and responding to an I/O

read cycle at the address that is on the address bus. This signal is

used by the host to control the enable of any input data buffers between

the CompactFlash Storage Card or CF+Card and the CPU.

(PC Card I/O Mode)

Input Acknowledge

-INPACK

In True IDE mode this output signal is not used and should not be

connected at the host.

(True IDE Mode)

-IORD

I

34

35

This signal is not used in this mode.

(PC Card Memory Mode)

-IORD

This is an I/O Read strobe generated by the host. This signal gates

I/O data onto the bus from the CompactFlash Storage Card or CF+Card

when the card is configured to use the I/O interface.

(PC Card I/O Mode)

-IORD

In True IDE Mode, this signal has the same function as in PC Card I/O

Mode.

(True IDE Mode)

-IOWR

This signal is not used in this mode.

(PC Card Memory Mode)

-IOWR

The I/O Write strobe pulse is used to clock I/O data on the Card Data

bus into the CompactFlash Strage Card or CF+Card controller registers

when the CompactFlash Storage Card or CF+Card is configured to use

the I/O interface.

(PC Card I/O Mode)

The clocking will occur on the negative to positive edge of the

signal(trailing edge).

-IOWR

In True IDE Mode, this signal has the same function as in PC Card I/O

Mode.

(True IDE Mode)

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Preliminary version

THNCFxxxMAA Series

Signal Name

Dir.

I

9

Description

-OE

This is an Output Enable strobe generated by the host interface. It is

used to read data from the CompactFlash Strage Card or CF+Card in

Memory Mode and to read the CIS and configuration registers.

(PC Card Memory Mode)

-OE

In PC Card I/O Mode, this signal is used to read the CIS and configuration

registers.

(PC Card I/O Mode)

-ATA SEL

To enable True IDE Mode this Input should be grounded by the host.

(True IDE Mode)

RDY/-BSY

O

37

In Memory Mode this signal is set high when the CompactFlash Storage

Card or CF+Card is ready to accept a new data transfer operation and

held low when the card is busy. The Host memory card socket must

provide a pull-up resistor.

(PC Card Memory Mode)

At power up and at Reset, the RDY/-BSY signal is held low(busy) until the

CompactFlash Storage Card or CF+Card has completed its power up or

reset function.

No access of any type should be made to the

CompactFlash Storage Card or CF+Card during this time.

The

RDY/-BSY signal is held high(disabled from being busy) whenever the

following condition is true: The CompactFlash Storage Card or CF+Card

has been powered up with +RESET continuously disconnected or

asserted.

-IREQ

I/O Operation –After the CompactFlash Storage Card or CF+Card has

been configured for I/O operation, this signal is used as

–Interrupt Request. This line is strobed low to generate a pulse mode

interrupt or held low for a level mode interrupt.

(PC Card I/O Mode)

INTRQ

(True IDE Mode)

In True IDE Mode signal is the active high Interrupt Request to the host.

-REG

I

44

41

This signal is used during Memory Cycles to distinguish between Common

Memory and Register (Attribute) Memory accesses.

(PC Card Memory Mode)

Attribute Memory Select

High for Common Memory, Low for Attribute Memory.

-REG

The signal must also be active (low) during I/O Cycles when the I/O

address is on the Bus.

(PC Card I/O Mode)

-REG

In True IDE Mode this input signal is not used and should be connected to

VCC by the host.

(True IDE Mode)

RESET

When the pin is high, this signal Resets the CompactFlash Storage Card

or CF+Card. The CompactFlash Storage Card or CF+Card is Reset only

at power up if this pin is left high or open from power-up. The

CompactFlash Storage Card or CF+Card is also Reset when the Soft

Reset bit in the Card Configuration Option Register is set.

(PC Card Memory Mode)

RESET

This signal is the same as the PC Card Memory Mode signal.

(PC Card I/O Mode)

-RESET

In the True IDE Mode this input pin is the active low hardware reset from

the host.

(True IDE Mode)

VCC

-

13,38 +5V, +3.3V power

This signal is the same for all modes.

(PC Card Memory Mode)

VCC

(PC Card I/O Mode)

VCC

(True IDE Mode)

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Preliminary version

THNCFxxxMAA Series

Signal Name

Dir. Pin Description

-VS1

O

33

40

Voltage Sense Signals. –VS1 is grounded so that the CompactFlash

Storage Card or CF+Card CIS can be read at 3.3 volts and –VS2 is reserved

by PCMCIA for a secondary voltage.

-VS2

(PC Card Memory Mode)

-VS1

This signal is the same for all modes.

-VS2

(PC Card I/O Mode)

-VS1

This signal is the same for all modes.

-VS2

(True IDE Mode)

-WAIT

O

42

36

The –WAIT signal is driven low by the CompactFlash Storage Card or

CF+Card to signal the host to delay completion of a memory or I/O cycle that

is in progress.

(PC Card Memory Mode)

-WAIT

This signal is the same as the PC Card Memory Mode signal.

(PC Card I/O Mode)

IORDY

In True IDE Mode this output signal may be used as IORDY.

(True IDE Mode)

-WE

I

This is a signal driven by the host and used for strobing memory write data

to the registers of the CompactFlash Storage Card Storage Card or CF+Card

when the card is configured in the memory interfacce mode. It is also used

for writing the configuration registers.

(PC Card Memory Mode)

-WE

In PC Card I/O Mode, this signal is used for writing the configuration

registers.

(PC Card I/O Mode)

-WE

In True IDE Mode this input signal is not used and should be connected to

VCC by the host.

(True IDE Mode)

WP

O

24

Memory Mode – The CompactFlash Storage Card or CF+Card does not

have a write protect switch. This signal is held low after the completion of

the reset initialization sequence.

(PC Card Memory Mode)

Write Protect

-IOIS16

I/O Operation – When the CompactFlash Storage Card or CF+Card is

configured for I/O Operation Pin 24 is used for the –I/O Selected is 16Bit

Port (-IOIS16) function. A Low signal indicates that a 16bit or odd byte only

operation can be performed at the addressed port.

(PC Card I/O Mode)

-IOIS 16

In True IDE Mode this output signal is asserted low when this device is

expecting a word data transfer cycle.

(True IDE Mode)

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Preliminary version

THNCFxxxMAA Series

Access Specifications

1. Attribute access specifications

When CIS-ROM region or Configuration register region is accessed, read and write operations are executed under

the condition of –REG=”L” as follows. That region can be accessed by Byte/World/Old-byte modes, which are

defined by PC card standard specifications.

Attribute Read Access Mode

Mode

-REG -CE2 -CE1 A0

-OE

-WE

x

D8 to D15

High-Z

invalid

D0 to D7

High-Z

Standby mode

Byte access(8-bit)

x

L

H

L

H

L

H

x

L

H

x

L

H

even byte

invalid

H

Word access(16-bit)

Odd byte access(8-bit)

Note: x: L or H

H

even byte

High-Z

L

x

H

invalid

Attribute Write Access Mode

Mode

-REG -CE2 -CE1 A0

-OE

x

-WE

D8 to D15

Don’t care

D0 to D7

Don’t care

even byte

Don’t care

even byte

Don’t care

Standby mode

Byte access(8-bit)

x

L

H

L

H

L

H

x

L

H

x

L

H

Word access(16-bit)

Odd byte access(8-bit)

Note: x: L or H

H

L

x

H

Note: write CIS-ROM region is invalid.

Attribute Access Timing Example

A0 to A10

-REG

-CE2/-CE1

-OE

-WE

D0 to D15

Dout

Din

write cycle

read cycle

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Preliminary version

THNCFxxxMAA Series

Task File register access specifications

There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory

address area. Each case of Task File registers read and write operations is executed under the condition as

follows. That area can be accessed by Byte/World/Odd Byte modes, which are defined by PC card standard

specifications.

(1) I/O address map

Task File Register Read Access Mode (1)

Mode

-REG -CE2 -CE1 A0 -IORD -IOWR -OE -WE D8 to D15 D0 to D7

Standby mode

Byte access(8-bit)

x

L

H

L

H

L

H

x

L

H

x

L

x

High-Z

H

High-Z

even byte

odd byte

even byte

High-Z

Word access(16-bit)

Odd byte access(8-bit)

Note: x: L or H

odd byte

L

x

Task File Register Write Access Mode (1)

Mode

-REG -CE2 -CE1 A0 -IORD -IOWR -OE -WE D8 to D15 D0 to D7

Standby mode

Byte access(8-bit)

x

L

H

L

H

L

H

x

L

H

x

L

x

Don’t care Don’t care

Don’t care even byte

Don’t care odd byte

H

Word access(16-bit)

Odd byte access(8-bit)

Note: x: L or H

odd byte

even byte

L

x

odd byte

Don’t care

Task File Register Access Timing Example (1)

A0 to A10

-REG

-CE2/-CE1

-IORD

-IOWR

D0 to D15

Dout

read cycle

Din

write cycle

2001-09-05 14/52

Preliminary version

THNCFxxxMAA Series

Memory address map

Task File Register Read Access Mode (2)

Mode

-REG -CE2 -CE1 A0 -OE -WE -IORD -IOWR D8 to D15 D0 to D7

Standby mode

Byte access(8-bit)

x

H

L

H

L

H

x

L

H

x

L

x

High-Z

H

High-Z

even byte

odd byte

even byte

High-Z

Word access(16-bit)

Odd byte access(8-bit)

Note: x: L or H

odd byte

L

x

Task File Register Write Access Mode (2)

Mode

-REG -CE2 -CE1 A0 -OE -WE -IORD -IOWR D8 to D15 D0 to D7

Standby mode

Byte access(8-bit)

x

H

L

H

L

H

x

L

H

x

L

x

Don’t care Don’t care

Don’t care even byte

Don’t care odd byte

H

Word access(16-bit)

Odd byte access(8-bit)

Note: x: L or H

odd byte

even byte

L

x

odd byte

Don’t care

Task File Register Access Timing Example (2)

A0 to A10

-REG

-CE2/-CE1

-OE

-WE

D0 to D15

Dout

Din

write cycle

read cycle

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Preliminary version

THNCFxxxMAA Series

True IDE Mode

The card can be configured in a True IDE This card is configured in this mode only when the-OE input signal is

asserted GND by the host. In this True IDE mode Attribute Registers are not accessible from the host. Only

I/O operation to the task file and data register is allowed. If this card is configured during power on sequence,

data register is accessed in word (16-bit). The card permits 8-bit accessed if the user issues a Set Feature

Command to put the device in 8-bit mode.

True IDE Mode Read I/O Function

Mode

-CE2 -CE1 A0 to A2

-IORD

-OWR

D8 to D15

High-Z

D0 to D7

High-Z

Invalid mode

L

H

L

H

L

H

L

x

Standby mode

High-Z

Data register access

Alternate status access

Other task file access

Note: x: L or H

0

L

H

odd byte

High-Z

even byte

status out

data

6H

1-7H

H

High-Z

True IDE Mode Write I/O Function

Mode

-CE2 -CE1 A0 to A2

-IORD

-OWR

D8 to D15

don’t care

odd byte

D0 to D7

don’t care

even byte

control in

data

Invalid mode

L

H

L

H

L

H

L

x

Standby mode

Data register access

Control register access

Other task file access

Note: x: L or H

0

H

L

6H

1-7H

don’t care

H

True IDE Mode I/O Access Timing Example

A0 to A2

-CE

-IORD

-IOWR

-IOIS16

D0 to D15

Dout

Din

write cycle

read cycle

2001-09-05 16/52

Preliminary version

THNCFxxxMAA Series

Configuration register specifications

This card supports four Configuration registers for the purpose of the configuration and observation of this card.

These registers can be used in memory card mode and I/O card mode. In True IDE mode, these registers can not

be used.

1. Configuration Option register(Address 200H)

This register is used for the configuration of the card configuration status and for the issuing soft reset to the

card.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

SRESET

LevlREQ

INDEX

Note: initial value: 00H

Name

R/W

Function

SRESET

Setting this bit to “1”, places the card in the reset state (Card Hard Reset). This

operation is equal to Hard Reset, except this bit is not cleared. Then this bit set to

“0”, places the card in the reset state of Hard Reset (This bit is set to “0” by Hard

Reset). Card configuration status is reset and the card internal initialized operation

starts when Card Hard Reset is executed, so next access to the card should be

the same sequence as the power on sequence.

LevlREQ

(HOST->)

INDEX

R/W

This bit sets to “0” when pulse mode interrupt is selected, and “1” when level mode

interrupt is selected.

This bits is used for select operation mode of the card as follows.

When Power on, Card Hard Reset and Soft Reset, this data is “000000” for the

purpose of Memory card interface recognition.

(HOST->)

INDEX bit assignment

INDEX bit

5

0

4

0

3

0

2

0

1

0

1

0

Card mode Task File register address

Mapping mode

0 Memory card 0H to FH, 400H to 7FFH

Memory mapped

1 I/O card

0 I/O card

1 I/O card

xx0H to xxFH

contiguous I/O mapped

primary I/O mapped

Secondary I/O mapped

1F0H to 1F7H,3F6H to 3F7H

1F0H to 177H,376H to 3F7H

2001-09-05 17/52

Preliminary version

THNCFxxxMAA Series

2. Configuration and Status register (Address 202H)

This register is used for observing the state of the card.

bit7

bit6

bit5

bit4

0

bit3

0

bit2

bit1

bit0

0

CHGED

SIGCHG

IOIS8

PWD

INTR

Note: initial value: 00H

Name

R/W

R

Function

CHGED

This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to “1”.

When CHGED bit is set to “1”, -STSCHG pin is held “L” at the condition of

SIGCHG bit set to “1” and the card configured for the I/O interface.

This bit is set or reset by the host for enabling and disabling the status-change

signal (-STSCHG pin). When the card is configured I/O card interface and this bit

is set “1”, -STSCHG pin is controlled by CHGED bit. If this bit is set to “0”,

-STSCHG pin is kept “H”.

(CARD->)

SIGCHG

R/W

(HOST->)

IOIS8

R/W

The host sets this field to “1” when it can provide I/O cycles only with on 8 bit

data bus (D7 to D0).

(HOST->)

PWD

When this bit is set to “1”, the card enters sleep state (Power Down mode). When

this bit is reset to “0”, the card transfers to idle state (active mode). RRDY/BSY

bit on Pin Replacement Register becomes BUSY when this bit is changed.

RRDY/BSY will not become Ready until the power state requested has been

entered. This card automatically powers down when it is idle and powers back up

when it receives a command.

(HOST->)

INTR

R

This bit indicates the internal state of the interrupt request. This bit state is

available whether I/O card interface has been configured or not. This signal

remains true until the condition, which caused the interrupt request, has been

serviced. If the –IEN bit in the Device Control Register disables interrupts, this bit

is a zero.

(CARD->)

2001-09-05 18/52

Preliminary version

THNCFxxxMAA Series

3. Pin Replacement register (Address 204H)

This register is used for providing the state of –IREQ signal when the card configured I/O card interface.

bit7

0

bit6

0

bit5

bit4

0

bit3

bit2

bit1

bit0

0

CRDY/-BSY

1

RRDY/-BSY

Note: initial value: 0CH

Name

R/W

Function

CRDY/-BSY

(HOST->)

This bit is set to “1” when the RRDY/-BSY bit changes state. The host may also

write this bit.

RRDY/-BSY

(HOST->)

R

When read, this bit indicates +READY pin states. When written, this bit is used for

CRDY/-BSY bit masking.

4. Socket and Copy register (Address 206H)

This register is used for identification of the card from the other cards. Host can read and write this register.

Host should set this register before this card’s Configuration Option register set.

bit7

0

bit6

0

bit5

0

bit4

bit3

0

bit2

0

bit1

bit0

0

DRV#

0

Note: initial value: 00H

Name

R/W

R

Function

DRV#

These fields are used for the configuration of the plural cards. When host

configures the plural cards, written the card’s copy number in this field. In this way,

host can perform the card’s master/slave organization.

(HOST->)

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Preliminary version

THNCFxxxMAA Series

CIS information

CIS information of CompactFlash card is defined as follows.

Address

000H

002H

004H

006H

008H

00AH

00CH

00EH

010H

012H

014H

016H

018H

01AH

Data

01h

03h

d9h

01h

ffh

Description of contents

CISTPL_DEVICE

TPL_LINK

CIS function

Tuple code

Tuple link

Device information

END MARKER

Tuple data

End of Tuple

Tuple code

Tuple link

1ch

04h

03h

d9h

01h

ffh

CISTPL_DEVICE_OC

TPL_LINK

Conditions information

Device information

END MARKER

Tuple data

End of Tuple

Tuple code

Tuple link

18h

02h

dfh

CISTPL_JEDEC_C

TPL_LINK

PCMCIA’s manufacture’s JEDEC ID Tuple data

code

01CH

01EH

020H

022H

024H

026H

028H

02AH

02CH

02EH

030H

032H

034H

036H

038H

03AH

03CH

03EH

040H

042H

044H

046H

048H

04AH

04CH

01h

20h

04h

00h

15h

20h

04h

01h

xxh

PCMCIA’s JEDEC device code

CISTPL_MANFID

Tuple data

Tuple code

Tuple link

TPL_LINK

Low byte of manufacturer's ID code

High byte of manufacturer's ID code

Low byte of product code

High byte of product code

CISTPL_VERS_1

Tuple data

Tuple code

Tuple link

TPL_LINK

TPLLV1_MAJOR

Tuple data

TPLLV1_MINOR

' ' (Vender Specific Strings)

2001-09-05 20/52

Preliminary version

THNCFxxxMAA Series

04EH

050H

052H

054H

056H

058H

05AH

05CH

05EH

060H

062H

064H

066H

068H

06AH

06CH

06EH

070H

072H

074H

076H

078H

07AH

07CH

07EH

080H

082H

084H

086H

088H

08AH

08CH

08EH

090H

092H

094H

096H

098H

09AH

09CH

09EH

0A0H

0A2H

0A4H

xxh

00h

xxh

00h

ffh

' ' (Vender Specific Strings)

Null terminator

Tuple data

End of Tuple

Tuple code

Tuple link

' ' (Vender Specific Strings)

Null terminator

END MARKER

21h

02h

04h

01h

22h

02h

01h

22h

03h

02h

0ch

0fh

CISTPL_FUNCID

TPL_LINK

IC Card function code

System initialization bit mask

CISTPL_FUNCE

Tuple data

Tuple code

Tuple link

TPL_LINK

Type of extended data

Function information

CISTPL_FUNCE

Tuple data

Tuple code

Tuple link

TPL_LINK

Type of extended data

Function information

CISTPL_CONFIG

Tuple data

Tuple code

Tuple link

1ah

05h

01h

03h

00h

02h

0fh

TPL_LINK

Size field

Tuple data

Index number of last entry

Configuration register base address (Low) Tuple data

Configuration register base address (High) Tuple data

Configuration register present mask

CISTPL_CFTABLE_ENTRY

TPL_LINK

Tuple data

Tuple code

Tuple link

Tuple data

1bh

08h

c0h

a1h

01h

55h

08h

Configuration Index Byte

Interface Descriptor

Feature Select

Vcc Selection Byte

Nom V Paramete

Memory length (256 byte pages)

2001-09-05 21/52

Preliminary version

THNCFxxxMAA Series

0A6H

0A8H

0AAH

0ACH

0AEH

0B0H

0B2H

0B4H

0B6H

0B8H

0BAH

0BCH

0BEH

0C0H

0C2H

0C4H

0C6H

0C8H

0CAH

0CCH

0CEH

0D0H

0D2H

0D4H

0D6H

0D8H

0DAH

0DCH

0DEH

0E0H

0E2H

0E4H

0E6H

0E8H

0EAH

0ECH

0EEH

0F0H

0F2H

0F4H

0F6H

0F8H

0FAH

0FCH

00h

20h

1bh

06h

00h

01h

21h

b5h

1eh

4dh

1bh

0ah

c1h

41h

99h

01h

55h

64h

f0h

Memory length (256 byte pages)

Misc features

Tuple data

Tuple code

Tuple link

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Feature Select

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

Peak I Parameter

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Interface Descriptor

Feature Select

Tuple data

Tuple date

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

I/O param

IRQ parameter

ffh

IRQ request mask

Misc features

ffh

20h

1bh

06h

01h

21h

b5h

1eh

4dh

1bh

0fh

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Feature Select

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

Peak I Parameter

CISTPL_CFTABLE_ENTRY

TPL_LINK

c2h

41h

99h

01h

55h

eah

61h

f0h

Configuration Index Byte

Interface Descriptor

Feature Select

Tuple data

Vcc Selection Byte

Nom V Parameter

I/O param

I/O range length and size

Base address

01h

07h

f6h

Base address

Address length

Base address

03h

Base address

2001-09-05 22/52

Preliminary version

THNCFxxxMAA Series

0FEH

100H

102H

104H

106H

108H

10AH

10CH

10EH

110H

112H

114H

116H

118H

11AH

11CH

11EH

120H

122H

124H

126H

128H

12AH

12CH

12EH

130H

132H

134H

136H

138H

13AH

13CH

13EH

140H

142H

144H

146H

148H

14AH

01h

eeh

20h

1bh

06h

02h

01h

21h

b5h

1eh

4dh

1bh

0fh

Address length

Tuple data

Tuple code

Tuple link

IRQ parameter

Misc features

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Feature Select

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

Peak I Parameter

CISTPL_CFTABLE_ENTRY

TPL_LINK

c3h

41h

99h

01h

55h

eah

61h

70h

01h

07h

76h

03h

01h

eeh

20h

1bh

06h

03h

01h

21h

b5h

1eh

4dh

14h

00h

ffh

Configuration Index Byte

Interface Descriptor

Feature Select

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

I/O param

I/O range length and size

Base address

Address length

Base address

Address length

IRQ parameter

Misc features

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Feature Select

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

Peak I Parameter

CISTPL_NO_LINK

TPL_LINK

CISTPL_END

End of Tuple

2001-09-05 23/52

Preliminary version

THNCFxxxMAA Series

Task File register specification

These registers are used for reading and writing the storage data in this card. These registers are mapped five

types by the configuration of INDEX in Configuration Option register. The decoded addresses are shown as

follows.

Memory map (INDEX=0)

-REG A10 A9 to A4 A3 A2 A1 A0 Offset -OE=L

-WE=L

1

0

1

x

0

1

x

0

1

0

1

x

0

1

0

1

0

1

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0H

1H

2H

3H

4H

5H

6H

7H

8H

9H

DH

EH

FH

8H

9H

Data register

Error register

Feature register

Sector count register

Sector number register Sector number register

Cylinder low register

Cylinder high register

Drive head register

Status register

Cylinder low register

Cylinder high register

Drive head register

Command register

Dup. even data register Dup. even data register

Dup. odd data register

Dup. error register

Alt. status register

Drive address register

Even data register

Odd data register

Dup. odd data register

Dup. feature register

Device control register

Reserved

Even data register

Odd data register

2001-09-05 24/52

Preliminary version

THNCFxxxMAA Series

Contiguous I/O map (INDEX=1)

-REG A10 to A4 A3 A2 A1 A0 Offset -IORD=L

-IOWR=L

0

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0H

1H

2H

3H

4H

5H

6H

7H

8H

9H

DH

EH

FH

Data register

Error register

Data register

Feature register

Sector count register

Sector number register Sector number register

Cylinder low register

Cylinder high register

Drive head register

Status register

Cylinder low register

Cylinder high register

Drive head register

Command register

Dup. even data register Dup. even data register

Dup. odd data register

Dup. error register

Dup. odd data register

Dup. feature register

Device control register

Reserved

Alt. status register

Drive address register

Primary I/O map (INDEX=2)

-REG A10 A9 to A4 A3 A2 A1 A0 -IORD=L

-IOWR=L

0

x

1FH

3FH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Data register

Error register

Data register

Feature register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Command register

Device control register

Reserved

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Status register

Alt. status register

Drive address register

2001-09-05 25/52

Preliminary version

THNCFxxxMAA Series

Secondary I/O map (INDEX=3)

-REG A10 A9 to A4 A3 A2 A1 A0 -IORD=L

-IOWR=L

0

x

17FH

37FH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Data register

Error register

Data register

Feature register

Sector count register

Sector number register Sector number register

Cylinder low register

Cylinder high register

Drive head register

Status register

Cylinder low register

Cylinder high register

Drive head register

Command register

Device control register

Reserved

Alt. status register

Drive address register

True IDE Mode I/O map

-CE2 -CE1 A2

A1

0

A0

0

-IORD=L

-IOWR=L

1

0

1

0

1

Data register

Error register

Data register

0

1

Feature register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Command register

Device control register

Reserved

1

0

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Status register

1

0

1

0

1

0

Alt. status register

Drive address register

1

2001-09-05 26/52

Preliminary version

THNCFxxxMAA Series

1.Data register: This register is a 16-bit register that has read/write ability, and it is used for transferring 1 sector

data between the card and the host. This register can be accessed in word mode and byte mode. This register

overlaps the Error or Feature register.

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

D0 to D15

2.Error register: This register is a read only register, and it is used for analyzing the error content at the card

accessing. This register is valid when the BSY bit in Status register and Alternate Status register are set to

“0”(Ready).

bit5

bit4

bit3

bit2

bit1

“0”

bit0

bit7

bit6

BBK

UNC

“0”

IDNF

“0”

ABRT

AMNF

bit Name

Function

BBK(Bad Block detected)

UNC(Data ECC error)

This bit is set when a Bad Block is detected in requester ID field.

7

6

This bit is set when Uncorrectable error is occurred at reading the

card.

IDNF(ID Not Found)

The requested sector ID is in error or cannot be found.

4

2

ABRT(ABoRTed command)

This bit is set if the command has been aborted because of the card

status condition.(Not ready, Write fault, Invalid command, etc.)

AMNF(Address Mark Not Found) This bit is set in case of a general error.

0

3.Feature register: This register is write-only register, and provides information regarding features of the drive that

the host wishes to utilize.

bit5

bit4

bit3

bit2

bit1

bit0

bit7

bit6

Feature byte

5. Sector count register: This register contains the numbers of sectors of data requested to be transferred on a

read or write operation between the host and the card. If the value of this register is zero, a count of 256

sectors is specified. In plural sector transfer, if not successfully completed, the register contains the number of

sectors, which need to be transferred in order to complete, the request.

bit5

bit4

bit3

bit2

bit1

bit0

bit7

bit6

Sector count byte

2001-09-05 27/52

Preliminary version

THNCFxxxMAA Series

5.Sector number register: This register contains the starting sector number, which is started by following sector

transfer command.

bit5

bit4

bit3

bit2

bit1

bit0

bit7

bit6

Sector number byte

6.Cylinder low register: This register contains the low 8-bit of the starting cylinder address, which is started by

following sector transfer command.

bit5

bit4

bit3

bit2

bit1

bit0

bit7

bit6

Cylinder low byte

7.Cylinder high register: This register contains the high 8-bit of the starting cylinder address, which is started by

following sector transfer command.

bit5

bit4

bit3

bit2

bit1

bit0

bit7

bit6

Cylinder high byte

8.Drive head register: This register is used for selecting the Drive number and Head number for the following

command.

bit5

bit4

bit3

bit2

bit1

bit0

bit7

bit6

1

LBA

1

DRV

Head number

bit Name

Function

1

7

This bit is set to “1”.

LBA

6

LBA is a flag to select either Cylinder/Head/Sector (CHS) or

Logical Block Address (LBA) mode. When LBA =0, CHS mode

is selected. When LBA=1, LBA mode is selected. In LBA

mode, the Logical Block Address is interrupted as follows:

LBA07-LBA00：Sector Number Register D7-D0.

LBA15-LBA08：Cylinder Low Register D7-D0.

LBA23-LBA16：Cylinder High Register D7-D0.

LBA27-LBA24：Drive / Head Register bits HS3-HS0.

This bit is set to “1”.

This bit is used for selecting the Master (Card 0)and

Slave(Card 1) in Master/Slave organization. The card is set

to be Card 0 or 1 by using DRV# of the Socket and Copy

register.

1

5

4

DRV(DriVe select)

Head number

3

This bit is used for selecting the Head number for the

following command. Bit 3 is MSB.

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Preliminary version

THNCFxxxMAA Series

9.Status register: This register is read only register, and it indicates the card status of command execution. When

this register is read in configured I/O card mode (INDEX=1,2,3) and level interrupt mode, -IREQ is negated.

bit5

bit4

bit3

bit2

bit1

bit0

bit7

bit6

BSY

DRDY

DWF

DSC

DRQ

CORR

IDX

ERR

bit Name

Function

7

BSY(BuSY)

This bit is set when the card internal operation is executing. When

this bit is set to “1”, other bits in this register are invalid.

If this bit and DSC bit are set to “1”, the card is capable of receiving

the read or write or seek requests. If this bit is set to “0”, the card

prohibits these requests.

6

DRVY(Drive ReaDY)

5

4

3

DWF(Drive Write Fault)

DSC(Drive Seek Complete)

DRQ(Data ReQuest)

This bit is set if this card indicates the write fault status.

This bit is set when the drive seeks complete.

This bit is set when the information can be transferred between the

host and Data register. This bit is cleared when the card receives

the other command.

2

CORR(CORRected data)

This bit is set when a correctable data error has been occurred and

the data has been corrected.

1

IDX(InDeX)

This bit is always set to “0”.

This bit is set when the previous command has ended in some type

of error. The error information is set in this error register or other

Status registers. This bit is cleared by the next command.

0

ERR(ERRor)

10.Alternate status register: This register is the same as Status register in physically, so the bit assignment refers

to previous item of Status register. But this register is different from Status register that –IREQ is not negated

when data read.

11.Command register: This register is write only register, and it is used for writing the command to execute the

requested operation. The command codes is written in the command register, after the parameter is written in the

Task File when the card is in Ready state.

2001-09-05 29/52

Preliminary version

THNCFxxxMAA Series

Used parameter

SC SN CY DR HD LBA

Command

Command code

E5H or 98H

90H

FR

N

Y

Check power mode

Execute drive diagnostic

Erase sector

Format track

Identify Drive

Idle

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

C0H

50H

ECH

E3H or 97H

E1H or 95H

Idle immediate

Initialize drive parameters 91H

Read buffer

E4H

Read multiple

Read long sector

Read sector

C4H

22H or 23H

20H or 21H

40H or 41H

1XH

Read verify sector

Recalibrate

Request sense

Seek

Set features

03H

7XH

EFH

C6H

Set multiple mode

Set sleep mode

Stand by

N

E6H or 99H

E2H or 96H

E0H or 94H

87H

Stand by immediate

Translate sector

Wear level

F5H

E8H

Write buffer

Write long sector

Write multiple

Write multiple w/o erase

Write sector

32H or 33H

C5H

CDH

30H or 31H

38H

3CH

Write sector w/o erase

Write verify

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Preliminary version

THNCFxxxMAA Series

Note: FR: Feature register

SC: Sector Count register

SN: Sector Number register

CY: Cylinder register

DR: DRV bit of Drive Head register

HD: Head Number of Drive Head register

LBA: Logical Block Address Mode Supported

Y: The register contains a valid parameter for this command

N: The register does not contain a valid parameter for this command

12. Device control register: This register is write only register, and it is used for controlling the card interrupt

request and issuing an ATA soft reset to the card.

bit5

x

bit4

x

bit3

bit2

bit1

bit0

0

bit7

x

bit6

x

1

SRST

nIEN

bit

Name

Function

don’t care

This bit is set to “1”.

This bit is set to “1” in order to force the card to perform Task File

Reset operation. This does not change the Card Configuration

registers as a Hardware Reset does. The card remains in Reset until

this bit is reset to “0”.

This bit is used for enabling –IREQ. When this bit is set to “0”,

-IREQ is enabled. When this bit is set to “1”, -IREQ is disabled.

This bit is set to “0”.

7to 4 X

3

2

1

SRST(Software ReSeT)

1

nIEN(Interrupt Enable)

0

13.Drive Address register: This register is read only register, and it is used for confirming the drive status. This

register is provides for compatibility with the AT disk drive interface. It is recommended that this register is not

mapped into the host’s I/O space because of potential conflicts on bit7.

bit5

bit4

bit3

bit2

bit1

bit0

bit7

x

bit6

nWTG

nHS3

nHS2

nHS1

nHS0

nDS1

nDS0

bit

7

Name

X

Function

This bit is unknown.

6

nWTG(WriTing Gate)

5 to 2 nHS3-0(Head Select3-0)

These bits is the negative value of Head Select bits(bit 3 to 0)in

Drive/Head register.

This bit is unknown.

1

nDS1(Idrive Select1)

0

nDS0(Idrive Select0)

2001-09-05 31/52

Preliminary version

THNCFxxxMAA Series

ATA Command specifications

This table summarizes the ATA command set with the paragraphs. Following shows the supported commands and

command codes, which are written in command registers.

ATA Command Set

No. Command set

Code

FR

－

Y

SC

－

Y

SN

－

Y

CY

－

Y

DR

Y

HD

－

Y

LSB

－

Y

1

2

3

4

5

6

7

8

9

Check power mode

E5H or 98H

90H

Execute drive diagnostic

Erase sector(s)

Format track

C0H

50H

Y

－

Y

Identify Drive

ECH

－

Y

－

Y

－

Y

－

Y

Idle

E3H or 97H

E1H or 95H

91H

Idle immediate

Initialize drive parameters

Read buffer

－

Y

E4H

－

Y

－

Y

10 Read multiple

11 Read long sector

12 Read sector(s)

13 Read verify sector(s)

14 Recalibrate

C4H

22H,23H

20H,21H

40H, 41H

1XH

－

Y

－

Y

－

Y

－

Y

－

Y

－

Y

15 Request sense

16 Seek

03H

7XH

17 Set features

EFH

－

Y

－

Y

－

Y

－

Y

18 Set multiple mode

19 Set sleep mode

20 Stand by

C6H

－

E6H or 99H

E2H or 96H

E0H or 94H

87H

－

Y

21 Stand by immediate

22 Translate sector

23 Wear level

F5H

－

Y

－

Y

－

Y

－

Y

24 Write buffer

E8H

－

Y

25 Write long sector

26 Write multiple

27 Write multiple w/o erase

28 Write sector

32H or 33H

C5H

Y

CDH

Y

30H or 31H

38H

Y

29 Write sector w/o erase

30 Write verify

Y

3CH

Y

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Preliminary version

THNCFxxxMAA Series

Note： FR：Feature Register

SC：Sector Count register (00H to FFH)

SN：Sector Number register (01H to 20H)

CY：Cylinder Low/High register

DR：Drive bit of Drive/Head register

HD：Head No.(0 to 3) of Drive/Head register

Y：Set up

－：Not set up

1.Check Power Mode (code: E5H or 98H): This command checks the power mode.

2.Execute Drive Diagnostic (code: 90H): This command performs the internal diagnostic tests implemented by the

Card.

3.Erase Sector(s)(code: C0H): This command is used to erase data sectors.

4.Format Track (code: 50H): This command writes the desired head and cylinder of the selected drive with a

vendor unique data pattern (typically FFH or 00H). To remain host backward compatible, the card expects one

sector (512Bytes) of data from the host to follow the command with same protocol as the Write Sector

Command.

5.Identify Drive (code: ECH): This command enables the host to receive parameter information from the Card.

2001-09-05 33/52

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THNCFxxxMAA Series

Identify Drive Information

Word address

Default value Total bytes Data field type information

0

848AH

XXXX

0000H

00XXH

0000H

XXXX

0000H

XXXX

0001H

0004H

XXXX

0001H

0000H

0200H

0000H

0200H

0000H

XXXX

0101H

XXXX

0000H

2

General configuration bit-significant information

1

2

Default number of cylinders

2

Reserved

3

2

Default number of heads

4

2

Number of unformatted bytes per track

Number of unformatted bytes per sector

Default number of sectors per track

Number of sectors per card(Word7=MSW,Words=LSW)

Reserved

5

2

6

2

7 to 8

4

9

2

10 to 19

20

2

Serial number in ASCII

20

Buffer type(single ported)

21

2

Buffer size in 512 byte increments

# of ECC bytes passed on Read/Write Long Commands

Firmware revision in ASCII etc.

Maximum of 1 sector on Read/Write Multiple command

22

2

23 to 46

47

48

2

48

2

Double Word not supported

Capabilities: DMA NOT Supported(bit 8), LBA supported

49

2

50

2

Reserved

51

2

PIO data transfer cycle timing mode 2

DMA data transfer cycle timing mode not Supported

Reserved

52

2

53 to 58

59

12

2

Multiple sector setting is valid

Total number of sectors addressable in LBA Mode

Reserved

60 to 61

62 to 255

4

388

6.Idle (code: E3H or 97H): This command causes the Card to set BSY, enter the Idle mode, clear BSY and generate

an interrupt. If sector count is non-zero, the automatic power down mode is enabled. If the sector count is

zero, the automatic power mode is disabled.

7.Idle Immediate (code: E1H or 95H): This command causes the Card to set BSY, enter the Idle(Read) mode, clear

BSY and generate an interrupt.

8.Initialize Drive Parameters (code: 91H): This command enables the host to set the number of sectors per track

and the number of heads per cylinder.

9.Read Buffer (code: E4H): This command enables the host to read the current contents of the card’s sector

buffer.

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THNCFxxxMAA Series

Read Multiple (code: C4H): This command performs similarly to the Read Sectors command. Interrupts

10.

are not generated on each sector, but on the transfer of a block which contains the number of sectors defined

by a Set Multiple command.

11.

Read Long Sector (code 22H or 23H): This command performs similarly to the Read Sector(s) command

except that it returns 516 bytes of data instead of 512 bytes.

12.

Read Sector(s) (code 20H, 21H): This command reads from 1 to 256 sectors as specified in the Sector

Count register. A sector count of 0 requests 256 sectors. The transfer beings specified in the Sector Number

register.

13.

Read Verify Sector(s) (code: 40H or 41H): This command is identical to the Read Sectors command,

except that DRQ is never set and no data is transferred to the host.

14.

compatibility purposes.

15.

error.

Recalibrate (code: 1XH): This command is effectively a NOP command to the Card and is provided for

Request Sense (code: 03H): This command requests an extended error code after command ends with an

16.

Seek (code: 7XH): This command is effectively a NOP command to the Card although it does perform a

range check.

17.

Set Features (code: EFH): This command is used by the host to establish or select certain features.

Feature

Operation

01H

55H

66H

81H

BBH

CCH

Enable 8-bit data transfers.

Disable Read Look Ahead.

Disable Power on Reset (POR) establishment of defaults at Soft Reset.

Disable 8-bit data transfers.

4 bytes of data apply on Read/Write Long commands.

Enable Power on Reset (POR) establishment of defaults at Soft Reset.

18.

Set Multiple Mode (code: C6H): This command enables the Card to perform Read and Write Multiple

operations and establishes the block count for these commands.

19. Set Sleep Mode (code: E6H or 99H): This command causes the Card to set BSY, enter the Sleep mode,

clear BSY and generate an interrupt.

20.

Stand By (code: E2H or 96H): This command causes the Card to set BSY, enter the Sleep mode (which

corresponds to the ATA “Standby” Mode), clear BSY and return the interrupt immediately.

21.

Stand By Immediate (code: E0H or 94H): This command causes the Card to set BSY, enter the Sleep

mode (which corresponds to the ATA “Standby” Mode), clear BSY and return the interrupt immediately.

22.

Translate Sector (code: 87H): This command allows the host a method of determining the exact number

of times a use sector has been erased and programmed.

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Preliminary version

THNCFxxxMAA Series

Wear Level (code: F5H): This command effectively a NOP command and only implemented for backward

23.

compatibility. The Sector Count Register will always be returned with a 00H indicating Wear Level is not

needed.

24.

Write Buffer (code: E8H): This command enables the host to overwrite contents of the Card’s sector

buffer with any data pattern desired.

25.

Write Long Sector (code: 32H or 33H): This command is provided for compatibility purposes and is

similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes.

26.

Write Multiple (code: C5H): This command is similar to the Write Sectors command. Interrupts are not

presented on each sector, but on the transfer of a block which contains the number of sectors defined by Set

Multiple command.

27.

Write Multiple without Erase (code: CDH): This command is similar to the Write Multiple command with

the exception that an implied erase before write operation is not performed.

28.

Write Sector(s): (code: 30H or 31H): This command writes from 1 to 256 sectors as specified in the

Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector

specified in the Sector Number register.

29.

Write Sector(s) without Erase (code: 38H): This command is similar to the Write Sector(s) command with

the exception that an implied erase before write operation is not performed.

30.

Write Verify (code: 3CH): This command is similar to the Write Sector(s) command, except each sector is

verified immediately after being written.

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Preliminary version

THNCFxxxMAA Series

Sector Transfer Protocol

1.Sector read: sector read procedure after the card configured I/O interface is shown as follows.

Start

I/O Access, INDEX=1

Set the cylinder low/high register

Set the head No. of drive head register

(1)Set the logical sector number

Set the sector number register

Set in sector count register

Set “2φH” in Command register

(2)set read sector command

(3)Polling until ready

N

Read the status register

N

“51H”?

“58H”?

Y

Read 256 times the data register

(512 bytes)

Y

(4)Burst data transfer

(5)Read more sectors?

error handle

N

Get all data?

Y

Wait the command input

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Preliminary version

THNCFxxxMAA Series

2.Sector write: write sector procedure after the card configured I/O interface is shown as follows.

(3)

(4)

(5)

(1)

(2)

7H

A0 to A10

7H

0H

7H

4H 5H 6H 3H 2H

-CE1

-CE2

-IOWR

-IORD

D0 to D15

-IREQ

01H20H D0H→58H (Data transfer)

D0H→50H

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Preliminary version

THNCFxxxMAA Series

Start

I/O Access, INDEX=1

Set the cylinder low/high register

Set the head No. of drive head register

Set the sector number register

Set in sector count register

Set “30H” in command register

Read the status register

(1)Set the logical sector number

(2)

(3)

N

“51H”

“58H”?

Y

Read 256 times the data register

(512 bytes)

(4)Burst data transfer

all data write

N

Y

N

Y

Read the status register

N

(5)

“51H”

“50H”?

Y

error handle

Wait the command input

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Preliminary version

THNCFxxxMAA Series

(1)

(2)

7H

(3)

(4)

0H

(5)

7H

A0 to A10

-CE1

7H

0H

7H

4H 5H 6H 3H 2H

-CE2

-IOWR

-IORD

D0 to D15

01H30H D0H→58H (Data transfer)

D0H→50H

-IREQ

Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

V

Note

All input/output voltages

V_CCvoltage

Vin, Vout

V_CC

-0.3 to V_CC+0.3

-0.3 to +6.7

0 to +85

1

V

Operation temperature range

Storage temperature range

Topr

°C

Tstg

-55 to +125

Note: 1. Vin, Vout min=-2.0 V for pulse width ≦20ns.

Recommended Operation Conditions

Parameter

Symbol

Ta

Min

0

Typ

25

Max

60

Unit

°C

V

Operation temperature

V_CCvoltage

V_CC

4.5

3.15

5.0

3.3

5.5

3.45

V

Capacitance (Ta=25°C, f=1MHz)

Parameter

Symbol

Cin

Min

－

Typ

Max

Unit

pF

Test conditions Note

Input capacitance

－

15

Vin=0V

1

Output capacitance Count

－

pF

Vout=0V

Note: 1. This parameter is sampled and not 100% tested.

2001-09-05 40/52

Preliminary version

THNCFxxxMAA Series

Card System performance

Item

Performance

500 ms (max)

100 μs (max)

4 ms (max)

Set up times (Reset to ready)

Set up times (Sleep to idle)

Set up times (Deep power down to idle)

Data transfer rate to/from host

Sustained read transfer rate

Sustained write transfer rate

Controller overhead (Command to DRQ)

Data transfer cycle end to ready(Sector write)

16 Mbyte/s burst (max), theoretically

5.4Mbyte/s (max), actually

3.2Mbyte/s (max), actually

4 ms (max)

500μs (typ), 50 ms (max)

2001-09-05 41/52

Preliminary version

THNCFxxxMAA Series

DC Characteristics-1 (Ta=0 to +70°C, V_CC= 3.3V±5%, 5V±10%)

Parameter

Symbol

V_IH

Min

2.0

-0.3

－

Typ

－

Max

V_CC+0.3

0.6

Unit Test conditions

Input voltage

V

－

V_IL

－

Schmitt circuit

V_T+

V_T-

V_OH

V_OL

I_LI

2.1

1.2

－

V

V_CC=3.3V

－

V

Output voltage (4mA)

2.4

－

V

I_OH=-4mA

I_OL=4mA

－

0.4

V

Input leakage current

Output leakage current

－

1

μA

I_LO

－

1

μA V_OUT=high impedance

Pull-up current (Resistivity) －I_PU

Pull-down current (Resistivity) －I_PD

20/(165) 45/(73) 72/(45) μA(kΩ) V_Force=3.3V

-20/(1800) -48/(206) -72/(85) μA(kΩ) V_Force=0V

Sleep/standby current

I_SP1

－

(0.2)

(0.5)

MA CMOS level

(control signal=V_CC-0.2)

MA CMOS level

(control signal=V_CC-0.2)

Sector read current

I_CCR(DC)

－

(25)

(50)

I_CCR(Peak)

I_CCW(DC)

－

(50)

(25)

(80)

(50)

MA

Sector write current

MA CMOS level

(control signal=V_CC-0.2)

I_CCW(Peak)

－

(50)

(80)

MA

XIN

T_clkl

T_clkh

Symbol

Parameter

clock LOW time

clock HIGH time

Min

Max

Tclkl

20

Tclkh

2001-09-05 42/52

Preliminary version

THNCFxxxMAA Series

AC Characteristics (Ta=0 to +60°C, V_CC= 5V±10%, V_CC= 3.3V±5%)

Attribute Memory Read AC Characteristics

Parameter

Symbol

Tcr

Min

100

－

5

Typ

－

Max

－

Unit

ns

Read cycle time

Address access time

-CE access time

ta(A)

100

50

ta(CE)

ta(OE)

tdis(CE)

tdis(OE)

ten(CE)

ten(OE)

tv(A)

-OE access time

Output disable time(-CE)

Output disable time(-OE)

Output enable time(-CE)

Output enable time(-OE)

Data valid time(A)

40

－

5

－

0

－

Address setup time

tsu(A)

30

－

Attribute Memory Read Timing

tc ( R )

An

ta ( A )

-REG

tv ( A )

tsu ( A )

ta ( CE )

-CE

tdls ( CE )

tdls ( OE )

ten ( CE )

ta ( OE )

-OE

ten ( OE )

Dout

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Preliminary version

THNCFxxxMAA Series

Attribute Memory Write AC Characteristics

Parameter

Symbol

tCW

Min

100

60

Typ

－

Max

－

Unit

ns

Write cycle time

Write pulse time

Address setup time

Data setup time (-WE)

Data hold time

tw(WE)

tsu(A)

－

ns

30

－

ns

tsu(D-WEH)

th(D)

40

－

ns

30

－

ns

Write recover time

trec(WE)

20

－

ns

Attribute Memory Write Timing

tc(W)

-Reg

An

tsu(A)

trec(WE)

-WE

tw(WE)

tsu(D-WEH)

th(D)

-CE

-OE

Din

Data in Valid

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Preliminary version

THNCFxxxMAA Series

I/O Access Read AC Characteristics

Parameter

Symbol

Min

－

0

Typ

－

Max

45

－

45

35

Unit

ns

Data delay after –IORD

Data hold following –IORD

-IORD pulse width

td(IORD)

th(IORD)

tw(IORD)

80

30

20

0

Address setup before -IORD

Address hold following –IORD

-CE setup before –IORD

-CE hold following –IORD

-REG setup before –IORD

-REG hold following –IORD

-INPACK delay failing from –IORD tdfINPACK(IORD)

-INPACK delay rising from –IORD

-IOIS16 delay falling from address

-IOIS16 delay rising from address

tsuA(IORD)

thA(IORD)

tsuCE(IORD)

thCE(IORD)

tsuREG(IORD)

thREG(IORD)

0

tdrINPACK(IORD)

tdfIOIS16(ADR)

tdrIOIS16(ADR)

－

I/O Access Read Timing+

An

tsuA(IORD)

thA(IORD)

tsuREG(IORD)

thREG(IORD)

-REG

-CE

tsuCE(IORD)

thCE(IORD)

tw(IORD)

-IORD

tdnINPACK(IORD)

tdnIOIS16(ADR)

tdfINPACK(IORD)

td(IORD)

-INPACK

-IOIS16

tdfIOIS16(ADR)

Dout

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Preliminary version

THNCFxxxMAA Series

I/O Access Write AC Characteristics

Parameter

Symbol

Min

40

30

80

30

20

0

Typ

－

Max

－

35

Unit

ns

Data setup before –IOWR

Data hold following –IOWR

-IOWR pulse width

tsu(IOWR)

th(IOWR)

tw(IOWR)

Address setup before –IOWR

Address hold following –IOWR

-CE setup before –IOWR

-CE hold following –IOWR

-REG setup before –IOWR

-REG hold following –IOWR

-IOIS16 delay falling from address

-IOIS16 delay rising from address

tsuA(IOWR)

thA(IOWR)

tsuCE(IOWR)

thCE(IOWR)

tsuREG(IOWR)

thREG(IOWR)

tdfIOIS16(ADR)

tdrIOIS16(ADR)

0

－

I/O Access Write Timing

An

tsuA(IOWR)

tsuREG(IOWR)

thA(IOWR)

thREG(IOWR)

thCE(IOWR)

-REG

-CE

tsuCE(IOWR)

tw(IOWR)

tsu(IOWR)

th(IOWR)

-IOWR

tdrIOIS16(ADR)

-IOIS16

tdfIOIS16(ADR)

Din Valid

Din

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Preliminary version

THNCFxxxMAA Series

Command Memory Access Read AC Characteristics

Parameter

Symbol

ta(OE)

tdis(OE)

tsu(A)

Min

－

30

20

0

Typ

－

Max

60

40

－

Unit

ns

-OE access time

Output disable time (-OE)

Address setup time

Address hold time

-CE setup time

ns

th(A)

－

ns

tsu(CE)

th(CE)

－

ns

-CE hold time

0

－

ns

Common Memory Access Read Timing

An

tsu(A)

th(A)

-REG

tsu(CE)

th(CE)

-CE

-OE

ta(OE)

tdis(OE)

Dout

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Preliminary version

THNCFxxxMAA Series

Common Memory Access Write AC Characteristic

Parameter

Symbol

tsu(D-WEH)

th(D)

Min

40

30

80

30

0

Typ

－

Max

－

Unit

ns

Data setup time (-WE)

Data hold time

ns

Write pulse time

Address setup time

-CE setup time

tw(WE)

tsu(A)

ns

tsu(CE)

trec(WE)

th(CE)

ns

Write recover time

-CE hold following -WE

20

0

ns

Common Memory Access Write Timing

An

tsu(A)

th(A)

-REG

th(CE)

tsu(CE)

-CE

-WE

Din

trec(WE)

tw(WE)

th(D)

Din Valid

2001-09-05 48/52

Preliminary version

THNCFxxxMAA Series

The IDE Mode Access Read AC Characteristics

Parameter

Symbol

Min

－

0

Typ

－

Max

45

－

35

Unit

ns

Data delay after IORD

Data hold following IORD

IORD with time

td(IORD)

th(IORD)

tw(IORD)

80

30

20

0

Address setup before IORD

Address hold following IORD

CE setup before IORD

CE hold following IORD

IOIS16 delay falling from address

IOIS16 delay rising from address

tsuA(IORD)

thA(IORD)

tsuCE(IORD)

thCE(IORD)

tdfIOIS16(ADR)

tsfIOIS16(ADR)

0

－

True IDE Mode Access Read Timing

An

tsuA(IORD)

tsuCE(IORD)

thA(IORD)

-CE

thCE(IORD)

tw(IORD)

-IORD

tdrIOIS16(ADR)

th(IORD)

td(IORD)

-IOIS16

tdfIOIS16(ADR)

Dout

2001-09-05 49/52

Preliminary version

THNCFxxxMAA Series

True IDE Mode Access Write AC Characteristics

Parameter

Symbol

Min

40

30

80

30

20

0

Typ

－

Max

－

35

Unit

ns

Data setup before IOWR

Data hold following IOWR

IORD width time

tsu(IOWR)

th(IOWR)

tw(IOWR)

Address setup before IOWR

Address hold following IOWR

CE setup before IOWR

CE hold following IOWR

IOIS16 delay falling from address

IOIS16 delay rising from address

tsuA(IOWR)

thA(IOWR)

tsuCE(IOWR)

thCE(IOWR)

tdfIOIS16(ADR)

tsfIOIS16(ADR)

0

－

True IDE Mode Access Write Timing

An

tsuA(IOWR)

tsuCE(IOWR)

thA(IOWR)

-CE

thCE(IOWR)

tw(IOWR)

-IORD

tdrIOIS16(ADR)

th(IOWR)

-IOIS16

tsu(IOWR)

tdfIOIS16(ADR)

Dout

Din Valid

2001-09-05 50/52

Preliminary version

THNCFxxxMAA Series

Reset Characteristics (only Memory Card Mode or I/O Card Mode)

Hard Reset Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

Reset setup time

-CE recover time

VCC rising up time

VCC falling down time

Reset pulse width

tsu(RESET)

trec(VCC)

tpr

100

1

－

ms

µs

－

0.1

3

100

300

－

ms

µs

tpf

tw(RESET)

th(Hi-ZRESET)

ts(Hi-ZRESET)

10

1

－

ms

0

－

ms

Hard Reset Timing

tpr

90%

trec(Vcc)

Vcc

10%

-CE1, -CE2

th(Hi-ZRESET)

High-Z

tsu(RESET)

tw(RESET)

ts(Hi-ZRESET)

High-Z

RESET

Low

2001-09-05 51/52

Preliminary version

THNCFxxxMAA Series

Power on Reset Characteristics

Power on reset sequence must need by –PORST at the rising of V_CC.

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

-CE setup time

tsu(VCC)

tpr

100

0.1

－

ms

VCC rising up time

100

Power on Reset Timing

tpr

Vcc

tsu(Vcc)

-PORST

-CE1, -CE2

Attention for Card Use

In the reset or power off, the information of all registers is cleared.

l

Notice that the card insertion/removal should not be executed during host is active, if the card is used in True

IDE mode.

l

After the card hard reset, soft reset, or power on reset, ATA reset, command applied the card cannot access

during +RDY/-BSY pin is “low” level. Flash card can’t be operated in this case.

Before the card insertion V_CCcan not be supplied to the card. After confirmation that –CD1, -CD2 pins are

inserted, supply V_CCto the card.

Note:

-OE must be kept at the V_CClevel during power on reset in memory card mode and I/O card mode. –OE must be

kept constantly at the GND level in True IDE mode.

2001-09-05 52/52


型号：	THNCF256MAA
厂家：	TOSHIBA
描述：	CompactFlash Card CF卡闪存存储内存集成电路 PC
文件：	总52页 (文件大小：462K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THNCF256MAA [TOSHIBA]

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