THNID256MBBI [TOSHIBA]
IC FLASH MEMORY DRIVE CONTROLLER, XMA40, CARD-40, Secondary Storage Controller;
| 型号： | THNID256MBBI |
| 厂家： | 
TOSHIBA |
| 描述： | IC FLASH MEMORY DRIVE CONTROLLER, XMA40, CARD-40, Secondary Storage Controller 数据传输 外围集成电路 |
| 文件： | 总23页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THNIDxxxxBx Series Rev1.7
NAND Flash Drive
--- THNIDxxxxBx Series ---
Outline
The THNIDxxxxBx NAND Flash Drive series from Toshiba features an IDE interface, a flash disk controller chip,
and NAND-type flash memory devices. There are two form factors, 2.5 inch-type and 3.5 inch-type, available in the
series. The THNIDxxxxBx is available in 16 MB, 32 MB, 64 MB, 128 MB, 192 MB, 256 MB, 320 MB, 384 MB, 512
MB, 640 MB, 1024 MB, 1536 MB and 2048 MB capacities in each type. The drives operate with a 5-volts power
supply and support Mode 4 PIO data transfer.
The NAND Flash Drive is geared specifically to the industrial market for use in ATM, factory automation
machine, POS terminal, measuring product, ticket-vending machine, parking system and other industrial products
that require high tolerance to environmental condition.
Features
•
•
•
Capacity
16MB up to 2GB
Form factor
2.5 inch-type, 3.5 inch-type, (HDD compatible)
IDE interface
Mode4 PIO
ATA command set compatible
Power supply
•
•
V
CC
= 5.0 V 10%
Operating temperature
−40°C~85°C (Industrial grade : THNIDxxxxBxI)
0°C~70°C (Commercial grade : THNIDxxxxBx)
Performance
•
Burst data transfer rate (Drive-Host)
Sustained write speed
16.6 MB/sec. (max)
3.2 MB/sec. (max)
6.5 MB/sec. (max)
Sustained read speed
Shock
9800 m/s2 (max) [Non-operating]
Vibration
147 m/s2 peak (25~2000 Hz) [Operating]
000707EBA1
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.
2002-06-11 1/23
THNIDxxxxBx Series Rev1.7
Product Models
2.5 inch-type
Unformatted
Cylinder
Head
Sector
Model No.
16 MB
32 MB
248
496
4
32
32
32
32
32
32
48
48
63
63
63
63
63
THNID016MBA/BAI
THNID032MBA/BAI
THNID064MBA/BAI
THNID128MBA/BAI
THNID192MBA/BAI
THNID256MBA/BAI
THNID320MBA/BAI
THNID384MBA/BAI
THNID512MBA/BAI
THNID640MBA/BAI
THNID1G02BA/BAI
THNID1G53BA/BAI
THNID2G04BA/BAI
4
64 MB
978
4
128 MB
192 MB
256 MB
320 MB
384 MB
512 MB
640 MB
1024 MB
1536 MB
2048 MB
978
8
733
16
16
16
16
16
16
16
16
16
978
814
977
993
1241
1985
2966
3954
3.5 inch-type
Unformatted
Cylinder
Head
Sector
Model No.
16 MB
32 MB
248
496
4
32
32
32
32
32
32
48
48
63
63
63
63
63
THNID016MBB/BBI
THNID032MBB/BBI
THNID064MBB/BBI
THNID128MBB/BBI
THNID192MBB/BBI
THNID256MBB/BBI
THNID320MBB/BBI
THNID384MBB/BBI
THNID512MBB/BBI
THNID640MBB/BBI
THNID1G02BB/BBI
THNID1G53BB/BBI
THNID2G04BB/BBI
4
64 MB
978
4
128 MB
192 MB
256 MB
320 MB
384 MB
512 MB
640 MB
1024 MB
1536 MB
2048 MB
978
8
733
16
16
16
16
16
16
16
16
16
978
814
977
993
1241
1985
2966
3954
2002-06-11 2/23
THNIDxxxxBx Series Rev1.7
Product Specification
•
Storage Capacities:
16, 32, 64, 128, 192, 256, 320, 384, 512, 640, 1024, 1536, 2048 Mbytes (unformatted)
Performance:
•
To/from host
16.6 Mbytes/sec. (max theoretical)
Sustained write
3.2 Mbyte/sec. (max) [ATA PIO mode 4] (≥64 MB)
1.5 Mbyte/sec. (max) [ATA PIO mode 4] (16 MB~32 MB)
6.5 Mbyte/sec. (max) [ATA PIO mode 4]
Sustained read
Operating Voltage:
5V +/− 10%
•
•
Power Consumption:
Read mode
51 mA (typ)
Write mode
43 mA (typ)
Idle mode
16 mA (typ)
Sleep mode
1 mA (typ) (≤64 MB)
3 mA (typ) (2 GB)
•
•
Environmental Specification:
Operating temperature
−40°C to 85°C (Industrial grade : THNIDxxxxBxI)
0°C to 70°C (Commercial grade : THNIDxxxxBx)
−40°C to 85°C (Industrial grade : THNIDxxxxBxI)
−20°C to 85°C (Commercial grade : THNIDxxxxBx)
95% (max) [No condensation]
Storage temperature
Humidity
Shock
9800 m/s2 (max) (3 axis) [No-operating]
Vibration
Reliability:
Error rate
ECC
147 m/s2 peak (25Hz~2000Hz) [Operating]
<1 bit/1015 bit read
1 bit error connection
2002-06-11 3/23
THNIDxxxxBx Series Rev1.7
Mechanical Specification
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
V
Power Supply Voltage
Input Voltage
−0.6 to 6.0
V
V
CC
IN
−0.3 to V + 0.3
CC
−40 to 85 (Industrial grade)
0 to 70 (Commercial grade)
−40 to 85 (Industrial grade)
−20 to 85 (Commercial grade)
T
T
Storage Temperature
Operating Temperature
°C
°C
STG
OPR
Recommended DC Operating Conditions
Symbol
Parameter
Power Supply Voltage
Min
Typ
Max
5.5
Unit
V
V
V
4.5
2.0
5.0
V
V
V
CC
High Level Input Voltage
Low Level Input Voltage
IH
IL
0.8
DC Characteristics (Ta = −40°C to 85°C, VCC = 5.0 V 10%)
Symbol
Parameter
Operating Current (Read)
Operating Current (Write)
Min
Typ
Max
Unit
I
I
51
43
1
mA
mA
mA
mA
V
CCR
CCW
CCS
<
Sleep Mode Current ( 64 MB)
=
I
Sleep Mode Current (2 GB)
High Level Output Voltage
Low Level Output Voltage
3
V
V
V
−0.8
CC
OH
OL
0.4
V
2002-06-11 4/23
THNIDxxxxBx Series Rev1.7
Package Dimensions
3.5 inch
146.5
25.9
41.28
44.45
28.5
41.6
60
10-6.32UN
3.5 inch Flash Drive Dimensions
2002-06-11 5/23
THNIDxxxxBx Series Rev1.7
2.5 inch
101.55
9.50
16-M3
20.93
14.00
38.10
17.57
2.5 Flash Drive Dimensions
2002-06-11 6/23
THNIDxxxxBx Series Rev1.7
Jumper Settings
3.5 inch
Master
1
1
1
Slave
Cable Select
2.5 inch
1
1
Master
Slave
1
Cable Select
2002-06-11 7/23
THNIDxxxxBx Series Rev1.7
Pin Assignments and Pin Type
Pin Number
Signal Name
Pin Type
Pin Number
Signal Name
Pin Type
1
3
RESET
DD7
I
2
4
GND
DD8
I/O
I/O
5
DD6
DD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
6
DD9
DD10
DD11
DD12
DD13
DD14
DD15
KEY(NC)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
7
8
9
DD4
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
DD3
DD2
DD1
DD0
GND
DMARQ(NC)
DIOW
DIOR
GND
I
GND
Reserved
DMACK (NC)
INTRQ
DA1
O
CSEL
GND
O
I/O
I
Reserved
PDIAG
DA2
I
DA0
I
CS0
I
CS1
I
DASP
VCC
I/O
GND
VCC
GND
Note 1: Pins #41 to 44 are for the IDE 44-pin standard (2.5 inch-type).
Note 2: To avoid damage to the drive or its pins, be sure to connect the drive to the IDE connecter properly
Note 3: “I” is defined as a direction from the host to the drive.
“O” is defined as a direction from the drive to the host.
3.5 inch (40 pins)
Power supply
Jumper Pin
2
1
4
3
6
5
8
7
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2.5 inch (44 pins)
Jumper Pin
43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9
7
5
3
1
44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4
2
2002-06-11 8/23
THNIDxxxxBx Series Rev1.7
Signal Description
Signal Name
RESET
Dir.
I
Pin
1
Description
This pin is shall be used by host to reset the device. Reset signal is
from the host and it is active low.
DD[0:15]
DIOW
I/O
3 to 18
23
These lines carry Data, Commands and Status information between
the host and controller. DD[0] is the LSB and DD[15] is the MSB.
I
I
DIOW is the strobe signal asserted by the host to write the device
register.
DIOR
25
DIOR is the strobe signal asserted by the host to read the device
register
INTRQ
O
31
This signal is used by the selected device to interrupt the host
system when interrupt pending is set. When the nIEN bit is cleared to
zero and the device is selected, INTRQ shall be enabled through a
tri-state buffer. When the nIEN bit is set to one or the device is not
selected, the INTRQ signal shall be released.
DA[0: 2]
I
I
33, 35, 36
37, 38
DA[2:0] are used to select one of eight registers
CS0 , CS1
CS0 is used to select the Command Block registers while CS1 is
used to select the Control Block Register.
CSEL
I
28
34
CSEL is used to select Master/Slave mode, Low for Master, High for
Slave mode.
PDIAG
I/O
This bi-directional open drain signal is asserted by the slave after an
Execute Diagnostic command to indicate to the master it has passed
its diagnostics.
DASP
I/O
39
This open drain output is asserted low any time the drive is active. In
a Master/Slave configuration, this signal is used for the slave to
inform the master that a slave drive is present.
GND
VCC
2, 19, 22, 24, 26, 30, 40, 43 Ground
41, 42 Power
2002-06-11 9/23
THNIDxxxxBx Series Rev1.7
I/O Register Specifications
The data is transferred between the host system and the device via I/O registers in the device.
Reads and writes to the registers are performed using the following logics.
Read I/O Register Function
Mode
CS1
CS0
DA0~DA2
DIOR
DIOW
DD8~DD15
High-Z
DD0~DD7
High-Z
Invalid mode
L
H
H
L
L
H
L
×
×
×
×
L
L
L
×
×
Standby mode
High-Z
odd byte
High-Z
High-Z
High-Z
Data register access
Alternate status access
Other command block register access
0
H
H
H
even byte
status out
data
H
L
6H
1~7H
H
Note: ×: L or H
Write I/O Register Function
Mode
CS1
CS0
DA0~DA2
DIOR
DIOW
DD8~DD15
DD0~DD7
Invalid mode
L
H
H
L
L
H
L
×
×
×
×
×
×
L
L
L
don’t care
don’t care
odd byte
don’t care
don’t care
even byte
control in
data
Standby mode
Data register access
Control register access
Other command block register access
0
H
H
H
H
L
6H
1~7H
don’t care
don’t care
H
Note: x: L or H
I/O Register Address
This table summarizes the register selected by DA0~DA2.
CS1
CS0
DA2
DA1
DA0
DIOR = L
Data register
Error register
DIOW = L
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
Data register
Feature register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Device/Head register
Status register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Command register
Device control register
Reserved
Alt. status register
Drive address register
Register Access Timing Example
DA0~DA2
CS
DIOR
DIOW
Dout
Din
DD0~DD15
read cycle
write cycle
2002-06-11 10/23
THNIDxxxxBx Series Rev1.7
1. Data register:
This register is a 16-bit register that has read/write capability. is used for
transferring 1 sector of data between the drive and the host.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DD0~DD15
2. Error register:
This register is read-only. It contains info on errors that occur when the drive is being
accessed. This register is valid when the BSY bit in Status register and Alternate
Status register are set to ”0”
Bit 7
BBK
Bit 6
UNC
Bit 5
“0”
Bit 4
Bit 3
“0”
Bit 2
Bit 1
“0”
Bit 0
IDNF
ABRT
AMNF
Bit
Name
Function
This bit is set when a Bad Block is detected.
7
6
BBK (Bad Block detected)
UNC (Data ECC error)
This bit is set when an uncorrectable error has occurred when
reading the drive.
This bit is set when the requested sector is in error or cannot
be found.
4
2
IDNF (ID Not Found)
This bit is set if the command has been aborted because of the
drive status condition. （Not ready, Write fault, Invalid
command）
ABRT (ABoRTed command)
This bit is set in case of a general error.
0
AMNF (Address Mark Not Found)
3. Feature register:
This register is write-only. It provides information regarding features of the drive
that the host wishes to utilize.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Feature byte
4. Sector count register:
This register contains the number of sectors of data requested to be transferred via a
read or write operation between the host and the drive. If the value of this register is
zero, a count of 256 sectors is specified.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sector count byte
2002-06-11 11/23
THNIDxxxxBx Series Rev1.7
5. Sector number register: This register contains the starting sector number, which is started by following sector
transfer command.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sector number byte
6. Cylinder low register:
This register contains the low 8-bits of the starting cylinder address, which is started
by following sector transfer command.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Cylinder low byte
7. Cylinder high register: This register contains the high 8-bits of the starting cylinder address, which is
started by following sector transfer command.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Cylinder high byte
8. Device/head register:
This register is used for selecting the drive number and Head number for the
following command.
Bit 7
Bit 6
LBA
Bit 5
Bit 4
DRV
Bit 3
Bit 2
Bit 1
Bit 0
Obsolete
Obsolete
Head number
Bit
Name
Function
7
6
Obsolete
This bit is set to “1”.
LBA
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block
Address (LBA) mode. When LBA = 0, CHS mode is selected. When
LBA = 1, LBA mode is selected. In LBA mode, the Logical Block Address is
interpreted as follows:
LBA07-LBA00: Sector Number Register D7-D0.
LBA15-LBA08: Cylinder Low Register D7-D0.
LBA23-LBA16: Cylinder High Register D7-D0.
LBA27-LBA24: Drive/Head Register bits HS3-HS0.
This bit is set to “1”.
5
4
Obsolete
DEV (Device select)
This bit is used for selecting the Master (Drive 0) and Slave (Drive 1) in
Master/Slave organization. Cleared to zero selects the Master (Drive 0)
3
Head number
This bit is used for selecting the Head number for the following command.
Bit 3 is MSB.
2002-06-11 12/23
THNIDxxxxBx Series Rev1.7
9. Status register:
This register is read-only. It indicates the status of the command execution. The
contents of this register are updated to reflect the current state of the device and the
progress of any command being executed by the device. Reading this register when
an interrupt is pending causes the pending interrupt to be cleared. The host should
not read the Status register when an interrupt is expected as this may clear the
pending interrupt before the INTRQ can be recognized by the host.
Bit 7
BSY
Bit 6
DRDY
Bit 5
Bit 4
DSC
Bit 3
Bit 2
Bit 1
Bit 0
ERR
DWF
DRQ
CORR
Obsolete
Bit
7
Name
Function
BSY (BuSY)
This bit is set to “1” when an internal operation is executing. When this
bit is set to “1”, other bits in this register are invalid.
6
DRDY (Drive ReaDY)
This bit is set to “1” when an internal operation has been ended and the
drive is capable of being accessed from the host.
5
4
3
DWF (Drive Write Fault)
This bit is set to “1” if this drive indicates a write fault status.
This bit is set to “1” when the drive seek is complete.
DSC (Drive Seek Complete)
DRQ (Data ReQuest)
This bit is set to “1” when the device is ready to transfer a word of data
between the host and Data register.
2
CORR (CORRected data)
This bit is set to “1” when a correctable data error has occurred and the
data has been corrected.
1
0
Obsolete
This bit is always set to “0”.
ERR (ERRor)
This bit is set to “1” when the previous command has ended in some
type of error. The error information is set in the Error register. This bit is
cleared by the next command.
10. Alternate status register: This register is the same as the Status register in the command block. The bit
assignment is same as the prior description of the Status register. But this register is
different from the Status register in that -IREQ is not negated when data is read.
2002-06-11 13/23
THNIDxxxxBx Series Rev1.7
11. Device control register: This register is write-only. This register allows a host to software reset attached
devices and to enable or disable the assertion of the INTRQ signal by a selected
device.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Reserved
SRST
nIEN
Bit
Name
Function
7~3
2
X
Reserved bits
SRST (Software ReSeT)
This bit is set to “1” in order to have the drive perform Software Reset
operation. The drive remains in Reset until this bit is set to “0”.
1
0
nIEN (Interrupt Enable)
0
This bit is used to enable INTRQ. When this bit is set to”0”, INTRQ is
active. When this bit is set to “1”, INTRQ is high impedance.
This bit is set to “0”.
12. Drive Address register: This register is read-only. It is used for confirming the drive status.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
×
nWTG
nHS3
nHS2
nHS1
nHS0
nDS1
nDS0
Bit
Name
Function
7
X
This bit is unknown. It remains in tri-state, when host read.
“0”
6
nWTG (WriTing Gate)
5~2
nHS3-0 (Head Select 3~0)
These 4 bits are the negative value of Head Number in the Drive/Head
register.
1
0
nDS1 (Idrive Select 1)
nDS0 (Idrive Select 0)
This bit is “0”, when drive 1 is selected.
This bit is “0”, when drive 0 is selected.
2002-06-11 14/23
THNIDxxxxBx Series Rev1.7
13. Command register:
This register is write-only. Each command to be executed is written to this register,
after setting the parameters as follows.
Used Parameter
Command
Command code
FR
SC
SN
CY
DR
HD
LBA
Check power mode
Execute drive diagnostic
CFA erase sector
Format track
E5H or 98H
90H
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
N
Y
N
Y
N
Y
N
Y
Y
N
N
N
N
Y
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
Y
N
N
N
N
N
N
Y
Y
Y
Y
N
N
Y
N
N
N
N
N
Y
N
N
Y
Y
Y
Y
Y
Y
N
N
Y
Y
N
N
N
N
N
Y
Y
Y
Y
N
N
Y
N
N
N
N
N
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
N
N
N
Y
N
Y
Y
Y
Y
N
N
Y
N
N
N
N
N
Y
N
N
Y
Y
Y
Y
Y
Y
N
N
Y
Y
N
N
N
N
N
Y
Y
Y
Y
N
N
Y
N
N
N
N
N
Y
N
N
Y
Y
Y
Y
Y
Y
C0H
50H
Identify Drive
ECH
Idle
E3H or 97H
E1H or 95H
91H
Idle immediate
Initialize drive parameters
Read buffer
E4H
Read multiple
C4H
Read long sector
Read sector
22H or 23H
20H or 21H
40H or 41H
1XH
Read verify sector
Recalibrate
CFA request extended error
Seek
03H
7XH
Set features
EFH
Set multiple mode
Sleep
C6H
E6H or 99H
E2H or 96H
E0H or 94H
87H
Stand by
Stand by immediate
CFA translate sector
CFA wear level
Write buffer
F5H
E8H
Write long sector
Write multiple
32H or 33H
C5H
CFA write multiple w/o erase
Write sector
CDH
30H or 31H
38H
CFA write sector w/o erase
Write verify
3CH
Note: FR: Feature register
SC: Sector Count register
SN: Sector Number register
CY: Cylinder Low/High register
DR: DRV bit of Drive Head register
HD: Head Number of Drive/Head register
LBA: Logical Block Address Mode Supported
Y:
The register contains a valid parameter for this command
The register does not contain a valid parameter for this command
N:
2002-06-11 15/23
THNIDxxxxBx Series Rev1.7
ATA Command Specification
1. Check Power Mode (code: E5H or 98H): This command checks the power mode.
2. Execute Drive Diagnostic (code: 90H): This command performs the internal diagnostic tests implemented by
the drive.
3. CFA Erase Sector (s) (code: C0H): This command is used to erase data sectors.
4. Format Track (code: 50H): This command writes the desired head and cylinder of the selected drive. But
selected sector data is not exchanged. This drive expects one sector (512 bytes) of data from the host to follow
the command with the same protocol as the Write Sector Command
5. Identify Drive (code: ECH): This command enables the host to receive parameter information from the drive.
Identify Drive Information
Word address
Default value
Total bytes
Data field type information
0
040AH
XXXX
0000H
00XXH
XXXX
XXXX
XXXX
XXXX
0000H
XXXX
0001H
0004H
0004H
XXXX
0001H
0000H
0200H
0000H
0400H
0000H
XXXX
0101H
XXXX
0000H
2
2
General configuration bit-significant information
Default number of cylinders
1
2
2
Reserved
3
2
Default number of heads
4
2
Number of unformatted bytes per track
Number of unformatted bytes per sector
Default number of sectors per track
Reserved
5
6
2
2
7 to 8
9
4
2
Reserved
10 to 19
20
20
2
Serial number in ASCII
Buffer type(single ported)
21
2
Buffer size in 512 byte increments
# of ECC bytes passed on Read/Write Long Commands
Firmware revision in ASCII etc.
Maximum number of sectors on Read/Write Multiple command
Double Word not supported
22
2
23 to 46
47
48
2
48
2
49
2
Capabilities: DMA NOT Supported (bit8), LBA supported (bit9)
Reserved
50
2
51
2
PIO data transfer cycle timing mode 4
DMA data transfer cycle timing mode not Supported
Reserved
52
2
53 to 58
59
12
2
Multiple sector setting is valid
Total number of sectors addressable in LBA Mode
Reserved
60 to 61
62 to 255
4
388
6. Idle (code: E3H or 97H): This command causes the drive to set BSY, enter the Idle mode, clear BSY and
generate an interrupt. If the sector count is non-zero, the automatic power down mode is enabled. If the
sector count is zero, the automatic power mode is disabled.
7. Idle Immediate (code: E1H or 95H): This command causes the drive to set BSY, enter the Idle(Read) mode,
clear BSY and generate an interrupt.
2002-06-11 16/23
THNIDxxxxBx Series Rev1.7
8. Initialize Drive Parameters (code: 91H): This command enables the host to set the number of sectors per track
and the number of heads per cycle.
9. Read Buffer (code: E4H): This command enables the host to read the current contents of the drive’s sector
buffer.
10. Read Multiple (code: C4H): This command performs similarly to the Read Sectors command. Interrupts are
not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a
Set Multiple command.
11. Read Long Sector (code 22H or 23H): This command performs similarly to the Read Sector(s) command except
that it returns 516 bytes of data instead of 512 bytes.
12. Read Sector(s) (code 20H, 21H): This command reads from 1 to 256 sectors as specified in the Sector Count
register. A sector count of 0 requests 256 sectors. The transfer beings at the sector specified in the Sector
Number register.
13. Read Verify Sector(s) (code: 40H or 41H): This command is identical to the Read Sectors command, except that
DRQ is never set and no data is transferred to the host.
14. Recalibrate (code: 1XH): This command is effectively a NOP command to the drive and is provided for
compatibility purposes.
15. CFA Request Extended Error (code: 03H): This command requests an extended error code after command ends
with an error.
16. Seek (code: 7XH): This command is effectively a NOP command to the drive although it does perform a range
check.
17. Set Features (code: EFH): This command is used by the host to establish or select certain features.
Feature
Operation
01H
55H
66H
81H
BBH
CCH
Enable 8-bit data transfers.(CFA feature set only)
Disable Read Look Ahead.
Disable Power on Reset (POR) establishment of defaults at Soft Reset.
Disable 8-bit data transfers. (CFA feature set only)
4 bytes of data apply on Read/Write Long commands.
Enable Power on Reset (POR) establishment of defaults at Soft Reset.
18. Set Multiple Mode (code: C6H): This command enables the drive to perform Read and Write Multiple
operations and establishes the block count for these commands.
19. Sleep (code: E6H or 99H): This command causes the drive to set BSY, enter the Sleep mode, clear BSY and
generate an interrupt.
20. Stand By (code: E2H or 96H): This command causes the drive to set BSY, enter the Standby mode, clear BSY
and return the interrupt immediately.
21. Stand By Immediate (code: E0H or 94H): This command causes the drive to set BSY, enter the Ｓｔａｎｄｂｙ mode,
clear BSY and return the interrupt immediately
22. CFA Translate Sector (code: 87H): This command allows the host a method of determining the exact number of
times a use sector has been erased and programmed
23. CFA Wear Level (code: F5H): This command is effectively a NOP command and only implemented for backward
compatibility. The Sector Count Register will always be returned with a 00H indicating Wear Level is not
needed.
24. Write Buffer (code: E8H): This command enables the host to overwrite contents of the drive’s sector buffer with
any data pattern desired.
25. Write Long Sector (code: 32H or 33H): This command is provided for compatibility purposes and is similar to
the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes.
2002-06-11 17/23
THNIDxxxxBx Series Rev1.7
26. Write Multiple (code: C5H): This command is similar to the Write Sector(s) command. Interrupts are not
presented on each sector, but on the transfer of a block which contains the number of sectors defined by Set
Multiple command.
27. CFA Write Multiple without Erase (code: CDH): This command is similar to the Write Multiple command with
the exception that an implied erase before write operation is not performed.
28. Write Sector(s) (code: 30H or 31H): This command writes from 1 to 256 sectors as specified in the Sector Count
register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector
Number register.
29. CFA Write Sector(s) without Erase (code: 38H): This command is similar to the Write Sector(s) command with
the exception that an implied erase before write operation is not performed.
30. Write Verify(s) (code: 3CH): This command is similar to the Write Sector(s) command, except each sector is
verified immediately after being written.
2002-06-11 18/23
THNIDxxxxBx Series Rev1.7
Sector Transfer Protocol
1. Sector read: The protocol of sector(s) read is as follows.
Start
I/O Access, INDEX = 1
Set the cylinder low/high register
Set the head No. of drive head register
Set the sector number register
Set in sector count register
(1) Set the logical sector number
(2) Set read sector command
Set “2 φH” in command register
Read the status register
“58 H”?
N
(3) Polling until ready
N
“51 H”
Read 256 times from the data register
(512 bytes)
Y
(4) Burst data transfer
error handle
(5) Read more sectors?
N
Get all data?
Y
Wait the command input
2002-06-11 19/23
THNIDxxxxBx Series Rev1.7
2. Sector write: The protocol of write sector(s) is as follows.
Start
Set the cylinder low/high register
Set the head No. of drive head register
Set the sector number register
Set in sector count register
(1) Set the logical sector number
(2) Set write sector command
Set “30 H” in command register
Read the status register
N
(3) Polling until ready
N
“51 H”
“58 H”?
Write 256 times into the data register
(512 bytes)
(4) Burst data transfer
(5) Write more sector
N
all data write
Y
N
Y
Read the status register
N
“51 H”
“50 H”?
Y
Y
error handle
Wait the command input
2002-06-11 20/23
THNIDxxxxBx Series Rev1.7
AC Characteristics (Ta = −40 ~ +85°C, V = 5 V 10%)
CC
Access Read AC Characteristics
Parameter
Data delay after DIOR
Symbol
td (DIOR)
Min
Typ.
Max
Unit
5
50
ns
ns
ns
ns
ns
ns
ns
Data hold following DIOR
DIOR width time
th (DIOR)
tw (DIOR)
70
15
10
5
Address setup before DIOR
Address hold following DIOR
CS setup before DIOR
CS hold following DIOR
tsuA (DIOR)
thA (DIOR)
tsuCS (DIOR)
thCS (DIOR)
10
Access Read Timing
An
thA (DIOR)
tsuA (DIOR)
CS
tsuCE (DIOR)
thCE (DIOR)
tw (DIOR)
DIOR
th (DIOR)
td (DIOR)
DD [0:15]
2002-06-11 21/23
THNIDxxxxBx Series Rev1.7
Access Write AC Characteristics
Parameter
Symbol
tsu (DIOW)
Min
Typ.
Max
Unit
Data setup before DIOW
Data hold following DIOW
DIOW width time
20
10
70
15
10
5
ns
ns
ns
ns
ns
ns
ns
th (DIOW)
tw (DIOW)
Address setup before DIOW
Address hold following DIOW
CS setup before DIOW
CS hold following DIOW
tsuA (DIOW)
thA (DIOW)
tsuCS (DIOW)
thCS (DIOW)
10
Access Write Timing
An
thA (DIOW)
tsuA (DIOW)
CS
tsuCE (DIOW)
thCE (DIOW)
tw (DIOW)
DIOW
th (DIOW)
td (DIOW)
DD [0:15]
2002-06-11 22/23
THNIDxxxxBx Series Rev1.7
Power on Reset Characteristics
This table summarizes the power on reset sequence.
Hard Reset Timing
tw (RESET)
RESET
tsu (RESET)
CS0 , CS1
Hard Reset Characteristics
Parameter
Reset setup time
Symbol
Min
Typ
Max
Unit
Test Conditions
tsu (RESET)
tw (RESET)
2
ms
Reset pulse width
25
µs
Attention for Drive Use
•
•
•
After performing the reset or power off operation, the information of all registers is cleared.
Please do not insert or remove the drive while the host is active.
After performing a hard reset, soft reset, power on reset or command input, commands cannot be applied to the
drive while the bit7 (BSY) in the Status register is “high” level. Flash drive will not respond in this case.
It is recommended that the drive should be formatted using an operating system before using it.
•
2002-06-11 23/23
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