TMP47C201M中文资料_数据手册_规格书

TOSHIBA

TLCS-47E Series

TMP47C101/201

The 47C101/201 are high speed and high performance 4-bit sin-

gle chip microcomputers, integrating ROM, RAM, input/output

ports and timer/counters on a chip. The 47C101/201 are the

standard type devices in the TLCS-47E series.

CMOS 4-bit Microcontroller

TMP47C101P, TMP47C201P,

TMP47C101M, TMP47C201M

Part No.

ROM

RAM

Package

OTP

Piggyback + Adapter

TMP47C101P

TMP47C101M

TMP47C201P

TMP47C201M

DIP16

SOP16

DIP16

SOP16

TMP47P201VP

T.B.D.

1024 x 8-bit

2048 x 8-bit

64 x 4-bit

TMP47C990E

+ BM1160 (for DIP)

TMP47P201VP

T.B.D.

128 x 4-bit

Features

• 4-bit single chip microcomputer

• Instruction execution time: 1.3µs (at 6MHz)

• Low voltage operation: 2.2V (at 2MHz RC)

• 89 basic instructions

- Instruction set is the same as TLCS-47 series

• ROM table look-up instructions

• Subroutine nesting: 15 levels max.

• 5 interrupt sources (External: 2, Internal: 3)

- All sources have independent latches each, and multiple

interrupt control is available

• I/O port (11 pins)

• 12-bit Timer/Counters (TC2)

- Timer, event counter, and pulse width measurement

mode

• 12-bit programmable Timer (TC1)

• Interval Timer

• High current outputs

- LED direct drive capability: typ. 20mA x 4 bits (Port R4)

• Hold function

- Battery/Capacitor back-up

• Real Time Emulator: BM4721A + BM1160 (for DIP)

The information contained here is subject to change without notice.

The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties

which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic

equipments (ofﬁce equipment, communication equipment, measuring equipment, domestic electriﬁcation, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-

ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, trafﬁc signal, combustion control, all types

of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.

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Pin Assignment (Top View)

Pin Function

Pin Name

Input/Output

Functions

R43 to R40

4-bit I/O port with latch.

When used as input port, the latch must be set to “1”.

Every bit data is possible to be set, cleared and tested by the bit manipulation

instruction of the L-register indirect addressing.

I/O

R53 to R50

R81 (T2)

2-bit I/O port with latch.

Timer/Counter 2 external input

I/O (Input)

When used as input port, external interrupt pin, or timer/counter

external input pin, the latch must be set to “1”.

R80 (INT2)

External interrupt 2 input

XIN

XOUT

Input

Output

Resonator connecting pins,

For inputting external clock, XIN is used and XOUT is opened.

RESET

HOLD (INT1)

VDD

Input

Reset signal input

I/O (Input)

Hold request/release signal input

External interrupt 1 input and R82 I/O

+5 V

Power Supply

VSS

OV (GND)

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• 2.5 ALU, Accumulator

• 2.6 Flags

Operational Description

Concerning the above component parts, the conﬁguration and

functions of hardwares are described.

• 2.7 System Controller

• 2.8 Interrupt Controller

• 2.9 Reset Circuit

1. System Conﬁguration

Peripheral Hardware Function

Internal CPU Function

• 3.1 I/O Ports

• 3.2 Interval Timer

• 3.3 Timer/Counters (TC1, TC2)

• 2.1 Program Counter (PC)

• 2.2 Program Memory (ROM)

• 2.3 H Register, L Register

• 2.4 Data Memory (RAM)

- Stack

- Stack Pointer Word (SPW)

- Data Counter (DC)

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number of bytes of the instruction every time it is fetched.

When a branch instruction or a subroutine instruction has been

executed or an interrupt has been accepted, the speciﬁed val-

ues listed in Table 2-1 are set to the PC. The PC is initialized to

“0” during reset.

2. Internal CPU Function

2.1 Program Counter (PC)

The program counter is a 11-bit binary counter which indicates

the address of the program memory storing the next instruc-

tion to be executed.Normally, the PC is incremented by the

Figure 2-1. Conﬁguration of Program Counter

The PC can directly address a 2048-byte address space.

However, with the short branch, the following points must be

considered:

dition is satisﬁed, the value speciﬁed in the instruction

is set to the lower 6 bits of the PC.That is, [BSS a]

becomes the in-page branch instruction. When [BSS

a] is stored at the last address of the page, the upper 5

bits of the PC point the next page, so that branch is

made to the next page.

• Short branch instruction [BSS a]

In [BSS a] instruction execution, when the branch con-

Table 2-1 Status Change of Program Counter

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2.2 Program Memory (ROM)

speciﬁed in the data counter (DC) to place them into

the accumulator. [LDL A, @DC] instruction reads the

lower 4 bits of ﬁxed data, and [LDH A, @DC+] instruc-

tion reads the upper 4 bits.

Programs and ﬁxed data are stored in the program memory.

The instruction to be executed next is read from the address

indicated by the contents of the PC.

The fixed data can be read by using the table look-up in-

structions.

The DC is a 12-bit register, allowing it to address the

entire program memory space.

• Table look-up instructions

Example: When [LDL A, @DC] instruction is executed

with the DC value being 7AO being 58 ,

H

“8” is stored in the accumulator; when [LDH

A, @DC+] instruction is executed, “5” is

stored in the accumulator and the DC value

[LDL A, @DC], [LDH A, @DC+]

The table look-up instructions read the lower and

upper 4 bits of the ﬁxed data stored at the address

is incremented to 7A1 .

H

Figure 2-2. Conﬁguration of Program Memory

2.2.1 Program Memory Capacity

The 47C101 has 1024 x 8 bits (addresses 000 through 3FF )

of program memory (mask ROM), the 47C201 has 2048 x 8

2.2.2 Program Memory Map

Figure 2-3 shows the program memory map. Address 000 -

H

086 of the program memory are also used for special pur-

H

bits (addresses 000 through 7FF ).

poses. On the 47C101, no physical program memory exists in

H

the address range 400 through 7FF . However, if this space

H

is accessed by program, the most signiﬁcant bit of each

address is always regarded as “0” and the contents of the pro-

gram memory corresponding to the address is always

regarded as “0” and the contents of the program memory cor-

responding to the address 000 through 3FF are read.

H

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Figure 2-3. Program Memory Map

2.3 H Register and L Register

During the execution of [SET @L], [CLR @L], or [TEST @L]

instructions, the L register is also used to specify the bits cor-

responding to I/O port pins R73 through R40 (the indirect ad-

dressing of port bits by the L register).

The H register and L register are 4-bit general registers. They

are also used as a register pair (HL) for the data memory (RAM)

addressing pointer. The RAM consists of pages, each page

being 16 words long (1 word = 4 bits). The H register speciﬁes

a page and the L register speciﬁes an address in the page.

Example: To Write immediate values “5” and FH” to data

memory addresses 10H and 11H.

The L register has the auto-post-increment/decrement

capability, implementing the execution of composite instruc-

tions. For example, [ST A, @HL+] instruction automatically in-

crements the contents of the L register after data transfer.

LD HL, #10H

;

HL 10

H

RAM [10 5 , LR←LR + 1

RAM [11 ] F , LR←LR + 1

H H

ST

#5,@HL+

#0FH,@HL+ ;

H] H

Figure 2-4. Conﬁguration of H and L Registers

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2.4 Data Memory (RAM)

The 47C101 has 64 x 4 bits (addresses 00 through 3F of

(2)

(3)

Direct addressing mode

H

H)

the data memory (RAM), and the 47C201 has 128 x 4 bits

(addresses 00 through 7F ).

In this mode, an address is directly speciﬁed by the 8

bits of the second byte (operand) in the instruction

ﬁeld.

H

The RAM is addressed in one of the three ways (address-

ing modes):

Example: LD A, 2CH

Zero-page addressing mode

In this mode, an address in zero-page (addresses 00

;

Acc←RAM [2C ]

H

(1)

Register-indirect addressing mode

In this mode, a page is speciﬁed by the H register and

an address in the page by the L register.

H

through 0F ) is speciﬁed by the lower 4 bits of the sec-

H

ond byte (operand) in the instruction ﬁeld.

Example: LD A, @HL

;

Acc←RAM [HL]

Example: ST #3, 05H

;

RAM [05 ]←3

H

Figure 2-5. Addressing Mode

➁ Data Counter (DC)

2.4.1 Data Memory Map

Figure 2-6 shows the data memory map. The data memory is

also used for the following special purpose.

➂Count registers of the timer/counters (TC1, TC2)

➃Zero-page

➀ Stack and Stack Pointer Word (SPW)

Figure 2-6. Data Memory Map (47C201)

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(1)

Stack

usable.If an interrupt is accepted with location 4

already used, the user-processed data stored in

addresses 4C through 4F corresponding to the

location 3 area is lost.)

H

The stack provides the area in which the return

address is saved before a jump is performed to the

processing routine at the execution of a subroutine call

instruction or the acceptance of an interrupt. When a

subroutine call instruction is executed, the contents

(the return address) of the program counter are saved;

when an interrupt is accepted, the contents of the pro-

gram counter and ﬂags are saved.

The SPW is not initialized by hardware, requiring to

write the initial value (the location with which the use of

the stack starts) by using the initialization routine. Nor-

mally, the initial value of “12” is used.

Example:

To initialize the SPW (when the stack is

used from location 12)

When returning from the processing routine, executing

the subroutine return instruction [RET] restores the

contents of the program counter from the stack; exe-

cuting the interrupt return instruction [RETI] restores

the contents of the program counter and ﬂags.

LD

ST

A,#12 ;

A,0FFH

SPW←12

(3)

Data Counter (DC)

The stack consists of up to 15 levels (locations 0

through 14) which are provided in the data memory

The data counter is a 12-bit register to specify the

address of the data table to be referenced in the pro-

gram memory (ROM). Data table reference is per-

formed by the table look-up instructions [LDL A, @DC]

and [LDH A, @DC +]. The data table may be located

anywhere within the program memory address space.

(addresses 40 through 7B ). Each location consists

H

of 4-word data memory. Locations 13 and 14 are

shared with the count registers of the timer/counters

(TC1, TC2) to be described later.

The save/restore locations in the stack are determined

by the stack pointer word (SPW). The SPW is automat-

ically decremented after save, and incremented before

restore.That is, the value of the SPW indicates the

stack location number for the next save.

The DC is assigned with a RAM address in unit of 4

bits. Therefore, the RAM manipulation instruction is

used to set the initial value or read the contents of the

DC.

(2)

Stack Pointer Word (SPW)

Example:

LD

To set the DC to 380

H.

Address 7F (3F for the 47C101) in the data memory

H

HL,#07CH ; Sets RAM address of

is called the stack pointer word, which identiﬁes the

location in the stack to be accessed (save or restore).

DC to HL register pair.

L

ST

#0H,@HL+ ; DC←380H

#8H,@HL+

#3H,@HL+

Generally, location number 0 to 12 can be set to the

SPW, providing up to 13 levels of stack nesting. Loca-

tions 13 and 14 are shared with the timer/counters to

be described later; therefore, when the timer/counters

are not used, the stack area of up to 15 levels is avail-

able. Address 7F is assigned to the SPW, so that the

H

contents of the SPW cannot be set “15” in any case.

The SPW is automatically updated when a subroutine

call is executed or an interrupt is accepted. However, if

it is used in excess of the stack area permitted by the

data memory allocating conﬁguration, the user-pro-

cessed data may be lost.(For example, when the user-

processed data area is in an address range 00

H

through 4F , up to location 4 of the stacks are

H

Figure 2-7. Data Counter

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Figure 2-8. Accessing Stack (Save/Restore) at the 47C201

(4)

Count registers of the timer/counters (TC1, TC2)

stack is usable from location 13 when the timer/

counter 1 is not used. When none of timer/counter 1

and timer/counter 2 are used, the stack is usable from

location 14.

The 47C101/201 has two channels of 12-bit timer/

counters. The count register of the timer/counter is

assigned with a RAM addresses in unit of 4 bits, so

that the initial value is set and the contents are read by

using the RAM manipulation instruction.

When both timer/counter 1 and timer/counter 2 are

used, the data memory locations at addresses 77

H

and 7B (37 and 3B for the 47C101) can be used to

H

store the user-processed data.

The count registers are shared with the stack area

(locations 13 and 14) described earlier, so that the

Figure 2-9. Count Registers of the Timer/Counters (TC1, TC2)

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(5)

Zero-page

The 16 words (at addresses 00 through 0F ) of the

zero page of the data memory can be used as the user

ﬂags or pointers by using zero-page addressing mode

instructions (comparison, addition, transfer, and bit

manipulation), providing enhanced efﬁciency in pro-

gramming.

Example: To write immediate data “8” to address 09 if

H

bit 2 at address 04 in the RAM is “1”.

H

TEST 04H,2

;

Skips if bit 2 at address 04 in

the RAM is “0”.

H

B

ST

SKIP

#8, 09H ;

Writes “8” to address 09 in the

H

RAM

SKIP:

2.4.2 Data Memory Capacity

Figure 2-10. Data Memory Capacity and Address Assignment

When power-on is performed, the contents of the RAM

2.5 ALU and Accumulator

become unpredictable, so that they must be initialized by the

initialization routine.

2.5.1 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations speci-

ﬁed by instructions on 4-bit binary data and outputs the result

of the operation, the carry information(C), and the zero detect

information (z).

Example: To clear RAM (use common to the 47C101 and

47C201)

LD

ST

HL, #00H ; HL←00H

#0, @HL+ ; RAM [HL]←0, LR

SCLRRAM:

(1)

Carry information (C)

LR + 1

B

SCLRRAM

The carry information indicates a carry-out from the

most signiﬁcant bit in an addition. A subtraction is per-

formed as addition of two’s complement, so that, with

a subtraction, the carry information indicates that there

is no borrow to the most signiﬁcant bit. With a rotate

instruction, the information indicates the data to be

shifted out from the accumulator.

ADD H, #1

SCLRRAM

; HR←HR + 1

B

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(2)

Zero detect information (Z)

2.6 Flags

There is a carry ﬂag (CF), a zero ﬂag (ZF), a status ﬂag (SF), and

a general ﬂag (GF), each consisting of 1 bit. These ﬂags are set

or cleared according to the condition speciﬁed by an instruc-

tion. When an interrupt is accepted, the ﬂags are saved on the

stack along with the program counter. When the [RETI]

instruction is executed, the ﬂags are restored from the stack to

the states set before interrupt acceptance.

This information is “1” when the operation result or the

data to be transferred to the accumulator/data mem-

ory is “0000 ”.

B

(1)

Carry ﬂag (CF)

The carry ﬂag holds the carry information received from

the ALU at the execution of an addition/subtraction

with carry instruction, a compare instruction, or a

rotate instruction. With a carry ﬂag test instruction, the

CF holds the value speciﬁed by it.

➀ Addition/subtraction with carry instructions [ADDC A,

@HL], [SUBRC A, @HL]

The CF becomes the input (C ) to the ALU to hold the

carry information.

in

Figure 2-11. ALU

Example: The carry information and zero detect

information for 4-bit additions and subtrac-

tions.

➁ Compare instructions [CMPR A, @HL], [CMPR A, #k]

The CF holds the carry information (non-borrow).

➂ Rotate instructions [ROLC A], [RORC A]

The CF is shifted into the accumulator to hold the car-

ry information (the data shifted out from the accumu-

lator).

Operation

4 + 2 =

7 + 9 =

9 + 9 =

Result

C

0

1

Z

0

1

0

6

0

2

➃ Carry flag test instructions [TESTP CF], [TEST CF]

With [TESTP CF] instruction, the content of the CF is

transferred to the SF then the CF is set to “1”.

With [TEST CF] instruction, the value obtained by in-

verting the content of the CF is transferred to the SF

then the CF is cleared to “0”.

Operation

8 - 1 =

2 - 2 =

Result

C

1

Z

0

1

0

7

0

5 - 8 =

3 (1101 )

0

B

(2)

(3)

Zero ﬂag (ZF)

2.5.2 Accumulator (Acc)

The accumulator is a 4-bit register used to hold source data or

results of the operations and data manipulations.

The zero ﬂag holds the zero detect information (Z)

received from the ALU at the execution of an opera-

tional instruction, a rotate instruction, an input instruc-

tion, or a transfer-to-accumulator instruction.

Status ﬂag (SF)

The status ﬂag provides the branch condition for a

branch instruction. Branch is performed when this ﬂag

is set to “1”. Normally the SF is set to “1”, so that any

branch instruction can be regarded as an uncondi-

tional branch instruction. When a branch instruction is

executed upon set or clear of the SF according to the

condition speciﬁed by an instruction, this instruction

becomes a conditional branch instruction. During

reset, the SF is initialized to “1”, other ﬂags are not

affected.

Figure 2-12. Accumulator

Figure 2-13. Flags

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(4)

General ﬂag (GF)

Example: When the following instruction are exe-

cuted with the accumulator, H register, L

register, data memory (address 07H), and

This is a 1-bit general-purpose ﬂag which can be set,

cleared, or tested by program.

carry ﬂag being set to “C ”, “0”, “7”, “5”,

H

and “1” respectively, the contents of the

accumulator and ﬂags become as follows:

2.7. System Controller

Figure 2-14. Clock Generator and Timing Generator

2.7.1 Clock Generator

pins. (RC oscillation is also possible, depending on the mask

option) The clock from the external oscillator is also available.

In the hold operating mode, the clock generator stops oscillat-

ing.

The clock generator provides the basic clock pulse (CP) by

which the system clock to be supplied to the CPU and the

peripheral hardware is produced. The CP can be easily

obtained by connecting the resonator to the XIN and XOUT

Figure 2-15. Examples of Oscillator Connection

Note: Accurate adjustment of the oscillation frequency.

itoring this pulse. With a system requiring the oscillation frequency

adjustment the adjusting program must be created beforehand.

Although the hardware to externally and directly monitor the CP is

not provided, the oscillation frequency can be adjusted by making

the program to output the pulse with a ﬁxed frequency to the port

with the all interrupts disabled and timer/counters stopped and mon-

Example: To output the oscillation frequency adjusting moni-

tor pulse to port R40.

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2.7.2 Timing Generator

The timing generator consists of a 18-stage binary

counter with a divided-by-16 prescaler. The basic clock (fre-

quency: fc) provides the timing generator. Therefore, the out-

put frequency at the last stage is fc/2 [Hz]. During reset, the

binary counter is cleared to “0”, however, the prescaler is not

cleared.

The timing generator produces the system clocks from basic

clock pulse (CP) which are supplied to the SPU and the

peripheral hardware.

22

Figure 2-16. Conﬁguration of Interval Timer

The timing generator provides the following functions:

2.7.3 Instruction Cycle

The instruction execution and the on-chip peripheral hardware

operations are performed in synchronization with the basic

clock pulse (CP: fx [Hx]). The smallest unit of instruction execu-

tion is called an instruction cycle. The instruction set of the

TLCS-47 series consists of 1-cycle instructions and 2-cycle

instructions. The former requires 1 cycle for their execution;

the latter, 2 cycles. Each instruction cycle consists of 4 states

(S1 through S4). Each state consists of 2 basic clock pulses.

➀ Generation of an internal source clock for interval timer

➁ Generation of an internal source clock for timer/

counters

➂ Generation of a warm-up time for releasing of the hold

operating mode

Figure 2-17. Instruction Cycle

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2.7.4 Hold Operating Mode

states during the hold operation:

The hold feature stops the system and holds the system’s

internal states active before stop with a low power. The hold

operation is controlled by the command register (OP10) and

the HOLD pin input. The HOLD pin input state can be known

by the status register (IPOE). The HOLD pin is wired with the

R82 output latch. To use this port for hold operating mode, the

R82 output latch should be set to “1”.

➀ The oscillator stops and the system’s internal opera-

tions are all held up.

➁ The timing generator is cleared to “0”.

➂ The states of the data memory, registers, and latches

valid immediately before the system is put in the hold

state are all held.

(1)

Starts Hold Operating Mode

➃ The program counter holds the address of the in-

struction to be executed after the instruction ([OUT A,

%OP10] or [OUT @HL, %OP10]) which starts the

hold operating mode.

The hold operating mode consists of the level-sensitive

release mode and the edge-sensitive release mode.

The hold operation is started when the command is

set to the command register and holds the following

Figure 2-18. Hold Operating Mode Command Register/Status Register

a. Level-sensitive release (back-up) mode

➀ Testing HOLD (bit 0 of the status register)

➁ Generating the external interrupt 1 request.

In this mode, the hold operation is released by setting

the HOLD pin to the high level. This mode is used for

the capacitor backup with power off or for the battery

backup for long hours.

Example: To test HOLD to start the hold operation in

the level-sensitive release mode (the warm-

14

up time = 2 /fc).

If the instruction to start the hold operation is executed

with the HOLD pin input being high, the hold operation

does not start but the release sequence (warm-up)

starts immediately. Therefore, to start the hold opera-

tion in the level-sensitive release mode, that the HOLD

pin input being low (the hold operation request) must

be recognized in program. This recognition is per-

formed in one of the two ways below:

SHOLDH:

TEST %IPOE, 0 ; Waits until

HOLD pin input

goes low.

B

SHOLDH

LD

OUT

A, #1101B ; OP10←1101

A, %OP10

B

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Figure 2-19. Level-Sensitive Release Mode

b. Edge-sensitive release (clock) mode

mode, even if the HOLD pin input is high, the hold

operation is performed.

In this mode, the hold operation is released at the ris-

ing edge of the HOLD pin input. This mode is used for

applications in which a relatively short-time program

processing is repeated at a certain cycle. This cyclic

signal (for example, the clock supplied from the low

power dissipation oscillator). In the edge-sensitive

Example: To start the hold operation in the edge-sen-

sitive release mode (the warm-up time =

14

2 /fc).

LD A, #0101B ; OP10←0101

B

OUT A, %OP10

Figure 2-20. Edge-Sensitive Release Mode

Note 1: In the hold operation, the dissipation of the power associated with

the oscillator and the internal hardware is lowered; however, the

power dissipation associated with the pin interface (depending on

the external circuitry and program) is not directly determined by the

hardware operation of the hold feature. This point should be con-

sidered in the system design and the interface circuit design.

(2)

Releases Hold Operating Mode

The hold operating mode is released in the following

sequence:

➀ The oscillator starts

Note 2: In the CMOS circuitry, a current does not ﬂow when the input level

is stable at the power voltage level (V /V ): however, when the

DD SS

input level gets higher than the power voltage level (by approxi-

mately 0.3 to 0.5 V), a current begins to ﬂow. Therefore, if cutting

off the output transistor at an I/O port (the open drain output pin

with an input transistor connected) puts the pin signal into the

high-impedance state, a current ﬂows across the ports input tran-

sistor, requiring to ﬁx the level by pull-up or other means.

➁ Warm-up is performed to acquire the time for stabi-

lizing oscillation. During the warm-up, the internal

operations are all stopped. One of three warm-up

times can be selected by program depending on

the characteristics of the oscillator used.

➂ When the warm-up time has passed, an ordinary

operation restarts from the instruction next to the

instruction which starts the hold operation. At this

time, the interval timer starts from the reset state

“0”.

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The warm-up time is obtained by dividing the basic

level of the RESET pin input gets under the non-

inverted high input voltage of the RESET pin input (the

hysteresis input), a reset operation may happen.

clock by the interval timer, so that, if the frequency at

releasing the hold operation is unstable, the warm-up

time shown in Figure 2-18. includes an error. There-

fore, the warm-up time must be handled as an approx-

imate value. The hold operation is also released by

setting the RESET pin to the low level. In this case, the

normal reset operation follows immediately.

2.8 Interrupt Function

2.8.1 Interrupt Controller

There are 5 interrupt sources (2 external and 3 internal). The

prioritized multiple interrupt capability is supported. The inter-

Note:

To release the hold operation at a low hold voltage, the following

points must be considered:

When the power voltage rises from the hold voltage to the operat-

ing voltage, the RESET pin input is also at the high level and its

voltage rises with the power voltage.

rupt latches (IL through IL ) to hold interrupt requests are pro-

5

0

vided for the interrupt sources. Each interrupt latch is set to “1”

when an interrupt request is made, asking the CPU to accept

the interrupt. The acceptance of interrupt can be permitted or

prohibited by program through the interrupt enable master ﬂip-

ﬂop (EIF) and interrupt enable register (EIR). When two or more

interrupts occur simultaneously, the one with the highest prior-

ity determined by hardware is serviced ﬁrst.

In this case, if a time-constant circuit or the like is

externally attached, the voltage rise of the RESET pin

input occurs after the power voltage rise. If the voltage

Table 2-2. Interrupt Sources

16/32

TOSHIBA CORPORATION

TMP47C101/201

Figure 2-21. Interrupt Controller Block Diagram

(1)

Interrupt enable master ﬂip-ﬂop (EIF)

enabled when the corresponding bit of the EIR is “1”,

and an interrupt is disabled when the corresponding

bit of the EIR is “0”. Bit 1 of the EIR (EIR ) is shared by

both IOVF2 and ITMR interrupts.

1

The EIF controls the enable/disable of all interrupts.

When this ﬂip-ﬂop is cleared to “0”, all interrupts are

disabled; when it is set to “1”, the interrupts are

enabled.

Read/write on the EIR is performed by executing [SCH

a, EIR] instruction. The EIR initialized to “0” during

reset.

When an interrupt is accepted, the EIF is cleared to

“0”, temporarily disabling the acceptance of subse-

quent interrupts.

(3)

Interrupt latch (IL5 through IL0)

When the interrupt service program has been exe-

cuted, the EIF is set to “1” by the execution of the

interrupt return instruction [RETI], being put in the

enabled state again.

An interrupt latch is provided for each interrupt source.

The IL is set to “1” when an interrupt request is made

to ask the CPU for accepting the interrupt. Each IL is

cleared to “0” upon acceptance of the interrupt. It is

initialized to “0” during reset.

Set or clear of the EIF in program is performed by

instruction [EICLR IL, r] and [DICLR IL, R], respectively.

The EIF is initialized to “0” during reset.

The ILS can be cleared independently by interrupt

latch operation instructions ([EICLR IL, r], [DICLR IL, r],

and [CLR IL, r]) to make them cancel interrupt requests

or initialize by program. When the value of instruction

ﬁeld (r) is “0”, the interrupt latch is cleared; when the

value is “1”, the IL is held. Note that the ILs cannot be

set by instruction.

(2)

Interrupt enable register (EIR)

The EIR is a 4-bit register speciﬁes the enable or dis-

able of each interrupt except INT1. An interrupt is

TOSHIBA CORPORATION

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TMP47C101/201

Example 1: To enable IOVF1, INT1, and INT2 interrupts.

The interrupt acknowledge processing consists of the fol-

lowing sequence:

LD

XCH

A,#0101B

A,EIR

; EIR←0101

B

➀ The contents of the program counter and the flags are

saved on the stack.

EICLR IL,111111B ; EIF←1

➁ The interrupt entry address corresponding to the inter-

Example 2: To set the EIF to “1”, and to clear the inter-

rupt latches except ITMR to “0”.

rupt source is set to the program counter.

➂ The status flag is set to “1”.

EICLR IL,000010B ; EIF←1, IL ←0, IL -

0

2

IL ←0

5

➃ The EIF is cleared to “0”, temporarily disabling the ac-

ceptance of subsequent interrupts.

2.8.2 Interrupt Processing

An interrupt request is held until the interrupt is accepted or the

IL is cleared by the reset of the interrupt latch operation

instruction.The interrupt acknowledge processing is performed

in 2 instruction cycles after the end of the current instruction

execution (or after the timer/counter processing if any). The

interrupt service program terminates upon execution of the

interrupt return instruction [RETI].

➄ The interrupt latch for the accepted interrupt source is

cleared to “0”.

➅ The instruction stored at the interrupt entry address is

executed. (Generally, in the program memory space at

the interrupt entry address, the branch instruction to

each interrupt processing program is stored.)

Figure 2-22. Interrupt Timing Chart (Example)

To perform the multi-interrupt, the EIF is set to “1” in the

interrupt service program, and the acceptable interrupt

source is selected by the EIR. However, for the INT1 interrupt,

the interrupt service is disabled under software control be-

cause it is not disabled by the EIR.

PINT1: TEST 05H,0 ; Skips if RAM [05 ] 0

H

is “1”

B

SINT1

RET1

:

SINT1:

Example: The INT1 interrupt service is disabled under

The Interrupt return instruction [RETI] performs the follow-

ing operations:

software control (Bit 0 of RAM [05 ] are as-

H

signed to the disabling switch of interrupt ser-

vice).

➀ Restores the contents of the program counter and the

flags from the stack.

➁ Sets the EIF to “1” to provide the interrupt enable state

again.

18/32

TOSHIBA CORPORATION

TMP47C101/201

In the interrupt processing, the program counter and

flags are automatically saved or restored but the accumulator

and other registers are not. If it is necessary to save or restore

them, it must be performed by program as shown in the fol-

lowing example. To perform the multi-interrupt, the saving

RAM area never be overlapped.

The INT1 interrupt cannot be disabled by the EIR, so that

it is always accepted in the interrupt enable state (EIF=”1”).

Therefore, INT1 is used for an interrupt with high priority such

as an emergency interrupt. When HOLD (INT1) pin is used for

the I/O port, the INT1 interrupt occurs at the falling edge of the

pin input, so that the interrupt return [RET1] instruction must

be stored at the interrupt entry address to perform dummy in-

terrupt processing.

Example: To save and restore the accumulator and HL

register pair.

XCH

HL, GSAV1;

A, GSAV1+2; RAM GSAV1+2

RAM GSAV1

HL

Acc

2.9 Reset Function

When the RESET pin is held to the low level for three or more

instruction cycles when the power voltage is within the operat-

ing voltage range and the oscillation is stable, reset is per-

formed to initialize the internal states.

Note. The lower 2 bits of GSAV1 should be “0’s”.

2.8.3 External Interrupt

When an external interrupt (INT1 or INT2) occurs, the interrupt

latch is set at the falling edge of the corresponding pin input

(INT1 or INT2). The external interrupt input is the hysteresis

type, each of high and low level time requires 2 or more

instruction cycles for a correct interrupt operation.

When the RESET pin input goes high, the reset is cleared

and program execution starts from address 000 . The RESET

H

pin is a hysteresis input with a pull-up resistor (220k typ.). Ex-

ternally attaching a capacitor and a diode implement a simpli-

fied power-on-reset operation

Figure 2-23. Simpliﬁed Power-On-Reset

Table 2-3. Initialization of Internal States by Reset Operation

TOSHIBA CORPORATION

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TMP47C101/201

These ports are assigned with port addresses (00H

through IFH). Each port is selected by specifying its port ad-

dress in an I/O instruction. Table 3-1 lists the port address as-

signments and the I/O instructions that can access the ports.

3. Peripheral Hardware Function

3.1 Ports

The data transfer with the external circuit and the command/

status/data transfer with the internal circuit are performed by

using the I/O instructions (13 kinds). There are 4 types of ports:

3.1.1 I/O Timing

(1)

Input timing

➀ I/O port

;

Data transfer with external cir-

cuit

External data is read from an input port or an I/O port

in the S3 state of the second instruction cycle during

the input instruction (2-cycle instruction) execution.

This timing cannot be recognized from the outside, so

that the transient input such as chattering must be

processed by program.

➁ Command register ; Control of internal circuit

➂Status register

;

Reading the status signal from

internal circuit

➃Data register

;

Data transfer with internal cir-

cuit

Figure 3-1. Input Timing

(2)

Output timing

state of the second instruction cycle during the output

instruction (2-cycle instruction) execution.

Data is output to an output port or an I/O port in the S4

Figure 3-2. Output Timing

➂KE

3.1.2 I/O Ports

;

1-bit sense input (shared with

hold request/release signal in-

put)

The 47C101/201 have 4 I/O ports (11 pins) each as follows:

➀ R4, R5

➁ R8

;

4-bit input/output

Each output port contains a latch, which holds the out-

put data. The input ports have no latch; therefore, it is

desired to hold data externally until it is read or read

twice or more before processing it.

2-bit input/output (shared with

external interrupt input and

timer/counter input)

20/32

TOSHIBA CORPORATION

TMP47C101/201

Table 3-1. Port Address Assignments and Available I/O Instructions

TOSHIBA CORPORATION

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TMP47C101/201

(1)

Ports R4 (R43 to R40), R5 (R53 to 50)

and [TEST @L]). Table 3-1 lists the pins (I/O ports) that

correspond to the contents of L register.

These ports are 4-bit I/O ports with a latch. When used

as an input port, the latch must be set to “1”. The latch

is initialized to “1” during reset. Port R4 can directly

drive LEDs.

Example: To clear R43 output as specified by the L

register indirect addressing bit manipulation

instruction.

LD L, #00011B ; Sets R43 pin address to L

register

These 2 ports (8 pins) can be set, cleared, and tested

for each bit as speciﬁed by L register indirect address-

ing bit manipulation instructions ([SET @L], [CLR @L],

CLR @L

; R43 0

Table 3-2. Relationship Between L Register Contents and I/O Port Bits.

Figure 3-3. Ports R4, R5

(2)

Port R8 (R81 to R80) and Port KE

Port KE (KEO) is a 1-bit sense input port shared with

the hold request/release signal input in (HOLD). This

input port is assigned to the least signiﬁcant bit of port

address IPOE and is processed as the data with

inverted polarity. For example, if an input instruction is

executed with the pin on the high level, ”0” is read. The

bit1 to bit3 of port KE, and undeﬁned value is read

when an input instruction is executed.

Port R8 is a 2-bit I/O port with a latch.When used as

an input port, the latch must be set to “1”. The latch is

initialized to “1” during reset.

Port R8 is shared with the external interrupt input pin

and the timer/counter input pin. To use this port for

one of these functional pins, the latch should be set to

“1”. To us it for an ordinary I/O port, the acceptance of

external interrupt should be disabled or the event

counter/pulse width measurement modes of the timer/

counter should be disabled.

Note:

When HOLD (INT1) pin is used for an I/O port, external interrupt 1

occurs upon detection of the falling edge of pin input, and if the

interrupt enable master ﬂip-ﬂop is enabled, the interrupt request is

always accepted. So that a dummy interrupt processing must be

performed (only the interrupt return instruction [RETI] is executed).

With R80 (INT2) pin, external interrupt 2 occurs like HOLD (INT1)

R82, R83 pins do not exist actually but R82, R83 has

the latch. And R82 is wired to HOLD (INT1) pin, inter-

nally.

in but bit 0 of the interrupt enable register (EIR ) is only kept at

0

“0”not accepting the interrupt request.

22/32

TOSHIBA CORPORATION

TMP47C101/201

Figure 3-4. Port R8 and HOLD (INT1) Pin

3.2 Interval Timer

may occur earlier than the preset interrupt period.

The interval timer can be used to generate an interrupt with a

ﬁxed frequency. For an interval timer interrupt (ITMR), one of 4

frequencies can be selected by command. The command reg-

ister (OP19) is initialized to “0” during reset. An interval timer

interrupt is generated at the ﬁrst rising edge of the binary

counters output after the command has been set. The interval

timer is not cleared by command, so that the ﬁrst interrupt

Example: To set the interval timer interrupt frequency to

12

fc/2 [Hz].

LD

OUT

A,

#0110B

%OP19

Figure 3-5. Command Register

TOSHIBA CORPORATION

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TMP47C101/201

3.3 Timer/Counters (TC1,TC2)

through the RAM manipulation instruction. When the timer/

counter is not used, the mode selection may be set to

“stopped” to use the RAM at the address corresponding to the

timer/counter for storing the ordinary user-processed data.

The 47C101/201 contain two 12-bit timer/counters (TC1,

TC2). RAM addresses are assigned to the count register in unit

of 4 bits, permitting the initial value setting and counter reading

Figure 3-16. Count Registers of the Timer/Counters (TC1, TC2)

3.3.1 Functions of Timer/Counters

3.3.2 Control of Timer/Counters

The timer/counters provide the following functions:

The timer/counters are controlled by the command registers.

The command register is accessed as port address OP1C for

TC1 and port address OP1D for TC2. These registers are ini-

tialized to “0” during reset.

➀ Event counter

➁ Programmable timer

➂ Pulse width measurement

Figure 3-7. Timer/Counter Control Command Registers

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TOSHIBA CORPORATION

TMP47C101/201

The timer/counter increments at the rising edge of each

count pulse. Counting starts with the first rising edge of the

count pulse generated after the command has been set.

Count operation is performed in one instruction cycle after the

current instruction execution, during which the execution of a

next instruction and the acceptance of an interrupt are de-

layed. If counting is requested by both TC1 and TC2 simulta-

neously, the request by TC1 is preferred. The request by TC2

is accepted in the next instruction cycle. Therefore, during

count operation, the apparent instruction execution speed

drops as counting occurs more frequently.

The timer/counter causes an interrupt upon occurrence of an

overﬂow (a transition of the count value from FFF to 000 ). If

the timer/counter is in the interrupt enabled state and the over-

ﬂow interrupt is accepted immediately after its occurrence, the

interrupt is processed in the sequence shown in Figure 3-8.

Note that counting continues if there is a count request after

overﬂow occurrence.

H

Figure 3-8. Timer/Counter Overﬂow Interrupt Timing

(1)

Event counter mode

cycles. For example, the instruction execution speed

of 2µs drops to 2.66µs

In the event counter mode, the timer/counter incre-

ments at each rising edge of the external pin (T2) input.

The maximum applied frequency of the external pin

input is fc/32. The apparent instruction execution

speed drops most to (1/3) x 100 = 33% when TC2 is

operated at the maximum applied frequency because

the count operation is inserted once every 4 instruction

Example: To operate TC2 in the event counter mode.

LD

A, #0100B ; OP1D←01**

A, %0P1D

B

OUT

Figure 3-9. Event Counter Timing Chart

interval.

(2)

Timer mode

10

When an internal pulse rate of fc/2 is used, a count

operation is inserted once every 128 instruction cycles,

so that the apparent instruction execution speed drops

by (1/127) x 100 = 0.8%. For example, the instruction

execution speed of 2µs drops to 2.016µs.

In the timer mode, the timer/counter increments at the

rising edge of the internal pulse generated from the

timing generator. One of 4 internal pulse rates can be

selected by the command register. The selected rate

can be initially set to the timer/counter to generate an

overﬂow interrupt in order to create a desired time

TOSHIBA CORPORATION

25/32

TMP47C101/201

Example: To generate an overﬂow interrupt (at fc =

4MHz) by the TC1 after 100ms.

Calculating the preset value of the count register

The preset value of the count register is obtained from

the following relation

LD

HL, #0F4H

;

TC1←E79 (set-

ting of the count

register)

H

12

2

- (interrupt setting time) x (internal pulse rate)

ST

#9, @HL+

ST

LD

OUT

LD

#7, @HL+

For example, to generate an overﬂow interrupt after

100ms at fc = 4MHz with the internal pulse rate of fc/

2 , set the following value to the count register as the

#0EH, @HL+

A, #1000B

A, %OP1C

A, #0100B

:

;

OP1C←1000

B

10

preset value:

EIR←0100

B

(enables interrupt)

12

-3

10

A

EIR

2

- (100 x 10 ) x (4 x 106/2 ) = 3705 = E79

H

EICLR IL, 110111B ; EIF←1, IL ←0

3

Table 3-3. Internal Pulse Rate Selection

Example: At fc = 4.194304MHz

Internal Pulse Rate

Max. Setting Time

Internal Pulse Rate

Max. Setting Time

10

22

fc/2 [Hz]

2 /fc [s]

4096 [Hz]

1 [s]

16

14

26

fc/2

2

256

16

1

18

30

fc/2

2

256

22

34

fc/2

2

4096

(3)

Pulse width measurement mode

only while the external pin input is high. The maximum

applied frequency to the external pin input must be

one that is enough for analyzing the count value. Nor-

mally, a frequency sufﬁciently slower than the internal

pulse rate setting is applied to the external pin.

In the pulse width measurement mode, the timer/

counter increments with the pulse obtained by sam-

pling the external pins (T2) by the internal pulse. As

shown in Figure 3-11, the timer/counter increments

Figure 3-11. Pulse Width Measurement Mode Timing Chart

26/32

TOSHIBA CORPORATION

TMP47C101/201

The input/output circuitries of the 47C101/201 control

pins are shown below, any one of the circuitries can be

chosen by a code (FA, FB, FD or FE) as a mask option.

Input/Output Circuitry

(1)

Control pins

(2)

I/O Ports

TOSHIBA CORPORATION

27/32

TMP47C101/201

Electrical Characteristics

Absolute Maximum Ratings (V = 0V)

SS

Parameter

Symbol

Pins

Rating

Unit

Supply Voltage

Input Voltage

Output Voltage

V

-0.3 to 6.5

V

DD

V

-0.3 to V + 0.3

DD

IN

V

-0.3 to V + 0.3

OUT1

OUT2

DD

I

Port R4

30

3.2

Output Current (Per 1 pin)

Output Current (Total)

mA

mW

Ports R5, R8, HOLD

Port R4

∑I

120

OUT1

DIP

600

Power Dissipation [T = 70°C]

PD

opr

SOP

600

Soldering Temperature (time)

Storage Temperature

T

260 (10s)

-55 to 125

-30 to 70

°C

sld

T

stg

Operating Temperature

T

opr

Recommended Operating Conditions (V = 0V, T

= -430 to 70°C)

SS

opr

Parameter

Symbol

Pins

Normal mode

Conditions

Min.

Max.

Unit

fc = 6.0MHz

fc = 4.2MHz

fc = 2.5MHz

–

4.5

2.7

Crystar or ceramic

Supply Voltage

V_DD

5.5

V

RC

–

2.2

HOLD mode

Except Hysteresis Input

2.0

V_IH1

V_IH2

V_IH3

V_IL1

V_IL2

V_IL3

V_DDx 0.7

V_DDx 0.75

V_DDx 0.9

In the normal operating area

Input High Voltage

Hysteresis Input

V_DD

V

In the HOLD mode

Except Hysteresis Input

Hysteresis Input

V_DDx 0.3

V_DDx 0.25

V_DDx 0.1

6.0

In the normal operating area

Input Low Voltage

Clock Frequency

0

In the HOLD mode

V

= 4.5 to 5.5V

DD

fc

XIN, XOUT

0.4

MHz

= 2.7 to 5.5V

4.2

= 2.2 to 5.5V (RC)

2.5

28/32

TOSHIBA CORPORATION

TMP47C101/201

DC Characteristics (V = 0V, T = -30 to 70°C)

SS

opr

Parameter

Hysteresis Voltage

Symbol

V_HS

Pins

Hysteresis Input

Conditions

Min.

typ.

Max.

Unit

–

0.7

–

V

I

RESET, HOLD

IN1

IN2

Input Current

V

= 5.5V, V = 5.5V/0V

–

±2

µA

DD

IN

Open drain output ports

RESET

Input Resistance

R

100

–

220

–

450

-2

2

kΩ

mA

µA

IN

Input Low Current

Output Leakage Current

I

Push-pull output ports

Open drain output ports

V

= 5.5V, V = 0.4V

IL

DD IN

I

V

= 5.5V, V = 5.5V

–

LO

DD

OUT

V

_DD= 4.5V, I_OH= -200µA

2.4

2.0

–

Output High Voltage

V_OH

V_OL

Push-pull output ports

V

= 2.2V, I = -5µA

–

DD

OH

_DD= 4.5, I_OL= 1.6mA

= 2.2V, I = 20µA

–

0.4

0.1

–

Except XOUT and port R4

Port R4

Output Low Voltage

Output Low Current

V

–

DD

OL

I

V_DD= 4.5V, V_OL= 1.0V

–

20

mA

OL1

V_DD= 5.5V, fc = 4MHz

–

2

4

Supply Current

(in the Normal operating mode)

I

mA

DD

V

= 5.5V, fc = 4MHz

= 3.0V, fc = 400kHz

–

1

2

DD

0.5

–1

DD

Supply Current

(in the HOLD operating mode)

I

V

= 5.5V

–

0.5

10

µA

DDH

DD

Note 1. Typ. values show those at T = 25 °C, V = 5V.

opr

DD

Note 2. Input Current I ; The current through resistor is not included.

IN1

IN

Note 3. Supply Current V = 5.3 V/0.2V (V = 5.5V) or 2.8V/0.2V (V = 3.0V)

DD

AC Characteristics (V = 0V, T = -30 to 70°C)

SS

opr

Parameter

Instruction Cycle Time

Symbol

t_cy

Conditions

Min.

Typ.

Max.

Unit

V

= 4.5 to 5.5V

= 2.7 to 5.5V

= 2.2 to 5.5V

≥ 2.7V

1.3

1.9

3.2

80

DD

–

20

µs

High Level Clock Pulse Width

Low Level Clock Pulse Width

t_WCH

For external clock

operation

< 2.7V

160

80

–

ns

≥ 2.7V

t

WCL

< 2.7V

160

TOSHIBA CORPORATION

29/32

TMP47C101/201

Recommended Oscillating Conditions (V = 0V, V = 2.7 to 5.5V, T = -30 to 70°C)

SS

DD

opr

(1)

6MHz

Ceramic Resonator

CSA6.00MGU (MURATA)

KBR-6.00MS (KYOCERA)

EFOEC6004A4 (NATIONAL)

C

= C

= 30 pF

XIN

XOUT

(2)

4MHz

Ceramic Resonator

CSA4.00MG (MURATA)

KBR-4.00MS (KYOCERA)

EFOEC4004A4 (NATIONAL)

C

= C

= 30 pF

XIN

XOUT

Crystal Oscillator

204B-6F 4.0000 (TOYOCOM) C = C

= 20pF

XIN

XOUT

(3)

(4)

400kHz

Ceramic Resonator

CSB400B (MURATA)

KBR-400B (KYOCERA)

EFOA400K04B (NATIONAL) C = C

C

= C

= 220pF, R

= 6.8kΩ

XIN

XOUT

CXIN = CXOUT = 100pF, R

= 10kΩ

XOUT

= 470pF, R

= 0Ω

XIN

XOUT

RC Oscillation (V = 0V, V = 5.0V, Topr = 25°C)

SS

DD

2MHz (Typ.)

400kHz (Typ.)

C

= 33pF, R = 10kΩ

X

= 100pF, R = 30kΩ

X

XIN

30/32

TOSHIBA CORPORATION

TMP47C101/201

Typical Characteristics

TOSHIBA CORPORATION

31/32

TMP47C101/201

Notes

32/32

TOSHIBA CORPORATION

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP, SOP16,.3
针数：	16	Reach Compliance Code：	unknown
HTS代码：	8542.31.00.01	风险等级：	5.9
Is Samacsys：	N	具有ADC：	NO
其他特性：	OPERATES AT 2.2V MIN SUPPLY @ 6 MHZ	地址总线宽度：
位大小：	4	CPU系列：	TLCS-47E
最大时钟频率：	6 MHz	DAC 通道：	NO
DMA 通道：	NO	外部数据总线宽度：
JESD-30 代码：	R-PDSO-G16	长度：	10.3 mm
I/O 线路数量：	11	端子数量：	16
最高工作温度：	70 °C	最低工作温度：	-30 °C
PWM 通道：	NO	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.3
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2/5.5 V
认证状态：	Not Qualified	RAM（字节）：	64
ROM（单词）：	2048	ROM可编程性：	MROM
座面最大高度：	1.9 mm	速度：	6 MHz
子类别：	Microcontrollers	最大压摆率：	4 mA
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5.3 mm	uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

型号	制造商	描述	价格	文档
TMP47C201MG	TOSHIBA	Document Change Notification	获取价格
TMP47C201MX	TOSHIBA	IC 4-BIT, MROM, MICROCONTROLLER, PDSO16, 0.300 INCH, 1.27 MM PITCH, PLASTIC, SOP-16, Microcontroller	获取价格
TMP47C201P	TOSHIBA	CMOS 4-bit Microcontroller	获取价格
TMP47C201PG	TOSHIBA	Document Change Notification	获取价格
TMP47C201VP	TOSHIBA	CMOS 4-bit Microcontroller	获取价格
TMP47C202M	TOSHIBA	CMOS 4-BIT MICROCONTROLLER	获取价格
TMP47C202MG	TOSHIBA	TOSHIBA Original CMOS 4-Bit Microcontroller	获取价格
TMP47C202P	TOSHIBA	CMOS 4-BIT MICROCONTROLLER	获取价格
TMP47C202PG	TOSHIBA	TOSHIBA Original CMOS 4-Bit Microcontroller	获取价格
TMP47C203M	TOSHIBA	CMOS 4-BIT MICROCON	获取价格

TMP47C201M

TMP47C201M 概述

TMP47C201M 规格参数

TMP47C201M 数据手册

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