TMP88CP38BNG_技术文档

TMP88CS38B/CM38B/CP38B

CMOS 8-Bit Microcontroller

TMP88CS38BNG/FG, TMP88CM38BNG/FG, TMP88CP38BNG/FG

The TMP88CS38B/CM38B/CP38B is the high speed and high performance 8-bit single chip

microcomputers. This MCU contain CPU core, ROM, RAM, input/output ports, four Multi-function

timer/counters, serial bus interface, on-screen display, PWM output, 8-bit AD converter, and

remote control signal preprocessor on chip.

Product No.

ROM

RAM

Package

OTP MCU

TMP88CS38BNG/FG

TMP88CM38BNG/FG

TMP88CP38BNG/FG

64 K × 8 bits

32 K × 8 bits

48 K × 8 bits

2 K × 8 bits

SDIP42-P-600-1.78

TMP88PS38BNG/FG

P-QFP44-1414-0.80K

1.5 K × 8 bits

Features

♦

8-bit single chip microcomputer TLCS-870/X series

Instruction execution time: 0.25 μs (at 16 MHz)

842 basic instructions

•

Multiplication and division (8 bits × 8 bits, 16 bits × 8 bits, 16 bits/8 bits)

Bit manipulations (Set/clear/complement/move/test/exclusive or)

16-bit data and 20-bit data operations

1-byte jump/subroutine call (Short relative jump/vector call)

RESTRICTIONS ON PRODUCT USE

20070701-EN

• The information contained herein is subject to change without notice.

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical

stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety

in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such

TOSHIBA products could cause loss of human life, bodily injury or damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as

set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and

conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability

Handbook” etc.

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer,

personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These

TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high

quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury

(“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship

instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical

instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall

be made at the customer’s own risk.

• The products described in this document shall not be used or embedded to any downstream products of which

manufacture, use and/or sale are prohibited under any applicable laws and regulations.

• The information contained herein is presented only as a guide for the applications of our products. No responsibility

is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its

use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third

parties.

• Please contact your sales representative for product-by-product details in this document regarding RoHS

compatibility. Please use these products in this document in compliance with all applicable laws and regulations that

regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring

as a result of noncompliance with applicable laws and regulations.

2007-09-12

88CS38B-1

TMP88CS38B/CM38B/CP38B

♦

I/O ports: Maximum 33 (High current output: 4)

17 interrupt sources: External 6, internal 11

•

All sources have independent latches each, and nested interrupt control is available.

Edge-selectable external interrupts with noise reject

High-speed task switching by register bank changeover

♦

ROM corrective function

Two 16-bit timer/counters: TC1, TC2

•

Timer, event counter, pulse width measurement, external trigger timer, window modes

Two 8-bit timer/counters: TC3, TC4

Timer, event counter, capture (Pulse width/duty measurement) mode

♦

•

♦

Time base timer (Interrupt frequency: 0.95 Hz to 31250 Hz)

Watchdog timer

•

Interrupt source/reset output

Serial bus interface

I²C bus, 8-bit SIO mode (Selectable two I/O channels)

On-screen display circuit

♦

•

Font ROM characters: 384 characters

Characters display: 32 columns × 12 lines

Composition: 16 × 18 dots

Size of character: 3 kinds (Line by line)

Color of character: 8 or 15 kinds (Character by character)

Variable display position: Horizontal 256 steps, Vertical 512 steps

Fringing, smoothing, slant, underline, blinking function

♦

Jitter elimination

Data slicer circuit 1 channel

DA conversion (Pulse width modulation) outputs

•

14- or 12-bit resolution (2 channels)

12-bit resolution (2 channels)

7-bit resolution (6 channels)

♦

8-bit successive approximate type AD converter with sample and hold

Remote control signal preprocessor

Two power saving operating modes

•

STOP mode: Oscillation stops. Battery/capacitor back up. Port output hold/high

impedance.

•

IDLE mode: CPU stops, and peripherals operate using high-frequency clock. Release by

interrupts.

♦

Operating Voltage: 4.5 to 5.5 V at 16 MHz

Emulation POD: BM88CS38N0A-M15

2007-09-12

88CS38B-2

TMP88CS38B/CM38B/CP38B

Pin Assignments

Package

SDIP42-P-600-1.78

VSS

( PWM0 ) P40

( PWM1) P41

( PWM2 ) P42

( PWM3 ) P43

( PWM4 ) P44

( PWM5 ) P45

( PWM6 ) P46

( PWM7 ) P47

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

VDD

P33 (TC4/VIN0)

P32 (VIN1/CSIN)

VVSS

P35 (SDA0)

P34 (SCL0)

P31 (INT4/TC3)

P30 (INT3/RXIN)

P20 ( INT5 / STOP )

RESET

(TC2/ INT0 / PWM8 ) P50

(SI1/SCL1/ PWM9 ) P51

(SO1/SDA1) P52

XOUT

XIN

TEST

OSC2

OSC1

P71 ( VD )

TMP88CS38BNG

TMP88CP38BNG

TMP88CM38BNG

TMP88PS38BNG

( KWU0 / SCK1 /INT2/TC1/AIN0) P53

( KWU1 /AIN1) P54

( KWU2 /AIN2) P55

( KWU3 /AIN3) P56

( KWU4 /Y/BLIN/AIN4) P60

( KWU5 /BIN/AIN5) P61

(GIN/CSOUT) P62

P70 ( HD )

P67 (Y/BL)

P66 (B)

P65 (G)

P64 (R)

(RIN) P63

(I) P57

Package

P-QFP44-1414-0.80K

TMP88CS38BFG

TMP88CP38BFG

TMP88CM38BFG

TMP88PS38BFG

(SDA0) P35

VVSS

(VIN1/CSIN) P32

(TC4/VIN0) P33

N.C.

34

35

36

37

38

39

40

41

42

43

44

22

21

20

19

18

17

16

15

14

13

12

P70 ( HD )

P67 (Y/BL)

P66 (B)

P65 (G)

P64 (R)

VDD

VSS

N.C.

P57

P63 (RIN)

P62 (GIN/CSOUT)

P61 (BIN//AIN5/ KWU5 )

( PWM0 ) P40

( PWM1) P41

( PWM2 ) P42

( PWM3 ) P43

P60 (Y/BLIN/AIN4/ KWU4 )

2007-09-12

88CS38B-3

TMP88CS38B/CM38B/CP38B

Pin Functions (1/2)

Pin Name

I/O

Function

1-bit input/output port with latch. When

used as an input port, the latch must be

set to “1”.

External interrupt input 5 or STOP

mode release signal input

P20 ( INT5 / STOP )

I/O (Input)

P35 (SDA0)

P34 (SCL0)

I/O (Input/Output)

6-bit programmable input/output port.

Each bit of these ports can be

individually configured as an input or

an output under software control.

During reset, all bits are configured as

inputs. When used as a serial bus

interface input/output, the latch must

be set to “1”.

I²C bus serial data input/output 0

I²C bus serial clock input/output 0

Timer counter input 4 or video signal

Input 0

P33 (TC4/VIN0)

P32 (VIN1/CSIN)

P31 (INT4/TC3)

P30 (INT3/RXIN)

I/O (Input)

Video signal input 1 or composite sync

input

External interrupt input 4 or timer

counter input 3

External interrupt input 3 or remote

control signal preprocessor input

P47 ( PWM7 )

P46 ( PWM6 )

P45 ( PWM5 )

P44 ( PWM4 )

P43 ( PWM3 )

P42 ( PWM2 )

P41 ( PWM1 )

P40 ( PWM0 )

P57 (I)

I/O (Output)

I/O (Input)

8-bit programmable input/output port.

Each bit of these ports can be

7-bit DA conversion (PWM) outputs

individually configured as an input or

an output under software control.

During reset, all bits are configured as

inputs. When used as a PWM output,

the latch must be set to “1”.

12-bit DA conversion (PWM) outputs

14/12-bit DA conversion (PWM)

outputs

8-bit programmable input/output port.

Each bit of these ports can be

Translucent signal output

P56 ( KWU3 /AIN3)

P55 ( KWU2 /AIN2)

P54 ( KWU1 /AIN1)

individually configured as an input or

an output under software control.

During reset, all bits are configured as

inputs. When used as a PWM output, a

serial bus interface input/output, the

latch must be set to “1”.

Key-on wakeup inputs or AD converter

analog inputs

I/O (Input)

Key-on wakeup input or AD converter

analog input or timer counter input 1 or

external interrupt input 2 or SIO serial

clock input/output 1

I/O

P53 ( KWU0 /AIN0/TC1

/INT2/ SCK1)

(Input /Input/Input

/Input/Output)

I/O

I²C bus serial data input/output 1 or

SIO serial data output 1

P52 (SDA1/SO1)

(Input/Output /Output)

7-bit DA conversion (PWM) output or

I²C bus serial data input/output 1 or

SIO serial data input 1

I/O (Output/Input/Output

/Input)

P51 ( PWM9 /SCL1/SI1)

P50 ( PWM8 /TC2/ INT0 )

7-bit DA conversion (PWM) output or

timer counter input 2 or external

interrupt input 0

I/O

(Output/Input /Input)

P67 (Y/BL)

P66 (B)

I/O (Output)

I/O (Input)

8-bit programmable input/output port.

(P67 to P64: Tri-State, P63 to P60:

High current output) Each bit of these

ports can be individually configured as

an input or an output under software

control. During reset, all bits are

configured as inputs. When used P64

to P67 as port, each bit of the P6 port

data selection register (Bit7 to 4 in

ORP6S) must be set to “1”.

Y or BL output

R/G/B outputs

P65 (G)

P64 (R)

P63 (RIN)

P62 (GIN/CSOUT)

R input

I/O (Input/Output)

G input or TEST video signal output

Key-on wakeup input 5 or B input or AD

converter analog input 5

P61 ( KWU5 /BIN/AIN5)

I/O (Input)

P60

Key-on wakeup input 4 or Y/BL input or

AD converter analog input 4

( KWU4 /YBLIN/AIN4)

2007-09-12

88CS38B-4

TMP88CS38B/CM38B/CP38B

Pin Functions (2/2)

Pin Name

I/O

Function

2-bit programmable input/output port.

Each bit of these ports can be

individually configured as an input or

an output under software control.

During reset, all bits are configured as

inputs.

P71 ( VD )

P70 ( HD )

I/O (Input)

Vertical synchronous signal input

Horizontal synchronous signal input

I/O (Input)

Resonator connecting pins. For inputting external clock, XIN is used and XOUT

is opened.

XIN, XOUT

RESET

Input, Output

I/O

Reset signal input or watchdog timer output/address-trap-reset

output/system-clock-reset output

TEST

Input

Test pin for out-going test. Be tied to low.

Resonator connecting pins for on-screen display circuitry

+5 V, 0 V (GND)

OSC1, OSC2

VDD, VSS, VVSS

Input, Output

Power supply

2007-09-12

88CS38B-5

TMP88CS38B/CM38B/CP38B

Block Diagram

I/O ports

P64 to P67 P70, P71 P57

R, G, B,

Y/BL

VD

OSC connecting

pins for on-screen

display

Display

memory

Character

ROM

Jitter

elimination

HD

OSC1

OSC2

On-screen display circuit

P6

P7

P5

Power

supply

VDD

VSS

VVSS

TLCS-870/X

CPU core

Data memory

(RAM)

Data slicer

ROM corrective circuit

Program counter

Reset I/O test pin

RESET

Interrupt Controller

System controller

TEST

Standby controller

Timing generator

Program memory

(ROM)

Resonator

connecting pins

Time base

timer

16-bit

timer

8-bit

timer/counter

XIN

XOUT

High

Clock

TC1 TC2

TC3 TC4

Watchdog

timer

frequency generator

Inst. register

Inst. decoder

DA converter

P2 P4

8-bit

AD

Key-on

wakeup

Video signal

output

Remote

control signal

Serial bus

interface

P5

P6

P3

Y/BLIN

(PWM)

RIN

GIN

BIN

P32

P33

P20 P40 to P47

P50 to P56

P60 to P63

P30 to P35

Video

signal

I/O ports

2007-09-12

88CS38B-6

TMP88CS38B/CM38B/CP38B

Operational Description

1. CPU Core Functions

The CPU core consists of a CPU, a system clock controller, and an interrupt controller.

This section provides a description of the CPU core, the program memory, the data memory, the

external memory interface, and the reset circuit.

1.1 Memory Address Map

The TMP88CS38B/CM38B/CP38B memory consists of four blocks: ROM, RAM, SFR (Special

function register), and DBR (Data buffer register). They are all mapped to a 1-Mbyte address

space. Figure 1.1.1 shows the TMP88CS38B/CM38B/CP38B memory address map. There are

16 banks of the general-purpose register. The register banks are also assigned to the RAM

address space.

00000H

SFR

64 bytes

0003FH

00040H

0003FH

00040H

0003FH

00040H

General-purpose

register banks

(8 registers × 16 banks)

128 bytes

000BFH

000C0H

000BFH

000C0H

000BFH

000C0H

RAM

1536 bytes

2048 bytes

128 bytes

1536 bytes

128 bytes

006BFH

00F80H

006BFH

00F80H

008BFH

00F80H

128 bytes

DBR

00FFFH

04000H

00FFFH

04000H

00FFFH

04000H

32512 bytes

program area

48896 bytes

program area

65280 bytes

program area

0BEFFH

0FEFFH

20000H

13EFFH

20000H

24576 bytes

OSD font area

ROM

25FFFH

FFF00H

25FFFH

FFF00H

25FFFH

FFF00H

Vector table for

interrupts

64 bytes

128 bytes

64 bytes

128 bytes

64 bytes

128 bytes

FFF3FH

FFF40H

FFF3FH

FFF40H

FFF3FH

FFF40H

Vector table for vector

call instruction

FFF7FH

FFF80H

FFF7FH

FFF80H

FFF7FH

FFF80H

Vector table for

interrupts

FFFFFH

TMP88CS38B

TMP88CP38B

TMP88CM38B

ROM: Read only memory includes

Program memory, Character data memory for OSD

RAM: Random access memory includes

Data memory, Stack, General-purpose register banks

SFR: Special function register includes

I/O ports, Peripheral hardware control registers, Peripheral hardware status registers,

System control registers, Interrupt control registers, Program status word

DBR: Data buffer register includes

Control resister for on-screen display(OSD)

Remote-control-receive control/status resigsters, ROM correction control registers,

Test video signal control registers

Figure 1.1.1 Memory Address Map

2007-09-12

88CS38B-7

TMP88CS38B/CM38B/CP38B

1.2 Program Memory (ROM)

The TMP88CS38B contains a 64-Kbyte program memory (Mask ROM) at addresses from

04000H to 13EFFH and FFF00H to FFFFFH.

The TMP88CM38B contains a 32-Kbyte program memory (Mask ROM) at address from

04000H to 0BEFFH and FFF00H to FFFFFH. The TMP88CP38B contains a 48-Kbyte program

memory (Mask ROM) at address from 04000H to 0FEFFH and FFF00H to FFFFFH.

Addresses FFF00H through FFFFFH in the program memory are also used for a particular

purpose.

1.3 Data Memory (RAM)

The TMP88CS38B has a 2-Kbyte data memory (Static RAM) address from 0040H to 08BFH.

The TMP88CM38B/CP38B has a 1.5-Kbyte data memory (Static RAM) address from 0040H

to 06BFH.

The first 128 bytes (Addresses 00040H through 000BFH) in the built-in RAM are also

available as general-purpose register banks.

The general-purpose registers are mapped in the RAM; therefore, do not clear RAM at the

current bank addresses.

Example: Clears RAM to “00H” except the bank0 (TMP88CS38B/CM38B/CP38B):

LD

HL, 0048H

A, H

BC, 0877H

;

Sets start address to HL register pair

Sets initial data (00H) to A register

Sets number of byte to BC register pair

SRAMCLR: LD

(HL+), A

DEC BC

JRS

F, SRAMCLR

Note: The data memory contents become unstable when the power supply is turned on; therefore,

the data memory should be initialized by an initialization routine. Note that the

general-purpose registers are mapped in the RAM; therefore, do not clear RAM at the

current bank addresses.

1.4 System Clock Controller

The system clock controller consists of a clock generator, a timing generator, and a standby

controller.

Timing generator control register

TBTCR

Clock

generator

00036H

XIN

fc

High-frequency

clock oscillator

Timing

generator

Standby controller

00039H

XOUT

00038H

SYSCR1

System control registers

System clocks

SYSCR2

Clock generator control

Figure 1.4.1 System Clock Controller

2007-09-12

88CS38B-8

TMP88CS38B/CM38B/CP38B

1.4.1

Clock Generator

The clock generator generates the basic clock which provides the system clocks supplied

to the CPU core and peripheral hardware. It contains oscillation circuit: one for the

high-frequency clock.

The high-frequency (fc) clock can be easily obtained by connecting a resonator between

the XIN/XOUT pin, respectively. Clock input from an external oscillator is also possible. In

this case, external clock is applied to the XIN/XTIN pin not connected. The

TMP88CS38B/CM38B/CP38B is not provided an LC oscillation.

High-frequency clock

XIN

XOUT

XIN

XOUT

(Open)

(a) Crystal/Ceramic

resonator

(b) External oscillator

Figure 1.4.2 Examples of Resonator Connection

Note: Accurate adjustment of the oscillation frequency:

Although hardware to externally and directly monitor the basic clock pulse is not

provided, the oscillation frequency can be adjusted by making the program to output

fixed frequency pulses to the port while disabling all interrupts and monitoring this pulse.

With a system requiring adjustment of the oscillation frequency, the adjusting program

must be created beforehand.

1.4.2

Timing Generator

The timing generator generates from the basic clock the various system clocks supplied

to the CPU core and peripheral hardware. The timing generator provides the following

functions:

1. Generation of main system clock

2. Generation of source clocks for time base timer

3. Generation of source clocks for watchdog timer

4. Generation of internal source clocks for timer/counters TC1 to TC4

5. Generation of warm-up clocks for releasing STOP mode

6. Generation of a clock for releasing reset output

(1) Configuration of timing generator

The timing generator consists of a 21-stage divider with a divided by 3 prescaler, a

main system clock generator, and machine cycle counters.

During reset and at releasing STOP mode, the prescaler and the divider are cleared

to “0”, however, the prescaler is not cleared.

An input clock to the 7th stage of the divider depends on the operating mode.

A divided by 256 of high-frequency clock (fc/2⁸) is input to the 7th stage of the divider.

2007-09-12

88CS38B-9

TMP88CS38B/CM38B/CP38B

fm

Machine cycles

Machine cycle counters

States

DV1CK

S

Prescaler

0 1 2

Divider

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

fc/2⁸

High-frequency

clock

A

fc

Y

1

2

3

4

5

6

B

Reset circuit

standby

controller

Timer/

counters

Watchdog

timer

Time base

timer

fc

MK8 MHz

SLICER

SG

FC8OUT

D1

D0

JITTA

Figure 1.4.3 Configuration of Timing Generator

CGCR

(00030H)

“0”

DV1CK

“0”

(Initial value: 0000 0000)

0: fc/4

1: fc/8

Selection of input clock to

the 1st stage of the divider.

DV1CK

R/W

Note 1: fc: High-frequency clock [Hz], *: Don’t care

Note 2: The all bits except DV1CK are cleared to “0”.

Figure 1.4.4 Divider Control Register

FC8CR

(00FEEH)

D1

D0

Read/Write (Initial value: 0000 0010)

D1

1

D0

0

FC8OUT

1/2 fc

1/1 fc

0

Figure 1.4.5 FC8 Control Register

2007-09-12

88CS38B-10

TMP88CS38B/CM38B/CP38B

(2) Machine cycle

Instruction execution and peripheral hardware operation are synchronized with the

main system clock. The minimum instruction execution unit is called a “machine cycle”.

There are a total of 15 different types of instructions for the TLCS-870/X series:

Ranging from 1-cycle instructions which require one machine cycle for execution to

15-cycle instructions which require 15 machine cycles for execution.

A machine cycle consists of 4 states (S0 to S3), and each state consists of one main

system clock.

1/fc

Main System clock

fm

S0

S1

S2

S3

S0

S1

S2

S3

State

Machine cycle

(0.25 μs at fc =16 MHz)

Figure 1.4.6 Machine Cycle

1.4.3

Standby Controller

The standby controller starts and stops the switches the main system clock. These modes

are controlled by the system control registers (SYSCR1, SYSCR2).

Figure 1.4.7 shows the operating mode transition diagram and Figure 1.4.8 shows the

system control registers.

(1) Single-clock mode

In the single-clock mode, the machine cycle time is 4/fc [s] (0.25 μs at fc = 16 MHz).

1. NORMAL mode

In this mode, both the CPU core and on-chip peripherals operate using the

high-frequency clock.

2. IDLE mode

In this mode, the internal oscillation circuit remains active. The CPU and the

watchdog timer are halted; however, on-chip peripherals remain active (Operate

using the high-frequency clock). IDLE mode is started by setting IDLE bit in the

system control register 2 (SYSCR2), and IDLE1 mode is released to NORMAL

mode by an interrupt request from on-chip peripherals or external interrupt

inputs. When IMF (Interrupt master enable flag) is “1” (Interrupt enable), the

execution will resume upon acceptance of the interrupt, and the operation will

return to normal after the interrupt service is completed. When IMF is “0”

(Interrupt disable), the execution will resume with the instruction which follows

IDLE mode start instruction.

3. STOP mode

In this mode, the internal oscillation circuit is turned off, causing all system

operations to be halted. The internal status immediately prior to the halt is held

with the lowest power consumption during this mode.

STOP mode is started by setting STOP bit in the system control register 1

(SYSCR1), and STOP mode is released by an input (Either level-sensitive or

edge-sensitive can be programmably selected) to the STOP pin. After the warm-up

period is completed, the execution resumes with the next instruction which

follows the STOP mode start instruction.

2007-09-12

88CS38B-11

TMP88CS38B/CM38B/CP38B

RESET

Reset release

Software

Interrupt

Software

IDLE

mode

NORMAL

mode

STOP

mode

STOP pin input

(a) Single-clock mode

Note: NORMAL mode are generically called NORMAL; STOP mode is called STOP; and IDLE mode is

called IDLE.

Frequency

On-chip

Peripherals Cycle Time

Machine

Operating Mode

CPU Core

High-frequency

RESET

Reset

Turning on oscillation

Turning off oscillation

4/fc [s]

NORMAL

Operate

Single clock

Operate

IDLE

Halt

STOP

Halt

−

Figure 1.4.7 Operating Mode Transition Diagram

2007-09-12

88CS38B-12

TMP88CS38B/CM38B/CP38B

System Control Register 1

7

6

5

4

3

2

1

0

SYSCR1

(00038H) STOP

RELM

“0”

“1”

WUT

(Initial value: 0000 00**)

0: CPU core and peripherals remain active

STOP

STOP mode start

1: CPU core and peripherals are halted

(Start STOP mode)

0: STOP Edge-sensitive release (Rising edge)

1: STOP Level-sensitive release (“H” level)

Return to NORMAL mode

RELM

WUT

Release method for STOP mode

R/W

DV1CK = 0

3 × 2¹⁶/fc

2¹⁶/fc

DV1CK = 1

3 × 2¹⁷/fc

2¹⁷/fc

Warm-up time at releasing STOP

mode

00

01

10

11

2¹⁴/fc

2¹⁵/fc

Reserved

Note 1: Always set bit5 in SYSCR1 to “0”.

Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL mode regardless of the

RETM contents.

Note 3: fc: High-frequency clock [Hz]

*: Don’t care

Note 4: Bits 1 and 0 in SYSCR1 are read in as undefined data when a read instruction is executed.

Note 5: Always set bit4 in SYSCR1 to “1” when STOP mode is started.

System Control Register 2

7

6

5

4

3

2

1

0

SYSCR2

(00039H)

“1”

“0”

IDLE

(Initial value: 1000 ****)

0: CPU and watchdog timer remain active

IDLE

IDLE mode start

R/W

1: CPU and watchdog timer are stopped (Start IDLE mode)

Note 1: *: Don’t care

Note 2: Always set bit7, 6 and 5 in SYSCR2 to “100”.

Figure 1.4.8 System Control Registers

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1.4.4

Operating Mode Control

(1) STOP mode

STOP mode is controlled by the system control register 1 (SYSCR1) and the STOP

pin input. The STOP pin is also used both as a port P20 and an INT5 (External

interrupt input 5) pin. STOP mode is started by setting STOP (Bit7 in SYSCR1 ) to “1”.

During STOP mode, the following status is maintained.

1. Oscillations are turned off, and all internal operations are halted.

2. The data memory, registers and port output latches are all held in the status in

effect before STOP mode was entered.

3. The prescaler and the divider of the timing generator are cleared to “0”.

4. The program counter holds the address of the instruction following the instruction

which started the STOP mode.

STOP mode includes a level-sensitive release mode and an edge-sensitive release

mode, either of which can be selected with RELM (Bit6 in SYSCR1).

a. Level-sensitive release mode (RELM = 1)

In this mode, STOP mode is released by setting the STOP pin high. This mode

is used for capacitor back up when the main power supply is cut off and long term

battery back up.

When the STOP pin input is high, executing an instruction which starts the

STOP mode will not place in STOP mode but instead will immediately start the

release sequence (Warm up). Thus, to start STOP mode in the level-sensitive

release mode, it is necessary for the program to first confirm that the STOP pin

input is low. The following method can be used for confirmation:

Using an external interrupt input INT5 ( INT5 is a falling edge-sensitive input).

Example: Starting STOP mode with an INT5 interrupt.

PINT5:

TEST

JRS

LD

(P2). 0

;

To reject noise, the STOP mode does not start

if port P20 is at high

F, SINT5

(SYSCR1), 01010000B

(SYSCR1). 7

;

Sets up the level-sensitive release mode

Starts STOP mode

SET

LDW

RETI

(IL), 1110011101010111B

IL

← 0 (Clears interrupt latches)

12, 11, 7, 5, 3

SINT5:

V

STOP pin

IH

XOUT pin

STOP

operation

Warm up

NORMAL

operation

NORMAL

operation

STOP mode is released by the hardware.

Confirm by program that the

STOP pin input is low and

start STOP mode.

Always released if the STOP

pin input is high.

Note 1: After warm up is started, when STOP pin input is changed “L” level, STOP mode is not placed.

Note 2: When changing to the level-sensitive release mode from the edge-sensitive release mode, the release

mode is not switched until a rising edge of the STOP pin input is detected.

Figure 1.4.9 Level-sensitive Release Mode

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b. Edge-sensitive release mode (RELM = 0)

In this mode, STOP mode is released by a rising edge of the STOP pin input.

This is used in applications where a relatively short program is executed

repeatedly at periodic intervals. This periodic signal (for example, a clock from a

low-power consumption oscillator) is input to the STOP pin.

In the edge-sensitive release mode, STOP mode is started even when the STOP

pin input is high.

Example: Starting STOP mode from NORMAL mode

LD

(SYSCR1), 10010000B

;

Starts after specified to the edge-sensitive mode

V

IH

STOP pin

XOUT pin

STOP

operation

STOP

operation

NORMAL

operation

Warm up

NORMAL

operation

STOP mode started

by the program.

STOP mode is released by the hardware at the rising

edge of STOP pin input.

Figure 1.4.10 Edge-sensitive Release Mode

STOP mode is released by the following sequence:

1. When returning to NORMAL, clock oscillator is turned on.

2. A warm-up period is inserted to allow oscillation time to stabilize. During

warm-up, all internal operations remain halted. Two different warm-up times can

be selected with WUT (Bits 2 and 3 in SYSCR1) as determined by the resonator

characteristics.

3. When the warm-up time has elapsed, normal operation resumes with the

instruction following the STOP mode start instruction (e.g., [SET (SYSCR1). 7]).

The start is made after the divider of the timing generator is cleared to “0”.

Table 1.4.1 Warm-up Time Example

Warm-up Time [s]

WUT

Return to NORMAL mode

DV1CK = 0 DV1CK = 1

00

01

10

11

3 × 2¹⁶/fc

(12.29 m)

3 × 2¹⁷/fc

(24.58 m)

2¹⁶/fc

2¹⁴/fc

(4.10 m)

(1.02 m)

2¹⁷/fc

2¹⁵/fc

(8.20 m)

(2.05 m)

Reserved

(

-

)

Reserved

(

-

)

Note: The warm-up time is obtained by dividing the basic clock by the divider: therefore,

the warm-up time may include a certain amount of error if there is any fluctuation of

the oscillation frequency when STOP mode is released. Thus, the warm-up time

must be considered an approximate value.

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Figure 1.4.11 STOP Mode Start/Release

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STOP mode can also be released by setting the RESET pin low, which immediately

performs the normal reset operation.

Note: When STOP mode is released with a low hold voltage, the following cautions must

be observed.

The power supply voltage must be at the operating voltage level before releasing

STOP mode. The RESET pin input must also be high, rising together with the

power supply voltage. In this case, if an external time constant circuit has been

connected, the RESET pin input voltage will increase at a slower rate than the

power supply voltage. At this time, there is a danger that a reset may occur if input

voltage level of the RESET pin drops below the non-inverting high-level input

voltage (hysteresis input).

(2) IDLE mode

IDLE mode is controlled by the system control register 2 and maskable interrupts.

The following status is maintained during IDLE mode.

1. Operation of the CPU and watchdog timer is halted. On-chip peripherals continue

to operate.

2. The data memory, CPU registers and port output latches are all held in the status

in effect before IDLE mode was entered.

3. The program counter holds the address of the instruction following the instruction

which started IDLE mode.

Example: Starting IDLE mode.

SET

(SYSCR2). 4

;

IDLE ← 1

Starting IDLE mode

by instruction

CPU, WDT are halted

Yes

Reset

Reset input

No (High)

No

Interrupt request

Yes

Normal

release mode

No

IMF = 1

Yes (Interrupt release mode)

Interrupt processing

Execution of the

instruction which follows

the IDLE mode start

instruction

Figure 1.4.12 IDLE Mode

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IDLE mode includes a normal release mode and an interrupt release mode. Selection

is made with the interrupt master enable flag (IMF). Releasing the IDLE mode returns

from IDLE to NORMAL.

a. Normal release mode (IMF = “0”)

IDLE mode is released by any interrupt source enabled by the individual

interrupt enable flag (EF) or an external interrupt 0 ( INT0 pin) request.

Execution resumes with the instruction following the IDLE mode start instruction

(e.g., [SET (SYSCR2).4]). Normally, IL (Interrupt latch) of interrupt source to

release IDLE mode must be cleared by load instructions.

b. Interrupt release mode (IMF = “1”)

IDLE mode is released and interrupt processing is started by any interrupt

source enabled with the individual interrupt enable flag (EF) or an external

interrupt 0 ( INT0 pin) request. After the interrupt is processed, the execution

resumes from the instruction following the instruction which started IDLE mode.

Note: When a watchdog timer interrupt is generated immediately before the IDLE mode is

started, the watchdog timer interrupt will be processed but IDLE mode will not be

started.

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Figure 1.4.13 IDLE Mode Start/Release

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IDLE mode can also be released by setting the RESET pin low, which immediately

performs the reset operation. After reset, the TMP88CS38B/CM38B/CP38B is placed

in NORMAL mode.

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1.5 Interrupt Controller

The TMP88CS38B/CM38B/CP38B has a total of 17 interrupt sources; 6 externals and 11

internals. Multiple interrupts with priorities are also possible. Two of the internal sources are

pseudo non-maskable interrupts; the remainder are all maskable interrupts.

Table 1.5.1 Interrupt Sources

Interrupt Vector Table

Interrupt Source

Enable Condition

Priority

Latch

Address

Internal/

External

(Reset)

Non maskable

−

FFFFCH

High 0

Internal INTSW

(Software interrupt)

−

FFFF8H

FFFF4H

FFFF0H

FFFECH

FFFE8H

FFFE4H

FFFE0H

FFFDCH

FFFD8H

FFFD4H

FFFD0H

FFFCCH

FFFC8H

FFFC4H

FFFC0H

FFFBCH

FFFB8H

FFFB4H

FFFB0H

FFFACH

FFFA8H

FFFA4H

FFFA0H

FFF9CH

FFF98H

FFF94H

FFF90H

FFF8CH

FFF88H

FFF84H

FFF80H

1

2

Pseudo non maskable

Internal INTWDT (Watchdog timer interrupt)

IL

2

IL

3

IL

4

IL

5

IL

6

IL

7

IL

8

IL

9

External INT0

(External interrupt 0)

(16-bit TC1 interrupt)

IMF ·EF = 1, INT0EN = 1

3

Internal INTTC1

IMF ·EF = 1

4

External INTKWU (Key-on wakeup)

IMF ·EF = 1

5

Internal INTTBT

External INT2

(Time base timer interrupt)

IMF ·EF = 1

6

(External interrupt 2)

(8-bit TC3 interrupt)

IMF ·EF = 1

7

Internal INTTC3

IMF ·EF = 1

8

Internal INTTSBI (SBI interrupt)

IMF ·EF = 1

9

Internal INTTC4

External INT3

(8-bit TC4 interrupt)

IMF ·EF = 1

10

IL

10

IL

11

IL

12

IL

13

IL

14

IL

15

IL

16

IL

17

IL

18

IL

19

IL

20

IL

21

IL

22

IL

23

IL

24

IL

25

IL

26

IL

27

IL

28

IL

29

IL

30

IL

31

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Low 31

(External interrupt 3)

(External interrupt 4)

(AD converter interrupt)

(16-bit TC2 interrupt)

(External interrupt 5)

(OSD interrupt)

(Slicer interrupt)

Reserved

IMF ·EF = 1

11

External INT4

IMF ·EF = 1

12

Internal INTADC

Internal INTTC2

External INT5

IMF ·EF = 1

13

IMF ·EF = 1

14

IMF ·EF = 1

15

Internal INTOSD

Internal INTSLI

IMF ·EF = 1

16

IMF ·EF = 1

17

IMF ·EF = 1

18

Reserved

IMF ·EF = 1

19

Reserved

IMF ·EF = 1

20

Reserved

IMF ·EF = 1

21

Reserved

IMF ·EF = 1

22

Reserved

IMF ·EF = 1

23

Reserved

IMF ·EF = 1

24

Reserved

IMF ·EF = 1

25

Reserved

IMF ·EF = 1

26

Reserved

IMF ·EF = 1

27

Reserved

IMF ·EF = 1

28

Reserved

IMF ·EF = 1

29

Reserved

IMF ·EF = 1

30

Reserved

IMF ·EF = 1

31

Note: Before you change each enable flag (EF) and/or each interrupt latch (IL), be sure to clear the

interrupt master enable flag (IMF) to “0” (to disable interrupts).

a. After a DI instruction is executed.

b. When an interrupt is accepted, IMF is automatically cleared to “0”.

However to enable nested interrupts, change EF and/or IL before setting IMF to “1” (to enable

interrupts).

If the individual enable flags (EF) and interrupt latches (IL) are set under conditions other than the

above, the proper operation cannot be guaranteed.

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························

···························

Figure 1.5.1 Interrupt Controller Block Diagram

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Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources.

Each interrupt vector is independent.

The interrupt latch is set to “1” when an interrupt request is generated, and requests the

CPU to accept the interrupt. The acceptance of maskable interrupts can be selectively enabled

and disabled by program using the interrupt master enable flag (IMF) and the individual

interrupt enable flags (EF). When two or more interrupts are generated simultaneously, the

interrupt is accepted in the highest priority order as determined by the hardware. Figure 1.5.1

shows the interrupt controller.

(1) Interrupt latches (IL to IL )

31

2

Interrupt latches are provided for each source, except for a software interrupt. The latch

is set to “1” when an interrupt request is generated, and requests the CPU to accept the

interrupt. The latch is cleared to “0” just after the interrupt is accepted. All interrupt

latches are initialized to “0” during reset.

The interrupt latches are assigned to addresses 0003CH, 0003DH, 0002EH and 0002FH

in the SFR. Except for IL2, each latch can be cleared to “0” individually by an instruction ;

however, the read-modify-write instruction such as bit manipulation or operation

instructions cannot be used. When interrupt occurred during order execution, the reason is

because interrupt request is cleared. Thus, interrupt requests can be canceled and

initialized by the program. Note that request the interrupt latches cannot be set to “1” by

an instruction. For example, it may be that each latch is cleared even if an interrupt

request is generated during instruction exection.

The contents of interrupt latches can be read out by an instruction. Therefore, testing

interrupt request by software is possible.

Example 1: Clears interrupt latches

DI

;

Disable interrupt

LDW

(ILL), 1110100000111111B

IL , IL to IL ← 0

12 10 6

Example 2: Reads interrupt latches

LD WA, (ILL)

;

W ← ILH, A ← ILL

Example 3: Tests an interrupt latch

TEST

JR

(ILL). 7

if IL = 1 then jump

7

F, SSET

(2) Interrupt enable register (EIR)

The interrupt enable register (EIR) enables and disables the acceptance of interrupts,

except for the pseudo non-maskable interrupts (Software and watchdog timer interrupts).

Pseudo non-maskable interrupts are accepted regardless of the contents of the EIR;

however, the pseudo non-maskable interrupt cannot be nested more than once at the same

time.

The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt

enable flags (EF). These registers are assigned to addresses 0003AH, 0003BH, 0002CH and

0002DH in the SFR, and can be read and written by an instruction (including

read-modify-write instruction such as bit manipulation instructions).

Note: Do not use the read-modify-write instruction for the EIRL (Address 0003AH) during

pseudo non-maskable interrupt service task. If the read-modify-write instruction is used,

the IMF is not set to “1” after RETN.

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1. Interrupt master enable flag (IMF)

The interrupt master enable flag (IMF) enables and disables the acceptance of all

maskable interrupts. Clearing this flag to “0” disables the acceptance of all maskable

interrupts. Setting to “1” enables the acceptance of interrupts.

When an interrupt is accepted, this flag is cleared to “0” to temporarily disable the

acceptance of other maskable interrupts. After execution of the interrupt service

program, this flag is set to “1” by the maskable interrupt return instruction [RETI] to

again enable the acceptance of interrupts. If an interrupt request has already been

occurred, interrupt service starts immediately after execution of the [RETI]

instruction.

Pseudo non-maskable interrupts are returned by the [RETN] instruction. In this

case, the IMF is set to “1” only when pseudo non-maskable interrupt service is started

with interrupt acceptance enabled (IMF = 1). Note that the IMF remains “0” when

cleared by the interrupt service program.

The IMF is assigned to bit0 at address 0003A in the SFR, and can be read and

H

written by an instruction. The IMF is normally set and cleared by the [EI] and [DI]

instructions, and the IMF is initialized to “0” during reset.

2. Individual interrupt enable flags (EF to EF )

17

3

These flags enable and disable the acceptance of individual maskable interrupts,

except for an external interrupt 0. Setting the corresponding bit of an individual

interrupt enable flag to “1” enables acceptance of an interrupt, setting the bit to “0”

disables acceptance.

Example 1: Sets EF for individual interrupt enable, and sets IMF to “1”.

DI

;

Disable interrupt

EF ← 1

LD

(EIRE), 00000001B

16

LDW

(EIRL), 1110100010100001B

EF to EF , EF , EF , EF , IMF ← 1

15 13 11 7 5

Example 2: Sets an individual interrupt enable flag to “1”.

SET (EIRH). 4

;

EF ← 1

12

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Interrupt Latches (IL)

15

IL

14

13

12

IL

11

IL

10

9

8

7

6

5

4

3

2

1

0

IL

30

IL

29

IL

26

IL

19

IL

18

IL

17

IL

16

(0002E,

31

28

27

25

24

23

22

21

20

0002FH)

IL (0002FH)

D

IL (0002EH)

E

(Initial value: 00000000 00000000)

IL

14

IL

13

IL

12

IL

11

IL

10

IL

5

IL IL IL INF

15

9

8

7

6

4

3

2

(0003C,

0003DH)

IL (0003DH)

H

IL (0003CH)

L

(Initial value: 00000000 00000000**)

Interrupt Enable Registers (EIR)

15

14

13

12

EF

11

EF

10

9

8

7

6

5

4

3

2

1

0

EIR

(0002C,

0002DH)

EF

25

EF

24

EF

23

EF

22

EF

21

EF

20

EF

19

EF

18

EF

17

EF

16

31

30

29

28

27

26

EIR (0002DH)

EIR (0002CH)

D

E

(Initial value: 00000000 00000000)

EIR

(0003A,

0003BH)

EF

12

EF

11

EF

5

EF EF IMF

15

14

13

10

9

8

7

6

4

3

EIR (0003BH)

EIR (0003AH)

L

H

(Initial value: 00000000 0000000**0)

Note 1: Do not clear IL with read-modify-write instructions such as bit operations.

Note 2: Do not set IMF to “1” during non-maskable interrupt service program.

Note 3: Bits 1 and 0 in IL are read in as undefined data when a read instruction is executed.

L

Note 4: *: Don’t care

Note 5: Do not clear IL to “0” by an instruction.

2

Note 6: At TMP88CS38/CM38A/CP38A, IL to IL and EF to EF are not used.

18

31

18

31

Note 7: After IMF is cleared, modify EF and IL.

Figure 1.5.2 Interrupt Latches (IL) and Interrupt Enable Registers (EIR)

Interrupt Sequence

1.5.1

An interrupt request is held until the interrupt is accepted or the interrupt latch is

cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 12

machine cycles (3 μs at fc = 16 MHz in the NORMAL mode) after the completion of the

current instruction execution. The interrupt service task terminates upon execution of an

interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for pseudo

non-maskable interrupts). Figure 1.5.3 shows the timing chart of interrupt acceptance

processing.

(1) Interrupt acceptance

Interrupt acceptance processing is as follows.

1. The interrupt master enable flag (IMF) is cleared to “0” to temporarily disable the

acceptance of any following maskable interrupts. When a non-maskable interrupt

is accepted, the acceptance of any following interrupts is temporarily disabled.

2. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.

3. The contents of the program counter (PC) and the program status word (PSW) are

saved (Pushed) on the stack in sequence of PSW , PSW , PC , PC , PC . The

H

L

E

H

L

stack pointer (SP) is decremented five times.

4. The entry address of the interrupt service program is read from the vector table,

and set to the program counter.

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5. The RBS control code is read from the vector table. The lower 4 bits of this code is

added to the RBS.

6. The instruction stored at the entry address of the interrupt service program is

executed.

Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt

service program.

Vector table address

Entry address

FFFE4H

CD243H

CD244H

CD245H

CD246H

43

H

FFFE5H

FFFE6H

FFFE7H

Interrupt

service

program

Vector

D2

0C

H

RBS

control

06

A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable

interrupt higher than the level of current servicing interrupt is occurred.

When nested interrupt service is necessary, the IMF is set to “1” in the interrupt

service program. In this case, acceptable interrupt sources are selectively enabled by

the individual interrupt enable flags.

Note: Do not use the read-modify-write instruction for the EIRL (Address 0003AH) during

pseudo non-maskable interrupt service task.

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Interrupt service task

1-machine cycle

INT5

INTTBT

IL

15

6

IMF

Instruction

Execution

Instruction

Interrupt acceptance

Address

bus

a

a + 1

FFFE4 FFFE5 FFFE6 FFFE7

n

n − 1 n − 2 n − 3 n − 4

b

b + 1 b + 2

PC

a

a + 1

a

b

b + 1 b + 2 b + 3

SP

n

n − 1 n −2 n − 3 n − 4

n − 5

k = i + (FFFE7H). 3 − 0

i

RBS

INF

(a) Interrupt acceptance

Interrupt service task

IMF

Execution

RETI instruction

Address

bus

c

c + 1 n − 4 n − 3 n − 2 n − 1

n

a

a + 1

PC

c

c + 1

C + 2

a

a + 1 a + 2

SP

n − 5

n − 4 n − 3 n − 2 n − 1

n

RBS

INF

k

i

(b) Return from interrupt instruction

Note 1: a: Return address, b: Entry address, c: Address which the RETI instruction is stored

Note 2: The maximum response time from when an IL is set until an interrupt acceptance processing starts is 62/fc

[s] with interrupt enabled.

Figure 1.5.3 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction

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(2) Saving/restoring general-purpose registers

During interrupt acceptance processing, the program counter (PC) and the program

status word (PSW) are automatically saved on the stack, but not the accumulator and

other registers. These registers are saved by the program if necessary. Also, when

nesting multiple interrupt services, it is necessary to avoid using the same data

memory area for saving registers.

The following method is used to save/restore the general-purpose registers.

1. General-purpose register save/restore by automatic register bank changeover

The general-purpose registers can be saved at high speed by switching to a

register bank that is not in use. Normally, the bank0 is used for the main task and

the banks 1 to 15 are assigned to interrupt service tasks. To increase the efficiency

of data memory utilization, the same bank is assigned for interrupt sources which

are not nested.

The switched bank is automatically restored by executing an interrupt return

instruction [RETI] or [RETN]. Therefore, it is not necessary for a program to save

the RBS.

Example: Register bank changeover

PINTxx:

Interrupt processing

RETI

VINTxx:

DP

DB

PINTxx

1

;

RBS ← RBS + 1

2. General-purpose register save/restore by register bank changeover

The general-purpose registers can be saved at high speed by switching to a

register bank that is not in use. Normally, the bank0 is used for the main tank and

the banks 1 to 15 are assigned to interrupt service tasks.

Example: Register bank changeover

PINTxx:

LD RBS, n

Interrupt processing

RETI

;

Restores bank and returns

VINTxx:

DP

DB

PINTxx

0

Interrupt service routine entry address

Main task

Bank m

Main task

m

Switch to bank n by

LD, RBS and n

instruction

Acceptance

of interrupt

Interrupt

service task

Acceptance

of interrupt

Interrupt

service task

m

n

Saving

registers

Switch to bank n

automatically

Time

m

Restore to bank m

automatically by

[RETI]/[RETN]

Interrupt return

Restoring

registers

Interrupt return

(a) Saving/restoring by register bank changeover

(b) Saving/restoring using push/pop or data transfer instructions

Figure 1.5.4 Saving/Restoring General-purpose Registers

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3. General-purpose registers save/restore using push and pop instructions

To save only a specific register, and when the same interrupt source occurs more

than once, the general-purpose registers can be saved/restored using the push/pop

instructions.

Example: Register save/restore using push and pop instructions

PINTxx:

PUSH

WA

;

Save WA register pair

Interrupt processing

POP

RETI

WA

;

Restore WA register pair

Return

Address (Example)

SP

0023AH

0023B

0023C

0023D

0023E

0023F

00240

00241

A

W

SP

PC

L

H

E

L

H

E

L

H

E

PC

PSW

L

PSW

SP

H

At acceptance

of an interrupt

At execution

of a push

instruction

At execution

of a pop

instruction

At execution of an

interrupt return

instruction

4. General-purpose registers save/restore using data transfer instructions

Data transfer instruction can be used to save only a specific general-purpose

register during processing of single interrupt.

Example: Saving/restoring a register using data transfer instructions

PINTxx:

LD

(GSAVA), A

;

Save A register

Interrupt processing

LD

A, (GSAVA)

;

Restore A register

Return

RETI

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TMP88CS38B/CM38B/CP38B

(3) Interrupt return

The interrupt return instructions [RETI]/[RETN] perform the following operations.

[RETI] Maskable Interrupt Return [RETN] Non-maskable Interrupt Return

1. The contents of the program counter and 1. The contents of the program counter and program status

the program status word are restored

from the stack.

word are restored from the stack.

2. The stack pointer is incremented 5 times. 2. The stack pointer is incremented 5 times.

3. The interrupt master enable flag is set to 3. The interrupt master enable flag is set to “1” only when a

“1”.

non-maskable interrupt is accepted in interrupt enable status.

However, the interrupt master enable flag remains at “0”

when so clear by an interrupt service program.

4. The interrupt nesting counter is

decremented, and the interrupt nesting

flag is changed.

4. The interrupt nesting counter is decremented, and the

interrupt nesting flag is changed.

Interrupt requests are sampled during the final cycle of the instruction being

executed. Thus, the next interrupt can be accepted immediately after the interrupt

return instruction is executed.

Note: When the interrupt processing time is longer than the interrupt request generation

time, the interrupt service task is performed but not the main task.

1.5.2

Software Interrupt (INTSW)

Executing the [SWI] instruction generates a software interrupt and immediately starts

interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a

non-maskable interrupt is already underway, executing the SWI instruction will not

generate a software interrupt but will result in the same operation as the [NOP]

instruction.

Use the [SWI] instruction only for detection of the address error or for debugging.

1. Address error detection

FF is read if for some cause such as noise the CPU attempts to fetch an instruction

H

from a non-existent memory address. Code FF is the SWI instruction, so a software

H

interrupt is generated and an address error is detected. The address error detection

range can be further expanded by writing FF to unused areas of the program memory.

H

Address-trap reset is generated in case that an instruction is fetched from RAM, SFR

or DBR areas.

2. Debugging

Debugging efficiency can be increased by placing the SWI instruction at the software

break point setting address.

1.5.3

External Interrupts

The TMP88CS38B/CM38B/CP38B each have five external interrupt inputs ( INT0 , INT2,

INT3, INT4 and INT5 ). Three of these are equipped with digital noise rejection circuits

(Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also

possible with INT2, INT3 and INT4.

The INT0 /P50 pin can be configured as either an external interrupt input pin or an

input/output port, and is configured as an input port during reset.

Edge selection, noise rejection control except INT3 pin input and INT0 /P50 pin function

selection are performed by the external interrupt control register (EINTCR). Edge selecting

and noise rejection control for INT3 pin input are preformed by the remote control signal

preprocessor control registers. (Refer to the section of the remote control signal

preprocessor.) When INT0EN = 0, the IL3 will not be set even if the falling edge of INT0

pin input is detected.

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TMP88CS38B/CM38B/CP38B

Table 1.5.2 External Interrupts

Enable Conditions

Secondary

Function Pin

Source

Edge

Digital Noise Rejection

Any pulse shorter than 2/fc [s]

is regarded as noise and

removed. Pulses not shorter

than 7/fc [s] are definitely

regarded as signals.

INT0

P50/TC2/ PWM8 IMF = 1, INT0EN = 1, EF = 1

Falling edge

3

Pulses of less than 7/fc [s] are

eliminated as noise. Pulses

equal to or more than 25/fc [s]

are regarded as signals.

P53/TC1/ SCK1/

AIN0/ KWU0

Falling edge or

rising edge

INT2

INT3

INT4

INT2

INT3

INT4

IMF·EF = 1

7

Falling edge,

rising edge or

falling/rising edge

Refer to the section of the

remote control preprocessor

P30/RXIN

IMF·EF = 1

11

Pulses of less than 7/fc [s] are

eliminated as noise. Pulses of

25/fc [s] or more are

Falling edge or

rising edge

P31/TC3

IMF·EF = 1

12

considered to be signals.

Any pulse shorter than 2/fc [s]

is regarded as noise and

removed. Pulses not shorter

than 7/fc [s] are definitely

regarded as signals.

INT5

P20/ STOP

IMF·EF = 1

15

Falling edge

Note 1: The noise rejection function is also affected for timer counter input 1 (TC1 pin).

Note 2: If a noiseless signal is input to the external interrupt pin in the NORMAL or IDLE mode, the maximum

time from the edge of input signal until the IL is set is as follows:

(1) INT2, INT4 pin 31/fc [s]

(2) INT3 pin

Refer to the section of the remote control preprocessor.

Note 3: If a dual-function pin is used as an output port, changing data or switching between input and output

generates a pseudo interrupt request signal. To ignore this signal, it is necessary to reset the interrupt

enable flag.

Note 4: If INT0EN = “0”, detecting the falling edge of the INT0 pin input does not set the interrupt latch IL3.

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TMP88CS38B/CM38B/CP38B

EINTCR

7

6

5

4

3

2

1

0

(00037H)

INT0

EN

INT4

ES

INT2

ES

“0”

−

“0”

−

(Initial value: 00*0 *00*)

0: P50 input/output port

INT0EN P50/INT0 pin configuration

1: INT0 pin (Port P50 should be set to an input mode)

Write

only

0: Rising edge

1: Falling edge

INT4ES

INT4 and INT2 edge select

INT2ES

Note 1: fc: High-frequency clock [Hz], *: Don’t care

Note 2: Edge detection during switching edge selection is invalid.

Note 3: Do not change EINTCR only when IMF = 1. After changing EINTCR, interrupt latches of external interrupt

inputs must be cleared to “0” using load instruction.

Note 4: In order to change of external interrupt input by rewriting the contents of INT2ES and INT4ES during

NORMAL mode, clear interrupt latches of external interrupt inputs (INT2 and INT4) after 8 machine cycles

from the time of rewriting.

Note 5: In order to change an edge of timer counter input by rewritng the contents of INT2ES during NORMAL

mode, rewrite the contents after timer counter is stopped (TC*s = 0) , that is, terrupt disable state.

Then, clear a interrupt latch of external interrupt input (INT2) after 8 machine cycles from the time of

rewriting to change to interrupt enable state. Finally, start timer counter.

Example: When change TC1 pin inputs edge in external trigger timer mode from rising edge falling edge.

LD (TC1CR) , 01001000B

DI

LD (EINTCR) , 00000100B

;

TC1S ← 00 (Stops TC1)

IMF ← 0 (Disables interrupt service)

INT2ES ← 1 (Change edge selection)

NOP

to

NOP

8-machine

cycles

LD (ILL) , 01111111B

EI

LD (TC1CR) , 01111000B

;

IL7 ← 0 (Clears interrupt latch)

IMF ← 1 (Enable interrupt service)

TC1S ← 11 (Starts TC1)

Figure 1.5.5 External Interrupt Control Register

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TMP88CS38B/CM38B/CP38B

1.6 Reset Circuit

The TMP88CS38B/CM38B/CP38B has four types of reset generation procedures: An external

reset input, an address trap reset output, a watchdog timer reset output and a system clock

reset output. Table 1.6.1 shows on-chip hardware initialization by reset action.

The malfunction reset output circuit such as watchdog timer reset, address trap reset and

system clock reset is not initialized when power is turned on. The RESET pin can output level

“L” at the maximum 24/fc [s] (1.5 μs at 16 MHz) when power is turned on.

Table 1.6.1 Initializing Internal Status by Reset Action

On-chip Hardware

Initial Value

On-chip Hardware

Initial Value

Program counter

(PC)

(SP)

(FFFFEH to FFFFCH)

Not initialized

Prescaler and divider of timing

generator

Stack pointer

0

General-purpose registers

Not initialized

(W, A, B, C, D, E, H, L)

Register bank selector

(RBS)

(JF)

0

Watchdog timer

Enable

Jump status flag

Zero flag

1

(ZF)

Not initialized

0

Carry flag

(CF)

(HF)

(SF)

(VF)

(IMF)

Half carry flag

Refer to I/O port

circuitry

Output latches of I/O ports

Sign flag

Overflow flag

Interrupt master enable flag

Interrupt individual enable flags

0

Refer to each of

control register

(EF)

(IL)

Control registers

RAM

Interrupt latches

0

−

Not initialized

1.6.1

External Reset Input

The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.

When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the

power supply voltage within the operating voltage range and oscillation stable, a reset is

applied and the internal state is initialized.

When the RESET pin input goes high, the reset operation is released and the program

execution starts at the vector address stored at addresses FFFFCH to FFFFEH.

VDD

Reset input

RESET

Watchdog timer reset

Address trap reset

System clock reset

Malfunction

reset output

circuit

Sink open drain

Figure 1.6.1 Reset Circuit

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TMP88CS38B/CM38B/CP38B

1.6.2

Address-trap-reset

If the CPU should start looping for some cause such as noise and an attempt be made to

fetch an instruction from the on-chip RAM, DBR or the SFR area, address-trap-reset will

be generated. Then, the RESET pin output will go low. The reset time is about 8/fc to 24/fc

[s] (0.5 to 1.5 μs at 16 MHz).

Instruction

JP

a

Instruction at address

Reset release

execution

Address trap is occurred

(“L” output)

RESET output

(High-Z)

8/fc to 24/fc [s]

4/fc

to

20/fc [s]

(No wait)

12/fc [s]

Note 1: 0 ≤ a ≤ 008BFH (TMP88CS38B), 0 ≤ a ≤ 006BFH (TMP88CM38B/CP38B)

0 ≤ a ≤ 002BFH (The ROM corrective function is enabled.)

Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.

Figure 1.6.2 Address-trap-reset

1.6.3

1.6.4

Watchdog Timer Reset

Refer to section 2.4 “Watchdog Timer”.

System-clock-reset

Clearing bits 7 in SYSCR2 to “0”, system clock stops and causes the microcomputer to

deadlock. This can be prevented by automatically generating a reset signal whenever bits 7,

6 and 5 in SYSCR2 = 000 is detected to continue the oscillation. The RESET pin output

goes low from high-impedance. The reset time is about 8/fc to 24/fc [s] (0.5 to 1.5 μs at 16

MHz).

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TMP88CS38B/CM38B/CP38B

1.7 ROM Corrective Function

The ROM corrective function can patch the part (s) of on-chip ROM with some bugs.

The ROM corrective function have two modes. One is to replaced the instruction on a certain

address in the ROM with the jump instruction to branch into the RAM area where the patched

codes (Program jump mode). The other is to replace a byte or a word (2 or 3 bytes) length data in

the ROM with the patched data (Data replacement mode). Four independent location can be

patched.

Note 1: When use ROM corrective circuit, it is necessary to contain a program which operates to load

patched program and/or replacement data from external memory into an internal data RAM

in an initial routine.

Note 2: The address of a instruction for IDLE mode can not be specificated as start address of

corrective area.

Note 3: The BM88CS38N0A does not support the ROM corrective circuit. Use the TMP88PS38B to

debug a program of this circuit. In this case, note the following.

In program jump mode, jump target addresses that can be specified with the

TMP88CM38B/CP38B (002C0H to 006BFH) are different from those that can be specified

with the TMP88PS38B (002C0H to 008BFH). Therefore, if a jump target address is within a

range of 006C0H to 008BFH, it is necessary to change this addresse and also addresses for

loading a patch program.

Example:

ROM corrective circuit

ROMCDR

Serial

bus

interface

•

Correction mode

Correction code

Patch program

RAM

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TMP88CS38B/CM38B/CP38B

1.7.1

Configuration

Address bus

Data bus

Match

signal

Address compare circuit

Instruction fetch control circuit

23

to

6

5

4

to

Register

selection

circuit

3

2

1

0

the lower

the middle

the upper

the lower

the middle

the upper

5

Compare address register

Data register

CM CM CM CM

Corrective mode signal

WDC

0

1

2

3

Write data count

Register write signal

ROMCDR

CM3-0

ROM corrective

data register

Write data

count register

ROM corrective

control register

Figure 1.7.1 ROM Corrective Circuit

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1.7.2

Control

The ROM corrective function is controlled by ROM corrective control register (ROMCCR)

and ROM corrective data register (ROMCDR).

ROM Corrective Control Register

7

6

5

4

3

2

1

0

ROMCCR

(00FE0H)

−

CM2

−

CM3

CM1

CM0

(Initial value: **** 0000)

Corrective mode setting

(BANK3)

CM3

CM2

CM1

CM0

Corrective mode setting

(BANK2)

0: Proguram jump mode

1: Data replacement mode

R/W

Corrective mode setting

(BANK1)

Corrective mode setting

(BANK0)

ROM Corrective Status Register

7

6

5

4

3

2

1

0

ROMCSR

(00FE1H)

WDC

−

(Initial value: ***0 0000)

Read

only

WDC

Write data counter

Counting the number of the byte written in ROMCDR

ROM Corrective Data Register

7

6

5

4

3

2

1

0

ROMCDR

(00FE2H)

(Initial value: 0000 0000)

Write

only

ROMC

ROM Corrective data register

Figure 1.7.2 ROM Corrective Control Register, Status Register and ROM Corrective Data Register

(1) Enable and disable

The ROM corrective function is disabled after releasing reset. It is enabled after

setting the data for one bank into ROMCDR. And the address-trap-reset is not

generated when fetching an instruction from the RAM area except the address 02C0H

to 08BFH.

After the ROM corrective function is enabled, it is necessary to reset the

microcontroller in order to disable it.

(2) Data replacement mode

The ROM corrective function has the program jump mode and the data replacement

mode.

By setting CMx (x: 0 to 3) in ROMCCR, the data replacement mode is selected.

(3) The ROM corrective data register writing

The ROM corrective data register has four banks corresponding to four independent

locations to patch. The write data counter (WDC) points each bank set. (Figure 1.7.2)

2007-09-12

88CS38B-37

TMP88CS38B/CM38B/CP38B

ROM Corrective Data Register

ROMCDR

ROMC6

ROMC4

ROMC2

ROMC3 ROMC1 ROMC0

ROMC7

ROMC5

(Initial value: 0000 0000)

(00FE2H)

The value of WDC after writing a data to ROMCDR

00000 (Initial value)

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

00000

The lower start address of the corrective area (8 bits)

The middle start address of the corrective area (8 bits)

The upper start address of the corrective area (4 bits)

The lower 8 bits of the jump address/replacement data

The middle 8 bits of the jump address/replacement data

The upper 4 bits of the jump address/replacement data

The lower start address of the corrective area (8 bits)

The middle start address of the corrective area (8 bits)

The upper start address of the corrective area (4 bits)

The lower 8 bits of the jump address/replacement data

The middle 8 bits of the jump address/replacement data

The upper 4 bits of the jump address/replacement data

The lower start address of the corrective area (8 bits)

The middle start address of the corrective area (8 bits)

The upper start address of the corrective area (4 bits)

The lower 8 bits of the jump address/replacement data

The middle 8 bits of the jump address/replacement data

The upper 4 bits of the jump address/replacement data

The lower start address of the corrective area (8 bits)

The middle start address of the corrective area (8 bits)

The upper start address of the corrective area (4 bits)

The lower 8 bits of the jump address/replacement data

The middle 8 bits of the jump address/replacement data

The upper 4 bits of the jump address/replacement data

BANK0

BANK1

BANK2

BANK3

Note 1: WDC value equals to the number of the byte stored in ROMCDR.

Note 2: ROMCDR is set in order of the lower (8 bits), the middle (8 bits) and the upper (4 bits) start address of the

corrective area, the lower (8 bits), the middle (8 bits) and the upper (4 bits) of the jump address/the

replacement data.

Figure 1.7.3 Banks and WDC Value of the Program Corrective Data Register

Whenever ROMCDR is written, WDC is incremented to indicate what data is writen via

ROMCDR. During reset, WDC is initialized to “0”.

(1) The lower start address of the corrective area (8 bits)

(2) The middle start address of the corrective area (8 bits)

(3) The upper start address of the corrective area (4 bits)

(4) The lower jump address/replacement data (8 bits)

(5) The middle jump address/replacement data (8 bits)

(6) The upper jump address (4 bits)/replacement data

Note 1:Corrective addresses must have over five addresses each other.

Note 2:The address of a instruction for IDLE mode can not be specificated as start address of

corrective area.

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TMP88CS38B/CM38B/CP38B

1.7.3

Functions

The ROM corrective function can correct maximum four ROM areas with their

corresponding four banks of ROM corrective registers. Either program jump mode or data

replacement mode is selected for each bank by CM0 to CM3 respectively.

(1) Program jump mode

In the program jump mode, the system executes a jump instruction when the

program execution reaches the instruction at the corrective ROM address, skips from

the instruction which would have been executed, and executes an instruction at a

preset jump address.

Clearing ROMCCR CMx (x: 0 to 3) to “0” puts the system in the program jump mode.

Use ROMCDR to set the corrective ROM address and jump address.

When the start address of an erroneous program is a corrective ROM address, and

that of the patch program is a jump address, the bug in the erroneous program can be

fixed. Note that the patch program should end with a jump instruction, which causes a

return to the built-in ROM.

Note: For program jump mode, the address to be corrected must be the start address of

the instruction.

Example 1: Setting the program correction circuit with the initial routine

Using the initial routine program, which is executed right after reset, set the

program correction circuit's register and stores the patch program into the built-in

RAM as follows.

1. Read the flag, which indicates whether to use the program correction circuit, from

the external memory.

2. If that circuit is not used, perform normal initial processing.

3. If it is used, clear CMx to 0 to establish the program jump mode.

4. Read the corrective ROM address and jump address from the external memory.

5. Set the corrective ROM address and jump address, which were read in step “4.”, in

ROMCDR.

6. Read the number of bytes for the patch program from the external memory.

7. Read the program with a number of bytes, equal to the byte count read in step “6.”,

from the external memory, and store that program into the built-in RAM.

8. Repeat steps “4.” through “7.” as many times as there are required banks.

Example 2: There is bugs on the locations from 0C020H to 0C085H

The corrective address, the jump vector, the program patch codes and other

information to patch the ROM with the bugs must be read out from any of memory

storage that holds them during initial program routine. CMn = 0 specifies the

program jump mode. Subsequently, the patch program codes are loaded into RAM

(00600H to 006EFH). The start address (0C020H) of the ROM necessary to patch

is written to the corrective ROM address registers, and the start address (00600H)

of the RAM area to patch is loaded onto the jump address registers. When the

instruction at 0C020H is fetched, the instruction to jump into 00600H is

unconditionally executed instead of the instruction at 0C020H, and the

subsequent patch program codes are executed. The jump instruction at the end of

the patch program codes returns to the ROM at 0C086H.

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88CS38B-39

TMP88CS38B/CM38B/CP38B

00000H

SFR

00600H

0003FH

00040H

Patch

program

RAM

0083FH

00F80H

JP 0C086H

006EFH

006F0H

DBR

00FFFH

04000H

Return

ROM

0C020H

Bug area

0C085H

0C086H

FFFFFH

Note: Corrective address must be assigned to 1st byte of instruction codes on the

program jump mode.

(2) Data replacement mode

In the data replacement mode, the system replaces reference data stored in the ROM

area with the new instead of correcting the data reference instruction when that

reference data is changed.

The program jump mode reduces the complexity of correcting the processing routine.

However, when this mode is used, if there is a need to replace only the fixed data in

ROM, the instruction to reference this ROM data should be corrected. Thus, a large

amount of ROM is required for the patch program. To avoid this, the system has the

data replacement mode. With this mode, three consecutive bytes of data can be

replaced for each bank. (For an instruction which accesses only one byte, only the first

byte can be replaced. For an instruction which accesses only two bytes, the two

consecutive bytes can be replaced.) Setting ROMCCR CMx (x: 0 to 3) to “1” puts the

system in the data replacement mode. Specify the start address of ROM data to be

replaced as the corrective ROM address. Then, specify the new three-byte data as the

patch data.

Note: For data replacement mode, the corrective address should be the address of fixed

data (including a vector). (The operation code and operand cannot be changed.)

Example 1: Setting the program correction circuit with the initial routine

Using the initial routine program, which is executed right after reset, set the

program correction circuit's register as follows.

1. Read the flag, which indicates whether to use the program correction circuit, from

the external memory.

2. If that circuit is not used, perform normal initial processing.

3. If it is used, set CMx to “1” to establish the data replacement mode.

4. Read the address of the data to be replaced and the patch data from the external

memory.

5. Set the address and patch data, which were read in step “4.”, in ROMCDR.

6. Repeat steps “4.” and “5.” as many times as there are required banks.

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TMP88CS38B/CM38B/CP38B

Example 2: Replacing data 55H at 0C020H with 33H

Using the initial routine program, which is executed right after reset, read the

start address of the data to be replaced and the patch data from the external

memory. Set CMx (x: 0 to 3) to “1” to change the correction mode to the data

replacement mode. Specify the start address (0C020H) of the data to be replaced

as the corrective ROM address. Then, specify the new three-byte data (33H for

0C020H, CCH for 0C021H, and C3H for 0C022H) as the patch data.

00000H

SFR

0003FH

00040H

RAM

0083FH

00F80H

DBR

00FFFH

04000H

ROM

0C020H

0C021H

0C022H

33H

CCH

3CH

55H

AAH

A5H

Replacement data

FFFFF

H

1. At HL = 0C020H, Executing LD A, (HL) loads 33H in A. (Data replacement)

2. At HL = 0C021H, Executing LD A, (HL) loads AAH in A. (No data replacement)

3. At HL = 0C020H, Executing LD WA, (HL) loads CC33H in WA. (Data replacement)

4. At HL = 0C020H, Executing LD IX, (HL) loads CCC33H in IX. (Data replacement)

Note 1: Corrective address must be assigned to constant data area on the data

replacement mode. (Ope-code and ope-rand can’t be replaced by ROM correction

circuit.)

Note 2: Instructions which includes “(HL+)” or “(−HL) ” operation can't be replaced by ROM

corrective circuit on the data replacement mode.

2007-09-12

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TMP88CS38B/CM38B/CP38B

2. On-chip Peripheral Functions

2.1 Special Function Registers (SFR) and Data Buffer Registers (DBR)

The TLCS-870/X series uses the memory mapped I/O system and all peripheral control and

data transfers are performed through the special function registers (SFRs) and data buffer

registers (DBR).

The SFR are mapped to addresses 00000H to 0003FH, and DBR are mapped to address

00F80H to 00FFFH.

Figure 2.1.1 shows the list of the TMP88CS38B/CM38B/CP38B SFRs and-DBRs.

Address

00000H

00001

00002

00003

00004

00005

00006

00007

00008

00009

0000A

0000B

0000C

0000D

0000E

0000F

00010

00011

00012

00013

00014

00015

00016

00017

00018

00019

0001A

0001B

0001C

0001D

0001E

0001F

Read

Write

Address

00020H

00021

00022

00023

00024

00025

00026

00027

00028

00029

0002A

0002B

0002C

0002D

0002E

0002F

00030

00031

00032

00033

00034

00035

00036

00037

00038

00039

0003A

0003B

0003C

0003D

0003E

0003F

Read

SBISRA (SBI statusA)

Write

Reserved

P2 port

P3 port

P4 port

P5 port

P6 port

P7 port

SBICRA (SBI control register A)

SBIDBR (SBI data buffer)

−

I²CAR (I²C bus address)

SBISRB (SBI statusB)

SBICRB (SBI control register B)

−

ORDMA (OSD control)

L

ORDMA (OSD control)

H

RCSR (TC3 status)

RCCR (TC3 control)

PMPXCR (Port control)

−

P5CR1 (P5 port I/O control1)

P7CR (P7 port I/O control)

−

PWMCR1A (PWM control 1A)

PWMCR1B (PWM control 1B)

PWMDBR1 (PWMDBR1)

P3CR1 (P3 I/O control)

−

Reserved

P4CR (P4 port I/O control)

P6CR (P6 port I/O control)

−

EIR

E

(Interrupt enable register)

(Interrupt latch)

D

ADCCRA (AD converter control A)

ADCCRB (AD converter control B)

IL

E

IL

D

TC1DRA

CGCR (Divider control)

L

(Timer register 1A)

TC1DRA

ADCDR1 (AD conversion result)

ADCDR2 (AD conversion result)

Reserved

H

TC1DRB

−

L

(Timer register 1B)

H

Watchdog timer

control

TC1CR (TC1 control)

−

WDTCR1

WDTCR2

−

TC2CR (TC2 control)

TC2DR

L

TBTCR (TBT/TG control)

(Timer register 2)

TC2DR

−

EINTCR (External interrupt control)

H

TC3DRA (Timer register 3A)

SYSCR1

SYSCR2

(System control)

TC3DRB (Timer register 3B)

−

TC3CR (TC3 control)

TC4DR (Timer register 4)

TC4CR (TC4 control)

EIR

L

(Interrupt enable register)

(Interrupt latch)

EIR

H

IL

L

ORDSN (OSD control)

IL

H

ORCRA (OSD control)

L

PSW

L

(Program status word)

ORCRA (OSD control)

H

PSW

H

(a) Special function registers

Note 1: Do not access reserved areas by the program.

Note 2: −: Cannot be accessed.

Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation

instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).

Note 4: When defining address 0003FH with assembler symbols, use GRBS.

Address 0003EH must be GPSW/GFLAG.

Figure 2.1.1 (a) SFR

2007-09-12

88CS38B-42

TMP88CS38B/CM38B/CP38B

Address

00F80H

81

Read

Write

ORDON (OSD control)

OSD control register

Reserved

−

A1

A2

−

OSD control register

−

ORIRC (OSD display counter)

ORIRC (OSD interrupt control)

OSD control register

B9

BA

−

OSD control register

Reserved

IDLECR (Key-on wakeup control)

C0

IDLEINV (Key-on wakeup status)

D0

D1

Reserved

SINTCR (Data slicer interrupt control)

DACLCR (Sync. tip slice level setting)

SLVLCR (Slice level control)

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

−

SIFDR1 (Caption data 1st byte)

SIFDR2 (Caption data 2nd byte)

SIFSR (Data slicer status)

−

SIFS1R (Data slicer status2)

SIFSMS1 (Data slicer mode setting)

ROMCCR (ROM corrective control)

ROMCSR (ROM corrective status)

−

ROMCDR (ROM corrective data)

Reserved

JECR (Jitter elimination control)

JESR (Jitter elimination status)

−

TVSCR (Test video signal output)

Reserved

RXCR1 (Remote control recieve control 2)

RXCR2 (Remote control recieve control 1)

RXCTR (Remote control receive counter)

−

RXDBR (Remote control receive data buffer)

RXSR (Remote control status)

Reserved

FC8CR (FC8 control)

Reserved

SCCRB (Serial clock source control)

SCSR (Serial clock source status)

Reserved

−

PWMCR2A (PWM control 2A)

PWMCR2B (PWM control 2B)

PWMDBR2 (PWM data buffer)

Reserved

PSELCR (P3, P5 control 2)

Reserved

−

FE

FF

(b) Data buffer registers

Note 1: Do not access reserved areas by the program.

Note 2: −: Cannot be accessed.

Note 3: Write-only registers cannot use the read-modify-write instructions (Bit manipulation instructions such as

SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).

Figure 2.1.2 (b) DBR

2007-09-12

88CS38B-43

TMP88CS38B/CM38B/CP38B

2.2 I/O Ports

The TMP88CS38B/CM38B/CP38B has 6 parallel input/output ports (33 pins) as follows:

Primary Function

Secondary Functions

Port P2

Port P3

1-bit I/O port

6-bit I/O port

External interrupt input, and STOP mode release signal input

External interrupt input, remote control signal input, data slicer analog

input, timer/counter input, serial bus interface input/output and data

slicer input

Port P4

Port P5

8-bit I/O port

Pulse width modulation output

Pulse width modulation output external interrupt input, timer/counter

input, key-on wakeup input, serial bus interface input/output, analog

input and I output from OSD circuitry.

Port P6

Port P7

8-bit I/O port

2-bit I/O port

R, G, B and Y/BL output from OSD circuitry, R.G.B and Y/BL input,

analog input, test video signal output and key-on wakeup input

Horizontal synchronous pulse input and vertical synchronous pulse

input to OSD circuitry

Each output port contains a latch, which holds the output data. All input ports do not have

latches, so the external input data should either be held externally until read or reading should

be performed several times before processing. Figure 2.2.1 shows input/output timing examples.

External data is read from an I/O port in the S1 state of the read cycle during execution of the

read instruction. This timing can not be recognized from outside, so that transient input such as

chattering must be processed by the program. Output data changes in the S2 state of the write

cycle during execution of the instruction which writes to an I/O port.

Fetch cycle

Read cycle

S

2 3

0

1

2

3

0

1

2

3

0

1

Instruction

execution

cycle

Ex.: LD A, (x)

Input strobe

Data input

(a) Input timing

Fetch cycle

Write cycle

S

2 3

0

1

2

3

0

1

2

3

0

1

Instruction

execution

cycle

Ex.: LD (x), A

Output latch

pulse

Data output

(b) Output timing

Note: The positions of the read and write cycles may vary, dispending on the instruction.

Figure 2.2.1 Input/Output Timing (Example)

2007-09-12

88CS38B-44

TMP88CS38B/CM38B/CP38B

When reading an I/O port except programmable I/O ports, whether the pin input data or the

output latch contents are read depends on the instructions, as shown below:

(1) Instructions that read the output latch contents

1. XCH r, (src)

2. SET/CLR/CPL (src).b

3. SET/CLR/CPL (pp).g

4. LD (src).b, CF

5. LD (pp).b, CF

6. ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), n

7. (src) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL)

(2) Instructions that read the pin input data

1. Instructions other than the above (1)

2. (HL) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL)

2.2.1

Port P2 (P20)

Port P2 is a 1bit input/output port. It is also used as an external interrupt input, and a

STOP mode release signal input. When used as an input port, or a secondary function pin,

the output latch should be set to “1”. During reset, the output latch is initialized to “1”.

It is recommended that pin P20 should be used as an external interrupt input, a STOP

mode release signal input, or an input port. If used as an output port, the interrupt latch is

set on the falling edge of the P20 output pulse.

When a read instruction for port P2 is executed, bits 7 to 1 in P2 are read in as undefined

data.

SET/CLR/CPI/others

Output latch

D

Q

P20 ( INT5 / STOP )

Data input

Control input

STOP

OUTEN

7

6

5

4

3

2

1

0

P20

INT5

P2

(Initial value: **** ***1)

(00002H)

STOP

*: Don’t care

Figure 2.2.2 Port P2

2007-09-12

88CS38B-45

TMP88CS38B/CM38B/CP38B

2.2.2

Port P3 (P35 to P30)

Port P3 is an 6-bit input/output port which can be configured as an input or an output in

one-bit unit under software control. Input/output mode is specified by the corresponding bit

in the port P3 input/output control register 1 (P3CR1). Port P3 is configured as an input if

its corresponding P3CR1 bit is cleared to “0”, and as an output if its corresponding P3CR1

bit is set to “1”. During reset, P3CR1 is initialized to “0”, which configures port P3 as an

input. The P3 output latches are also initialized to “1”. Data is written into the output latch

regardless of the P3CR1 contents. Therefore initial output data should be written into the

output latch before setting P3CR1.

Port P3 is also used as an external interrupt input, remote-control signal input a

timer/counter input, data slicer input and serial bus interface input/output. When used as a

secondary function input pin except I²C bus interface input/output, the input pins should

be set to the input mode. When used as a secondary function output pin except I²C bus

interface input/output, the output pins should be set to the output mode and beforehand

the output latch should be set to “1”. When P34 and P35 are used as I²C bus interface

input/output, P3CR2 bits should be set to the sink open-drain mode, the output latches

should be set to “1”, and the output pins should be set to the output mode.

Note: Input mode port is read the state of input pin. When input/output mode is used mixed,

the contents of output latch setting input mode may be changed by executing bit

manipulation instructions.

Example 1: Outputs an immediate data 5A to port P3

H

LD

(P3), 5A

;

P3 ← 5A

H

Example 2: Inverts the output of the lower 4 bits (P33 to P30) in port P3

XOR

(P3), 00001111B

;

P33 to P30 ← P33 to P30

2007-09-12

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TMP88CS38B/CM38B/CP38B

STOP

OUTEN

P3iCR1

P3jCR1

Data input

Control input

P3iCR2

Control input (*1)

D

Q

D

Q

Data output

P3j

P3i

Output latch

Control output

VIN (*2)

(a) P35 to P34

(b) P33 to P30

7

6

5

4

3

2

1

0

P30

INT3

RXIN

P35

SDA0

P34

SCL0

P33

VIN0

TC4

P32

VIN1

CSIN

P31

INT4

TC3

P3

(Initial value: **11 1111)

(Initial value: **00 0000)

(00003H)

7

6

5

4

3

2

1

0

P3CR1

(0002BH)

P35CR1 P34CR1 P33CR1 P32CR1 P31CR1 P30CR1

0: Input mode

Write

only

P3CR1

I/O control for P3

1: Output mode

2

7

6

5

4

3

1

0

PSELCR

(0FFEH)

“0”

P35CR2 P34CR2

“0”

P52CR2 P51CR2

“0”

(Initial value: 0*00 *00*)

0: Sink open drain

1: Tri-state

Write

only

P3CR2

I/O control for P3

(*1) only P33, P31, P30

(*2) only P33, P32

Note 1: *: Don’t care, i = 5 to 4, j = 3 to 0

Note 2: P3CR1 cannot used the read-modify-write instructions.

(Bit manipulation instructions such as SET, CLR, etc. and logical operation such as AND, OR, etc.)

Note 3: Clear bit7, 6, 3 and 0 to “0” in PSELCR.

Figure 2.2.3 Port P3 and P3CR

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TMP88CS38B/CM38B/CP38B

2.2.3

Port P4 (P47 to P40)

Port P4 is an 8-bit input/output port which can be configured as an input or an output in

one-bit unit under software control. Input/output mode is specified by the corresponding bit

in the port P4 input/output control register (P4CR). Port P4 is configured as an input if its

corresponding P4CR bit is cleared to “0”, and as an output if its corresponding P4CR bit is

set to “1”. During reset, P4CR is initialized to “0”, which configures port P4 as an input. The

P4 output latches are also initialized to “1”. Data is written into the output latch regardless

of the P4CR contents. Therefore initial output data should be written into the output latch

before setting P4CR.

Port P4 is also used as a pulse width modulation (PWM) output. When used as a PWM

output pin, the output pins should be set to the output mode and beforehand the output

latch should be set to “1”.

Note: Input mode port is read the state of input pin. When input/output mode is used mixed,

the contents of output latch setting input mode may be changed by executing bit

manipulation instructions.

STOP

OUTEN

P4iCR

Data input

D

Q

Data output

PWMi

P4i

Output latch

7

6

5

4

3

2

1

0

P46

P45

P43

P47

P44

P42

P41

P4

P40

PWM0

(Initial value: 1111 1111)

(Initial value: 0000 0000)

(00004H)

PWM6

PWM5

PWM3

PWM7

PWM4

PWM2

PWM1

7

6

5

4

3

2

1

0

P4CR

(0000CH)

P47CR P46CR P45CR P44CR P43CR P42CR P41CR P40CR

0: Input mode

Write

only

P4CR

I/O Control for port P4

1: Output mode

Note 1: i = 7 to 0.

Note 2: P4CR cannot used the read-modify-write instructions.

(Bit manipulation instructions such as SET, CLR, etc. and logical operation such as AND, OR, etc.)

Figure 2.2.4 Port P4 and P4CR

2007-09-12

88CS38B-48

TMP88CS38B/CM38B/CP38B

2.2.4

Port P5 (P57 to P50)

Port P5 is an 8-bit input/output port which can be configured as an input or an output in

one-bit unit under software control. Input/output mode is specified by the corresponding bit

in the port P5 input/output control register 1 (P5CR1). Port P5 is configured as an input if

its corresponding P5CR1 bit is cleared to “0”, and as an output if its corresponding P5CR1

bit is set to “1”. During reset, P5CR1 is initialized to “0”, which configures port P5 as an

input. The P5 output latches are also initialized to “1”. Data is written into the output latch

regardless of the P5CR1 contents. Therefore initial output data should be written into the

output latch before setting P5CR1.

Port P5 is also used as is also used as AD converter analog input, a pulse width

modulation (PWM) output external interrupt input, timer/counter input, serial bus

interface input/output, and an on screen display (OSD) output (I signal). When used as a

secondary function input pin except I²C bus interface input/output, the input pins should

be set to the input mode. When used as a secondary function output pin except I²C bus

interface input/output, the output pins should be set to the output mode and beforehand

the output latch should be set to “1”. When P52 and P51 are used as I²C bus interface

input/output, P5CR2 bits should be set to the sink open-drain mode, the output latches

should be set to “1”, and the output pins should be set to the output mode. When P57 is used

as an OSD output pin, the output pin should be set to the output mode and beforehand the

port 6 data selection register (PIDS) should be clear to “0”. When used as port P5, the port 6

data selection register (PIDS) should be set to “1”.

Note: Input mode port is read the state of input pin. When input/output mode is used mixed,

the contents of output latch setting input mode may be changed by executing bit

manipulation instructions.

2007-09-12

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TMP88CS38B/CM38B/CP38B

STOP

OUTEN

Analog input

AINDS

SAIN

STOP

P5iCR1

OUTEN

P5jCR1

Data input

B

A

Y

D

Q

Data output

D

Q

Data output

S

P5i

P5j

Output latch

I

PIDS

(b) P56 to P54

(a) P57

STOP

OUTEN

Analog input

AINDS

SAIN

P5lCR1

STOP

OUTEN

P5kCR1

Data input

Control input

P5lCR2

Data input

Control input

D

Q

Data output

D

Q

Data output

P5l

Output latch

P5k

Output latch

Control output

(c) P53

(d) P52 to P51

STOP

OUTEN

P5mCR1

Data input

Control input

D

Q

Data output

P5m

Output latch

Control output

(d) P50

7

6

5

4

3

2

1

0

P57

I

P56

AIN3

P55

AIN2

P54

AIN1

P53

INT2

TC1

P52

SO1

SDA1

P51

P50

P5

PWM9

SL1

SLC1

PWM8

INT0

TC2

(00005H)

(Initial value: 1111 1111)

(Initial value: 0000 0000)

SCK1

AIN0

7

6

5

4

3

2

1

0

P5CR1

(00008H)

P57CR1 P56CR1 P55CR1 P54CR1 P53CR1 P52CR1 P51CR1 P50CR1

0: Input mode

Write

only

P5CR1

7

I/O Control for P5

5

1: Output mode

2

6

4

3

1

0

PSELCR

(00FFEH)

“0”

P35CR2 P34CR2

“0”

P52CR2 P51CR2

(Initial value: 0*00 *00*)

0: Skin open drain

1: Tri-state

Write

only

P5CR2

7

I/O Control for P5

6

5

4

3

2

1

ORP6S

(00FBAH)

P67S

P66S

P65S

P64S

PIDS

YBLCS

MPXS

(Initial value: 0000 0000)

0: The OSD output (I)

1: Port P57 output latch

Selection of the output data

for port P57

Write

only

PIDS

Note 1: *: Don’t care, i = 7, j = 6 to 4, k = 3, l = 2 to 1, m = 0.

Note 2: P5CR1 cannot be used the read-modify-write instructions.

(Bit manipulation instructions such as SET, CLR, etc. and logical operation such as ADN, OR, etc.)

Note 3: Clear bit7, 6 and 3 to “0” in PSELCR.

Figure 2.2.5 Ports P5

2007-09-12

88CS38B-50

TMP88CS38B/CM38B/CP38B

2.2.5

Port P6 (P67 to P60)

Port P6 is an 8-bit input/output port which can be configured as an input or an output in

one-bit unit under software control. Input/output mode is selected by the corresponding bit

in the port P6 input/output control register (P6CR). Port P6 is configured as an input if its

corresponding P6CR bit is cleared to “0”, and as an output if its corresponding P6CR bit is

set to “1” and P6nS bit is set to “1”. P63 to P60 are sink open-drain ports. During reset,

P6CR is initialized to “0”, which configures port P6 as an input. The P6 output latches are

also initialized to “1”.

Data is written into the output latch regardless of the P6CR contents. Therefore initial

output data should be written into the output latch before setting P6CR.

Port P6 is used as an on screen display (OSD) output (R, G, B and Y/BL signal)/input

(RIN, GIN BIN, Y/BLIN signal), a test video signal output and AD converter analog input.

When used as a test video signal output pin, the output pins should be set to the output

mode and beforehand the signal control register (SGEN) should be set to “1”. When used as

a secondary function input, the input pins should be set to the input mode. When used as

an OSD output pin, the output pins should be set to the output mode and beforehand the

port P6 data selection register (P67S to P64S) should be clear to “0”. When used as port P6,

the signal control register (P67 to P64) should be set to “1”.

Note: Input mode port is read the state of input pin. When input/output mode is used mixed,

the contents of output latch setting input mode may be changed by executing bit

manipulation instructions.

Example: Sets the lower 4 bits (P63 to P60) in port P6 to the output mode, and the other bit to the input mode.

LD

(P6CR), 0FH

;

P6CR ← 00001111B

2007-09-12

88CS38B-51

TMP88CS38B/CM38B/CP38B

STOP

OUTEN

P6iCR

P63CR

Data input

RIN

A

B

Y

D

Q

Data output

D

Q

Data output

P6i

Output latch

P63

S

R, G, B, Y/BL

P6iS

Output latch

(a) P67 to P64

(b) P63

STOP

OUTEN

Analog input

AINDS

P62CR

SAIN

STOP

OUTEN

P6jCR

Data input

GIN

Data input

BIN, Y/BLIN

A

Y

D

Q

Data output

P62

Output latch

D

Q

Data output

B

S

CSOUT

SGEN

P6j

Output latch

(c) P62

(b) P61 to P60

7

6

5

4

3

2

1

0

P67

Y/BL

P66

B

P65

G

P64

R

P63

RIN

P62

GIN

CSOUT

P61

BIN

AIN5

P60

Y/BLIN

AIN4

P6

(Initial value: 1111 1111)

(Initial value: 0000 0000)

(00006H)

7

6

5

4

3

2

1

0

P6CR

(0000DH)

P67CR P66CR P65CR P64CR P63CR P62CR P61CR P60CR

0: Input mode

Write

only

P6CR

I/O Control for port P6

1: Output mode

2

7

6

5

4

3

1

0

SGCR

(00FE6H)

SGEN SGVBLK SGPAL

SGIV

SGCHS

SGPAT

(Initial value: 0000 0000)

0: Disable

Write

only

SGEN

Function selection

1: Enable

2

7

6

5

4

3

1

ORP6S

(00FBAH)

P67S

P66S

P65S

P64S

PIDS

YBLCS

MPXS

(Initial value: 0000 0000)

0: The OSD output (R, G, B, Y/BL)

1: Port P6i output latch

Selection of the output data

for port P6i

Write

only

P67S to P64S

Note 1: *: Don’t care, i = 7 to 4, j = 1 to 0.

Note 2: P6CR and ORP6S cannot used with the read-modify-write instructions. (Bit manipulations such as SET,

CLR, etc. and logical operation such as AND, OR, etc.)

Note 3: Clear bit2 and 0 to “0” in TVSCR

Figure 2.2.6 Ports P6, P6CR, and P67S to P64S

2007-09-12

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TMP88CS38B/CM38B/CP38B

2.2.6

Port P7 (P71 to P70)

Port P7 is a 2bit input/output port, and is also used as a vertical synchronous signal ( VD)

input and a horizontal synchronous signal ( HD ) input for the on screen display (OSD)

circuitry.

The output latches, are initialized to “1” during reset. When used as an input port or a

secondary function pin, the output latch should be set to “1”.

When a read instruction for port P7 is executed, bits 7 to 2 in P7 are read in as undefined

data.

STOP

OUTEN

P7iCR

Data input

HD , VD

D

Q

Data output

P7i

Output latch

7

6

5

4

3

2

1

0

P71

VD

P70

HD

P7

(Initial value: **** **11)

(Initial value: **** **00)

(00007H)

7

6

5

4

2

1

0

P7CR

(00009H)

P71CR P70CR

0: Input mode

Write

only

P7CR

I/O Control for P7

1: Output mode

Note: *: Don’t care, i = 1 to 0

Figure 2.2.7 Ports P7

2007-09-12

88CS38B-53

TMP88CS38B/CM38B/CP38B

2.3 Time Base Timer (TBT)

The time base timer generates time base for key scanning, dynamic displaying, etc. It also

provides a time base timer interrupt (INTTBT). The time base timer is controlled by a control

register (TBTCR) shown in Figure 2.3.1.

An INTTBT is generated on the first falling edge of source clock (the divider output of the

timing generator) after the time base timer has been enabled. The divider is not cleared by the

program; therefore, only the first interrupt may be generated ahead of the set interrupt period.

The interrupt frequency (TBTCK) must be selected with the time base timer disabled (When

the time base timer is changed from enabling to disabling, the interrupt frequency can’t be

changed.)

Both frequency selection and enabling can be performed simultaneously.

Example: Sets the time base timer frequency to fc/2¹⁶[Hz] and enables an INTTBT interrupt.

LD

(TBTCR), 00000010B

(TBTCR), 00001010B

(EIRL). 6

;

TBTCK = “010”

TBTEN = “1”

LD

SET

MPX

INTTBT

interrupt

request

fc/2²³, fc/2²⁴

fc/2²¹, fc/2²²

fc/2¹⁶, fc/2¹⁷

fc/2¹⁴, fc/2¹⁵

fc/2¹³, fc/2¹⁴

fc/2¹², fc/2¹³

fc/2¹¹, fc/2¹²

fc/2⁹, fc/2¹⁰

A

B

C

D

E

F

Source clock

Rising

edge

detector

Y

TBTEN

INTTBT

G

H

S

3

Interrupt

period

TBTCK

TBTEN

Enable TBT

TBTCR

Time base timer control register

(a) Configuration

(b) Time base timer interrupt

Figure 2.3.1 Time Base Timer

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7

6

5

4

3

2

1

0

TBTCR

(00036H)

“0”

−

“0”

TBTEN

TBTCK

(Initial value: 0**0 0***)

0: Disable

1: Enable

Time base timer

enable/disable

TBTEN

NORMAL, IDLE mode

DV1CK = 0

DV1CK = 1

fc/2²⁴[Hz]

fc/2²²

fc/2¹⁷

fc/2¹⁵

fc/2¹⁴

fc/2¹³

fc/2¹²

fc/2¹⁰

fc/2²³[Hz]

fc/2²¹

fc/2¹⁶

fc/2¹⁴

fc/2¹³

fc/2¹²

fc/2¹¹

fc/2⁹

000

001

010

011

100

101

110

111

Write

only

Time base timer interrupt

frequency select

TBTCK

Note 1: fc: High-frequency clock [Hz], *: Don’t care

Note 2: TBTCR is a write-only register and must not be used with any of read-modify-write

instruction.

Note 3: Set bit7 and 4 in TBTCR to “0”.

Figure 2.3.2 Time Base Timer and Divider Output Control Register

Table 2.3.1 Time Base Timer Interrupt Frequency (Example: at fc = 16MHz)

Time Base Timer Interrupt Frequency [Hz]

TBTCK

NORMAL, IDLE Mode

DV1CK = 0

DV1CK = 1

000

001

010

011

100

101

110

111

1.90

7.62

0.95

3.81

244.14

976.56

1953.12

3906.25

7812.50

31250

122.07

488.28

976.56

1953.12

3906.25

15625

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2.4 Watchdog Timer (WDT)

The watchdog timer is a fail-safe system to rapidly detect the CPU malfunctions such as

endless looping caused by noise or the like, or deadlock and resume the CPU to the normal

state.

The watchdog timer signal for detecting malfunction can be selected either a reset output or a

pseudo non-maskable interrupt request. However, selection is possible only once after reset. At

first the reset output is selected.

When the watchdog timer is not being used for malfunction detection, it can be used as a

timer to generate an interrupt at fixed intervals.

Note: Care must be given in system design so as to protect the watchdog timer from disturbing

noise. Otherwise the watchdog timer may not fully exhibit its functionality.

2.4.1

Watchdog Timer Configuration

Reset release signal from T.G.

MPX

fc/2²³, fc/2²⁴

A

B

C

D

R

Binary counters

Overflow

fc/2²¹, fc/2²²

fc/2¹⁹, fc/2²⁰

fc/2¹⁷, fc/2¹⁸

Clock

Reset output

Y

WDT output

1

2

Q

S

RESET

S

Clear

Interrupt request

2

INTWDT

Internal reset

Q

S

R

WDTEN

00034H

Writing

disable code

Writing

clear code

WDTT

WDTOUT

Controller

00035H

WDTCR2

WDTCR1

MPX: Multiplexer

T.G.: Timing generator

Watchdog timer control registers

Figure 2.4.1 Watchdog Timer Configuration

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2.4.2

Watchdog Timer Control

Figure 2.4.2 shows the watchdog timer control registers (WDTCR1, WDTCR2). The

watchdog timer is automatically enabled after reset.

(1) Malfunction detection methods using the watchdog timer

The CPU malfunction is detected at follows.

1. Setting the detection time, selecting output, and clearing the binary counter.

2. Repeatedly clearing the binary counter within the setting detection time.

Note: The watchdog timer consists of an internal divider and two-stage binary counter.

Writing the clear code (4E ) clears the binary counter, but not the internal divider.

H

The minimum overflow time for the binary counter might be three quarters of the

WDTCR1 (WDTT) time setting depending on when the clear code (4E ) is written

H

into the WDTCR2 register. So, write the clear code on a cycle which is shorter than

that minimum overflow time.

If the CPU malfunctions such as endless looping or deadlock occur for any cause, the

watchdog timer output will become active at the rising of an overflow from the binary

counters unless the binary counters are cleared. At this time, when WDTOUT = 1 a

reset is generated, which drivers the RESET pin low to reset the internal hardware

and the external circuit. When WDTOUT = 0, a watchdog timer interrupt (INTWDT) is

generated.

The watchdog timer temporarily stops counting in STOP mode including warm-up or

IDLE mode, and automatically restarts (Continues counting) when the STOP/IDLE

mode is released.

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Example: Sets the watchdog timer detection time to 2²¹/fc [s] and resets the CPU malfunction.

LD

(WDTCR2), 4EH

; Clears the binary counters

(WDTCR1), 00001101B ; WDTT ← 10, WDTOUT ← 1

(WDTCR2), 4EH

; Clears the binary counters

Within 3/4 of WDT

detection time

(always clear immediately before and after changing WDTT)

LD

; Clears the binary counters

Within 3/4 of WDT

detection time

Watchdog Timer Register 1

7

6

5

4

3

2

1

0

WDTCR1

(00034H)

WDTEN

WDTOUT

WDTT

(Initial value: **** 1001)

0: Disable (It is necessary to write the disable code to

WDTCR2)

Watchdog timer

enable/disable

WDTEN

1: Enable

NORMAL mode

DV1CK = 0

²⁵/fc

DV1CK = 1

2²⁶/fc

Write

only

2

00

Watchdog timer

detection time [s]

WDTT

2²³/fc

2²¹/fc

2¹⁹/fc

2²⁴/fc

2²²/fc

2²⁰/fc

01

10

11

0: Interrupt request

1: Reset output

Watchdog timer

output select

WDTOUT

Note 1: WDTOUT cannot be set to “1” by program after clearing WDTOUT to “0”.

Note 2: fc: High-frequency clock [Hz], *: Don’t care

Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions.

Note 4: The watchdog timer must be disabled or the counter must be cleared immediately before entering to the

STOP mode. When the counter is cleared, the counter must be cleared again immediately after releasing

the STOP mode.

Note 5: Just right before disabling the watchdog timer, disable the acceptance of interrupts (DI) and clear the

watchdog timer.

If the watchdog timer is disabled under conditions other than the above, the proper operation cannot be

guaranteed.

Watchdog Timer Register 2

7

6

5

4

3

2

1

0

WDTCR2

(Initial value: **** ****)

(00035H)

4E : Watchdog timer binary counter clear (Clear code)

H

Write

only

Watchdog timer control

code write register

WDTCR2

B1 : Watchdog timer disable (Disable code)

H

Others: Invalid

Note 1: The disable code is invalid unless written when WDTEN = 0.

Note 2: *: Don’t care

Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.

Note 4: Clears the binary counter does not clear the source clock.

It is recommended that the time to clear is set to 3/4 of the detecting time.

Note 5: The watchdog timer counter must be disabled by writing the disable code (B1 ) to WDRCR2 after writing

H

WDTCR2 to. “4E ”.

H

Figure 2.4.2 Watchdog Timer Control Registers

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(2) Watchdog timer enable

The watchdog timer is enabled by setting WDTEN (Bit3 in WDTCR1) to “1”.

WDTEN is initialized to “1” during reset, so the watchdog timer operates immediately

after reset is released.

Example: Disables watchdog timer

LDW

(WDTCR1), 00001000B

;

WDTEN ← 1

(3) Watchdog timer disable

To disable the watchdog timer, clear the interrupt mask enable flag (IMF) to “0” and

write the clear code (4E ) into WDTCR2. Then, clear WDTEN (Bit3 in WDTCR1) to “0”.

H

When WDTEN is “0”, the watchdog timer is disabled by writing the disable code (B1 )

H

into WDTCR2. If WDTEN is cleared to “0” after the disable code has been written into

WDTCR2, the watchdog timer is not disabled. While it is disabled, its binary counter is

cleared.

Example:

DI

;

Disables interrupt acceptance.

Clears the watchdog timer.

Disables the watchdog timer.

Enables interrupt acceptance.

LD

LDW

EI

(WDTCR2), 4EH

(WDTCR1), B101H

Table 2.4.1 Watchdog Timer Detection Time (Example: fc = 16 MHz)

Watchdog Timer Detection Time [s]

WDTT

NORMAL Mode

DV1CK = 0

DV1CK = 1

00

01

10

11

2.097

4.194

1.048

524.288 m

131.072 m

32.768 m

262.1

65.5

m

2.4.3

Watchdog Timer Interrupt (INTWDT)

This is a pseudo non-maskable interrupt which can be accepted regardless of the

contents of the EIR. If a watchdog timer interrupt or a software interrupt is already

accepted, however, the new watchdog timer interrupt waits until the previous interrupt

processing is completed (the end of the [RETN] instruction execution).

The stack pointer (SP) should be initialized before using the watchdog timer output as an

interrupt source with WDTOUT.

Example: Watchdog timer interrupt setting up

LD

SP, 023FH

;

Sets the stack pointer

(WDTCR1), 00001000B

WDTOUT ← 0

2.4.4

Watchdog Timer Reset

If the watchdog timer output becomes active, a reset is generated, which drivers the

RESET pin (Sink open-drain input/output with pull-up) low to reset the internal hardware.

The reset output time is about 8/fc to 24/fc [s] (0.5 to 1.5 μs at fc = 16.0 MHz).

Note: If there is any fluctuation in the oscillation frequency at the start of clock oscillation, the

reset time includes error. Thus, regard the reset time as an approximate value.

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2¹⁹/fc [s]

2¹⁷/fc

(WDTT = 11 )

B

Clock

Binary counter

1

2

3

0

1

2

0

3

Overflow

INTWDT interrupt

WDT reset output

(High-Z)

(“L” output)

Writes 4E to WDTCR2

H

Figure 2.4.3 Watchdog Timer Interrupt/Reset

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2.5 16-Bit Timer/Counter 1 (TC1A)

2.5.1

Configuration

Figure 2.5.1 Timer/Counter 1

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2.5.2

Control

The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two

16-bit timer registers (TC1DRA and TC1DRB).

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TC1DRA

(00010, 00011H)

TC1DRA (00011H)

TC1DRA (00010H)

L

H

Read/Write

TC1DRB

(00012, 00013H)

TC1DRB (00013H)

TC1DRB (00012H)

L

H

Read only

7

6

5

4

3

2

1

0

ACPAP1

MCAP1

METT1

MPPG1

TC1CR

Read/Write

“0”

TC1S

TC1CK

TC1M

(00014H)

(Initial value: 0000 0000)

00: Timer/external trigger timer/event counter mode

01: Window mode

10: Pulse width measurement mode

11: Reserved

TC1M

TC1 operating mode select

NORMAL, IDLE mode

DV7CK = 0, DVCK = 00

DV1CK = 0

DV1CK = 1

fs/2¹²

TC1CK TC1 source clock select [Hz]

00

01

10

11

fc/2¹¹

fc/2⁷

fc/2³

fc/2⁸

fc/2⁴

R/W

External clock (TC1 pin input)

Timer Extend Event Window Pulse PPG

00: Stop and counter clear

01: Command start

10: External trigger start at the rising edge

11: External trigger start at the falling edge

○

×

○

×

○

×

○

×

○

×

○

×

○

TC1S

TC1 start control

×

ACAP1 Auto-capture control

0: Auto-capture disable

0: Double edge capture

1: Auto-capture enable

Pulse width measurement

MCAP1

1: Single edge capture

mode control

External trigger timer

METT1

0: Trigger start

1: Trigger start and stop

mode control

Note 1: fc: High-frequency clock [Hz]

Note 2: The timer register consists of two shift registers. A value set in the timer register is put in effect at the rising

edge of the first source clock pulse that occurs after the upper data (TC1DRAH) are written. Therefore, the

lower byte must be written before the upper byte (It is recommended that a 16-bit access instruction be

used in writing). Writing only the lower data (TC1DRAL) does not put the setting of the timer register in

effect.

Note 3: Set the mode, source clock PPG control and timer F/F control when TC1 stops (TC1S = 00).

Note 4: Auto capture can be used in only timer, event counter, and window modes.

Note 5: Values to be loaded to timer registers must satisfy the following condition.

TC1DRA > TC1DRB, TC1DRA > 1

Note 6: Always write “0” to TFF1 except PPG output mode.

Note 7: On entering STOP mode, the TC1 start control (TC1S) is cleared to “00” automatically. So, the timer stops.

Once the STOP mode has been released, to start using the timer counter, set TC1S again.

Note 8: In the Auto-capture function, when the capture value is read after stop and clear counter or Auto-capture

disable is executed by the TC1 start control (TC1S), the correct capture value might not be able to be

read.When using Auto-capture function, set capture to enable.

Note 9: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting

TC1CR<ACAP1> to “1”. Therefore, to read the captured value, wait at least one cycle of the internal source

clock before reading TC1DRB for the first time.

Figure 2.5.2 Timer registers and TC1 control register

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2.5.3

Function

Timer/counter 1 has five operating modes: Timer, external trigger timer, event counter,

window, pulse width measurement.

(1) Timer mode

In this mode, counting up is performed using the internal clock. The contents of

TC1DRA are compared with the contents of up counter. If a match is found, an INTTC1

interrupt is generated, and the counter is cleared to “0”. Counting up resumes after the

counter is cleared. The current contents of up counter can be transferred to TC1DRB

by setting ACAP1 (Bit6 in TC1CR) to “1” (Software capture function). (Auto-capture

function)

Table 2.5.1 Source Clock (Internal clock) for Timer/Counter 1 (Example: at fc = 16.0 MHz)

NORMAL, IDLE Mode

DV1CK = 0

DV1CK = 1

TC1CK

Maximum Time

Resolution [μs]

Setting [s]

00

01

10

128.0

8.0

8.39

256.0

16.0

1.0

16.78

0.524

1.049

0.5

32.77 m

65.54 m

Example 1: Sets the timer mode with source clock fc/2¹¹[Hz] and generates an interrupt 1 later (at fc = 16 MHz)

LDW

DI

(TC1DRA), 1E84H

;

Sets the timer register (1 s ÷ 2¹¹/fc = 1E84H)

SET

EI

(EIRL). 4

;

Enable INTTC1

LD

(TC1CR), 00000000B

(TC1CR), 00010000B

;

Selects the source clock and mode

Starts TC1

LD

Example 2: Auto capture

LD

:

(TC1CR), 01010000B

;

ACAP1 ← 1 (Capture)

:

Wait at least one cycle of the internal source clock

Reads the capture value

LD

WA, (TC1DRB)

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Count start

Source clock

Up counter

TC1DRA

0

?

1

2

3

4

n − 1 n

0

1

2

3

4

5

6

7

n

Match detect

Counter clear

INTTC1 interrupt

(a) Timer mode

Source clock

Up counter

m − 2

m − 1

m

m + 1

m + 2

n − 1

n

n + 1

Capture

m

Capture

n n + 1

TC1DRB

ACAP1

?

m − 1

m + 1

m + 2

n − 1

(b) Auto capture

Figure 2.5.3 Timer Mode Timing Chart

(2) External trigger timer mode

In this mode, counting up is started by an external trigger. This trigger is the edge of

the TC1 pin input. Either the rising or falling edge can be selected with TC1S. Source

clock is an internal clock. The contents of TC1DRA is compared with the contents of up

counter. If a match is found, an INTTC1 interrupt is generated, and the counter is

cleared to “0” and halted. The counter is restarted by the selected edge of the TC1 pin

input.

When METT1 (Bit6 in TC1CR) is “1”, inputting the edge to the reverse direction of

the trigger edge to start counting clears the counter, and the counter is stopped.

Inputting a constant pulse width can generate interrupts. When METT1 is “0”, the

reverse directive edge input is ignored. The TC1 pin input edge before a match

detection is also ignored.

The TC1 pin input has the noise rejection; therefore, pulses of 7/fc [s] or less are

rejected as noise. A pulse width of 13/fc [s] or more is required for edge detection in

NORMAL or IDLE mode.

Example 1: Detects rising edge in TC1 pin input and generates an interrupt 100 μs later. (at fc = 16.0 MHz,

DV1CK = 1)

LDW

DI

(TC1DRA), 0064H

;

100 μs ÷ 2⁴/fc = 64H

SET

EI

(EIRL). 4

;

INTTC1 interrupt enable

LD

(TC1CR), 00001000B

(TC1CR), 00101000B

;

Selects the source clock and mode

LD

TC1 external trigger start, METT1 = 0

Example 2: Generates an interrupt, inputting “L” level pulse (Pulse width: 4 ms or more) to the TC1 pin. (at fc =

16.0 MHz, DV1CK = 1)

LDW

DI

(TC1DRA), 00FAH

;

4 ms ÷ 2⁸/fc = FAH

SET

EI

(EIRL). 4

;

INTTC1 interrupt enable

LD

(TC1CR), 00000100B

(TC1CR), 01110100B

;

Selects the source clock and mode

LD

TC1 external trigger start, METT1 = 1

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Count start

TC1S = 10 at the

rising edge

TC1 pin input

Internal clock

0

1

2

3

4

n

1

2

3

0

n − 1

Up counter

TC1DRA

n

Match detect

Counter clear

INTTC1

interrupt

(a) Trigger start (METT1 = 0)

TC1S = 10

at the rising

edge

Count start

Counter clear

Count start

TC1 pin input

Internal clock

0

1

2

3

m − 1

1

2

3

n

0

n − 1

m

Up counter

TC1DRA

n

Match detect

Counter clear

INTTC1

interrupt

(b) Trigger start and stop (METT1 = 1)

m < n

Figure 2.5.4 External Trigger Timer Mode Timing Chart

(3) Event counter mode

In this mode, events are counted at the edge of the TC1 pin input (Either the rising

or falling edge can be selected with the external trigger TC1CR<TC1S>). The contents

of TC1DRA are compared with the contents of up counter. If a match is found, an

INTTC1 interrupt is generated, and the counter is cleared.

Match detect is executed on other edge of count-up. A match can not be detected and

INTTC1 is not generated when the pulse is still in same state.

Setting ACAP1 to “1” transfers the current contents of up counter to TC1DRB

(Auto-capture function).

Count start

TC1S = 10

at the falling

edge

TC1 pin input

Up counter

TC1DRA

0

1

n

1

2

0

n − 1

n

?

Match detect

Counter clear

INTTC1 interrupt

Figure 2.5.5 Event Counter Mode Timing Chart

Table 2.5.2 Input Pulse Width for Timer/Counter 1

Minimum Pulse Width [s]

NORMAL/IDLE

“H” Width

“L” Width

2³/fc

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(4) Window mode

Counting up is performed on the rising edge of the pulse that is the logical AND-ed

product of the TC1 pin input (Window pulse) and an internal clock. The contents of

TC1DRA are compared with the contents of up counter. If a match is found, an INTTC1

interrupt is generated, and the counter is cleared. Positive or negative logic for the TC1

pin input can be selected with bit4 or 5 in TC1CR.

It is necessary that the maximum applied frequency be such that the counter value

can be analyzed by the program. That is; the frequency must be considerably slower

than the selected internal clock.

Count start

Command start

Count stop

Count start

TC1 pin input

Internal clock

Up counter

TC1DRA

0

1

2

3

4

5

6

7

0

1

2

3

n

?

Match detect

Counter clear

INTTC1 interrupt

(a) Positive logic (at TC1S = 10)

Count start Count stop

Command start

Count start

TC1 pin input

Internal clock

Up counter

TC1DRA

7

6

0

1

2

3

4

5

8

9

0

1

9

?

Match detect

Counter clear

INTTC1 interrupt

(a) Negative logic (at TC1S = 11)

Figure 2.5.6 Window Mode Timing Chart

(5) Pulse width measurement mode

In this mode, counting is started by the external trigger (Set to external trigger start

by TC1CR). The trigger can be selected either the rising or falling edge of the TC1 pin

input. The source clock is used an internal clock. On the next falling (rising) edge, the

counter contents are transferred to TC1DRB and an INTTC1 interrupt is generated.

The counter is cleared when the single edge capture mode is set. When double edge

capture is set, the counter continues and, at the next rising (falling) edge, the counter

contents are again transferred to TC1DRB. If a falling (rising) edge capture value is

required, it is necessary to read out TC1DRB contents until a rising (falling) edge is

detected. Falling or rising edge is selected with the external trigger TC1S (Bit4 or 5 in

TC1CR), and single edge or double edge is selected with MCAP1 (Bit6 in TC1CR).

Note 1:Be sure to read the captured value from TC1DRB before the next trigger edge is

detected. If fail to read it, it becomes undefined. It is recommended that a 16-bit access

instruction be used to read from TC1DRB.

Note 2:If either the falling or rising edge is used in capturing values, the counter stops at “1”

after a value has been captured until the next edge is detected. So, the value captured

next will become “1” larger than the value captured right after capturing starts.

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Note 3: In the Pulse width measurement mode, the capture value of the first time after the timer

starts might not be a correct value. Thus, execute the dummy read once.

Example: Duty measurement (Resolution fc/2⁷[Hz] DV1CK = 0)

CLR

(INTTC1SW). 0

;

INTTC1 service switch initial setting:

Clears bit0 of INTTC1SW. This bit is inverted by

CPL instruction before INTTC1 is generated.

LD

DI

(TC1CR), 00000110B

(EIRL). 4

;

Sets the TC1 mode and source clock

SET

EI

Enables INTTC1

LD

(TC1CR), 00100110B

Starts TC1 with an external trigger at MCAP1 = 0

.

PINTTC1:

SINTTC1:

CPL

JRS

LD

(INTTC1SW). 0

F, SINTTC1

;

Complements INTTC1 service switch

WA, (TC1DRBL)

Reads TC1DRB (“H” level pulse width)

Lower address in TC1DRBL: TC1DRB

LD

(HPULSE), WA

RETI

LD

WA, (TC1DRBL)

(WIDTH), WA

;

Reads TC1DRB (Period)

LD

.

RETI

;

Duty calculation

Sets INTTC1

.

VINTTC1:

DW

PINTTC1

WIDTH

HPULSE

TC1 pin

INTTC1

INTTC1SW

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Figure 2.5.7 Pulse Width Measurement Mode Timing Chart

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2.6 16-Bit Timer/Counter 2 (TC2A)

2.6.1

Configuration

MPX

TC2S

Port

(Note)

TC2 pin

H

Window

Clear

B

A

fc/2²³or fc/2²⁴

fc/2¹³or fc/2¹⁴

fc/2⁸or fc/2⁹

fc/2³or fc/2⁴

A

B

C

D

Timer/

event counter

Y

16-bit up counter

Source

clock

Y

S

TC2M

INTTC2

interrupt

CMP

S

3

TC2S

TC2CK

TC2DR

MPX: Multiplexer

CMP: Comparator

TC2CR

TC2 control register

16-bit timer register 2

Note:

Propagation of control input/output requires the correct I/O port setting. For details, see the section on I/O

ports.

Figure 2.6.1 Timer/Counter 2 (TC2)

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2.6.2

Control

The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a

16-bit timer register 2 (TC2DR). Reset does not affect TC2DR.

15

7

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TC2DR

(00016H, 00017H)

TC2DRH (00017H)

TC2DRL (00016H)

Read/Write

6

5

4

3

2

1

0

TC2CR

(00015H)

TC2S

TC2CK

TC2M

(Initial value: **00 00*0)

TC2

0: Timer/event counter mode

1: Window mode

TC2M

operating mode select

NORMAL1/2, IDLE1/2 mode

DV1CK = 0

DV1CK = 1

000

001

010

011

100

101

110

111

fc/2²³

fc/2¹³

fc/2²⁴

fc/2¹⁴

fc/2⁸

fc/2³

fc/2⁹

fc/2⁴

TC2

Write

only

TC2CK

source clock select [Hz]

Reserved

External clock (TC2 pin input)

TC2

start control

0: Stop and counter clear

1: Start

TC2S

Note 1: fc: High-frequency clock [Hz], *: Don’t care.

Note 2: Writing to the lower byte of timer register 2 (TC2DRL), the comparison is inhibited until the upper byte

(TC2DRH) is written. After writing to the upper byte, any match during 1 machine cycle (Instruction

execution cycle) is ignored.

Note 3: Set the mode and source clock when the TC2 stops (TC2S = 0).

Note 4: Values to be loaded to timer registers must satisfy the following condition.

TC2DR > 1

Note 5: TC2CR are write-only registers and must not be used with any of the read-modify-write instructions.

Note 6: When STOP mode is started, timer counter is stopped and cleared. Set TC2S to “1” after STOP mode is

released for restarting timer counter.

Figure 2.6.2 Timer Registers 2 and TC2 Control Register

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2.6.3

Function

The timer/counter 2 has three operating modes: Timer, event counter and window modes.

(1) Timer mode

In this mode, the internal clock is used for counting up. The contents of TC2DR are

compared with the contents of up counter. If a match is found, a timer/counter 2

interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed

after the counter is cleared.

Table 2.6.1 Source Clock (Internal clock) for Timer/Counter 2 (at fc = 16.0 MHz)

NORMAL, IDLE mode

DV1CK = 0

DV1CK = 1

TC2CK

Maximum

Time Setting

Maximum

Time Setting

Resolution

000

001

010

011

100

101

524.3 [ms]

512.0 [μs]

16.0 [μs]

0.5 [μs]

9.54 [h]

33.6 [s]

1.05 [s]

1.02 [ms]

32.0 [μs]

1.0 [μs]

Reserved

19.1 [h]

1.12 [min]

2.09 [s]

32.8 [ms]

Reserved

65.5 [ms]

Reserved

Example: Sets the source clock fc/2⁴[Hz] and generates an interrupt event 25 ms (at fc = 16 MHz, DV1CK = 1)

LDW

DI

(TC2DR), 61A8H

;

Sets TC2DR (25 ms ÷ 2⁴/fc = 61A8H)

SET

EI

(EIRH).6

;

Enable INTTC2 interrupt

LD

(TC2CR), 00001100B

(TC2CR), 00101100B

;

Selects TC2 source clock

Starts TC2

LD

Count start

Source clock

Up counter

n − 1

0

1

2

3

4

n

0

1

2

3

Match detect

Counter clear

Timer trigger

n

INTTC2 interrupt

Figure 2.6.3 Timer Mode Timing Chart

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(2) Event counter mode

In this mode, events are counted on the rising edge of the TC2 pin input. The

contents of TC2DR are compared with the contents of the up counter. If a match is

found, an INTTC2 interrupt is generated, and the counter is cleared. The minimum

pulse width to the TC2 pin is shown in Table 2.6.2. Two or more machine cycles are

required for both the “H” and “L” levels of the pulse width. Match detect is executed on

the falling edge of the TC2 pin. A match can not be detected and INTTC2 is not

generated when the pulse is still in a falling state.

Example: Sets the event counter mode and generates an INTTC2 interrupt 640 counts later.

LDW

DI

(TC2DR), 640

;

Sets TC2DR

SET

EI

(EIRH). 6

;

Enables INTTC2 interrupt

LD

(TC2CR), 00011100B

(TC2CR), 00111100B

;

Selects TC2 source clock

Starts TC2

LD

Table 2.6.2 Timer/Counter 2 External Clock Source

Minimum Pulse Width [S]

NORMAL, IDLE Mode

“H” Width

“L” Width

2³/fc

Count start

TC2 pin input

Up counter

n

0

1

2

3

n − 1

Match detect

1

2

3

Counter clear

Timer register

n

INTTC2 interrupt

Figure 2.6.4 Event Counter Mode Timing Chart

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(3) Window mode

In this mode, counting up performed on the rising edge of an internal clock during

TC2 external pin input (window pulse) is “H” level. The contents of TC2DR are

compared with the contents of up counter. If a match found, an INTTC2 interrupt is

generated, and the up counter is cleared.

The maximum applied frequency (TC2 input) must be considerably slower than the

selected internal clock.

Example: Generates an interrupt, inputting “H” level pulse width of 120 ms or more. (at fc = 16.0 MHz, DV1CK

= 1)

LDW

DI

(TC2DR), 0075H

;

Sets TC2DR (120 ms ÷ 2¹⁴/fc = 0075H)

SET

EI

(EIRH). 6

;

Enables INTTC2 interrupt

LD

(TC2CR), 00000101B

(TC2CR), 00100101B

;

Selects TC2 source clock

Starts TC2

LD

TC2 pin input

Internal clock

Up counter

TC2DR

0

1

2

n − 3

n − 2

n

0

1

2

3

n − 1

n

Match detect

Counter clear

INTTC2 interrupt

Figure 2.6.5 Window Mode Timing Chart

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2.7 8-Bit Timer/Counter 3 (TC3B)

2.7.1

Configuration

Rising

Edge

TC3S

detector

INTTC3

interrupt

Falling

TC3ES

Clear

TC3 pin

A

B

Y

H

A

B

C

D

E

F

fc/2¹³or fc/2¹⁴

fc/2¹²or fc/2¹³

fc/2¹¹or fc/2¹²

fc/2¹⁰or fc/2¹¹

fc/2⁹or fc/2¹⁰

fc/2⁸or fc/2⁹

fc/2⁷or fc/2⁸

Source clock

Overfolw

Comparator

Match detect

TC3S

8-bit up counter

Y

A

B

Y

G

S

Capture

3

Capture

TC3DRB

TC3DRA

TC3CK

8-bit timer register

ACAP

TC3S

TC3M

TC3CR

TC3 control register

Note: Propagation of control input/output requires the correct I/O port setting. For details, see the section on I/O ports.

Figure 2.7.1 Timer/Counter 3 (TC3)

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2.7.2

Control

The timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two

8-bit timer registers (TC3DRA and TC3DRB) and port multiplex control register

(PMPXCR).

7

6

5

4

3

2

1

0

TC3DRA

(0018H)

TC3DRB

(0019H)

Read/Write (Initial value: 1111 1111)

Read only (Initial value: 1111 1111)

6

5

4

3

2

1

0

TC3CR

ACAP

TC3S

TC3K

TC3M

(Initial value: *0*0 0000)

(001AH)

TC3

0: Timer/event counter

1: Capture

TC3M

operating mode select

NORMAL, IDLE mode

DV1CK = 0

fc/2¹³

fc/2¹²

fc/2¹¹

fc/2¹⁰

fc/2⁹

DV1CK = 1

fc/2¹⁴

000

001

010

011

100

101

110

111

fc/2¹³

fc/2¹²

fc/2¹¹

fc/2¹⁰

fc/2⁹

fc/2⁸

TC3

TC3CK

source clock select [Hz]

Write

only

fc/2⁸

fc/2⁷

External clock (TC3 pin input)

TC3

start control

0: Stop and clear

1: Start

TC3S

ACAP

0:

−

Auto-capture control

1: Auto-capture enable

Note 1: fc: High-frequency clock [Hz], *: Don’t care.

Note 2: Set the mode and source clock when the TC3 stops (TC3S = 0).

Note 3: Values to be loaded to timer register 3A must satisfy the following condition

TC3DRA > 0 (in the timer and event counter mode).

Note 4: Auto-capture can be used only int the timer and event counter mode.

Note 5: Before setting TC3DRA or switching the operation mode, stop the TC3 (TC3S = 0).

Note 6: When STOP mode is started, timer counter is stopped and TC3 start control (TC3S) is cleared to “0”

automatically. Set TC3S to “1” after STOP mode is released for restarting timer counter.

Note 7: TC3CR, TCESCR is a write-only register and must not be used with any of the read-modify-write

instructions.

7

6

5

4

3

2

1

0

PMPXCR

(0027H)

“0”

CHS

TC4ES TC3ES

(Initial value: 00** **00)

0: Normal

1: Invert

Write

only

TC3ES

TC3 input control

Note 8 Always write “0” to bit7 in PMPXCR.

Figure 2.7.2 Timer Registers 3 and TC3 Control Register

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2.7.3

Function

The timer/counter 3 has three operating modes: timer, event counter, and capture mode.

When it is used in the capture mode, the noise rejection time of TC3 pin input can be set

by remote control receive control register.

(1) Timer mode

In this mode, the internal clock is used for counting up. The contents of TC3DRA are

compared with the contents of up counter. If a match is found, a timer/counter 3

interrupt (INTTC3) is generated, and the up counter is cleared. The current contents of

up counter are loaded into TC3DRB by setting ACAP (Bit6 in TC3CR) to “1”

(Auto-capture function).

The contents of up counter can be easily confirmed by executing the read instruction

(RD instruction) of TC3DRB. Loading the contents of up counter is not synchronized

with counting up. The contents of over flow (FFH) and 00H can not be loaded correctly.

It is necessary to consider the count cycle.

Clock

Counter

FE

FF

00

01

FE

FF/00

01

TC3DRB

Table 2.7.1 Source Clock (Internal clock) for Timer/Counter 3 (Example: at fc = 16.0 MHz)

NORMAL, IDLE Mode

DV1CK = 0

DV1CK = 1

TC3CK

Maximum Setting

Resolution [μs]

Time [ms]

000

001

010

011

100

101

110

512

256

128

64

130.6

65.3

32.6

16.3

8.2

1024

512

256

128

64

261.1

130.6

65.3

32.6

16.3

8.2

32

16

4.1

32

8

2.0

16

4.1

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Count start

Source clock

Up counter

0

?

1

2

3

4

n − 1 n

0

1

2

3

4

5

6

7

Timer register B

n

Match detect

Counter clear

INTTC3 interrupt

(a) Timer mode

Source clock

Up counter

m − 2

m − 1

m

m + 1

m + 2

n − 1

n

n + 1

Capture

m

Capture

n n + 1

Timer register B

ACAP1

?

m − 1

m + 1

m + 2

n − 1

(b) Auto capture

Figure 2.7.3 Timer Mode Timing Chart

(2) Event counter mode

In this mode, the TC3 pin input pulses are used for counting up Either the rising on

falling edge can be selected with TC3ES (Bit0 in PMPXCR). The contents of TC3DRA

are compared with the contents of the up counter. If a match is found, an INTTC3

interrupt is generated and the counter is cleared. Match detect is executed on the

falling edge of the TC3 pin. A match can not be detected, and INTTC3 is not generated

when the pulse is still in a falling state.

The maximum applied frequency is shown in Table 2.7.2. Two or more machine

cycles are required for both the high and low levels of the pulse width.

The current contents of up counter are loaded into TC3DRB by setting ACAP (Bit6 in

TC3CR) to “1” (Auto-capture function).

The contents of up counter can be easily confirmed by executing the read instruction

(RD instruction) of TC3DRB. Loading the contents of up counter is not synchronized

with counting up. The contents of over flow (FFH) and 00H can not be loaded correctly.

It is necessary to consider the count cycle.

Example: Generates an interrupt every 0.5 s, inputting 50 Hz pulses to the TC3 pin.

LD

(TC3CR), 00001110B

(TC3DRA), 19H

;

Sets TC3 mode and source clock

0.5 s ÷ 1/50 = 25 = 19H

Starts TC3

(TC3CR), 00011100B

Table 2.7.2 Source Clock (External clock) for Timer/Counter

Minimum Applied Frequency [Hz]

NORMAL, IDLE Mode

“H” Width

“L” Width

2²/fc

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Count start

TC3 pin input

Up counter

n

0

1

2

3

n − 1

1

2

3

Match detect

Counter clear

Timer register

n

INTTC3 interrupt

Figure 2.7.4 Event Counter Mode Timing Chart

(3) Capture mode

In this mode, the pulse width, period and duty of the TC3 pin input are measured in

this mode, which can be used in decoding the remote control signals or distinguishing

AC 50/60 Hz, etc. The TC3 pin input can have its polarity changed between normal and

inverse by using the TC3ES Register.

a. If TC3ES = “0” (Non-inverting input)

Once command operation has started, the counter free-runs on an internal

source clock.

When the falling edge of the TC3 pin input is detected, the counter value is

loaded into TC3DRB. When the rising edge is detected, the counter value is loaded

into TC3DRA, and the counter is cleared, generating an INTTC3 interrupt.

If the rising edge is detected right after command operation has started, no

capture to TC3DRB and an INTTC3 interrupt occurs only on capture to TC3DRA.

If a read instruction is executed for TC3DRB, the value that exists at the end of

the previous capture (immediately after a reset, “FF”) is read.

b. If TC3ES = “1” (Inverse input)

Once command operation has started, the counter free-runs on an internal

clock.

When the rising edge of the TC3 pin input is detected, the counter value is

loaded into TC3DRB. When the falling edge is detected, the counter value is

loaded into TC3DRA, and the counter is cleared, generating an INTTC3 interrupt.

If the falling edge is detected right after command operation has started, the

counter value is not captured into TC3DRB and an INTTC3 interrupt occurs only

on capture to TC3DRA. If a read instruction is executed for TC3DRB, the value

that exists at end of the previous capture (immediately after a reset, “FF”) is read.

The minimum acceptable input pulse width is equal to the length of one source

clock period selected by TC3CR <TC3CK>.

Table 2.7.3 TC3INV-based Capture Input Edges

TC3ES

Capture into TC3DRB

Capture into TC3DRA

INTTC3 Interrupt

“0”

Falling edge

Rising edge

Falling edge

(Non-inverting input)

“1”

Rising edge

(Inverting input)

Note: Capture of the TC3 pin input requires at least 1 cycle of the selected source clock.

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Figure 2.7.5 Capture Mode Timing Chart

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The edge of TC3 pin input is detected in the remote control receive circuit with noise

rejection. The remote control receive circuit is controlled by the remote control receive

control register (RCCR). The remote control receive status register (RCSR) can monitor

the polarity selection and noise rejection circuit.

Rising

Polarity

select

Noise reject circuit

(5-bit up-down counter)

Capture

control

Edge detector

TC3IN

MPX

A

Falling

fc/2⁸or fc/2⁹

TC3

B

Y

S

Source clock

5

RCSCK

RPOLS

RCNC

RCNF

RCOVF

RNCM

RCCR/RCSR

Remote control receive control/status register

MPX: Multiplexer

Figure 2.7.6 Remote Control Receiving Circuit

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TMP88CS38B/CM38B/CP38B

RCCR

(00026H) RCEN RPOLS RCSCK

RCNC

(Initial value: 0001 1111)

Noise reject time select

Write

only

RCNC

(Source clock) × (RCNC − 1) [s]

02H ≤ RCNC ≤ 1FH

NORMAL, IDLE mode

Noise reject cricuit

Source clock select

DV1CK = 0

DV1CK = 1

RCSCK

R/W

0

2⁸/fc

2⁹/fc

1

TC3CK

(Note 2)

Remote control signal polarity

select

0: Positive

1: Negative

0: Disable

1: Enable

RPOLS

RCEN

Write

only

Remote control receive circuit

operation control

Note 1: Set RPOLS and RCSCK when the timer/counter stops (TC3S = 0).

Note 2: Source clock of timer/counter 3.

Note 3: fc: High-frequency clock [Hz], *: Don’t care

Note 4: RCCR includes a write-only register and must not be used with any of read-modify-write instructions.

Note5: Values to be loaded to RCNC must satisfy the following condition (02 ≤ RCNC ≤ 1F).

RCSR

(00026H) RCNF RPOLS RCSCK RCOVF RNCM

(Initial value: 0000 0***)

Remote control signal monitor

after noise rejector

0: Low level

1: High level

RNCM

Read

only

0: Signal and definition by overwriting the noise reject

time RCNC

Noise reject circuit overflow

flag

RCOVF

1: Overflow

NORMAL, IDLE mode

Noise reject circuit

Source clock Select

DV1CK = 0

DV1CK = 1

RCSCK

0

2⁸/fc

2⁹/fc

R/W

1

TC3CK

(Note 2)

Remote control signal polarity

select

0: Positive

1: Negative

0: Without noise

1: With noise

RPOLS

RCNF

Remote control signal monitor

after noise rejctor

Read

only

Note 1: Reading out the register RCSR resets RCNF and RCOVF.

Note 2: Source clock of timer/counter 3

Note 3: When a 5-bit up-down counter counts down to “0” after counting up, the RCNF defines to be noise.

Note 4: fc: High-frequency clock [Hz], *: Don’t care.

Figure 2.7.7 Remote Control Rceive Control Register and Remote Control Receive Status Register

Table 2.7.4 Combination between The Polarity and The Edge Selection

TC3 Pin Input Pulse

RPOLS

Measurement

(Interrupt occurrence is shown as allow.)

0

1

Note: When TC3CK is used in RCSCK, do not select an external clock to the TC3CK.

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Figure 2.7.8 Remote Control Receive Circuit Timing Chart

88CS38B-82

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TMP88CS38B/CM38B/CP38B

2.8 8-Bit Timer/Counter 4 (TC4)

2.8.1

Configuration

TC4S

fc/2¹¹or fc/2¹⁰

A

B

C

D

fc/2⁷or fc/2⁸

fc/2⁵or fc/2⁶

fc/2³or fc/2⁴

Source

clock

Clear

Overfolw

detect

8-bit up counter

Y

TC4ES

Comparator

A S

H

TC4 pin

Match

detect

Y

S

B

3

TC4CK

TC4S TC4M

2

INTTC4

interrupt

request signal

TC4CR

TC4DR

8-bit timer register 4

Timer/counter 4 control register

Note:

Set the input/output control correctly for the substitutive input/output pins. For details, see the description of

the input/output port control register.

Figure 2.8.1 Timer/Counter 4 (TC4)

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2.8.2

Control

The timer/counter 4 is controlled by a timer/counter 4 control register (TC4CR) and an

8-bit timer register 4 (TC4DR). Reset does not affect TC4DR.

7

6

5

4

3

2

1

0

TC4DR

(0001BH)

Write only (Initial value: 1111 1111)

5

3

TC4CR

(0001CH)

TC4S

TC4CK

TC4M

Write only (Initial value: **00 0000)

00: Timer/event counter mode

01: Reserved

TC4S

TC4CK

TC4M

TC4 start control

10: Reserved

11: Reserved

NORMAL, IDLE mode

DV1CK = 0

DV1CK = 1

000

001

010

fc/2¹¹

fc/2⁷

fc/2⁵

fs/2¹²

fs/2⁸

fs/2⁶

fs/2⁴

TC4 source clock select [Hz]

(Note 4)

R/W

011

100

101

110

fc/2³

Reserved

111

External clock (TC4 pin input)

00: Timer/event counter mode

01: Reserved

TC4 operating mode select

10: Reserved

11: Reserved

Note 1: fc: High-frequency clock [Hz], *: Don’t care

Note 2: Values to be loaded to the timer register must satisfy the following condition (1 ≤ TC4DR ≤ 255).

Note 3: When the TC4 is started (TC4S = 0 → 1) or disabled (TC4S = 1 → 0) or while the TC4 is operating (TC4S =

1 → 1), do not write to TC4M and TC4CK in TC4CR. If these registers are selected/changed during these

operations, counting up is not performed properly.

Note 4: When STOP mode is started, timer counter is stopped and cleared. Set TC4S to “1” after STOP mode is

released for restarting timer counter.

Note 5: Undefined values are read from bits 6 and 7 of TC4CR.

Note 6: Do not change TC4DR while the TC4 is operating.

7

6

5

4

3

2

1

0

PMPXCR

(00027H)

“0”

CHS

TC4ES (TC3ES) (Initial value: 00** **00)

0: Rising edge

1: Falling edge

Write

only

TC4ES

TC4 edge select

Note 1: TC4CR, TC4DR and PMPXCR are write only register and must not be used with any of the

read-modify-write instructions such as SET, CLR, etc.

Figure 2.8.2 Timer Register 4 and TC4 Control Register

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2.8.3

Function

The timer/counter 4 has two operating modes: timer, event counter mode.

(1) Timer mode

In this mode, the internal clock is used for counting up. The contents of TC4DR are

compared with the contents of up counter. If a match is found, an INTTC4 interrupt is

generated and the up counter is cleared to “0”. Counting up resumes after the up

counter is cleared.

Table 2.8.1 Source Clock (Internal clock) for Timer/Counter 4 (Example: at fc = 16.0 MHz)

NORMAL, IDLE mode

DV1CK = 0

DV1CK = 1

TC4CK

Maximum Setting

Resolution [μs]

Time [ms]

000

001

010

100

128.0

8.0

32.6

2.0

256.0

16.0

4.0

65.3

4.1

2.0

0.510

0.128

1.0

0.5

1.0

0.255

(2) Event counter mode

In this mode, the TC4 pin input (External clock) pulse is used for counting up. Either

the rising or falling edge can be selected with TC4ES (Bit1 PMPXCR). The contents of

TC4DR are compared with the contents of the up counter. If a match is found, an

INTTC4 interrupt is generated and the counter is cleared. The maximum applied

frequency is shown Table 2.8.2. Two or more machine cycles are required for both the

high and low level of the pulse width.

Note: The event counter mode can only be used in NORMAL or IDLE mode.

Table 2.8.2 Timer/Counter 4 External Clock Source

Minimum Input Pulse Width [s]

NORMAL1, IDLE1 Mode

“H” Width

“L” Width

2³/fc

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2.9 Serial Bus Interface (SBI-ver. D)

The TMP88CS38B and TMP88CM38B/CP38B has a 1-channel serial bus interface which

employs a clocked-synchronous 8-bit serial bus interface and an I²C bus (a bus system by

Philips). The serial bus interface pins are selectively used as either channel 0 or channel 1.

The serial interface is connected to external devices through P35 (SDA0)/P52 (SDA1) and P34

(SCL0)/P51 (SCL1) in the I²C bus mode; and through P53 (SCK1 ), P52 (SO1) and P51 (SI1) in

the clocked-synchronous 8-bit SIO mode.

The serial bus interface pins are also used for the P3/P5 port. When used for serial bus

interface pins, set the P3/P5 output latches of these pins to “1”. When not used as serial bus

interface pins, the P3/P5 port is used as a normal I/O port.

Note 1: When P3 and P5 is used as serial bus interface pins, P35, P34, P51 and P50 should be set

as a sink open-drain output by clearing PSELCR to “0”.

Note 2: The I²C of TMP88CS38B and TMP88CM38B/CP38B can be used only in the standard mode

of I²C. The fast mode and the high speed mode can not be used.

2.9.1

Configuration

INTSBI interrupt request

SCL

SCK

P53

( SCK )

SIO

clock

control

P52

(SDA1/SO1)

Input/

output

control

P51

(SCL1/SI1)

fc/2

fc/4

Source clock

Divider

generator

SO

SI

SIO

data control

Transfer

control

circuit

I²C bus

clock

sync.

+

Noise

canceller

P35

(SDA0)

P34

I²C bus

data

Control

Shift

register

Noise

canceller

SDA

control

(SCL0)

SBICRB/

SBISR

I2CAR

SBIDBR

SBICRA

SBI control register B/ I²C bus

SBI status register address register

SBI data

buffer register

SBI control register A

Figure 2.9.1 Serial Bus Interface (SBI)

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TMP88CS38B/CM38B/CP38B

2.9.2

Control

The following registers are used for control the serial bus interface and monitor the

operation status.

•

Serial bus interface control register A (SBICRA)

Serial bus interface control register B (SBICRB)

Serial bus interface data buffer register (SBIDBR)

I²C bus address register (I2CAR)

Serial bus interface status register A (SBISRA)

Serial bus interface status register B (SBISRB)

Serial clock source control register (SCCRB)

Serial clock control status register (SCSR)

The above registers differ depending on a mode to be used. Refer to section 2.9.7 “I²C Bus

Mode Control” and 2.9.9 “Clocked-synchronous 8-Bit SIO Mode Control”.

2.9.3

Serial Clock Source Control

A serial bus interface circuit can reduce the power consumption by stopping a serial clock

generater.

Serial Clock Source Control Register

7

6

5

4

3

2

1

0

SCCRB

SCEN

(Initial value: 0*** ****)

(00FF1H)

0: Do not generate source clock

1: Generate source clock

Write

only

SCEN

Serial clock source control

Note: When SCRQ and SCEN are “1”, SCEN cannot be cleared to “0”. When SCRQ is “0”, SCEN is cleared to “0”.

Serial Clock Control Status Register

7

6

5

4

3

2

1

0

SCSR

SCRQ

(Initial value: 0*** ****)

(00FF1H)

0: No source clock request from serial bus interface

1: Source clock request from serial bus interface

Read

only

SCRQ

Serial clock source request

SCRQ

SCEN

Source clock

Clock generation

“1” → SCEN Write data except

“00” to SBIM

Write data

“00” to SBIM

“0” → SCEN

Figure 2.9.2 Serial Clock Source

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2.9.4

Channel Select

A serial bus interface circuit can select I/O pin when a serial bus interface is used for I²C

bus mode.

Port Switching Register

7

6

5

4

3

2

1

0

PMPXCR

(00027H)

“0”

CHS

(TC4ES) (TC3ES) (Initial value: 00** **00)

0: Channel 0

1: Channel 1

I²C bus Channel Select

CHS

R/W

Note 1: When SIO mode, don’t use channel 0. Therefore, set to “1” in PMPXCR at SIO mode.

Note 2: Always write “0” to bit7 in PMPXCR.

Note 3: *: Don’t care

Figure 2.9.3 Channel Select

Software Reset

2.9.5

2.9.6

A serial bus interface circuit has a software reset function, when a serial bus interface

circuit is locked by an external noise, etc.

To occur software reset, write “01”, “10” into the SWRST (Bit1, 0 in SBICRB). During

software reset, the SWRMON (Bit0 in SBISRA) is clear to “0”.

The Data Format in The I²C bus Mode

The data format when using the TMP88CS38B and TMP88CM38B/CP38B in the I²C bus

mode are shown in as below.

(a) Addressing format

1

8 bits

1 to 8 bits

Data

1 to 8 bits

Data

R A

C

W K

A

C

K

A

C P

K

S

/

Slave address

1

1 or more

(b) Addressing format (with restart)

8 bits

1

1 to 8 bits

Data

8 bits

1 to 8 bits

Data

R A

A

C S

K

R A

C

W K

A

C P

K

S

/

C

/

Slave address

1

Slave address

W K

1 or more

1

1 or more

(c) Free data format

1

8 bits

Data

1 to 8 bits

Data

1 to 8 bits

Data

A

C

K

A

C

K

A

C P

K

S

1

1 or more

S:

Start condition

R/ W : Direction bit

ACK: Acknowledge bit

P:

Stop condition

Figure 2.9.4 Data Format in I²C Bus Mode

88CS38B-88

2007-09-12

TMP88CS38B/CM38B/CP38B

2.9.7

I²C Bus Mode Control

The following registers are used to control the serial bus interface (SBI) and monitor the

operation status in the I²C bus mode.

Serial Bus Interface Control Register A

SBICRA

7

6

5

4

3

2

1

0

(00020H)

BC

ACK

SCK

(Initial value: 0000 *000)

ACK = 1

ACK = 0

BC

Number of

Bits

clock

000

001

010

011

100

101

110

111

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

9

2

3

4

5

6

7

8

1

2

3

4

5

6

7

Write

only

BC

Number of transferred bits

ACK

Master mode

Slave mode

Not generate a clock

pulse for an

acknowledgement.

Not count a clock pulse

for an acknowledgement.

0

Acknowledgement mode

specification

ACK

R/W

Generate a clock pulse

for an

acknowledgement.

Count a clock pulse for

an acknowledgement.

1

DV1CK = 0

DV1CK = 1

000: Reserved (Note 3)

001: Reserved (Note 3)

010: 58.8 kHz

011: 30.3 kHz

100: 15.4 kHz

000: Reserved

001: Reserved

010: Reserved

011: 60.6 kHz

100: 30.7 kHz

101: 15.5 kHz

(Note 3)

Serial clock selection

Write

only

SCK

(At fc = 16 MHz, output on SCL pin)

101:

110:

7.7 kHz

3.9 kHz

110:

111 : Reserved

Note 1: Set the BC to “000” before switching to 8-bit SIO bus mode.

7.8 kHz

111 : Reserved

Note 2: SBICRA cannot be used with any of read-modify-write instructions such as bit manipulation, etc.

Note 3: This I2C bus circuit does not support the Fast mode. It supports the Standard mode only. Although

the I2C bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the I2C

specification is not guaranteed in that case.

Serial Bus Interface Data Buffer Register

SBIDBR

7

6

5

4

3

2

1

0

(00021H)

(Initial value: **** ****) R/W

Note 1: For writing transmitted data, start from the MSB (Bit7).

Note 2: The data which was written into SBIDBR cannot be read, since a write data buffer and a read buffer are

independent in SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions

such as bit manipulation, etc.

I²C bus Address Register

7

6

5

4

3

2

1

0

Slave address

SA3

I2CAR

(00022H)

ALS

(Initial value: 0000 0000)

SA6

SA5

SA4

SA2

SA1

SA0

SA

Slave address selection

Address recognition mode

specification

Write

only

0: Slave address recognition

1: Non slave address recognition

ALS

Note 1: I2CAR is write-only register and cannot be used with any of read-modify-write instruction such as bit

manipulation, etc.

Note 2: Do not set I2CAR to “00H” to avoid the incorrect response of acknowledgment in slave mode. If “00H” is set

to I2CAR as the slave address and received “01H” in slave mode, the device might transmit the

acknowledgement incorrectly.

Figure 2.9.5 Serial Bus Interface Control Register A, Serial Bus Interface Data Buffer Register

and I²C Bus Address Register In The I²C Bus Mode

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TMP88CS38B/CM38B/CP38B

Serial Bus Interface Control Register B

7

6

5

4

3

2

1

0

SBICRB

(00023H)

MST

TRX

BB

SBIM

SWRST1SWRST0

(Initial value: 0001 0000)

0: Slave

MST

TRX

BB

Master/slave selection

Transmitter/receiver selection

Start/stop generation

1: Master

0: Receiver

1: Transmitter

0: Generate a stop condition when MST, TRX and PIN are “1”.

1: Generate a start condition when MST, TRX and PIN are “1”.

Write

only

0:

−

Cancel interrupt service request

1: Cancel interrupt service request

00: Port mode (Serial bus interface output disable)

01: Clocked synchronous 8-bit SIO mode

10: I²C bus mode

Serial bus interface operating

mode selection

SBIM

11: Reserved

SWRST1

SWRST0

Software reset start bit

Software reset starts by first writing “10” and next writing “01”.

Note 1: Switch a mode to port after confirming that the bus is free.

Note 2: Switch a mode to I²C bus mode or clock synchronous 8-bit SIO mode after confirming that the port is high

level.

Note 3: SBICRB has write-only register and must not be used with any of read-modify-write instructions such as bit

manipulation, etc.

Note 4: When the SWRST (Bit1, 0 in SBICRB) is written to “01”, “10”, software reset (Four machine cycles) is

occurred.

This time, control the serial bus interface and monitor the operation status registers except the SBIM (Bit3,

2 in SBICRB) and the CHS (Bit6 in PMPXCR) are reseted.

Control the serial bus interface and monitor the operation status registers are SBICRA, SBICRB, SBIDBR,

I2CAR, SBISRA, SBISRB, SCCRA and SCSR.

Serial Bus Interface Status Register A

7

6

5

4

3

2

1

0

SBISRA

(00020H)

SWR

MON

ACK

(Initial value: **** ***1)

0: During software reset

Read

only

SWRMON Software reset monitor

1: − (Initial)

*: Don’t care

Serial Bus Interface Status Register B

7

6

5

4

3

2

1

0

SBISRB

(00023H)

MST

TRX

BB

AL

AAS

AD0

LRB

(Initial value: 0001 0000)

0: Slave

Master/Slave selection status

monitor

MST

1: Master

0: Receiver

Transmitter/Receiver selection

status monitor

TRX

BB

1: Transmitter

0: Bus free

Bus status monitor

1: Bus busy

0: Requesting interrupt service

1: Releasing interrupt service request

0: −

Interrupt service requests

status monitor

AL

Read

only

Arbitration lost detection

monitor

1: Arbitration lost detected

0: Not detect slave address match or “GENERAL CALL”

1: Detect slave address match or “GENERAL CALL”

0: Not detect “GENERAL CALL”

Slave address match detection

monitor

AAS

AD0

LRB

“GENERAL CALL” detection

monitor

1: Detect “GENERAL CALL”

0: Last receive bit is “0”

Last Received bit monitor

1: Last receive bit is “1”

Figure 2.9.6 Serial Bus Interface Control Register B and Serial Bus Interface

Status Register A/B in the I²C Bus Mode

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TMP88CS38B/CM38B/CP38B

(1) Acknowledgement mode specification

a. Acknowledgement mode (ACK = “1”)

To set the device as an acknowledgement mode, the ACK (bit4 in SBICRA)

should be set to “1”. When a serial bus interface circuit is a master mode, an

additional clock pulse is generated for an acknowledge signal. In a slave mode, a

clock is counted for the acknowledge signal.

In the master transmitter mode, the SDA pin is released in order to receive an

acknowledge signal from the receiver during additional clock pulse cycle. In the

master receiver mode, the SDA pin is set to low level generation an acknowledge

signal during additional clock pulse cycle.

In a slave mode, when a received slave address matches to a slave address

which is set to the I2CAR or when a “GENERAL CALL” is received, the SDA pin is

set to low level generating an acknowledge signal. After the matching of slave

address or the detection of “GENERAL CALL”, in the transmitter the SDA pin is

released in order to receive an acknowledge signal from the receiver during

additional clock pulse cycle. In a receiver, the SDA pin is set to low level

generation an acknowledge signal during additional clock pulse cycle after the

matching of slave address or the detection of “GENERAL CALL”.

The Table 2.9.1 shows the SCL and SDA pins status in acknowledgement mode.

Table 2.9.1 SCL and SDA Pins Status in Acknowledgement Mode

Mode

Transmitter

Receiver

SCL

An additional clock pulse is generated.

Master

Released in order to receive

and acknowledge signal.

Set to low level generating an

acknowledge signal.

SDA

SCL

A clock is counted for the acknowledge signal.

When slave address

matches or a general

call is detected

Set to low level generating an

acknowledge signal.

−

Slave

SDA

After matching of slave

address or general call

Released in order to receive

an acknowledge signal.

Set to low level generating an

acknowledge signal.

b. Non-acknowledgement mode (ACK = “0”)

To set the device as a non-acknowledgement mode, the ACK should be cleared to

“0”. In the master mode, a clock pulse for an acknowledge signal is not generated.

In the slave mode, a clock for a acknowledge signal is not counted.

(2) Number of transfer bits

The BC (bits 7 to 5 in SBICRA) is used to select a number of bits for next

transmitting and receiving data.

Since the BC is cleared to “000” as a start condition, a slave address and direction bit

transmissions are always executed in 8 bits. Other than these, the BC retains a

specified value.

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TMP88CS38B/CM38B/CP38B

(3) Serial clock

a. Clock source

The SCK (bits 2 to 0 in SBICRA) is used to select a maximum transfer frequency

output from the SCL pin in the master mode. Set a communication baud rate that

meets the I2C bus specification, such as the shortest pulse width of tLOW, based

on the equations shown below.

Four or more machine cycles are required for both high and low levels of pulse

width in the external clock which is input from SCL pin.

Note: Since the I²C of TMP88CS38B AND TMP88CM38B/CP38B can not be used

as the Fast mode and the High Speed mode, do not set SCK as the frequency

that is over 100 kHz.

This I²C bus circuit does not support high-speed mode, it supports standard mode only.

Set the baud rates, which have been calculated according to the formula below, to meet

the specifications of the I2C bus, such as the smallest pulse width of t_LOW,

t

LOW

1/fscl

HIGH

n

SCK

(Bits 2 to 0 in the SBICRA)

DV1CK = 0

DV1CK = 1

t

= 2ⁿ/fc

= 2ⁿ/fc + 8/fc

LOW

000

001

010

011

100

101

110

4

5

6

7

8

5

6

7

8

9

HIGH

fscl = 1/(t

Low

+ t

)

HIGH

9

10

11

fc: High-frequency clock

Figure 2.9.7 Clock Source

b. Clock synchronization

In the I²C bus mode, in order to drive a bus with a wired AND, a master device

which pulls down a clock pulse to low will, in the first place, invalidate a clock

pulse of another master device which generates a high-level clock pulse.

The serial bus interface circuit has a clock synchronization function. This

function ensures normal transfer even if there are two or more masters on the

same bus.

The example explains clock synchronization procedures when two masters

simultaneously exist on a bus.

SCL pin (Master 1)

SCL pin (Master 2)

SCL (Bus)

wait

Count start

Count reset

a

b

c

Figure 2.9.8 Clock Synchronization

As master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of

the bus becomes the low level. After detecting this situation, master 2 resets

counting a clock pulse in the high level and sets the SCL pin to the low level.

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TMP88CS38B/CM38B/CP38B

Master 1 finishes counting a clock pulse in the low level at point “b” and sets the

SCL pin to the high level. Since master 2 holds the SCL line of the bus at the low

level, master 1 waits for counting a clock pulse in the high level. After master 2

sets a clock pulse to the high level at point “c” and detects the SCL line of the bus

at the high level, master 1 starts counting a clock pulse in the high level. Then,

the master, which has finished the counting a clock pulse in the high level, pulls

down the SCL pin to the low level.

The clock pulse on the bus is deteminded by the master device with the shortest

high-level period and the master device with the longest low-level period from

among those master devices connected to the bus.

(4) Slave address and address recognition mode specification

When the serial bus interface circuit is used with an addressing format to recognize

the slave address, clear the ALS (Bit0 in I2CAR) to “0”, and set the SA (Bits 7 to 1 in

I2CAR) to the slave address.

When the serial bus interfac circuit is used with a free data format not to recognize

the slave address, set the ALS to “1”. With a free data format, the slave address and the

direction bit are not recognized, and they are processed as data from immediately after

start condition.

(5) Master/slave selection

To set a master device, the MST (Bit7 in SBICRB) should be set to “1”. To set a slave

device, the MST should be cleared to “0”.

When a stop condition on the bus or an arbitration lost is detected, the MST is

cleared to “0” by the hardware.

(6) Transmitter/receiver selection

To set the device as a transmitter, the TRX (Bit6 in SBICRB) should be set to “1”. To

set the device as a receiver, the TRX should be cleared to “0”. When data with an

addressing format is transferred in the slave mode, the TRX is set to “1” by a hardware

if the direction bit (R/ W ) sent from the master device is “1”, and is cleared to “0” by a

hardware if the bit is “0. In the master mode, after an acknowledge signal is returned

from the slave device, the TRX is cleared to “0” by a hardware if a transmitted direction

bit is “1”, and is set to “1” by a hardware if it is “0”. When an acknowledge signal is not

returned, the current condition is maintained.

When a stop condition on the bus or an arbitration lost is detected, the TRX is

cleared to “0” by the hardware. The following table show TRX changing conditions in

each mode and TRX value after changing.

Mode

Direction Bit

Conditions

TRX after Changing

“0”

“1”

“0”

“1”

“0”

“1”

“0”

Slave

mode

A received slave address is the

same value set to I2CAR

Master

mode

ACK signal is returned

When a serial bus interface circuit operates in the free data format, a slave address

and a direction bit are not recognized. They are handled as data just after generating a

start condition. The TRX is not changed by a hardware.

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TMP88CS38B/CM38B/CP38B

(7) Start/stop condition generation

When the BB (Bit5 in SBICRB) is “0”, a slave address and a direction bit which are

set to the SBIDBR are output on a bus after generating a start condition by writing “1”

to the MST, TRX, BB and PIN. It is necessary to set transmitted data to the SBIDBR

and set “1” to ACK beforehand.

SCL pin

SDA pin

1

2

3

4

5

6

7

8

9

A6

A5

A4

A3

A2

A1

A0

R/ W

slave address and the direction bit

Start

condition

Acknowledge

signal

Figure 2.9.9 Start Condition Generation and Slave Address Generation

When the BB is “1”, sequence of generating a stop condition is started by writeng “1”

to the MST, TRX and PIN, and “0” to the BB. Do not modify the contents of MST, TRX,

BB and PIN until a stop condition is generated on a bus.

SCL pin

SDA pin

Stop condition

Figure 2.9.10 Stop Condition Generation

When a stop condition is generated and the SCL line on a bus is pulled down to low

level by another device, a stop condition is generated after releasing the SCL line.

The bus condition can be indicated by reading the contents of the BB (Bit5 in

SBISRB). The BB is set to “1” when a start condition on a bus is detected and is cleared

to “0” when a stop condition is detected.

(8) Interrupt service request and cancel

When a serial bus interface circuit is in the master mode and transferring a number

of clocks set by the BC and the ACK is complete, a serial bus interface interrupt

request (INTSBI) is generated.

In the slave mode, the conditions of generating INTSBI are follows:

•

At the end of acknowledge signal when the received slave address matches to the

value set by the I2CAR

•

At the end of acknowledge signal when a “GENERAL CALL” is received

At the end of transferring or receiving after matching of slave address or receiving

of “GENRAL CALL”

When a serial bus interface interrupt request occurs, the PIN (Bit4 in SBISR) is

cleared to “0”. During the time that the PIN is “0”, the SCL pin is pulled down to low

level.

Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN to “1”.

The time from the PIN being set to “1” until the SCL pin is released takes t

.

LOW

Although the PIN (Bit4 in SBICRB) can be set to “1” by the program, the PIN can not

be cleared to “0” by the program.

Note: If the arbitration lost occurs, when the slave address does not match, the PIN is not

cleared to “0” even thought INTSBI is generated.

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(9) Serial bus interface operating mode selection

The SBIM (Bit3 and 2 in SBICRB) is used to specify a serial bus interface operation

mode.

Set the SBIM to “10” in order to change a operation mode to I²C bus mode. Before

changing operation mode, confirm serial bus interface pins in a high level. And switch

a mode to port after confirming that a bus is free.

(10) Arbitration lost detection monitor

Since more than one master device can exist simultaneously on a bus in the I²C bus

mode, a bus arbitration procedure is implemented in order to guarantee the contents of

transferred data.

Data on the SDA line is used for bus arbitration of the I²C bus.

The following shows an example of a bus arbitration procedure when two master

devices exist simultaneously on a bus. Master 1 and master 2 output the same data

until point “a”. After master 1 outputs “1” and master 2, “0”, the SDA line of a bus is

wired AND and the SDA line is pulled-down to the low level by master 2. When the

SCL line of a bus is pulled up at point “b”, the slave device reads data on the SDA line,

that is data in master 2.

Data transmitted from master 1 becomes invalid. The state in master 1 is called

“arbitration lost”. A master device which loses arbitration releases the SDA pin and

the SCL pin in order not to effect data transmitted from other masters with arbitration.

When more than one master sends the same data at the first word, arbitration occurs

continuously after the second word.

SCL (Bus)

SDA pin (Master 1)

SDA pin (Master 2)

SDA (Bus)

SDA pin becomes “1” after losing arbitration.

b

a

Figure 2.9.11 Arbitration Lost

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The serial bus interface circuit compares levels of a SDA line of a bus with its those

SDA pin at the rising edge of the SCL line. If the levels are unmatched, arbitration is

lost and the AL (Bit3 in SBISRB) is set to “1”.

When the AL is set to “1”, the MST and TRX are cleared to “0” and the mode is

switched to a slave receiver mode.

The AL is cleared to “0” by writing or reading data to or from the SBIDBR or writing

data to the SBICRB.

SCL pin

SDA pin

SCL pin

SDA pin

AL

1

2

3

4

5

6

7

8

9

1

2

3

Master

A

D7A

D6A

D5A

D4A

D3A

D2A

D1A

D0A

D7A’ D6A’ D5A’

1

2

3

4

5

6

7

8

9

Master

B

Stop clock output

Releasing SDA pin and SCL pin to high level as losing arbitration.

D7B

D6B

MST

TRX

Accessed to

SBIDBR or SBICRB

INTSBI

Figure 2.9.12 Example of when a Serial Bus Interface Circuit is a Master B

(11) Slave address match detection monitor

In the slave mode, the AAS (Bit2 in SBISR) is set to “1” when the received data is

“GENERAL CALL” or the received data matches the slave address setting by I2CAR

with an address recognition mode (ALS = 0).

When a serial bus interface circuit operates in the free data format (ALS = 1), the

AAS is set to “1” after receiving the first 1-word of data.

The AAS is cleared to “0” by writing data to the SBIDBR or reading data from the

SBIDBR.

(12) GENERAL CALL detection monitor

The AD0 (Bit1 in SBISR) is set to “1” when all 8-bit received data is “0” immediately

after a start condition in a slave mode. The AD0 is cleared to “0” when a start or stop

condition is detected on a bus.

(13) Last received bit monitor

The SDA value stored at the rising edge of the SCL is set to the LRB (Bit0 in

SBISRB). In the acknowledge mode, immediately after an INTSBI interrupt request is

generated, an acknowledge signal is read by reading the contents of the LRB.

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TMP88CS38B/CM38B/CP38B

2.9.8

Data Transfer of I²C Bus

(1) Device initialization

For initialization of device, set the ACK in SBICRA to “1” and the BC to “000”.

Specify the data length to 8 bits to count clocks for an acknowledge signal. Set a

transfer frequency to the SCK in SBICRA.

Next, set the slave address to the SA in I2CAR and clear the ALS to “0” to set an

addressing format.

After confirming that the serial bus interface pin is high level, for specifying the

default setting to a slave receiver mode, clear “0” to the MST, TRX and BB in SBICRB,

set “1” to the PIN, “10” to the SBIM, and “00” to bits SWRST1 and SWRST0.

Note: The initialization of a serial bus interface circuit must be complete within the time

from all devices which are connected to a bus have initialized to and device does

not generate a start condition. If not, the data can not be received correctly because

the other device starts transferring before an end of the initialization of a serial bus

interface circuit.

(2) Start condition and slave address generation

Confirm a bus free status (when BB = 0).

Set the ACK to “1” and specify a slave address and a direction bit to be transmitted to

the SBIDBR.

By writing “1” to the MST, TRX, BB and PIN, the start condition is generated on a

bus and then, the slave address and the direction bit which are set to the SBIDBR are

output. An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle,

and the PIN is cleared to “0”. The SCL pin is pulled down to the low level while the PIN

is “0”. When an interrupt request occurs the TRX changes by the hardware according

to the direction bits only when an acknowledge signal is returned from the slave device.

Note 1: Do not write a slave address to be output to the SBIDBR while data is transferred. If

data is written to the SBIDBR, data to been outputting may be destroyed.

Note 2: The bus free must be confirmed by software within 98.0 μs (the shortest

transmitting time according to the I²C bus standard) after setting of the slave

address to be output. Only when the bus free is confirmed, set “1” to the MST, TRX,

BB, and PIN doesn’t finish within 98.0 μs, the other masters may start the

transferring and the slave address data written in SBIDBR may be broken.

SCL pin

SDA pin

2

3

4

5

6

7

8

9

1

R/ W

A6

A5

A4

A3

A2

A1

A0

Acknowledge

signal from a

slave device

Start condition

Slave address + direction bit

INTSBI

interrupt

request

Figure 2.9.13 Start Condition Generation and Slave Address Transfer

2007-09-12

88CS38B-97

TMP88CS38B/CM38B/CP38B

(3) 1-word data transfer

Check the MST by the INTSBI interrupt process after an 1-word data transfer is

completed, and determine whether the mode is a master or slave.

a. When the MST is “1” (Master mode)

Check the TRX and determine whether the mode is a transmitter or receiver.

1. When the TRX is “1” (Transmitter mode)

Test the LRB. When the LRB is “1”, a receiver does not request data. Implement

the process to generate a stop condition (Described later) and terminate data

transfer.

When the LRB is “0”, the receiver requests next data. When the next

transmitted data is other than 8 bits, set the BC, set the ACK to “1”, and write the

transmitted data to the SBIDBR. After writing the data, the PIN becomes “1”, a

serial clock pulse is generated for transferring a next 1 word of data from the SCL

pin, and then the 1-word data is transmitted. After the data is transmitted, and

an INTSBI interrupt request occurs. The PIN become “0” and the SCL pin is set to

low level. If the data to be transferred is more than one word in length, repeat the

procedure from the LRB test above.

Write to SBIDBR

SCL pin

SDA pin

2

3

4

5

6

7

8

9

1

D7

D6

D5

D4

D3

D2

D1

D0

Acknowledge

signal from a

receiver

INTSBI interrupt

request

Figure 2.9.14 Example of when BC = “000”, ACK = “1”

2. When the TRX is “0” (Receiver mode)

When the next transmitted data is other than of 8 bits, set the BC again. Set the

ACK to “1” and read the received data from the SBIDBR (Reading data is

undefined immediately after a slave address is sent). After the data is read, the

PIN becomes “1”. A serial bus interface circuit outputs a serial clock pulse to the

SCL to transfer next 1 word of data and sets the SDA pin to “0” at the

acknowledge signal timing.

An INTSBI interrupt request occurs and the PIN becomes “0”. Then a serial bus

interface circuit outputs a clock pulse for 1 word of data transfer and the

acknowledge signal each time that received data is read from the SBIDBR.

Read to SBIDBR

SCL pin

SDA pin

1

2

3

4

5

6

7

8

9

D7

D6

D5

D4

D3

D2

D1

D0

New D7

Acknowledge

signal to a

transmitter

INTSBI interrupt

Figure 2.9.15 Example of when BC = “000”, ACK = “1”

2007-09-12

88CS38B-98

TMP88CS38B/CM38B/CP38B

To make the transmitter terminate transmit, clear the ACK to “0” before

reading data which is 1 word before the last data to be received. A serial bus

interface circuit does not generate a clock pulse for the acknowledge signal by

clearing ACK. In the interrupt routine of end of transmission, when the BC is set

to “001” and read the data, PIN is set to “1” and generates a clock pulse for a 1-bit

data transfer. In this case, since the master device is a receiver, the SDA line on a

bus keeps the high level. The transmitter receives the high-level signal as an ACK

signal. The receiver indicates to the transmitter that data transfer is complete.

After 1-bit data is received and an interrupt request has occurred, generates the

stop condition to terminate data transter.

SCL pin

SDA pin

2

3

4

5

6

7

8

1

D7

D6

D5

D4

D3

D2

D1

D0

Acknowledge signal

sent to a transmitter

INTSBI interrupt

request

“001” → BC

Read SBIDBR

“0” → ACK

Read SBIDBR

Figure 2.9.16 Termination of Data Transfer in Master Receiver Mode

b. When the MST is “0” (Slave mode)

In the slave mode, a serial bus interface circuit operateseither in normal slave

mode orin slave mode after losing arbitration.

In the slave mode, the conditions of generating INTSBI are follows:

•

When the received slave address matches to the value set by the I2CAR

When a “GENERAL CALL” is received

At the end of transferring or receiving after matching of slave address or

receiving of “GENERAL CALL”

A serial bus interface circuit changes to a slave mode if arbitration is lost in the

master mode. And an INTSBI interrupt request occurs when word data transfer

terminates after losing arbitration. The behavior of INTSBI and PIN after losing

arbitration are shown in Table 2.9.2.

Table 2.9.2 The Behavior of INTSBI and PIN after Losing Arbitration

When the arbitration occurs during transmission

of slave address as a master

When the arbitration occurs during transmission

of data as a master transmit mode

INTSBI

INTSIB is generated at the terminatin of word data.

When the slave address matches the value set by

I2CAR, the PIN is cleared to “0” by generating of

INTSBI. When the slave address doesn’t match

the value set by I2CAR, the PIN keeps “1”.

PIN keeps “1”.

Check the AL (Bit3 in the SBISR), the TRX (Bit6 in the SBISR), the AAS (Bit2

in the SBISR), and the AD0 (Bit1 in the SBISR) and implements processes

according to conditions listed in Table 2.9.3.

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TMP88CS38B/CM38B/CP38B

Process

Table 2.9.3 Operation in the Slave Mode

Conditions

TRX

AL

AAS AD0

1

0

A serial bus interface circuit loses arbitration

when transmitting a slave address. And

receives a slave address of which the value

of the direction bit sent from another master

is “1”.

Set the number of bits in 1 word to the BC

and write transmitted data to the SBIDBR.

0

1

0

In the slave receiver mode, a serial bus

interface circuit receives a slave address of

which the value of the direction bit sent from

the master is “1”.

In the slave transmitter mode, 1-word data is

transmitted.

Test the LRB. If the LRB is set to “1”, set the

PIN to “1” since the receiver does not

request next data. Then, clear the TRX to “0”

release the bus. If the LRB is set to “0”, set

the number of bits in 1 word to the BC and

write transmitted data to the SBIDBR since

the receiver requests next data.

0

1

1/0

A serial bus interface circuit loses arbitration

when transmitting a slave address. And

receives a slave address of which the value

of the direction bit sent from another master

is “0” or receives a “GENERAL CALL”.

Read the SBIDBR for setting the PIN to “1”

(Reading dummy data) or write “1” to the

PIN.

0

1

0

A serial bus interface circuit loses arbitration

when transmitting a slave address or data.

And terminates transferring word data.

A serial bus interface circuit is changed to

slave mode. To clear AL to “0”, read the

SBIDBR or write the data to SBIDBR.

0

1/0

In the slave receiver mode, a serial bus

interface circuit receives a slave address of

which the value of the direction bit sent from

the master is “0” or receives “GENERAL

CALL”.

Read the SBIDBR for setting the PIN to “1”

(Reading dummy data) or write “1” to the

PIN.

0

1/0

In the slave receiver mode, a serial bus

interface circuit terminates receiving of

1-word data.

Set the number of bits in 1 word to the BC

and read received data from the SBIDBR.

Note: In the slave mode, if the slave address set in I2CAR is “00000000B”, the TRX

changes to “1” by receiving the start byte data “00000001B”.

(4) Stop condition generation

When the BB is “1”, a sequence of generating a stop condition is started by setting “1”

to the MST, TRX, and PIN, and clear “0” to the BB. Do not modify the contents of the

MST, TRX, BB, PIN until a stop condition is generated on a bus.

When a SCL line on a bus is pulled down by other devices, a serial bus interface

circuit generates a stop condition after they release a SCL line.

“1” → MST

“1” → TRX

“0” → BB

Stop condition

“1” → PIN

SCL pin

SDA pin

BB (Read)

Figure 2.9.17 Stop Condition Generation

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TMP88CS38B/CM38B/CP38B

(5) Restart

Restart is used to change the direction of data transfer between a master device and

a slave device during transferring data. The following explains how to restart a serial

bus interface circuit.

Clear “0” to the MST, TRX and BB and set “1” to the PIN. The SDA pin retains the

high level and the SCL pin is released. Since a stop condition is not generated on a bus,

a bus is assumed to be in a busy state from other devices. Test the BB until it becomes

“0” to check that the SCL pin a serial bus interface circuit is released. Test the LRB

until it becomes “1” to check that the SCL line on a bus is not pulled down to the low

level by other devices. After confirming that a bus stays in a free state, generate a start

condition with procedure (2).

In order to meet setup time when restarting, take at least 4.7 μs of waiting time by

software from the time of restarting to confirm that a bus is free until the time to

generate a start condition.

Note: When restarting after receiving in master receiver mode, because the divice doesn’t

send an acknowledgement as a last data, the level of SCL line can not be

conrirmied by reading LRB. Therefore, confirm the status of SCL line by reading

P5PRD register.

“0” → MST

“0” → TRX

“0” → BB

“1” → MST

“1” → TRX

“1” → BB

“1” → PIN

4.7 μs (Min)

Start condition

SCL (Bus)

SCL (Pin)

SDA (Pin)

LRB

BB

Figure 2.9.18 Timing Diagram when Restarting

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TMP88CS38B/CM38B/CP38B

2.9.9

Clocked-synchronous 8-Bit SIO Mode Control

The following registers are used to control the serial bus interface (SBI) and monitor the

operation in the clocked-synchronous 8-bit SIO mode.

Serial Bus Interface Control Register A

SBICRA

7

6

5

4

3

2

1

0

(00020H)

(Initial value: 0000 *000)

SIOS SIOINH

SIOS Indicate transfer start/stop

SIOINH Continue/abort transfer

SIOM

“0”

SCK

0: Stop

1: Start

0: Continue transfer

1: Abort transfer (Automatically cleared after abort)

00: 8-bit transmit mode

01: Reserved

SIOM

Transfer mode select

10: 8-bit transmit/receive mode

11: 8-bit receive mode

Write

only

DV1CK = 0

000: 1000.0 kHz

DV1CK = 1

000: 500.0 kHz

001: 250.0 kHz

010: 125.0 kHz

001: 500.0 kHz

010: 250.0 kHz

011: 125.0 kHz

Serial clock selection

011:

100:

101:

110:

62.5 kHz

31.2 kHz

15.6 kHz

7.8 kHz

(At fc = 16 MHz, Output on SCK

SCK

100:

101:

110:

62.5 kHz

31.2 kHz

15.6 kHz

pin)

111: External clock (Input

from SCK pin)

111: External clock (Input

from SCK pin)

Note 1: fc: High-frequency clock [Hz], *: Don’t care

Note 2: Clear the SIOS to “0” and set the SIOINH to “1” when setting the transfer mode and serial clock.

Note 3: SBICRA is write-only register and cannot be used with any of read-modify-write instructions such as bit

manipulation, etc.

Serial Bus Interface Data Register

SBIDBR

7

6

5

4

3

2

1

0

(00021H)

(Initial value: **** ****) R/W

Note1 : The data which was written into SBIDBR cannot be read, since a write buffer and a read buffer are

independent in SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions

such as bit manipulation, etc.

Note 2: *: Don’t care

Serial Bus Interface Control Register B

SBICRB

7

6

5

4

3

2

1

0

(00023H)

“0”

“1”

SBIM

SWRST1 SWRST0

(Initial value: **** 0000)

00: Port mode (Serial bus interface output disable)

01: SIO mode

10: I²C bus mode

Serial bus interface operation

mode selection

SBIM

Write

only

11: Reserved

SWRST1

SWRST0

Software reset start bit

Software reset starts by first writing “10” and next writing “01”

Note 1: *: Don’t care

Note 2: Switch a mode to port after data transfer is complete.

Note 3: Switch a mode to I²C bus mode or clock synchronous 8-bit SIO mode after confirming that the port is high

level.

Note 4: SBICRB is a write-only register and cannot be used with any of read-modify-write instructions such as bit

manipulation, etc.

Note 5: Clear bit7 to 5 in SBICRB to “0”, and set bit4 to “1”.

Note 6: When the SWRST (Bit1, 0 in SBICRB) is written to “01”, “10”, software reset is occurred.

This time, control the serial bus interface and monitor the operation status registers except the SBIM (Bit3,

2 in SBICRB) and the CHS (Bit6 in PMPXCR) are reseted.

Control the serial bus interface and monitor the operation status registers are SBICRA, SBICRB, SBIDBR,

I2CAR, SBISRA, SBISRB, SCCRA, SCCRB and SCSR.

Figure 2.9.19 Control Register/Data Buffer Register/Status Register in SIO Mode (1)

2007-09-12

88CS38B-102

TMP88CS38B/CM38B/CP38B

Serial Bus Interface Status Register A

SBISRA

7

6

5

4

3

2

1

0

(00020H)

SWR

MON

(Initial value: **** ***1)

0: During software reset

Read

only

SWRMON Software reset monitor

1: − (Initial)

Serial Bus Interface Status Register B

SBISRB

7

6

5

4

3

2

1

0

(00023H)

“1”

SIOF

SEF

“1”

0: Transfer terminated

Serial transfer operating status

monitor

SIOF

SEF

1: Transfer in process

Read

only

0: Shift operation terminated

1: Shift operation in process

Shift operating status monitor

Note: Set bit7 to 4, bit1 and bit0 in SBISRB to “1”.

Figure 2.9.20 Control Register/Data Buffer Register/Status Register in SIO Mode (2)

(1) Serial clock

a. Clock source

The SCK (Bits 2 to 0 in SBICRA) is used to select the following functions.

1. Internal clock

In an internal clock mode, any of seven frequencies can be selected. The serial

clock is output to the outside on the SCK pin. The SCK pin becomes a high level

when data transfer starts. When writing (in the transmit mode) or reading (in the

receive mode) data cannot follow the serial clock rate, an automatic-wait function

is executed to stop the serial clock automatically and hold the next shift operation

until reading or writing is complete.

Automatic-wait function

2

SCK pin output

SO pin output

1

2

3

7

8

1

6

7

8

1

2

3

a

b

c

2

b

0

1

2

5

6

7

1

4

5

6

7

0

1

0

Write transmitted data

a

b

c

Figure 2.9.21 Automatic-wait Function

2. External (SCK = “111”)

An external clock supplied to the SCK pin is used as the serial clock. In order to

ensure shift operation, a pulse width of at least 2-machine cycles is required for

both high and low levels in the serial clock. The maximum data transfer frequency

is 1MHz (fc = 16.0 MHz).

SCK pin

t

SCKL SCKH

Note: tcyc = 4/fc (in NORMAL mode, IDLE mode)

t

, t

SCKL SCKH

> 2 tcyc

Figure 2.9.22 The Maximum Data Transfer Frequency in The External Clock Input

88CS38B-103

2007-09-12

TMP88CS38B/CM38B/CP38B

b. Shift edge

The leading edge is used to transmit data, and the trailing edge is used to

receive data.

1. Leading edge

Data is shifted on the leading edge of the serial clock (at a falling edge of the

SCK pin input/output).

2. Trailing edge

Data is shifted on the trailing edge of the serial clock (at a rising edge of the

SCK pin input/output).

SCK pin

SO pin

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

76543210 *7654321 **765432 ***76543 ****7654 *****765 ******76 *******7

Shift register

(a) Leading edge

SCK pin

SI pin

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Shift register

******** 0******* 10****** 210***** 3210**** 43210*** 543210** 6543210* 76543210

(b) Trailing edge

*: Don’t care

Figure 2.9.23 Shift Edge

(2) Transfer mode

The SIOM (Bits 5 and 4 in SBICRA) is used to select a transmit, receive, or

transmit/receive mode.

a. 8-bit transmit mode

Set a control register to a transmit mode and write transmit data to the

SBIDBR.

After the transmit data is written, set the SIOS to “1” to start data transfer. The

transmitted data is transferred from the SBIDBR to the shift register and output

to the SO pin in synchronous with the serial clock, starting from the least

significant bit (LSB). When the transmit data is transferred to the shift register,

the SBIDBR becomes empty. The INTSBI (Buffer empty) interrupt request is

generated to request new data.

When the internal clock is used, the serial clock will stop and automatic-wait

function will be initiated if new data is not loaded to the data buffer register after

the specified 8-bit data is transmitted. When transmit new data is written,

automatic-wait function is canceled.

When the external clock is used, data should be written to the SBIDBR before

new data is shifted.

The SO pin is “1” from the time transmission starts until the first data bit is

sent. When SIOF becomes “0”, the shift register is cleared. So, output of an

undefined value is not prevented at the start of the next transmission.

The transfer speed is determined by the maximum delay time between the time

when an interrupt request is generated and the time when data is written to the

SBIDBR by the interrupt service program.

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Transmitting data is ended by cleaning the SIOS to “0” by the buffer empty

interrupt service program or setting the SIOINH to “1”. When the SIOS is cleared,

the transmitted mode ends when all data is output. In order to confirm if data is

surely transmitted by the program, set the SIOF (Bit3 in the SBISRB) to be

sensed. The SIOF is cleared to “0” when transmitting is complete. When the

SIOINH is set, transmitting data stops. The SIOF turns “0”.

When the external clock is used, it is also necessary to clear the SIOS to “0”

before new data is shifted; otherwise, dummy data is transmitted and operation

ends.

Clear SIOS

SIOS

SIOF

SEF

SCK pin (Output)

SO pin

a

b

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

INTSBI interrupt

request

SBIDBR

a

b

Write transmitted data

(a) Internal clock

Clear SIOS

SIOS

SIOF

SEF

SCK pin (Input)

SO pin

a

b

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

INTSBI interrupt

request

a

b

SBIDBR

Write transmitted data

(b) External clock

Figure 2.9.24 Transfer Mode

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TMP88CS38B/CM38B/CP38B

Example: Program to stop transmitting data. (When external clock is used.)

STEST1:

TEST

JRS

TEST

JRS

LD

(SBISRB). SEF

F, STEST1

;

If SEF = 1 then loop

If SCK = 0 then loop

SIOS ← 0

STEST2:

(P5). 3

T, STEST2

(SBICRA), 00000111B

SCK pin

SIOF

SO pin

Bit6

Bit7

t

= Min 3.5/fc [s] (in NORMAL mode, IDLE mode)

SODH

Figure 2.9.25 Transmitted Data Hold Time at End of Transmit

b. 8-bit receive mode

Set a control register to a receive mode and the SIOS to “1” for switching to a

receive mode.

Data is received from the SI pin to the shift register in synchronous with the

serial clock, starting from the least significant bit (LSB). When the 8-bit data is

received, the data is transferred from the shift register to the SBIDBR. The

INTSBI (Buffer full) interrupt request is generated to request of reading the

received data. The data is read from the SBIDBR by the interrupt service

program.

When the external clock is used, since shift operation is synchronized with the

clock pulse provided externally, the received data should be read from SBIDBR

before next serial clock is input. If the received data is not read, further data to be

received is canceled.

When the internal clock is used, the automatic wait function is executed until

received data is read from SBIDBR.

The maximum transfer speed when the external clock is used is determined by

the delay time between the time when an interrupt request is generated and the

time when received data is read.

Received data disappears if this data is not completely read before reception of

the next data terminates. In this case, the next data received is read.

Receiving data is ended by clearing the SIOS to “0” by the buffer full interrupt

service program or setting the SIOINH to “1”. When the SIOS is cleared, received

data is transferred to the SBIDBR in complete blocks. The received mode ends

when the transfer is complete. In order to confirm if data is surely received by the

program, set the SIOF (Bit3 in SBIDBR) to be sensed. The SIOF is cleared to “0”

when receiving is complete. After confirming that receiving has ended, the last

data is read. When the SIOINH is set, receiving data stops. The SIOF turns “0”

(the received data becomes invalid, therefore no need to read it).

Note: When the transfer mode is switched, the SBIDBR contents are lost. In case

that the mode needs to be switched, receiving data is concluded by clearing

the SIOS to “0”, read the last data, and then switch the mode.

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TMP88CS38B/CM38B/CP38B

Clear SIOS

SIOS

SIOF

SEF

SCK pin (Output)

SI pin

a

b

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

INTSBI interrupt

request

SBIDBR

a

b

Read received data

Figure 2.9.26 Receive Mode (Example: Internal clock)

c. 8-bit transmit/receive mode

Set a control register to a transmit/receive mode and write data to the SBIDBR.

After the data is written, set the SIOS to “1” to start transmitting/receiving. When

transmitting, the data is output from the SO pin on the leading edges in

synchronous with the serial clock, starting from the least significant bit (LSB).

When receiving, the data is input to the SI pin on the trailing edges of the serial

clock. 8-bit data is transferred from the shift register to the SBIDBR, and the

INTSBI interrupt request occurs. The interrupt service program reads the

received data from the data buffer register and writes data to be transmitted. The

SBIDBR is used for both transmitting and receiving. Transmitted data should

always be written after received data is read.

When the internal clock is used, automatic-wait function is initiated until

received data is read and next data is written.

When the external clock is used, since the shift operation is synchronized with

the external clock, received data is read and transmitted data is written before

new shift operation is executed. The maximum transfer speed when the external

clock is used is determined by the delay time between the time when an interrupt

request is generated and the time when received data is read and transmitted

data is written.

When transmission starts, a value which is the same as the last bit of previously

transmitted data is output from the time SIOF is set to “1” until the falling edge of

SCK occurs.

Transmitting/receiving data is ended by cleaning the SIOS to “0” by the INTSBI

interrupt service program or setting the SIONH to “1”. When the SIOS is cleared,

received data is transferred to the SBIDBR in complete blocks. The

transmit/receive mode ends when the transfer is complete. In order to confirm if

data is surely transmitted/received by the program, set the SIOF (bit 3 in

SBISRB) to be sensed. The SIOF becomes “0” after transmitting/receiving is

complete. When the SIONH is set, transmitting/receiving data stops. The SIOF

turns “0”.

Note: When the transfer mode is switched, the SBIDBR contents are lost. In case

that the mode needs to be switched, conclude transmitting/receiving data by

clearing the SIOS to “0”, read the last data, and then switch the transfer mode.

2007-09-12

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TMP88CS38B/CM38B/CP38B

Clear SIOS

SIOS

SIOF

SEF

SCK pin (Output)

SO pin

SI pin

a

b

d

b

d

b

d

b

d

b

d

b

d

b

d

b

d

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

c

0

1

2

3

4

5

6

7

INTSBI interrupt

request

SBIDBR

a

c

b

d

Write transmitted

data (a)

Read received Write transmitted

data (c) data (b)

Read received

data (d)

Figure 2.9.27 Transmit/Receive Mode (Example: Internal clock)

SCK pin

SIOF

SO pin

Bit6

Bit7 in last transmitted word

t

= Min 4/fc [s] (In NORMAL mode, IDLE mode)

SODH

Figure 2.9.28 Transmitted Data Hold Time at End of Transmit/Receive

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2.10 Remote Control Signal Preprocessor/External Interrupt 3 Input Pin

The remote control signal waveform can be determined by inputting the remote control signal

waveform from which the carrier wave was eliminated by the receive circuit to P30

(INT3/RXIN) pin. When the remote control signal preprocessor/external interrupt 3 pin is also

used as the P30 port, set the P30 port output latch to “1”. When it is not used as the remote

control signal preprocessor/external interrupt 3 input pin, it can be used for normal port.

2.10.1 Configuration

fc/2¹¹

fc/2¹⁰

fc/2⁸

fc/2⁷

fc/2⁶

Receive bit

counter

Receive bit counter value monitor (RBCTM)

fc/2⁵

fc/2²

Selector

RNC

Polarity

select

Interrupt

select

INT3

Interrupt

request

Noise canceller to

INT3/RXIN

RNCM

INT.

EINT

Measurement

width select

8-bit

up counter

Remote control receive

counter register (RXCTR)

Match detect

SRM

Selector

Shift register

fc/2⁶

fc/2⁸

fc/2¹⁰

fc/2¹²

2

3

2

Remote control receive

data buffer register

(RXDBR)

2

4

RPOLS

RCCK

RXCR1

RMM

RCS CREGA

RXCR2

Remote control receive

control register 1

Remote control receive

control register 2

Figure 2.10.1 Remote Control Signal Preprocessor

2.10.2 Remote Control Signal Preprocessor Control

When the remote control signal preprocessor is used, operating states are controlled and

monitored by the following registers. Interrupt requests also use the remote control signal

preprocessor/external interrupt 3 input pin.

•

Remote control receive control register 1 (RXCR1)

Remote control receive control register 2 (RXCR2)

Remote control receive counter register (RXCTR)

Remote control receive data buffer register (RXDBR)

Remote control receive status register (RXSR)

When this pin is used for the external interrupt 3 input, set EINT in RXCR1 to other

than “11”.

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Remote Control Receive Control Register 1

RXCR1

7

6

5

4

3

2

1

0

(00FE8H)

(Initial value: 0000 0000)

RCCK

RPOLS

EINT

RNC

00: fc/2⁶(Hz)

01: fc/2⁸

8-bit up counter source clock

select

RCCK

RPOLS

EINT

10: fc/2¹⁰

11: fc/2¹²

0: Positive

1: Negative

00: Rising edge

Remote control signal polarity

select

01: Falling edge (at RPOLS = 0)

10: Rising/falling edge

11: 8-bit receive end

001: 2²/fc × 7 − 1/fc (s)

010: 2⁵/fc × 7 − 1/fc

Interrupt source select

R/W

011: 2⁶/fc × 7 − 1/fc

100: 2⁷/fc × 7 − 1/fc

Noise canceler noise

eiminating time select

RNC

101: 2⁸/fc × 7 − 1/fc

110: 2¹⁰/fc × 7 − 1/fc

111: 2¹²/fc × 7 − 1/fc

000: Noise canceler disable

Note 1: fc: High-frequency clock [Hz]

Note 2: After reset, RPOLS do not change the set value in the receiving remote control signal. For setting interrupt

edge and measurement data, use EINT and RMM.

Remote Control Receive Control Register 2

RXCR2

7

6

5

4

3

2

1

0

(00FE9H)

CREGA

RCS RMCEN

RMM

(Initial value: 0000 0000)

Match detect time (Tth) = 16 × CREGA/RCCK [s]

CREGA = 0H to FH

Setting of detect time for

CREGA match with 8-bit up counter

upper 4 bits

Example: CREGA = 2H, RCCK = fc/2⁶[Hz], at fc = 16 MHz,

DV1CK = 1

Tth = 128 [μs]

0: Stop and counter clear

1: Start

RCS

8-bit up counter start control

R/W

0: Disable

1: Enable

Remote control signal

preprocesser enable/disable

RMCEN

00:

01:

Measurement mode select

(Invalid when EINT = “10”)

Refer to Talbe 2.10.1

RMM

10:

11:

Note 1: fc: High-frequency clock [Hz]

Note 2: When an interrupt source is set for rising/falling edge, low and high widths are forcibly measured

separately.

Note 3: Set CREGA (0H to FH) before EINT sets to 8-bit receive end.

Figure 2.10.2 Remote Control Receive Control Register 1, 2

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Remote Control Receive Counter Register

RXCTR

7

6

5

4

3

2

1

0

Read only

(Initial value: 0000 0000)

(00FEAH)

Remote Control Receive Data Buffer Register

RXDBR

7

6

5

Read only

(Initial value: 0000 0000)

(00FEBH)

Remote Control Receive Status Register

RXSR

7

6

5

2

1

0

Read only

(Initial value: 0000 *000)

(00FECH)

RBCTM

OVFF

SRM

RNCM

Receive bit counter value

monitor

RBCTM

OVFF

SRM

0: No overflow

1: Overflow

8-bit up counter overflow flag

Read

only

0: Upper 4 bits of 8 bit up counter < CREGA

1: Upper 4 bits of 8 bit up counter ≥ CREGA

Data buffer register input

monitor

Remote control signal monitor

after passing through noise

canceler

RNCM

*: Don’t care

Figure 2.10.3 Remote Control Receive Counter Register, Data Buffer Register, Status Register

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Table 2.10.1 Combination of Interrupt Source and Measurement Mode

RPOLS

EINT

RMM

Interrupt Source

Measurement Mode

00

10

11

01

10

11

01

0

10

11

−

00

10

00

10

11

01

10

11

Receive end

00

01

1

10

11

−

00

10

Receive end

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2.10.3 Noise Elimination Time Setting

The remote control receive circuit has a noise canceler. By setting RNC in RXCR1, input

signals shorter than the fixed time can be eliminated as noise.

Table 2.10.2 Noise Elimination Time Setting (fc = 16 MHz)

RNC

Minimum Signal Pulse Width

Maximum Noise Width to be Eliminated

000

001

010

011

100

101

110

111

−

(2⁵+ 5)/fc

(2.31 μs)

(16.31 μs)

(32.31 μs)

(64.31 μs)

(128.3 μs)

(512.3 μs)

(1.024 ms)

(2²× 7 − 1)/fc

(2⁵× 7 − 1)/fc

(2⁶× 7 − 1)/fc

(2⁷× 7 − 1)/fc

(2⁸× 7 − 1)/fc

(2¹⁰× 7 − 1)/fc

(2¹¹× 7 − 1)/fc

(1.69 μs)

(13.88 μs)

(27.88 μs)

(55.88 μs)

(111.9 μs)

(447.9 μs)

(895.9 μs)

(2⁸+ 5)/fc

(2⁹+ 5)/fc

(2¹⁰+ 5)/fc

(2¹¹+ 5)/fc

(2¹³+ 5)/fc

(2¹⁴+ 5)/fc

2.10.4 Operation

(1) Interrupts at rising, falling, or rising/falling edge, and measurement modes

First set EINT and RMM. Next, set RCS to “1”; the 8-bit up counter is counted up by

the internal clock. After measurement, the 8-bit up counter value is saved in RXCTR.

Then, the 8-bit up counter is cleared, an INT3 request is generated, and the 8-bit up

counter resumes counting.

If the 8-bit up counter overflows (FFH) before measurement is completed, an INT3

request is generated and the overflow flag (OVFF) is set to “1”. Then, the 8-bit up

counter is cleared. An overflow can be detected by reading OVFF by the interrupt

processing. To restart the 8-bit up counter, set RCS to “1”.

Setting RCS to “1” zero clears OVFF.

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Figure 2.10.4 Rising Edge Interrupt Timing Chart (RPOLS = 0)

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Figure 2.10.5 Falling Edge Interrupt Timing Chart (RPOLS = 0)

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Figure 2.10.6 Rising/Falling Edge Interrupt Timing Chart

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(2) 8-bit receive end interrupts and measurement modes

By determining one-cycle remote control signal as one-bit data set to “0” or one-pulse

width remote control signal as one-bit data set to “1”, an INT3 request is generated

after 8-bit data is received. When “0” is determined, this means the upper four bits in

the 8-bit up counter have not reached the CREGA value. When “1” is determined, this

means the upper four bits in the 8-bit up counter have reached or exceeded the CREGA

value. The 8-bit up counter value is saved in RXCTR after one bit is determined. The

determined data is saved, bit by bit, in RXDBR at the rising edge of the remote control

signal (when RPOLS = 1, falling edge). The number of bits saved in RXDBR is counted

by the receive bit counter and saved in RBCTM. RBCTM is set to “0001B” at the rising

edge of the input (when RPOLS = 1, falling edge) after the INT3 request is generated.

RNCM

RCCK

8-bit up

counter value

FE

FF

1

Set to “1” by command.

RCS

OVFF

Receive bit

counter value*

n − 1

n

RBCTM* n − 1

INT3

request

*: Valid only when 8 bits are received.

Figure 2.10.7 Overflow Interrupt Timing Chart

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Figure 2.10.8 8-Bit Receive End Interrupt Timing Chart (PROLS = 0)

88CS38B-118

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Table 2.10.3 Count Clock for Remote Control Preprocessor Circuit (at fc = 16 MHz)

Count Clock (RCCK)

Maximum Setting Time [ms]

Resolution [μs]

00

01

10

11

4

16

1.024

4.096

16.38

65.53

64

256

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2.11 8-Bit AD Converter (ADC)

The TMP88CS38B/CM38B/CP38B has a 8-bit successive approximation type AD converter.

2.11.1 Configuration

Figure 2.11.1 shows the circuit configuration of the AD converter.

The AD converter includes control registers ADCCRA and ADCCRB, conversion result

registers ADCDR1 and ADCDR2, a DA converter, a sample hold circuit, a comparator, and

sequential transducer circuit.

To use P5 and P6 as analog inputs, clear the output latch for P5 and P6 to “0”. Also, clear

the input/output control registers (P5CR1 and P6CR) to “0”.

VSS

VDD

DA converter

Reference

voltage

Sample hold

circuit

Analog input multiplexer

A

Y

AIN0

ADS

B

AIN1

8

Analog

comparator

E

AIN4

AIN5

Successive approximate circuit

3

SAIN

AINDS

F

S

Shift clock

EN

INTADC

Control circuit

EN

6

2

3

8

EOCF ADBF

AD8TRG

ADRS

AMD

ACK

external

trigger signal

P5CR, P6CR

ADCCRA

ADCCRB

ADCDR1, ADCDR2

P5, P6 port input/output control register

AD converter control register

AD conversion result register

Figure 2.11.1 AD Converter (ADC)

2.11.2 Control Register

The following register are used for AD converter.

AD converter control register 1 (ADCCRA)

•

AD converter control register 2 (ADCCRB)

AD conversion result register (ADCDR1/ADCDR2)

(1) AD converter control register 1 (ADCCRA)

ADCCRA control AD conversion start, AD operation mode select, analog input

control and analog input channel select.

(2) AD converter control register 2 (ADCCRB)

ADCCRB control AD conversion time select.

(3) AD conversion result register (ADCDR1)

AD conversion result is stored after end of conversion.

(4) AD conversion result register (ADCDR2)

For monitoring status of conversion.

Figure 2.11.2 and Figure 2.11.3 show AD converter control register.

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AD Converter Control Register 1

ADCCRA

(0000EH)

7

6

5

4

3

2

1

0

ADRS

AMD

AINDS

“0”

SAIN

(Initial value: 0001 0000)

The ADRS bit is automatically cleared after starting AD conversion.

During AD conversion, setting ADRS to “1” initializes the ADRS bit

and resets conversion.

ADRS

AD conversion start

0:

−

1: AD conversion restart

00: STOP mode

01: Software start mode

00: Trigger start mode

11: Reserved

0: Analog input enable

1: Analog input disable

000: select AIN0

001: select AIN1

010: select AIN2

011: select AIN3

100: select AIN4

101: select AIN5

110: −

AMD

AD operation mode select

Analog input control

R/W

AINDS

Analog input channel

selection

SAIN

111: −

Note 1: Select analog input when AD converter stops.

Note 2: When the analog input is all use disabling, the AINDS should be set to “1”.

Note 3: During conversion, do not perform output instruction to maintain a precision for all of the pins.

And port near to analog input, do not input intense signaling of change.

Note 4: The ADRS is automatically cleared to “0” after starting conversion.

Note 5: Always set bit3 in ADCCRA to “0”.

Note 6: Do not set ADRS (Bit7 in ADCCRA) to “1” during AD conversion. Reset it after confirming with EOCF (Bit5

in ADCDR2) that the conversion is completed or after generation an interrupt signal (INTADC) (by the

interrupt processing routine or the like).

Note 7 In the trigger mode, the system does not accept the second and subsequent triggers after accepting the first

trigger for starting AD conversion. To restart AD conversion by a trigger, set AMD (Bits 6 and 5 in ADCCRA)

to “00” and then put the system in trigger start mode again (with AMD = “10”).

Note 8: When the system enters STOP mode, AD converter control register 1 (ADCCRA) is initialized.

Reset this register after the system reenters NORMAL mode.

AD Converter Control Register 2

7

6

5

4

3

2

1

0

ADCCRB

(0000FH)

“0”

“1”

ACK

“0”

(Initial value: **0* 000*)

DV1CK = 1

Conversion

time

DV1CK = 0

ACK

fc = 16 MHz fc = 8 MHz fc = 16 MHz fc = 8 MHz

000

001

010

011

100

101

Reserved

ACK

AD conversion time select

156/fc [s]

312/fc [s]

624/fc [s]

−

19.5

39.0

−

39

78

156

−

R/W

19.5

39.0

78.0

39

78.0

78

110 1248/fc [s]

111

−

156

Reserved

Note 1: Do not use setting except the above liset.

Note 2: Set conversion time by analog reference voltage (V ) as follows.

DD

V

= 4.5 to 5.5 V (15.6 μ or more)

DD

Note 3: Always set bit0 and bit5 in ADCCRB to “0” and set bit4 in ADCCRB to “1”.

Note 4: When a read instruction for ADCCRB, bit6 to 7 in ADCCRB read in as undefined data.

Note 5: fc: High-frequency clock [Hz]

Note 6: When the system enters STOP mode, AD converter control register 2 (ADCCRA) is initialized.

Reset this register after the system reenters NORMAL mode.

Figure 2.11.2 AD Converter Control Register

88CS38B-121

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AD Conversion Result Register

ADCDR1

(00031H)

7

6

5

4

3

2

1

0

AD07

AD06

AD05

AD04

AD03

AD02

AD01

AD00

(Initial value: 0000 0000)

7

6

5

4

3

2

1

0

ADCDR2

(00032H)

−

EOCF

ADBF

−

(Initial value: **00 ****)

0: Under conversion or before conversion

1: End of conversion

0: During stop of AD conversion

1: During AD conversion

EOCF

ADBF

AD conversion end flag

AD conveersion busy flag

Read

only

Note 1: The EOCF is cleared to “0” when reading the ADCDR1.

Therefore, the AD conversion result should be read to ADCDR1 more first than ADCDR2.

Note 2: ADBR is set to “1” by starting AD conversion and cleared to “0” by end of AD conversion. Additionally,

ADBF is cleared to “0” by setting AMD = “00” in ADCCR2 or entering to the STOP mode.

Figure 2.11.3 AD Converter Result Register

2.11.3 AD Converter Operation

The high side of an analog reference voltage is applied to VDD, and the low side is

applied to VSS pin. Dividing a reference voltage between VDD and VSS to the voltage

corresponding to a bit by a rudder resistance and comparing it with the analog input

voltage converts the AD.

Table 2.11.1 AD Converter Operation Mode

Mode

Function

AD converter disable mode

Software start mode

Trigger start mode

AD converter stop mode. This mode is always used to change modes.

Single AD conversion of 1 channel which specifies input.

Single AD conversion of 1 channel which specifies input (AD8TRG) from

Key-on wakeup circuit as a trigger.

.

2.11.4 Interrupt

Interrupt request signal occur at the timing when the EOCF bit is set to “1”.

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2.11.5 AD Converter Operation Modes

When the MCU places in the STOP mode during the AD conversion, the conversion is

stopped and the ADCDR2 content becomes indefinite. After returning from the STOP mode,

the EOCF and INTADC does not occur. Therefore, the AD conversion must be restarted

after returning from the STOP mode.

ADS

ADCDR2

Invalid

Result

EOCF

Processing

Read Start

Start

Figure 2.11.4 AD Conversion Timing chart

(1) AD conversion in STOP mode

When the AD converter stop mode is specified during AD conversion, the AD

conversion is stopped immediately. The AD conversion is not implemented, so the

undefined value is not written to the AD conversion result register. The AD conversion

start commands which occur is the AD converter stop mode are ignored.

This mode is automatically selected by reset.

This mode is used to change the AD converter operation mode.

(2) Single mode

When the AMD (Bit6, 5 to in ADCCRA) set to “01”, the AD conversion signal mode

This mode does AD conversion of single channel, and conversion result is stored in

ADCDR1. The EOCF (Bit5 in ADCDR2) is set to “1” at end of one conversion, and an

intcrrupt request signal occurs. The EOCF is cleared to “0” by reading the AD

conversion registers.

But when the AD conversion is restarted before the ADCDR is read, the EOCF is

cleared to “0” and the last AD conversion result is maintained till next conversion end.

Do not set ADRS (Bit7 in ADCCRA) during AD conversion. Again set it after

confirming with EOCF (Bit5 in ADCDR2) that the conversion is completed or after

generating an interrupt signal (INTADC) (by the interrupt processing routine or the

like).

ADS

ADCDR2

Invalid

AD conversion result

EOCF

ADBF

Conversion time

(Reference to ADCCRB register)

Start

Read

Figure 2.11.5 Single Mode

88CS38B-123

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Example:

The AD conversion starts after 19.5 μs (at fc = 16 MHz) and AIN4 pin are selected as the conversion time

and the analog input channel. Confirming the EOCF, the converted value is read out, and the 8 bits data

is stored to address 009EH in RAM. The operation mode is a signal mode.

;AIN SELECT

LD

(P5), 00000000B

(P5CR1), 00000000B

(P6), 00000000B

(P6CR), 00000000B

(ADCCRA), 00100100B

(ADCCRB), 00011000B

;

Selects AIN4, selects the software start mode

Selects the conversion time and the operation mode

; AD CONVERT START

SET

TEST

JRS

(ADCCRA). 7

;

ADRS = 1

SLOOP:

(ADCCR2). 5

T, SLOOP

EOCF = 1 ?

; RESULT DATA READ

LD (9EH), (ADCDR1)

(3) Trigger start mode

The AD conversion of a specified single channel is executed when input (AD8TRG)

from Key-on wakeup circuit is set as trigger, the conversion result is stored in the

ADCDR1.

The EOCF (Bit5 in ADCDR2) is set to “1” at end of one conversion, and an interrupt

request signal occurs.

It needs to be set the STOP mode by bit5 to 6 in ADCCRA before the AD conversion is

executed again.

2.11.6 Analog Input Voltage and AD Conversion Result

The analog input voltage is corresponded to the 8-bit digital value converted by the AD as

shown in Figure 2.11.6.

AD Conversion

result

FFH

FEH

FDH

03H

02H

01H

V

− V

SS

DD

0

×

1

2

253

254

255

256

3

256

Analog input voltage

Figure 2.11.6 Analog Input Voltage and AD Conversion Result (typ.)

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2.11.7 STOP Modes during AD Conversion

When standby mode (STOP mode) is entered forcibly during AD conversion, the AD

convert operation is suspended and the AD converter is initialized. (ADCCRA and

ADCCRB are initialized to initial value.) Also, the conversion result is indeterminate.

(Conversion results up to the previous operation are cleared, so be sure to read the

conversion results before entering standby mode.) When restored from standby mode, AD

conversion is not automatically restarted, so it is necessary to restart AD conversion after

setting ADCCRA and ADCCRB. Note that since the analog reference voltage is

automatically disconnected, there is no possibility of current flowing into the analog

reference voltage.

2.11.8 Notice of AD Converter

(1) Analog input voltage range

Voltage range of analog input (AIN0 to AIN5) must be forced from VSS to VDD. If

input voltage of which out of range is forced to analog input pin, AD conversion result

to unknown. Also, this cause other analog input pin unstable.

(2) I/O port with analog input

Analog input pins (AIN0 to AIN5) are also I/O port. During AD conversion using any

analog input pin, don’t operate other I/O port with analog input. Because, AD accuracy

would be worse. Also, other electrically swinging port without analog input may cause

noise to near analog input pin.

(3) Reduce to noise

Figure 2.11.7 is shown as internal equivalent circuit of analog input pin.

Increasing output impedance of analog input supply, cause noise or other non-good

condition.

Therefore, output impedance of analog input supply must be less than 5 kΩ.

And we recommend to connect capacitance to analog input pin.

Internal resistance

R = 5 kΩ (typ.)

Analog converter

AINx

Analog input

supply impedance

5 kΩ (max)

Internal capacitance

C = 22 pF (typ.)

DA converter

Figure 2.11.7 Analog Input Equivalent Circuit and Analog Input Pin

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2.12 Key-on Wakeup

In this MCU the IDLE mode is also released by low active port inputs. The low input voltage

is regulated higher than the other normal ports. Therefore the ports can be enabled by analog

input level.

2.12.1 Configuration

Port P53

AIN0

AD converter

VIL ≤ VDD × 0.65

KWU0

AD8TRG

Port P54

KWU1

KWU2

AIN1

AIN2

AIN3

AIN4

AIN5

Port P55

Port P56

Port P60

Port P61

Noise

reject

circuit

KWU3

KWU4

KWU5

INTKWU

INTAD

EN

IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0

IN IN IN IN IN IN

IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0

*

IN

IDLECR (00FD0H)

IDLEIN (00FD0H)

Figure 2.12.1 Key-on Wakeup Control Circuit

2.12.2 Control

P53 to P56 and P60, P61 ports can be controlled by IDLE control register (IDLECR).

It can be configured as enable/disable in one-bit unit. When those pins are used by IDLE

mode release, those pins must be set input mode (P5CR1, P5, P6CR, P6, ADCCRA).

IDLE mode is controlled by system control register 2 (SYSCR2) and maskable interrupts.

After the individual enable flag (EF5) is set to “1”, the IDLE mode must starts. When

enabled port input generates INTKWU interrupt, the IDLE mode is released. Low level

input voltage in those ports is regulated to less than VDD × 0.65 (V).

IDLE port monitorring register (IDLEIN) can be used to check state of ports.

INTADEN can enable to generate AD8TRG, which is used as trigger of AD converter

trigger start mode.

Noise reject circuit eliminate noise, which is less than 24 μs period.

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IDLE Control Register

IDLECR

7

6

5

4

3

2

1

0

(Initial value: 0*00 0000)

(00FD0H)

INTAD

EN

IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0

EN EN EN EN EN EN

*

0: Disable

1: Enable

0: Disable

1: Enable

0: Disable

1: Enable

0: Disable

1: Enable

0: Disable

1: Enable

0: Disable

1: Enable

0: Disable

1: Enable

Generation of AD8TRG

INTADEN

IDLE5EN

IDLE4EN

IDLE3EN

IDLE2EN

IDLE1EN

Release IDLE mode by KWU5

Release IDLE mode by KWU4

Release IDLE mode by KWU3

Release IDLE mode by KWU2

Release IDLE mode by KWU1

Release IDLE mode by KWU0

Write

only

IDLE0EN

*: Don’t care

IDLE Port Monitoring Register

IDLEIN

7

6

5

4

3

2

1

0

IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0

IN IN IN IN IN IN

(Initial value: **00 0000)

(00FD0H)

*

0: “0” detect

1: “1” detect

0: “0” detect

1: “1” detect

0: “0” detect

1: “1” detect

0: “0” detect

1: “1” detect

0: “0” detect

1: “1” detect

0: “0” detect

1: “1” detect

Input level of KWU5

Input level of KWU4

Input level of KWU3

Input level of KWU2

Input level of KWU1

Input level of KWU0

IDLE5IN

IDLE4IN

IDLE3IN

IDLE2IN

IDLE1IN

Read

only

IDLE0IN

*: Don’t care

Figure 2.12.2 Key-on Wakeup Control Register

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2.13 Pulse Width Modulation Circuit Output

The TMP88CS38B/CM38B/CP38B has four 12-bit resolution PWM output channels including

two 14-bit resolution selectable and six 7-bit resolution PWM output channels.

DA converter output can easily be obtained by connecting an external low-pass filter. PWM

outputs are multiplexed with general purpose I/O ports as; P40 ( PWM0 ) to P47 ( PWM7 ), P50

( PWM8 ), P51 ( PWM9 ). PWM output is negative logic. When these ports are used PWM outputs,

the corresponding bits of P4, P5 output latches and input/output control latches should be set to

“1”.

In STOP mode, PWM output pin keeps high-level. When operation mode is changed from

STOP mode to NORMAL mode, PWM control register (PWMCR1A, PWMCR2A, PWMCR1B,

PWMCR2B) are initialized.

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2.13.1 Configuration

12-Bit Resolution PWM Output

Internal counter (2)

Internal counter (1)

PWM0

(fc/2 or fc/2²)

PWM1

PWM2

PWM3

Clock

14 13 12 11 10 9

8 7 6 5 4 3 2 1

S

R

Additional pulse generate

circuit

Compare circuit

All “0”

13

8

7

0

PWM data latch

5

0

Transfer buffer (the upper)

Transfer buffer (the lower)

7

0

PWMDBR1

2

0

6

0

PWMCR1B

PWMCR1A

PWM control register 1B

7-Bit Resolution PWM Output

Internal counter

PWM control register 1A

Clock

7

6 5 4 3 2 1

(fc/2 or fc/2²)

PWM5

PWM6

PWM7

PWM8

PWM9

PWM4

S

Compare circuit

R

6

0

PWM data latch

Transfer buffer

0

PWMDBR2

2

0

6

0

PWMCR2B

PWMCR2A

PWM control register 2B

PWM control register 2A

Figure 2.13.1 PWM Output Circuit

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2.13.2 PWM Output Wave Form

(1) PWM0 to PWM1 Outputs

PWM0 and PWM1 output can be selected 12-bit or 14-bit resolution PWM outputs.

1. 12-bit resolution PWM output

When these are used as 12-bit PWM output, one period is T = 2¹³/fc [s] (When

M

DV1CK = 0) and T = 2¹⁴/fc [s] (When DV1CK = 1) and sub period is T = T /16.

M

S

M

The lower 8 bits of the PWM data latch controls the low level pulse width with a

cycle of T . The lower 8 bits of the PWM data latch is n (n = 1 to 255), the low level

S

pulse width with a cycle becomes n × t [s] (t = 2/fc [s] when DV1CK = 0, t = 4/fc

0

[s] when DV1CK = 1).

The upper 4 bits of the PWM data latch controls a position to output the

additional pulses. When the upper 4 bits of the PWM data latch is m, the

additional pulses are generated in each of m periods out of 16 periods contained in

a T period.

M

The relationship between the 4-bit data and the position of T period where the

S

additional pulses are generated is shown in Table 2.13.1.

Table 2.13.1 The Addition Pulse (12-bit mode)

Bit Position of the Lower 4 Bits of PWMDRxH

Relative position of T in T period where the additional

S M

pulse is generated. (Number of T

is listed)

S (I)

Bit11

Bit10

Bit9

0

Bit8

0

a)

b)

c)

d)

e)

0

1

0

1

0

No additional pulse

0

1

8

1

0

4, 12

0

2, 6, 10, 14

0

1, 3, 5, 7, 9, 11, 13, 15

Note 1: The bit positions of a) to e) can be combined.

Note 2: If the low order eight bits for the PWM data latch are set to “FFH”, be sure to set the high order four

bits for this latch to “00H”.

2. 14-bit resolution PWM output

When these are used as 14-bit PWM output, one period is T = 2¹⁵/fc [s] (When

M

DV1CK = 0) and TM = 2¹⁶/fc [s] (When DV1CK = 1) and sub period is T = T /64.

S

M

The lower 8 bits of the PWM data latch controls the low level pulse width with a

cycle of T . The lower 8 bits of the PWM data latch is n (n = 1 to 255), the low level

S

pulse width with a cycle becomes n × t [s] (t = 2/fc [s] when DV1CK = 0, t = 4/fc

0

[s] when DV1CK = 1).

The upper 6 bits of the PWM data latch controls a position to output the

additional pulses. When the upper 6 bits of the PWM data latch is m, the

additional pulses are generated in each of m periods out of 64 periods contained in

a T period.

M

The relationship between the 6-bit data and the position of T period where the

S

additional pulses are generated is shown in Table 2.13.2.

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Table 2.13.2 The Addition Pulse (14-bit mode)

Bit Position of the Lower 6 Bits of PWMDRxH

Relative position of T in T period where the additional

S M

pulse is generated. (Number of T

is listed)

S (I)

Bit13

Bit12

Bit11

Bit10

Bit9

0

Bit8

0

a)

b)

c)

d)

e)

f)

0

1

0

1

0

1

0

1

0

No additional pulse

0

1

32

1

0

16, 48

0

8, 24, 40, 56

0

4, 12, 20, 28, 36, 44, 52, 60

0

2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62

g)

0

1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33,

35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63

Note 1: The bit positions of a) to g) can be combined.

Note 2: If the low order eight bits for the PWM data latch are set to “FFH”, be sure to set the high order 6 bits

for this latch to “00H”.

(2) PWM2 to PWM3 Outputs

PWM2 and PWM3 output are 12-bit resolution PWM outputs.

One period is T = 2¹³/fc [s] (When DV1CK = 0) and TM = 2¹⁴/fc [s] (When DV1CK =

M

1) and sub period is T = T /16.

S

M

The lower 8 bits of the PWM data latch controls the low level pulse width with a cycle

of T . The lower 8 bits of the PWM data latch is n (n = 1 to 255), the low level pulse

S

width with a cycle becomes n × t [s] (t = 2/fc [s] when DV1CK = 0, t = 4/fc [s] when

0

DV1CK = 1).

The upper 4 bits of the PWM data latch controls a position to output the additional

pulses. When the upper 4 bits of the PWM data latch is m, the additional pulses are

generated in each of m periods out of 16 periods contained in a T period.

M

The relationship between the 4-bit data and the position of T period where the

S

additional pulses are generated is shown in Table 2.13.1.

(3) PWM4 to PMW9 Outputs

These are 7-bit resolution PWM outputs.

One period is T = 2⁸/fc [s] (When DV1CK = 0) and T = 2⁹/fc [s] (When DV1CK = 1) .

N

The 7 bits of the PWM data latch controls the low level pulse width with a cycle of T .

N

The lower 7 bits of the PWM data latch is k (k = 1 to 127), the low level pulse width

with a cycle becomes k × t [s] (t = 2/fc [s] when DV1CK = 0, t = 4/fc [s] when DV1CK

0

= 1).

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14-bit resolution PWM mode: The additional pulse Ts (1) and Ts (63)

T

M

= 64 T

S

T

0

(0)

T

S

(1)

T (63)

S

t

0

n × t

PWM0

to

PWM1

Pulse width = n × t

Pulse width = (n + 1) t

0

12-bit resolution PWM mode: The additional pulse Ts (1) and Ts (15)

T

S

(0)

T

S

(1)

T (15)

S

t

0

n × t

0

PWM2

to

PWM3

Pulse width = n × t

Pulse width = (n + 1) t

0

T

N

PWM4

to

PWM9

Pulse width = k × t

0

Note 1: If the pulse width is set to “00H”, PWM will note operate. Its output will remain high.

Note 2: If the pulse width is set to “FFH”, settings for additional pulses cannot be made. Be sure to set the pulse

width to “00H”.

Figure 2.13.2 PWM Output Waveform

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2.13.3 Control

PWM output is controlled by PWM control register (PWMCR1A, PWMCR1B, PWMCR2A,

PWMCR2B) and PWM data buffer register (PWMDBR1, PWMDBR2).

PWM Control Register 1A

7

6

5

4

3

2

1

0

PWMCR1A

(00028H)

(Initial value: *000 0000)

RESOLUTION

−

ABORT1 START3 START2 START1 START0

1

0

0: Operation

Abort PWM operation of

channel 3 to 0

ABORT1

1: PWM abort (PWM outputs are fixed to a high level.)

0: Stop PWM3

START3

START2

START1

START0

Start channel 3

Start channel 2

Start channel 1

Start channel 0

1: Start PWM3

0: Stop PWM2

1: Start PWM2

0: Stop PWM1

1: Start PWM1

0: Stop PWM0

1: Start PWM0

Write

only

0: 14-bit resolution

1: 12-bit resolution

0: 14-bit resolution

1: 12-bit resolution

RESOLUTION1 Select channel 1 resolution

RESOLUTION2 Select channel 0 resolution

Note 1: *: Don’t care

Note 2

After set the ABORT1 to “1”, the ABORT1 is cleared to “0” automatically.

Note 3: PWMCR1A is write-only register and cannot be used with any of the read-modify-write instructions such

as SET, CLR, etc.

PWM Control Register 1B

7

6

5

4

3

2

1

0

PWMCR1B

(Initial value: **** *000)

PWMCHS1

PWMHL

(00029H)

00: Channel 0

01: Channel 1

10: Channel 2

11: Channel 3

0: Lower 8 bits

Select the PWM data latch of

12-bit PWM channel

PWMCHS1

PWMHL

Write

only

Select upper or lower data

transfer buffer (PWMDBR1)

1: Upper 4 bits or 6 bits

Note 1: *: Don’t care

Note 2: PWMCR1B is write-only register and cannot be used with any of the read-modify-write instructions such

as SET, CLR, etc.

PWM Data Buffer Register 1

7

6

5

4

3

2

1

0

Write only

PWMDBR1

(0002AH)

(Initial value: 0000 0000)

Note 1: PWMDBR1 is write-only register and cannot be used with any of the read-modify-write instructions such

as SET, CLR, etc.

Note 2: When operation mode is changed from STOP mode to NORMAL mode, PWMCR1A, PWMCR1B are

initialized.

Figure 2.13.3 PWM Control Register 1A/1B and PWM Data Buffer Register 1

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PWM Control Register 2A

7

6

5

4

3

2

1

0

PWMCR2A

(Initial value: *000 0000)

START5 START4

ABORT2 START9 START8 START7 START6

−

(00FF5H)

0: Operation

1: PWM abort

Abort PWM operation of

channel 9 to 4

ABORT2

0: Stop PWM9

1: Start PWM9

0: Stop PWM8

1: Start PWM8

START9

START8

START7

START6

START5

START4

Start channel 9

Start channel 8

Start channel 7

Start channel 6

Start channel 5

Start channel 4

0: Stop PWM7

1: Start PWM7

0: Stop PWM6

1: Start PWM6

Write

only

0: Stop PWM5

1: Start PWM5

0: Stop PWM4

1: Start PWM4

Note 1: *: Don’t care

Note 2 After set the ABORT2 to “1”, the ABORT2 is cleared to “0” automatically.

Note 3: PWMCR2A is write-only register and cannot be used with any of the read-modify-write instructions such

as SET, CLR, etc.

PWM Control Register 2B

7

6

5

4

3

2

1

0

PWMCR2B

(Initial value: **** *000)

PWMCHS2

(00FF6H)

000:

001:

010:

011:

100:

101:

110:

111:

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

Channel 9

Reserved

Select the PWM data latch of

7-bit PWM channel

Write

only

PWMCHS2

Note 1: *: Don’t care

Note 2: PWMCR2B is write-only register and cannot be used with any of the read-modify-write instructions such as

SET, CLR, etc.

PWM Data Buffer Register 2

7

6

5

4

3

2

1

0

Write only

PWMDBR2

(00FF7H)

(Initial value: *000 0000)

Note 1: *: Don’t care

Note 2: PWMDBR2 is write-only register and cannot be used with any of the read-modify-write instructions such as

SET, CLR, etc.

Note 3: When operation mode is changed from STOP mode to NORMAL mode, PWMCR2A, PWMCR2B are

initialized.

Figure 2.13.4 PWM Control Register 2A/2B and PWM Data Buffer Register 2

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Binary Counter Control Register

CGCR

7

6

5

4

3

2

1

0

(Initial value: 0000 0000)

(00030H)

“0”

DV1CK

“0”

0: fc/4

1: fc/8

Select of input clock to

1st divider

DV1CK

R/W

Note 1: *: Don’t care

Note 2: The all bits except DV1CK are cleared to “0”.

Figure 2.13.5 DIVIDER Control Register

(1) Internal counter

The internal counter of PWM outputs is a free running counter. The all bits of

counter are set to “1” and are not counted up at one of the following conditions.

1. During reset

2. The operation mode is changed to STOP mode.

3. Setting ABORTx (x: 1, 2) to “1”.

4. The START3 to 0 are “0” in 12-bit PWM outputs. The START9 to 4 are “0” in 7-bit

PWM outputs.

5. The lower 8-bit of PWM data latch in 12-bit PWM outputs is “00H”. The PWM

data latch in 7-bit PWM outputs is “00H”.

(2) Outputs control and programming of PWM data

The PWM outputs are fixed to a high-level immediately when the ABORTx (x: 1, 2) is

set to “1”. The PWM outputs starts the operation when the STARTx (x: 0 to 9) is set to

“1”.

The data from the transfer buffer to a PWM data latch is transferred when the all

bits of internal counter are set to “1”. Therefore, the data is transferred to a PWM data

latch immediately when the internal counter is initialized. And the data is transferred

to a PWM data latch at the beginning of the next cycle when all bits of the internal

counter are not set to “1”.

The sequence of writing the output data to PWM data latches is shown as follows;

1. PWM0 to PWM1

a) Write the channel number of PWM data latch to PWMCHS1 (Bit2 and 1 in

PWMCR1B) and clear PWMHL (Bit0 in PWMCR1B) to “0”.

b) Write the lower 8-bit PWM output data to PWMDBR1.

c) Write the channel number of PWM data latch to PWMCHS1 and set PWMHL

to “1”.

d) Write the upper 4-bit or 6-bit PWM output data to PWMDBR1.

e) Select the resolution of PWM output to RESOLUTIONx (x: 0, 1) (Bit0 and 1 in

PWMCR1A) and set STARTx (x: 0, 1) (Bit2 and 3 in PWMCR1B) to “1”.

Note: PWM output data must be write to PWMDBR1 in the order of the lower 8-bit

PWM output data, the upper 4-bit (or 6-bit) PWM output data. If the upper 4-bit

(or 6-bit) PWM output data is write to PWMDBR1, the lower 8-bit PWM output

data is not changed (except when lower 8-bit PWM output data is “00H”).

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2. PWM2 to PWM3

a) Write the channel number of PWM data latch to PWMCHS1 and clear

PWMHL to “0”.

b) Write the lower 8-bit PWM output data to PWMDBR1.

c) Write the channel number of PWM data latch to PWMCHS1 and set PWMHL

to “1”.

d) Write the upper 4-bit PWM output data to PWMDBR1.

e) Set STARTx (x: 2, 3) to “1”.

1) Data transfer timing and STOP/ABORT timing (X: 0 to 3)

T

M

T

M

T

S

T

S

PWMx

m × t

n × t

0

Writing PWMDBR1

(Data m to n)

T

S

PWMx

STARTx = 0

or

The lower 8-bit of PWM data latch = 00H

T

S

PWMx

ABORT1 = 1

or

STOP mode

2) Restart timing when operating for 1ch or more

T

M

T

M

PWM0

PWM1

Restarting PWM1

Restarts after one cycle.

3) Restart timing after all channels stop

T

M

T

M

Start command

Figure 2.13.6 Waveform of PWM0 to PWM3

Note: PWM output data must be write to PWMDBR1 in the order of the lower 8-bit PWM output data, the

upper 4-bit (or 6-bit) PWM output data. If the upper 4-bit (or 6-bit) PWM output data is write to

PWMDBR1, the lower 8-bit PWM output data is not changed (except when lower 8-bit PWM output

data is “00H”).

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3. PWM4 to PWM9

a) Write the channel number of PWM data latch to PWMCHS2.

b) Write the lower 7-bit PWM output data to PWMDBR2.

c) Set STARTx (x: 4 to 9) to “1”.

1) Data transfer timing and STOP/ABORT timing (X: 4 to 9)

T

N

T

N

PWMx

m × t

n × t

0

Writing PWMDBR2

(Data m to n)

STARTx (x: 4 to 9) = 0

or

The lower 8-bit of PWM data latch = 00H

PWMx

ABORT2 = 1

or

STOP mode

2) Restart timing when operating for 1ch or more

T

N

T

N

PWM4

PWM5

Restarting PWM5

Restarts after one cycle.

3) Restart timing after all channels stop

T

N

T

N

Start command

Figure 2.13.7 Waveform of PWM4 to PWM9

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Example: at fc = 16 MHz, DV1CK = 0

PWM0 pin outputs a 14-bit resolution PWM wave form with a low level of 32 μs width and no additional pulse.

PWM1 pin outputs a 12-bit resolution PWM wave form with a low level of 16 μs width and no additional pulse.

PWM4 pin outputs a PWM wave form with a low level of 8 μs width.

LD

(CGCR), 00H

;

DV1CK = 0

LD

(PWMCR1B), 00H

(PWMDBR1), 80H

(PWMCR1B), 01H

(PWMDBR1), 00H

(PWMCR1B), 02H

(PWMDBR1), 40H

(PWMCR1B), 03H

(PWMDBR1), 01H

(PWMCR1A), 0DH

;

Select the lower 8 bits of PWM0 output data latch

32 μs ÷ 4/fc = 80H

Select the upper 6 bits of PWM0 output data latch

No additional pulse = 00H

Select the lower 8 bits of PWM0 output data latch

16 μs ÷ 4/fc = 40H

Select the upper 4 bits of PWM0 output data latch

Additional pulse (Ts ) = 01H

(8)

Start PWM0 and PWM1 ,

PWM0 : 14-bit resolution, PWM1 : 12-bit resolution

LD

(PWMCR2B), 00H

(PWMDBR2), 20H

(PWMCR2A), 01H

;

Select PWM4 output data latch

8 μs ÷ 2/fc = 20H

Start PWM4

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2.14 Test Video Signal Output for Adjusting TV Screen

The TMP88CS38B/CM38B/CP38B has a built-in video signal output circuit to output

necessary signal for TV screen adjustment.

Picture pattern

Output format

:

Total eight types, monochromatic inversion possible

Three states (H, L, High-Z) output

Comp.sync duration time

Black level/pedestal duration time

White level duration time

L output

High-Z output

H output

2.14.1 Configuration

Horizontal pattern

generation circuit

Pattern mixed circuit

P62 (CSOUT)

Vertical pattern

generation circuit

Display pattern

generation circuit

3

SGIV SGPAT2 to 0

TVSCR

SGVBLK

SGPAL

Test video signal output control register

Figure 2.14.1 Test Video Signal Output Circuit

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2.14.2 Control

The test video signal output circuit can be controlled with the test video signal control

register.

7

6

5

4

3

2

1

0

TVSCR

SGPAT

“0”

(00FE6H)

(Initial value: 0000 0000)

SGEN SGVBLK SGPAL SGIV SGCHS

“0”

SGEN

SG function selection

0: Disable

1: Enable

SGVBLK

SGPAL

SGIV

Picuture signal for VBLK duration 0: Output

time

1: No output

0: NTSC

PAL/NTSC selection

1: PAL

Pattern monochromatic inversion

0: No inversion

1: Inversion

Write

only

SGCHS

SGPAT

OSD synchronous signal selection 0: Port

1: Pseudo signal circuit

000:Black on the whole screen

001:White on the whole screen

010:Cross hatch

Display pattern

011:Cross dot pattern

100:Cross bar

101:White on the upper side/black on the lower side

110:H signal pattern

111:H resolution pattern

Note 1: Test video signal output function does work correctly when fc is not 16 MHz.

Note 2: Clear the bit2 and bit0 of TVSCR to “0”.

Figure 2.14.2 Test Video Signal Control Register

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2.14.3 Functions

Video signal output is to generate monochromatic picture signal output to take easily the

necessary tests such as TV screen white adjustment and screen distortion amplitude

adjustment implemented on the final manufacturing process of a TV receiver set.

Table 2.14.1 Display Pattern and TV Screen

Display Pattern

TV Screen

000

(Black on the whole surface)

001

(White on the whole surface)

010

(Cross hatch)

011

(Cross dot)

100

(Cross bar)

101

(White on the upper side/

black on the lower side)

110

(H signal pattern)

111

(H resolution pattern)

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There are three states of the output to generate picture signal with the external circuit of

the resistance divided voltage.

Example of picture output generation)

5 V

TMP88CS38B/

CM38B/CP38B

P62 (CSOUT)

to video input

GND

Three state of

Picture signal output

the output

(1 Vp-p)

(5 Vp-p)

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2.15 On-screen Display (OSD) Circuit

The TMP88CS38B/CM38B/CP38B features a built-in on-screen display circuit used to

display characters and symbols on the TV screen. There are 384 characters and any characters

can be displayed in an area of 32 columns × 12 lines (Include 2 columns for solid space). With an

OSD interrupt, additional lines can be displayed. The functions of the OSD circuit meet the

requirements of on-screen display functions of closed caption decoders based on FCC standards.

OSD circuit functions are as follows:

(1) Number of character fonts:

384

(2) Number of display characters: 384 (32 columns × 12 lines)

(3) Composition of character:

(4) Character sizes:

Horizontal 16 × vertical 18 dots

3 kinds for large, middle and small characters

(Selectable line by line)

(5) Character ornamentation function

Fringing function

Smoothing function

Slant function (Italics)

Blinking function

Underline

(6) Solid space

(7) Area plane function: 2 planes

(8) Full-raster blanking function

(9) Display colors

Character colors: 8 or 15 colors (Selectable character by character)

Fringe color: 8 or 15 colors (Selectable page by page)

Background color:8 or 15 colors (Selectable page by page)

Area plane color: 8 or 15 colors (Selectable each of 2 planes)

Raster color:

8 or 15 colors (Selectable page by page)

(10) Display position: 256 horizontal steps and 512 vertical steps for code plane

: 512 horizontal steps and 512 vertical steps for area plane

(11) Window function:512 vertical steps

(12) Half transparency output function

The TMP88CS38B/CM38B/CP38B outputs OSD through 3 planes; code, area, and raster. 3

planes function independently. In addition, they are displayed simultaneously. There is the

priority among these 3 planes, so they are displayed on a screen according to the priority.

These 3 planes have the priority such as

Code > Area > Raster.

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1. Code plane

OSD character is displayed on the code plane.

The code plane consists of 32 characters × 1 row and a total of 12 planes. The 12

planes have the priority such as code 1 > code 2 > ... > code 11 > code 12.

On the code plane, characters of 16 × 18 dots is displayed. These fonts are called

characters, and read from character ROM and display memory through the character

code on the display memory.

2. Area plane

The area on a screen is displayed on the area plane.

The area plane can display 2 square areas of any size by specifying coordinates. The

2 planes have the priority such as area plane 1 > area plane 2.

2.15.1 Configuration

OSC1

OSC2

Oscillation

circuit for

OSD display

OSD

interrupt

Horizontal position

counter

OSD control

P70 ( HD )

Horizontal position

decoder

I

Display memory

32 × 12 × 16 bits

Jitter

elimina-

tion

Y/BL

B

P57 (I)

Character

code

P67 (Y/BL)

P66 (B)

P65 (G)

P64 (R)

Vertical position counter

Vertical position decoder

circuit

G

Character ROM

384 × 16 × 18 bits

P71 ( VD )

R

Character

data

P60 (Y/BLIN)

P61 (BIN)

P62 (GIN)

P63 (RIN)

Figure 2.15.1 OSD Circuit

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2.15.2 Character ROM and Display Memory

(1) Character ROM

The character ROM contains 384 character fonts. The user can set fonts as desired.

The character ROM consists of 384 characters in 16 × 18 dots (Character codes 000H to

17FH). Each dot corresponds to one bit in the character ROM. When a bit in the

character ROM is set to “1”, the corresponding dot is displayed; if set to “0”, the dot is

not displayed. The start address in the character ROM corresponding to a character

code is determined by the following expression:

Start address in character ROM = CRA × 40H + 20000H

Since character code 000H is used as blank character, the character font for this

character code cannot be changed. Write “0” in the data of character code 000H.

Write the data “FFH” to all unused address (5th bit of an address is “1” and also the

lower 4 bits of an address are 2H to FH) in character ROM.

Figure 2.15.2 (a) shows an example of the character font configuration for the

character code 000 and 001 , together with the ROM addresses and data.

H

Figure 2.15.2 (b) shows the character ROM dump list for these 2 character fonts.

Note 1: CRA: Character code (000H to 17FH).

Note 2: A data can not be read from character ROM by software.

Note 3: When ordering a mask, load the data to character ROM at addresses 20000H to

25FFFH.

And the data in unused are of character ROM are must be specified to FFH.

Address Data

(Hex) (Hex)

Address Data

(Hex) (Hex)

Address Data

(Hex) (Hex)

Address Data

(Hex) (Hex)

Bit

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

20000

20001

20002

20003

20004

20005

20006

20007

20008

20009

2000A

2000B

2000C

2000D

2000E

2000F

20010

20011

00

20020

20021

20022

20023

20024

20025

20026

20027

20028

20029

2002A

2002B

2002C

2002D

2002E

2002F

20030

20031

00

20040

20041

20042

20043

20044

20045

20046

20047

20048

20049

2004A

2004B

2004C

2004D

2004E

2004F

20050

20051

3F

7F

E0

C0

00

01

03

07

0E

1C

38

70

FF

00

20060

20061

20062

20063

20064

20065

20066

20067

20068

20069

2006A

2006B

2006C

2006D

2006E

2006F

20070

20071

C0

E0

70

30

70

E0

C0

80

00

F0

00

(Character code 000H)

(Character code 001H)

(a) Character font configuration

20000/

00

3F

00

7F

00

FF

00

FF

00

FF

00

FF

00

FF FF FF

00 00 00

FF FF FF

00 00 00

FF FF FF

30 70

FF FF FF

00

FF

00

FF

01

FF

00

FF FF FF

00 00 00

FF FF FF

03 07

FF FF FF

80 00 00

FF FF FF

00

FF

00

FF

00

FF FF FF FF

00 00 00 00

FF FF FF FF

38 70 FF FF

FF FF FF FF

00 00 F0 F0

FF FF FF FF

00

20010/

20020/

20030/

20040/

20050/

20060/

20070/

E0 C0

0E 1C

FF

70

FF

30

FF

00

FF

C0 E0

00 00

E0 C0

FF

(b) ROM dump list

Shared portions indicate unused data.

Note:

Figure 2.15.2 Character Font Configuration and ROM Dump List

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(2) Display memory

Each character of the 384 characters displayed in 32 columns × 12 lines consists of 16

bits in the display memory. Five data items are written to the display memory:

Character code, color data, blinking specification, underline enable, and slant enable.

There are two modes for writing display data to the display memory. One mode is

used for writing all display data (Character code, color data, blinking specification,

underline enable, and slant enable) simultaneously. The other mode is used for

changing either character codes or the remaining data items (Color data, blinking

specification, underline enable, and slant enable). How to write display data to the

display memory is described in section 2.15.5.7 (1).

Note: The display memory is in an unknown state at reset.

Display memory configuration

•

Character code specification register (9 bits)....CRA8 to CRA0

Color data specification register (4 bits) ...........IDT/RDT/GDT/BDT

Blinking specification register (1 bit)................BLF

Underline enable register (1 bit)........................EUL

Slant enable register (1 bit) ...............................SLNT

SLNT

EUL

BLF

IDT

RDT

GDT

BDT

CRA8

CRA7

CRA6

CRA5

CRA4

CRA3

CRA2

CRA1

CRA0

Character color specification register

Blinking specification register

Character code specification register

Underline enable register

Slant enable register

Figure 2.15.3 Display Memory Bit Configuration

Column

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Line

1

2

000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F

020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 038 039 03A 03B 03C 03D 03E 03F

3

040

060

080

0A0

0C0

0E0

100

120

140

4

5

6

7

8

9

10

11

12

160

17F

Note:

Numerals in the table indicate (hexadecimal) addresses in the display memory.

Figure 2.15.4 Display Memory Address Configuration

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2.15.3 OSD Circuit Control

The OSD circuit performs control functions using the OSD control registers which reside

in addresses 0001DH to 0001FH and 00024H to 00025H in the special function registers

(SFR), and in addresses 0F80H to 0FBFH in the data buffer register (DBR). Section

2.15.5.9 shows the OSD control registers. The OSD control registers are used to set display

start position, display character designs (that is, fringing, smoothing, color data, character

size, and etc.), display memory addresses, and character codes.

Setting the display on-off control bit, DON, (Bit0 in ORDON) to “1” enables display

(Starts display). Setting DON to “0” disables display (Halts display).

Note: The contents of OSD control registers except PIDS, P67S to P64S are initialized in

STOP mode.

2.15.4 OSD Control Register Write

There are lists of the OSD control registers on Table 2.15.5.10 and Table 2.15.5.11.

When data is written into a shaded register, the data is transferred to the OSD circuit,

and then the data becomes valid. After data is written into an unshaded register, the data

is transferred to the OSD circuit, and then the data becomes valid.

To transfer the contents of a control register to the OSD circuit, use data transfer request

register RGWR (Bit2 in ORDON).

Setting “1” in the RGWR register outputs the transfer request signal to the OSD circuit.

Three instruction cycles later, transfer of the written data to the OSD circuit starts. While

the data is being transferred, data transfer status monitoring flag RGWR (Bit2 in ORDON)

is “1”. When this transfer is completed, the flag is cleared to “0”.

Written data transfer register (1 bit)....RGWR (Bit2 in ORDON)

“0”

....... Initialized state

Transfers written data to OSD circuit.

(After transfer, RGWR is reset to 0.)

“1”

.......

Note: Don’t write “0” to RGWR.

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(1) RGWR system

OSD circuit

Q

D

LE

Transfer pulse by RGWR = 1

Register specified by RGWR

Figure 2.15.5 RGWR System

(2) Transfer timing

1. No display area

When having set RGWR to “1” during no display area, the timing OSD register

can be transferred is at the falling edge of HD signal.

HD

RGWR register

Set RGWR register to “1”

Clear RGWR

Data transfer pulse

Transfer the contents of OSD registers

into OSD circuit

Figure 2.15.6 Data Transfer Timing in No Display Area

2. Display area (including any lines specified as display off by character size)

When having set RGWR to “1” during display area, the timing OSD register can

be transferred is at the falling edge of HD signal when the display line has been

finished.

HD

Display line

RGWR register

Set RGWR register to “1”

Clear RGWR

Data transfer pulse

Transfer the contents of OSD registers

into OSD circuit

Figure 2.15.7 Data Transfer Timing in Display Area

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2.15.5 OSD Function

2.15.5.1 Signal Control (Port I/O)

(1) P6 port output select function

This function is used to select whether the contents of port P57, P67 to P64 will

be output or I, R, G, B, Y/BL signals of the OSD circuit will be output on pins P57,

P67 to P64.

P57 port output select registers (1 bit): PIDS (Bit3 in ORP6S)

PIDS = 0

PIDS = 1

P57

I

Port

P67 to P64 port output select registers (4 bits): P67S, P66S, P65S, P64S, (Bit7 to

4 in ORP6S)

P6nS = 0

P6nS = 1

P64

P65

P66

P67

R

G

Port

B

Y/BL

(2) OSD pin output polarity control function

This function is used to select the polarity of the OSD outputs for RGB, I and

Y/BL.

Output polarity control register (4 bits) ...... BLIV, YIV, RGBIV, IIV (Bit3 to 0 in

ORIV)

“0”

“1”

...... Active high

...... Active low

(3) OSD pin input polarity control

Input polarity control

Input polarity control register of RIN/GIN/BIN/Y/BLIN (2 bits)

For Y/BLIN.......................... YBLII (Bit5 in ORIV)

For RIN, GIN, and BIN ...... RGBII (Bit4 in ORIV)

Input polarity control

YBLII,

RGBII

“0”

“1”

...... Active high

...... Active low

Input polarity control register of HD / VD (2 bits)

For VD ..............VDPOL (Bit7 in ORIV)

For HD .............HDPOL (Bit6 in ORIV)

Input polarity control

VDPOL, HDPOL

“0”

“1”

....... Not invert input signal

....... Invert input signal

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Register setting for the

following waveform

Input waveform to P70, P71

VDPOL = 0

HDPOL = 0

P71 ( VD )

P70 ( HD )

VDPOL = 1

HDPOL = 0

P71 ( VD )

P70 ( HD )

VDPOL = 0

HDPOL = 1

P71 ( VD )

P70 ( HD )

VDPOL = 1

HDPOL = 1

P71 ( VD )

P70 ( HD )

Figure 2.15.8 VD /HD input and VDPOL/HDPOL

(4) Y/BL signal select function

This function is used to select either Y or BL signal output from the Y/BL pin.

Y/BL signal select register (1 bit).........YBLCS (Bit7 in ORP6S)

“0”

“1”

....... Y signal output

....... BL signal output

Y signal..............Output in all OSD areas (Logical OR for R, G, B data

as character data, fringing data, area data, etc.)

BL signal ...........When EXBL is “0”:

Output in all display character areas

(except for character code 000H: Blank character)

When EXBL is “1”:

Output in the whole page

(5) I signal function select

When PISEL (Bit6 in ORETC) is set to “1” and PIDS (Bit3 in ORP6S) is set to “0”,

Port 57 (I pin) can be used as half transparency/half tone through an extra circuit.

At half transparency/half tone function, contents of IDT (Bit3 in ORDSN) is

make no sense. Therefore character color are limited to 8 colors.

Similarly background color, fringing color, raster plane color and area plane

color are limited to 8 colors.

When PISEL (Bit6 in ORETC) sets to “0” and, PIDS (Bit3 in ORP6S) set to “0”,

15 colors to be selectable.

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(6) R, G, B, Y/BL Internal/external signal select.

Selects either R, G, B, and Y/BL signals from the internal OSD circuit, or RIN,

GIN, BIN, and Y/BLIN signals from external input.

R, G, B, Y/BL signal select registers (2 bits)........ MPXS1/MPXS0

(Bits 1 and 0 in ORP6S)

....... Simultaneous output (Signal from the OSD circuit

“00”

has higher priority.)

“01”

“10”

....... Output of signal from internal OSD circuit

....... Output of signal from external input

....... Simultaneous output (External input signal has

higher priority.)

“11”

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2.15.5.2 OSD Data Output Format Control

(1) Scan mode

The double scan mode is used to handle non-interlaced scanning TV. When

double scan mode is enabled, the vertical display counter increases every 2 scan

lines and a vertical size of a dot is double. This function is enabled by setting

VDSMD (Bit7 in ORETC) in the OSD control register to “1”.

Scan mode select register (1 bit).......VDSMD (Bit7 in ORETC)

“0”

“1”

....... Normal mode

....... Double scan mode

Note 1:The data written to those control register is transferred to the OSD circuit and

become valid when the data is written.

Note 2:When OSD circuit is used on an interlace scanning TV, a jitter elimination

circuit must be enabled and set AFLD to “1” in JECR.

Table 2.15.5.1 The Difference of 2 Types of Scan Mode

Normal Mode

Double Scan Mode

Specification unit of vertical display

start position

One scanning line

Two scanning lines

1 dot height

−

Normal mode height × 2

Normal mode

Double scan mode

Normal mode

Double scan mode

Interlace scanning

Non-interlace scanning

Figure 2.15.9 Scan Mode

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2.15.5.3 Display Position Control

(1) Code display position setting

1. Horizontal display start position

The horizontal display start position can be set in 256 steps by writing to OSD

control registers HS17 to HS10 (Bit7 to 0 in ORHS1). The value is in common with

all lines.

Specification unit: 2 T

OSC

Specification steps: 256

Specification horizontal display start position: Line 1 to 12: HS17 to HS10

(ORHS1)

HS1 = (HS17 to HS10) × 2T

+ 20T

(Line1 to 12)

H

OSC

Note 1: T

: One cycle of OSD oscillation.

OSC

Note 2: The data written to these control registers is transmitted to OSD circuit by

setting RGWR (Bit2 in ORDON) to “1”.

2. Vertical display start position

The vertical display start position can be specified for each display line using

512 steps by writing to VSn8 to VSn0 (in ORVSn (n: 1 to 12)).

Specification unit: 1 scan line

Specification steps: 512

Specification vertical display start position:

Line1: VS18 to VS10 (ORVS 1)

Line2: VS28 to VS20 (ORVS 2)

.

Line12: VS128 to VS120 (ORVS 12)

Line n: VSn = (VSn8 to VSn0) × 1T

(n: 1 to 12)

H

HD

Note 1: THD: One cycle of HD signal.

Note 2: The data written to these control registers is transmitted to OSD circuit by

setting RGWR (Bit2 in ORDON) to “1”.

Note 3: If display lines are overlapped each other, previous display line is enabled and

next line is disabled. If vertical display start positions of two or more lines are

set on same value, high priority line is enabled. Lines of OSD (VS1 to VS12)

are fixed priority levels as follows:

VS1 > VS2 > VS3 > ...... > VS12

Set the vertical display start position not to overlap display lines.

VS5 (Display on, small character)

VS2 (Display canceled, middle character)

VS3 (Display on, small character)

Occasion of overlapping

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Note 4: The line which is displayed off is managed as a small size character line.

Note 5: Transfer the contents of vertical display start position registers into OSD circuit

before the position of the scanning line coincides with their own vertical

display start position.

(2) Area display position setting

The planes have the priority such as Code plane > Area plane 1 > Area plane 2 >

Raster plane.

1. Horizontal display start and end position

The horizontal display start position can be set in 512 steps by writing to OSD

control registers AHSn8 to AHSn0 (Bit8 to 0 in ORAHSn). And also display stop

position is correspond to AHEn8 to AHEn0 (Bit8 to 0 in ORAHEn). (n: 1 to 2)

Horizontal display start position

AHSn = (AHSn8 to AHSn0) × 2T

H

OSC

Horizontal display end position

AHEn = (AHEn8 to AHEn0) × 2T

H

OSC

Note 1:T

: One cycle of OSD oscillation.

OSC

Note 2:If the horizontal display start position for characters is the same as that for

areas, the two positions are not displayed at the same time. The horizontal

display start position for characters is displayed 16 T

register value of 8) later than that for areas.

(Corresponding to a

OSC

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2. Vertical display start and end position

The vertical display start position can be set in 512 steps by writing to OSD

control registers AVSn8to AVSn0 (Bit8 to 0 ORAVSn). And also display stop

position is correspond to AVEn8 to AVEn0 (Bit8 to 0 in ORAVEn). (n: 1 to 2)

Vertical display start position

AVSn = (AVSn8 to AVSn0) × T

H

HD

Vertical display end position

AVEn = (AVEn8 to AVEn0) × T

H

HD

Note:

T

HD

: One cycle of HD signal.

HD

VS1 VS2

AVS1 AVE1

AVS2 AVE2

HS1

1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132

Code plane 1

Code plane 2

AHS1

Area plane 1

AHE1

VD

Area plane 2

HS1

SS 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132 SS Code plane 9

SS 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132SS Code plane 10

SS 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132SS Code plane 11

SS 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132SS Code plane 12

AHS2

AHE2

Figure 2.15.10 TV Scan Image

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2.15.5.4 Character Ornamentation Control

(1) Character sizes

Character size can be selected line by line from 3 sizes. And display on/off also

can be set line by line. Small, middle and large character size and display on/off

can be set with OSD control registers CSn (n: 1 to 12, ORCS4, ORCS8, ORCS12)

in the OSD control registers.

Character sizes: 3 sizes (Small, middle and large)

Character size and display on/off specification unit: Line

Character size select/display on/off register (2 bits × 12)

Line 1: CS1

Line 2: CS2

:

Line 12: CS12

Table 2.15.5.2 Character Size and Display On/Off Specifications (n: 1 to 12)

CSn (Upper bit)

CSn (Lower bit)

Character Size

Display On/Off

1

0

1

0

1

0

Small

Middle

Large

−

On

Off

Note 1:The display off line operates like the width of small character size line thought

the character is not displayed.

Note 2:The data written to these control registers is transmitted to OSD circuit by

setting RGWR (Bit2 in ORDON) to “1”.

Note 3:When OSD circuit is used on an interlace scanning TV, a jitter elimination

circuit must be enabled and set AFLD to “1” in JECR.

Note 4:When VDSMD and AFLD are “0”, only character of even display dot is

displayed. (Refer to 2.16 a jitter elimination circuit.)

Table 2.15.5.3 Dot and Character Sizes

VDSMD = 0 (Normal mode)

VDSMD = 1 (Double scan mode)

Character Size

Dot Size

EFRn = 0

EFRn = 1

(Fringe on)

EFRn = 0

EFRn = 1

(Fringe on)

(Fringe off)

Small

Middle

Large

Small

Middle

Large

1T

OSC

× 0.5T

HD

16T

× 9T

HD

16T

32T

64T

16T

32T

64T

× 11T

× 20T

× 40T

× 13T

× 25T

× 50T

1T

OSC

2T

OSC

4T

OSC

1T

OSC

2T

OSC

4T

OSC

× 1T

× 2T

× 4T

× 1T

× 2T

× 4T

16T

32T

64T

16T

32T

64T

× 18T

× 36T

× 72T

× 24T

× 48T

× 96T

16T

32T

64T

16T

32T

× 20T

× 40T

× 80T

× 25T

× 50T

OSC

HD

OSC

HD

OSC

HD

EULAn = 0

(Underline

off)

2T

× 1T

× 2T

32T

64T

16T

32T

64T

× 18T

× 36T

× 12T

× 24T

× 48T

OSC

HD

4T

1T

× 0.5T

HD

OSC

EULAn = 1

(Underline

on)

2T

× 1T

× 2T

OSC

HD

4T

64T

× 100T

HD

T

OSC

: One cycle of OSD oscillation, T : One cycle of HD signal

HD

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Small

Middle

Large

Figure 2.15.11 Character Size

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(2) Smoothing function

The smoothing function is used to make characters look smooth. Enabling

smoothing displays 1/4 dot between two dots connecting corner to corner within a

character. Small size character can not be enabled smoothing. Smoothing is

enabled by setting ESMZ (Bit4 in ORETC) in the OSD control register to “1”.

Smoothing specification unit:Display page

Smoothing specification register (1 bit)......ESMZ (Bit4 in ORETC)

“0”

“1”

....... Disable smoothing

....... Enable smoothing

Note: Data of the register is transferred to the OSD circuit and become valid when

the data is written.

Before

After

Before

After

Available form for smoothing

Invalid form for smoothing

Figure 2.15.12 Available Form and Invalid Form for Smoothing

Original character

Smoothing

Figure 2.15.13 Smoothing Example

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(3) Fringing function

The fringing function is used to display a character with a fringe width is 1 dot

in a different color from that of the character. When a character is displayed with

the maximum of 18 vertical dots and 16 horizontal dots, the fringe exceeds right

and left, top, and bottom of the character display area. If there is an adjacent

character that outer dot is active, then this dot will overrule the fringe in the

horizontal direction. Underlines are not fringed.

Fringing is enabled for each line by setting EFR1 to EFR8 (OREFR8) and EFR9

to EFR12 (OREFR12) in the OSD control register to “1”.

A color for fringe is specified common to all lines using OSD control registers,

IFDT, RFDT, GFDT, and BFDT (Bit3 to 0 in ORBK).

Fringing specification unit: Line

Fringing enable register (1 bit × 12)....EFRn (n: 1 to 8) (OREFR8), EFRn (n: 9

to 12) (OREFR12)

“0”

“1”

....... Disable fringing

....... Enable fringing

Fringe colors: 8 or 15

Fringe color specification unit: Display page

Fringe color register (4 bits).....IFDT, RFDT, GFDT, BFDT (Bit3 to 0 in ORBK)

I signal function select: PISEL (Bit6 in ORETC)

“0”

....... 15 colors specification

I pin can be used to make a half level of R, G, B

signal (Dark color) through an extra circuit.

....... 8 colors specification

“1”

Contents of IDT register is disregarded.

I pin can be used as half transparency/half tone

through an extra circuit.

Note: The fringe of 1st column character does not exceed left, and the fringe of 32th

character does not exceed right.

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Figure Color

Table 2.15.5.4 Fringe Color (15 colors)

IFDT

RFDT

GFDT

BFDT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Black

Blue

Green

Cyan

0

Red

Magenta

Yellow

White

Black

Dark blue

Dark green

Dark cyan

Dark red

Dark magenta

Dark yellow

Gray

1

R, G, B pin output

I pin output

R, G, B output

Figure 2.15.14 Example Circuit for 15 Colors by I Pin.

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2 dots

Before fringing

After fringing

Disable underline

2 dots

Before fringing

After fringing

Enable underline

a) Small character, NORMAL mode

Figure 2.15.15 (a) Fringing Example

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1 dot

Before fringing

After fringing

Disable underline

1 dot

Before fringing

After fringing

Enable underline

b) Small character, double scan mode

Figure 2.15.16 (b) Fringing Example

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1 dot

Before fringing

After fringing

Disable underline

1 dot

Before fringing

After fringing

Enable underline

c) Middle/Large character, NORMAL mode

Figure 2.15.17 (c) Fringing Example

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1 dot

Before fringing

After fringing

Disable underline

1 dot

Before fringing

After fringing

Enable underline

d) Middle/Large character, double scan mode

Figure 2.15.18 (d) Fringing Example

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(4) Background function

Background color function is used to color the entire background for the

character area (Refer to Table 2.15.4). Except the character area whose character

code is 000H.

This function is specified for each display page by setting EBKGD (Bit7 in

ORRCL) in the OSD control register to “1”.

A background color is specified for each display page by setting IBDT, RBDT,

GBDT, and BBDT (Bit7 to 4 in ORBK) in the OSD control registers.

Background specification unit: Display page

Background enable register (1 bit) ......EBKGD (Bit7 in ORRCL)

“0”

“1”

....... Disable background

....... Enable background

Background color specification unit: Display page

Background color specification registers (4 bits).... IBDT, RBDT, GBDT, BBDT

(Bit7 to 4 in ORBK)

I signal function select: PISEL (Bit6 in ORETC)

“0”

....... 15 colors specification

I pin can be used to make a half level of R, G, B

signal (Dark color) through an extra circuit.

....... 8 colors specification

“1”

Contents of IBDT register is disregarded.

I pin can be used as half transparency/half tone

through an extra circuit.

Table 2.15.5.5 Background Color (15 colors)

IBDT

RBDT

GBDT

BBDT

Background Color

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Black

Blue

Green

Cyan

0

Red

Magenta

Yellow

White

Black

Dark blue

Dark green

Dark cyan

Dark red

Dark magenta

Dark yellow

Gray

1

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R, G, B pin output

I pin output

R, G, B output

Figure 2.15.19 Example Circuit for 15 Colors by I Pin.

Character color: Cyan

Background color: Yellow

Scanning line

R

G

B

R

G

B

Y

BL

1) Disable background

2) Enable background

Figure 2.15.20 Background Function

Note: When the background function is enabled, the line enable the fringing function should not start with

a blank character. If it starts with a blank character, a fringe is displayed to the left of the blank

character.

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2.15.5.5 OSD Display Screen Control

(1) Display on/off

This function is used to display characters specified for on/off display.

Display on/off specification unit: Display page

Display on/off specification register (1 bit)......DON (Bit0 in ORDON)

“0”

“1”

....... Disable display

....... Enable display

Note: Do not start STOP mode during display is enable.

(2) Window function

This function is used to set upper and lower limit of display page. Window upper

limit is specified by WVSH (ORWVSH). Window lower limit is specified by WVSL

(ORWVSL). This function is enabled by setting EWDW (Bit1 in ORDON) in the

OSD control register to 1.

Window specification unit: Display page

Window function enable specification register (1 bit)...... EWDW (Bit1 in

ORDON)

“0”

“1”

....... Disable window function

....... Enable window function

Window upper limit specification register (9 bits).....WVSH8 to 0 (ORWVSH)

Window lower limit specification register (9 bits)......WVSL8 to 0 (ORWVSL)

Window upper and lower limit position......

When VDSMD is “0” (Normal mode):

WVSH = (WVSH8 to WVSH0) × T

H

HD

WVSL = (WVSL8 to WVSL0) × T

H

HD

When VDSMD is “1” (Double scan mode):

WVSH = (WVSH8 to WVSH0) × 2T

H

HD

WVSL = (WVSL8 to WVSL0) H × 2THD

Note 1:THD: One cycle of HD signal

Note 2:WVSL > WVSH ≥ “1”

Note 3:Modify the value of window upper and lower limit register and the value of

EWDW during VD signal is low.

Note 4:It is recommendable that the window function is always enabled (EWDW = “1”)

and set WVSH to “01H”, WVSL to “1FEH”.

Note 5:Characters and symbols at scanning line specified by WVSL are not displayed.

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HD

AVE2

Background color

Area plane color

Picture

WVSH

Raster color

SS 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132 SS

AHS1

SS 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132 SS

VD

SS 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132 SS

WVSL

Picture

Window display: On, Area plane display: On, Background color display: On, Raster plane display: On

Correspond to Closed Caption

Display off

WVSH

Display

Figure 2.15.21 If WVSH is on a Code Plane

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(3) Full-raster blanking function

Full-raster blanking function is used to color the entire background for the

display area (TV screen). When using the full-raster blanking function, set

YBLCS (Bit2 in ORP6S) to “1”, output BL signal from Y/BL pin, because Y signal

cannot delete whole display page from video signal.

This function is specified for each display page by setting EXBL (Bit6 in

ORRCL) in the OSD register to “1”.

Full-raster blanking specification unit: Display page

Full-raster blanking enable register (1 bit).....EXBL (Bit6 in ORRCL)

“0”

“1”

....... Disable full-raster blanking

....... Enable full-raster blanking

Full-raster blanking color specification ........ RCLI, RCLR, RCLG, RCLB

registers (4 bits) (Bit3 to 0 in ORRCL)

I signal function select: PISEL (Bit6 in ORETC)

“0”

....... 15 colors specification

I pin can be used to make a half level of R, G, B

signal (Dark color) through an extra circuit.

....... 8 colors specification

“1”

Contents of RCLI register is disregarded.

I pin can be used as half transparency/half tone

through an extra circuit.

Table 2.15.5.6 Raster Plane Color (15 colors)

RCLI

RCLR

RCLG

RCLB

Raster Plane Color

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Black

Blue

Green

Cyan

0

Red

Magenta

Yellow

White

Black

Dark blue

Dark green

Dark cyan

Dark red

Dark magenta

Dark yellow

Gray

1

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(4) Area plane function

Area plane function is used to display square area to two points on a screen.

Two planes operate independently. They are displayed according to the priority

(Area plane 1 > Area plane 2).

See area plane display position setting in section 2.15.5.3 (2) how to set display

positions for each area.

Each area plane is set to ON or OFF by AON2 and AON1 (Bit5 and bit4 in

ORRCL).

Area plane colors are set by ACLIx, ACLRx, ACLGx, ACLBx (Bit7 to bit0 in

ORACL, x: 1, 2).

Area plane colors: 8 or 15

Area plane specification unit: plane

Area plane color specification register (8 bits)

Area plane 1: ACLI1/ACLR1/ACLG1/ACLB1 (Bit3 to 0 in ORACL)

Area plane 2: ACLI2/ACLR2/ACLG2/ACLB2 (Bit7 to 4 in ORACL)

I signal function select: PISEL (Bit6 in ORETC)

“0”

....... 15 colors specification

I pin can be used to make a half level of R, G, B

signal (Dark color) through an extra circuit.

....... 8 colors specification

“1”

Contents of ACLI1 and ACLI2 register is

disregarded.

I pin can be used as half transparency/half tone

through an extra circuit.

Table 2.15.5.7 Area Plane Color (15 colors)

ACLIx

ACLRx

ACLGx

ACLBx

Area Plane Color

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Black

Blue

Green

Cyan

0

Red

Magenta

Yellow

White

Black

Dark blue

Dark green

Dark cyan

Dark red

Dark magenta

Dark yellow

Gray

1

x: 1, 2

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I signal function select

1. Using for 15 colors (PISEL = 0)

Example color

l = 0

l = 1

Area plane

Character

color

Dark

red

Red

Character

background

color

Dark

green

Green

Blue

Scanning

line

Area plane

color

Dark

blue

Raster plane: Off

Character background: On

YBLCS: 0 (Y select)

R

15 colors

specification

G

B

I

Y

Figure 2.15.22 TV Display and OSD Signals (PISEL = 0)

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2. Using for half transparency/half tone (PISEL = 1)

Example color

Character

Red

Area plane: Half transparency/half tone

color

Character

background

color

Green

Blue

Area plane

color

Scanning

line

Raster plane: Off

Character background: On

YBLCS: 0 (Y select)

R

G

B

I

8 colors

specification

Y

Figure 2.15.23 TV Display and OSD Signals (PISEL = 1)

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2.15.5.6 Interrupt Control

(1) Display line counter

The display line counter indicates number of display line (s) by OSD circuit on

the TV screen. The display line counter is a 4-bit counter which is initialized to “0”

by the falling edge of the VD signal and which increments when last scanning of

each display line is completed (Falling edge of the HD signal). It is necessary to be

read out display line counter several times, because it does not synchronize CPU

clock.

Display line counter register (4 bits).....DCTR (Bit3 to 0 in ORIRC)

“0000”......No display line is completed.

“0001”......1st display line is completed.

“0010”......2nd display line is completed.

.

“1111” .....15th display line is completed.

Display line

counter

VD signal

Display on

Display off

1st Display Line

2nd Display Line

Display on

3rd Display Line

4th Display Line with all blank characters

Display on

10th Display Line

11th Display Line

12th Display Line

Note 1: The display line counter also increments when a line with all blank characters or a line with display off is

specified.

Note 2: When display lines are overlapped each other, previous display line is enabled and next line is canceled.

At this time, the display line counter does not increment for canceled line.

Figure 2.15.24 Display Line Counter

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(2) Interrupt generator circuit

An interrupt request is generated when a falling edge of VD signal or when line

counter (DCTR) is counted to the certain value specified by ISDC.

Interrupt source select register (1 bit)...SVD (Bit4 in ORIRC)

“0”

....... Interrupt request generated when the display line

counter (DCTR) is counted to the certain value which

is specified by ISDC.

“1”

....... Interrupt request is generated when a falling edge of

VD signal.

Interrupt generation line specification register (4 bits) ...ISDC (Bit3 to 0 in

ORIRC)

“0000”

“0001”

“0010”

....... Interrupt request generated when the display line

counter is cleared.

....... Interrupt request generated at end points of the last

scanning line of the first display line

....... Interrupt request generated at end points of the last

scanning line of the 2nd display line

.

“1111”

....... Interrupt request generated at end points of the last

scanning line of the 15th display line

2.15.5.7 Display Memory Access

(1) Display memory

The display memory is accessed for two purposes, one for writing data to the

display memory, and one for reading data from the display memory.

Display memory address specification registers

(9 bits)

DMA8 to MDA0 (ORDMA)

....

Display memory data write registers

Character code write register (9 bits)

CRA8 to CRA0 (ORCRA)

....

Character ornamentation data write registers

(7 bits)

SLNT, EUL, BLF, IDT, RDT,

GDT, and BDT (ORDSN)

Display memory bank select register MBK (bit 1 in ORETC)

“0” ...

“1” ...

When writing either character code or character ornamentation data

When writing both character code and character ornamentation data

Note 1:These control registers have a characteristic that immediately when a value is

written to the register, the content of the register is transferred as valid data to

the OSD circuit/display memory.

Note 2: The data written to the display memory takes effect at the same time it is written.

When character code or character ornamentation data is written to the display

memory while it is displaying some character, the character may not be displayed

correctly. When writing data to the display memory, make sure no character is

being displayed in the memory location where you are going to write data.

Note 3:When writing data to or reading data from the display memory, do not use

two-byte transfer instructions such as “LDW(HL),mn LD rr, (pp)”. Otherwise,

erroneous data may be written to the display memory or data may be written to

an incorrect address.

Note 4:Allow for at least two instruction cycles between a display memory address

write instruction and a data write or read instruction. Also, when continuous

writing data to or reading data from the display memory, allow for at least two

instruction cycles between one write or read instruction and the next.

Otherwise, erroneous data may be written to the display memory or data may

be written to an incorrect address.

Note 5:When setting display memory addresses, always be sure to write all of 9

address bits sequentially in order of DMA8 and DMA7 to DMA0.

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1. Normal mode

In normal mode, the display memory addresses are automatically incremented

each time data is read from or written to the memory. Because addresses are

automatically incremented, this mode may be used for reading from or writing

data to multiple continuous addresses simultaneously.

a. When writing either character code or character ornamentation data

(1) Set MFYWR, MBK, and RDWRV all to 0.

(2) Write the most significant address bit of the display memory to DMA8. Go on

and write the 8 low-order address bits of the display memory to DMA7 to

DMA0.

(3) Writing character code or character ornamentation data

•

Writing character code

Write the most significant bit of character code to CRA8. Go on and write

the 8 low-order bits of character code to CRA7 through CRA0. At this point in

time, the 9 bits of character code written are transferred to the display

memory, and DMA8 to DMA0 are automatically incremented.

•

Writing character ornamentation data

Write character ornamentation data to SLNT, EUL, BLF, IDT, RDT, GDT,

and BDT. At this point in time, the character ornamentation data written are

transferred to the display memory, and DMA8 to DMA0 are automatically

incremented.

(4) To write data (character code or character ornamentation data) to continuous

addresses, repeat step (3).

b. When writing character code and character ornamentation data at a time

(1) Set MFYWR to 0, MBK to 1, and RDWRV to 0.

(2) Write the most significant address bit of the display memory to DMA8. Go on

and write the 8 low-order address bits of the display memory to DMA7 to

DMA0.

(3) Write character ornamentation data to SLNT, EUL, BLF, IDT, RDT, GDT, and

BDT. At this point in time, the character ornamentation written are

transferred to the display memory.

(4) Write the most significant bit of character code to CRA8. Go on and write the 8

low-order bits of character code to CRA7 to CRA0. At this point in time, the 9

bits of character code written and the character ornamentation data written

in step (3) are transferred to the display memory, and DMA8 to DMA0 are

automatically incremented.

(5) To write data to continuous addresses, repeat steps (3) and (4).

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a. When reading either character code or character ornamentation data

(1) Set MFYWR to 0, MBK to 0, and RDWRV to 1.

(2) Write the most significant address bit of the display memory to DMA8. Go on

and write the 8 low-order address bits of the display memory to DMA7 to

DMA0.

(3) Reading character code or character ornamentation data

•

Reading character code

Read the most significant bit of character code to CRA8. Go on and read the

8 low-order bits of character code to CRA7 to CRA0. At this point in time,

DMA8 to DMA0 are automatically incremented.

•

Reading character ornamentation data

Read character ornamentation data SLNT, EUL, BLF, IDT, RDT, GDT, and

BDT. At this point in time, DMA8 through DMA0 are automatically

incremented.

(4) To read data (character code or character ornamentation data) from

continuous addresses, repeat step (3).

b. When reading character code and character ornamentation data at a time

(1) Set MFYWR to 0, MBK to 1, and RDWRV to 1.

(2) Write the most significant address bit of the display memory to DMA8. Go on

and write the 8 low-order address bits of the display memory to DMA7 to

DMA0.

(3) Read character ornamentation data SLNT, EUL, BLF, IDT, RDT, GDT, and

BDT.

(4) Read the most significant bit of character code to CRA8. Read the 8 low-order

bits of character code to CRA7 to CRA0. At this point in time, DMA8 to DMA0

are automatically incremented.

(5) To read data from continuous addresses, repeat steps (3) and (4).

2. Read-modify-write mode

When writing data in read-modify-write mode, the display memory addresses

are automatically incremented as in normal mode, but when reading data in this

mode, the memory addresses are not automatically incremented.

Therefore, immediately after executing a read from some display memory

address, you can execute a write to the same display memory address. After

executing a write, the display memory addresses are automatically incremented.

a. Reading/writing either character code or character ornamentation data in

read-modify-write mode

(1) Set MFYWR to 1 and MBK to 0, and RDWRV to 1.

(2) Write the most significant address bit of the display memory to DMA8. Go on

and write the 8 low-order address bits of the display memory to DMA7 to

DMA0.

(3) Reading character code or character ornamentation data

•

Reading character code

Read the most significant bit of character code to CRA8. Read the 8

low-order bits of character code to CRA7 to CRA0. DMA8 to DMA0 are not

incremented.

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•

Reading character ornamentation data

Read character ornamentation data SLNT, EUL, BLF, IDT, RDT, GDT, and

BDT. DMA8 to DMA0 are not incremented.

(4) Writing character code or character ornamentation data

•

Set RDWRV to “0”.

Writing character code

Write the most significant bit of character code to CRA8. Go on and write

the 8 low-order bits of character code to CRA7 to CRA0. At this point in time,

the 9 bits of character code written are transferred to the display memory, and

DMA8 to DMA0 are automatically incremented.

•

Writing character ornamentation data

Write character ornamentation data to SLNT, EUL, BLF, IDT, RDT, GDT,

and BDT. At this point in time, the character ornamentation data written are

transferred to the display memory, and DMA8 to DMA0 are automatically

incremented.

(5) To continue executing read-modify-write operations, repeat steps (1) to (4). To

read/write data (Character code or character ornamentation data). To

continue executing read-modify-write mode from continuous addresses,

repeat steps (3) and (4).

b. Reading/writing both character code and character ornamentation data in

read-modify-write mode

(1) Set MFYWR to 1, MBK to 1 and RDWRV to 1

(2) Write the most significant address bit of the display memory to DMA8. Go on

and write the 8 low-order address bits of the display memory to DMA7 to

DMA0.

(3) Read character ornamentation data SLNT, EUL, BLF, IDT, RDT, GDT, and

BDT. At this point in time, DMA8 to DMA0 are not incremented.

(4) Read the most significant bit of character code to CRA8. Read the 8 low-order

bits of character code to CRA7 to CRA0. At this point in time, DMA8 to DMA0

are not incremented.

(5) Set RDWRV to “0”.

(6) Write character ornamentation data to SLNT, EUL, BLF, IDT, RDT, GDT, and

BDT. At this point in time, the character ornamentation data written is

transferred to the display memory.

(7) Write the most significant bit of character code to CRA8. Go on and write the 8

low-order bits of character code to CRA7 to CRA0. At this point in time, the 9

bits of character code written and the character ornamentation data written

in step (6) are transferred to the display memory, and DMA8 to DMA0 are

automatically incremented.

(8) To continue executing read-modify-write operations, repeat steps (1) to (7). (To

read/write data to and from continuous addresses in read-modify-write mode,

repeat steps (3) to (7).)

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Table 2.15.5.8 Address Increment

RD (RDWRV = 1)

WR (RDWRV = 0)

Character

Ornamentation

Character

Code

Character

Ornamentation

Character

Code

MBK = 0

MBK = 1

MBK = 0

MBK = 1

INC

−

INC

MFYWR = 0

MFYWR = 1

−

INC

−

INC: Automatic address increment at read or write.

−: No address change at data read or write.

Example:

Setting a character code (020H) to the display memory (Address: 120H) and setting (001H) for a

character ornamentation.

1. MBK = 0

; Set display memory address

LD

(0x25),

(0x24),

0x01

0x20

; ORDMA<DMA8>

; ORDMA<DMA7:0>

; Set character code

LD

(0x1F),

(0x1E),

0x00

0x20

; ORCRA<CRA8>

; ORCRA<CRA7:0>

; Set display memory address again

LD

(0x25),

(0x24),

0x01

0x20

; Set character ornamentation

LD (0x1D),

0X01

; ORDSN<SLNT, ..... BDT>

2.

MBK = 1

; Set display memory address

LD

(0x25),

(0x24),

0x01

0x20

; Set character ornamentation

LD (0x1D),

; Set character code

0X01

LD

(0x1F),

(0x1E),

0x00

0x20

Note 1: To write character code into the display memory, first write into register CRA8 and then

write into registers CRA7 to CRA0. When data is written into registers CRA7 to CRA0,

DMA8 to DMA0 is incremented. It is impossible to write into the display memory for

CRA7 to CRA0 alone. If no data is written into register CRA8 while data is written into

registers CRA7 to CRA0, the value previously written into register CRA8 is written into

the associated display memory.

Note 2: To read character code from the display memory, first read from register CRA8, and

then read from registers CRA7 to CRA0. When data is read from registers CRA7 to

CRA0, DMA8 to DMA0 is incremented.

Note 3: There should be a time interval of at least two machine cycles between a DMA set

instruction and a data write/read instruction. There should be a time interval of at least

two machine cycles between a data write instruction and a data read instruction.

(2) Character

Characters: 384 (including blank character)

Character specification register (9 bits) ...........CRA8 to CRA0 (Bit8 to 0 in ORCRA)

Character code “000H”............................Blank character

Character code “001H” to “017FH” ........User programmable by character

ROM

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(3) Character color

Character colors: 8 or 15

Character color specification unit: Character

Character color specification register (4 bits): IDT/RDT/GDT/BDT (Bit3 to 0 in

ORDSN)

I signal function select: PISEL (Bit6 in ORETC)

“0”

....... 15 colors specification

I pin can be used to make a half level of R, G, B

signal (Dark color) through an extra circuit.

....... 8 colors specification

“1”

Contents of IDT register is disregarded.

I pin can be used as half transparency/half tone

through an extra circuit.

Table 2.15.5.9 Character Color (15 colors)

IDT

RDT

GDT

BDT

Character Color

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Black

Blue

Green

Cyan

0

Red

Magenta

Yellow

White

Black

Dark blue

Dark green

Dark cyan

Dark red

Dark magenta

Dark yellow

Gray

1

R, G, B pin output

R, G, B output

I pin output

Figure 2.15.25 Example of Circuit for 15 Color by I Pin

2007-09-12

88CS38B-179

TMP88CS38B/CM38B/CP38B

(4) Blinking function

Blinking function is used to blink display characters.

When BKMF is “1”, characters specified for blinking by BLF are not displayed. (If

the background color function is used, the background color is not disappeared.)

Blinking specification unit: Character

Blinking specification register (1 bit).....BLF (Bit4 in ORDSN)

“0”

“1”

....... No blinking

....... Blinking

Blinking master specification register (1 bit).....BKMF (Bit5 in ORETC)

“0”

“1”

....... Disable blinking

....... Enable blinking (Characters whose BLF are set to

“1” are not displayed.)

Note: Regarding the extra dot of the left and/or right character by fringing function, it is not

enabled as blink.

(5) Underline function

Underline function is used to add a line under a display character. The underline is

same color as that of character.

Underline specification unit: Character/line

Underline enable register (Character unit) (1 bit).....EUL (Bit5 in ORDSN)

“0”

“1”

....... No underline

....... Underline

......EULAn (n: 1 to 8)(OREULA8),

EULAn (n: 9 to 12)

Underline enable register (Line unit) (1 bit × 12)

(OREULA12)

Underline colors: 8 or 15

Underline color specification registers (4 bits)

......RDT, GDT, BDT, IDT (Bit3 to 0 in

ORDSN) (Refer to Table 2.15.5.9)

Note: To use the underline function, set both the underline enable register for underlining

text in characters and that for underlining text in lines. If the former register (EUL)

only is set, an underline is not displayed.

16

Character display area

18

24

6

Underline display area

EUL = 0

EUL = 1

Figure 2.15.26 Underline

88CS38B-180

2007-09-12

TMP88CS38B/CM38B/CP38B

(6) Solid space control

Solid space control is used to display one column of solid space to the left and right of

32 columns.

Solid space control is used to delete the video signal in the areas where solid spaces

are located in the original display page, then add color to them.

Solid space specification unit: line

Solid space specification register (24 bits)

For line 1

SOL11 and SOL10 (Bits 1 and 0 in ORSOL4)

For line 2

SOL21 and SOL20 (Bits 3 and 2 in ORSOL4)

.

For line 12

SOL121 and SOL120 (Bits 7 and 6 in ORSOL12)

Solid space specification

The solid space control functions as follows:

SOLx1/SOLx0 (x: 1 to 12)

“00”

“01”

“10”

“11”

....... No solid space display

....... Solid space display left for 32 columns

....... Solid space display right for 32 columns

....... Solid space display left and right for 32 columns

Solid space color specification registers (4 bits)

....... IBDT, RBDT, GBDT, BBDT (Bits 3 to 0 in ORBK)

(Same color as that of background)

32 columns

Solid space

(Left)

Solid space

(Right)

Figure 2.15.27 Solid Space

2007-09-12

88CS38B-181

TMP88CS38B/CM38B/CP38B

(7) Slant function

Slant function is used to slant characters for italics.

Slant specification unit: Character

Slant enable register (1 bit).....SLNT (Bit6 in ORDSN)

“0”

“1”

....... No slant

....... Slant

Note 1: SLANT function is enabled each characters, and therefore, in case of using

background function, this color of the Background is enable as slant. Regarding

the extra dots of the left and/or right character by fringing function, it is not

enabled as slant.

Note 2: When a character is slanted in an area, which overlaps with the character field,

the overlap is also slanted.

Note 3: If slanting a character causes part of the character to get into the character field to

the immediate right of the character, then this part is not displayed.

Note 4: To provide closed caption display (CCD), specify black as the background color,

and set YBLCS to “1”. R, G, B and Y are all slanted. Thus, if the Y signal is

selected, a video signal is displayed above and to the left of the slant character.

Note 5: When a character is slanted, the dot data to the immediate left of the character is

also slanted.

The same color as that of the dot on the left is displayed.

When an entire character field (including its

background) contains dots:

When the character field on the right

does not contain a dots:

Figure 2.15.28 Slant

2007-09-12

88CS38B-182

TMP88CS38B/CM38B/CP38B

2.15.5.8 OSD Control Registers

Can not access all OSD control registers in any of read-modify-write instructions

such as bit operation, etc.

7

6

5

4

3

2

1

0

0RHS1

(00F81H)

HS17

HS16

HS15

HS14

HS13

HS12

HS11

HS10 (Initial value: 0000 0000)

Write

only

Horizontal display start position specification

7

VS17

−

6

VS16

−

5

VS15

−

4

VS14

−

3

VS13

−

2

VS12

−

1

VS11

−

0

ORVS1

(00F82H)

(00F83H)

VS10

VS18

(Initial value: 0000 0000)

(Initial value: **** ***0)

ORVS2

VS27

VS26

VS25

VS24

VS23

VS22

VS21

VS20

VS28

(Initial value: 0000 0000)

(00F84H)

(00F85H)

−

(Initial value: **** ***0)

ORVS3

VS37

VS36

VS35

VS34

VS33

VS32

VS31

VS30

VS38

(Initial value: 0000 0000)

(00F86H)

(00F87H)

−

(Initial value: **** ***0)

ORVS4

VS47

VS46

VS45

VS44

VS43

VS42

VS41

VS40

VS48

(Initial value: 0000 0000)

(00F88H)

(00F89H)

−

(Initial value: **** ***0)

ORVS5

VS57

VS56

VS55

VS54

VS53

VS52

VS51

VS50

VS58

(Initial value: 0000 0000)

(00F8AH)

(00F8BH)

−

(Initial value: **** ***0)

ORVS6

VS67

VS66

VS65

VS64

VS63

VS62

VS61

VS60

VS68

(Initial value: 0000 0000)

(00F8CH)

(00F8DH)

−

(Initial value: **** ***0)

ORVS7

VS77

VS76

VS75

VS74

VS73

VS72

VS71

VS70

VS78

(Initial value: 0000 0000)

(00F8EH)

(00F8FH)

−

(Initial value: **** ***0)

ORVS8

VS87

VS86

VS85

VS84

VS83

VS82

VS81

VS80

VS88

(Initial value: 0000 0000)

(00F90H)

(00F91H)

−

(Initial value: **** ***0)

ORVS9

VS97

VS96

VS95

VS94

VS93

VS92

VS91

VS90

VS98

(Initial value: 0000 0000)

(00F92H)

(00F93H)

−

(Initial value: **** ***0)

ORVS10

(00F94H)

VS107 VS106 VS105 VS104 VS103 VS102 VS101 VS100

VS108

(Initial value: 0000 0000)

(00F95H)

−

(Initial value: **** ***0)

ORVS11

(00F96H)

VS117 VS116 VS115 VS114 VS113 VS112 VS111 VS110

VS118

(Initial value: 0000 0000)

(00F97H)

−

(Initial value: **** ***0)

ORVS12

(00F98H)

VS127 VS126 VS125 VS124 VS123 VS122 VS121 VS120

(Initial value: 0000 0000)

(00F99H)

−

VS128

(Initial value: **** ***0)

VSn8 to

VSn0

Write

only

Vertical display start position for line n

(n: 1 to 12)

Note 1: If display lines are overlapped each other, previous display line is enabled and next line is disabled. Set

the vertical display start position not to overlap display lines.

Note 2: Transfer the contents of vertical display start position registers into OSD circuit before a position of the

scanning line coincides with their own vertical display start position.

2007-09-12

88CS38B-183

TMP88CS38B/CM38B/CP38B

7

6

5

4

3

2

1

0

ORCS4

(00F9AH)

ORCS8

(00F9BH)

ORCS12

(00F9CH)

CS4

CS8

CS3

CS7

CS2

CS6

CS1

CS5

CS9

(Initial value: 0000 0000)

CS12

CS11

CS10

00: Display off

01: Large size

10: Middle size

11: Small size

Character size and display

on/off for line n

Write

only

CSn

(n: 1 to 12)

OREULA8

(00F9DH)

OREULA12

(00F9EH)

EULA8 EULA7 EULA6 EULA5 EULA4 EULA3 EULA2 EULA1

(Initial value: 0000 0000)

−

EULA12 EULA11 EULA10 EULA9

(Initial value: **** 0000)

Underline for display line for

line n

0: Display off

1: Display on

EULAn

(n: 1 to 12)

OREFR8

(00F9FH)

OREFR12

(00FA0H)

EFR8

EFR7

EFR6

EFR5

EFR4

EFR3

EFR2

EFR1

(Initial value: 0000 0000)

−

EFR12 EFR11 EFR10 EFR9

(Initial value: **** 0000)

Fringing enable specification

register for line n

0: Disable fringing

1: Enable fringing

Write

only

EFRn

(n: 1 to 12)

Note: When a display line is enabled fringing function, its vertical size is increased by one dot (by two dots when its

character size is small) independent of its character font. Therefore, when a vertical display start position is

specified to no space between the lines, the display line which is overlapped with increasing dot(s) is canceled.

ORSLO4

(00FA2H)

ORSLO8

(00FA3H)

ORSLO12

(00FA4H)

SLO4

SLO8

SLO3

SLO7

SLO2

SLO6

SLO1

SLO5

SLO9

(Initial value: 0000 0000)

SLO12

SLO11

SLO10

00: No solid space display

01: Solid space display left

10: Solid space display right

Write

only

SLOn

Solid space for line n

11: Solid space display left and right

(n: 0 to 12)

2007-09-12

88CS38B-184

TMP88CS38B/CM38B/CP38B

7

6

5

4

3

2

1

0

ORBK

(00FA5H)

IBDT

RBDT

GBDT

BBDT

IFDT

RFDT

GFDT

BFDT

(Initial value: 0000 0000)

0000: Black

0001: Blue

0010: Green

0011: Cyan

0100: Red

0101: Magenta

0110: Yellow

0111: White

IBDT/

RBDT/

GBDT/

BBDT

Background color select

1000: Black

1001: Dark blue

1010: Dark green

1011: Dark cyan

1100: Dark red

1101: Dark magenta

1110: Dark yellow

1111: Gray

Write

only

0000: Black

0001: Blue

0010: Green

0011: Cyan

0100: Red

0101: Magenta

0110: Yellow

0111: White

IFDT/

RFDT/

GFDT/

BFDT

Fringing color select

1000: Black

1001: Dark blue

1010: Dark green

1011: Dark cyan

1100: Dark red

1101: Dark magenta

1110: Dark yellow

1111: Gray

Note: Set IBDT and IFDT to 1 when PISEL (Bit6 in ORETC) sets to 1. Then background color select and fringing

color select are 8 variety.

2007-09-12

88CS38B-185

TMP88CS38B/CM38B/CP38B

7

6

5

4

3

2

1

0

ORACL

(00FA6H)

ACLI2 ACLR2 ACLG2 ACLB2 ACLI1 ACLR1 ACLG1 ACLB1

(Initial value: 0000 0000)

0000: Black

0001: Blue

0010: Green

0011: Cyan

0100: Red

0101: Magenta

ACLI2/

ACLR2/

ACLG2/

ACLB2

0110: Yellow

0111: White

1000: Black

1001: Dark blue

1010: Dark green

1011: Dark cyan

1100: Dark red

1101: Dark magenta

1110: Dark yellow

1111: Gray

Area 2 plane color select

0000: Black

Write

only

0001: Blue

0010: Green

0011: Cyan

0100: Red

0101: Magenta

0110: Yellow

0111: White

ACLI1/

ACLR1/

ACLG1/

ACLB1

Area 1 plane color select

1000: Black

1001: Dark blue

1010: Dark green

1011: Dark cyan

1100: Dark red

1101: Dark magenta

1110: Dark yellow

1111: Gray

0: Not assign half transparency for area 2 plane

1: Assign half transparency for area 2 plane

0: Not assign half transparency for area 1 plane

1: Assign half transparency for area 1 plane

ACLI2

ACLI1

Note: Set ACLI2 and ACLI1 to 1 when PISEL (Bit6 in ORETC) sets to 1. Then area 2 plane color select and area 1

plane color select are 8 variety.

2007-09-12

88CS38B-186

TMP88CS38B/CM38B/CP38B

7

6

5

4

3

2

1

0

ORIV

(00FBBH)

VDPOL HDPOL YBLII

RGBII

YIV

BLIV

RGBIV

IIV

(Initial value: 0000 0000)

0: Non-invert input signal

1: Invert input signal

0: Non-invert input signal

1: Invert input signal

0: Active high

VDPOL

HDPOL

YBLII

RGBII

YIV

VD input polarity select

HD input polarity select

Y/BLIN input polarity select

1: Active low

RIN, GIN, BIN input polarity

select

0: Active high

1: Active low

Write

only

0: Active high

1: Active low

0: Active high

1: Active low

0: Active high

1: Active low

0: Active high

1: Active low

Y output polarity select

BL output polarity select

BLIV

RGBIV

IIV

R, G, B output polarity select

I output polarity select

7

6

5

4

3

2

1

0

ORDMA

(00024H)

(00025H)

DMA7 DMA6 DMA5 DMA4 DMA3 DMA2 DMA1 DMA0

(Initial value: 0000 0000)

−

DMA8

(Initial value: **** ***0)

Write

only

DMAn

Display memory address

(n: 0 to 8)

Note:

It necessary to write all bits of display memory address, writng DMA7 to DMA0 after DMA8, when writing

display address.

7

6

5

4

3

2

1

0

ORDSN

(0001DH)

−

SLNT

EUL

BLF

IDT

RDT

GDT

BDT

(Initial value: **** ****)

Slant enable specification

register

0: Disable slant

1: Enable slant

SLNT

Underline enable specification

register

0: Disable underline

1: Enable underline

EUL

BLF

Blinking enable specification

register

0: Disable blinking

1: Enable blinking

0000: Black

0001: Blue

0010: Green

0011: Cyan

0100: Red

0101: Magenta

0110: Yellow

0111: White

Read/

Write

IDT/

RDT/

GDT/

BDT

Character color select

1000: Black

1001: Dark blue

1010: Dark green

1011: Dark cyan

1100: Dark red

1101: Dark magenta

1110: Dark yellow

1111: Gray

Note:

Set IDT to 1 when PISEL (Bit6 in ORETC) sets to 1. Then character color select is 8 variety.

2007-09-12

88CS38B-187

TMP88CS38B/CM38B/CP38B

7

CRA7

−

6

CRA6

−

5

CRA5

−

4

CRA4

−

3

CRA3

−

2

CRA2

−

1

CRA1

−

0

ORCRA

(0001EH)

(0001FH)

CRA0

CRA8

(Initial value: **** ****)

Read/

Write

CRAn

Character code

(n: 0 to 8)

Note: Write or read CRA7 to CRA0 after write or read CRA8.

7

6

5

4

3

2

1

0

ORWVSH

(00FBCH) WVSH7 WVSH6 WVSH5 WVSH4 WVSH3 WVSH2 WVSH1 WVSH0

(Initial value: 0000 0000)

(00FBDH)

−

WVSH8

(Initial value: **** ***0)

Write

only

WVSLn

Window upper limit position

(n: 0 to 8)

7

6

5

4

3

2

1

0

ORWVSL

(00FBEH)

(00FBFH)

WVSL7 WVSL6 WVSL5 WVSL4 WVSL3 WVSL2 WVSL1 WVSL0

(Initial value: 0000 0000)

−

WVSL8

(Initial value: **** ***0)

Write

only

WVSLn

Window lower limit position

(n: 0 to 8)

7

6

5

4

3

2

1

0

ORDON

(00F80H)

−

RGWR EWDW

DON

(Initial value: **** *000)

0: (Initial state)

RGWR Written data transfer control

1: Transfers written data to OSD circuit

(after transfer, RGWR is reset to 0)

Read/

Write

Window enable specification

0: Disable window function

1: Enable window function

EWDW

register

0: Disable display

1: Enable display

DON

Display on/off select

2007-09-12

88CS38B-188

TMP88CS38B/CM38B/CP38B

7

6

5

4

3

2

1

0

ORRCL

(00FA7H)

EBKGD EXBL

AON2

AON1

RCLI

RCLR

RCLG

RCLB

(Initial value: 0000 0000)

Background function enable

specification register

0: No background function

1: Background function enable

EBKGD

EXBL

Full-raster blanking enable

specification register

0: No Full-raster blanking

1: Full-raster blanking

Area 2 plane display enable

specification register

0: No area 2 plane display

1: Area 2 plane display enable

AON2

AON1

Area 1 plane display enable

specification register

0: No area 1 plane display

1: Area 1 plane display enable

0000: Black

0001: Blue

0010: Green

0011: Cyan

0100: Red

Write

only

0101: Magenta

0110: Yellow

0111: White

RCLI

RCLR/

RCLG/

RCLB

Raster plane color select

1000: Black

1001: Dark blue

1010: Dark green

1011: Dark cyan

1100: Dark red

1101: Dark magenta

1110: Dark yellow

1111: Gray

Note:

Set RCLI to 1 when PISEL (Bit6 in ORETC) sets to 1. Then transfer plane select is 8 variety.

2007-09-12

88CS38B-189

TMP88CS38B/CM38B/CP38B

7

6

5

4

3

2

1

0

ORAHS1

(00FA8H)

(00FA9H)

AHS17 AHS16 AHS15 AHS14 AHS13 AHS12 AHS11 AHS10

AHS18

(Initial value: 0000 0000)

−

(Initial value: **** ***0)

ORAHE1

(00FAAH)

AHE17 AHE16 AHE15 AHE14 AHE13 AHE12 AHE11 AHE10

(Initial value: 0000 0000)

(00FABH)

−

AHE18

(Initial value: **** ***0)

AHS1n

AHE1n

Horizontal start point for area 1 plane

Horizontal end point for area 1 plane

Write

only

(n: 0 to 8)

ORAVS1

(00FACH)

(00FADH)

AVS17 AVS16 AVS15 AVS14 AVS13 AVS12 AVS11 AVS10

AVS18

(Initial value: 0000 0000)

−

(Initial value: **** ***0)

ORAVE1

(00FAEH)

AVE17 AVE16 AVE15 AVE14 AVE13 AVE12 AVE11 AVE10

(Initial value: 0000 0000)

(00FAFH)

−

AVE18

(Initial value: **** ***0)

AVS1n

AVE1n

Vertical start point for area 1 plane

Vertical end point for area 1 plane

Write

only

(n: 0 to 8)

ORAHS2

(00FB0H)

(00FB1H)

AHS27 AHS26 AHS25 AHS24 AHS23 AHS22 AHS21 AHS20

AHS28

−

ORAHE2

(00FB2H)

AHE27 AHE26 AHE25 AHE24 AHE23 AHE22 AHE21 AHE20

(Initial value: 0000 0000)

(00FB3H)

−

AHE28

(Initial value: **** ***0)

AHS2n

AHE2n

Horizontal start point for area 2 plane

Horizontal end point for area 2 plane

Write

only

(n: 0 to 8)

ORAVS2

(00FB4H)

(00FB5H)

AVS27 AVS26 AVS25 AVS24 AVS23 AVS22 AVS21 AVS20

AVS28

(Initial value: 0000 0000)

−

(Initial value: **** ***0)

ORAVE2

(00FB6H)

AVE27 AVE26 AVE25 AVE24 AVE23 AVE22 AVE21 AVE20

(Initial value: 0000 0000)

(00FB7H)

−

AVE28

(Initial value: **** ***0)

AVS2n

AVE2n

Vertical start point for area 2 plane

Vertical end point for area 2 plane

Write

only

(n: 0 to 8)

2007-09-12

88CS38B-190

TMP88CS38B/CM38B/CP38B

7

6

5

4

3

2

1

0

ORP6S

(00FBAH)

P67S

P66S

P65S

P64S

PIDS YBLCS

MPXS

(Initial value: 0000 0000)

P67S to

P64S

0: R, G, B, Y/BL signal output

1: P67 to P64 port output

P6 port output select

I pin output select

0: I signal output

1: P57 port output

PIDS

0: Y signal output

1: BL signal output

00: Simultaneous output (Signal from the OSD circuit has

higher priority)

YBLCS Y/BL signal select

Write

only

01: Output of signal from internal OSD circuit

10: Output of signal from externally input

11: Simultaneous output (Externally input signal has

higher priority)

MPXS

R, G, B, Y/BL signal select

7

6

5

4

3

2

1

0

ORETC

(00FB8H)

VDSMD PISEL BKMF ESMZ

“0”

MFYWR MBK RDWRV

(Initial value: 0000 0000)

0: Normal mode

1: Double scan mode

0: 15 colors

1: Half transparency/half tone

0: Double blinking

1: Enable blinking

VDSMD Scan mode select

PISEL

BKMF

ESMZ

I pin function select

Blinking master

Smoothing enable specification

register

0: Disable smoothing

1: Enable smoothing

Write

only

Display memory read mode

select

0: Normal mode

1: Read-modify-write mode

MFYWR

MBK

0: Access to either character code or character display

options

1: Access both character display option and character

code

Display memory bank

switching

0: Data write mode for display memory

1: Data read mode for display memory

RDWRV Read/write mode select

Note: Clear “0” to bit3 in ORETC.

2007-09-12

88CS38B-191

TMP88CS38B/CM38B/CP38B

7

6

5

4

3

2

1

0

ORIRC

(00FB9H)

−

SDV

ISDC

(Initial value: ***0 0000)

0: Interrupt request by ISDC value

1: Interrupt request at falling edge of VD signal

When the line display of the ISDC value ends (with the

falling edge of HD signal)

SVD

Interrupt source select

while SVD = 0, interrupt request is generated.

0000: Request interrupt when display of low-order 4 bits

“0000” of DCTR ends.

0001: Low-order 4 bits “0001” of DCTR

0010: Low-order 4 bits “0010” of DCTR

0011: Low-order 4 bits “0011” of DCTR

0100: Low-order 4 bits “0100” of DCTR

0101: Low-order 4 bits “0101” of DCTR

0110: Low-order 4 bits “0110” of DCTR

0111: Low-order 4 bits “0111” of DCTR

1000: Low-order 4 bits “1000” of DCTR

1001: Low-order 4 bits “1001” of DCTR

1010: Low-order 4 bits “1010” of DCTR

1011: Low-order 4 bits “1011” of DCTR

1100: Low-order 4 bits “1100” of DCTR

1101: Low-order 4 bits “1101” of DCTR

1110: Low-order 4 bits “1110” of DCTR

1111: Low-order 4 bits “1111” of DCTR

Write

only

ISDC

Interrupt generation line select

ORIRC

−

DCTR

(Initial value: **** 0000)

(00FB9H)

0000: No line display or when the display of the 16th line

ends.

0001: 1st line display ends.

0010: 2nd line display ends.

0011: 3rd line display ends.

0100: 4th line display ends.

0101: 5th line display ends.

0110: 6th line display ends.

0111: 7th line display ends.

1000: 8th line display ends.

1001: 9th line display ends.

1010: 10th line display ends.

1011: 11th line display ends.

1100: 12th line display ends.

1101: 13th line display ends.

1110: 14th line display ends.

1111: 15th line display ends.

Read

only

DCTR

Display line counter

Note 1: The display line counter also increments when a line with all blank data or a line with display off is specified.

If display lines are overlapped each other, previous display line is enabled and next line is disabled. At this

time, the display line counter for canceled line does not increment.

Note 2: *: Don’t care.

Note 3: All OSD control registers cannot use the read-modify-write instructions. (Bit manipulation instructions such

as SET, CLR, etc. and logical operation such as AND, OR, etc.)

2007-09-12

88CS38B-192

TMP88CS38B/CM38B/CP38B

Table 2.15.5.10 OSD Control Register List (1/2)

Register Bit Configuration

Register

Address

Register

Name

Bit Contents

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

00F81

00F82,

00F83 to

00F98,

00F99

00F9A

00F9B

00F9C

00F9D

00F9E

00F9F

00FA0

00FA2

00FA3

00FA4

00FA5

ORHS1

ORVSn

HS17

VSn7

−

HS16

VSn6

−

HS15

VSn5

−

HS14

VSn4

−

HS13

VSn3

−

HS12

VSn2

−

HS11

VSn1

−

HS10

VSn0

VSn8

HS17 to 10: Code horizontal display base position setting

VSn8 to 0: Code vertical display position setting

(n: 0 to 12)

ORCS4

ORCS8

CS4

CS8

CS3

CS7

CS2

CS6

CS1

CS5

CS9

CSn: Character size (n: 1 to 12)

00: Display off

01: Large size

10: Middle size

11: Small size

ORCS12

OREULA8

OREULA12

OREFR8

OREFR12

ORSOL4

ORSOL8

ORSOL12

ORBK

CS12

CS11

CS10

EULA8

EULA7

EULA6

EULA5

EULA4

EULA3

EULA2

EULA1

EULA9

EFR1

EULAn: Underline display setting for line n (n: 0 to 12)

−

EFR8

−

EFR7

−

EFR6

−

EFR5

−

EULA12 EULA11 EULA10

EFR4

EFR3

EFR2

EFRn: Fringing setting for line n (n: 0 to 12)

EFR12

EFR11

EFR10

EFR9

SOL4

SOL3

SOL2

SOL1

SOLn: Solid space display setting for line n (n: 0 to 12)

00: No solid space

01: Left

10: Right

11: Left and right

SOL8

SOL7

SOL6

SOL5

SOL9

SOL12

SOL11

SOL10

IBDT

RBDT

GBDT

BBDT

IFDT

RFDT

GFDT

BFDT

IBDT, RBDT, GBDT, BBDT: Background color setting

IFDT, RFDT, GFDT, BFDT: Fringing color setting

ACLI2/ACLR2/ACLG2/ACLB2: Area 2 plane color

ACLI1/ACLR1/ACLG1/ACLB1: Area 1 plane color

Set ACLI2 and SCLI1 to 1, when PISEL 1

EBKGD: Background function

00FA6

00FA7

ORACL

CRRCL

ACLI2

ACLR2

ACLG2

AON2

ACLB2

ACLI1

RCLI

ACLR1

ACLG1

RCLG

ACLB1

EBKGD

EXBL

AON1

RCLR

RCLB

EXBL: Full-raster blanking

AON2: Area 2 plane display

AON1: Area 1 plane display

RCLI/R/G/B: Raster plane color

Set RCLI to 1, when PISEL 1

00FA8

00FA9

00FAA

00FAB

00FAC

00FAD

00FAE

00FAF

00FB0

00FB1

00FB2

00FB3

00FB4

00FB5

00FB6

00FB7

00FB8

ORAHS1

ORAHE1

ORAVS1

ORAVE1

ORAHS2

ORAHE2

ORAVS2

ORAVE2

ORETC

AHS17

AHS16

AHS15

AHS14

AHS13

AHS12

AHS11

AHS10

AHS18

AHE10

AHE18

AVS10

AHS18

AVE10

AVE18

AHS20

AHS28

AHE20

AHE28

AVS20

AHS28

AVE20

AVE28

AHSx: Area 1 plane horizontal start position (n: 0 to 8)

−

AHE16

−

AVS16

−

AVE16

−

AHS26

−

AHE26

−

AVS26

−

AVE26

−

PISEL

−

AHE15

−

AVS15

−

AVE15

−

AHS25

−

AHE25

−

AVS25

−

AVE25

−

BKMF

−

AHE14

−

AVS14

−

AVE14

−

AHS24

−

AHE24

−

AVS24

−

AVE24

−

ESMZ

−

AHE17

AHE13

AHE12

AHE11

AHE1x: Area 1 plane horizontal end position (n: 0 to 8)

AVS1x: Area 1 plane vertical start position (n: 0 to 8)

AVE1x: Area 1 plane vertical end position (n: 0 to 8)

AHS2x: Area 2 plane horizontal start position (n: 0 to 8)

AHE2x: Area 2 plane horizontal end position (n: 0 to 8)

AVS2x: Area 2 plane vertical start position (n: 0 to 8)

AVE2x: Area 2 plane vertical end position (n: 0 to 8)

−

AVS17

−

AVE17

−

AHS27

−

AHE27

−

AVS27

−

AVE27

−

AVS12

−

AVE12

−

AHS22

−

AHE22

−

AVS22

−

AVE22

−

AVS11

−

AVE11

−

AHS21

−

AHE21

−

AVS21

−

AVE21

−

AVS13

−

AVE13

−

AHS23

−

AHE23

−

AVS23

−

AVE23

−

“0”

VDSMD

MFYWR

MBK

RDWRV VDSMD: Scan mode select

PISEL: I pin function select

BKMF: Blinking master

ESMZ: Smoothing

MFYWR: Display memory read mode select

MBK: Display memory bank switching select

RDWRV: Read/write mode select at normal mode

SVD: Interrupt source select

00FB9

ORIRC

−

SVD

ISDC

ISDC: Interrupt generation line select

DCTR: Display line counter

00FB9

00FBA

ORIRC

ORP6S

−

DCTR

YBLCS

P67S

P66S

P65S

P64S

PIDS

MPXS

P6xS: P6 port output select (x: 4 to 7)

PIDS: I pin output select

YBLCS: Y/BL signal select

MPXS: R, G, B, Y/BL single select

2007-09-12

88CS38B-193

TMP88CS38B/CM38B/CP38B

Table 2.15.5.11 OSD Control Register List (2/2)

Register Bit Configuration

Register

Address

Register

Name

Bit Contents

Bit7

Bit6

Bit5

Bit4

Bit3

YIV

Bit2

BLIV

Bit1

Bit0

IIV

00FBB

ORIV

VDPOL

HDPOL

YBLII

RGBII

RGBIV

VDPOL: VD input polarity select

HDPOL: HD input polarity select

YBLII: Y/BLIN input polarity select

RGBII: RIN, GIN, BIN input select

YIV: Y output polarity select

BLIV: BL output polarity select

RGBIV: R, G, B output polarity select

IIV: I pin polarity select

00024

00025

0001D

ORDMA

ORDSN

ORCRA

ORWVSH

ORWVSl

ORDON

DMA7

DMA6

−

SLNT

DMA5

−

EUL

DMA4

−

BLF

DMA3

−

IDT

DMA2

−

RDT

DMA1

−

GDT

DMA0

DMA8

BDT

DMAx: Display memory address setting (x: 0 to 8)

−

SLNT: Slant

BLF: Blinking

EUL: Underline

IDT/RDT/CDT/BDT: Character color

0001E

0001F

00FBC

00FBD

00FBE

00FBF

00F80

CRA7

CRA6

CRA5

CRA4

CRA3

CRA2

−

WVSH2

−

WVSL2

−

RGWR

CRA1

−

WVSH1

−

WVSL1

−

EWDW

CRA0

CRA8

CRAx: Character code (x: 0 to 8)

−

WVSH7

WVSH6

WVSH5

WVSH4

WVSH3

WVSH0 WVSHx: Window upper limit position (x: 0 to 8)

−

WVSH8

WVSL7

WVSL6

WVSL5

WVSL4

WVSL3

WVSL0 WVSL: Window lower limit position (x: 0 to 8)

WVSL8

−

DON

RGWR: Writing data transfer control

EWDW: Window enable

DON: OSD display on/off

Note 1: Except the meshed registers are changed by RGWR.

Note 2: Only lower 2 bits of the register in address 00F80H are changed by RGWR (the register in address 00F80H

must not be used with any of the read-modify-write instructions as SET, CLR, etc.).

2007-09-12

88CS38B-194

TMP88CS38B/CM38B/CP38B

2.16 Jitter Elimination Circuit

The TMP88CS38B/CM38B/CP38B has a built-in jitter elimination circuit which maintains

the vertical stability of the OSD even when input of the vertical signal fluctuates.

And the field decision information for the OSD circuit is detected by using jitter elimination

circuit.

2.16.1 Configuration

Jitter removal status register

Phase detect signal PDF [2:0]

JRMSR

Previous field

Field decision

decision

signal

A Y

B

circuit

S

HD (P70)

VD (P71)

A

B

Y

VD

Internal VD signal

output control

circuit

HD / VD

Delay value

(To OSD

circuit)

Edge detect circuit

setting circuit

VDSEL

VD signal delay value

measuring circuit

AFLD

JEEN

fc/2

JECR

Jitter elimination control register

Figure 2.16.1 Jitter Elimination Circuit

2007-09-12

88CS38B-195

TMP88CS38B/CM38B/CP38B

2.16.2 Control

Jitter elimination circuit is controlled by the jitter elimination control register (JECR).

Jitter Elimination Control Register

7

6

5

4

3

2

1

0

JECR

(00FE4H)

−

VDSEL AFLD

JEEN

“0”

(Initial value: ***0 0000)

0:

1:

VD from P71

VD from jitter elimination circuit

VDSEL VD select

Write

only

0: Automatic field decision disabled

1: Automatic field decision enabled

0: Jitter elimination disabled

AFLD

JEEN

Automatic field decision

Jitter elimination enable specification

1: Jitter elimination enabled

Note 1: Clear the AFLD to “0” to disable jitter elimination circuit.

Note 2: Always clear “0” to bit1 and bit0 of JECR.

Note 3: Clear “0” to AFLD and VDSEL if there is no phase shift in the vertical and horizontal sync. signals every

other time, such as with non-interlaced TV.

Note 4: *: Don’t care

Note 5: Setting JEEN to “0”, OSD display is only 2nd field.

Note 6: Setting AFLD to “0”, OSD display is only 2nd field.

Jitter Elimination Status Register

7

6

5

4

3

2

1

0

JESR

(00FE5H)

FDSF

PDF1

PDF0

−

PDF2

(Initial value: 0*** ****)

0: A position of a scanning line exists in the field

which has a second display dot of character on an

interlace TV screen.

1: A position of a scanning line exists in the field

which has a first display dot of character on an

interlace TV screen.

FDSF

Field detect status flag

Read

only

000: Phase 0

001: Phase 1

010: Phase 2

PDF2 to

PDF0

011: Phase 3

100: Phase 4

Phase detect flag between HD and VD

101: Phase 5

110: Phase 6

111: Phase 7

Note 1: FDSF is different from the 1st and the 2nd field. It is a unique field decided for OSD display.

Note 2: *: Don’t care.

Note 3:

HD

VD

Phase 7

Phase 0

Phase 1

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 0

Figure 2.16.2 Jitter Elimination Control Register and Jitter Elimination Status Register

2.16.3 Jitter Elimination Mode

The jitter elimination circuit is to identify the phase of the falling edges of the external

VD signal and HD signal. When VD signal is falling within HD signal falling +/−1/4HD,

the jitter is automatically eliminated and internal VD signal is set to the stable location.

This function is enabled by setting JEEN (Bit2 in JECR) in the jitter elimination control

register to “1”.

2007-09-12

88CS38B-196

TMP88CS38B/CM38B/CP38B

2.16.4 Auto Field Line Decision

The internal vertical and horizontal sync. signals corrected by the jitter elimination

circuit generate the field line decision signals used in the OSD.

The OSD display in normal mode

Type A)

Type B)

When the OSD circuit is used on the TV system which has a phase shift in the

vertical and horizontal sync. Signals every other filed such as the interlace

TV, enable jitter elimination circuit and set “1” to AFLD and VDSEL. At this

time, the field lines which have first and second display dot of character are

displayed.

When the OSD circuit is used on the TV system which has no phase shift in

the vertical and horizontal sync. Signals every other filed such as the

non-interlace TV, enable jitter elimination circuit and clear “0” to AFLD and

VDSEL. At this time, the field line which has a second display dot of

character is only displayed.

The OSD display in double scan mode

Type C)

Disable jitter elimination circuit and clear “0” to AFLD and VDSEL. At this

time, the field lines which have first and second display dot of character are

displayed.

(2) The field line which has a

second display dot of

character

(1) The field line which has a

first display dot of

character

Scanning System

Register

Display

(1) and (2)

(2)

Type A

Type B

Type C

VDSEL = 1, AFLD = 1

VDSEL = 0, AFLD = 0

(1) and (2)

Figure 2.16.3 Relation with Field Line and VDSEL, AFLD

2007-09-12

88CS38B-197

TMP88CS38B/CM38B/CP38B

2.17 Data Slicer

The TMP88CS38B/CM38B/CP38B contains the data slicer to decode the caption data which

multiplied during vertical flyback time of the composite video signal.

The composite video signal inputs to the data slicer circuit through P32 (VIN1) and P33

(VIN0). The caption data is decoded from the video signal. The composite video signal including

negative sync-tip inputs to VIN0 and VIN1 pins. The data slicer can comply with the copy guard

signal and special signals, and receive accurately the caption data under the condition of a weak

electrical field or a ghost.

Note: When the data slicer is used at fc = 16 MHz, set to “02H” in FC8CR.

When the data slicer is used at fc = 8 MHz, set to “00H” in FC8CR. (Refer to Figure 1.4.5)

2.17.1 Configuration

A0

A1

S

Z

Slicer mode setting register 1

SIF status read register 2

(00FDFH)

SYNCINV

EXSYNC

C.Sync external input mode

C.Sync signal

SIFSMS1/SIFS1R

Synchronous separator

V

IN1

Sync-tip clamp

Com-

parator 1

circuit

H timing circuit

V timing circuit

Composite

video

LINE21

signal

INTSLI

(to interrupt)

Clamping pulse

V

IN0

Pedestal clamp

circuit

Com-

parator 2

Sampling clock

generation

circuit

Slice level control

circuit

Data separator

SIFSR

(00FDDH)

Slicer interface

circuit

DA converter

DACLCR

SLVLCR

SIFDR1

(00FDBH)

SIFDR2

(00FD9H)

(00FDAH)

(00FDCH)

Sync-tip slice level

setting register

Slice level

control register

Data register 1 Data register 2

Figure 2.17.1 Data Slicer

2007-09-12

88CS38B-198

TMP88CS38B/CM38B/CP38B

2.17.2 Functions

(1) Video signal input

A low pass filter, a voltage amplifier and a condenser of about 0.1 μF are connected

between the video signal and the video signal input pin of VIN1 and VIN0 pins, that is

shown as Figure 2.17.3 the low pass filter functions to reduce noise and color burst

from the video signal, passes the amplifier and inputs the video signal to both VIN1

and VIN0 pins.

(2) Synchronous separator

This circuit is to separate the synchronous signal from the video signal. When

DACL7 to DACL0 of DACLCR are set for the synchronous separation, the sync slice

level is capable of setting. DACL7 to DACL4 set the slice level at the rising edge of the

sync signal clamped data, and DACL3 to DACL0 set the slice level at the falling edge of

the sync-tip clamped data. (Refer to section 2.17.5)

(3) Data separator

The data separator replaces the caption data piled on the video signal with the

digital signal.

When SLVL5 to SLVL0 of SLVLCR are set to get the digital signal, the Initial value

of the caption data slice level is capable of setting. (Refer to section 2.17.5)

(4) Sync-tip clamp circuit

The sync-tip level is clamped to the specified value.

(5) Pedestal clamp circuit

The video signal is set to the specified voltage with the clamp pulse generated from

the H/V timing part, which is called as a pedestal clamp.

(6) DA converter

This converter gets the DA changed slice level of the clamp circuit to the comparator.

(7) Comparator

This comparator replaces the composite video signal with the digital value while

inputting to the comparator.

(8) H timing circuit

This circuit detects the horizontal synchronous signal from C.Sync signal separated

synchornously from the video signal, and generates the clamp pulse to clamp the video

signal and provides it to the pedestal clamp circuit. In addition, the circuit detects the

change of H frequency and provides the data to the sampling clock generation part.

(9) V timing circuit

This circuit detects the horizontal synchronous signal from C.Sync signal separated

synchornously from the video signal, and provides line 21 detection signal to take out

caption signal to the slice level control part.

(10) Slice level control circuit

This circuit detects CRI (Clock run in) signal from VIDEO signal with line 21

detection signal generated at H/V timing part after slicing, and controls to the most

suitable slice level and takes out the caption data.

2007-09-12

88CS38B-199

TMP88CS38B/CM38B/CP38B

(11) Sampling clock generation circuit

This circuit generates the sampling clock which is phase-locked to CRI signal with

CRI signal detected at the slice level control part. In addition, the circuit revises the

location where the sampling clock generates with H frequency variable data generated

at H timing generation part.

(12) Slicer interface circuit

This is a 16-bit serial interface to receive the serial data.

(13) Interrupt generation circuit

Interrupts are generated by a rise in the caption line detection signal.

Video signal

Caption line

7.7 μs

Caption line detection signal ( LINE21 )

95 μs

Interrupt generation

Figure 2.17.2 Interrupt Generation Timing

See the description of the on-screen display circuit interrupt vectors for details of

interrupt vectors.

(14) C.Sync external input mode

The external C.Sync signal can be used internally by setting EXSYNC (SIFSMS1

bit5) to “1“.

As shown in Figure 2.17.3 (b), insert a low-pass filter (f = 503 kHz), voltage

T

amplifier

(× 2 voltage amplification), and a capacitor of approximately 0.1 μF between the video

signal and the video signal input pin VIN1 and input an external C.Sync signal to

CSIN.

The polarity of the C.Sync signal is selected by SYNCINV (SIFSMS1 bit6).

(Internally used as C.Sync .)

CSIN (P32)

C.Sync (

SYNCINV

)

“0”

“1”

2007-09-12

88CS38B-200

TMP88CS38B/CM38B/CP38B

2.17.3 Video Signal Connection

TMP88CS38B/CM38B/CP38B

Outer circuit

0.1 μF

(1.0 V

)

PP

Composite

video signal

P32 (VIN1)

P33 (VIN0)

(2 V

)

PP

Low pass filter

Amplifier

(a) Internal sync separation mode

TMP88CS38B/CM38B/CP38B

Outer circuit

Ext.C.Sync

signal

(5.0 V

(1.0 V

)

PP

P32 (CSIN)

P33 (VIN0)

Composite

video signal

PP

(2 V

)

PP

0.1 μF

Low pass filter

Amplifier

(b) C.sync external input mode

Figure 2.17.3 Video Signal Connection

Data Slicer Control Register

7

6

5

4

3

2

1

0

SINTCR

(00FD8H)

−

SLON

SLCR

−

(Initial value: 0000 00**)

1: Enable

0: Disable

1: Enable interrupt

0: Disable interrupt

SLON

SLCR

Data slicer enable/disable

Data slicer interrupt control

Write

only

Data Slicer Interrupt Satus Register

7

6

5

4

3

2

1

0

SINTCR

(00FD8H)

−

SLIS

−

(Initial value: ***0 ****)

0:

−

Read

only

SLIS

Data slicer interrupt status

1: Interrupt request

Note 1: For setting SCLR to “1”, write “1” after SLON is set to “1”.

Note 2: SLIS is cleared to “0” after reading SINTCR.

Figure 2.17.4 Data Slicer Control (I)

2007-09-12

88CS38B-201

TMP88CS38B/CM38B/CP38B

SIF Data Register 1 (Caption data 1st byte read register) (Read only)

7

6

5

4

3

2

1

0

SIFDR1

(00FDBH)

D1ST7 D1ST6 D1ST5 D1ST4 D1ST3 D1ST2 D1ST1 D1ST0

Read

only

D1ST7-0 Caption data 1st byte read register

SIF Data Register 2 (Caption data 2nd byte read register) (Read only)

7

6

5

4

3

2

1

0

SIFDR2

(00FDCH)

D2ST7 D2ST6 D2ST5 D2ST4 D2ST3 D2ST2 D2ST1 D2ST0

Read

only

D2ST7-0 Caption data 2nd byte read register

SIF Status Register (Read only)

7

6

5

4

3

2

1

0

SIFST

(00FDDH)

STCRI CRIN3 CRIN2 CRIN1 CRIN0 STFLD STSB

STDE

1: Clock run in detection

0: No clock run in detection

STCRI

CRIN

Clock run in detection

CRI number − 1

Actual CRI number − 1

1: 2nd field

0: 1st field

STFLD Field identification

Read

only

1: From detection of start bit until fall in VD

0: Other times

STSB

STDE

Start bit identification flag

16-bit data receive end identification

flag

1: From end of 16-bit data reception until fall in VD

0: Other times

Figure 2.17.5 Data Slicer Control (II)

Slicer Mode Setting Register 1 (Write only)

7

6

5

4

3

2

1

0

SIFSMS1

(00FDFH)

SYNC

INV

(Initial value: 0001 1011)

“0”

EXSYNC

“1”

CLINE3 CLINE2 CLINE1 CLINE0

0:

1:

0:

1:

No inversion

Inversion of C.Sync external input signal

Internal sync separation

SYNCINV Sync signal input inversion

EXSYNC Sync signal selection

External C.Sync input

0000: 10 lines

0001: 11 lines

0010: 12 lines

0011: 13 lines

0100: 14 lines

0101: 15 lines

0110: 16 lines

0111: 17 lines

1000: 18 lines

1001: 19 lines

1010: 20 lines

1011: 21 lines

1100: 22 lines

1101: 23 lines

1110: 24 lines

1111: 25 lines

Write

only

CLINE

Setting lines piled on caption data

Note:

Always write “0” to bit7 of SIFSMS1 and “1” to bit4 when writing to SIFSMS1.

Figure 2.17.6 Data Slicer Control (III)

2007-09-12

88CS38B-202

TMP88CS38B/CM38B/CP38B

SIF Status Read Register 2

7

6

5

4

3

2

1

0

SIFS1R

(00FDFH)

−

GOODV FLINE4 FLINE3 FLINE2 FLINE1 FLINE0

0:

1:

Out of synchronization (One or more)

V timing synchronizing

GOODV Monitor signal of synchronization

00000: 0

00001: 1

00010: 2

00011: 3

00100: 4

00101: 5

00110: 6

00111: 7

01000: 8

01001: 9

01010: 10

01011: 11

01100: 12

01101: 13

01110: 14

01111: 15

263.5

264.5

Read

only

Field scanning line

(Standard 262.5 = − 1)

Two’s complement

278.5

FLINE

10000: V synchronizing adjustment

10001: − 15

10010: − 14

10011: − 13

10100: − 12

10101: − 11

10110: − 10

10111: − 9

11000: − 8

11001: − 7

11010: − 6

11011: − 5

11100: − 4

11101: − 3

11110: − 2

11111: − 1

248.5

261.5

262.5

Figure 2.17.7 Data Slicer Control (IV)

The explanation of the monitor signals (GOODV, FLINE) are as follows.

1.GOODV 0: Data slicer can not synchronize video signal.

1: Data slicer can synchronize video signal.

2.FLINE The number of field signal scanning line which the data slicer is detecting or

monitor flag of detecting state.

Example:

FLINE = 1FH: NTSC signal

FLINE = 10H: V synchronizing adjustment

2007-09-12

88CS38B-203

TMP88CS38B/CM38B/CP38B

Caption Data Slice Level Control Register (Write/Read)

7

6

5

4

3

2

1

0

SLVLCR

(00FDAH)

−

SLVL5 SLVL4 SLVL3 SLVL2 SLVL1 SLVL0

(Initial value: **00 1010)

000000: VPCLAMP + (1/256) V

DD

000001: VPCLAMP + (2/256) V

000010: VPCLAMP + (3/256) V

000011: VPCLAMP + (4/256) V

000100: VPCLAMP + (5/256) V

Slice level (Initial value:) setting

Sice level setting

SLVL

Write

Read

.

111101: VPCLAMP + (62/256) V

111110: VPCLAMP + (63/256) V

111111: VPCLAMP + (64/256) V

DD

Slice level (final value)

Note 1: VPCLAMP (Pedestal clamp) = (1/2) V

DD

Note 2: The SLVLCR has different write buffer and read buffer, and cannot be read write-buffer fata. The SBIDBR

cannot be used with any read-modify-write instructions. (Bit manipulation instructions such as SET, CLR,

etc. and logical operation such as AND, OR, etc.)

Sync-tip Slice Level Setting Register (Write only)

7

6

5

4

3

2

1

0

DACLCR

(00FD9H)

DACL7 DACL6 DACL5 DACL4 DACL3 DACL2 DACL1 DACL0

(Initial value: 0100 0010)

DD

0000: VSCLAMP + (3/512) V

0001: VSCLAMP + (6/512) V

DD

0010: VSCLAMP + (9/512) V

DACL7 to DACL4:Slice level

Lower limit setting

DACL3 to DACL0:Slice level

Upper limit setting

0011: VSCLAMP + (12/512) V

DD

Write

only

DACL

.

1101: VSCLAMP + (42/512) V

1110: VSCLAMP + (45/512) V

1111: VSCLAMP + (48/512) V

DD

Note:

VSCLAMP (Sync-tip clamp) = (204/512) V

DD

Figure 2.17.8 Data Slicer Control (V)

2007-09-12

88CS38B-204

TMP88CS38B/CM38B/CP38B

2.17.4 Clamp and Data Slicer Operation

The slicer uses the following steps to obtain the caption signals:

The composite video signal input via VIN1 (Pin 40) is clamped by the sync tip

clamp circuit and the HD and VD sync signals separated by the sync separation

circuit.

Sync signal separation

Caption line detection

CRI detection

Field decision and caption line detection are effected using the HD and VD sync

signals

The CRI signal of the caption line interval is detected from the pedestal clamped

video signal at VIN0 (Pin 41).

The slice level is controlled during the CRI signal interval, detected by the slice

level control block, to obtain the optimum level.

Slice level setting and

generation of sampling clock

To determine the timing for extracting the caption data, a sampling clock is

generated that is phase locked to the CRI.

The caption data is extracted at the selected slice level using sampling clock,

which is locked to the caption data.

Caption signal extraction

The data slicer has two separation circuits:

a. Sync signal (sync tip clamp + sync signal slice) separation.

b. Caption data (pedestal clamp + data slice) separation.

The two circuits are described briefly below.

2007-09-12

88CS38B-205

TMP88CS38B/CM38B/CP38B

a. Sync signal (Sync tip clamp + sync signal slice)

a-1 Sync tip clamp (Pin 40) ........The sync tip is clamped at (204/512) V

in Figure 2.17.9.

[V] as shown

DD

A, B: Sync tip slice levels

A: DACL7 to DACL4

Video signal

1

2

Lower-limit setting

B: DACL3 to DACL0

Upper-limit setting

B

A

(204/512) V

DD

[V]

GND

After sync signal separation

H

L

Figure 2.17.9 Sync Signal Slice

a-2 Method of sync signal slice

The sync signal is separated as shown in Figure 2.17.9.

Sync signal separation is accomplished by comparing the voltage of the sync

tip-clamped video signal with the sync tip slice level. For a 1 → 2 video signal

change, if the sync signal after separation is high, the slice level A is selected; if

low, the slice level B is selected.

(Sync tip slice level)

Slice level = VSCLAMP + {(3 + 3X)/512} V

DD

V

: Power supply voltage

DD

VSCLAMP: Sync tip clamp voltage = (204/512) V

DD

X: Setup data (4 bits)

2007-09-12

88CS38B-206

TMP88CS38B/CM38B/CP38B

b. Caption data (Pedestal clamp + data slice)

b-1 Pedestal clamp (Pin 41)......Clamped at (1/2) V

[V] as shown in Figure 2.17.10.

DD

Slice level

(1/2) V

DD

[V]

GND

Figure 2.17.10 Pedestal Clamp

b-2 Method of data slice

The data slice level constitutes a level at which the CCD data is differentiated.

The slice level’s setup value is indicated by the following:

Slice level = VPCLAMP + (X/256) V

[V]

DD

V

: Power supply voltage

DD

VPCLAMP: Pedestal clamp voltage = (1/2) V

DD

X: Setup data (6 bits)

b-3 Automatic slice level correction circuit

The slice level is corrected to the appropriate value during the CRI period.

Slice level correction always begins with the setup value of SLVL (Bit5 to bit0 of

SLVLCR).

If you want the last value to become the initial value of the next slice level, set it

to SLVL (Bit5 to bit0 of SLVLCR).

2007-09-12

88CS38B-207

TMP88CS38B/CM38B/CP38B

Input/Output Circuit

(1) Control pins

The input/output circuitries of the TMP88CS38B/CM38B/CP38B control pins are shown

below.

Control Pin

I/O

Input/Output Circuitry

Remarks

Resonator connection pins

(High frequency)

Osc. enable

VDD

fc

VDD

XIN

XOUT

R

f

R = 1.2 MΩ (typ.)

f

I/O

R

O

R

O

= 0.5 kΩ (typ.)

XIN

XOUT

Sink open-drain output

Hysteresis input

Pull-up resistor

VDD

R

IN

R

Address-trap-reset

Watchdog-timer-reset

System-clock-reset

RESET

I/O

R

= 220 kΩ (typ.)

IN

R = 1 kΩ (typ.)

Hysteresis input

VDD

R = 1 kΩ (typ.)

STOP /INT5

(P20)

Input

R

P20/ STOP /INT5

Pull-down resistor

VDD

R

IN

= 70 MΩ (typ.)

R = 1 kΩ (typ.)

TEST

Input

R

IN

Pin for connecting a resonator

for on-screen display

Osc. enable

VDD

fc

VDD

R = 1.2 MΩ (typ.)

f

OSC1

OSC2

R

f

R

O

I/O

R

O

= 0.5 kΩ (typ.)

OSC1

OSC2

2007-09-12

88CS38B-208

TMP88CS38B/CM38B/CP38B

Remarks

(2) Input/output ports

Port

I/O

Input/Output Circuitry

Sink open-drain output

Hysteresis input

VDD

Initial “High-Z”

R = 1 kΩ (typ.)

P20

I/O

R

Tri-state I/O

Hysteresis input

VDD

P30

to

Initial “High-Z”

P33

R = 1 kΩ (typ.)

P50,

P57

I/O

R

Disable

P70,

P71

Tri-state I/O or open-drain

output programmable

Hysteresis input

VDD

Initial “High-Z”

Open drain

output enable

P34,

P35,

I/O

P51,

P52

R = 1 kΩ (typ.)

R

Disable

Tri-state I/O

R = 1 kΩ (typ.)

VDD

Initial “High-Z”

P40

to

I/O

R

Disable

P47

Tri-state I/O

Hysteresis input

VDD

Initial “High-Z”

Key-on wakeup input

(V = 0.65 × V

IL4

DD)

P53

to

R

Disable

I/O

R = 1 kΩ (typ.)

R

A

C

A

= 5 kΩ (typ.)

= 22 pF (typ.)

P56

C

A

R

A

Key-on

wakeup

2007-09-12

88CS38B-209

TMP88CS38B/CM38B/CP38B

Remarks

Port

I/O

Input/Output Circuitry

Sink open-drain output

High current output

VDD

Initial “High-Z”

Disable

I

= 20 mA (typ.)

OL

R = 1 kΩ (typ.)

R

P60,

P61

I/O

R

C

= 5 kΩ (typ.)

= 22 pF (typ.)

A

C

A

R

A

Key-on wakeup input

Key-on

wakeup

(V = 0.65 × V

IL4

DD)

Tri-state I/O

High current output

VDD

Initial “High-Z”

Disable

I

= 20 mA (typ.)

OL

P62

(at

CSOUT)

I/O

R = 1 kΩ (typ.)

R

Sink open-drain output

High current output

I

VDD

Initial “High-Z”

Disable

= 20 mA (typ.)

OL

P62,

P63

R = 1 kΩ (typ.)

R

Tri-state I/O

R = 1 kΩ (typ.)

VDD

Initial “High-Z”

Disable

P64

to

R

P67

2007-09-12

88CS38B-210

TMP88CS38B/CM38B/CP38B

Electrical Characteristics

Absolute Maximum Ratings

(V = 0 V)

SS

Parameter

Symbol

Pins

Ratings

Unit

Supply voltage

V

−

−0.3 to 6.5

DD

V

Input voltage

−0.3 to V

+ 0.3

IN

DD

Output voltage

OUT1

OUT2

OUT1

OUT2

I

Ports P2, P3, P4, P5, P64 to P67, P7

3.2

30

Output current (Per 1 pin)

Output current (Total)

Ports P60 to P63

mA

Σ I

Ports P2, P3, P4, P5, P64 to P67, P7

120

Ports P60 to P63

TMP88CS38: 600

TMP88CP38A/CM38A: 400

Power dissipation [Topr = 70°C]

Soldering temperature (Time)

Storage temperature

PD

−

mW

Tsld

Tstg

Topr

260 (10 s)

−55 to 125

−30 to 70

°C

Operating temperature

Note: The absolute maximum ratings are rated values which must not be exceeded during operation,

even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is

exceeded, a device may break down or its performance may be degraded, causing it to catch fire or

explode resulting in injury to the user. Thus, when designing products which include this device,

ensure that no absolute maximum rating value will ever be exceeded.

Recommended Operating Conditions

(V = 0 V, Topr = −30 to 70°C)

SS

Parameter

Symbol

Pins

Conditions

Min

Max

Unit

Fc = 16 MHz NORMAL mode

Supply voltage

V

4.5

5.5

Fc = 16 MHz IDLE mode

DD

STOP mode

V

Except hysteresis input

Hysteresis input

V

× 0.70

IH1

IH2

IL1

IL2

IL4

DD

V

Input high voltage

Input low voltage

V

= 4.5 to 5.5V

V

DD

× 0.75

Except hysteresis input

Hysteresis input

V

× 0.30

× 0.25

× 0.65

DD

0

DD

Key-on wakeup input

XIN, XOUT

V

= 4.5 to 5.5V

DD

fc

8.0

16.0

Clock frequency

MHz

fc = 8 MHz

12.0

24.0

f

OSC1, OSC2

V

= 4.5 to 5.5V

OSC

DD

fc = 16 MHz

16.0

Note 1:The recommended operating conditions for a device are operating conditions under which it can be

guaranteed that the device will operate as specified. If the device is used under operating conditions

other than the recommended operating conditions (Supply voltage, operating temperature range,

specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include

this device, ensure that the recommended operating conditions for the device are always adhered

to.

Note 2:Clock frequency fc: Supply voltage range is specified in NORMAL mode and IDLE mode.

Note 3:Smaller value is alternatively specified as the maximum value.

2007-09-12

88CS38B-211

TMP88CS38B/CM38B/CP38B

DC Characteristics

Parameter Symbol

(V = 0 V, Topr = −30 to 70°C)

SS

Pins

Hysteresis inputs

TEST

Conditions

Min

−

Typ. Max Unit

Hysteresis voltage

V

0.9

−

±2

450

2

V

HS

IN1

IN2

IN3

IN4

I

V

= 5.5 V, V = 5.5 V/0 V

IN

−

DD

Open-drain ports

Tri-state ports

RESET , STOP

RESET

= 5.5 V, V = 5.5 V/0 V

IN

−

Input current

μA

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

= 5.5 V, V = 5.5 V/0 V

IN

−

= 5.5 V, V = 5.5 V/0 V

IN

−

Input resistance

R

= 5.5 V, V = 0 V

IN

100

−

220

−

kΩ

μA

IN2

LO1

LO2

I

Sink open-drain ports

Tri-state ports

= 5.5 V, V

= 5.5 V

OUT

Output leakage

current

= 5.5 V/0 V

−

±2

−

Output high voltage

Output low voltage

Output low current

V

= 4.5 V, I

= − 0.7 mA

OH

4.1

−

OH2

V

Except XOUT, OSC2 and

ports P60 to P63

V

= 4.5 V, I = 1.6 mA

OL

−

0.4

−

OL

DD

I

Port P60 to P63

= 4.5 V, V = 1.0 V

20

25

OL3

OL

Supply current in

NORMAL mode

30

V

= 5.5 V

DD

mA

fc = 16 MHz

= 5.3 V/0.2 V

(Note 3)

Supply current in

IDLE mode

V

IN

I

−

20

25

10

DD

Supply current in

STOP mode

V

= 5.5 V

DD

= 5.3 V/0.2 V

0.5

μA

IN

Note 1:Typical values show those at Topr = 25°C, V = 5 V.

DD

Note 2:Input current I : The current through resistor is not included.

IN3

Note 3:Supply current I : The current (Typ. 0.5 mA) through ladder resistors of ADC is included in

DD

NORMAL mode and IDLE mode.

AD Conversion Characteristics

(V = 0 V, V

SS

= 4.5 V to 5.5 V, Topr = −30 to 70°C)

DD

Parameter

Symbol

Conditions

Min

Typ.

Max

Unit

V

supplied from V

pin.

−

V

−

AREF

DD

0

Analog reference voltage

V

supplied from V pin.

ASS

SS

V

Analog reference voltage range

Analog input voltage

Nonlinearity error

Zero point error

ΔV

= V

− V

DD SS

V

AREF

DD

V

−

V

DD

AIN

SS

−

±1

±2

±3

−

V

= 5.0 V

LSB

DD

Full scale error

Total error

Note: The total error means all error except quanting error.

2007-09-12

88CS38B-212

TMP88CS38B/CM38B/CP38B

AC Characteristics

Parameter

(V = 0 V, V

SS

= 4.5 V to 5.5 V, Topr = −30 to 70°C)

DD

Symbol

Conditions

Min

Typ.

Max

Unit

in NORMAL mode

Machine cycle time

t

0.5

−

1.0

μs

cy

in IDLE mode

High level clock pulse width

Low level clock pulse width

T

for external clock operation

(XIN input), fc = 16 MHz

WCH

31.25

−

ns

T

WCL

Recommended Oscillating Conditions

(V = 0 V, V

SS

= 4.5 V to 5.5 V, Topr = −30 to 70°C)

DD

Recommended

Constant

Oscillation

Frequency

Parameter

Oscillator

Recommended Oscillator

C₁

C₂

High-frequency

oscillation

Ceramic resonator

8 MHz

Murata

CSA 8.00MTZ

30 pF

16 MHz

CSA 16.00MXZ040

5 pF

XIN

XOUT

C

1

C

2

High-frequency oscillation

Note 1:To keep reliable operation, shield the device electrically with the metal plate on its package mold

surface against the high electric field, for example, by CRT (Cathode ray tube).

Note 2:The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are

subject to change. For up-to-date information, please refer to the following URL:

http://www.murata.co.jp/search/index.html

2007-09-12

88CS38B-213

TMP88CS38B/CM38B/CP38B

Recommended Oscillating Conditions

(V = 0 V, V

SS

= 4.5 V to 5.5 V, Topr = −30 to 70°C)

DD

Oscillation

Frequency

Recommended Parameter Value

Item

Resonator

L (μH)

C₁(pF)

C₂(pF)

8 MHz

12 MHz

16 MHz

20 MHz

24 MHz

33

15

5 to 30

5 to 25

10

Oscillation for OSD

LC resonator

10

6.8

4.7

OSC1

OSC2

L

C

1

C

2

Oscillation for OSD

The frequency generated in LC oscillation can be obtained using the following equations.

1

C ･C

1 2

f =

,C =

C + C

2π LC

1

2

C is not fixed at a constant value. It can be changed to tune into the desired frequency.

1

Note 1:Toshiba’s OSD circuit determines a horizontal display start position by counting clock pulses

generated in LC oscillation. For this reason, the OSD circuit may fail to detect clock pulses normally,

resulting in the horizontal start position becoming unstable, at the beginning of oscillation, if the

oscillation amplitude is low.

Changing L and C from the values recommended for a specific frequency may hamper a stable

2

OSD display.

If the LC oscillation frequency is the same as a high-frequency clock value, the oscillation of the

high-frequency oscillator may cause the LC oscillation frequency to fluctuate, thus making OSD

displays flicker.

When determining these parameters, please check the oscillation frequency and the stability of

oscillation on your TV sets.

Also check the determined parameters on your final products, because the optimum parameter

values may vary from one product to another.

Note 2:When using the LSI package in a strong electric field, such as near a CRT, electrically shield the

package so that its normal operation can be maintained.

2007-09-12

88CS38B-214

TMP88CS38B/CM38B/CP38B

Notice of ROM Entry

When you make a ROM data entry for TMP88CS38B and TMP88CM38B/CP38B,

Please transfer one file including program area, vector table area and OSD font area.

The ROM area must be transferred is as follows.

TMP88CM38B

Program area

TMP88CS38B

Program area

TMP88CP38B

Program area

4000H

FEFFH

BEFFH

13EFFH

20000H

25FFFH

FFF00H

FFFFFH

20000H

25FFFH

FFF00H

FFFFFH

OSD font area

25FFFH

FFF00H

FFFFFH

Vector table

area

Vector table

area

Vector table

area

Flow of ROM data entry

After evaluation finished

OSD font

Program and vector table

Program

vector table

OSD font

Two files are merged into one file.

ROM data entry

2007-09-12

88CS38B-215

TMP88CS38B/CM38B/CP38B

Package

P-SDIP42-600-1.78

Unit: mm

2007-09-12

88CS38B-216

TMP88CS38B/CM38B/CP38B

Unit: mm

P-QFP44-1414-0.80K

2007-09-12

88CS38B-217

TMP88CS38B/CM38B/CP38B

2007-09-12

88CS38B-218


型号：	TMP88CP38BNG
厂家：	TOSHIBA
描述：	CMOS 8-Bit Microcontroller 8位CMOS微控制器微控制器和处理器外围集成电路光电二极管时钟
文件：	总218页 (文件大小：2024K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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