TMP91CK27UG_技术文档

TOSHIBA Original CMOS 16-Bit Microcontroller

TLCS-900/L1 Series

TMP91CU27UG

TMP91CP27UG

TMP91CK27UG

TMP91CU27FG

Semiconductor Company

Preface

Thank you very much for making use of Toshiba microcomputer LSIs.

Before use this LSI, refer the section, “Notes and Restrictions”.

Especially, take care below cautions.

**CAUTION**

How to release the HALT mode

Usually, interrupts can release all halts stats. However, the interrupts = (NMI,

INT0, INTRTC), which can release the HALT mode may not be able to do so if

they are input during the period CPU is shifting to the HALT mode (for about 5

clocks of f_FPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case).

(In this case, an interupt request is kept on hold internally.)

If another interupt is generated after it has shifted to HALT mode completely,

halt status can be released without difficultly. The priority of this interrupt is

compare with that of the interrupt kept on hold internally, and the interrupt with

higher priority is handled first followed by the other interrupt.

TMP91CU27/CP27/CK27

CMOS 16-Bit Microcontrollers

TMP91CU27UG/TMP91CP27UG/TMP91CK27UG/TMP91CU27FG

1. Outline and Features

The TMP91CU27/CP27/CK27 are high-speed 16-bit microcontrollers designed for the control of

various mid- to large-scale equipment.

The TMP91CU27UG/CP27UG/CK27UG/CU27FG come in a 64-pin flat package respectively.

Listed below are the features.

Product Name

RAM

ROM

Package

TMP91CU27UG

TMP91CP27UG

TMP91CK27UG

TMP91CU27FG

10KB

4KB

96KB

48KB

24KB

96KB

LQFP64-P-1010-0.50D

QFP64-P-1414-0.80A

1KB

10KB

(1) High-speed 16-bit CPU (900/L1 CPU)

•

Instruction mnemonics are upward-compatible with TLCS-90/900

16 Mbytes of linear address space

General-purpose registers and register banks

16-bit multiplication and division instructions; bit transfer and arithmetic instructions

Micro DMA: 4 channels (593 ns/2 bytes at 27 MHz)

RESTRICTIONS ON PRODUCT USE

20070701-EN

• The information contained herein is subject to change without notice.

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical

stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety

in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such

TOSHIBA products could cause loss of human life, bodily injury or damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as

set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and

conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability

Handbook” etc.

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer,

personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These

TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high

quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury

(“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship

instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical

instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall

be made at the customer’s own risk.

• The products described in this document shall not be used or embedded to any downstream products of which

manufacture, use and/or sale are prohibited under any applicable laws and regulations.

• The information contained herein is presented only as a guide for the applications of our products. No responsibility

is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its

use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third

parties.

• Please contact your sales representative for product-by-product details in this document regarding RoHS

compatibility. Please use these products in this document in compliance with all applicable laws and regulations that

regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring

as a result of noncompliance with applicable laws and regulations.

2008-01-24

91CU27-1

TMP91CU27/CP27/CK27

(2) Minimum instruction execution time: 148 ns (at 27 MHz)

(3) External memory expansion

Expandable up to 16 Mbytes (Shared program/data area)

Can simultaneously support 8-/16-bit width external data bus (Dynamic data bus sizing)

(4) 8-bit timers: 6 channels

(5) 16-bit timers: 1 channel

(6) General-purpose serial interface: 2 channels

•

UART/Synchronous mode: 2 channels

IrDA Ver.1.0 (115.2 kbps) mode selectable: 1 channel

(7) Serial bus interface: 1 channel

I²C bus mode/clock synchronous mode selectable

•

(8) 10-bit AD converter (Sample hold circuit is inside): 4 channels

(9) Watchdog timer

(10) Special timer for CLOCK

(11) Chip select/wait controller: 4 blocks

(12) Interrupts: 34 interrupts

•

9 CPU interrupts: Software interrupt instruction and illegal instruction

21 internal interrupts: 7 priority levels are selectable

4 external interrupts: 7 priority levels are selectable

(among 3 interrupts are selectable edge mode)

(13) Input/output ports: 53 pins

(14) Standby function

Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP

(15) Clock controller

•

Clock gear function: Select a high-frequency clock fc to fc/16

Special timer for CLOCK (fs = 32.768 kHz)

(16) Operating voltage

•

V_CC= 2.7 V to 3.6 V (fc max = 27 MHz)

V_CC= 1.8 V to 3.6 V (fc max = 10 MHz)

(17) Package

•

LQFP64-P-1010-0.50D（TMP91CU27UG, TMP91CP27UG, TMP91CK27UG）

QFP64-P-1414-0.80A（TMP91CU27FG）

2008-01-24

91CU27-2

TMP91CU27/CP27/CK27

DVCC

DVSS

X1

ADTRG (P53)

CPU (TLCS-900/L1)

High-speed

oscillator

AN0 to AN3

(P50 to P53)

XWA

XBC

XDE

XHL

XIX

W A

B C

D E

H L

10-bit

X2

4-ch AD

converter

AVCC, AVSS

Clock gear

IX

IY

XT1 (P96)

XT2 (P97)

Low speed

oscillator

XIY

XIZ

IZ

RESET

AM0

AM1

ALE

TXD0 (P90)

RXD0 (P91)

SCLK0/ CTS0 (P92)

XSP

SP

SIO/UART/IrDA

(Channel 0)

32 bits

SR

PC

F

TXD1 (P93)

RXD1 (P94)

SCLK1/ CTS1 (P95)

(P00 to P07)

AD0 to AD7

(P10 to P17)

AD8/A8 to AD15/A15

(P20 to P25)

A0/A16 to A5/A21

SIO/UART

Port 0

Port 1

Port 2

(Channel 1)

Watchdog

timer

SCK (P60)

SO/SDA (P61)

SI/SCL (P62)

Serial bus

interface

(WDT)

RD (P30)

WR (P31)

HWR (P32)

Special timer

for CLOCK

8-bit timer

Port 3

TA0IN (P70)

(TMRA0)

8-bit timer

(TMRA1)

TA1OUT (P71)

8-bit timer

(TMRA2)

Port 6

8-bit timer

(TMRA3)

TA3OUT (P72)

(P40 to P42)

CS0 to CS2

CS/WAIT

10-Kbyte RAM

96-Kbyte ROM

controller

(4 blocks)

8-bit timer

(TMRA4)

TA4IN (P73)

NMI

Interrupt

controller

INT0 (P63)

8-bit timer

(TMRA5)

TA5OUT (P74)

TB0IN0/INT5 (P80)

TB0IN1/INT6 (P81)

TB0OUT0 (P82)

TB0OUT1 (P83)

16-bit timer

(TMRB0)

( ): Initial function after resert

Figure 1.1 TMP91CU27 Block Diagram

2008-01-24

91CU27-3

TMP91CU27/CP27/CK27

DVCC

DVSS

X1

CPU (TLCS-900/L1)

ADTRG (P53)

AN0 to AN3

(P50 to P53)

High-speed

oscillator

XWA

W A

B C

D E

H L

10-bit 4-ch

AD

X2

XBC

XDE

XHL

XIX

converter

Clock gear

AVCC, AVSS

IX

IY

XT1 (P96)

XT2 (P97)

Low speed

oscillator

XIY

XIZ

IZ

RESET

AM0

AM1

ALE

TXD0 (P90)

RXD0 (P91)

SCLK0/ CTS0 (P92)

XSP

SP

SIO/UART/IrDA

(Channel 0)

32 bits

SR

PC

F

TXD1 (P93)

RXD1 (P94)

SCLK1/ CTS1 (P95)

(P00 to P07)

AD0 to AD7

(P10 to P17)

AD8/A8 to AD15/A15

(P20 to P25)

A0/A16 to A5/A21

SIO/UART

Port 0

Port 1

Port 2

(Channel 1)

Watchdog

timer

SCK (P60)

SO/SDA (P61)

SI/SCL (P62)

Serial bus

interface

(SBI)

(WDT)

RD (P30)

WR (P31)

HWR (P32)

Special timer

for CLOCK

8-bit timer

(TMRA 0)

Port 3

TA0IN (P70)

8-bit timer

(TMRA 1)

TA1OUT (P71)

8-bit timer

(TMRA 2)

Port 6

8-bit timer

(TMRA 3)

TA3OUT (P72)

CS/WAIT

(P40 to P42)

CS0 to CS2

4-Kbyte RAM

controller

(4 blocks)

8-bit timer

(TMRA 4)

TA4IN (P73)

NMI

INT0 (P63)

Interrupt

controller

8-bit timer

(TMRA 5)

TA5OUT (P74)

TB0IN0/INT5 (P80)

TB0IN1/INT6 (P81)

TB0OUT0 (P82)

TB0OUT1 (P83)

16-bit timer

(TMRB0)

48-Kbyte ROM

( ): Initial function after resert

Figure 1.2 TMP91CP27 Block Diagram

2008-01-24

91CU27-4

TMP91CU27/CP27/CK27

DVCC

DVSS

X1

ADTRG (P53)

CPU (TLCS-900/L1)

10-bit

High-speed

oscillator

AN0 to AN3

(P50 to P53)

XWA

W A

B C

D E

H L

4-ch AD

converter

X2

XBC

XDE

XHL

XIX

AVCC, AVSS

Clock gear

IX

IY

XT1 (P96)

XT2 (P97)

Low speed

oscillator

XIY

XIZ

IZ

RESET

AM0

AM1

ALE

TXD0 (P90)

RXD0 (P91)

SCLK0/ CTS0 (P92)

XSP

SP

SIO/UART/IrDA

(Channel 0)

32 bits

SR

PC

F

TXD1 (P93)

RXD1 (P94)

SCLK1/ CTS1 (P95)

(P00 to P07)

AD0 to AD7

(P10 to P17)

AD8/A8 to AD15/A15

(P20 to P25)

A0/A16 to A5/A21

SIO/UART

Port 0

Port 1

Port 2

(Channel 1)

Watchdog

timer

SCK (P60)

SO/SDA (P61)

SI/SCL (P62)

Serial bus

interface

(WDT)

RD (P30)

WR (P31)

HWR (P32)

8-bit timer

(TMRA0)

Special timer

for CLOCK

Port 3

TA0IN (P70)

8-bit timer

(TMRA1)

TA1OUT (P71)

8-bit timer

(TMRA2)

8-bit timer

(TMRA3)

Port 6

TA3OUT (P72)

(P40 to P42)

CS0 to CS2

CS/WAIT

1-Kbyte RAM

controller

(4 blocks)

8-bit timer

(TMRA4)

TA4IN (P73)

NMI

Interrupt

controller

INT0 (P63)

8-bit timer

(TMRA5)

TA5OUT (P74)

TB0IN0/INT5 (P80)

TB0IN1/INT6 (P81)

TB0OUT0 (P82)

TB0OUT1 (P83)

16-bit timer

(TMRB0)

24-Kbyte ROM

( ): Initial function after resert

Figure 1.1 TMP91CK27 Block Diagram

2008-01-24

91CU27-5

TMP91CU27/CP27/CK27

2. Pin Assignment and Pin Functions

The assignment of input/output pins for the TMP91CU27/CP27/CK27, their names and

functions are as follows:

2.1 Pin Assignment Diagram

Figure 2.1.1 shows the pin assignment of the TMP91CU27/CP27/CK27.

P61/SO/SDA

P62/SI/SCL

57

58

56 P60/SCK

55 P42/ _CS2

54 P41/ _CS1

53 P40/ _CS0

P63/INT0

P50/AN0

P51/AN1

P52/AN2

59

60

61

62

52 P32/ HWR

51 P31/ WR

P53/AN3/

AVCC

63

64

ADTRG

50 P30/

RD

49 P25/A5/A21

AVSS

1

48 P24/A4/A20

47 P23/A3/A19

46 P22/A2/A18

45 P21/A1/A17

44 P20/A0/A16

P70/TA0IN

2

3

P71/TA1OUT

P72/TA3OUT

P73/TA4IN

4

5

P74/TA5OUT

6

7

43 P17/AD15/A15

42 P16/AD14/A14

P80/TB0IN0/INT5

Top view

LQFP64, QFP64

41 P15/AD13/A13

40 P14/AD12/A12

P81/TB0IN1/INT6

P82/TB0OUT0

P83/TB0OUT1

8

9

10

39 P13/AD11/A11

38 P12/AD10/A10

P90/TXD0

P91/RXD0

11

12

37 P11/AD9/A9

36 P10/AD8/A8

35 P07/AD7

P92/SCLK0/ _CTS013

P93/TXD1

P94/RXD1

14

15

34 P06/AD6

33 P05/AD5

P95/SCLK1/

16

CTS1

32 P04/AD4

31 P03/AD3

30 P02/AD2

29 P01/AD1

AM0

DVCC

X2

17

18

19

20

DVSS

28 P00/AD0

27 ALE

X1

21

22

23

24

AM1

26

NMI

RESET

P96/XT1

25 P97/XT2

Figure 2.1.1 Pin Assignment Diagram (64-pin LQFP, 64-pin QFP)

2008-01-24

91CU27-6

TMP91CU27/CP27/CK27

2.2 Pin names and Functions

The names of the input/output pins and their functions are described below.

Table 2.2.1 to Table 2.2.3 show pin names and functions.

Table 2.2.1 Pin Names and Functions (1/3)

Number

Pin Names

I/O

Functions

of Pins

P00 to P07

AD0 to AD7

P10 to P17

AD8 to AD15

A8 to A15

P20 to P25

A0 to A5

A16 to A21

P30

8

I/O

Port 0: I/O port that allows I/O to be selected at the bit level

Address data (Lower): 0 to 7 of address/data bus

Port1: I/O port that allows I/O to be selected at the bit level

Address data (Upper): 8 to 15 of address/data bus

Address: 8 to 15 of address bus

8

6

1

I/O

Output

I/O

Port 2: I/O port that allows I/O to be selected at the bit level

Address: 0 to 5 of address bus

Output

Address: 16 to 21 of address bus

Port 30: Output port

RD

Read: Strobe signal for reading external memory when read internal area

also, output RD by setting to P3<P30> = 0, P3FC<P30F> = 1.

P31

WR

1

4

Output

I/O

Port 31: Output port

Write: Strobe signal for writing data to pins AD0 to AD7

Port 32: I/O port (with pull-up resistor)

P32

HWR

P40

CS0

Output

I/O

High write: Strobe signal for writing data to pins AD8 to AD15

Port 40: I/O port (with pull-up resistor)

Output

Chip select 0: Outputs “0” when address is within specified address area.

P41

I/O

Output

I/O

Port41: I/O port (with pull-up resistor)

CS1

Chip select 1: Outputs “0” when address is within specified address area.

Port 42: I/O port (with pull-up resistor)

Chip select 2: Outputs “0” when address is within specified address area.

Port 5: Input port

P42

CS2

Output

Input

I/O

P50 to P53

AN0 to AN3

ADTRG

P60

Analog input: Analog input pins of the AD converter

AD trigger: Pin used for request AD start (Shared with P53).

Port 60: I/O port

1

SCK

I/O

Serial bus interface clock I/O at SIO mode

Port 61: I/O port

P61

I/O

SO

Output

I/O

Serial bus interface send data at SIO mode

Serial bus interface send/receive data at I²C mode

Open-drain output mode by programmable

Port 62: I/O port

SDA

P62

SI

1

I/O

Input

I/O

Serial bus interface receive data at SIO mode

SCL

Serial bus interface clock I/O at I²C mode

Open-drain output mode by programmable

P63

I/O

Port 63: I/O port (Schmitt input)

INT0

Input

Interrupt request pin 0: Interrupt request pin with selectable

level/rising/falling edge

2008-01-24

91CU27-7

TMP91CU27/CP27/CK27

Table 2.2.2 Pin Names and Functions (2/3)

Number

of Pins

Pin Names

I/O

Functions

P70

1

I/O

Input

I/O

Port 70: I/O port

TA0IN

P71

8-bit timer 0 input: Input pin of 8-bit timer TMRA0

Port 71: I/O port

TA1OUT

P72

Output

I/O

8-bit timer 1 output: Output pin of 8-bit timer TMRA0 or TMRA1

Port 72: I/O port

TA3OUT

P73

Output

I/O

8-bit timer 3 output: Output pin of 8-bit timer TMRA2 or TMRA3

Port 73: I/O port

TA4IN

P74

Input

I/O

8-bit timer 4 input: Input pin of 8-bit timer TMRA4

Port 74: I/O port

TA5OUT

P80

Output

I/O

8-bit timer 5 output: Output pin of 8-bit timer TMRA4 or TMRA5

Port 80: I/O port

TB0IN0

INT5

Input

I/O

16-bit timer 0 Input 0: Input of count/capture trigger in 16-bit timer TMRB0

Interrupt request pin 5: Interrupt request pin with selectable rising/falling edge

Port 81: I/O port

P81

1

TB0IN1

INT6

Input

I/O

16-bit timer 0 input 1: Input of count/capture trigger in 16-bit timer TMRB0

Interrupt request pin 6: Interrupt request pin of rising edge

Port 82: I/O port

P82

1

TB0OUT0

P83

Output

I/O

16-bit timer 0 output 0: Outpit pin of 16-bit timer TMRB0

Port 83: I/O port

TB0OUT1

P90

Output

I/O

16-bit timer 0 output 1: Output pin of 16-bit timer TMRB0

Port 90: I/O port

TXD0

P91

Output

I/O

Serial 0 send data: Open-drain output pin by programmable

Port 91: I/O port

RXD0

P92

Input

I/O

Serial 0 receive data

Port 92: I/O port

SCLK0

CTS0

P93

I/O

Serial 0 clock I/O

Input

I/O

Serial 0 data send enable (Clear to send)

Port 93: I/O port

1

TXD1

P94

Output

I/O

Serial 1 send data: Open-drain output pin by programmable

Port 94: I/O port

RXD1

P95

Input

I/O

Serial 1 receive data

Port 95: I/O port

SCLK1

CTS1

P96

I/O

Serial 1 clock I/O

Input

I/O

Serial 1 data send enable (Clear to send)

Port 96: I/O port. Open-drain output pin

Low-frequency oscillator connection pin

Port 97: I/O port. Open-drain output pin

Low-frequency oscillator connection pin

1

XT1

Input

I/O

P97

XT2

Output

2008-01-24

91CU27-8

TMP91CU27/CP27/CK27

Table 2.2.3 Pin Names and Functions (3/3)

Number

of Pins

Pin Names

I/O

Functions

ALE

1

Output

Address latch enable (It can be set as prohibition of an output for noise

reduction.)

NMI

1

Input

Non-maskable interrupt request pin: Receives an interrupt request triggered

by a falling edge (Schmitt input). A rising edge can be the trigger as well with

additional programming.

AM0, AM1

2

Input

Operation mode:

Fixed to AM1 = “1” and AM0 = “1”.

RESET

AVCC

1

Reset: Initialize LSI. (Schmitt input, with pull-up resistor)

Pin used for both power supply pin for AD converter and standard power

supply for AD converter (H).

AVSS

1

Pin used for both GND pin for AD converter (0 V) and standard power supply

pin for AD converter (L).

X1

1

Input

High-frequency oscillator connection pin.

X2

Output

DVCC

Power supply pins (All DVCC pins should be connected to the power supply

pin.)

DVSS

1

GND pins (All pins shuold be connected to GND (0 V).)

2008-01-24

91CU27-9

TMP91CU27/CP27/CK27

3. Operation

This following describes block by block the functions and operation of the TMP91CU27/CP27/CK27.

3.1 CPU

The TMP91CU27/CP27/CK27 incorporate a high-performance 16-bit CPU (The 900/L1-CPU).

For CPU operation, see the “TLCS-900/L1 CPU”.

The following describe the unique function of the CPU used in the TMP91CU27/CP27/CK27;

these functions are not covered in the TLCS-900/L1 CPU section.

3.1.1

Reset

When resetting the TMP91CU27/CP27/CK27 microcontroller, ensure that the power

supply voltage is within the operating voltage range, and that the internal high-frequency

oscillator has stabilized. Then hold the RESET input to low level at least for 10 system

clocks (12 μs at 27 MHz).

Thus, when turning on the switch, the power supply voltage being set is within the

operating voltage range, and the internal high-frequency oscillator goes into a stable state.

Then hold the RESET input to Low level at least for 10 system clocks.

The clock gear is initialized 1/16 mode by reset operation. It means that the system clock

mode f_SYSis set to fc/32 (= fc/16 × 1/2).

When the reset has been accepted, the CPU performs the following:

•

Sets as follows the program counter (PC) in accordance with the reset vector stored

at address FFFF00H to FFFF02H:

PC<7:0>

←

Value at FFFF00H address

Value at FFFF01H address

Value at FFFF02H address

PC<15:8> ←

PC<23:16> ←

•

Sets the stack pointer (XSP) to 100H.

Sets bits<IFF2:0> of the status register (SR) to “111” (Sets the interrupt level mask

register to level 7).

•

Sets the <MAX> bit of the status register (SR) to “1” (MAX mode).

Clears bits<RFP2:0> of the status register (SR) to “000” (Sets the register bank to

“0”).

When reset is released, the CPU starts executing instructions in accordance with the

program counter settings. CPU internal registers not mentioned above do not change when

the reset is released.

When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows.

•

Initializes the internal I/O registers.

•

Sets the port pins, including the pins that also act as internal I/O, to

general-purpose input or output port mode.

•

Sets ALE pin to high impedance.

Note: The CPU internal register (except to PC, SR, XSP in CPU) and internal RAM data do not change by resetting.

Figure 3.1.1 is a reset timing chart of the TMP91CU27/CP27/CK27.

2008-01-24

91CU27-10

TMP91CU27/CP27/CK27

Read

Write

Figure 3.1.1 TMP91CU27/CP27/CK27 Reset Timing Chart

91CU27-11

2008-01-24

TMP91CU27/CP27/CK27

3.2 Memory Map

Figure 3.2.1, Figure 3.2.2 and Figure 3.2.3 show the memory maps of the

TMP91CU27/CP27/CK27 respectively.

000000H

Internal I/O

Direct

area (n)

(4 Kbyte)

000100H

001000H

64 Kbyte area

(nn)

Internal RAM

(10 Kbyte)

003800H

010000H

External memory

16 M byte area

(R)

(−R)

(R+)

(R + R8/16)

(R + d8/16)

(nnn)

FE8000H

96 Kbyte

Internal ROM

FFFF00H

FFFFFFH

Vecter table (256 byte)

(

= Internal area)

Figure 3.2.1 TMP91CU27 Memory Map

2008-01-24

91CU27-12

TMP91CU27/CP27/CK27

000000H

Internal I/O

(4 Kbytes)

Direct area (n)

000100H

001000H

64-Kbyte area

(nn)

Internal RAM

(4 Kbytes)

002000H

010000H

External

memory

16-Mbyte area

(R)

(−R)

(R+)

(R + R8/16)

(R + d8/16)

(nnn)

FF4000H

(

= Internal area)

48-Kbyte

Internal ROM

FFFF00H

FFFFFFH

Vecter table (256 bytes)

Figure 3.2.2 TMP91CP27 Memory Map

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91CU27-13

TMP91CU27/CP27/CK27

000000H

Internal I/O

(4 Kbyte)

Direct

area (n)

000100H

001000H

001400H

Internal RAM

(1 Kbyte)

64 Kbyte area

(nn)

010000H

External memory

16 Mbyte area

(R)

(−R)

(R+)

(R + R8/16)

(R + d8/16)

(nnn)

FFA000H

24 Kbyte

Internal ROM

FFFF00H

FFFFFFH

Vector table (256 byte)

(

= Internal area)

Figure 3.2.3 TMP91CK27 Memory Map

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3.3 Diversity of TMP91CW12A and TMP91CU27/CP27/CK27

The TMP91CU27/CP27/CK27 achieved downsizing TMP91CW12A with less pins and

functions. The specification of the functions is shown in the section 3.3.1 to 3.3.6. Wide

difference of AC/DC characteristic is AC characteristics (Shown section 3.3.7). For the details,

please refer to Chapter 4, “Electrical characteristics”.

3.3.1

Cut Internal I/O

The TMP91CU27/CP27/CK27 are micro controllers that reduced 8-bit timer (TMRA6 to

TMRA7), 16-bit timer (TMRB1) and clock doublers circuit (DFM) from TMP91CW12A.

Please doesn’t access to special function register address of above internal I/O in

TMP91CW12A.

Please refer to “Table of special function register”.

3.3.2

Cut Port Function

The TMP91CU27/CP27/CK27 reduced the following port functions from TMP91CW12A.

•

Port 2: P27 (A23/A7) and P26 (A22/A6)

Port 3: P37, P36 ( R / W ), P35 (BUSAK ), P34 ( BUSRQ ) and P33 ( WAIT )

•

Port 4: P43 (CS3)

Port 5: P57 to P54 (AN7 to AN4)

Port 6: P66, P65 and P64 (SCOUT)

Port 7: P75 (TA7OUT)

Port 8: P87 (TB1OUT1), P86 (TB1OUT0), P85 (TB1IN1/INT8) and

P84 (TB1IN0/INT7)

•

Port A: PA7 to PA4, PA3 to PA0 (INT4 to INT1)

3.3.3

Cut factor of Interrupt

TMP91CU27/CP27/CK27 be cut factor of interrupt by cut internal I/O and port function

(Refer to Table 3.5.1). Please don’t access to interrupt priority setting register for cut factor

of interrupt. Please refer to “table of special function register”.

3.3.4

3.3.5

Bus Release Function

TMP91CU27/CP27/CK27 don’t include bus release function by cutting bus request pin

(P34) and bus acknowledge pin (P35).

CS/WAIT Controller

When set TMP91CU27/CP27/CK27 to BxCS<BxW2:0> = “010” (1 + N) WAIT mode, it

operates as 1 wait by cutting WAIT pin.

And there is not CS3 pin (P43), but when set MSAR3, MAMR3 and set B3CS<B3E> = “1”,

wait control is effective.

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3.3.6

3.3.7

AD Converter

Analog input pin AN4 to AN7 be cut. Therefore please don’t select cutting channel in

ADMOD1<ADCH2:0>.

AC Characteristic

When accessing to external, AC characteristic don’t guarantee at 2 V operation.

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3.4 System Clock Function and Standby Control

The TMP91CU27/CP27/CK27 contains (1) a clock gear, (2) stand-by controller and (3)

noise-reduction circuits. It is used for low-power and low-noise systems.

The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b)

Dual clock mode (X1, X2, XT1 and XT2 pins).

Figure 3.4.1 shows a transition figure.

Reset

(f

/32)

OSCH

Release

Instruction

Interrupt

IDLE2 mode

(I/O operate)

Instruction

Interrupt

NORMAL mode

/gear value/2)

STOP mode

(Stops all circuits)

Instruction

Interrupt

(f

OSCH

IDLE1 mode

(Operate only oscillator)

(a)

Single clock mode transition figure

Reset

(f

/32)

OSCH

Instruction

Interrupt

Release

IDLE2 mode

(I/O operate)

NORMAL mode

/gear value/2)

Instruction

Interrupt

Instruction

Interrupt

(f

OSCH

IDLE1 mode

(Operate only oscillator)

STOP mode

(Stops all circuits)

Instruction

Interrupt

IDLE2 mode

(I/O operate)

SLOW mode

(fs/2)

Instruction

Interrupt

IDLE1 mode

(Operate only oscillator)

(b)

Dual clock mode transition fiigure

Figure 3.4.1 Clock Operating Mode

Note: The clock frequency input from the X1 and X2 pins is called f

and the clock frequency input from the XT1

OSCH

and XT2 pins is called fs. The clock frequency selected by SYSCR1<SYSCK> is called f

. The system clock

FPH

f

is defined as the divided clock of f

, and one cycle of f

FPH

is defined as one state.

SYS

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3.4.1

Block Diagram of System Clock

SYSCR0<WUEF>

SYSCR2<WUPTM1:0>

SYSCR0

Warm-up timer

φT

<PRCK1:0>

(for high/low frequency oscillator)

φT0

fc/16

÷2 ÷4

SYSCR0

f

FPH

<XTEN, RXTEN>

fs

f

FPH

Low-

frequency

oscillator

XT1

XT2

fs

f

SYS

÷2

fc

fc/2

SYSCR0

<XEN, RXEN>

SYSCR1<SYSCK>

fc/4

fc/8

fc/16

X1

X2

High-

frequency

oscillator

÷2 ÷4 ÷8 ÷16

f

SYSCR1<GEAR2:0>

OSCH

Clock gear

f

SYS

CPU

ROM

RAM

TMRA01 to TMRA45

Prescaler

φT0

Interrupt

TMRB0

Prescaler

controller

WDT

I/O port

ADC

SIO0 to SIO1

Prescaler

CS/WAIT

controller

SBI

φT

Prescaler

Special timer for CLOCK

Binary counter

fs

Figure 3.4.2 Block Diagram of System Clock

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3.4.2

SFR

7

6

5

4

3

2

1

0

SYSCR0 Bit symbol

XEN

XTEN

RXEN

RXTEN

RSYSCK

WUEF

PRCK1

PRCK0

(00E0H)

Read/Write

Reset State

Function

R/W

1

0

1

0

High-

Low-

High-

Low-

Selects

Warm-up Select prescaler clock

00: f

frequency frequency frequency frequency clock after timer

FPH

oscillator

(fc)

oscillator

(fs)

oscillator

(fc) after

oscillator

(fs) after

release of control

01: Reserved

10: fc/16

0 Write:

Don’t

STOP

release of release of mode

11: Reserved

0:Stop

0: Stop

care

1 Write:

Start

STOP

mode

0: Stop

STOP

mode

0: Stop

0: fc

1: fs

1:Oscillation 1: Oscillation

(Note 2)

warm-up

0 Read:

End

1: Oscillation 1: Oscillation

warm-up

1 Read:

Do not

end

warm-up

7

6

5

4

3

2

1

0

SYSCR1 Bit symbol

SYSCK

GEAR2

GEAR1

GEAR0

(00E1H)

Read/Write

Reset State

Function

R/W

0

1

0

Select

Select gear value of high frequency

system

clock

0: fc

(fc)

000: fc

001: fc/2

1: fs

010: fc/4

011: fc/8

100: fc/16

101: (Reserved)

110: (Reserved)

111: (Reserved)

7

6

5

4

3

2

1

0

SYSCR2 Bit symbol

−

R/W

0

WUPTM1 WUPTM0 HALTM1

HALTM0

R/W

DRVE

R/W

(00E2H)

Read/Write

Reset State

Function

R/W

1

R/W

0

R/W

1

0

Always

Select warm-up time for HALT mode

00: Reserved

Pin state

control in

STOP

write to “0”. oscillator

01: STOP mode

10: IDLE1 mode

11: IDLE2 mode

00: Reserved

8

01: 2 /inputted frequency

mode

14

0: I/O off

1: Remains

the state

before

10: 2 /inputted frequency

16

11: 2 /inputted frequency

HALT

Note 1: The unassigned registers, SYSCR1<bit7:4>, SYSCR2<bit7,bit1> are read as undefined value.

Note 2: When using internal SBI, set prescaler clock select register SYSCR0<PRCK1:0> to f

.

FPH

Figure 3.4.3 SFR for System Clock

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7

6

5

4

3

2

1

0

EMCCR0 Bit symbol

PROTECT

–

R/W

0

–

R/W

–

R/W

ALEEN

R/W

0

EXTIN

R/W

0

DRVOSCH DRVOSCL

(00E3H)

Read/Write

Reset State

Function

R

0

R/W

1

R/W

1

0

Protect flag Always

Always

write “1”.

Always

write “0”.

1: ALE

1: fc

fc oscillator fs oscillator

0: OFF

1: ON

write “0”.

output

enable

external driver ability driver ability

clock

1: NORMAL

0: WEAK

1: NORMAL

0: WEAK

0: ALE

output

disable

EMCCR1 Bit symbol

(00E4H)

Protect OFF by writing “1FH”.

Protect ON by writing except “1FH”.

Read/Write

Reset State

Function

Note 1: When restarting the oscillator from the stop oscillation state (e.g. restarting the oscillator in STOP mode), set

the drive function of the oscillator circuit to NORMAL. When shifting to HALT state while stop mode is set, set

EMCCR0<DRVOSCH>, <DRVOSCL>=”1” before executing a HALT instruction.

Note 2: When V_CCexceeds 2.7V, EMCCR0<DRVOSCH> to “1”.

Figure 3.4.4 SFR for Noise Reduction

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3.4.3

System Clock Controller

The system clock controller generates the system clock signal (f_SYS) for the CPU core and

internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency

(fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc or fs,

SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator,

and SYSCR1<GEAR2:0> sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2,

fc/4, fc/8 or fc/16). These functions can reduce the power consumption of the equipment in

which the device is installed.

The combination of settings <XEN> = “1”, <XTEN> = “0”, <SYSCK> = “0” and

<GEAR2:0> = “100” will cause the system clock (f_SYS) to be set to fc/32 (fc/16 × 1/2) after a

Reset.

For example, f_SYSis set to 0.84 MHz when the 27 MHz oscillator connected to the X1 and

X2 pins.

(1) Switching from NORMAL mode to SLOW mode

When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins,

the warm-up timer can be used to change the operation frequency after stable

oscillation has been attained.

The warm-up time can be selected using SYSCR2<WUPTM1:0>.

This warm-up timer can be programmed to start and stop as shown in the following

examples 1 and 2.

Table 3.4.1 shows the warm-up time.

Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed.

Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time.

Note 3: Note of using low-frequency oscillator

When connect low-frequency oscillator to ports 96 and 97, need below setting for cut consumption power.

(Case of resonators)

Set P9CR<P96C, P97C> = “11”, P9<P96, P97> = “00”

(Case of oscillator)

Set P9CR<P96C, P97C> = “11”, P9<P96, P97> = “10”

Table 3.4.1 Warm-up Times (when changing clock)

At

Select Warm-up Time

SYSCR2<WUPTM1:0>

Change to NORMAL (fc)

Change to SLOW (fs)

f

= 27 MHz,

OSCH

fs = 32.768 kHz

8

01 (2 /frequency)

9.0 [μs]

7.8 [ms]

500 [ms]

2000 [ms]

14

10 (2 /frequency)

0.607 [ms]

2.427 [ms]

16

11 (2 /frequency)

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Example 1:Setting the clock

Changing from high frequency (fc) to low frequency (fs).

SYSCR0

SYSCR1

SYSCR2

EQU

00E0H

00E1H

EQU

LD

00E2H

(SYSCR2), X−11− −X−B

6, (SYSCR0)

2, (SYSCR0)

NZ, WUP

; Sets warm-up time to 2¹⁶/fs.

SET

BIT

; Enables low-frequency oscillation.

; Clears and starts warm-up timer.

WUP:

;

Detects stopping of warm-up timer.

;

JR

SET

RES

3, (SYSCR1)

7, (SYSCR0)

; Changes f_SYSfrom fc to fs.

; Disables high-frequency oscillation.

X: Don’t care, −: No change

<XEN>

X1 and X2 pins

<XTEN>

XT1 and XT2 pins

Warm-up timer

Counts up by fs

End of warm-up timer

<SYSCK>

fc

fs

System clock f

SYS

Disabiles

high-frequency

Enables

Clears and starts

warm-up timer

Chages f

SYS

from fc to fs

low-frequency

End of warm-up timer

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Example 2: Setting the clock

Changing from low frequency (fs) to high frequency (fc).

SYSCR0

SYSCR1

SYSCR2

EQU

00E0H

00E1H

EQU

LD

00E2H

(SYSCR2), X−10−−X−B

7, (SYSCR0)

2, (SYSCR0)

NZ, WUP

; Sets warm-up time to 2¹⁴/fc.

SET

BIT

; Enables high-frequency oscillation.

; Clears and starts warm-up timer.

WUP:

;

Detects stopping of warm-up timer.

;

JR

RES

3, (SYSCR1)

6, (SYSCR0)

; Changes f_SYSfrom fs to fc.

; Disables low-frequency oscillation.

X: Don’t care, −: No change

<XEN>

X1 and X2 pins

<XTEN>

XT1 and XT2 pins

Counts up by f

Warm-up timer

End of warm-up timer

<SYSCK>

OSCH

fs

fc

System clock f

SYS

Chages f

SYS

from fs to fc

Enables

high-frequency

Clears and starts

warm-up timer

Disables

low-frequency

End of warm-up

timer

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(2) Clock gear controller

When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> = “0”, f_FPH

is set according to the contents of the clock gear select register SYSCR1<GEAR2:0> to

either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fFPH

reduces power consumption.

Below show example of changing clock gear.

Example 3:Changing to a clock gear

SYSCR1

EQU

LD

00E1H

Changes f

to fc.

(SYSCR1), XXXX0000B

;

FPH

SYS

to fc/2.

X: Don’t care

(Clock gear changing)

To change the clock gear, write the register value to the SYSCR1<GEAR2:0> register.

It is necessary for the warm-up time to elapse before the changing occurs after writing

the register value.

There is the possibility that the instruction following the clock gear changing

instruction is executed by the clock gear before changing. To execute the instruction

following the clock gear switching instruction by the clock gear after changing, input

the dummy instruction as follows (instruction to execute the write cycle).

Example:

SYSCR1

EQU

LD

00E1H

Changes f

to fc/4.

(SYSCR1), XXXX0001B

(DUMMY), 00H

;

SYS

LD

Dummy instruction

Instruction to be executed after clock gear has changed.

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3.4.4

3.4.5

Prescaler Clock Controller

For the internal I/O (TMRA01 to TMRA45, TMRB0, SIO0 to SIO1 and SBI) there is a

prescaler which can divide the clock.

The φT, φT0 clock input to the prescaler is either the clock f_FPHdivided by 2 or the clock

fc/16 divided by 4. The setting of the SYSCR0<PRCK1:0> register determines which clock

signal is input.

When using internal SBI, set SYSCR0<PRCK1:0> to “00”.

Noise Reduction Circuits

Noise reduction circuits are built in, allowing implementation of the following features.

(1) Reduced drivability for high-frequency oscillator

(2) Reduced drivability for low-frequency oscillator

(3) Single drive for high-frequency oscillator

(4) Output ALE pin disable

(5) SFR protection of register contents

The above functions are performed by making the appropriate settings in the EMCCR0

to EMCCR1 registers.

(1) Reduced drivability for high-frequency oscillator

(Purpose)

Reduces noise and power for oscillator when a resonator is used.

(Block diagram)

f

OSCH

X1 pin

C1

Enable oscillation (STOP + EMCCR0<EXTIN>)

Resonator

EMCCR0<DRVOSCH>

C2

X2 pin

(Setting method)

The drivability of the oscillator is reduced by writing “0” to EMCCR0

<DRVOSCH> register. At reset, <DRVOSCH> is initialized to “1” and the

oscillator starts oscillation by normal drivability when the power supply is on.

When V_CC< 2.7 V, don’t use this function. When V_CC< 2.7 V, don’t set EMCCR0

<DRVOSCH> to “0”.

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(2) Reduced drivability for low-frequency oscillator

(Purpose)

Reduces noise and power for oscillator when a resonator is used.

(Block diagram)

XT1 pin

C1

Enable oscillation

Resonator

C2

EMCCR0<DRVOSCL>

f

S

XT2 pin

(Setting method)

The drivability of the oscillator is reduced by programming “0” to the

EMCCR0<DRVOSCL> register. At Reset, <DRVOSCL> is initialized to “1”. The

oscillation starts in the NORMAL mode at power-on.

(3) Single drive for high-frequency oscillator

(Purpose)

Remove the need for twin drives and prevent operational errors caused by noise

input to X2 pin when an external oscillator is used.

(Block diagram)

f

OSCH

X1 pin

Enable oscillation (STOP+EMCCR0<EXTIN>)

EMCCR0<DRVOSCH>

X2 pin

(Setting method)

The oscillator is disabled by programming “1” to EMCCR0<EXTIN> register. X2

pin’s output is always “1”.

At reset, <EXTIN> is initialized to “0”.

Note: Do not write EMCCR0<EXTIN> = “1” when using external resonator.

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(4) Output ALE pin disable

(Purpose)

Not need noise of clock property case of don’t access external area is reduced.

(Block diagram)

EMCCR0<ALEEN>

Internal

ALE

ALE pin

(Setting method)

Output buffer of ALE pin is output disable by programming “0” to

EMCCR0<ALEEN>. And ALE pin is high impedance.

At resetting, <ALEEN> is initialized to “0”.

When you access to external area, you must program “1” to <ALEEN> before

access.

(5) Runaway prevention using SFR protection register

(Purpose)

Prevention of program runaway caused by introduction of noise.

Write operations to a specified SFR are prohibited so that the program is

protected from runaway caused by stopping of the clock or by changes to the

memory control register (CS/WAIT controller) which prevent fetch operations.

Specified SFR list

1. CS/WAIT controller

B0CS, B1CS, B2CS, B3CS, BEXCS,

MSAR0, MSAR1, MSAR2, MSAR3,

MAMR0, MAMR1, MAMR2, MAMR3

2. Clock gear (write enable only EMCCR1)

SYSCR0, SYSCR1, SYSCR2, EMCCR0

(Block diagram)

Protect register

EMCCR0<PROTECT>

Write except “1FH” to EMCCR1

S

R

Q

Write signal to specified SFR

Write signal to other SFR

Write “1FH” to EMCCR1

Write signal to SFR

(Setting method)

If writing except “1FH” code to EMCCR1 register, it becomes protect ON. By

this operation, write operation to specified SFR is disabling.

If writing “1FH” to EMCCR1 register, it becomes protect OFF. Protect state can

be confirmed by reading EMCCR0<PROTECT>.

At reset, protection becomes OFF.

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3.4.6

Standby Controller

(1) HALT modes

When the HALT instruction is executed, the operating mode switches to IDLE2,

IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0>

register.

The subsequent actions performed in each mode are as follows:

a. IDLE2: Only the CPU halts.

The internal I/O is available to select operation during IDLE2 mode by setting

the following register.

Table 3.4.2 shows the register setting operation during IDLE2 mode.

Table 3.4.2 SFR Setting Operation during IDLE2 Mode

Internal I/O

SFR

TMRA01

TA01RUN<I2TA01>

TA23RUN<I2TA23>

TA45RUN<I2TA45>

TB0RUN<I2TB0>

SC0MOD1<I2S0>

SC1MOD1<I2S1>

SBI0BR0<I2SBI0>

ADMOD1<I2AD>

WDMOD<I2WDT>

TMRA23

TMRA45

TMRB0

SIO0

SIO1

SBI

AD converter

WDT

b. IDLE1: Only the oscillator and the Special timer for CLOCK continue to operate.

c. STOP: All internal circuits stop operating.

The operation of each of the different HALT modes is described in Table 3.4.3.

Table 3.4.3 I/O Operation during HALT Modes

HALT Mode

IDLE2

11

IDLE1

10

STOP

01

SYSCR2<HALTM1:0>

CPU

Stop

I/O port

Keep the state when the HALT instruction was

executed.

See Table 3.4.6,

Table 3.4.7.

TMRA, TMRB

SIO0, SIO1, SBI

AD converter

Available to select operation block

Stop

Block

WDT

Special timer for CLOCK

Interrupt controller

Operate enable

Operate

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(2) How to release the HALT mode

These halt states can be released by resetting or requesting an interrupt. The halt

release sources are determined by the combination of the states of the interrupt mask

register <IFF2:0> and the HALT modes. The details for releasing the halt status are

shown in Table 3.4.4.

•

Released by interrupt requesting

The HALT mode release method depends on the status of the enabled interrupt.

When the interrupt request level set before executing the HALT instruction

exceeds the value of the interrupt mask register, the interrupt is processed

depending on its status after the HALT mode is released, and the CPU status

executing the instruction that follows the HALT instruction. When the interrupt

request level set before executing the HALT instruction is less than the value of the

interrupt mask register, HALT mode release is not executed. (In non-maskable

interrupts, interrupt processing is processed after releasing the HALT mode

regardless of the value of the mask register.) However only for INT0 and INTRTC

interrupts, even if the interrupt request level set before executing the HALT

instruction is less than the value of the interrupt mask register, HALT mode

release is executed. In this case, the interrupt is processed, and the CPU starts

executing the instruction following the HALT instruction, but the interrupt

request flag is held at “1”.

Note: Usually, interrupts can release all halts status. However, the interrupts = (NMI,

INT0, INTRTC) which can release the HALT mode may not be able to do so if

they are input during the period CPU is shifting to the HALT mode (for about 5

clocks of f_FPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case).

(In this case, an interrupt request is kept on hold internally.)

If another interrupt is generated after it has shifted to HALT mode completely,

halt status can be released without difficulty. The priority of this interrupt is

compared with that of the interrupt kept on hold internally, and the interrupt with

higher priority is handled first followed by the other interrupt.

•

Release by resetting

Release of all halt statuses is executed by resetting.

When the STOP mode is released by RESET, it is necessary to allow enough

resetting time (See Table 3.4.5 ) for operation of the oscillator to stabilize.

When releasing the HALT mode by resetting, the internal RAM data keeps the

state before the “HALT” instruction is executed. However the other settings

contents are initialized. (Releasing due to interrupts keeps the state before the

“HALT” instruction is executed.)

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Table 3.4.4 Source of Halt State Clearance and Halt Clearance Operation

Interrupt Enable

(Interrupt level) ≥ (Interrupt mask)

Interrupt Disable

(Interrupt level) < (Interrupt mask)

Status of Received Interrupt

HALT Mode

IDLE2

IDLE1 STOP

IDLE2

IDLE1 STOP

*1

NMI

♦

×

−

○

×

−

○

×

−

○

INTWD

♦

×

*1

INT0 (Note1)

♦

×

INTRTC

♦

×

INT5 to INT6

♦ (Note 2)

×

INTTA0 to INTTA5

INTTB00, INTTB01, INTTBOF0

INTRX0 to INTRX1, INTTX0 to INTTX1

INTSBI

♦

×

INTAD

×

RESET

Initialize LSI

♦: After clearing the HALT mode, CPU starts interrupt processing.

○: After clearing the HALT mode, CPU resumes executing starting from the instruction following the HALT

instruction. (Interrupt routine don’t execute.)

×: Cannot be used to release the HALT mode.

−: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority

level. This combination is not available.

*1: Release of the HALT mode is executed after warm-up time has elapsed.

Note 1:When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled

status, hold high level until starting interrupt process. If low level was set before interrupt process is

stared, interrupt process is not started correctly.

Note 2:If using external interrupt INT5 to INT6 in IDLE2 mode, set 16-bit timer RUN register

TB0RUN<I2TB0> to “1”.

Example: Releaseing halt state

An INT0 interrupt clears the halt state when the device is in IDLE1 mode.

Address

8200H

8203H

8206H

8209H

820BH

820EH

LD

(P6FC), 08H

(IIMC), 00H

(INTE0AD), 06H

5

; Selects INT0 interrupt

LD

; Selects INT0 interrupt rising edge.

; Sets INT0 interrupt level to 6.

; Sets CPU interrupt level to 5.

; Sets HALT mode to IDLE1 mode.

; Halts CPU.

LD

EI

LD

(SYSCR2), 28H

HALT

INT0 interrupt routine

RETI

INT0

820FH

LD

XX, XX

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(3) Operation

a. IDLE2 mode

In IDLE2 mode only specific internal I/O operations, as designated by the

IDLE2 setting register, can take place. Instruction execution by the CPU stops.

Figure 3.4.5 illustrates an example of the timing for clearance of the IDLE2

mode halt state by an interrupt.

X1

A0 to A21

ALE

Address

Address + 2

Data

Address

AD0 to AD15

RD

Address

WR

Interrupt for

release halt

IDLE2

mode

Figure 3.4.5 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt

b. IDLE1 mode

In IDLE1 mode, only the internal oscillator and the Special timer for CLOCK

continue to operate. The system clock in the MCU stops.

In the halt state, the interrupt request is sampled asynchronously with the

system clock; however, clearance of the Halt state (e.g., restart of operation) is

synchronous with it.

Figure 3.4.6 illustrates the timing for clearance of the IDLE1 mode halt state by

an interrupt.

X1

A0 to A21

Address

Address + 2

ALE

Data

Address

Data

AD0 to AD15

RD

WR

Interrupt for

release halt

IDLE1

mode

Figure 3.4.6 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt

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c. STOP mode

When STOP mode is selected, all internal circuits stop, including the internal

oscillator. Pin status in STOP mode depends on the settings in the

SYSCR2<DRVE> register. Table 3.4.6 and Table 3.4.7 summarizes the state of

these pins in STOP mode.

After STOP mode has been cleared, system clock output starts when the

warm-up time has elapsed, in order to allow oscillation to stabilize. After STOP

mode has been cleared, either NORMAL mode or SLOW mode can be selected

using the SYSCR0<RSYSCK> register. Therefore, <RSYSCK>, <RXEN> and

<RXTEN> must be set. See the sample warm-up times in Table 3.4.5.

Figure 3.4.7 illustrates the timing for clearance of the STOP mode halt state by

an interrupt.

Warm-up time

X1

A0 to A21

Address

Address + 2

ALE

Data

Address

Data

AD0 to AD15

RD

WR

Interrupt for

release halt

STOP

mode

Figure 3.4.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt

Table 3.4.5 Sample Warm-up Times after Clearance of STOP Mode

@ f

= 27 MHz, fs = 32.768 kHz

OSCH

SYSCR2<WUPTM1:0>

10 (2¹⁴)

SYSCR0

01 (2⁸)

11 (2¹⁶)

0 (fc)

1 (fs)

9.0 μs

0.607 ms

500 ms

2.427 ms

2000 ms

7.8 ms

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Example:

•

The STOP mode is entered when the low-frequency operates, and

high-frequency operates after releasing due to NMI.

Address

SYSCR0

SYSCR1

SYSCR2

EQU

LD

00E0H

00E1H

00E2H

8FFDH

9000H

9002H

9005H

(SYSCR1), 08H

; f_SYS= fs/2

LD

(SYSCR2), X−1001X1B ; Sets warm-up time to 2¹⁴/fc

LD

(SYSCR0), −11000 − − B ; Operates high frequency after released.

HALT

Clears and starts warm-up timer

(High frequency)

NMI pin input

END

NMI Interrupt routine

9006H

LD

XX, XX

RETI

−: No change

Note: When different modes are used before and after STOP mode as the above mentioned, there is possible to

release the HALT mode without changing the operation mode by acceptance of the halt release interrupt

request during execution of “HALT” instruction (during 6 state). In the system which accepts the interrupts

during execution “HALT” instruction, set the same operation mode before and after the STOP mode.

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Table 3.4.6 Input Buffer State Table

Input Buffer State

When the CPU is

Operating

In HALT mode

(IDLE2/IDLE1)

In HALT mode（STOP）

<DRVE>=1

<DRVE>=0

Port

Name

Input Function

Name

During

Reset

When

Used as

Function

When

Used as

Function

Input Port

Used as

Function

Used as

Function

Used as

Input Port

Used as

Input Port

P00 to P07

P10 to P17

AD0 to AD7

ON upon

external

OFF

AD8 to AD15

OFF

read

ON

OFF

P20 to P25

P32

−

*1

−

P40 to P42

P50 to P52

P53

−

ON

*1

*2

OFF

ON upon

port read

OFF

ADTRG

ON

OFF

P60

SCK

SDA

SI

P61

ON

P62

SCL

INT0

TA0IN

−

P63

P70

P71

P72

P73

P74

ON

OFF

−

TA4IN

−

ON

OFF

−

TB0IN0

INT5

TB0IN1

INT6

−

P80

P81

ON

OFF

P82

P83

P90

P91

−

OFF

−

RXD0

SCLK0

CTS0

－

ON

−

OFF

P92

P93

P94

−

RXD1

SCLK1

CTS1

ON

P95

ON

OFF

For oscillator

XT1

OFF

ON

OFF

ON

OFF

ON

OFF

ON

P96

P97

OFF

For port

OFF

−

NMI

ON

OFF

RESET

ON

−

ON

−

AM0,AM1

X1

OFF

ON: The buffer is always turned on. A current flows

through the input buffer if the input pin is not

driven.

*1: Port having a pull-up/pull-down resistor.

OFF: The buffer is always turned off.

－: Not applicable

*2: AIN input does not cause a current to flow through the buffer.

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Table 3.4.7 Output buffer State Table

Output Buffer State

In HALT mode

(IDLE2/IDLE1)

When the CPU is

Operating

In HALT mode（STOP）

<DRVE>=1

<DRVE>=0

When When

Used as Used as

Port

Name

Output Function

Name

During

Reset

When

Used as

Function

When

Used as

Output

Port

When

Used as

Output

Port

When

Used as

Function

When Used

as Output

Port

Used as

Function

Output

Port

P00 to P07

P10 to P17

AD0 to AD7

ON upon

external

write

OFF

AD8 to AD15

OFF

ON

A8 to A15

A0 to A5

A16 to A21

RD

P20 to P25

P30

P31

P32

WR

OFF

*1

HWR

CS0

ON

P40 to P42

CS1

CS2

P60

P61

SCK

SDA

SO

P62

P63

P70

P71

P72

P73

P74

P80

P81

P82

P83

P90

P91

P92

P93

P94

P95

P96

SCL

ON

−

OFF

−

TA1OUT

TA3OUT

−

ON

OFF

−

TA5OUT

−

ON

OFF

−

TB0OUT0

TB0OUT1

TXD0

−

ON

OFF

−

SCLK0

TXD1

−

ON

OFF

−

ON

−

ON

−

ON

−

OFF

−

SCLK1

−

ON

OFF

ON

For oscillator

XT2

ON

OFF

ON

OFF

ON

OFF

ON

P97

OFF

ON

OFF

ON

For port

ALE

X2

−

OFF

ON

−

ON

−

ON: The buffer is always turned on.

OFF: The buffer is always turned off.

－:Not applicable

*1: Port having a pull-up/pull-down resistor.

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3.5 Interrupts

Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in

interrupt controller.

The TMP91CU27/CP27/CK27 have a total of 34 interrupts divided into the following three

types:

•

Interrupts generated by CPU: 9 sources

(Software interrupts, illegal instruction interrupt)

•

Internal interrupts: 21 sources

Interrupts on external pins ( NMI , INT0, INT5 and INT6): 4 sources

A (fixed) individual interrupt vector number is assigned to each interrupt.

One of six (Variable) priority level can be assigned to each maskable interrupt.

The priority level of non-maskable interrupts are fixed at 7 as the highest level.

When an interrupt is generated, the interrupt controller sends the priority of that interrupt

to the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends

the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for

non-maskable interrupts.)

The CPU compares the priority level of the interrupt with the value of the CPU interrupt

mask register <IFF2:0>. If the priority level of the interrupt is higher than the value of the

interrupt mask register, the CPU accepts the interrupt.

The interrupt mask register <IFF2:0> value can be updated using the value of the EI

instruction (“EI num” sets <IFF2:0> data to num).

For example, specifying “EI3” enables the maskable interrupts which priority level set in the

interrupt controller is 3 or higher, and also non-maskable interrupts.

Operationally, the DI instruction (<IFF2:0> = “7”) is identical to the “EI7” instruction. DI

instruction is used to disable maskable interrupts because of the priority level of maskable

interrupts is 0 to 6. The EI instruction is valid immediately after execution.

In addition to the above general-purpose interrupt processing mode, TLCS-900/L1 has a

micro DMA interrupt processing mode as well. The CPU can transfer the data (1/2/4 bytes)

automatically in micro DMA mode, therefore this mode is used for speed-up interrupt

processing, such as transferring data to the internal or external peripheral I/O. Moreover,

TMP91CU27/CP27/CK27 has software start function for micro DMA processing request by the

software not by the hardware interrupt.

Figure 3.5.1 shows the overall interrupt processing flow.

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Interrupt processing

Micro DMA soft start

request

Interrupt specified

by micro DMA

start vector?

Yes

Clear interrupt requenst flag

No

Data transfer by micro

DMA

Interrupt vector value “V” read

Interrupt request F/F clear

General-purpose

interrupt

processing

Count ← Count − 1

PUSH

PC

SR

Micro DMA processing

SR<IFF2:0> ←Level of

accepted

interrupt + 1

INTNEST ← INTNEST + 1

Clear vector register

generating micro DMA

trasfer and interrupt

(INTTC0 to INTTC3)

Yes

Count = 0

No

PC ← (FFFF00H + V)

Interrupt processing

program

RETI instruction

POP

SR

PC

INTNEST ←INTNEST − 1

End

Figure 3.5.1 Overall Interrupt Processing Flow

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3.5.1

General-Purpose Interrupt Processing

When the CPU accepts an interrupt, it usually performs the following sequence of

operations. That is also the same as TLCS-900/L and TLCS-900/H.

(1) The CPU reads the interrupt vector from the interrupt controller.

If the same level interrupts occur simultaneously, the interrupt controller generates an

interrupt vector in accordance with the default priority and clears the interrupt

request.

(The default priority is already fixed for each interrupt: The smaller vector value has

the higher priority level.)

(2) The CPU pushes the value of program counter (PC) and status register (SR) onto the

stack area (indicated by XSP).

(3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1)

to the interrupt mask register <IFF2:0>. However, if the priority level of the accepted

interrupt is 7, the register’s value is set to 7.

(4) The CPU increases the interrupt nesting counter INTNEST by 1 (+1).

(5) The CPU jumps to the address indicated by the data at address “FFFF00H + interrupt

vector” and starts the interrupt processing routine.

The above processing time is 18-states (1.33 μs at 27 MHz) as the best case (16 bits

data bus width and 0 waits).

When the CPU completed the interrupt processing, use the RETI instruction to return to

the main routine. RETI restores the contents of program counter (PC) and status register

(SR) from the stack and decreases the interrupt nesting counter INTNEST by 1(−1).

Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts,

however, can be enabled or disabled by a user program. A program can set the priority level

for each interrupt source.

If an interrupt request which has a priority level equal to or greater than the value of the

CPU interrupt mask register <IFF2:0> comes out, the CPU accepts its interrupt. Then, the

CPU interrupt mask register <IFF2:0> is set to the value of the priority level for the

accepted interrupt plus 1 (1).

Therefore, if an interrupt is generated with a higher level than the current interrupt

during its processing, the CPU accepts the later interrupt and goes to the nesting status of

interrupt processing.

Moreover, if the CPU receives another interrupt request while performing the said (1) to

(5) processing steps of the current interrupt, the latest interrupt request is sampled

immediately after execution of the first instruction of the current interrupt processing

routine. Specifying DI as the start instruction disables maskable interrupt nesting.

A reset initializes the interrupt mask register <IFF2:0> to “7”, disabling all maskable

interrupts.

Table 3.5.1 shows the TMP91CU27/CP27/CK27 interrupt vectors and micro DMA start

vectors. The address FFFF00H to FFFFFFH (256 bytes) is assigned for the interrupt vector

area.

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Table 3.5.1 TMP91CU27/CP27/CK27 Interrupt Vectors and Micro DMA Start Vectors

Vector

Reference DMA Start

Address

Micro

Default

Priority

Interrupt Source and Source of Micro DMA

Request

Vector

Value (V)

Type

Vector

1

“RESET” or SWI0 instruction

SWI1 instruction

0000H

0004H

0008H

000CH

0010H

0014H

0018H

001CH

0020H

0024H

−

FFFF00H

FFFF04H

FFFF08H

FFFF0CH

FFFF10H

FFFF14H

FFFF18H

FFFF1CH

FFFF20H

FFFF24H

−

2

3

INTUNDEF: Illegal Instruction or SWI2 instruction

SWI3 instruction

−

4

−

Non

5

SWI4 instruction

−

-maskable

6

SWI5 instruction

−

7

SWI6 instruction

−

8

SWI7 instruction

−

NMI pin

9

−

10

−

INTWD: Watchdog timer

(Micro DMA)

−

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

INT0 pin

0028H

−

FFFF28H

−

0AH

−

Reserved

−

Reserved

−

Reserved

−

INT5 pin

003CH

0040H

−

FFFF3CH

FFFF40H

−

0FH

10H

−

INT6 pin

Reserved

−

INTTA0: 8-bit timer 0

INTTA1: 8-bit timer 1

INTTA2: 8-bit timer 2

INTTA3: 8-bit timer 3

INTTA4: 8-bit timer 4

INTTA5: 8-bit timer 5

Reserved

004CH

0050H

0054H

0058H

005CH

0060H

−

FFFF4CH

FFFF50H

FFFF54H

FFFF58H

FFFF5CH

FFFF60H

−

13H

14H

15H

16H

17H

18H

−

Reserved

−

INTTB00: 16-bit timer 0 (TB0RG0)

INTTB01: 16-bit timer 0 (TB0RG1)

Reserved

006CH

0070H

−

FFFF6CH

FFFF70H

−

1BH

1CH

−

Maskable

Reserved

−

INTTBOF0: 16-bit timer 0 (Over flow)

Reserved

007CH

−

FFFF7CH

−

1FH

−

INTRX0: Serial reception (Channel 0)

INTTX0: Serial transmission (Channel 0)

INTRX1: Serial reception (Channel 1)

INTTX1: Serial transmission (Channel 1)

INTSBI: Serial bus interface interrupt

INTRTC: Special timer for clock

INTAD: AD conversion end

INTTC0: End of Micro DMA (Channel 0)

INTTC1: End of Micro DMA (Channel 1)

INTTC2: End of Micro DMA (Channel 2)

INTTC3: End of Micro DMA (Channel 3)

(Reserved)

0084H

0088H

008CH

0090H

0094H

0098H

009CH

00A0H

00A4H

00A8H

00ACH

00B0H

:

FFFF84H

FFFF88H

FFFF8CH

FFFF90H

FFFF94H

FFFF98H

FFFF9CH

FFFFA0H

FFFFA4H

FFFFA8H

FFFFACH

FFFFB0H

:

21H

22H

23H

24H

25H

26H

27H

−

:

(Reserved)

00FCH

FFFFFCH

−

Note: Micro DMA default priority: the micro DMA initiation takes priority over other Maskable interrupts.

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3.5.2

Micro DMA

In addition to general-purpose interrupt processing, the TMP91CU27/CP27/CK27

supports a micro DMA function. Interrupt requests set by micro DMA perform micro DMA

processing at the highest priority level among maskable interrupts, regardless of the

priority level of the particular interrupt source. The micro DMA has 4 channels and is

possible continuous transmission by specifying the say later burst mode.

Because the micro DMA function is implemented through the CPU, when the CPU is

placed in a standby mode by a HALT instruction, the requirements of the micro DMA will

be ignored (Pending).

(1) Micro DMA operation

When an interrupt request specified by the micro DMA start vector register is

generated, the micro DMA triggers a micro DMA request to the CPU at interrupt

priority highest level and starts processing the request in spite of any interrupt

source’s level. The micro DMA is ignored on <IFF2:0> = “7”.

The 4 micro DMA channels allow micro DMA processing to be set for up to 4 types of

interrupts at any one time. When micro DMA is accepted, the interrupt request

flip-flop assigned to that channel is cleared.

The data are automatically transferred once (1/2/4 bytes) from the transfer source

address to the transfer destination address set in the control register, and the transfer

counter is decreased by 1(−1).

If the decreased result is “0”, the micro DMA transfer end interrupt (INTTCn) passes

from the CPU to the interrupt controller. In addition, the micro DMA start vector

register DMAnV is cleared to 0, the next micro DMA is disabled and micro DMA

processing completes.

If the decreased result is other than “0”, the micro DMA processing completes if it

isn’t specified the say later burst mode. In this case, the micro DMA transfer end

interrupt (INTTCn) aren’t generated.

If an interrupt request is triggered for the interrupt source in use during the interval

between the clearing of the micro DMA start vector and the next setting,

general-purpose interrupt processing executes at the interrupt level set. Therefore, if

only using the interrupt for starting the micro DMA (Not using the interrupts as a

general-purpose interrupt: Level 1 to 6), first set the interrupts level to 0 (Interrupt

requests disabled).

If using the interrupt source to activate both micro DMA and general-purpose

interrupts, first set the level of the interrupt used to start micro DMA processing lower

than all the other interrupt levels. In this case, the cause of general interrupt is limited

to the edge interrupt. (Note)

Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows.

In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking “Interrupt

specified by micro DMA start vector” (in the Figure 3.5.1) and reading interrupt vector with setting below. The

vector shifts to that of INTyyy at the time.

This is because the priority level of INTyyy is higher than that of INTxxx.

In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And

INTyyy is generated regardless of transfer counter of micro DMA.

INTxxx: level 1 without micro DMA

INTyyy: level 6 with micro DMA

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The priority of the micro DMA transfer end interrupt is defined by the interrupt level

and the default priority as the same as the other maskable interrupt.

If a micro DMA request is set for more than one channel at the same time, the

priority is not based on the interrupt priority level but on the channel number. The

smaller channel number has the higher priority (Channel 0 (High) > channel 3 (Low)).

While the register for setting the transfer source/transfer destination addresses is a

32-bit control register, this register can only effectively output 24-bit addresses.

Accordingly, micro DMA can access 16 Mbytes (The upper eight bits of the 32 bits are

not valid).

Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte transfer, and

4-byte transfer. After a transfer in any mode, the transfer source/destination addresses

are increased, decreased, or remain unchanged.

This simplifies the transfer of data from I/O to memory, from memory to I/O, and

from I/O to I/O. For details of the transfer modes, see 3.5.2 (4) “Detailed description of

the transfer mode register: DMAM0 to DMAM3”.

As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to

65536 times per interrupt source. (The micro DMA processing count is maximized

when the transfer counter initial value is set to 0000H.)

Micro DMA processing can be started by the 30 interrupts shown in the micro DMA

start vectors of and by the micro DMA soft start, making a total of 31interrupts.

Figure 3.5.2 shows the word transfer micro DMA cycle in transfer destination

address INC mode (except for Counter mode, the same as for other modes).

(The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer

source/transfer destination addresses both even-numbered values).

1 state

(Note 1)

(Note 2)

DM1

DM2

DM3

DM4

DM5

DM6

DM7 DM8

X1

A0 to A23

RD

Source

Input

Destination

Output

WR / HWR

D0 to D5

Figure 3.5.2 Timing for Micro DMA Cycle (Word transfer)

States 1 to 3: Instruction fetch cycle (gets next address code).

If 3 bytes and more instruction codes are inserted in the instruction

queue buffer, this cycle becomes a dummy cycle.

States 4 to 5: Micro DMA read cycles

State 6:

Dummy cycle (The address bus remains unchanged from state 5)

States 7 to 8: Micro DMA write cycle

Note 1:If the source address area is an 8-bit bus, it is increased by two states.

If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two

states.

Note 2:If the destination address area is an 8-bit bus, it is increased by two states.

If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by

two states.

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(2) Soft start function

In addition to starting the micro DMA function by interrupts,

TMP91CU27/CP27/CK27 includes a micro DMA software start function that starts

micro DMA on the generation of the write cycle to the DMAR register.

Writing “1” to each bit of DMAR register causes micro DMA activate once. At the end

of transfer, the corresponding bit of the DMAR register is automatically cleared to “0”.

Only one-channel can be set once for micro DMA. (Do not write “1” to plural bits.)

When writing again “1” to the DMAR register, check whether the bit is “0” before

writing “1”. The read value “1” does not cause micro DMA transfer.

When a burst is specified by DMAB register, data is continuously transferred until

the value in the micro DMA transfer counter is 0 after start up of the micro DMA. If

execute soft start during micro DMA transfer by interrupt source, micro DMA

transfer counter doesn’t change. Don’t use Read-modify-write instruction to avoid

writing to other bits by mistake.

Symbol Name Address

7

6

5

4

3

2

1

0

DMAR3

DMAR2

DMAR1

DMAR0

DMA

89H

software

R/W

DMAR

(Prohibit

RMW)

request

register

0

DMA request

(3) Transfer control registers

The transfer source address and the transfer destination address are set in the

following registers in CPU. An instruction of the form “LDC cr,r” can be used to set

these registers.

Channel 0

DMAS0

DMAD0

DMA Source address register 0: Only use LSB 24 bits

DMA Destination address register 0: Only use LSB 24 bits

DMA Counter register 0: 1 to 65536

DMAC0

DMAM0 DMA Mode register 0

Channel 3

DMAS3

DMA Source address register 3

DMA Destination address register 3

DMA Counter register 3

DMAD3

DMAC3

DMAM3 DMA Mode register 3

8 bits

16 bits

32 bits

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(4) Detailed description of the transfer mode register: DMAM0 to DMAM3

(DMAM0 to DMAM3)

Note: The upper three bits of data programmed to

these registers must always be 0.

0

Mode

Execution time

ZZ: 0 = Byte transfer, 1 = Word transfer, 2 = 4-byte transfer, 3 = Reserved

Transfer destination address INC mode .....................I/O to memory

(DMADn+) ← (DMASn)

0

1

0

1

0

1

0

1

0

1

Z

0

8 states (593 ns)

@ byte/word transfer

12 states (889ns)

@4-byte transfer

8 states (593 ns)

@ byte/word transfer

12 states (889 ns)

@4-byte transfer

8 states (593 ns)

@ byte/word transfer

12 states (889 ns)

@4-byte transfer

8 states (593 ns)

@ byte/word transfer

12 states (889 ns)

@4-byte transfer

8 states (593 ns)

@ byte/word transfer

12 states (889 ns)

@4-byte transfer

5 states

DMACn ← DMACn − 1

if DMACn = 0 then INTTC is generated

Transfer destination address DEC mode....................I/O to memory

(DMADn−) ← (DMASn)

Z

0

DMACn ← DMACn − 1

if DMACn = 0 then INTTC is generated

Transfer source address INC mode............................Memory to I/O

(DMADn) ← (DMASn+)

DMACn ← DMACn − 1

if DMACn = 0 then INTTC is generated

Transfer source address DEC mode...........................Memory to I/O

(DMADn) ← (DMASn−)

DMACn ← DMACn − 1

if DMACn = 0 then INTTC is generated

Address fixed mode ............................................................ I/O to I/O

(DMADn) ← (DMASn)

DMACn ← DMACn − 1

if DMACn = 0 then INTTC is generated

Counter mode ···for counting number of times interrupt is generated

DMASn ← DMASn + 1

DMACn ← DMACn − 1

(370 ns)

if DMACn = 0 then INTTC is generated

Note 1:“n” is the corresponding micro DMA channels 0 to 3

DMADn+/DMASn+: Post increment (Increment register value after transfer)

DMADn−/DMASn−: Post decrement (Decrement register value after transfer)

The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC)

addresses.

Note 2:Execution time is under the condition of:

16-bit bus width/0 waits.

fc = 27MHz/selected high frequency mode (fc × 1)

Note 3:Do not use an undefined code for the transfer mode register except for the defined codes listed in the above

table.

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3.5.3

Interrupt Controller Operation

The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the

diagram shows the interrupt controller circuit. The right-hand side shows the CPU

interrupt request signal circuit and the halt release circuit.

For each of the 25 interrupt channels there is an interrupt request flag (Consisting of a

flip-flop), an interrupt priority setting register and a micro DMA start vector register. The

interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to

zero in the following cases:

•

When reset occurs

When the CPU reads the channel vector after accepted its interrupt

When executing an instruction that clears the interrupt (Program DMA start

vector to INTCLR register)

•

When the CPU receives a micro DMA request (When micro DMA is set.)

When the micro DMA burst transfer is terminated

An interrupt priority can be set independently for each interrupt source by writing the

priority to the interrupt priority setting register (e.g., INTE0AD or INTE56). 6 interrupt

priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7)

disables interrupt requests from that source. The priority of non-maskable interrupts

(NMI pin interrupts and watchdog timer interrupts) is fixed at 7. If interrupt request with

the same level are generated at the same time, the default priority (The interrupt with the

lowest priority or, in other words, the interrupt with the lowest vector value) is used to

determine which interrupt request is accepted first.

The 3rd and 7th bits of the interrupt priority setting register indicate the state of the

interrupt request flag and thus whether an interrupt request for a given channel has

occurred.

The interrupt controller sends the interrupt request with the highest priority among the

simultaneous interrupts and its vector address to the CPU. The CPU compares the priority

value <IFF2:0> in the status register by the interrupt request signal with the priority value

set; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than

the priority value by 1 (+1) in the CPU SR<IFF2:0>. Interrupt request where the priority

value equals or is higher than the set value are accepted simultaneously during the

previous interrupt routine.

When interrupt processing is completed (after execution of the RETI instruction), the

CPU restores the priority value saved in the stack before the interrupt was generated to

the CPU SR<IFF2:0>.

The interrupt controller also has registers (4 channels) used to store the micro DMA start

vector. Writing the start vector of the interrupt source for the micro DMA processing (See

Table 3.5.1), enables the corresponding interrupt to be processed by micro DMA processing.

The values must be set in the micro DMA parameter register (e.g., DMAS and DMAD) prior

to the micro DMA processing.

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Figure 3.5.3 Block Diagram of Interrupt Controller

91CU27-45

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TMP91CU27/CP27/CK27

(1) Interrupt level setting registers

Symbol

Name Address

7

6

5

4

3

2

1

0

INTAD

INT0

INT5

INT0 &

INTAD

enable

IADC

IADM2

IADM1

R/W

0

IADM0

I0C

R

I0M2

0

I0M1

R/W

0

I0M0

INTE0AD

90h

93h

95h

96h

97h

R

0

I6M2

0

INT6

INT5 &

INT6

enable

I6C

R

I6M1

R/W

0

I6M0

I5C

R

I5M2

0

I5M1

R/W

0

I5M0

INTE56

0

INTTA1 (TMRA1)

INTTA0 (TMRA0)

INTTA0 &

INTTA1

enable

ITA1C

ITA1M2

ITA1M1

R/W

0

ITA1M0

ITA0C

ITA0M2

ITA0M1

R/W

0

ITA0M0

INTETA01

INTETA23

INTETA45

R

0

R

0

ITA3M0

0

ITA2M0

0

INTTA3 (TMRA3)

INTTA2 (TMRA2)

INTTA2 &

INTTA3

enable

ITA3C

ITA3M2

ITA3M1

R/W

0

ITA2C

ITA2M2

ITA2M1

R/W

0

R

0

R

0

INTTA5 (TMRA5)

INTTA4 (TMRA4)

INTTA4 &

INTTA5

enable

ITA5C

ITA5M2

ITA5M1

R/W

0

ITA5M0

0

ITA4C

ITA4M2

ITA4M1

R/W

0

ITA4M0

0

R

0

R

0

Interrupt request flag

lxxM2

lxxM1

lxxM0

Function (Write)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Disable interrupt request

Setting interrupt priority level to “1”.

Setting interrupt priority level to “2”.

Setting interrupt priority level to “3”.

Setting interrupt priority level to “4”.

Setting interrupt priority level to “5”.

Setting interrupt priority level to “6”.

Disable interrupt request

2008-01-24

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Symbol

Name Address

7

6

5

4

3

2

1

0

INTTB01 (TMRB0)

INTTB00 (TMRB0)

INTTB00 &

INTTB01

enable

ITB01C

ITB01M2 ITB01M1 ITB01M0

R/W

ITB00C

ITB00M2 ITB00M1 ITB00M0

R/W

INTETB0

99H

9BH

9CH

9DH

9EH

A0H

A1H

R

0

R

0

−

0

−

INTTBOF0 (TMRB0 over flow)

INTTBOF0

(over-flow)

enable

−

R

0

−

R/W

0

−

ITF0C

ITF0M2

ITF0M1

R/W

0

ITF0M0

INTETB01V

INTES0

R

0

INTTX0

INTRX0

INTRX0 &

INTTX0

enable

ITX0C

ITX0M2

ITX0M1

R/W

0

ITX0M0

IRX0C

IRX0M2

IRX0M1

R/W

0

IRX0M0

R

0

R

0

ITX1M2

0

IRX1M2

0

INTTX1

INTRX1

INTRX1 &

INTTX1

enable

ITX1C

ITX1M1

R/W

0

ITX1M0

IRX1C

IRX1M1

R/W

0

IRX1M0

INTES1

R

0

R

0

INTRTC

INTSBI

INTSBI &

INTRTC

enable

IRTCC

IRTCM2

IRTCM1

R/W

0

IRTCM0

IS2C

R

IS2M2

IS2M1

R/W

0

IS2M0

INTES2RTC

INTETC01

INTETC23

R

0

ITC1M2

0

ITC0M2

0

INTTC1

INTTC0

INTTC0 &

INTTC1

enable

ITC1C

ITC1M1

R/W

0

ITC1M0

ITC0C

ITC0M1

R/W

0

ITC0M0

R

0

R

0

ITC3M0

0

ITC2M0

0

INTTC3

INTTC2

INTTC2 &

INTTC3

enable

ITC3C

ITC3M2

ITC3M1

R/W

0

ITC2C

ITC2M2

ITC2M1

R/W

0

R

0

R

0

Interrupt request flag

lxxM2

lxxM1

lxxM0

Function (Write)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Disable interrupt request

Setting interrupt priority level to “1”.

Setting interrupt priority level to “2”.

Setting interrupt priority level to “3”.

Setting interrupt priority level to “4”.

Setting interrupt priority level to “5”.

Setting interrupt priority level to “6”.

Disable interrupt request

2008-01-24

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TMP91CU27/CP27/CK27

(2) External interrupt control

Symbol Name Address

7

6

5

4

3

2

1

0

−

I0EDGE

I0LE

NMIREE

W

0

Interrupt

8CH

INT0

edge

INT0

mode

1: Operate

even on

rising/

input

IIMC

(Prohibit

RMW)

mode

control

0: Rising 0: Edge

1: Falling 1: Level

Always write “0”.

falling

edge of

NMI

INT0 level enable

0

1

edge detect interrupt

“H” level interrupt

NMI rising edge enable

0

1

Interrupt request generation at falling edge

Interrupt request generation at rising/falling

edge

(3) Interrupt request flag clear register

The interrupt request flag is cleared by writing the appropriate micro DMA start

vector, as given in Table 3.5.1, to the register INTCLR.

For example, to clear the interrupt flag INT0, perform the following register

operation after execution of the DI instruction.

INTCLR ← 0AH Clears interrupt request flag INT0

Symbol Name Address

7

6

5

4

3

2

1

0

CLRV5

CLRV4

CLRV3

CLRV2

CLRV1

CLRV0

Interrupt

88H

W

clear

INTCLR

(Prohibit

RMW)

0

control

Interrupt vector

(4) Micro DMA start vector registers

This register assigns micro DMA processing to which interrupt source. The interrupt

source with a micro DMA start vector that matches the vector set in this register is

assigned as the micro DMA start source.

When the micro DMA transfer counter value reaches zero, the micro DMA transfer

end interrupt corresponding to the channel is sent to the interrupt controller, the micro

DMA start vector register is cleared, and the micro DMA start source for the channel is

cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector

register again during the processing of the micro DMA transfer end interrupt.

If the same vector is set in the micro DMA start vector registers of more than one

Accordingly, if the same vector is set in the micro DMA start vector registers of two

channels, the interrupt generated in the channel with the lower number is executed

until micro DMA transfer is complete. If the micro DMA start vector for this channel is

not set again, the next micro DMA is started for the channel with the higher number.

(Micro DMA chaining)

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Symbol Name Address

7

6

5

4

3

2

1

0

DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0

R/W

DMA0

start

vector

DMA0V

DMA1V

DMA2V

DMA3V

80H

81H

82H

83H

0

DMA0 start vector

DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0

R/W

DMA1

start

vector

0

DMA1 start vector

DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0

R/W

DMA2

start

vector

0

DMA2 start vector

DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1 DMA3V0

R/W

DMA3

start

vector

0

DMA3 start vector

(5) Micro DMA burst specification

Specifying the micro DMA burst continues the micro DMA transfer until the transfer

counter register reaches zero after micro DMA start. Setting a bit which corresponds to

the micro DMA channel of the DMAB registers mentioned below to “1” specifies a

burst.

Symbol Name Address

7

6

5

4

3

2

1

0

DMAR3

DMAR2

DMAR1

DMAR0

DMA

89H

software

R/W

DMAR

(Prohibit

RMW)

request

register

0

1: DMA software request

DMAB3

0

DMAB2

DMAB1

DMAB0

0

DMA burst

request

register

R/W

DMAB

8AH

0

1: DMA request on Burst Mode

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(6) Attention point

The instruction execution unit and the bus interface unit of this CPU operate

independently. Therefore, immediately before an interrupt is generated, if the CPU

fetches an instruction that clears the corresponding interrupt request flag, the CPU

may execute the instruction that clears the interrupt request flag (*1) between

accepting and reading the interrupt vector. In this case, the CPU reads the default

vector 0008H and reads the interrupt vector address FFFF08H.

To avoid the above program, place instructions that clear interrupt request flags

after a DI instruction. And in the case of setting an interrupt enable again by EI

instruction after the execution of clearing instruction, execute EI instruction after

clearing and more than 1 instructions (Example: “NOP” × 1 times). If placed EI

instruction without waiting NOP instruction after execution of clearing instruction,

interrupt will be enable before request flag is cleared.

In the case of changing the value of the interrupt mask register <IFF2:0> by

execution of POP SR instruction, disable an interrupt by DI instruction before

execution of POP SR instruction.

In addition, take care as the following 2 circuits are exceptional and demand special

attention.

INT0 level mode

In level mode INT0 is not an edge-triggered interrupt. Hence, in level

mode the interrupt request flip-flop for INT0 does not function. The

peripheral interrupt request passes through the S input of the flip-flop

and becomes the Q output. If the interrupt input mode is changed from

edge mode to level mode, the interrupt request flag is cleared

automatically.

If the CPU enters the interrupt response sequence as a result of INT0

going from 0 to 1, INT0 must then be held at 1 until the interrupt

response sequence has been completed. If INT0 is set to level mode so

as to release a halt state, INT0 must be held at 1 when INT0 changes

from 0 to 1 until the halt state is released. (Hence, it is necessary to

ensure that input noise is not interpreted as a 0, causing INT0 to revert

to 0 before the halt state has been released.)

When the mode changes from level mode to edge mode, interrupt

request flags which were set in level mode will not be cleared. Interrupt

request flags must be cleared using the following sequence.

DI

LD (IIMC), 00H

; Switches interrupt input mode from level

mode to edge mode.

LD (INTCLR), 0AH ; Clears interrupt request flag

NOP

EI

; Wait EI instruction

INTRX

The interrupt request flip-flop can only be cleared by a reset or by

reading the serial channel receive buffer. It cannot be cleared by

INTCLR register write.

Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt

request flag.

INT0: Instructions which switch to Level Mode after an interrupt request has been generated in edge mode.

The pin input change from high to low after interrupt request has been generated

in Level Mode. (H → L)

INTRX: Instruction which read the receive buffer

2008-01-24

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TMP91CU27/CP27/CK27

3.6 Port Function

The TMP91CU27/CP27/CK27 I/O port pins are shown in Table 3.6.1. In addition to

functioning as general-purpose I/O ports, these pins are also used by the internal CPU and I/O

functions.

Table 3.6.2 to Table 3.6.3 lists the I/O registers and their specifications.

Table 3.6.1 Port Function

(R: PU = with pull-up resistor)

Number of

Pins

Direction

Setting Unit

Pin Names for Built-in

Functions

Port Names Pin Names

Direction

R

Port 0

Port 1

Port 2

Port 3

P00 to P07

P10 to P17

P20 to P25

P30

8

6

1

4

1

I/O

−

Bit

AD0 to AD7

AD8 to AD15/A8 to A15

I/O

−

Bit

A16 to A21/A0 to A5

RD

Output

I/O

−

(Fixed)

Bit

WR

P31

−

HWR

P32

PU

−

CS0

Port 4

P40

I/O

Bit

CS1

P41

I/O

Bit

CS2

P42

I/O

Bit

AN0 to AN3, ADTRG (P53)

Port 5

Port 6

P50 to P53

P60

Input

I/O

(Fixed)

Bit

−

SCK

P61

I/O

−

Bit

SO/SDA

SI/SCL

P62

I/O

−

Bit

P63

I/O

−

Bit

INT0

Port 7

P70

I/O

−

Bit

TA0IN

P71

I/O

−

Bit

TA1OUT

TA3OUT

TA4IN

P72

I/O

−

Bit

P73

I/O

−

Bit

P74

I/O

−

Bit

TA5OUT

TB0IN0/INT5

TB0IN1/INT6

TB0OUT0

TB0OUT1

Port 8

Port 9

P80

I/O

−

Bit

P81

I/O

−

Bit

P82

I/O

−

Bit

P83

I/O

−

Bit

P90

I/O

−

Bit

TXD0

P91

I/O

−

Bit

RXD0

SCLK0/ CTS0

P92

I/O

−

Bit

P93

I/O

−

Bit

TXD1

P94

I/O

−

Bit

RXD1

SCLK1/ CTS1

P95

I/O

−

Bit

P96

I/O

−

Bit

XT1

XT2

P97

I/O

−

Bit

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Table 3.6.2 I/O Port Setting List (1/2)

I/O Register Setting Values

Reset

State

Ports

Pin Names

Specifications

Pn

PnCR

PnFC

•

Port 0

P00 to P07

Input port

×

1

0

1

×

0

1

0

1

0

1

0

1

Register

setting:

None

Output port

AD0 to AD7 bus (Note 1)

Input port

•

Port 1

Port 2

Port 3

P10 to P17

P20 to P25

P30

0

1

0

1

0

1

Output port

AD8 to AD15 bus

A8 to A15

•

Input port

Output port

A0 to A5 output

A16 to A21 output

Output port

Register

setting:

None

RD output only when accessing

an external area

Always RD output

Output port

0

1

0

1

P31

P32

×

Register

setting:

None

WR output only when accessing

an external area

Input port (without pull up)

Input port (with pull up)

Output port

×

0

1

×

0

1

×

0

1

0

1

0

1

0

1

HWR output

Port 4

P40 to P42

Input port (without pull up)

Input port (with pull up)

Output port

CS0 output

P40

CS1 output

CS2 output

P41

P42

•

Port 5

Port 6

P50 to P53

Input port

Register setting:

None

AN0 to AN3 input

ADTRG input

P53

P60 to P63

Input port

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Output port

SCK input

P60

P61

SCK output

SDA input

SDA output (Note 2)

SO output

P62

P63

SI input

SCL input

SCL output (Note 2)

INT0 input

X: Don’t care

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Table 3.6.3 I/O Port Setting List (2/2)

I/O Register Setting Values

Reset

State

Ports

Pin Names

P70 to P74

P70

Specifications

Pn

PnCR

PnFC

•

Port 7

Input port

×

0

1

0

Output port

TA0IN input

0

Register

setting:

None

P71

P72

P73

TA1OUT output

TA3OUT output

TA4IN input

×

1

0

1

Register

setting:

None

P74

TA5OUT output

Input port

×

1

0

1

0

1

0

1

0

1

•

Port 8

P80 to P83

0

Output port

0

P80

TB0IN0, INT5 input

TB0IN1, INT6 input

TB0OUT0 output

TB0OUT1 output

Input port

1

P81

1

P82

1

P83

1

Port 9

P90 to P95

0

Output port

0

P90

P91

TXD0 output

1

Register

setting:

None

0

RXD0 input

P92

SCLK0 input

×

0

1

0

1

0

SCLK0 output

CTS0 input

1

0

P93

P94

TXD1 output

RXD1 input

1

Register

setting:

None

0

P95

SCLK1 input

SCLK1 output

CTS1 input

×

0

1

0

1

0

1

0

P96 to P97

Input port

Register

setting:

None

•

Output port (Note 3)

XT1 to XT2

X: Don’t care

Note 1:Switching among AD0 to AD7 are automatically executed at accessing external area. No port setting is

required.

Note 2:Set ODE<ODE62:61> when using P61 at SDA and P62 at SCL as open drain output.

Note 3: P96 to P97 are open-drain buffers if they are used as the output ports.

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3.6.1

Port 0 (P00 to P07)

Port 0 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or

output using the control register P0CR. Resetting, reset all bits of the control register

P0CR to “0” and sets port 0 to input mode.

In addition to functioning as a general-purpose I/O port, port 0 can also function as

address data bus (AD0 to AD7).

When access external memory, port 0 function as address data bus (AD0 to AD7) and

P0CR be cleared to “0”.

Reset

External access

Direction

control

(on bit basis)

External access(Data write)

P0CR write

A

S

Output latch

Port 0

P00 to P07

(AD0 to AD7)

Output buffer

P0 write

B

AD0 to AD7

P0 Read

External access (Data read)

Figure 3.6.1 Port 0

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Port 0 Register

4

7

6

5

3

2

1

0

P0

Bit symbol

Read/Write

Reset State

P07

P06

P05

P04

P03

P02

P01

P00

(0000H)

R/W

Data from external port (Output latch register is undefined.)

Port 0 Control Register

7

6

5

4

3

2

1

0

P0CR

Bit symbol

Read/Write

Reset State

Function

P07C

P06C

P05C

P04C

P03C

P02C

P01C

P00C

(0002H)

W

0

0: Input 1: Output

(When access to external, become AD7 to AD0 and this register is cleared to “0”.)

Port 0 I/O setting

0

1

Input

Output

Note: A read-modify-write operation cannot be performed in P0CR.

Figure 3.6.2 Register for Ports 0

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3.6.2

Port 1 (P10 to P17)

Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or

output using the control register P1CR and function register P1FC. Resetting reset all bits

of output latch P1, the control register P1CR and function register P1FC to “0” and sets

port 1 to input mode.

In addition to functioning as a general-purpose I/O port, port 1 can also function as

address data bus (AD8 to AD15) and address bus (A8 to A15).

Reset

Direction control

(on bit basis)

P1CR write

Function control

(on bit basis)

P1FC write

Output latch

P1 write

Port 1

P10 to P17

Output buffer

(AD8 to AD15/A8 to A15)

P1 read

Figure 3.6.3 Port 1

2008-01-24

91CU27-56

TMP91CU27/CP27/CK27

Port 1 Register

4

7

6

5

3

2

1

0

P1

Bit symbol

Read/Write

Reset State

P17

P16

P15

P14

P13

P12

P11

P10

(0001H)

R/W

Data from external port (Output latch register is cleared to “0”.)

Port 1 Control Register

7

6

5

4

3

2

1

0

P1CR

Bit symbol

Read/Write

Reset State

Function

P17C

P16C

P15C

P14C

P13C

P12C

P11C

P10C

(0004H)

W

0

<<Refer to column of P1FC>>

Port 1 Function Register

7

6

5

4

3

2

1

0

P1FC

Bit symbol

Read/Write

Reset State

Function

P17F

P16F

P15F

P14F

P13F

P12F

P11F

P10F

(0005H)

W

0

P1FC/P1CR = 00: Input, 01: Output, 10: AD15 to AD8, 11: A15 to A8

Port1 function setting

P1FC<P1XF>

0

1

P1CR<P1XC>

Address data bus

(AD15 to AD8)

Address bus

0

1

Input Port

Output Port

(A15 to A8)

Note: <P1XF>/<P1XC> is bit X of each register P1FC/P1CR.

Note: A read-modify-write operation cannot be performed in P1CR and P1FC.

Figure 3.6.4 Register for Port 1

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3.6.3

Port 2 (P20 to P25)

Port 2 is a 6-bit general-purpose I/O port. Each bit can be set individually for input or

output using the control register P2CR and function register P2FC. Resetting, set all bits of

output latch P2 to “1”, and reset the control register P2CR and function register P2FC to

“0” and sets port 2 to input mode.

In addition to functioning as a general-purpose I/O port, port 2 can also function as

address bus (A0 to A5) and address bus (A16 to A21).

B

A16 to A21

A

Y

A0 to A5

Reset

S

Direction control

(on bit basis)

P2CR write

Function

control

(on bit basis)

P2FC write

S

B

A

Y

Output latch

P2 write

Port 2

P20 to P25

(A0 to A5/A16 to A21)

Output buffer

P2 read

Figure 3.6.5 Port 2

2008-01-24

91CU27-58

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Port 2 Register

4

7

6

5

3

2

1

0

P2

Bit symbol

Read/Write

Reset State

P25

P24

P23

P22

P21

P20

(0006H)

R/W

Data from external port (Output latch register is set to “1”.)

Port 2 Control Register

5

4

3

2

1

0

P2CR

Bit symbol

Read/Write

Reset State

Function

P25C

P24C

P23C

P22C

P21C

P20C

(0008H)

W

0

<<Refer to column of P2FC>>

Port 2 Function Register

7

6

5

4

3

2

1

0

P2FC

Bit symbol

Read/Write

Reset State

Function

P25F

P24F

P23F

P22F

P21F

P20F

(0009H)

W

0

P2FC/P2CR = 00: Input, 01: Output, 10: A5 to A0, 11: A21 to A16

Port 2 function setting

P2FC<P2XF>

0

1

P2CR<P2XC>

Address bus

(A5 to A0)

0

1

Input Port

Address bus

(A21 to A16)

Output Port

Note: <P2XF>/<P2XC> is bit X of each register P2FC/P2CR.

When setting the address buses A21 to A16, set P2FC

first and then set P2CR. Otherwise, addresses A5 to A0

are output until P2CR is set provided P2CR is “0”.

Note: A read-modify-write operation cannot be performed in P2CR and P2FC.

Figure 3.6.6 Register for Port 2

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3.6.4

Port 3 (P30 to P32)

Port 3 is a 3-bit general-purpose I/O port (however P30 and P31 is only output port). Each

bit can be set individually for input or output using the control register P3CR and function

register P3FC. Resetting, all bits of output latch P3 is set to “1”, and the control register

P3CR (Bit0 and bit1 don’t using) and function register P3FC are reset to “0”. And P30 and

P31 of port 3 output “High”, and sets P32 to input mode with pull-up resistor.

In addition to functioning as a general-purpose I/O port, port 3 can also function as the

output for the CPU’s control/status signal.

Case of P30 is defined as RD signal output mode (Case of <P30F> = “1”), when the output

latch register <P30> clearing to “0”, outputs the RD strobe (used for the pseudo static

RAM) of the RD pin even when the internal addressed.

If the <P30 > remains “1”, the RD strobe signal is output only when the external address

area is accessed.

Reset

Direction control

(on bit basis)

P3FC write

S

A

Output latch

P30 ( RD )

Output buffer

B

P3 write

RD

Internal address area

P3 read

Figure 3.6.7 Port 3 (P30)

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Reset

Function control

(on bit basis)

P3FC write

S

A

B

P31( WR )

Output latch

Output buffer

P3 write

WR

Internal address area

P3 read

Reset

Direction control

(on bit basis)

P3CR write

Function control

(on bit basis)

Programmable

pull up

P3FC write

P-ch

S

A

B

P32( HWR )

Output latch

Output buffer

P3 write

HWR

P3 read

Figure 3.6.8 Port 3 (P31 and P32)

2008-01-24

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Port 3 Register

4

7

6

5

3

2

1

0

P3

Bit symbol

Read/Write

Reset State

P32

P31

R/W

1

P30

(0007H)

Data from

external

1

port Note3

0(output

latch

Function

register):

Pull-up

resistor

OFF

1(output

latch

register):

Pull-up

resistor ON

Port 3 Control Register

7

6

5

4

3

2

1

0

P3CR

Bit symbol

Read/Write

Reset State

P32C

W

(000AH)

0

0: Input

1: Output

Input/ Output setting

0

1

Input

Output

Port 3 Function Register

7

6

5

4

3

2

1

0

P3FC

Bit symbol

Read/Write

Reset State

Function

−

W

P32F

P31F

W

P30F

(000BH)

0

0: Port

1: RD

Always

write “0”.

0: Port

1: HWR

0: Port

1: WR

Note 1: A read-modify-write operation cannot be performed in

P3CR and P3FC.

P30 ( RD ) function setting

<P30>

0

1

<P30F>

Note 2: When port 3 is used in Input mode, the P3 register

controls the internal pull-up resistor. Read-modify-write

instruction is prohibited in Input mode or I/O mode.

Setting the internal pull-up resistor may be depend on

the states of the input pin.

“0” output

“1” output

0

RD output

always.

(Correspond external

to pseudo

SRAM)

RD is only

output during

1

accesses.

P31 ( WR ) function setting

Note 3: Output latch register is set to “1”.

<P31>

<P31F>

0

1

“0” output

“1” output

0

WR is only output during

external accesses.

1

P32 ( HWR ) function setting

<P32C>

<P32F>

0

1

0

Input port

Output port

HWR output

1

−

Figure 3.6.9 Register for Port 3

91CU27-62

2008-01-24

TMP91CU27/CP27/CK27

3.6.5

Port 4 (P40 to P42)

Port 4 is a 3-bit general-purpose I/O port. Each bit can be set individually for input or

output using the control register P4CR and function register P4FC. Resetting, set P40 to

P42 of output register to “1”, the control register P4CR and function register P4FC are reset

to “0” and P40 to P42 are set to input mode with pull-up resistor.

In addition to functioning as a general-purpose I/O port, port 4 can also function as chip

select output signal (CS0 to CS2).

Reset

Direction

control

(on bit basis)

P4CR write

Function

control

(on bit basis)

Programmable

P-ch

P4FC write

pull up

S

A

B

Output latch

P40 ( CS0 ),

P41 ( CS1 ),

P42 ( CS2 )

Output buffer

P4 write

CS0 , CS1 , CS2

P4 read

Figure 3.6.10 Port4

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Port 4 Register

4

7

6

5

3

2

1

0

P4

Bit symbol

Read/Write

Reset State

P42

P41

R/W

P40

(000CH)

Data from external port

(output latch register is set to “1”.)

0(output latch register)

Function

: Pull-up resistor OFF

1(output latch register)

: Pull-up resistor ON

Port 4 Control Register

7

6

5

4

3

2

1

0

P4CR

Bit symbol

Read/Write

Reset State

P42C

P41C

W

P40C

(000EH)

0

0: Input

1: Output

Input/Output setting

0

1

Input

Output

Port 4 Function Register

7

6

5

4

3

2

1

0

P4FC

Bit symbol

Read/Write

Reset State

Function

P42F

P41F

W

P40F

(000FH)

0

0: Port 1: CS

0

1

Port (P40)

CS0

0

1

Port (P41)

CS1

0

1

Port (P42)

CS2

Note 1:A read-modify-write operation cannot be performed in P4CR and P4FC.

Note 2:When port 4 is used in Input mode, the P4 register controls the internal pull-up resistor. Read-modify-write

instruction is prohibited in Input mode or I/O mode. Setting the internal pull-up resistor may be depend on the

states of the input pin.

Note 3:When output chip select signal ( CS0 to CS2 ), set bit of control register (P4CR) to “1” after set bit of function

register (P4FC) to “1”. Otherwise, the value in P4 is output until P4FC is set.

Figure 3.6.11 Register for Port 4

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3.6.6

Port 5 (P50 to P53)

Port 5 is a 4-bit input port and can also be used as the analog input pin for the AD

converter. P53 can also be used as AD trigger input pin for AD converter.

Port 5

P50 (AN0)

P51 (AN1)

P52 (AN2)

Port 5 read

P53 (AN3, ADTRG )

Convertion

result

AD

Channel

selector

converter

register

AD read

ADTRG

(only P53)

Figure 3.6.12 Port 5

Port 5 Register

7

6

5

4

3

2

1

0

P5

(000DH)

Bit symbol

Read/Write

Reset State

P53

P52

P51

P50

R

Data from external port

Note: The input channel selection of AD converter and the permission of AD trigger input of P53 set by AD converter

mode register ADMOD1.

Figure 3.6.13 Register for Port 5

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3.6.7

Port 6 (P60 to P63)

Port 60 to P63 are 4-bit general-purpose I/O ports. It is changed to an input port by

resetting. All bits of output latch register P6 are set to “1”.

In addition to functioning as an I/O port, port 6 can also function as input or output

function of serial bus interface. This function enables each function by writing “1” to

applicable bit of Port 6 function register P6FC.

At reset, P6CR and P6FC are reset to “0” and all the bits are changed to the input ports.

(1) Port 60 (SCK)

In addition to functioning as an I/O port, port 60 can also function as clock SCK I/O

port in SIO mode of serial bus interface.

Reset

Direction

control

(on bit basis)

P6CR write

Function

control

(on bit basis)

P6FC write

S

A

Output latch

P6 write

Selector

B

P60 (SCK)

SCK output

S

B

Selector

A

P6 read

SCK input

Figure 3.6.14 Port 60

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(2) Port 61 (SO/SDA)

In addition to functioning as an I/O port, port 61 can also function as data SDA I/O

port in I²C mode or data SO output pin in SIO mode of serial bus interface.

Reset

Direction

control

(on bit basis)

P6CR write

Function

control

(on bit basis)

P6FC write

S

Output latch

P6 write

S

A

Selector

P61 (SO/SDA)

Open-drain

possible:

SO output

B

SDA output

ODE<ODE61>

S

B

Selector

A

P6 read

SDA input

Figure 3.6.15 Port 61

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(3) Port 62 (SI/SCL)

In addition to functioning as an I/O port, port 62 can also function as data SI

receiving pin in SIO mode or clock SCL I/O pin in I²C bus mode of serial bus interface.

Reset

Direction

control

(on bit basis)

P6CR write

Function

control

(on bit basis)

P6FC write

S

Output latch

P6 write

S

A

Selector

P62 (SI/SCL)

Open-drain

possible:

SCL output

B

ODE<ODE62>

S

B

Selector

P6 read

A

SI input

SCL input

Figure 3.6.16 Port 62

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(4) Port 63 (INT0)

In addition to functioning as an I/O port, port 63 can also function as INT0 input pin

of external interrupt.

Reset

Direction

control

(on bit basis)

P6CR write

Function

control

(on bit basis)

P6FC write

S

Output latch

P63 (INT0)

P6 write

S

B

Selector

A

P6 read

Select level/edge

&

INT0

Select rising/falling

IIMC<I0LE, I0EDGE>

Figure 3.6.17 Port 63

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91CU27-69

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Port 6 Register

4

7

6

5

3

2

1

0

P6

(0012H)

Bit symbol

Read/Write

Reset State

P63

P62

P61

P60

R/W

Data from external port

(Output latch register is set to “1”)

Port 6 Control Register

5

4

3

2

1

0

P6CR

Bit symbol

Read/Write

Reset State

Function

P63C

P62C

P61C

P60C

(0014H)

W

0

0: Input

1: Output

Port6 I/O setting

0

1

Input

Output

Port 6 Function Register

7

6

5

4

3

2

1

0

P6FC

Bit symbol

Read/Write

Reset State

Function

P63F

W

P62F

W

P61F

W

P60F

W

(0015H)

0

0: Port

1: SCL

output

0: Port

1: SDA/SO 1: SCK

output output

0: Port

1: INT0

input

P60 SCK output setting

P6FC<P60F>

1

P6CR<P60C>

P61 SDA/SO output setting

P6FC<P61F>

P6CR<P61C>

1

P62 SCL output setting

P6FC<P62F>

1

P6CR<P62C>

P63 INT0 input setting

P6FC<P63F>

1

0

P6CR<P63C>

Note: A read-modify-write operation cannot be performed in P6CR and P6FC.

Figure 3.6.18 Register for Port 6

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Open Drain Output Setting Register

7

6

5

4

3

2

1

0

ODE

bit Symbol

Read/Write

Reset State

Function

ODE62

ODE61

ODE93

ODE90

(002FH)

R/W

0

0: Tri-state 0: Tri-state 0: Tri-state 0: Tri-state

1: Open

drain

1: Open

drain

1: Open

drain

1: Open

drain

P61 output setting

0

1

Tri-state

Open drain

P62 output setting

0

1

Tri-state

Open drain

Figure 3.6.19 Register for Port 6

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3.6.8

Port 7 (P70 to P74)

Port 7 is a 5-bit general-purpose I/O port. It is changed to an input port by resetting.

In addition to functioning as a I/O port, port 70 and 73 can also function as clock input

pin TA0IN, TA4IN of 8-bit timer 0, 4 and port 71, 72 and 74 can also function 8-bit timer

output pin TA1OUT, TA3OUT and TA5OUT. This timer output function enables each

function by writing “1” to applicable bit of Port 7 function register P7FC.

At reset, P7CR and P7FC are reset to “0” and all the bits are changed to the input ports.

Reset

Direction

control

(on bit basis)

P7CR write

S

P70 (TA0IN)

P73 (TA4IN)

Output latch

S

B

P7 write

P7 read

Selector

A

TA0IN

TA4IN

Reset

Direction

control

(on bit basis)

P7CR write

Function

control

(on bit basis)

P7FC write

S

Output latch

A

S

P7 write

Selector

P71 (TA1OUT)

P72 (TA3OUT)

P74 (TA5OUT)

Timer F/F OUT

B

TA1OUT: TMRA01

TA3OUT: TMRA23

TA5OUT: TMRA45

B

Selector

P7 read

A

S

Figure 3.6.20 Port 7

2008-01-24

91CU27-72

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Port 7 Register

7

6

5

4

3

2

1

0

P7

Bit symbol

Read/Write

Reset State

P74

P73

P72

R/W

P71

P70

(0013H)

Data from external port

(Output latch register is set to “1”.)

Port 7 Control Register

5

4

3

2

1

0

P7CR

Bit symbol

Read/Write

Reset State

Function

P74C

P73C

P72C

W

P71C

P70C

(0016H)

0

0: Input

1: Output

Port 7 I/O setting

0

1

Input

Output

Port 7 Function Register

7

6

5

4

3

2

1

0

P7FC

Bit symbol

Read/Write

Reset State

Function

P74F

W

P72F

P71F

(0017H)

W

0

0: Port

1: TA5OUT

0: Port

1: TA3OUT 1: TA1OUT

P71 timer out 1 output setting

P7FC<P71F>

1

P7CR<P71C>

P72 timer out 3 output setting

P7FC<P72F>

1

P7CR<P72C>

P74 timer out 5 output setting

P7FC<P74F>

1

P7CR<P74C>

Note 1:A read-modify-write operation cannot be performed in P7CR and P7FC.

Note 2:P70/TA0IN and P73/TA4IN pin does not have a register changing Port/Function.

For example, when it is used as an input port, the input signal is inputted to 8-bit timer.

Figure 3.6.21 Register for Port 7

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3.6.9

Port 8 (P80 to P83)

Port 8 is a 4-bit general-purpose I/O port. It is changed to an input port by resetting. All

the bits of output latch register P8 are set to “1”.

In addition to functioning as a I/O port, port 8 can also function as clock input of 16-bit

timer, output of 16-bit timer F/F and input function of INT5 to INT6. This function enables

each function by writing “1” to applicable bit of port 8 function register P8FC.

At reset, P8CR and P8FC are reset to “0” and all the bits are changed to the input ports.

(1) P80 to P83

Reset

Direction

control

(on bit basis)

P8CR write

Function

control

(on bit basis)

P8FC write

S

P80

(TB0IN0/INT5)

Output latch

P81

S B

P8 write

(TB0IN1/INT6)

Selector

A

P8 read

Reset

TB0IN0, INT5

TB0IN1, INT6

Direction

control

(on bit basis)

P8CR write

Function

control

(on bit basis)

P8FC write

S

A

S

Output latch

P82

(TB0OUT0)

Selector

B

P8 write

Timer F/F OUT

P83

(TB0OUT1)

TB0OUT0: TMRB0

TB0OUT1: TMRB0

B

Selector

P8 read

S

A

Figure 3.6.22 Port 8 (P80 to P83)

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TMP91CU27/CP27/CK27

Port 8 Register

4

7

6

5

3

2

1

0

P8

Bit symbol

Read/Write

Reset State

P83

P82

P81

P80

(0018H)

R/W

Data from external port

(Output latch register is set to “1”.)

Port 8 Control Register

5

4

3

2

1

0

P8CR

Bit symbol

Read/Write

Reset State

P83C

P82C

P81C

P80C

(001AH)

W

0

0: Input

1: Output

Port 8 I/O setting

0

1

Input

Output

Port 8 Function Register

7

6

5

4

3

2

1

0

P8FC

Bit symbol

Read/Write

Reset State

Function

P83F

W

P82F

W

P81F

W

P80F

(001BH)

W

0

0: Port

1: TB0OUT1 1: TB0OUT0 1: TB0IN1

INT6 input

1: TB0IN0

INT5 input

P82 TB0OUT0 output setting

P8FC<P82F>

1

P8CR<P82C>

P83 TB0OUT1 output setting

P8FC<P83F>

1

P8CR<P83C>

1

Note: A read-modify-write operation cannot be performed in P8CR and P8FC.

Figure 3.6.23 Register for Port 8

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3.6.10 Port 9 (P90 to P97)

• Ports 90 to 95

Ports 90 to 95 are a 6-bit general-purpose I/O port. It is changed to an input port by

resetting. All the bits of output latch register are set to “1”.

In addition to functioning as a I/O port, port 90 to 95 can also function as I/O of SIO0,

SIO1. This function enables each function by writing “1” to applicable bit of port 9

function register P9FC.

At reset, P9CR and P9FC are reset to “0” and all the bits are changed to the input

ports.

•

Ports 96 to 97

Ports 96 to 97 are a 2-bit general-purpose I/O port. When they function as an output

port, open drain output is selected. At reset, output latch register and control register

are set to “1” and “High-Z” (High impedance) are set.

In addition to functioning as a I/O port, ports 96 to 97 can also function as the

low-frequency oscilator connection pins (XT1 and XT2) during using low speed clock

function. Therefore, dual clock function can use by setting of system clock control

registers SYSCR0 and SYSCR1.

(1) Ports 90 and 93 (TXD0 and TXD1)

In addition to functioning as an I/O port, Ports 90 and 93 can also function as TXD

output pin of serial channel.

And P90 and P93 have a programmable open-drain function which can be controlled

by the ODE<ODE90, 93> register.

Reset

Direction

control

(on bit basis)

P9CR write

Function

control

(on bit basis)

P9FC write

S

A

S

Output latch

Selector

P90 (TXD0)

P93 (TXD1)

P9 write

B

TXD0, TXD1

Open-drain

possible

S

B

ODE<ODE90, 93>

Selector

P9 read

A

Figure 3.6.24 Ports 90 and 93

2008-01-24

91CU27-76

TMP91CU27/CP27/CK27

(2) Ports 91 and 94 (RXD0 and RXD1)

In addition to functioning as an I/O port, ports 91 and 94 can also function as the

RXD input pin of serial channel.

Reset

Direction

control

(on bit basis)

P9CR write

S

P91 (RXD0)

Output latch

P94 (RXD1)

S

B

P9 write

P9 read

Selector

A

RXD0, RXD1

Figure 3.6.25 Ports 91 and 94

(3) Ports 92 and 95 (CTS0 /SCLK0, CTS1/SCLK1)

In addition to functioning as an I/O port, ports 92 and 95 can also function as the

CTS input pin or SCLK I/O pin of serial channel.

Reset

Direction

control

(on bit basis)

P9CR write

Function

control

(on bit basis)

P9FC write

S

A

S

Output latch

P92 (SCLK0/ CTS0 )

P95 (SCLK1/ CTS1 )

Selector

P9 write

B

SCLK0, 1

output

S B

Selector

A

P9 read

CTS0 , CTS1

SCLK0, SCLK1 input

Figure 3.6.26 Port 92, 95

2008-01-24

91CU27-77

TMP91CU27/CP27/CK27

(4) Ports 96 (XT1) and 97 (XT2)

In addition to functioning as an I/O port, ports 96 and 97 can also function as low

frequency oscillator connection pins.

Reset

S

Low-frequency oscillation enable

Direction

control

(on bit basis)

P9CR write

S

Output latch

P96 (XT1)

Output buffer

(Open-drain

output)

P9 write

S

B

Selector

Y

A

P9 read

(ON at 1)

S

Direction

control

(on bit basis)

P9CR write

S

Output latch

P97 (XT2)

Output buffer

(Open-drain

output)

P9 write

S

Low-frequency clock

B

Selector

Y

A

P9 read

Figure 3.6.27 Ports 96 and 97

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91CU27-78

TMP91CU27/CP27/CK27

Port 9 Register

4

7

6

5

3

2

1

0

P9

Bit symbol

Read/Write

Reset State

P97

P96

P95

P94

P93

P92

P91

P90

(0019H)

R/W

Data from external port

(Output latch register is set to “1”.)

1

Port 9 Control Register

7

6

5

4

3

2

1

0

P9CR

Bit symbol

Read/Write

Reset State

Function

P97C

P96C

P95C

P94C

P93C

P92C

P91C

P90C

(001CH)

W

1

0

0: Input

1: Output

Port9 I/O setting

0

1

Input

Output

Port 9 Function Register

7

6

5

4

3

2

1

0

P9FC

Bit symbol

Read/Write

Reset State

Function

P95F

W

P93F

W

P92F

W

P90F

W

(001DH)

0

0: Port

1: TXD1

0: Port

1: TXD0

1: SCLK1

output

1: SCLK0

output

P90 TXD0 output setting

P9FC<P90F>

1

P9CR<P90C>

P92 SCLK0 output setting

P9FC<P92F>

1

P9CR<P92C>

P93 TXD1 output setting

P9FC<P93F>

1

P9CR<P93C>

P95 SCLK1 output setting

P9FC<P95F>

1

P9CR<P95C>

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Open Drain Output Setting Register

7

6

5

4

3

2

1

0

ODE

(002FH)

bit Symbol

Read/Write

Reset State

Function

ODE62

ODE61

ODE93

ODE90

R/W

0

0: Tri-state 0: Tri-state 0: Tri-state 0: Tri-state

1: Open

drain

1: Open

drain

1: Open

drain

1: Open

drain

P90 output setting

0

1

Tri-state

Open drain

P93 output setting

0

1

Tri-state

Open drain

Note 1:Ports 96 and 97 are open-drain output pins

Note 2:A read-modify-write operation cannot be performed in P9CR and P9FC.

Note 3:When setting TXD pin to open-drain output, write “1” to bit0 of ODE register (for TXD0 pin), or bit1 (for TXD1

pin). P91/RXD0 and P94/RXD1 pin do not have a register changing Port/Function.

For example, when it is also used as an input port, the input signal is inputt to SIO as serial receiving data.

Note 4:Low frequency oscillation circuit

To connect a low frequency resonator to ports 96 and 97, it is necessary to set a following procedure to reduce

the consumption power supply.

(Case of resonator connection)

P9CR<P96C, P97C> = “11”, P9<P96:97> = “00”

(Case of oscillator connection)

P9CR<P96C, P97C> = “11”, P9<P96:97> = “10”

Figure 3.6.28 Register for Port 9

2008-01-24

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TMP91CU27/CP27/CK27

3.7 Chip select/Wait Controller

On the TM91CU27/CP27/CK27, four user-specifiable address spaces (CS0 to CS3) can be set.

The data bus width and the number of waits can be set independently for each address spaces

(CS0 to CS3 and others).

The pins CS0 to CS2 (which can also function as port pins P40 to P42) are the respective

output pins for the CS0 to CS2 spaces. When the CPU specifies an address in one of these

spaces, the corresponding CS0 to CS2 pin outputs the chip select signal for the specified address

space (in ROM or SRAM). However, in order for the chip select signal to be output, the port 4

control register P4CR and function register P4FC must be set.

The CS0 to CS3 spaces are defined by the values in the memory start address registers

MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3.

The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the

master enable status, the data bus width and the number of waits for each address space.

Since the TM91CU27/CP27/CK27 are not equipped with CS3 pin, CS signal that should be

generated in CS3 space is not automatically generated. Generating CS signal is required (e.g.

by decoding the address by the external circuit). Other functions (setting the bus width and

WAIT value) are available.

3.7.1

Specifying an Address spaces

The CS0 to CS3 address spaces are specified using the start address registers (MSAR0 to

MSAR3) and memory address mask registers (MAMR0 to MAMR3).

At each bus cycle, a compare operation is performed to determine if the address on the

specified a location in the CS0 to CS3 spaces. If the result of the comparison is a match, this

indicates an access to the corresponding CS space. In this case, the CS0 toCS2 pin outputs

the chip select signal and the bus cycle operates in accordance with the settings in chip

select/wait control register B0CS to B3CS. (See section 3.7.2, “Chip Select/Wait Control

Registers”.)

2008-01-24

91CU27-81

TMP91CU27/CP27/CK27

(1) Memory Start Address registers

Figure 3.7.1 shows the Memory Start Address registers. The MSAR0 to MSAR3

specify the start addresses for the CS0 to CS3 spaces. The bits <S23:S16> specify the

upper 8 bits (A23 to A16) of the start address. The lower 16 bits of the start address

(A15 to A0) are assumed to be “0”. Accordingly, the start address can only be a multiple

of 64-Kbytes ranging from 000000H. Figure 3.7.2 shows the relationship between the

start addresses and the Memory Start Address register values.

Memory Start Address Register (CS0 to CS3 spaces)

7

6

5

4

3

2

1

0

MSAR0

MSAR1 Bit symbol

Read/Write

MSAR3 Reset State

S23

S22

S21

S20

S19

S18

S17

S16

(00C8H) (00CAH)

R/W

MSAR2

1

(00CCH) (00CEH)

Function

Determines A23 to A16 of the start address

Specifies start addresses for CS0 to CS3

spaces

Figure 3.7.1 Memory Start Address Register

Start address

Start address register value (MSAR0 to MSAR3)

Address

000000H

000000H ...................... 00H

010000H ...................... 01H

020000H ...................... 02H

030000H ...................... 03H

040000H ...................... 04H

050000H ...................... 05H

060000H ...................... 06H

64 Kbytes

:

FF0000H ...................... FFH

FFFFFFH

Figure 3.7.2 Relationship Between Start Addresses and the Memory Start Address Register Values

2008-01-24

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TMP91CU27/CP27/CK27

(2) Memory Address Mask Registers

Figure 3.7.3 shows the Memory Address Mask registers. MAMR0 to MAMR3 are

used to determine the sizes of the CS0 to CS3 spaces by setting particular bits in

MAMR0 to MAMR3 to mask the corresponding start address bits. The address

compare logic uses only the address bits that are not masked (i.e., mask bit cleared to

“0”) to detect an address match in the CS0 to CS3 spaces.

Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0

to CS3 spaces. Accordingly, the block size that can be assigned to each space is also

different.

Memory Address Mask Register (CS0 space)

7

6

5

4

3

2

1

0

MAMR0

(00C9H)

Bit symbol

Read/Write

Reset State

Function

V20

V19

V18

V17

V16

V15

V14 to 9

V8

R/W

1

CS0 block size. 0: The address compare logic uses this address bit

The CS0 block size can vary from 256 bytes to 2 Mbytes

Memory Address Mask Register (CS1 space)

7

6

5

4

3

2

1

0

MAMR1

(00CBH)

Bit symbol

Read/Write

Reset State

Function

V21

V20

V19

V18

V17

V16

V15 to 9

V8

R/W

1

CS1 block size. 0: The address compare logic uses this address bit

The CS1 block size can vary from 256 bytes to 4 Mbytes.

Memory Address Mask Register (CS2 and CS3 spaces)

7

6

5

4

3

2

1

0

MAMR2 MAMR3 Bit symbol

V22

V21

V20

V19

V18

V17

V16

V15

(00CDH) (00CFH)

Read/Write

Reset State

Function

R/W

1

CS2 or CS3 block size. 0: The address compare logic uses this address bit

The CS2 and CS3 block sizes can vary from 32 Kbytes to 8 Mbytes.

Figure 3.7.3 Memory Address Mask Register

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(3) Setting the start address and address ranges

An example of specifying a 64-Kbyte address spaces starting from 010000H for the

CS0 space:

Set “01H” in the MSAR0<S23:S16> bit that corresponds to the upper 8 bits of the

start address. Then, calculate the difference between the start address and the

anticipated end address (01FFFFH) based on the size of the CS0 space. Bits 20 to 8 of

the calculation result correspond to the mask value to be set for the CS0 space. Setting

this value in the MAMR0<V20:V8> bits specifies the block size. This example sets

“07H” in MAMR0 to allocate a 64-Kbyte address space for the CS0 space.

0

1

Memory

end

address

H

CS0 block

size

(64 Kbytes)

0

1

F

0

F

0

F

0

F

0

Memory

start

address

S23 S22 S21 S20 S19 S18 S17 S16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSAR0

MAMR0

0

1

V20 V19 V18 V17 V16 V15

V14 to V9

V8

1

0

1

7

1

Memory address

mask register

setting

0

H

Setting of 07H specifies a 64-Kbyte space.

Figure 3.7.4 Example Showing How to Set the CS0 space

After a reset, MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to “FFH”.

B0CS<B0E>, B1CS<B1E> and B3CS<B3E> are reset to “0”. Therefore this is disabling

the CS0, CS1 and CS3 spaces. However, set as B2CS<B2M> to “0” and B2CS<B2E> to

“1”, CS2 is enabled from 003800H to FE7FFFH in TMP91CU27, from 002000H to

FF3FFFH in TMP91CP27 and from 001400H to FF9FFFH in TMP91CK27. Also, the

bus width and number of waits specified in BEXCS are used for accessing addresses

outside the specified CS0 to CS3 spaces. (See section 3.7.2, “Chip Select/Wait Control

Registers”.)

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TMP91CU27/CP27/CK27

(4) Programming block sizes

Table 3.7.1 shows the relationship between CS spaces and their sizes. The “Δ” symbol

indicates the size that might not be programmable depending on the combination of

the values of the Memory Start Address and Memory Address Mask registers. When

specifying a block size indicated as “Δ”, set the start address register to a multiple of

the desired block size starting from 000000H.

If the 16 Mbytes range is defined as CS2 space or if two or more spaces overlap, the

setting for the CS space with the smallest number overrides the setting for other

spaces because of its highest priority.

Example: Defining 128 Kbytes area as the CS0 space:

a. Valid start addresses

000000H

020000H

040000H

060000H

128 Kbytes

The desired block size can be programmed with

this configuration.

b. Invalid start addresses

000000H

010000H

030000H

050000H

64 Kbytes

128 Kbytes

This start address is not a multiple of the desired

block size. Hence, the desired block size cannot

be programmed with this configuration.

Table 3.7.1 Valid Block Sizes for Each CS Space

Size

(Byte) 256

512

32 K 64 K 128 K 256 K 512 K 1 M

2 M

4 M

8 M

CS space

CS0

○

Δ

CS1

Δ

○

CS2

Δ

CS3

Note: The “Δ” symbol indicates the sizes that may not be programmable depending on the combination of the values

of the Memory Start Address and Memory Start Address mask register combinations.

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3.7.2

Chip Select/Wait Control Registers

Figure 3.7.5 lists the chip select/wait control registers.

The master enable/disable, chip select output waveform, data bus width and number of

wait states for each address area (CS0 to CS3 and others) are set in their respective chip

select/wait control registers, B0CS to B3CS and BEXCS.

2008-01-24

91CU27-86

TMP91CU27/CP27/CK27

Chip Select/Wait Control Register

7

6

5

4

3

2

1

0

B0CS

Bit symbol

Read/Write

Reset State

Function

B0E

W

B0OM1

B0OM0

B0BUS

B0W2

B0W1

B0W0

(00C0H)

W

0

0: Disable

1: Enable

Chip select output

waveform selection

00: For ROM/SRAM

01: Don’t care

Data bus

width

0: 16 bits

1: 8 bits

Number of waits

000: 2 waits

001: 1 wait

100: Reserved

101: 3 waits

010: (1 + N) waits 110: 4 waits

10: Don’t care

11: Don’t care

011: 0 waits

111: 8 waits

B1W1 B1W0

B1CS

Bit symbol

Read/Write

Reset State

Function

B1E

W

B1OM1

B1OM0

0

B1BUS

B1W2

(00C1H)

W

0

0: Disable

1: Enable

Chip select output

waveform selection

00: For ROM/SRAM

01: Don’t care

Data bus

width

0: 16 bits

1: 8 bits

Number of waits

000: 2 waits

001: 1 wait

100: Reserved

101: 3 waits

010: (1 + N) waits 110: 4 waits

10: Don’t care

011: 0 waits

111: 8 waits

11: Don’t care

B2CS

Bit symbol

Read/Write

Reset State

Function

B2E

1

B2M

0

B2OM1

B2OM0

0

B2BUS

B2W2

B2W1

B2W0

0

(00C2H)

W

0

0: Disable CS2 area Chip select output

1: Enable selection

Data bus

width

0: 16 bits

1: 8 bits

Number of waits

000: 2 waits

001: 1 wait

010: (1 + N) waits 110: 4 waits

011: 0 waits

waveform selection

00: For ROM/SRAM

01: Don’t care

10: Don’t care

11: Don’t care

100: Reserved

101: 3 waits

0:16-

Mbyte

area

111: 8 waits

1: CS area

B3CS

Bit symbol

Read/Write

Reset State

Function

B3E

W

B3OM1

B3OM0

0

B3BUS

B3W2

B3W1

0

B3W0

(00C3H)

W

0

0: Disable

1: Enable

Chip select output

waveform selection

00: For ROM/SRAM

01: Don’t care

Data bus

width

0: 16 bits

1: 8 bits

Number of waits

000: 2 waits

001: 1 wait

100: Reserved

101: 3 waits

010: (1 + N) waits 110: 4 waits

10: Don’t care

11: Don’t care

011: 0 waits

111: 8 waits

BEXW1 BEXW0

BEXCS

Bit symbol

Read/Write

Reset State

Function

BEXBUS

BEXW2

(00C7H)

W

0

Data bus

width

0: 16 bits

1: 8 bits

Number of Waits

000: 2 waits

001: 1 wait

010: (1 + N) waits 110: 4 waits

011: 0 waits 111: 8 waits

100: Reserved

101: 3 waits

Master enable bit

Number of address space waits

(See section 3.7.2, “(3) Wait Control.”)

0

1

Disable CS area

Enable CS area

Chip select output waveform

selection

00 For ROM/SRAM

Data bus width selection

CS2 area selection

0

1

16-bit data bus

8-bit data bus

01 Don’t care

10 Don’t care

11 Don’t care

0

1

16-Mbyte area

Specified address area

Note1: A read-modify-write operation cannot be performed in B0CS, B1CS, B2CS, B3CS and BEXCS.

Note2:TMP91CU27/CP27/CK27 are not equipped with WAIT pin. 1 WAIT is automatically selected when

BxCS<BxW2:0>="010"(1+N)WAIT is set.

Note3: TMP91CU27/CP27/CK27 are not equipped with CS3 pin (P43). WAIT control is enabled when MSAR3 and

MAMR3 are set and B3CS<B3E>="1".

Figure 3.7.5 Chip Select/Wait Control Register

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TMP91CU27/CP27/CK27

(1) Master enable bits

Bit7 (<B0E>, <B1E>, <B2E> or <B3E>) of a chip select/wait control register is the

master bit that is used to enable or disable settings for the corresponding address

space. Writing “1” to this bit enables the settings. Reset disables (Sets to “0”) <B0E>,

<B1E> and <B3E>, and enables (sets to “1”) <B2E>. This enables space CS2 only.

(2) Data bus width specification

Bit3 (<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS> or <BEXBUS>) of a chip

select/wait control register specifies the width of the data bus. This bit should be set to

“0” when memory is to be accessed using a 16-bit data bus and to “1” when an 8-bit data

bus is to be used.

This process of changing the data bus width according to the address being accessed

is known as “dynamic bus sizing”. For details of this bus operation see Table 3.7.2.

Table 3.7.2 Dynamic Bus Sizing

CPU Data

Operand Data Operand Start Memory Data

CPU Address

Bus Width

Address

Bus Width

D15 to D8

D7 to D0

8 bits

2n + 0

8 bits

16 bits

8 bits

2n + 0

2n + 1

2n + 0

2n + 1

2n + 0

2n + 1

2n + 2

2n + 1

2n + 2

2n + 0

2n + 1

2n + 2

2n + 3

2n + 0

2n + 2

2n + 1

2n + 2

2n + 3

2n + 4

2n + 1

2n + 2

2n + 4

xxxxx

b7 to b0

xxxxx

(Even number)

2n + 1

xxxxx

(Odd number)

16 bits

8 bits

b7 to b0

xxxxx

16 bits

2n + 0

b7 to b0

b15 to b8

b7 to b0

b15 to b8

xxxxx

(Even number)

xxxxx

16 bits

8 bits

b15 to b8

xxxxx

2n + 1

(Odd number)

xxxxx

16 bits

8 bits

b7 to b0

xxxxx

b15 to b8

b7 to b0

b15 to b8

b23 to b16

b31 to b24

b7 to b0

b23 to b16

b7 to b0

b15 to b8

b23 to b16

b31 to b24

xxxxx

32 bits

2n + 0

xxxxx

(Even number)

xxxxx

16 bits

8 bits

b15 to b8

b31 to b24

xxxxx

2n + 1

(Odd number)

xxxxx

16 bits

b7 to b0

b23 to b16

xxxxx

b15 to b8

b31 to b24

“xxxxx”: The input data placed on the data bus indicated by this symbol is ignored during a read operation. During a

write operation, the bus is in the high–impedance state, and the write strobe signal remains inactive.

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(3) Wait control

Bits 0 to 2 (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2>, <BEXW0:2>) of a chip

select/wait control register specify the number of waits that are to be inserted when the

corresponding memory area is accessed.

The following types of wait operation can be specified using these bits. Bit settings

other than those listed in the table should not be made. These bits are set to “000” (2

waits) by resetting.

Table 3.7.3 Wait Operation Setting

Number of

<BxW2:0>

Wait Operation

Waits

000

001

010

011

100

101

110

111

2

Inserts a wait of 2 states.

Inserts a wait of 1 state.

1

Same operation with 1 wait because of nothing WAIT pin.

Ends the bus cycle without a wait.

Invalid setting

(1 + N)

0

Reserved

3

4

8

Inserts a wait of 3 states.

Inserts a wait of 4 states.

Inserts a wait of 8 states.

(4) Bus width and wait control for an area other than CS0 to CS3

The chip select/wait control register BEXCS controls the bus width and number of

waits when memory locations that are not in one of the four user-specified address

spaces (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for

areas other than CS0 to CS3.

(5) Selecting 16-Mbyte area/specified address area

Setting B2CS<B2M> (Bit6 of the chip select/wait control register for CS2) to “0”

designates the 16-Mbyte areas (from 003800H to FE7FFFH in TMP91CU27, from

002000H to FF3FFFH in TMP91CP27 and from 001400H to FF9FFFH in

TMP91CK27) as the CS2 space. Setting B2CS<B2M> to “1” designates the address

area specified by the start address register MSAR2 and the address mask register

MAMR2 as CS2 (e.g., if B2CS<B2M> = 1, CS2 is specified in the same manner as CS0,

CS1 and CS3 are).

A Reset clears this bit to “0”, specifying CS2 as a 16-Mbytes address area.

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(6) Procedure for setting chip select/wait control

When using the chip select/wait control function, set the registers in the following

order:

a. Set the Memory Start Address Registers MSAR0 to MSAR3.

Set the start addresses for CS0 to CS3.

b. Set the Memory Address Mask Registers MAMR0 to MAMR3.

Set the sizes of CS0 to CS3.

c. Set the chip select/wait control registers B0CS to B3CS.

Set the chip select output waveform, data bus width, number of waits and master

enable/disable status for CS0 to CS3 spaces.

The CS0 to CS2 pins can also function as pins P40 to P42. To output a chip select

signal using one of these pins, set the corresponding bit in the port 4 function register

P4FC and port 4 control register P4CR to “1”.

If a CS0 to CS3 address is specified which is actually an internal I/O, RAM and ROM

area address, the CPU accesses the internal address area and no chip select signal is

output on any of the CS0 to CS2 pins.

Example:

In this example CS0 is set to be the 64-Kbyte space 010000H to 01FFFFH. The

bus width is set to 16 bits and the number of waits is cleared to “0”.

MSAR0 = 01H

MAMR0 = 07H

B0CS = 83H

Start address: 010000H

Address space: 64 Kbytes

ROM/SRAM, 16-bit data bus, zero waits, CS0 space

settings enabled

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3.7.3

Connecting External Memory

Figure 3.7.6 shows an example of how to connect external memory to the

TMP91CU27/CP27/CK27.

In this example the ROM is connected using a 16-bit bus. The RAM and I/O are

connected using an 8-bit bus.

TMP91CU27

74AC573

TMP91CP27

TMP91CK27

D Q

LE

Address data bus

CS0

CS

OE

CS

Upper byte

ROM

Lower byte

ROM

8-bit

I/O

CS1

CS2

ALE

RAM

D Q

LE

OE

OE WE

AD8

:

AD15

AD0

:

AD7

RD

WR

Figure 3.7.6 Example of External Memory Connection

(ROM uses 16-bit bus, RAM and I/O uses 8-bit bus)

A reset clears all bits of the port 4 control register P4CR and the port 4 function register

P4FC to “0” and disables output of the CS signal in TMP91CU27/CP27/CK27. To output the

CS signal, the appropriate bit must be set P4CR to “1” after set P4FC to “1”.

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3.8 8-Bit Timers (TMRA)

The TMP91CU27/CP27/CK27 feature 6 channels (TMRA0 to TMRA5) built-in 8-bit timers.

These timers are paired into 3 modules: TMRA01, TMRA23 and TMRA45. Each module

consists of 2 channels and can operate in any of the following 4 operating modes.

•

8-bit interval timer mode

16-bit interval timer mode

8-bit programmable square wave pulse generation output mode (PPG: Variable duty

cycle with variable period)

•

8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant

period)

Figure 3.8.1 to Figure 3.8.3 show block diagrams for TMRA01, TMRA23 and TMRA45.

Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register.

In addition, a timer flip-flop and a prescaler are provided for each pair of channels.

The operation mode and timer flip-flops are controlled by a 5-byte registers (SFR: Special

function registers).

Each of the three modules (TMRA01, TMRA23 and TMRA45) can be operated independently.

All modules operate in the same manner except for the differences shown in Table 3.8.1; hence

only the operation of TMRA01 is explained here.

Table 3.8.1 Registers and Pins for Each Module

Module

TMRA01

TMRA23

TMRA45

Specification

Input pin for external

TA0IN

TA4IN

None

External

pins

clock

(Shared with P70)

TA1OUT

(Shared with P73)

TA5OUT

Output pin for timer

flip-flop

TA3OUT

(Shared with P71)

(Shared with P72)

(Shared with P74)

Timer RUN register

TA01RUN (0100H) TA23RUN (0108H) TA45RUN (0110H)

TA0REG (0102H)

TA1REG (0103H)

TA2REG (010AH)

TA3REG (010BH)

TA4REG (0112H)

TA5REG (0113H)

SFR

name

Timer register

Timer mode register

Timer flop-flop control

register

TA01MOD (0104H) TA23MOD (010CH) TA45MOD (0114H)

(Address)

TA1FFCR (0105H) TA3FFCR (010DH) TA5FFCR (0115H)

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3.8.1

Block Diagram

Figure 3.8.1 Block Diagram of TMRA01

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Figure 3.8.2 Block Diagram of TMRA23

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Figure 3.8.3 Block Diagram of TMRA45

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3.8.2

Operation of Each Circuit

(1) Prescalers

A 9-bit prescaler generates the input clock to TMRA01.

The prescaler clock (φT0) is a divided clock (divided by 4) from selected clock by the

register SYSCR0<PRCK1:0> of clock gear.

The prescaler operation can be controlled using TA01RUN<TA01PRUN> in the

timer control register. Setting <TA01PRUN> to “1” starts the count; setting

<TA01PRUN> to “0” clears the prescaler to zero and stops operation. Table 3.8.2 shows

the various prescaler output clock resolutions.

Table 3.8.2 Prescaler Output Clock Resolution

Prescaler Clock

Selection

Clock Gear

Value

Timer Counter Input Clock

TMRA Prescaler

System Clock

Selection

−

SYSCR0

SYSCR1

<GEAR2:0>

TAxxMOD<TAxCLK1:0>

φT4(1/8) φT16(1/32) φT256(1/512)

<SYSCK>

<PRCK1:0>

φT1(1/2)

1 (fs)

−

fs/8

fc/8

fs/32

fc/32

fc/64

fs/128

fc/128

fc/256

fs/2048

fc/2048

fc/4096

000(1/1)

001(1/2)

fc/16

00

(f

)

010(1/4)

fc/32

fc/128

fc/512

fc/8192

FPH

1/4

0 (fc)

011(1/8)

fc/64

fc/256

fc/512

fc/1024

fc/2048

fc/16384

fc/32768

100(1/16)

fc/128

10

−

fc/128

fc/512

fc/2048

fc/32768

(fc/16 clocks )

(2) Up counters (UC0 and UC1)

These are 8-bit binary counters which count up the input clock pulses for the clock

specified by TA01MOD.

The input clock for UC0 is selectable and can be either the external clock input via

the TA0IN pin or one of the three internal clocks φT1, φT4, and φT16. The clock setting

is specified by the value set in TA01MOD<TA0CLK1:0>.

The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the

overflow output from UC0 is used as the input clock. In any mode other than 16-bit

timer mode, the input clock is selectable and can either be one of the internal clocks

φT1, φT16, and φT256, or the comparator output (The match detection signal) from

TMRA0 by setting TA01MOD<TA1CLK1:0>.

For each interval timer the timer operation control register bits

TA01RUN<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the up

counters and to control their count. A reset clears both up counters, stopping the

timers.

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(3) Timer registers (TA0REG and TA1REG)

These are 8-bit registers that can be used to set a time interval. When the value set

in the timer register TA0REG or TA1REG matches the value in the corresponding up

counter, the comparator match detect signal goes Active. If the value set in the timer

register is 00H, the signal goes Active when the up counter overflows.

TA0REG has a double buffer structure, making a pair with the register buffer.

The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s double

buffer structure is enabled or disabled. It is disabled if <TA0RDE> = “0” and enabled if

<TA0RDE> = “1”.

When the double buffer is enabled, data is transferred from the register buffer to the

timer register when a 2ⁿoverflow occurs in PWM mode, or at the start of the PPG cycle

in PPG mode. Hence the double buffer cannot be used in timer mode.

A Reset initializes <TA0RDE> to “0”, disabling the double buffer. To use the double

buffer, write data to the timer register, set <TA0RDE> to “1”, and write the following

data to the register buffer. Figure 3.8.4 shows the configuration of TA0REG.

Timer registers 0 (TA0REG)

B

Matching detection in PPG cycle

2ⁿoverflow of PWM

Y

Selector

S

Shift trigger

Register buffers 0

Write

Write to TA0REG

A

TA01RUN<TA0RDE>

Internal data bus

Figure 3.8.4 Configuration of Timer Register 0 (TA0REG)

Note: The same memory address is allocated to the timer register and the register buffer when write data to

TA0REG. When <TA0RDE> = “0”, the same value is written to the register buffer and the timer register; when

<TA0RDE> = “1”, only the register buffer is written to.

The address of each timer register is as follows.

TA0REG: 000102H TA1REG: 000103H

TA2REG: 00010AH TA3REG: 00010BH

TA4REG: 000112H TA5REG: 000113H

All these registers are write only and cannot be read.

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(4) Comparator (CP0 and CP1)

The comparator compares the value in an up counter with the value set in a timer

register. If they match, the up counter is cleared to “0” and an interrupt signal

(INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer

flip-flop is inverted at the same time.

(5) Timer flip-flop (TA1FF)

The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signals (8-bit

comparator output) of each interval timer.

Whether inversion is enabled or disabled is determined by the setting of the bit

TA1FFCR<TA1FFIE> in the Timer Flip-Flop Control Register.

A reset clears the value of TA1FF to “0”.

Programming “01” or “10” to TA1FFCR<TA1FFC1:0> sets TA1FF to “1” or “0”.

Programming “00” to these bits inverts the value of TA1FF (This is known as software

inversion).

The TA1FF signal is output via the TA1OUT pin (Concurrent with P71). When this

pin is used as the timer output, the timer flip-flop should be set beforehand using the

Port 7 relation registers P7CR and P7FC.

Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required as explained

below.

If new data is written to the register buffer immediately before an overflow occurs by a match between the

timer register value and the up-counter value, the timer flip-flop may output an unexpected value.

For this reason, make sure that in PWM mode new data is written to the register buffer by six cycles (f

before the next overflow occurs by using an overflow interrupt.

× 6)

SYS

In the case of using PPG mode, make sure that new data is written to the register buffer by six cycles before

the next cycle compare match occurs by using a cycle compare match interrupt.

Example when using PWM mode

Match between

TA0REG and up-counter

2ⁿoverflow interrupt

(INTTA0)

TA1OUT

t

PWM

(PWM cycle)

Desired PWM cycle

change point

Write new data to the register buffer

before the next overflow occurs by

using an overflow interrupt

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3.8.3

SFR

TMRA01 Run Register

7

6

5

4

3

2

1

0

TA01RUN Bit symbol

TA0RDE

R/W

I2TA01 TA01PRUN TA1RUN

R/W

TA0RUN

(0100H)

Read/Write

Reset State

Function

0

Double

buffer

IDLE2

TMRA01

Up-counter Up-counter

0: Stop

1: Operate

prescaler (UC1)

0: Stop and clear

1: Run (Count up)

(UC0)

0: Disable

1: Enable

TA0REG double buffer control

Timer run/stop control

0

1

Disable

Enable

0

1

Stop and clear

Run (Count up)

Note: 4, 5 and 6 of TA01RUN are read as undefined values.

TMRA23 Run Register

7

6

5

4

3

2

1

0

TA23RUN Bit symbol

TA2RDE

R/W

I2TA23 TA23PRUN TA3RUN

R/W

TA2RUN

(0108H)

Read/Write

Reset State

Function

0

Double

buffer

IDLE2

TMRA23

Up-counter Up-counter

0: Stop

1: Operate

prescaler (UC3)

0: Stop and clear

1: Run (Count up)

(UC2)

0: Disable

1: Enable

TA2REG double buffer control

Timer run/stop control

0

1

Disable

Enable

0

1

Stop and clear

Run (Count up)

Note: 4, 5 and 6 of TA23RUN are read as undefined values.

Figure 3.8.5 Register for TMRA

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TMRA45 Run Register

7

6

5

4

3

2

1

0

TA45RUN Bit symbol

TA4RDE

R/W

I2TA45 TA45PRUN TA5RUN

R/W

TA4RUN

(0110H)

Read/Write

Reset State

Function

0

Double

buffer

IDLE2

TMRA23

Up-counter Up-counter

0: Stop

1: Operate

prescaler (UC5)

0: Stop and clear

1: Run (Count up)

(UC4)

0: Disable

1: Enable

TA4REG double buffer control

Count operate

0

1

Disable

Enable

0

1

Stop and clear

Run (Count up)

Note: 4, 5 and 6 of TA45RUN are read as undefined values.

Figure 3.8.6 Register for TMRA

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TMRA01 Mode Register

7

6

5

4

3

2

1

0

TA01MOD Bit symbol

TA01M1

TA01M0

PWM01

PWM00

TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0

R/W

(0104H)

Read/Write

Reset State

Function

0

Source clock for TMRA1

00: TA0TRG

01: φT1

Source clock for TMRA0

00: TA0IN pin

01: φT1

Operation mode

PWM cycle

00: Reserved

01: 2⁶

10: 2⁷

11: 2⁸

00: 8-bit timer mode

01: 16-bit timer mode

10: 8-bit PPG mode

11: 8-bit PWM mode

10: φT16

10: φT4

11: φT256

11: φT16

TMRA0 source clock selection

00

01

10

11

TA0IN

φT1

φT4

φT16

TMRA1 source clock selection

TA01MOD

<TA01M1:0> ≠ 01

<TA01M1:0> = 01

Overflow output from

TMRA0

Comparator

output from TMRA0

φT1

00

(16-bit timer mode)

01

10

11

φT16

φT256

PWM cycle selection

00

01

10

11

Reserved

2⁶× Source clock

2⁷× Source clock

2⁸× Source clock

TMRA01 operation mode selection

00

01

10

11

Two 8-bit timers

16-bit timer

8-bit PPG

8-bit PWM (TMRA0) + 8-bit timer (TMRA1)

Figure 3.8.7 Register for TMRA

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TMRA23 Mode Register

7

6

5

4

3

2

1

0

TA23MOD Bit symbol

TA23M1

TA23M0

PWM21

PWM20

TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0

R/W

(010CH)

Read/Write

Reset State

Function

0

Source clock for TMRA3

00: TA2TRG

01: φT1

Source clock for TMRA2

00: Reserved

01: φT1

Operation mode

PWM cycle

00: Reserved

01: 2⁶

10: 2⁷

11: 2⁸

00: 8-bit timer mode

01: 16-bit timer mode

10: 8-bit PPG mode

11: 8-bit PWM mode

10: φT16

10: φT4

11: φT256

11: φT16

TMRA2 source clock selection

00

01

10

11

Reserved

φT1 (Prescaler)

φT4 (Prescaler)

φT16 (Prescaler)

TMRA3 source clock selection

TA23MOD

<TA23M1:0> ≠ 01

<TA23M1:0> = 01

00

Comparator output

from TMRA2

φT1

Overflow output from

TMRA2

(16-bit timer mode)

01

10

11

φT16

φT256

PWM cycle selection

00

01

10

11

Reserved

2⁶× Source clock

2⁷× Source clock

2⁸× Source clock

TMRA23 operation mode selection

00

01

10

11

Two 8-bit timers

16-bit timer

8-bit PPG

8-bit PWM (TMRA2) + 8-bit timer (TMRA3)

Figure 3.8.8 Register for TMRA

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TMRA45 Mode Register

7

6

5

4

3

2

1

0

TA45MOD Bit symbol

TA45M1

TA45M0

PWM41

PWM40

TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0

R/W

(0114H)

Read/Write

Reset State

Function

0

Source clock for TMRA5

00: TA4TRG

01: φT1

Source clock for TMRA4

00: TA4IN pin

01: φT1

Operation mode

PWM cycle

00: Reserved

01: 2⁶

10: 2⁷

11: 2⁸

00: 8-bit timer mode

01: 16-bit timer mode

10: 8-bit PPG mode

11: 8-bit PWM mode

10: φT16

10: φT4

11: φT256

11: φT16

TMRA4 source clock selection

00

01

10

11

TA4IN

φT1

φT4

φT16

TMRA5 source clock selection

TA45MOD

<TA45M1:0> ≠ 01

<TA45M1:0> = 01

00

Comparator output

from TMRA4

φT1

Overflow output from

TMRA4

(16-bit timer mode)

01

10

11

φT16

φT256

PWM cycle selection

00

01

10

11

Reserved

2⁶× Source clock

2⁷× Source clock

2⁸× Source clock

TMRA45 operation mode selection

00

01

10

11

Two 8-bit timers

16-bit timer

8-bit PPG

8-bit PWM (TMRA4) + 8-bit timer (TMRA5)

Figure 3.8.9 Register for TMRA

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TMRA1 Flip-Flop Control Register

7

6

5

4

3

2

1

0

TA1FFCR

(0105H)

Bit symbol

Read/Write

Reset State

Function

TA1FFC1 TA1FFC0 TA1FFIE

TA1FFIS

R/W R/W

A read

1

0

-modify-write

operation

cannot be

performed

00: Invert TA1FF

01: Set TA1FF

10: Clear TA1FF

11: Don’t care

TA1FF

control for inversion

inversion select

0: Disable 0: TMRA0

1: Enable 1: TMRA1

Inverse signal for timer flip-flop 1 (TA1FF)

(Don’t care except in 8-bit timer mode)

0

1

Inversion by TMRA0

Inversion by TMRA1

Inversion of TA1FF

0

1

Disabled

Enabled

Control of TA1FF

00

Inverts the value of TA1FF

(by software).

01

10

11

Sets TA1FF to “1”.

Clears TA1FF to “0”.

Don’t care

Note: The values of bits 4, 5, 6 and 7 of TA1FFCR are undefined when read.

Figure 3.8.10 Register for TMRA

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TMRA3 Flip-Flop Control Register

7

6

5

4

3

2

1

0

TA3FFCR

(010DH)

Bit symbol

Read/Write

Reset State

Function

TA3FFC1 TA3FFC0 TA3FFIE

TA3FFIS

R/W R/W

A read

1

0

-modify-write

operation

cannot be

performed

00: Invert TA3FF

01: Set TA3FF

10: Clear TA3FF

11: Don’t care

TA3FF

control for inversion

inversion select

0: Disable 0: TMRA2

1: Enable 1: TMRA3

Inverse signal for timer flip-flop 3 (TA3FF)

(Don’t care except in 8-bit timer mode)

0

1

Inversion by TMRA2

Inversion by TMRA3

Inversion of TA3FF

0

1

Disabled

Enabled

Control of TA3FF

00

Inverts the value of TA3FF (by

software)

01

10

11

Sets TA3FF to “1”.

Clears TA3FF to “0”.

Don’t care

Note: The values of bits 4, 5, 6 and 7 of TA3FFCR are undefined when read.

Figure 3.8.11 Register for 8-Bit Timer

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TMRA5 Flip-Flop Control Register

7

6

5

4

3

2

1

0

TA5FFCR

(0115H)

Bit symbol

Read/Write

Reset State

Function

TA5FFC1 TA5FFC0 TA5FFIE

TA5FFIS

R/W R/W

A read

1

0

-modify-write

operation

cannot be

performed

00: Invert TA5FF

01: Set TA5FF

10: Clear TA5FF

11: Don’t care

TA5FF

control for inversion

inversion select

0: Disable 0: TMRA4

1: Enable 1: TMRA5

Inverse signal for timer flip-flop 5 (TA5FF)

(Don’t care except in 8-bit timer mode)

0

1

Inversion by TMRA4

Inversion by TMRA5

Inversion of TA5FF

0

1

Disabled

Enabled

Control of TA5FF

00

Inverts the value of TA5FF (by

software).

01

10

11

Sets TA5FF to “1”.

Clears TA5FF to “0”.

Don’t care

Note: The values of bits 4, 5, 6 and 7 of TA5FFCR are undefined when read.

Figure 3.8.12 Register for TMRA

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Timer Register

4

7

6

5

3

2

1

0

－

TA0REG bit Symbol

(0102H)

Read/Write

Reset State

W

Undefined

－

TA1REG bit Symbol

(0103H)

Read/Write

Reset State

W

Undefined

－

TA2REG bit Symbol

(010AH)

Read/Write

Reset State

W

Undefined

－

TA3REG bit Symbol

(010BH)

Read/Write

Reset State

W

Undefined

－

TA4REG bit Symbol

(0112H)

Read/Write

Reset State

W

Undefined

－

TA5REG bit Symbol

(0113H)

Read/Write

Reset State

W

Undefined

Note: A read-modify-write operation cannot be performed.

Figure 3.8.13 TMRA Register

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3.8.4

Operation in Each Mode

(1) 8-bit timer mode

Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers.

When set function and counter data, be stopped operation of TMRA0 and TMRA1

registers beforehand.

a. Generating interrupts at a fixed interval (using TMRA1)

To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop

TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and

TA1REG register, respectively. Then, enable the interrupt INTTA1 and start

TMRA1 counting.

Example: To generate an INTTA1 interrupt every 12 μs at fc = 27 MHz, set each

register as follows:

* Clock state

System clock: High frequency (fc)

Clock gear: 1(fc)

Prescaler: 1/2

MSB

LSB

7

−

0

6

5

X

4

X

3

−

0

2

−

1

0

−

TA01RUN

TA01MOD

←

X

0

Stop TMRA1 and clear it to 0.

3

Select 8-bit timer mode and select φT1 ((2 /fc)s at fc =

27 MHz) as the input clock.

X

TA1REG

0

X

–

0

1

X

1

0

1

−

0

−

1

0

−

1

0

−

Set TA1REG to 12 μs ÷ φT1 = 40 = 28H

Enable INTTA1 and set it to level 5.

Start TMRA1 counting.

INTETA01

TA01RUN

←

X

X: Don’t care, −: No change

Select the input clock using Table 3.8.2.

Note: The input clocks for TMRA0 and TMRA1 are different from as follows.

TMRA0: TA0IN input, φT1, φT4 or φT16

TMRA1: Comparator output from TMRA0, φT1, φT16 and φT256

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b. Generating a 50% duty ratio square wave pulse

The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its

status output via the timer output pin (TA1OUT).

Example: To output a 1.8 μs square wave pulse from the TA1OUT pin at fc = 27 MHz,

use the following procedure to make the appropriate register settings. This

example uses TMRA1; however, either TMRA0 or TMRA1 may be used.

* Clock state

System clock: High frequency (fc)

Clock gear: 1(fc)

Prescaler : 1/2

MSB

LSB

7

6

X

0

5

4

3

2

1

0

TA01RUN

TA01MOD

←

−

X

−

0

−

Stop TMRA1 and clear it to 0.

Select 8-bit timer mode and select φT1 ((2³/fc) μs at fc

0

1

X

= 27 MHz) as the input clock.

TA1REG

←

0

1

0

1

Set the timer register to 1.8 μs ÷ φT1 ÷ 2 = 3

Clear TA1FF to “0” and set it to invert on the match

detects signal from TMRA1.

TA1FFCR

X

P7CR

←

X

–

X

−

X

−

1

−

X

−

Set P71 to function as the TA1OUT pin.

Start TMRA1 counting.

P7FC

TA01RUN

X

X: Don’t care, −: No change

φT1

TA01RUN

Bit7 to Bit2

Up

counter

Bit1

1

2

3

1

0

1

2

3

0

2

3

Bit0

Comparator timing

Comparator output

(Match detect)

INTTA1

Up counter

clear

TA1FF

TA1OUT

0.9 μs @fc = 27 MHz

Figure 3.8.14 Square Wave Output Timing Chart (50% Duty)

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c. Making TMRA1 count up on the match signal from the TMRA0 comparator

Select 8-bit timer mode and set the comparator output from TMRA0 to be the

input clock to TMRA1.

Comparaot output

(TMRA0 match)

TMRA0 up counter

(when TA0REG = 5)

1

2

3

4

5

1

2

3

2

4

5

1

2

3

TMRA1 up counter

(when TA1REG = 2)

1

TMRA1 match output

Figure 3.8.15 TMRA1 Count Up on Signal from TMRA0

(2) 16-bit timer mode

A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and

TMRA1.

To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together,

set TA01MOD<TA01M1:0> to “01”.

In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for

TMRA1, regardless of the value set in TA01MOD<TA1CLK1:0>. Table 3.8.2 shows the

relationship between the timer (Interrupt) cycle and the input clock selection.

Timer interrupt cycle set lower 8 bits to TA0REG and set upper 8 bits to TA1REG.

Please keep setting TA0REG first because setting data for TA0REG inhibit its compare

function and setting data for TA1REG permit it.

Setting example: To generate an INTTA1 interrupt every 0.3 s at fc = 27MHz, set the

timer registers TA0REG and TA1REG as follows:

* Clock state

System clock: High frequency (fc)

Clock gear: 1(fc)

Prescaler: 1/2

If φT16 ((2⁷/fc) s @fc = 27 MHz) is used as the input clock for counting, set the

following value in the registers:

0.3 s/(2⁷/fc)s = 62500 = F424H;

i.e. set TA1REG to F4H and TA0REG to 24H.

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The comparator match signal is output from TMRA0 each time the up counter UC0

matches TA0REG, though the up counter UC0 is not be cleared and also INTTA0 is not

generated.

In the case of the TMRA1 comparator, the match detect signal is output on each

comparator pulse on which the values in the up counter UC1 and TA1REG match.

When the match detect signal is output simultaneously from both the comparators

TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to “0” and the

interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer

flip-flop TA1FF is inverted.

Example: When TA1REG = 04H and TA0REG = 80H

Value of up counter

(UC1, UC0)

0080H

0080H 0180H 0280H 0380H 0480H

TMRA0 comparator match

detect signal

TMRA0 comparator match

detect signal

INTTA0

INTTA1

TA1OUT

Inversion

Figure 3.8.16 Timer Output by 16-Bit Timer Mode

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(3) 8-bit PPG (Programmable pulse generation) output mode

Square wave pulses can be generated at any frequency and duty ratio by TMRA0.

The output pulses may be active low or active high. In this mode TMRA1 cannot be

used.

TMRA0 outputs pulses on the TA1OUT pin (shared with P71).

t

L

H

When <TA1FFC1:0>=”10”

t

H

L

When <TA1FFC1:0>=”01”

Example when <TA1FFC1:0>=”01”

TA0REG and UC0 match

(Interrupt INTTA0)

TA1REG and UC0 match

(Interruput INTTA1)

TA1OUT

TA0REG

TA1REG

Figure 3.8.17 8-Bit PPG Output Waveforms

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In this mode, a programmable square wave is generated by inverting the timer

output each time the 8-bit up counter (UC0) matches the value in one of the timer

registers TA0REG or TA1REG.

The value set in TA0REG must be smaller than the value set in TA1REG.

Although the up counter for TMRA1 (UC1) is not used in this mode,

TA01RUN<TA1RUN> should be set to “1”, so that UC1 is set for counting.

Figure 3.8.18 shows a block diagram representing this mode.

TA1OUT

TA01RUN<TA0RUN>

Selector

TA0IN

φT1

φT4

φT16

8-bit

up counter (UC0)

TA1FF

Inversion

TA1FFCR<TA1FFIE>

TA01MOD<TA0CLK1:0>

INTTA0

Comparator

INTTA1

Selector

TA0REG

Shift trigger

Register Buffer

TA0REG-WR

TA1REG

TA01RUN<TA0RDE>

Internal data bus

Figure 3.8.18 Block Diagram of 8-Bit PPG Output Mode

If the TA0REG double buffer is enabled in this mode, the value of the register buffer

will be shifted into TA0REG each time TA1REG matches UC0.

Use of the double buffer facilitates the handling of low-duty waves (when duty is

varied).

Match with TA0REG

and up counter

(Up counter = Q )

(Up countner = Q )

2

1

Match with TA1REG

Shift from register buffer

TA0REG

(Value to be compared)

Q

2

Q

1

Register buffer

Q

2

Q

3

TA0REG (Register buffer)

write

Figure 3.8.19 Operation of Register Buffer

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Example: To generate 1/4-duty 50-kHz pulses (at fc = 27 MHz):

20 μs

* Clock state

System clock: High frequency (fc)

Clock gear: 1(fc)

Prescaler: 1/2

Calculate the value that should be set in the timer register.

To obtain a frequency of 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 μs

φT1 = (2³/fc) s (@fc = 27 MHz);

20 μs ÷(2³/fc) s ≒67

Therefore set TA1REG to 67 (43H) and then 50.3kHz pulse is generated.

The duty is to be set to 1/4: t × 1/4 = 20 μs × 1/4 = 5 μs

5 μs ÷ (2³/fc) s ≒17

Therefore, set TA0REG = 17 = 11H.

MSB

7

LSB

0

6

5

4

3

2

0

1

0

TA01RUN

←

0

X

−

0

Stop TMRA0 and TMRA1 and clear it to “0” (double buffer

disable).

TA01MOD

TA0REG

TA1REG

TA1FFCR

←

1

0

X

0

1

X

0

X

1

X

0

X

0

1

0

1

X

Set the 8-bit PPG mode, and select φT1 as input clock.

Write 11H

0

Write 43H

X

Set TA1FF, enabling inversion.

Writing “10” provides negative logic pulse.

P7CR

←

X

1

X

−

X

−

1

−

X

1

Set P71 as the TA1OUT pin.

P7FC

TA01RUN

X

Start TMRA0 and TMRA1 counting and enable double buffer.

X: Don’t care, −: No change

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(4) 8-bit PWM output mode

This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum

resolution of 8 bits can be output.

When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also

used as P71). TMRA1 can also be used as an 8-bit timer.

The timer output is inverted when the up counter (UC0) matches the value set in the

timer register TA0REG or when 2ⁿcounter overflow occurs (n = 6, 7 or 8 as specified by

TA01MOD<PWM01:00>). The up counter UC0 is cleared when 2ⁿcounter overflow

occurs.

The following conditions must be satisfied before this PWM mode can be used.

Value set in TA0REG < Value set for 2ⁿcounter overflow

Value set in TA0REG ≠ “0”

TA0REG and

UC0 match

2ⁿoverflow

(INTTA0 interrupt)

TA1OUT

t

PWM

(PWM cycle)

Figure 3.8.20 8-Bit PWM Output Wave Form

Figure 3.8.21 shows a block diagram representing this mode.

TA1OUT

TA1FF

TA01RUN <TA0RUN>

8-bit up counter

TA0IN

φT1

TA1FFCR

Clear

Selector

(UC 0)

φT4

φT16

Invert

2ⁿ

TA01MOD

overflow

control

<PWM01:00>

TA01MOD<TA0CLK1:0>

Overflow

Comparator

TA0REG

INTTA0

Selector

Shift trigger

TA0REG-WR

Register buffer

TA01RUN<TA0RDE>

Internal data bus

Figure 3.8.21 Block Diagram of 8-Bit PWM Output Mode

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In this mode, the value of the register buffer will be shifted into TA0REG if 2ⁿ

overflow is detected when the TA0REG double buffer is enabled.

Use of the double buffer facilitates the handling of low duty ratio waves.

Match with TA0REG

Up counter = Q

UP counter = Q

1

2

2ⁿoverflow

Shift into TA0REG

TA0REG

(Value to be compared)

Q

2

Q

1

Q

2

Q

3

Register buffer

TA0REG (Register buffer)

Write

Figure 3.8.22 Operation of Register Buffer

Example: To output the following PWM waves on the TA1OUT pin at fc = 27 MHz:

15 μs

37.9 μs

* Clock state

System clock: High frequency (fc)

Clock gear: 1(fc)

Prescaler : 1/2

To achieve a 37.9 μs PWM cycle by setting φT1 to (2³/fc) s (@fc = 27 MHz):

37.9 μs ÷ (2³/fc) s = 128 = 2ⁿ

Therefore n should be set to 7.

Set the following value for TA0REG during the low-level period:

15.0 μs ÷(2³/fc) s = 51 = 33H

MSB

LSB

7

6

X

1

5

X

1

4

X

0

3

−

2

−

1

−

0

1

TA01RUN

TA01MOD

←

−

Stop TMRA0 and clear it to “0”.

Select 8-bit PWM mode (cycle: 2⁷) and select φT1 as the

input clock.

1

TA0REG

←

0

1

0

1

0

1

Write 33H.

TA1FFCR

X

Clear TA1FF to 0; enable the inversion.

P7CR

←

X

1

X

−

–

X

−

X

−

1

−

X

1

Set P71 to function as the TA1OUT pin.

Start TMRA0 counting.

P7FC

TA01RUN

X: Don’t care, −: No change

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Table 3.8.3 PWM Cycle

Select

system

clock

Select

prescaler

clock

PWM Cycle

2⁷(x128)

2⁶(x64)

2⁸(x256)

Gear value

SYSCR1

−

TAxxMOD<TAxCLK1:0>

<GEAR2:0>

SYSCR1

SYSCR0

φT1(x2) φT4(x8) φT16(x32) φT1(x2) φT4(x8) φT16(x32) φT1(x2) φT4(x8) φT16(x32)

1 (1/fs)

512/fs 2048/fs

512/fc 2048/fc

8192/fs

8192/fc

1024/fs

1024/fc

4096/fs

16384/fs 2048/fs 8192/fs 32768/fs

−

4096/fc

8192/fc

16384/fc 2048/fc 8192/fc 32768/fc

32768/fc 4096/fc 16384/fc 65536/fc

000(x1)

001(x2)

010(x4)

011(x8)

100(x16)

00

1024/fc 4096/fc 16384/fc 2048/fc

(f

)

FPH

x4

2048/fc 8192/fc 32768/fc 4096/fc 16384/fc 65536/fc 8192/fc 32768/fc 131072/fc

4096/fc 16384/fc 65536/fc 8192/fc 32768/fc 131072/fc 16384/fc 65536/fc 262144/fc

8192/fc 32768/fc 131072/fc 16384/fc 65536/fc 262144/fc 32768/fc 131072/fc 524288/fc

0 (1/fc)

10

8192/fc 32768/fc 131072/fc 16384/fc 65536/fc 262144/fc 32768/fc 131072/fc 524288/fc

(fcx16)

−

(5) Settings for each mode

Table 3.8.4 shows the SFR settings for each mode.

Table 3.8.4 Timer Mode Setting Registers

Register Name

TA01MOD

TA1FFCR

<TA01M1:0> <PWM01:00> <TA1CLK1:0> <TA0CLK1:0>

Upper Timer

Input Clock

Lower Timer Timer F/F Invert

Function

Timer Mode

PWM Cycle

Input Clock

Signal Select

Lower timer match, External clock,

0: Lower timer output

1: Upper timer output

8-bit timer × 2 channels

00

−

φT1, φT16, φT256

φT1, φT4, φT16

(00, 01, 10, 11)

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

16-bit timer mode

01

10

−

8-bit PPG × 1 channel

8-bit PWM × 1 channel

2⁶, 2⁷, 2⁸

11

−

(01, 10, 11)

φT1, φT16 , φT256

8-bit timer × 1 channel

−: Don’t care

−

Output disabled

(01, 10, 11)

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3.9 16-Bit Timer/Event Counters (TMRB)

The TMP91CU27/CP27/CK27 contains one multifunctional 16-bit timer/event counter

(TMRB0) which have the following operation modes:

•

16-bit interval timer mode

16-bit event counter mode

16-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle

with variable period)

Can be used following operation modes by capture function:

Frequency measurement mode

•

Pulse width measurement mode

Time differential measurement mode

Figure 3.9.1 show block diagram of TMRB0. The timer/event counter consists of a 16-bit up

counter, two 16-bit timer registers (one of them with a double-buffer structure), two 16-bit

capture register, two comparators, a capture input controller, a timer flip-flop and a control

circuit.

The timer/Event counter is controlled by 11-byte control register (SFR).

Table 3.9.1 Registers and Pins for TMRB0

Channel

TMRB0

Spec

External clock/

TB0IN0 (Shared with P80)

TB0IN1 (Shared with P81)

TB0OUT0 (Shared with P82)

TB0OUT1 (Shared with P83)

TB0RUN (0180H)

capture trigger input pin

External pin

Timer flip-flop output pin

Timer RUN register

Timer mode register

TB0MOD (0182H)

Timer flip-flop control register

TB0FFCR (0183H)

TB0RG0L (0188H)

TB0RG0H (0189H)

Timer register

SFR name

(Address)

TB0RG1L (018AH)

TB0RG1H (018BH)

TB0CP0L (018CH)

TB0CP0H (018DH)

TB0CP1L (018EH)

Capture register

TB0CP1H (018FH)

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3.9.1

Block Diagram of TMRB0

Figure 3.9.1 Block Diagram of TMRB0

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3.9.2

Operation of Each Circuit

(1) Prescaler

The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0)

is a divided clock (divided by 4) from selected clock by the register SYSCR0<PRCK1:0>

of clock gear.

This prescaler can be started or stopped using TB0RUN<TB0PRUN>. Counting

starts when <TB0PRUN> is set to “1”; the prescaler is cleared to “0” and stops

operation when <TB0PRUN> is cleared to “0”.

Table 3.9.2 show prescaler output clock resolution.

Table 3.9.2 Prescaler Output Clock Resolution

System Clock Prescaler Clock

Clock Gear

Value

Timer Counter Input Clock

TMRB Prescaler

Selection

SYSCR1

<SYSCK>

Selection

SYSCR0

−

SYSCR1

<GEAR2:0>

TB0MOD<TB0CLK1:0>

<PRCK1:0>

φT1(1/2)

φT4(1/8) φT16(1/32)

1 (fs)

0 (fc)

−

fs/8

fc/8

fs/32

fc/32

fc/64

fs/128

fc/128

fc/256

000(1/1)

001(1/2)

fc/16

00

(f

)

010(1/4)

fc/32

fc/128

fc/512

FPH

1/4

011(1/8)

fc/64

fc/256

fc/512

fc/1024

fc/2048

100(1/16)

fc/128

10

−

fc/128

fc/512

fc/2048

(fc/16 clock)

(2) Up counter (UC10)

UC10 is a 16-bit binary counter which counts up according to input from the clock

specified by TB0MOD<TB0CLK1:0> register.

As the input clock, one of the prescaler internal clocks φT1, φT4 and φT16 or an

external clock from TB0IN0 pin can be selected. Counting or stopping and clearing of

the counter is controlled by timer operation control register TB0RUN<TB0RUN>.

When clearing is enabled, the up counter UC10 will be cleared to “0” each time its

value matches the value in the timer register TB0RG1H/L. If clearing is disabled, the

counter operates as a free-running counter. Clearing can be enabled or disabled using

TB0MOD<TB0CLE>.

A timer overflow interrupt (INTTBOF0) is generated when UC10 overflow occurs.

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(3) Timer registers (TB0RG0H/L and TB0RG1H/L)

These two 16-bit registers are used to set the interval time. When the value in the up

counter UC10 matches set value of timer register, the comparator match detect signal

will be active.

Setting data for both upper and lower timer registers are always needed. For

example, either using a 2-byte data transfer instruction or using a 1-byte date transfer

instruction twice for the lower 8 bits and upper 8 bits in order.

The TB0RG0H/L timer register has a double-buffer structure, which is paired with a

register buffer 0. The timer control register TB0RUN<TB0RDE> control whether the

double buffer structure should be enabled or disabled: it is disabled when <TB0RDE> =

“0”, and enabled when <TB0RDE> = “1”.

When the double buffer is enabled, data is transferred from the register buffer to the

timer register when the values in the up counter (UC10) and the timer register

TB0RG1H/L match.

After a Reset, TB0RG0H/L and TB0RG1H/L are undefined. To use the 16-bit timer

after reset, data should be written beforehand.

When reset, <TB0RDE> is initialized to “0”, whereby the double buffer is disabled.

To use the double buffer, write data to the timer register, set <TB0RDE> to “1”, then

write following data to the register buffer.

TB0RG0H/L and the register buffer are allocated to the same memory address

0188H/0189H. When <TB0RDE> = “0”, same value will be written to both the timer

register and register buffer. When <TB0RDE> = “1”, the value is written into only the

register buffer.

Therefore, when write initial value to timer register, set register buffer to disable.

The addresses of the timer registers are as follows:

TMRB0

TB0RG0H/L

TB0RG1H/L

Upper 8-bit

(TB0RG0H)

Lower 8-bit

(TB0RG0L)

Upper 8-bit

(TB0RG1H)

Lower 8-bit

(TB0RG1L)

000189H

000188H

00018BH

00018AH

The TB0RG0H/L to TB0RG1H/L are write-only registers and thus cannot be read.

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(4) Capture registers (TB0CP0H/L, TB0CP1H/L)

These 16-bit registers are used to latch the values of the up counters.

All 16 bits of data in the capture register should be read. For example, using 2-byte

data load instruction or using 1-byte date load instruction twice for lower 8 bits and

upper 8 bits in order.

The addresses of the capture registers are as follows:

TMRB0

TB0CP0H/L

TB0CP1H/L

Upper 8-bit

(TB0CP0H)

Lower 8-bit

(TB0CP0L)

Upper 8-bit

(TB0CP1H)

Lower 8-bit

(TB0CP1L)

00018DH

00018CH

00018FH

00018EH

The TB0CP0H/L to TB0CP1H/L are read-only registers and thus cannot be read.

(5) Capture, external interrupt control

This circuit controls the timing to latch the value of the up counter UC10 into

TB0CP0H/L, TB0CP1H/L and control generation of external interrupt. The latch

timing of capture register and selection of edge for external interrupt is set in

TB0MOD<TB0CPM1:0>.

The edge of external interrupt INT6 is fixed to rising edge.

Besides, the value of up counter can be loaded into a capture registers by software.

Whenever “0” is written to TB0MOD<TB0CP0I>, the current value in the up counter is

loaded into capture register TB0CP0H/L. It is necessary to keep the prescaler in run

mode (i.e., TB0RUN<TB0PRUN> must be held at a value of “1”).

Note: As described above, whenever “0” is written to TB0MOD<TB0CP0I>, the current value in the up counter is

loaded into capture register TB0CP0H/L. However, note that the current value in the up counter is also loaded

into capture register TB0CP0H/L when “1” is written to TB0MOD<TB0CP0I> while this bit is holding “0”.

Notice

“0” WR

“1” WR

NOP

Write to TB0MOD

register

TB0MOD

CAPTURE

operation

Capture

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(6) Comparators (CP10 and CP11)

CP10 and CP11 are 16-bit comparators which compare the value in the up counter

UC10 value with the value set of TB0RG0H/L or TB0RG1H/L respectively, in order to

detect a match. If a match is detected, the comparators generate an interrupt

(INTTB00 or INTTB01 respectively).

(7) Timer flip-flops (TB0FF0 and TB0FF1)

These flip-flops are inverted by the match detect signals from the comparators and

the latch signals to the capture registers. Inversion can be enabled and disabled for

each element using TB0FFCR<TB0C1T1, TB0C0T1, TB0E1T1, TB0E0T1>.

After a reset, the value of TB0FF0 and TB0FF1 is undefined. If “00” is written to

TB0FFCR<TB0FF0C1:0> or <TB0FF1C1:0>, TB0FF0 or TB0FF1 will be inverted. If

“01” is written to the flip-flops control registers, the value of TB0FF0 and TB0FF1 will

be set to “1”. If “10” is written to the flip-flops control registers, the value of TB0FF0

and TB0FF1 will be cleared to “0”.

The values of TB0FF0 and TB0FF1 can be output to the timer output pins TB0OUT0

(which is shared with P82), TB0OUT1 (which is shared with P83). Timer output should

be specified by using the port 8 function register P8FC and port 8 control register

P8CR.

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3.9

3.9.3

SFR

Figure 3.9.1

TMRB0 RUN Register

7

6

5

4

3

2

1

0

TB0RUN

(0180H)

Bit symbol

TB0RDE

R/W

–

I2TB0

R/W

0

TB0PRUN

R/W

TB0RUN

R/W

Read/Write

Reset State

Function

R/W

0

Double

buffer

Always write

“0”.

IDLE2

TMRB0

Up-counter

(UC10)

0: Stop

prescaler

0: Stop and clear

1: Run (Count up)

0: Disable

1: Enable

1: Operation

Count operation

0

1

Stop and clear

Count

Note: 1, 4 and 5 of TB0RUN are read as undefined values.

Figure 3.9.2 Register for TMRB

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TMRB0 Mode Register

7

6

5

4

3

2

1

0

TB0MOD

(0182H)

Bit symbol

Read/Write

Reset State

Function

TB0CT1

TB0ET1

TB0CP0I TB0CPM1 TB0CPM0 TB0CLE

TB0CLK1 TB0CLK0

R/W

W*

1

R/W

0

A read

TB0FF1 Inversion

trigger

Software

capture

Capture timing

00:Disable

Up counter TMRB0 source clock

-modify-write

operation

cannot be

performed

control

0:Clear

select

INT5 is rising edge

0: Trigger disable

control

0:Software

00: TB0IN0 pin input

01: φT1

01:TB0IN0 ↑ TB0IN1 ↑

INT5 is rising edge

1: Trigger enable

Invert when Invert

capture to when

capture

register 1 with timer

register 1

disable

1:Clear

enable

capture

10: φT4

10:TB0IN0 ↑ TB0IN0 ↓

INT5 is falling edge

1:Undefined

11: φT16

*Always

match UC0

11:TA1OUT ↑ TA1OUT ↓

INT5 is rising edge

read as “1”

TMRB0 source clock

00

01

10

11

External input clock (TB0IN0 pin input)

φT1

φT4

φT16

Clear of up counter 10 (UC10)

0

1

Disable clear of up counter

Clear by match with TB0RG1H/L

Capture/Interrupt timing

Capture control

Capture disable

INT5 control

INT5 generate by rising TB0IN0

00

01

TB0CP0H/L by rising TB0IN0

TB0CP1H/L by rising TB0IN1

TB0CP0H/L by rising TB0IN0

TB0CP1H/L by falling TB0IN0

TB0CP0H/L by rising TA1OUT

TB0CP1H/L by falling TA1OUT

INT5 generate by falling TB0IN0

INT5 generate by rising TB0IN0

10

11

Software capture

0

1

Capture value of up counter to TB0CP0.

Undefined (Note)

Note: Whenever programming “0” to TB0MOD<TB0CP0I> bit, present value of up counter is received to capture

register TB0CP0H/L. But, write “1” to TB0MOD<TB0CP0I> in condition of written “0” to TB0MOD<TB0CP0I>

bit, present value of up counter is received to capture register TB0CP0H/L. Therefore you must to regard.

Figure 3.9.3 Register for TMRB

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TMRB0 Flip-Flop Control Register

7

6

5

4

3

2

1

0

TB0FFCR

(0183H)

Bit symbol

Read/Write

Reset State

Function

TB0FF1C1 TB0FF1C0 TB0C1T1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0

W* R/W W*

1

0

1

A read

TB0FF1 control

00: Invert

TB0FF0 inversion trigger

0: Trigger disable

TB0FF0 Control

00: Invert

-modify-write

operation

cannot be

performed

01: Set

1: Trigger enable

01: Set

Invert when Invert when Invert when Invert when

10: Clear

the UC

value is

loaded into loaded into with

the UC

value is

the UC

matches

the UC

matches

with

11: Don’t care

* Always read as “11”.

TB0CP1H/ TB0CP0H/ TB0RG1H/ TB0RG0H/

L. L. L.

L

Timer Flip-Flop (TB0FF0) control

00

01

10

11

Invert to TB0FF0 (Software inversion).

Set TB0FF0 to “1”.

Clear TB0FF0 to “0”.

Don’t care

Inversion trigger of TB0FF0 when the UC10 matches

with TB0RG0H/L

0

1

Trigger disable (Disable inversion)

Trigger enable (Enable inversion)

Inversion trigger of TB0FF0 when the UC10 matches

with TB0RG1H/L

0

1

Trigger disable (Disable inversion)

Trigger enable (Enable inversion)

Inversion trigger of TB0FF0 when the UC10 value is

loaded into TB0CP0H/L

0

1

Trigger disable (Disable inversion)

Trigger enable (Enable inversion)

Inversion trigger of TB0FF0 when the UC10 value is

loaded into TB0CP1H/L

0

1

Trigger disable (Disable inversion)

Trigger enable (Enable inversion)

Figure 3.9.4 Register for TMRB

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TMRB0 register

4

7

6

5

3

2

1

0

－

TB0RG0L bit Symbol

(0188H)

Read/Write

Reset State

W

Undefined

－

TB0RG0H bit Symbol

(0189H)

Read/Write

Reset State

W

Undefined

－

TB0RG1L bit Symbol

(018AH)

Read/Write

Reset State

W

Undefined

－

TB0RG1H bit Symbol

(018BH)

Read/Write

Reset State

W

Undefined

Note: A read-modify-write operation cannot be performed.

Figure 3.9.5 TMRB Register

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3.9

3.9.4

Operation in Each Mode

(1) 16-bit interval timer mode

Generating interrupts at fixed intervals

In this example, the interval time is set the timer register TB0RG1H/L to generate the

interrupt INTTB01.

Figure 3.9.1 TMRB RegisterFigure 3.9.2Figure 3.9.3Figure 3.9.4Figure 3.9.5

7

–

X

1

0

6

0

1

0

5

X

0

1

4

X

0

3

–

X

0

2

0

1

X

0

1

*

0

1

*

TB0RUN

INTETB0

TB0FFCR

TB0MOD

←

Stop TMRB0.

Enable INTTB01 and set interrupt level 4. Disable INTTB00.

Disable the trigger.

Select source clock and

Disable the capture function.

Set the interval time.

(** = 01, 10, 11)

TB0RG1H/L

TB0RUN

←

*

–

*

0

*

–

*

1

*

1

(16 bits)

X

Start TMRB0.

X: Don’t care, −: No change

(2) 16-bit event counter mode

In 16-bit timer mode as described in above, the timer can be used as an event counter

by selecting the external clock (TB0IN0 pin input) as the input clock.

Up counter counting up by rising edge of TB0IN0 pin input. And execution software

capture and reading capture value enable reading count value.

7

0

6

0

5

X

0

4

X

0

3

–

X

2

0

–

0

1

X

–

0

1

0

TB0RUN

P8CR

←

Stop TMRB0.

X

1

Set P80 to TB0IN0 input mode.

P8FC

INTETB0

Enable INTTB01 and set interrupt level 4. Disable INTTB00.

TB0FFCR

TB0MOD

←

1

0

∗

0

1

0

∗

0

1

∗

0

∗

0

∗

–

0

1

∗

1

0

∗

1

0

∗

1

Disable trigger.

Set input clock to TB0IN0 pin input.

Set number of count.

(16 bits)

TB0RG1H/L

∗

TB0RUN

←

X

Start TMRB0.

X: Don’t care, −: No change

When used as an event counter, set the prescaler to “RUN”.

(TB0RUN<TB0PRUN> = “1”)

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(3) 16-bit programmable pulse generation (PPG) output mode

Square wave pulses can be generated at any frequency and duty ratio. The output

pulse may be either low active or high active.

The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is enabled

by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L

and is output to TB0OUT0. In this mode, the following conditions must be satisfied.

(Set value of TB0RG0H/L) < (Set value of TB0RG1H/L)

Match with TB0RG0H/L

(INTTB00 inerrupt)

Match with TB0RG1H/L

(INTTB01 interrupt)

TB0OUT0 pin

Figure 3.9.6 Programmable Pulse Generation (PPG) Output Waveforms

When the TB0RG0H/L double buffer is enabled in this mode, the value of register

buffer 0 will be shifted into TB0RG0H/L at match with TB0RG1H/L. This feature

makes easy the handling of low-duty waves.

Match with TB0RG0H/L

Up counter = Q

2

1

Match with TB0RG1H/L

Shift into TB0RG1H/L

TB0RG0H/L

(Value to be compared)

Q

1

Q

2

Register buffer

Q

2

Q

3

Write TB0RG0H/L

Figure 3.9.7 Operation of Register Buffer

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The following block diagram illustrates this mode.

TB0RUN<TB0RUN>

TB0OUT0 (PPG output)

Selector

TB0IN0

16-bit up counter

UC10

φT1

φT4

F/F

(TB0FF0)

clear

φT16

Match

16-bit comparator

TB0RG0H/L

16-bit comparator

Selector

TB0RG0-WR

Register buffer 0

TB0RG1H/L

TB0RUN<TB0RDE>

Internal data bus

Figure 3.9.8 Block Diagram of 16-Bit PPG Mode

The following example shows how to set 16-bit PPG output mode:

7

0

*

1

6

0

*

0

5

X

*

4

X

*

3

–

*

–

2

0

*

0

1

X

*

0

*

0

TB0RUN

←

Disable the TB0RG0H/L double buffer and stop TMRB0.

Set the duty ratio.

TB0RG0H/L

*

(16 bits)

TB0RG1H/L

TB0RUN

←

*

Set the frequency.

*

(16 bits)

X

Enable the TB0RG0H/L double buffer.

(The duty and frequency are changed on an INTTB01

interrupt.)

TB0FFCR

TB0MOD

←

X

0

X

0

1

0

1

0

1

0

Set the mode to invert TB0FF0 at the match with

TB0RG0H/L /TB0RG1H/L. Clear TB0FF0 to “0”.

*

Select the source clock and disable the capture function.

(** = 01, 10, 11)

P8CR

←

–

1

–

0

–

X

–

X

–

1

–

X

–

X

1

Set P82 to function as TB0OUT0.

Start TMRB0.

P8FC

TB0RUN

X: Don’t care, −: No change

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(4) Capture function examples

Used capture function, they can be applicable in many ways, for example:

a. One-shot pulse output from external trigger pulse

b. For frequency measurement

c. For pulse width measurement

d. For time difference measurement

a. One-shot pulse output from external trigger pulse

Set the up counter UC10 in free-running mode with the internal input clock,

input the external trigger pulse from TB0IN0 pin, and load the value of

up-counter into capture register TB0CP0H/L at the rise edge of the TB0IN0 pin.

When the interrupt INT5 is generated at the rise edge of TB0IN0 input, set the

TB0CP0H/L value (c) plus a delay time (d) to TB0RG0H/L (= c + d), and set the

above set value (c + d) plus a one-shot width (p) to TB0RG1H/L (= c + d + p). And,

set “11” to timer flip-flop control register TB0FFCR<TB0E1T1, TB0E0T1>. Set to

trigger enable for be inverted timer flip-flop TB0FF0 by UC10 matching with

TB0RG0H/L and with TB0RG1H/L. When interrupt INTTB01 occurs, this

inversion will be disabled after one-shot pulse is output.

The (c), (d) and (p) correspond to c, d and p Figure 3.9.9.

Set the counter in free-running mode.

Count clock

(Prescaler output clock)

c

c + d + p

c + d

TB0IN0 pin input

(External trigger pulse)

Load the up counter value into capture

Register 0 (TB0CP0H/L) and INT5 occurred

Match with TB0RG0H/L

Match with TB0RG1H/L

Timer output pin TB0OUT0

INTTB01 occurred

Inversion

enable

Disables inversion

caused by loading of

the up counter value

into TB0CP0H/L.

Inversion

enable

Delay time

(d)

Pulse width

(p)

Figure 3.9.9 One-shot Pulse Output (with delay)

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Example:To output a 2-ms one-shot pulse with a 3-ms delay to the external trigger

pulse via the TB0IN0 pin.

* Clock state

System clock: High frequency (fc)

Clock gear:1 (fc)

Prescaler clock: f

FPH

Main setting

TB0MOD

Set free running.

Count using φT1.

←

X

1

0

1

0

1

0

Load the up counter value into TB0CP0H/L at the rising

edge of TB0IN0 pin input.

TB0FFCR

Clear TB0FF0 to 0.

Disable inversion of TB0FF0.

Set P82 to function as the TB0OUT0 pin.

Set P80 to TB0IN0 input mode.

P8CR

P8FC

←

–

1

X

INTE56

←

X

–

0

–

0

–

0

X

–

1

0

1

0

1

Enable INT5. Disable INTTB00 and INTTB01.

Start TMRB0.

INTETB0

TB0RUN

X

Setting in INT5

TB0RG0H/L

TB0RG1H/L

TB0FFCR

←

TB0CP0H/L + 3ms/φT1

TB0RG0H/L + 2ms/φT1

X

–

1

–

Enable inversion of TB0FF0 when the up counter value

match with value of TB0RG0H/L or TB0RG1H/L.

Enable INTTB01.

INTETB0

←

X

1

0

X

–

Setting in INTTB01

TB0FFCR

←

X

0

–

0

–

0

–

Disable inversion of TB0FF0 when the up counter value

match with value of TB0RG0H/L or TB0RG1H/L.

Disable INTTB01.

INTETB0

←

X

X: Don’t care, −: No change

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When delay time is unnecessary, invert timer flip-flop TB0FF0 when up-counter

value is loaded into capture register (TB0CP0H/L), and set the TB0CP0H/L value (c)

plus the one-shot pulse width (p) to TB0RG1H/L when the interrupt INT5 occurs. The

TB0FF0 inversion should be enable when the up counter (UC10) value matches

TB0RG1H/L, and disabled when generating the interrupt INTTB01.

Count clock

(Prescaler output clock)

c

c + p

TB0IN0 pin input

(External trigger pulse)

Load the up counter value into capture

register 0 (TB0CP0H/L).

INT5 occurred.

Load the up counter value into

capture register 1 (TB0CP1H/L)

INTTB01

Match with TB0RG1H/L

Timer output TB0OUT0

occurred.

Inversion enable

Pulse width

(p)

Enables inversion caused by loading

of the up counter value into

TB0CP0H/L.

Disables inversion caused by loading

of the up counter value into

TB0CP1H/L.

Figure 3.9.10 One-shot Pulse Output of External Trigger Pulse (without delay)

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b. Frequency measurement

The frequency of the external clock can be measured in this mode. The clock is

input through the TB0IN0 pin, and its frequency is measured by the 8-bit timers

TMRA01 and the 16-bit timer/event counter (TMRB0). (TMRA01 is used to setting

of measurement time by inversion TA1FF.)

The TB0IN0 pin input should be for the input clock of TMRB0. Set to TB0MOD

<TB0CPM1:0> = “11”. The value of the up counter (UC10) is loaded into the

capture register TB0CP0H/L at the rise edge of the timer flip-flop TA1FF of 8-bit

timers (TMRA01), and into TB0CP1H/L at its fall edge.

The frequency is calculated by difference between the loaded values in

TB0CP0H/L and TB0CP1H/L when the interrupt (INTTA0 or INTTA1) is

generates by either 8-bit timer.

Count clock

(TB0IN0 pin input)

C2

C1

TA1FF

C1

Load to TB0CP0H/L

C2

Load to TB0CP1H/L

INTTA0/INTTA1

Figure 3.9.11 Frequency Measurement

For example, if the value for the level 1 width of TA1FF of the 8-bit timer is set

to 0.5 s and the difference between the values in TB0CP0H/L and TB0CP1H/L is

100, the frequency is 100 ÷ 0.5 s = 200 Hz.

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c. Pulse width measurement

This mode allows to measure the high-level width of an external pulse. While

keeping the 16-bit timer/event counter counting (Free running) with the internal

clock input, external pulse is input through the TB0IN0 pin. Then the capture

function is used to load the UC10 values into TB0CP0H/L and TB0CP1H/L at the

rising edge and falling edge of the external trigger pulse respectively. The

interrupt INT5 occurs at the falling edge of TB0IN0.

The pulse width is obtained from the difference between the values of

TB0CP0H/L and TB0CP1H/L and the internal clock cycle.

For example, if the internal clock is 0.8 μs and the difference between

TB0CP0H/L and TB0CP1H/L is 100, the pulse width will be 100 × 0.8 μs = 80 μs.

Additionally, the pulse width which is over the UC10 maximum count time

specified by the clock source, can be measured by changing software.

Count clock

C2

(Prescaler output clock)

C1

TB0IN0 pin input

(External pulse)

C1

Load to TB0CP0H/L

C2

Load to TB0CP1H/L

INT5

Figure 3.9.12 Pulse Width Measurement

Note: Pulse width measure by setting “10” to TB0MOD<TB0CPM1:0>. The external interrupt INT5 is generated in

timing of falling edge of TB0IN0 input. In other modes, it is generated in timing of rising edge of TB0IN0 input.

The width of low-level can be measured from the difference between the first C2

and the second C1 at the second INT5 interrupt.

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d. Measurement of difference time

This mode is used to measure the difference in time between the rising edges of

external pulses input through TB0IN0 and TB0IN1.

Keep the 16-bit timer/event counter (TMRB0) counting (Free running) with the

internal clock, and load the UC10 value into TB0CP0H/L at the rising edge of the

input pulse to TB0IN0. Then the interrupt INT5 is generated.

Similarly, the UC10 value is loaded into TB0CP1H/L at the rising edge of the

input pulse to TB0IN1, generating the interrupt INT6.

The time difference between these pulses can be obtained by multiplying the

value subtracted TB0CP0H/L from TB0CP1H/L and the internal clock cycle

together at which loading the up counter value into TB0CP0H/L and TB0CP1H/L

has been done.

.

Count clock

C2

C1

(Prescaler output clock)

TB0IN0 pin input

TB0IN1 pin input

Load to TB0CP0H/L

Load to TB0CP1H/L

INT5

INT6

Differnce time

Figure 3.9.13 Measurement of Difference Time

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3.10 Serial Channels

The TMP91CU27/CP27/CK27 includes 2 serial I/O channels. Each channel is called SIO0 and

SIO1. For each channel, either UART mode (Asynchronous transmission) or I/O interface mode

(Synchronous transmission) can be selected.

• I/O interface mode

Mode 0: For transmitting and receiving I/O data using the

synchronizing signal SCLK for extending I/O.

Mode 1: 7-bit data

• UART mode

Mode 2: 8-bit data

Mode 3: 9-bit data

In mode 1 and mode 2 a parity bit can be added. Mode 3 has a wakeup function for making the

master controller start slave controllers via a serial link (A multi-controller system).

Figure 3.10.2 and Figure 3.10.3 are block diagrams for each channel. Each channel is

structured in prescaler, serial clock generation circuit, receiving buffer and control circuit,

transfer buffer and control circuit.

Serial channels 0 and 1 can be used independently.

Both channels operate in the same fashion except for the following points; hence only the

operation of channel 0 is explained below.

Table 3.10.1 Differences Between Channels 0 to 1

SIO0

SIO1

Pin name

TXD0 (P90)

TXD1 (P93)

RXD0 (P91)

RXD1 (P94)

CTS0 /SCLK0 (P92)

CTS1 /SCLK1 (P95)

IrDA mode

Yes

No

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• Mode 0 (I/O interface mode)

Bit0

1

2

3

4

5

6

7

Transfer direction

• Mode 1 (7-bit UART mode)

No parity

Start Bit0

1

2

3

4

5

6

Stop

Parity

Start Bit0

1

5

Parity Stop

• Mode 2 (8-bit UART mode)

No parity

Start Bit0

1

2

3

4

5

6

7

Stop

Start

Parity Stop

Parity

Bit0

• Mode 3 (9-bit UART mode)

Start Bit0

1

2

3

4

5

6

7

8

Stop

Start Bit0

Bit8 Stop

Wakeup

Figure 3.10.1 Data Format

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3.10.1 Block Diagram of Each Channels

Prescaler

φT0

2

4

8 16 32 64

φT2 φT8 φT32

Serial clock generation circuit

BR0CR

TA0TRG

<BR0CK1:0>

(from TMRA0)

BR0CR

BR0ADD

<BR0S3:0> <BR0K3:0>

UART

mode

φT0

φT2

φT8

φT32

SIOCLK

BR0CR

SC0MOD0 SC0MOD0

Baud rate

generator

<SC1:0>

<SM1:0>

f

SYS

÷2

I/O

interface mode

SCLK0

input

Shared

with P92

SC0CR

<IOC>

I/O interface mode

INT request

INTRX0

INTTX0

SCLK0

ouptut

Shared

with P92

Receive

counter

(UART only ÷ 16)

Serial channel

interrupt

Transmision

counter

(UART only ÷ 16)

SC0MOD0

<WU>

control

RXDCLK

TXDCLK

SC0MOD0

<RXE>

Receive

control

Transmission

control

CTS0

Shared

with P92

SC0CR

SC0MOD0

<CTSE>

Parity control

Receive buffer 1 (Shift register)

RXD0

Shared

with P91

TB8 Transmission buffer (SC0BUF)

RB8

Receive buffer 2 (SC0BUF)

Error flag

SC0CR

TXD0

Shared

with P90

Internal data bus

Figure 3.10.2 Block Diagram of SIO0

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Prescaler

φT0

2

4

8 16 32 64

φT2 φT8 φT32

Serial clock generation circuit

BR1CR

TA0TRG

<BR1CK1:0>

(from TMRA0)

BR1CR

BR1ADD

<BR1S3:0> <BR1K3:0>

UART

mode

φT0

φT2

φT8

φT32

SIOCLK

BR1CR

SC1MOD0 SC1MOD0

Baud rate

generator

<SC1:0>

<SM1:0>

f

SYS

÷2

I/O

interface mode

SCLK1

input

Shared

with P95

SC1CR

<IOC>

I/O interface mode

INT request

SCLK1

output

INTRX1

INTTX1

Shared

with P95

Receive

SC1MOD0 Serial channel

<WU>

Transmision

counter

(UART only ÷ 16)

counter

interrupt

control

(UART only ÷ 16)

RXDCLK

TXDCLK

SC1MOD0

<RXE>

Receive

control

Transmission

control

CTS1

SC1CR

Shared

with P95

SC1MOD0

<CTSE>

Parity control

Receive buffer 1 (Shift register)

RXD1

Shared

with P94

Error flag

SC1CR

RB8

TB8 Transmission buffer (SC1BUF)

Receive buffer 2 (SC1BUF)

TXD1

Shared

with P93

Internal data bus

Figure 3.10.3 Block Diagram of SIO1

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3.10.2 Operation of Each Circuit

(1) Prescaler

There is a 6-bit prescaler for generating a clock to SIO0. The prescaler clock (φT0) is

a divided clock (divided by 4) from selected clock by the register SYSCR0<PRCK1:0> of

clock gear.

The prescaler can be run only case of selecting the baud rate generator as the serial

transfer clock.

Table 3.10.2 shows prescaler clock resolution into the baud rate generator.

Table 3.10.2 Prescaler Clock Resolution to Baud Rate Generator

Select

System Clock

SYSCR1

Select Prescaler Clock Gear

Baud Rate Generator Input Clock

SIO Prescaler

Clock

Value

−

SYSCR0

SYSCR1

BRxCR<BRxCK1:0>

<SYSCK>

<PRCK1:0>

<GEAR2:0>

φT0(1/1)

φT2(1/4)

φT8(1/16) φT32(1/64)

1 (fs)

Don’t care

000(1/1)

001(1/2)

fs/4

fc/4

fs/16

fc/16

fc/32

fc/64

fs/64

fc/64

fs/256

fc/256

fc/512

fc/1024

fc/8

fc/128

fc/256

00

fc/16

(f

)

010(1/4)

FPH

1/4

0 (fc)

fc/32

fc/64

fc/128

fc/256

fc/512

fc/2048

fc/4096

011(1/8)

100(1/16)

fc/1024

10

Don’t care

−

fc/256

fc/1024

fc/4096

(fc/16 clock)

−: Can not be used

The serial interface baud rate generator selects between 4 clock inputs: φT0, φT2,

φT8, and φT32 among the prescaler outputs.

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(2) Baud rate generator

The baud rate generator is a circuit that generates transmission and receiving clocks

that determine the transfer rate of the serial channels.

The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by

the SIO 6-bit prescaler which is shared by the timers. One of these input clocks is

selected using the BR0CR<BR0CK1:0> field in the baud rate generator control register.

The baud rate generator includes a frequency divider, which divides the frequency by 1

or N + (16 – K)/16 to 16 values, thereby determining the transfer rate.

The transfer rate is determined by the settings of BR0CR<BR0ADDE, BR0S3:0> and

BR0ADD<BR0K3:0>.

•

In UART mode

(1) When BR0CR<BR0ADDE> = “0”

The settings BR0ADD<BR0K3:0> are ignored. The baud rate generator divides

the selected prescaler clock by N, which is set in BR0CR<BR0S3:0>. (N = 1, 2, 3

16)

(2) When BR0CR<BR0ADDE> = “1”

The N + (16 – K)/16 division function is enabled. The baud rate generator

divides the selected prescaler clock by N + (16 – K)/16 using the value of N set in

BR0CR<BR0S3:0> and the value of K set in BR0ADD<BR0K3:0>. (N = 2, 3 15,

K = 1, 2, 3 15)

Note: If N = 1 or N = 16, the N + (16 − K)/16 division function is disabled. Clear BR0CR<BR0ADDE> register to “0”.

•

In I/O interface mode

The N + (16 – K)/16 division function is not available in I/O Interface Mode. Set

BR0CR<BR0ADDE> to “0” before dividing by N.

The method for calculating the transfer rate when the baud rate generator is used is

explained below.

•

In UART mode

Input clock of baud rate generator

Frequency divider for baud rate generator

Baud rate =

÷ 16

÷ 2

•

In I/O interface mode

Input clock of baud rate generator

Baud rate =

Frequency divider for baud rate generator

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•

Integer divider (N divider)

For example, when the source clock frequency (fc) = 12.288 MHz, the input clock

frequency = φT2 (fc/16), the frequency divider N (BR0CR<BR0S3:0>) = 5, and

BR0CR<BR0ADDE> = “0”, the baud rate in UART Mode is as follows:

* Clock state

System clock: High frequency (fc)

Clock gear:

1(fc)

Prescaler clock: f

FPH

fc/16

5

Baud rate =

÷ 16

=

12.288 × 10⁶÷ 16 ÷ 5 ÷ 16 = 9600 (bps)

Note: The N + (16 − K)/16 division function is disabled and setting BR0ADD<BR0K3:0> is invalid.

•

N + (16 − K)/16 divider (UART mode only)

Accordingly, when the source clock frequency (fc) = 4.8 MHz, the input clock

frequency

=

φT0, the frequency divider

N

(BR0CR<BR0S3:0>)

=

7,

K

(BR0ADD<BR0K3:0>) = 3, and BR0CR<BR0ADDE> = “1”, the baud rate in UART

Mode is as follows:

* Clock state

System clock: High frequency (fc)

Clock gear:

1(fc)

Prescaler clock: f

FPH

fc/4

7 + (16 – 3)/16

Baud rate =

÷ 16

=

4.8 × 10⁶÷ 4 ÷ (7 + 13/16) ÷ 16 = 9600 (bps)

Table 3.10.3 shows examples of UART mode transfer rates.

Additionally, the external clock input is available in the serial clock. (Serial channels

0 and 1). The method for calculating the baud rate is explained below:

•

In UART mode

Baud rate = external clock input frequency ÷ 16

It is necessary to satisfy (external clock input cycle) ≥ 4/fc

In I/O interface mode

Baud rate = External clock input frequency

It is necessary to satisfy (external clock input cycle) ≥ 16/fc

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Table 3.10.3 Transfer Rate Selection

(when baud rate generator is used and BR0CR<BR0ADDE> = 0.)

Unit (kbps)

Input Clock

φT0

φT2

φT8

φT32

fc [MHz]

Divider N

(fc/4)

(fc/16)

(fc/64)

(fc/256)

(Set to BR0CR<BR0S3:0>)

9.830400

2

4

8

0

5

A

2

3

6

C

1

2

4

8

10

3

1

2

4

5

8

A

0

76.800

38.400

19.200

9.600

19.200

9.600

4.800

2.400

1.200

0.600

2.400

1.200

7.200

4.800

2.400

1.200

19.200

9.600

4.800

2.400

1.200

7.200

24.000

12.000

6.000

4.800

3.000

2.400

1.500

1.200

0.600

0.300

0.150

0.600

0.300

1.800

1.200

0.600

0.300

4.800

2.400

1.200

0.600

0.300

1.800

6.000

3.000

1.500

1.200

0.750

0.600

0.375

↑

4.800

↑

2.400

12.288000

38.400

19.200

115.200

76.800

38.400

19.200

307.200

153.600

76.800

38.400

19.200

115.200

384.000

192.000

96.000

76.800

48.000

38.400

24.000

9.600

↑

4.800

14.745600

28.800

19.200

9.600

↑

4.800

19.6608

76.800

38.400

19.200

9.600

↑

4.800

22.1184

28.800

96.000

48.000

24.000

19.200

12.000

9.600

24.576

↑

6.000

Note 1: Transfer rates in I/O interface mode are eight times faster than the values given above.

Note 2: The values in this table are calculated for when fc is selected as the system clock, fc/1 is selected as the clock

gear and f is selected as the clock for prescaler.

FPH

Timer out clock (TA0TRG) can be used for source clock of UART mode only.

Calculation method the frequency of TA0TRG

Frequency of TA0TRG = Baud rate × 16

Note 3: The TMRA0 match detect signal cannot be used as the transfer clock in I/O interface mode.

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(3) Serial clock generation circuit

This circuit generates the basic clock for transmitting and receiving data.

In I/O interface mode

•

In SCLK output mode with the setting SC0CR<IOC> = “0”, the basic clock is

generated by dividing the output of the baud rate generator by 2, as described

previously.

In SCLK input mode with the setting SC0CR<IOC> = “1”, the rising edge or

falling edge will be detected according to the setting of the SC0CR<SCLKS>

register to generate the basic clock.

•

In UART mode

The SC0MOD0<SC1:0> setting determines whether the baud rate generator

clocks, the internal system clock f_SYS, the trigger output signal from timer TMRA0

or the external clock (SCLK0) is used to generate the basic clock SIOCLK.

(4) Receiving counter

The receiving counter is a 4-bit binary counter used in UART mode that counts up

the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data; each

data bit is sampled three times – on the 7th, 8th and 9th clock cycles.

The value of the data bit is determined from these three samples using the majority

rule.

For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and 9th

clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 are

taken to be 0.

(5) Receiving control

•

In I/O interface mode

In SCLK output mode with the setting SC0CR<IOC> = “0”, the RXD0 signal is

sampled on the rising edge of the shift clock which is output on the SCLK0 pin.

In SCLK input mode with the setting SC0CR<IOC> = “1”, the RXD0 signal is

sampled on the rising or falling edge of the SCLK input, according to the

SC0CR<SCLKS> setting.

•

In UART mode

The receiving control block has a circuit that detects a start bit using the

majority rule. Received bits are sampled three times; when two or more out of

three samples are 0, the bit is recognized as the start bit and the receiving

operation commences.

The values of the data bits that are received are also determined using the

majority rule.

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(6) The receiving buffers

To prevent overrun errors, the receiving buffers are arranged in a double-buffer

structure.

Received data is stored one bit at a time in receiving buffer 1 (which is a shift

register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored

data is transferred to receiving buffer 2 (SC0BUF); this causes an INTRX0 interrupt to

be generated.

The CPU only reads receiving buffer 2 (SC0BUF). Even before the CPU reads

receiving buffer 2 (SC0BUF), the received data can be stored in receiving buffer 1.

However, unless receiving buffer 2 (SC0BUF) is read before all bits of the next data are

received by receiving buffer 1, an overrun error occurs. If an overrun error occurs, the

contents of receiving buffer 1 will be lost, although the contents of receiving buffer 2

and SC0CR<RB8> will be preserved.

SC0CR<RB8> is used to store either the parity bit − added in 8-bit UART mode − or

the most significant bit (MSB) − in 9-bit UART mode.

In 9-bit UART mode the wake-up function for the slave controller is enabled by

setting SC0MOD0<WU> to “1”; in this mode INTRX0 interrupts occur only when the

value of SC0CR<RB8> is “1”.

(7) Transmission counter

The transmission counter is a 4-bit binary counter used in UART mode and which,

like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is

generated every 16 SIOCLK clock pulses.

SIOCLK

15 16

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

1

2

TXDCLK

Figure 3.10.4 Generation of Transmission Clock

(8) Transmission controller

• In I/O interface mode

In SCLK output mode with the setting SC0CR<IOC> = “0”, the data in the

transmission buffer is output one bit at a time to the TXD0 pin on the rising or

falling edge of the shift clock which is output on the SCLK0 pin, according to the

SC0CR<SCLKS> setting.

In SCLK input mode with the setting SC0CR<IOC> = “1”, the data in the

transmission buffer is output one bit at a time on the TXD0 pin on the rising or

falling edge of the SCLK0 input, according to the SC0CR<SCLKS> setting.

•

In UART mode

When transmission data sent from the CPU is written to the transmission buffer,

transmission starts on the rising edge of the next TXDCLK.

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Handshake function

Use of this pin allows data to be sent in units of one data format; thus, overrun

errors can be avoided. The handshake function is enabled or disabled by the

SC0MOD0<CTSE> setting.

When the CTS0 pin goes High on completion of the current data send, data

transmission is halted until the CTS0 pin goes low again. However, the INTTX0

Interrupt is generated, and it requests the next data send from the CPU. The next

data is written in the transmission buffer and data sending is halted.

Though there is no RTS pin, a handshake function can be easily configured by

setting any port assigned to be the RTS function. The RTS should be output high

to request send data halt after data receive is completed by software in the RXD

interrupt routine.

TMP91CU27/CP27/CK27

TXD

RXD

CTS

RTS (any port)

Receiving side

Transmission side

Figure 3.10.5 Hand Shake Function

Timing of writing to the

transmission buffer

Send is suspended

during this period

b

CTS

13

14

15

16

1

2

3

14

15

16

1

2

3

a

SIOCLK

TXDCLK

TXD

Bit0

Start bit

Note 1: If the CTS signal goes high during transmission, no more data will be sent after completion of the current

transmission.

Note 2: Transmission starts on the first falling edge of the TXDCLK clock after the CTS signal has fallen.

Figure 3.10.6 CTS (Clear to send) Timing

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(9) Transmission buffer

The transmission buffer (SC0BUF) shifts out and sends the transmission data

written from the CPU in order from the least significant bit (LSB) in order. When all

the bits are shifted out, the transmission buffer becomes empty and generates an

INTTX0 interrupt.

(10) Parity control circuit

When SC0CR<PE> in the serial channel control register is set to “1”, it is possible to

transmit and receive data with parity. However, parity can be added only in 7-bit

UART mode or 8-bit UART mode. The SC0CR<EVEN> field in the serial channel

control register allows either even or odd parity to be selected.

In the case of transmission, parity is automatically generated when data is written

to the transmission buffer SC0BUF. The data is transmitted after the parity bit has

been stored in SC0BUF<TB7> in 7-bit UART mode or in SC0MOD0<TB8> in 8-bit

UART mode. SC0CR<PE> and SC0CR<EVEN> must be set before the transmission

data is written to the transmission buffer.

In the case of receiving, data is shifted into receiving buffer 1, and the parity is added

after the data has been transferred to receiving buffer 2 (SC0BUF), and then compared

with SC0BUF<RB7> in 7-bit UART mode or with SC0CR<RB8> in 8-bit UART mode.

If they are not equal, a parity error is generated and the SC0CR<PERR> flag is set.

(11) Error flags

Three error flags are provided to increase the reliability of data reception.

1. Overrun error<OERR>

If all the bits of the next data item have been received in receiving buffer 1 while

valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun error is

generated.

The below is a recommended flow when the overrun error is generated.

(INTRX interrupt routine)

1) Read receiving buffer

2) Read error flag

3) If<OERR> = “1”

then

a. Set to disable receiving (write “0” to SC0MOD0<RXE>)

b. Wait to terminate current frame

c. Read receiving buffer

d. Read error flag

e. Set to enable receiving (write “1” to SC0MOD0<RXE>)

f. Request to transmit again

4) Other

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2. Parity error<PERR>

The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is

compared with the parity bit received via the RXD pin. If they are not equal, a

parity error is generated.

3. Framing error<FERR>

The stop bit for the received data is sampled three times around the center. If

the majority of the samples are 0, a framing error is generated.

(12) Timing generation

a. In UART mode

Receiving

Mode

9 bits

8 bits + Parity

8 bits, 7 bits + Parity, 7 bits

Interrupt generation

Center of last bit

(Bit8)

Center of last bit

(Parity bit)

Center of stop bit

timing

Framing error generation

timing

Center of stop bit

Center of last bit

Center of stop bit

Parity error

Center of last bit

(Parity bit)

−

generation timing

Overrun error generation

timing

Center of last bit

(Bit8)

Center of last bit

(Parity bit)

Note: In 9 bits and 8 bits + Parity modes, interrupts coincide with the ninth bit pulse.

Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be

transferred) to allow checking for a framing error.

Transmitting

Mode

9 bits

8 bits + Parity

8 bits, 7 bits + Parity, 7 bits

Just before stop bit is Just before stop bit is Just before stop bit is transmitted

transmitted transmitted

Interrupt timing

b. I/O interface

Transmission

interrupt

SCLK output mode

Immediately after the last bit.(See Figure 3.10.19.)

Immediately after rise of last SCLK signal rising mode, or immediately

after fall in falling mode. (See Figure 3.10.20.)

SCLK input mode

SCLK output mode

SCLK input mode

timing

Timing used to transfer received to data receive buffer 2 (SC0BUF)

(e.g., immediately after last SCLK). (See Figure 3.10.21.)

Timing used to transfer received data to receive buffer 2 (SC0BUF)

(e.g., immediately after last SCLK). (See Figure 3.10.22.)

Receiving

interrupt

timing

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3.10.3 SFR

7

6

5

4

3

2

1

0

SC0MOD0 Bit symbol

TB8

CTSE

RXE

WU

SM1

SM0

SC1

SC0

(0202H)

Read/Write

Reset State

Function

R/W

0

Transfer

data bit8

Hand shake Receive

Wakeup

function

Serial transmission

mode

Serial transmission

clock (UART)

function

control

0: CTS

disable

1: CTS

enable

control

0: Receive 0: Disable 00: I/O interface mode 00: TMRA0 trigger

disable

1: Receive

enable

1: Enable 01: 7-bit UART mode

10: 8-bit UART mode

01: Baud rate generator

10: Internal clock f

SYS

11: 9-bit UART mode

11: External clock

(SCLK0 input)

Serial transmission clock source (UART)

00 Timer TMRA0 trigger output signal

01 Baud rate generator

10 Internal clock f

SYS

11 External clock (SCLK0 input)

Note: The clock selection for the I/O

interface mode is controlled by the

serial control register (SC0CR).

Serial transmission mode

00 I/O Interface mode

01

10

11

7-bit mode

8-bit mode

9-bit mode

UART mode

Wakeup function

9-bit UART

Other modes

Don’t care

Interrupt generated when

0

data is received

Interrupt generated only

1

when SC0CR<RB8> = “1”

Receiving function

0

1

Receive disabled

Receive enabled

Handshake function ( CTS pin)

0

1

Disabled (Always transferable)

Enabled

Transmission data bit8

Figure 3.10.7 Serial Mode Control Register 0 (for SIO0 and SC0MOD0)

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7

6

5

4

3

2

1

0

SC1MOD0 Bit symbol

TB8

CTSE

RXE

WU

SM1

SM0

SC1

SC0

(020AH)

Read/Write

Reset State

Function

R/W

0

Transfer

data bit8

Handshake Receive

Wakeup

function

Serial transmission

mode

Serial transmission

clock

function

0: CTS

disable

1: CTS

enable

control

0: Receive 0: Disable 00: I/O interface mode (UART)

disable

1: Receive

enable

1: Enable

01: 7-bit UART mode

10: 8-bit UART mode

11: 9-bit UART mode

00: TMRA0 trigger

01: Baud rate generator

10: Internal clock f

SYS

11: External clock

(SCLK1 input)

Serial transmission clock source (for UART)

00 Timer TMRA0 trigger output signal

01 Baud rate generator

10

Internal clock f

SYS

11 External clock (SCLK1 input)

Note: The clock selection for the I/O

interface mode is controlled by the

serial control register (SC1CR).

Serial transmission mode

00 I/O interface mode

01

10

11

7-bit mode

8-bit mode

9-bit mode

UART mode

Wakeup function

9-bit UART

Other modes

Don’t care

Interrupt generated when

0

data is received

Interrupt generated only

1

when SC1CR<RB8> = “1”

Receiving function

0

1

Receive disabled

Receive enabled

Handshake function ( CTS pin)

0

1

Disabled (Always transferable)

Enabled

Transmission data bit8

Figure 3.10.8 Serial Mode Control Register 0 (for SIO1 and SC1MOD0)

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7

6

5

4

3

2

1

0

SC0CR

(0201H)

Bit symbol

Read/Write

Reset State

Function

RB8

R

EVEN

PE

OERR

PERR

FERR

SCLKS

IOC

R/W

R (Cleared to 0 when read)

R/W

Undefined

Received

data bit8

0

A read

Parity

1: Error

Parity

0: SCLK0 0:Baud rate

generator

-modify-write

operation

cannot be

performed

0: Odd

addition

Overrun

Framing

1: Even

0: Disable

1: Enable

1: SCLK0 1:SCLK0

pin input

I/O interface input clock selection

0

1

Baud rate generator

SCLK0 pin input

Edge selection for SCLK0 pin (I/O mode)

0

Transmits and receives

data on rising edge of SCLK0

Transmits and receives

1

data on falling edge SCLK0.

Framing error flag

Parity error flag

Cleared to “0”

when read

Overrun error flag

Parity addition enables

0

1

Disabled

Enabled

Even parity addition/check

0

1

Odd parity

Even parity

Received data 8

Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction.

Figure 3.10.9 Serial Control Register (for SIO0 and SC0CR)

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7

6

5

4

3

2

1

0

SC1CR

(0209H)

Bit symbol

Read/Write

RB8

R

EVEN

PE

OERR

PERR

FERR

SCLKS

IOC

R/W

R (Cleared to 0 when read)

R/W

Reset State Undefined

0

A read

Function

Received

data bit8

Parity

1: Error

Parity

0: SCLK1 0:Baud rate

generator

-modify-write

operation

cannot be

performed

0: Odd

addition

Overrun

Framing

1: Even

0: Disable

1: Enable

1:SCLK1 pin

1: SCLK1

input

I/O interface input clock selection

0

1

Baud rate generator

SCLK1 pin input

Edge selection for SCLK1 pin (I/O mode)

Transmits and receives

0

data on rising edge of SCLK1.

Transmits and receives

1

data on falling edge SCLK1.

Framing error flag

Cleared to “0”

Parity error flag

when read

Overrun error flag

Parity addition enables

0

1

Disabled

Enabled

Even parity addition/check

0

1

Odd parity

Even parity

Received data bit8

Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction.

Figure 3.10.10 Serial Control Register (for SIO1 and SC1CR)

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7

6

5

4

3

2

1

0

BR0CR

(0203H)

Bit symbol

Read/Write

Reset State

Function

−

BR0ADDE BR0CK1

BR0CK0

BR0S3

BR0S2

BR0S1

BR0S0

R/W

0

+(16 −

K)/16

0

Always

write “0”.

00: φT0

01: φT2

10: φT8

Setting of the divided frequency “N”

(0 to F)

division

0: Disable 11: φT32

1: Enable

Setting the input clock of baud rate generator

+ (16 − K)/16 divisions enable

00

01

10

11

Internal clock φT0

Internal clock φT2

Internal clock φT8

Internal clock φT32

0

1

Disable

Enable

7

6

5

4

3

2

1

0

BR0ADD Bit symbol

BR0K3

BR0K2

BR0K1

BR0K0

(0204H)

Read/Write

Reset State

Function

R/W

0

Sets frequency divisor “K”

(divided by N + (16 − K)/16)

Sets baud rate generator frequency divisor seting

BR0CR<BR0ADDE> = “1”

BR0CR<BR0ADDE> = “0”

BR0CR

0000 (N = 16) 0010 (N = 2)

0001 (N = 1) (UART only)

to

<BR0S3:0>

or

to

BR0ADD

0001 (N = 1) 1111 (N = 15)

1111 (N = 15)

0000 (N = 16)

<BR0K3:0>

0000

Disable

Divided by

0001 (K = 1)

to

Divided by N

N + (16 − K)/16

1111 (K = 15)

Note1:Availability of +(16-K)/16 division function

N

UART mode

I/O mode

○

×

2 to 15

1 , 16

The baud rate generator can be set to “1” in UART mode only when the +(16-K)/16 division function is not used.

Do not use in I/O interface mode.

Note2:Set BR0CR <BR0ADDE> to “1” after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when the +(16-K)/16

division function is used. Writes to unused bits in the BR0ADD register do not affect operation, and undefined

data is read from these unused bits.

Figure 3.10.11 Baud Rate Generator Control (for SIO0, BR0CR and BR0ADD)

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7

6

5

4

3

2

1

0

－

BR1CR

(020BH)

Bit symbol

Read/Write

Reset State

Function

BR1ADDE BR1CK1

BR1CK0

BR1S3

BR1S2

BR1S1

BR1S0

R/W

0

Always

+(16 − K)/16 00: φT0

write “0”. division

0: Disable

01: φT2

10: φT8

11:φT32

Divided frequency setting

1: Enable

Input clock selection for baud rate generator

+ (16 − K)/16 divisions enable

0

1

Disabled

Enabled

00

01

10

11

Internal clock φT0

Internal clock φT2

Internal clock φT8

Internal clock φT32

7

6

5

4

3

2

1

0

BR1ADD

(020CH)

Bit symbol

Read/Write

Reset State

Function

BR1K3

BR1K2

BR1K1

BR1K0

R/W

0

Set frequency divisor K

(Divided by N + (16 − K)/16)

Baud rate generator frequency divisor setting

BR1CR<BR1ADDE> = “1”

BR1CR<BR1ADDE> = “0”

0001 (N = 1) (UART only)

to

BR1CR

0000 (N = 16)

or

0010 (N = 2)

to

<BR1S3:0>

BR1ADD

1111 (N = 15)

0001 (N = 1)

1111 (N = 15)

<BR1K3:0>

0000 (N = 16)

0000

Disable

Divided by

0001 (K = 1)

to

Divided by N

N + (16 − K)/16

1111 (K = 15)

Note1:Availability of +(16-K)/16 division function

N

UART mode

I/O mode

○

×

2 to 15

1 , 16

The baud rate generator can be set “1” in UART mode only when the +(16-K)/16 division function is not used.

Do not use in I/O interface mode.

Note2:Set BR1CR <BR1ADDE> to “1” after setting K (K = 1 to 15) to BR1ADD<BR1K3:0> when the +(16-K)/16

division function is used. Writes to unused bits in the BR1ADD register do not affect operation, and undefined

data is read from these unused bits.

Figure 3.10.12 Baud Rate Generator Control (for SIO1, BR1CR and BR1ADD)

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7

6

5

4

3

2

1

0

TB7

TB6

TB5

TB4

TB3

TB2

TB1

TB0

(Transmission)

(Receiving)

SC0BUF

(0200H)

7

6

5

4

3

2

1

0

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

Note: A read-modify-write operation cannot be performed in SC0BUF.

Figure 3.10.13 Serial Transmission/Receiving Buffer Register (for SIO0 and SC0BUF)

7

6

5

4

3

2

1

0

SC0MOD1 Bit symbol

I2S0

R/W

0

FDPX0

R/W

0

(0205H)

Read/Write

Reset State

Function

IDLE2

Duplex

0: Stop

1: Run

0: Half

1: Full

Figure 3.10.14 Serial Mode Control Register1 (for SIO0 and SC0MOD1)

7

6

5

4

3

2

1

0

TB7

TB6

TB5

TB4

TB3

TB2

TB1

TB0

(Transmission)

SC1BUF

(0208H)

7

6

5

4

3

2

1

0

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

(Receiving)

Note: A read-modify-write operation cannot be performed in SC1BUF.

Figure 3.10.15 Serial Transmission/Receiving Buffer Register (for SIO1 and SC1BUF)

7

6

5

4

3

2

1

0

SC1MOD1 Bit symbol

I2S1

R/W

0

FDPX1

R/W

0

(020DH)

Read/Write

Reset State

Function

IDLE2

Duplex

0: Stop

1: Run

0: Half

1: Full

Figure 3.10.16 Serial Mode Control Register1 (for SIO1 and SC1MOD1)

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3.10.4 Operation of Each Mode

(1) Mode 0 (I/O interface mode)

This mode allows an increase in the number of I/O pins available for transmitting

data to or receiving data from an external shift register.

This mode includes the SCLK output mode to output synchronous clock SCLK and

SCLK input mode to input external synchronous clock SCLK.

Output extension

Input extension

A

B

C

A

B

C

Shift

register

Shift

register

TMP91CU27

/CP27/CK27

TMP91CU27

/CP27/CK27

TXD

SI

RXD

QH

D

E

D

E

SCLK

Port

SCK

RCK

SCLK

Port

CLOCK

S/L

F

G

H

TC74HC165 or equivalent

TC74HC595 or equivalent

Figure 3.10.17 Example of SCLK Output Mode Connection

Output extension

Input extension

Shift

register

Shift

register

A

B

A

B

TMP91CU27

/CP27/CK27

TMP91CU27

/CP27/CK27

C

D

C

D

TXD

SI

RXD

QH

E

F

E

F

SCLK

Port

SCK

RCK

SCLK

Port

CLOCK

S/L

G

H

G

H

TC74HC595 or equivalent

External clock

TC74HC165 or equivalent

External clock

Figure 3.10.18 Example of SCLK Input Mode Connection

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a. Transmission

In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0

and SCLK0 pins respectively each time the CPU writes data to the transmission buffer.

When all data is outputted, INTES0<ITX0C> will be set to generate the INTTX0

interrupt.

Timing of transmitted

data writing

SCLK0 output

(<SCLKS>=”0”:

Rising edge mode)

(Internal clock

timing)

SCLK0 output

(<SCLKS>=”1”:

Falling edge mode)

Bit0

Bit1

Bit6

Bit7

TXD0

ITX0C

(INTTX0

Interrupt request)

Figure 3.10.19 Transmission Operation in I/O Interface Mode (SCLK0 output mode)

In SCLK Input Mode, 8-bit data is output from the TXD0 pin when the SCLK0 input

becomes active after the data has been written to the transmission buffer by the CPU.

When all data is outputted, INTES0<ITX0C> will be set to generate INTTX0 an

interrupt.

SCLK0 input

(<SCLKS> = “0”: Rising mode)

SCLK0 input

(<SCLKS> = “1”: Falling mode)

Bit0

Bit1

Bit5

Bit6

Bit7

TXD0

<ITX0C>

(INTTX0 intterrupt reqest)

Figure 3.10.20 Transmission Operation in I/O Interface Mode (SCLK0 input mode)

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b. Receiving

In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the

data is shifted to receiving buffer 1. This starts when the receive interrupt flag

INTES0<IRX0C> is cleared by reading the received data. When 8-bit data are received,

the data will be transferred to receiving buffer 2 (SC0BUF according to the timing

shown below) and INTES0<IRX0C> will be set to generate INTRX0 interrupt.

The outputting for the first SCLK0 starts by setting SC0MOD0<RXE> to “1”.

IRX0C

(INTRX0

interrupt request)

SCLK0 output

(<SCLKS>=”0”:

Rising edge mode)

SCLK0 output

(<SCLKS>=”1”:

Fallingf edge mode)

RXD0

Bit0

Bit1

Bit6

Bit7

Figure 3.10.21 Receiving Operation in I/O Interface Mode (SCLK0 output mode)

In SCLK input mode, the data is shifted to receiving buffer 1 when the SCLK input

becomes active after the receive interrupt flag INTES0<IRX0C> is cleared by reading

the received data. When 8-bit data is received, the data will be shifted to receiving

buffer 2 (SC0BUF according to the timing shown below) and INTES0<IRX0C> will be

set again to be generate INTRX0 interrupt.

SCLK0input

(<SCLKS> = 0:

Rising edge mode)

SCLK0 input

(<SCLKS> = 1:

Falling edge mode)

Bit0

Bit1

Bit5

Bit6

Bit7

RXD0

IRX0C

(INTRX0 )

Figure 3.10.22 Receiving Operation in I/O Interface Mode (SCLK0 input mode)

Note: If receiving, set to the receive-enable state (SC0MOD0<RXE> = “1”) in both SCLK input mode and output

mode.

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c. Transmission and receiving (Full duplex mode)

When the full duplex mode is used, set the level of receive interrupt to “0”, and only

set the interrupt level (from 1 to 6) of the transmit interrupt. In the transfer interrupt

program, the receiving operation should be done like the below example before setting

the next transmit data.

Example: Channel 0, SCLK output

Baud rate = 9600 bps

fc = 14.7456 MHz

* Clock state

System clock: High frequency (fs)

Clock gear:

1 (fc)

Prescaler clock: f

FPH

•

Main routine

7

6

0

5

4

1

3

2

0

1

0

INTES0

X

0

X

Set transmission interrupt level, and disable receiving

interrupt.

P9CR

–

X

–

1

–

X

–

1

–

X

–

X

–

X

–

0

X

–

1

0

X

–

0

X

–

1

–

X

–

Set to P90 (TXD0), P91 (RXD0) and P92(SCLK0).

P9FC

SC0MOD0

SC0MOD1

SC0CR

Set to I/O interface mode.

Set to full duplex mode.

SCLK out, transmit on negative edge, receive on positive

edge

X

0

BR0CR

0

–

*

0

–

*

1

*

1

–

*

0

–

*

0

–

*

1

–

*

1

–

*

Set to 9600 bps.

SC0MOD0

SC0BUF

Enable receiving.

Set the transfer data.

•

INTTX0 interrupt routine

Acc←SC0BUF

Read the receiving data.

Set the next transfer data.

SC0BUF

*

X: Don’t care, −: No change

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(2) Mode 1 (7-bit UART mode)

7-bit UART mode is selected by setting serial channel mode register

SC0MOD0<SM1:0> to “01”.

In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by

the setting of the serial channel control register SC0CR<PE> bit; whether even parity

or odd parity will be used is determined by the SC0CR<EVEN> setting when

SC0CR<PE> is set to “1” (Enabled).

Setting example: When transmitting data of the following format, the control registers

should be set as described below. This explanation applies to channel

0.

Even

parity

Start Bit0

1

2

3

4

5

6

Stop

Transmission direction (Transmission rate: 2400 bps at fc = 12.288 MHz)

* Clock state

System clock: High frequency (fc)

Clock gear: 1(fc)

Prescaler clock: f

FPH

7 6 5 4 3 2 1 0

← X X − − 1

← X X − X − − X 1

− 0 1 0 1

P9CR

P9FC

−

Set P90 to function as the TXD0 pin.

SC0MOD0 ← −

−

Select 7-bit UART mode.

SC0CR

BR0CR

INTES0

SC0BUF

← − 1 1

−

Add even parity.

← 0 0 1 0 0 1 0 1

Set the transfer rate to 2400 bps.

Enable the INTTX0 interrupt and set it to interrupt level 4.

Set data for transmission.

← X 1 0 0

← *

−

*

* *

*

X: Don’t care, −: No change

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(3) Mode 2 (8-bit UART mode)

8-bit UART mode is selected by setting SC0MOD0<SM1:0> to “10”. In this mode, a

parity bit can be added (use of a parity bit is enabled or disabled by the setting of

SC0CR<PE>); whether even parity or odd parity will be used is determined by the

SC0CR<EVEN> setting when SC0CR<PE> is set to “1” (Enabled).

Setting example: When receiving data of the following format, the control registers

should be set as described below.

Odd

parity

Start Bit0

1

2

3

4

5

6

7

Stop

Transmission direction (Transmission rate: 9600 bps at fc = 12.288 MHz)

* Clock state

System clock: High frequency (fc)

Clock gear: 1(fc)

Prescaler clock: f

FPH

•

Main settings

7 6 5 4 3 2 1 0

← − − 0 −

P9CR

−

Set P91 (RXD0) pin to input pin.

Enable receiving in 8-bit UART mode.

Add odd parity.

SC0MOD0 ← − − 1 − 1 0 0 1

SC0CR

BR0CR

INTES0

← − 0 1

← 0 0 0 1 0 1 0 1

← − − X 1 0 0

− − − − −

Set to 9600 bps.

−

Enable the INTRX0 interrupt and set it to interrupt level 4.

•

Interrupt processing

Acc

← SC0CR AND 00011100

0 then ERROR

← SC0BUF

Check for errors.

if Acc

Acc

≠

Read the received data.

X: Don’t care, −: No change

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(4) Mode 3 (9-bit UART mode)

9-bit UART mode is selected by setting SC0MOD0<SM1:0> to “11”. In this mode

parity bit cannot be added.

In the case of transmission the MSB (9th bit) is written to SC0MOD0<TB8>. In the

case of receiving it is stored in SC0CR<RB8>. When the buffer is written or read, the

<TB8> or <RB8> is read or written first, before the rest of the SC0BUF data.

Wakeup function

In 9-bit UART mode, the wakeup function for slave controllers is enabled by setting

SC0MOD0<WU> to “1”. The interrupt INTRX0 occurs only when <RB8> = “1”.

TXD

RXD

TXD

RXD

TXD

RXD

TXD

RXD

Master

Slave 1

Slave 2

Slave 3

Note: The TXD pin of each slave controller must be in open-drain output mode.

Figure 3.10.23 Serial Link Using Wakeup Function

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Protocol

a. Select 9-bit UART mode on the master and slave controllers.

b. Set the SC0MOD0<WU> bit on each slave controller to “1” to enable data receiving.

c. The master controller transmits one-frame data including the 8-bit select code for the

slave controllers. The MSB (Bit8)<TB8> is set to “1”.

Start Bit0

1

2

3

4

5

6

7

8

Stop

Select code of slave controller

“1”

d. Each slave controller receives the above frame. If it matches with own select code,

clears<WU> bit to “0”.

e. The master controller transmits data to the specified slave controller whose

SC0MOD0<WU> bit is cleared to “0”. The MSB (Bit8) <TB8> is cleared to “0”.

Start Bit0

1

2

3

4

5

6

7

Bit8 Stop

“0”

Data

f. The other slave controllers (whose<WU> bits remain at 1) ignore the received data

because their MSB (Bit8 or <RB8>) are set to “0”, disabling INTRX0 interrupts.

The slave controller (<WU> bit = “0”) can transmit data to the master controller, and it

is possible to indicate the end of data receiving to the master controller by this

transmission.

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Example: To link two slave controllers serially with the master controller using the system clock

f_SYSas the transfer clock.

TXD

RXD

TXD

RXD

TXD

RXD

Master

Slave 1

Slave 2

Select code

00000001

Select code

00001010

•

Master controller setting

Main routine

P9CR

P9FC

← −

−

− 0 1

Set P90 to TXD0 pin. Set P91 to RXD0 pin.

← X X − X − − X 1

← X 1 0 0 X 1 0 1

INTES0

Set INTTX0 to enable, set interrupts level to level 4.

Set INTRX0 to enable, set interrupt level to level 5.

Set to 9-bit UART mode, and set transfer clock to f

SC0MOD0 ← 1 0 1 0 1 1 1 0

SC0BUF

← 0 0 0 0 0 0 0 1

SYS.

Set select code of slave 1.

Interrupt routine (INTTX0)

SC0MOD0 ← 0

SC0BUF

← *

−

Clear<TB8> to “0”.

*

Set transmission data.

•

Slave setting

Main routine

P9CR

P9FC

ODE

← −

−

− 0 1

← X X − X − − X 1

← X X X X − − 1

← X 1 0 1 X 1 1 0

Set P90 to TXD0 (Open-drain output) and P91 to RXD0.

−

INTES0

Set INTTX0 and INTRX0 to enable.

SC0MOD0 ← 1 0 1 1 1 1 1 0

Set to<WU> = “1” in 9-bit UART mode, and set transfer clock

f

SYS.

Interrupt routine (INTRX0)

Acc ← SC0BUF

if Acc = Select code

Then SC0MOD0 ← − − − 0 − − − − −

Clear<WU> to “0”.

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3.10.5 Support for IrDA

SIO0 includes support for the IrDA 1.0 infrared data communication specification.

Figure 3.10.24 shows the block diagram.

Transmisison data

TXD0

IR modulator

Modem

IR transmitter & LED

IR output

IR input

SIO0

Receive data

RXD0

IR demodulator

IR receiver

IR module

TMP91CU27/CP27/CK27

Figure 3.10.24 Block Diagram of IrDA

(1) Modulation of transmission data

When the transmission data is “0”, output “H” level with either 3/16 or 1/16 times for

width of baud rate (Selectable in software). When data is “1”, modem output “L” level.

Transmission

data

Start

0

1

0

1

0

Stop

Output after

modulation

Figure 3.10.25 Example of Modulation of Transmission Data

(2) Modulation of receiving data

When the receive data has an effective high level pulse width (Software selectable),

the modem outputs “0” to SIO0. Otherwise modem outputs “1” to SIO0. Receive pulse

logic is selectable by SIRCR<RXSEL>.

Receiving pulse

<RXSEL> = “0”

Receiving pulse

<RXSEL> = “1”

Start

1

0

1

0

1

0

Stop

Data after modulation

Figure 3.10.26 Example of Modulation of Receiving Data

(3) Data format

Format of transmission/receiving must set to data length 8 bits, without parity bit,

1-bit of stop bit.

Any other settings don’t guarantee the normal operation.

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(4) SFR

Figure 3.10.27 shows the control register SIRCR. If change setting this register,

must set it after set operation of transmission/receiving to disable (Both <TXEN> and

<RXEN> of this register should be cleared to “0”).

Any changing for this register during transmission or receiving operation doesn’t

guarantee the normal operation.

The following example describes how to set this register:

7

6

5

4

3

2

1

0

Bit symbol

PLSEL

RXSEL

TXEN

RXEN

SIRWD3

SIRWD2

SIRWD1

SIRWD0

SIRCR

(0207H) Read/Write

R/W

Reset State

0

Receive

data

0

Function

Select

Transmit

Receive

Select effective pulse width of SIRRxD

transmit

pulse

0: Disable 0: Disable Set effective pulse width to equal to or more

0:”H” pulse 1: Enable 1: Enable than 2x × (Value +1) +100ns

width

1:”L”’ pulse

Can be set: 1 to 14

Cannot be set:0, 15

0: 3/16

1:1/16

Select receive pulse width

Formula: Effective pulse width ≥ 2x × (Value + 1) +100ns

x = 1/f_FPH

0000

0001

to

Cannot be set.

Equal to or more than 4x + 100 ns.

1110

1111

Equal to or more than 30x + 100 ns.

Cannot be set.

Receive operation

0

Disabled

(ignores received data)

Enabled

1

Transmit operation

0

Disabled

(ignores the data transmit from SIO)

Enabled

1

Select transmit pulse width

0

1

3/16

1/16

Note:If pulse width complying with the IrDA 1.0 standard (1.6 μs min.)

can be guaranteed with a low baud rate, setting this bit to “1” will

result in reduced power dissipation.

Figure 3.10.27 IrDA Control register

1) SIO setting

; Set SIO side.

↓

2) LD (SIRCR), 07H

3) LD (SIRCR), 37H

↓

; Set receiving effect pulse width to 8/16.

; Enable transmission/receiving by setting<TXEN>, <RXEN> bit to “1”.

4) Start of transmission/receiving ; The modem operates as follows:

•

SIO0 starts transmitting.

IR receiver starts receiving.

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(5) Notes

1. Baud rate for IrDA

When IrDA is operated, set “01” to SC0MOD0<SC1:0> to generate baud rate.

Settings other than the above (TA0TRG, f

and SCLK0 input) cannot be used.

SYS

2. The pulse width for transmission

The IrDA 1.0 specification is defined in Table 3.10.4.

Table 3.10.4 Baud Rate and Pulse Width Specifications

Rate

Pulse Width Pulse Width Pulse Width

Baud Rate

Modulation

Tolerance

(% of rate)

(min)

(typ.)

(max)

2.4 kbps

9.6 kbps

1.41 μs

78.13 μs

19.53 μs

9.77 μs

4.88 μs

3.26 μs

1.63 μs

88.55 μs

22.13 μs

11.07 μs

5.96 μs

4.34 μs

2.23 μs

RZI

±0.87

19.2 kbps

38.4 kbps

57.6 kbps

115.2 kbps

The pulse width is defined as either baud rate T × 3/16 or 1.6 μs (1.6 μs is equal to T ×

3/16 pulse width when baud rate is 115.2 kbps).

The TMP91CU27/CP27CK27 has a function which can select the pulse width of

transmission as either 3/16 or 1/16. However, 1/16 pulse width can only be selected

when the baud rate is equal to or less than 38.4 kbps.

When 57.6 kbps and 115.2 kbps, the output pulse width should not be set to T × 1/16.

For the same reason, + (16 – K)/16 division function in the baud rate generator of

SIO0 cannot be used to generate a 115.2 kbps baud rate.

The + (16 – K)/16 division function can not be used also when the baud rate is 38.4 kbps

and the pulse width is 1/16.

Table 3.10.5 shows baud rate and pulse width for (16 – K)/16 division function.

Table 3.10.5 Baud Rate and Pulse Width for (16 − K)/16 Division Function

Baud Rate

Pulse Width

115.2 kbps 57.6 kbps 38.4 kbps 19.2 kbps 9.6 kbps 2.4 kbps

○

−

○

×

○

T × 3/16

T × 1/16

×

−

○: (16 − K)/16 division function can be used.

×: (16 − K)/16 division function can be used.

−: Cannot be set to T × 1/16 pulse width.

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3.11 Serial Bus Interface (SBI)

The TMP91CU27/CP27/CK27 has a 1-channel serial bus interface which employs a

clocked-synchronous 8-bit SIO mode and an I²C bus mode (Multi muster).

The serial bus interface is connected to an external device through P61 (SDA) and P62 (SCL)

in the I²C bus mode; and through P60 (SCK), P61 (SO), and P62 (SI) in the clocked-synchronous

8-bit SIO mode.

Each pin is specified as follows.

ODE <ODE62, 61>

P6CR <P62C, P61C, P60C> P6FC <P62F, P61F, P60F>

I²C bus mode

11

11X

011

010

11X

X11

Clock synchronous

8-bit SIO mode

XX

X: Don’t care

3.11.1 Configuration

INTSBI interrupt request

SCL

SCK

SIO

clock

P60

(SCK)

control

I/O

control

φT

Divider

P61

SO

SI

SIO

(SO/SDA)

Transfer

data control

I²C bus

clock sync.

+

control

circuit

Noise

P62

Control

I²C bus data

control

canceller

(SI/SCL)

Shift register

Noise

SDA

canceller

SBI0CR2/

SBI0SR

I2C0AR

SBI0DBR

SBI0CR1

SBI0BR0, 1

SBI control register 2/ I²C bus

SBI status register address register buffer register

SBI data

SBI control

register 1

SBI baud rate

registers 0 and 1

Figure 3.11.1 Serial Bus Interface (SBI)

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3.11.2 Control

The following registers are used to control the serial bus interface and monitor the

operation status.

•

Serial bus interface control register 1 (SBI0CR1)

Serial bus interface control register 2 (SBI0CR2)

Serial bus interface data buffer register (SBI0DBR)

I²C bus address register (I2C0AR)

Serial bus interface status register (SBI0SR)

Serial bus interface baud rate register 0 (SBI0BR0)

Serial bus interface baud rate register 1 (SBI0BR1)

The above registers differ depending on a mode to be used.

Refer to Section, “3.11.4 I²C Bus Mode Control Register” and “3.11.7 Clocked

Synchronous 8-Bit SIO Mode Control.”

3.11.3 Data Format in I²C Bus Mode

Data format in I²C bus mode is shown Figure 3.11.2.

(a) Addressing format

8 bits

Slave address

1

1 to 8 bits

Data

1

1 to 8 bits

Data

1

R

/

A

C

K

A

C

K

A

C

K

S

P

1

W

1 or more

(b) Addressing format (With restart)

8 bits

1

1 to 8 bits

Data

1

8 bits

Slave address

1

1 to 8 bits

Data

1

R

/

R

/

A

C

K

A

C

K

A

C

K

A

C

K

S

Slave address

1

S

P

W

1 or more

(c) Free data format (Transfer-format transfer from master device to slave device.)

8 bits

Data

1

1 to 8 bits

Data

1

1 to 8 bits

Data

1

A

C

K

A

C

K

A

C

K

S

P

1 or more

S:

Start condition

R/W : Direction bit

ACK: Acknowledge bit

P:

Stop condition

Figure 3.11.2 Data Format in I²C Bus Mode

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3.11.4 I²C Bus Mode Control Register

The following registers are used to control and monitor the operation status when using

the serial bus interface (SBI) in the I²C bus mode.

Serial Bus Interface Control Register 1

7

6

5

4

3

2

1

0

SCK0/

SWRMON

SBI0CR1

(0240H)

Bit symbol

BC2

BC1

BC0

ACK

SCK2

SCK1

Read/Write

Reset State

Function

W

0

R/W

W

R/W

0

0/1 (Note3)

A

Select number of transferred bits

(Note 1)

Acknowledge

mode

specification

0: Not

generate

1: Generate

Internal serial clock selection and

software reset monitor

(Note 2)

read-modify

-write

operation

cannot be

performed.

Internal serial clock selection <SCK2:0> @ write

000

001

010

011

100

101

110

n = 5

n = 6

n = 7

n = 8

n = 9

n = 10

n = 11

−

Note4

System clock: fc

Clock gear: fc/1

fc = 27 MHz

51.9 kHz

26.2 kHz

13.1 kHz

(Output to internal SCL)

fc

Frequency =

[Hz]

2ⁿ+ 8

111 Reserved (Reserved)

Software reset state monitor <SWRMON> @ read

0

1

During software reset

(Default value)

Acknowledge mode selection

0

1

Not generate clock pulse for acknowledge signal

Generate clock pulse for acknowledge signal

Select number of bits transferred

<ACK> = “0”

<ACK> = “1”

Number

<BC2:0>

Data

of clock

pulses

of clock

pulses

length

000

001

010

011

100

101

110

111

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

9

2

3

4

5

6

7

8

1

2

3

4

5

6

7

Note 1: Set the <BC2:0> to “000” before switching to a clock-synchronous 8-bit SIO mode.

Note 2: For the frequency of the SCL line clock, see section 3.11.5, (3) “Serial clock”.

Note 3: After reset, default value of <SCK0> is cleared to “0”. Also, default value of <SWRMON> is set to “1”.

Note 4: This I²C bus circuit does not support fast mode, it supports standard mode only. Although the I²C bus circuit

itself allows the setting of a baud rate over 100kbps, the compliance with the I²C specification is not

guraranteed in that case.

Figure 3.11.3 Register for I²C Bus Mode

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Serial Bus Interface Control Register 2

7

6

5

4

3

2

1

0

SBI0CR2

(0243H)

Bit symbol

Read/Write

Reset State

Function

MST

TRX

BB

SBIM1

SBIM0

SWRST1 SWRST0

W (Note 1)

W

W (Note 1)

0

Master/

slave

0

1

0

A

Transmitte Start/stop Cancel

r/receiver condition INTSBI

Serial bus interface

operation mode

selection (Note 2)

00:Port mode

Software reset control

write “10” and “01” in

order, then an internal

reset signal is

read-modify

-write

selection selection

generation interrupt

request

operation

cannot be

performed.

01:SIO mode

10:I²C bus mode

generated.

11:(Reserved)

Serial bus interface operating mode selection (Note 2)

00 Port mode (Serial bus interface output disabled)

01 Clocked synchronous 8-bit SIO mode

10 I²C bus mode

11 (Reserved)

INTSBI interrupt request

0

1

Don’t care

Cancel interrupt request

Start/stop condition generation

0

1

Generates the stop condition

Generates the start condition

Transmitter/receiver selection

0

1

Receiver

Transmitter

Master/slave selection

0

1

Slave

Master

Note 1: Reading this register function as SBI0SR register.

Note 2: Switch a mode to port mode after confirming that the bus is free.

Switch a mode between I²C bus mode and clock-synchronous 8-bit SIO mode after confirming that input

signals via port are high level.

Figure 3.11.4 Register for I²C Bus Mode

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Serial Bus Interface Status Register

7

6

5

4

3

2

1

0

SBI0SR

(0243H)

Bit symbol

Read/Write

Reset State

Function

MST

TRX

BB

AL

AAS

AD0

LRB

R

0

Master/

slave

status

selection selection

monitor monitor

0

1

0

A

Transmitter/ I2C bus

receiver

status

INTSBI

interrupt

request

monitor

Arbitration Slave

GENERAL Last

CALL

detection

monitor

0:Undetected 1: 1

status

monitor

lost

address

match

detection

monitor

received bit

monitor

0: 0

read-modify

-write

detection

monitor

0: −

1: Detected 0:Undetected 1: Detected

1: Detected

operation

cannot be

performed.

Last received bit monitor

0

1

Last received bit was “0”.

Last received bit was “1”.

GENERAL CALL detection monitor

0

1

Undetected

GENERAL CALL detected

Slave address match detection monitor

0

Undetected

Slave address match or GENERAL

CALL detected

1

Arbitration lost detection monitor

0

1

−

Arbitration lost

INTSBI interrupt request monitor

0

1

Interrupt requested

Interrupt canceled

I²C bus status monitor

0

1

Free

Busy

Transmitter/receiver status monitor

0

1

Receiver

Transmitter

Master/slave status monitor

0

1

Slave

Master

Note: Writing in this register functions as SBI0CR2.

Figure 3.11.5 Register for I²C Bus Mode

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Serial Bus Interface Baud Rate Register 0

7

6

5

4

3

2

1

0

SBI0BR0

Bit symbol

Read/Write

Reset State

Function

−

W

I2SBI0

R/W

0

(0244H)

A

read-modify

-write

operation

cannot be

performed.

0

Always

write “0”.

IDLE2

0: Stop

1: Run

Operation during IDLE2 mode

0

1

Stop

Run

Serial Bus Interface Baud Rate Register 1

7

6

5

4

3

2

1

0

SBI0BR1

Bit symbol

Read/Write

Reset State

Function

P4EN

W

−

W

(0245H)

A

read-modify

-write

operation

cannot be

performed.

0

Internal

clock

0: Stop

1: Run

Always

write “0”.

Baud rate clock control

0

1

Stop

Run

Serial Bus Interface Data Buffer Register

7

6

5

4

3

2

1

0

SBI0DBR

Bit symbol

Read/Write

Reset State

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

(0241H)

A

read-modify

-write

R (Receiving)/W (Transmission)

Undefined

operation

cannot be

performed.

Note 1: When writing transmitted data, start from the MSB (Bit7). Receiving data is placed from LSB (Bit0).

Note 2: SBI0DBR cannott be read the written data. Therefore a read-modify-write operation (e.g., “BIT” instruction)

cannot be performed.

I²C Bus Address Register

7

6

5

4

3

2

1

0

I2C0AR

(0242H)

A

read-modify

-write

operation

cannot be

performed.

Bit symbol

Read/Write

Reset State

Function

SA6

SA5

SA4

SA3

SA2

SA1

SA0

ALS

W

0

Address

recognition

mode

Slave address selection for when device is operating as slave device

specification

Address recognition mode specification

0

1

Slave address recognition

Non slave address recognition

Figure 3.11.6 Register for I²C Bus Mode

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3.11.5 Control in I²C Bus Mode

(1) Acknowledge mode specification

Set the SBI0CR1<ACK> to “1” for operation in the acknowledge mode. The

TMP91CU27/CP27/CK27 generates an additional clock pulse for an acknowledge

signal when operating in master mode. In the transmitter mode during the clock pulse

cycle, the SDA pin is released in order to receive the acknowledge signal from the

receiver. In the receiver mode during the clock pulse cycle, the SDA pin is set to the low

in order to generate the acknowledge signal.

Clear the <ACK> to “0” for operation in the non-acknowledge mode, the

TMP91CU27/CP27/CK27 does not generate a clock pulse for the acknowledge signal

when operating in the master mode.

(2) Number of transfer bits

The SBI0CR1<BC2:0> is used to select a number of bits for next transmission and

receiving data.

Since the <BC2:0> is cleared to “000” as a start condition, a slave address and

direction bit transmission are executed in 8 bits. Other than these, the <BC2:0>

retains a specified value.

(3) Serial clock

a. Clock source

The SBI0CR1<SCK2:0> is used to select a maximum transfer frequency

outputted on the SCL pin in master mode. Set a communication baud rate that

meets the I²C bus specification, such as the shortest pulse width of t_LOW, based on

the equations shown below.

t

1/fscl

HIGH

LOW

SBI0CR1<SCK2:0>

n

= 2^{n 1}/f

−

t

LOW

SBI

000

001

010

011

100

101

110

5

6

7

8

9

= 2^{n 1}/f

+ 8/f

SBI

−

HIGH

SBI

+ t

fscl = 1/(t

)

Low

HIGH

f

SBI

2ⁿ+ 8

=

10

11

Note 1: f

SBI

shows f

FPH

.

Note 2: It’s prohibit to use fc/16 prescaler clock (SYSCR0<PRCK1:0> = “10”) when using SBI block.

(I²C bus and clocked synchronous)

Figure 3.11.7 Clock Source

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b. Clock synchronization

In the I²C bus mode, in order to wired-AND a bus, a master device which pulls

down a clock line to low-level, in the first place, invalidate a clock pulse of another

master device which generates a high-level clock pulse. The master device with a

high-level clock pulse needs to detect the situation and implement the following

procedure.

The TMP91CU27/CP27/CK27 has a clock synchronization function for normal

data transfer even when more than one master exists on the bus.

The example explains the clock synchronization procedures when two masters

simultaneously exist on a bus.

Wait counting high-level

width of a clock pulse

Start couting high-level width of a clock pulse

Internal SCL output

(Master A)

Reset a counter of

high-level width of

a clock pulse

Internal SCL output

(Master B)

SCL line

a

b

c

Figure 3.11.8 Clock Synchronization

As master A pulls down the internal SCL output to the low level at point “a”, the

SCL line of the bus becomes the low level. After detecting this situation, Master B

resets a counter of high-level width of an own clock pulse and sets the internal

SCL output to the low level.

Master A finishes counting low-level width of an own clock pulse at point “b”

and sets the internal SCL output to the high level. Since master B holds the SCL

line of the bus at the low level, master A wait for counting high-level width of an

own clock pulse. After master B finishes counting low-level width of an own clock

pulse at point “c” and master A detects the SCL line of the bus at the high level,

and starts counting high level of an own clock pulse. The clock pulse on the bus is

determined by the master device with the shortest high-level width and the

master device with the longest low-level width from among those master devices

connected to the bus.

(4) Slave address and address recognition mode specification

When the TMP91CU27/CP27/CK27 is used as a slave device, set the slave address

<SA6:0> and <ALS> to the I2C0AR. Clear the <ALS> to “0” for the address recognition

mode.

(5) Master/slave selection

Set the SBI0CR2<MST> to “1” for operating the TMP91CU27/CP27/CK27 as a

master device. Clear the SBI0CR2<MST> to “0” for operation as a slave device. The

<MST> is cleared to “0” by the hardware after a stop condition on the bus is detected or

arbitration is lost.

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(6) Transmitter/receiver selection

Set the SBI0CR2<TRX> to “1” for operating the TMP91CU27/CP27/CK27 as a

transmitter. Clear the <TRX> to “0” for operation as a receiver. When data with an

addressing format is transferred in slave mode, when a slave address with the same

value that an I2C0AR or a GENERAL CALL is received (All 8-bit data are “0” after a

start condition), the <TRX> is set to “1” by the hardware if the direction bit (R/ W ) sent

from the master device is “1”, and <TRX> is cleared to “0” by the hardware if the bit is

“0”.

In the Master Mode, after an Acknowledge signal is returned from the slave device,

the <TRX> is cleared to “0” by the hardware if a transmitted direction bit is “1”, and is

set to “1” by the hardware if it is “0”. When an acknowledge signal is not returned, the

current condition is maintained.

The <TRX> is cleared to “0” by the hardware after a stop condition on the bus is

detected or arbitration is lost.

(7) Start/stop condition generation

When the SBI0SR<BB> is “0”, slave address and direction bit which are set to

SBI0DBR are output on a bus after generating a start condition by writing “1” to the

SBI0CR2<MST, TRX, BB, PIN>. It is necessary to set transmitted data to the data

buffer register (SBI0DBR) and set “1” to <ACK> beforehand.

SCL line

1

2

3

4

5

6

7

8

9

SDA line

A6

A5

A4

A3

A2

A1

A0

R/ W

Acknowledge

signal

Start condition

Slave address and direction bit

Figure 3.11.9 Generation of Start Condition and Slave Address

When the <BB> is “1”, a sequence of generating a stop condition is started by writing

“1” to the <MST, TRX, PIN>, and “0” to the <BB>. Do not modify the contents of <MST,

TRX, BB, PIN> until a stop condition is generated on a bus.

SCL line

SDA line

Stop condition

Figure 3.11.10 Generation of Stop Condition

The state of the bus can be ascertained by reading the contents of SBI0SR<BB>.

SBI0SR<BB> will be set to “1” if a start condition has been detected on the bus, and

will be cleared to “0” if a stop condition has been detected (Bus free status).

And about generation of stop condition in master mode, there are some limitation

points. Please refer to section 3.11.6, (4) “Stop condition generation”.

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(8) Interrupt service requests and interrupt cancellation

When a serial bus interface interrupt request (INTSBI) occurs, the SBI0CR2<PIN>

is cleared to “0”. During the time that the SBI0CR2<PIN> is “0”, the SCL line is pulled

down to the low level.

The <PIN> is cleared to “0” when a 1 word of data is transmitted or received. Either

writing/reading data to/from SBI0DBR sets the <PIN> to “1”.

The time from the <PIN> being set to “1” until the SCL line is released takes t

.

LOW

In the address recognition mode (<ALS> = “0”), <PIN> is cleared to “0” when the

received slave address is the same as the value set at the I2C0AR or when a GENERAL

CALL is received (All 8-bit data are “0” after a start condition). Although SBI0CR2

<PIN> can be set to “1” by the program, the <PIN> is not clear it to “0” when it is

written “0”.

(9) Serial bus interface operation mode selection

SBI0CR2<SBIM1:0> is used to specify the serial bus interface operation mode. Set

SBI0CR2<SBIM1:0> to “10” when the device is to be used in I²C bus mode after

confirming pin condition of serial bus interface to “H”.

Switch a mode to port after confirming a bus is free.

(10) Arbitration lost detection monitor

Since more than one master device can exist simultaneously on the bus in I²C bus

mode, a bus arbitration procedure has been implemented in order to guarantee the

integrity of transferred data.

Data on the SDA line is used for I²C bus arbitration.

The following shows an example of a bus arbitration procedure when two master

devices exist simultaneously on the bus. Master A and master B output the same data

until point “a”. After master A outputs “L” and master B, “H”, the SDA line of the bus is

wire-AND and the SDA line is pulled down to the low level by master A. When the SCL

line of the bus is pulled up at point b, the slave device reads the data on the SDA line,

that is, data in master A. A data transmitted from master B becomes invalid. The state

in master B is called “ARBITRATION LOST”. Master B device that loses arbitration

releases the internal SDA output in order not to affect data transmitted from other

masters with arbitration. When more than one master sends the same data at the first

word, arbitration occurs continuously after the second word.

SCL (line)

Internal SDA output

(Master A)

Internal SDA output

(Master B)

Internal SDA output becomes “1” after arbitration has

been lost.

SDA line

a

b

Figure 3.11.11 Arbitration Lost

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The TMP91CU27/CP27/CK27 compares the levels on the bus’s SDA line with those

of the internal SDA output on the rising edge of the SCL line. If the levels do not match,

arbitration is lost and SBI0SR<AL> is set to “1”.

When SBI0SR<AL> is set to “1”, SBI0SR<MST, TRX> are cleared to “0” and the

mode is switched to slave receiver mode. Thus, clock output is stopped in data transfer

after setting <AL> = “1”.

SBI0SR<AL> is cleared to “0” when data is written to or read from SBI0DBR or

when data is written to SBI0CR2.

Internal

1

2

3

4

5

6

7

8

9

1

2

3

4

Master

A

SCL output

Internal

D7A D6A D5A D4A D3A D2A D1A D0A

Stop the clock pulse

D7A’ D6A’ D5A’ D4A’

SDA output

Internal

1

2

3

4

SCL output

Master

B

Internal

D7B D6B

Keep internal SDA output to high-level as losing arbitration

SDA output

<AL>

<MST>

<TRX>

Accessed to

SBI0DBR or SBI0CR2

Figure 3.11.12 Example of When TMP91CU27/CP27/CK27 is a Master Device B

(D7A = D7B, D6A = D6B)

(11) Slave address match detection monitor

SBI0SR<AAS> is set to “1” in slave mode, in address recognition mode (e.g., when

I2C0AR<ALS> = “0”), when a GENERAL CALL is received, or when a slave address

matches the value set in I2C0AR. When I2C0AR<ALS> = “1”, SBI0SR<AAS> is set to

“1” after the first word of data has been received. SBI0SR<AAS> is cleared to “0” when

data is written to or read from the data buffer register SBI0DBR.

(12) General call detection monitor

SBI0SR<AD0> is set to “1” in slave mode, when a GENERAL CALL is received (All

8-bit received data is “0” after a start condition). SBI0SR<AD0> is cleared to “0” when

a start condition or stop condition is detected on the bus.

(13) Last received bit monitor

The SDA line value stored at the rising edge of the SCL line is set to the

SBI0SR<LRB>. In the acknowledge mode, immediately after an INTSBI interrupt

request is generated, an acknowledge signal is read by reading the contents of the

SBI0SR<LRB>.

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(14) Software reset function

The software reset function is used to initialize the SBI circuit, when SBI is rocked

by external noises, etc.

An internal reset signal pulse can be generated by setting SBI0CR2<SWRST1:0> to

“10” and “01”. This initializes the SBI circuit internally. All command (except

SBI0CR2<SBIM1:0>) registers and status registers are initialized as well.

SBI0CR1<SWRMON> is automatically set to “1” after the SBI circuit has been

initialized.

(15) Serial bus interface data buffer register (SBI0DBR)

The received data can to read and transmission data can to write by reading or

writing SBI0DBR.

In the master mode, after the start condition is generated the slave address and the

direction bit are set in this register.

(16) I²C bus address register (I2C0AR)

I2C0AR<SA6:0> is used to set the slave address when the TMP91CU27/CP27/CK27

functions as a slave device.

The slave address outputted from the master device is recognized by setting the

I2C0AR<ALS> to “0”. The data format is the addressing format. When the slave

address is not recognized at the <ALS> = “1”, the data format is the free data format.

(17) Baud rate register (SBI0BR1)

Write “1” to SBI0BR1<P4EN> before operation commences.

(18) Setting register for IDLE2 mode operation (SBI0BR0)

SBI0BR0<I2SBI0> is the register setting operation/stop during IDLE2 mode.

Therefore, setting <I2SBI0> is necessary before the HALT instruction is executed.

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3.11.6 Data Transfer In I²C Bus Mode

(1) Device initialization

Set the SBI0BR1<P4EN>, SBI0CR1<ACK, SCK2:0>, set SBI0BR1 to “1” and clear

bits 7 to 5 and 3 in the SBI0CR1 to “0”.

Set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addressing

format) to the I2C0AR.

For specifying the default setting to a slave receiver mode, clear “0” to the <MST,

TRX, BB> and set “1” to the <PIN>, “10” to the <SBIM1:0>.

(2) Start condition and slave address generation

a. Master mode

In the master mode, the start condition and the slave address are generated as

follows.

Check a bus free status (when <BB> = “0”).

Set the SBI0CR1<ACK> to “1” (Acknowledge mode) and specify a slave address

and a direction bit to be transmitted to the SBI0DBR.

When SBI0CR2<BB> = “0”, the start condition are generated by writing “1111”

to SBI0CR2<MST, TRX, BB, PIN>. Subsequently to the start condition, nine

clocks are output from the SCL pin. While eight clocks are output, the slave

address and the direction bit which are set to the SBI0DBR. At the 9th clock, the

SDA line is released and the acknowledge signal is received from the slave device.

An INTSBI interrupt request occurs at the falling edge of the 9th clock. The

<PIN> is cleared to “0”. In the master mode, the SCL pin is pulled down to the low

level while <PIN> is “0”. When an interrupt request occurs, the <TRX> is changed

according to the direction bit only when an acknowledge signal is returned from

the slave device.

b. Slave mode

In the slave mode, the start condition and the slave address are received.

After the start condition is received from the master device, while eight clocks

are output from the SCL pin, the slave address and the direction bit that are

output from the master device are received.

When a GENERAL CALL or the same address as the slave address set in

I2C0AR is received, the SDA line is pulled down to the low level at the 9th clock,

and the acknowledge signal is output.

An INTSBI interrupt request generate on the falling edge of the 9th clock. The

<PIN> is cleared to “0”. In slave mode the SCL line is pulled down to the low level

while the <PIN> = “0”.

SCL line

SDA line

1

2

3

4

5

6

7

8

9

A6

A5

A4

A3

A2

A1

A0

R / W

ACK

Acknowledge

signal from a

slave device

Start condtion

Slave address + Direction bit

<PIN>

INTSBI

interrupt request

Output of master

Output of slave

Figure 3.11.13 Start Condition and Slave Address Generation

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(3) 1-word data transfer

Check the <MST> by the INTSBI interrupt process after the 1-word data transfer is

completed, and determine whether the mode is a master or slave.

a. If <MST> = “1” (Master mode)

Check the <TRX> and determine whether the mode is a transmitter or receiver.

When the <TRX> = “1” (Transmitter mode)

Check the <LRB>. When <LRB> is “1”, a receiver does not request data.

Implement the process to generate a stop condition (Refer to 3.11.6 (4)) and

terminate data transfer.

When the <LRB> is “0”, the receiver requests new data. When the next

transmitted data is 8 bits, write the transmitted data to SBI0DBR. When the next

transmitted data is other than 8 bits, set the <BC2:0> <ACK> and write the

transmitted data to SBI0DBR. After written the data, <PIN> becomes “1”, a serial

clock pulse is generated for transferring a new 1 word of data from the SCL pin,

and then the 1-word data is transmitted. After the data is transmitted, an INTSBI

interrupt request generates. The <PIN> becomes “0” and the SCL line is pulled

down to the low level. If the data to be transferred is more than one word in length,

repeat the procedure from the <LRB> checking above.

Write to SBI0DBR

1

2

3

4

5

6

7

8

9

SCL pin

D7

D6

D5

D4

D3

D2

D1

D0

ACK

SDA pin

<PIN>

Acknowledge signal

from a receiver

INTSBI

interrupt request

Output of master

Output of slave

Figure 3.11.14 Example in Which <BC2:0> = “000” and <ACK> = “1” (Transmitter mode)

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When the <TRX> is “0” (Receiver mode)

When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and

read the received data from SBI0DBR to release the SCL line (Data which is read

immediately after a slave address is sent is undefined). After the data is read,

<PIN> becomes “1”. Serial clock pulse for transferring new 1 word of data is

defined SCL and outputs “L” level from SDA pin with acknowledge timing.

An INTSBI interrupt request then generates and the <PIN> becomes “0”, Then

the TMP91CU27/CP27/CK27 pulls down the SCL pin to the low level. The

TMP91CU27/CP27/CK27 outputs a clock pulse for 1-word of data transfer and the

acknowledge signal each time that received data is read from the SBI0DBR.

Read receiving data

1

2

3

4

5

6

7

8

9

SCL line

SDA line

D7

D6

D5

D4

D3

D2

D1

D0

ACK

New D7

Acknowledge signal

to a transmitter

<PIN>

INTSBI

interrupt request

Output of master

Output of slave

Figure 3.11.15 Example of When <BC2:0> = “000” and <ACK> = “1” (Receiver mode)

In order to terminate the transmission of data to a transmitter, clear <ACK> to “0”

before reading data which is 1-word before the last data to be received. The last data

word does not generate a clock pulse as the acknowledge signal. After the data has

been transmitted and an interrupt request has been generated, set <BC2:0> to “001”

and read the data. The TMP91CU27/CP27/CK27 generates a clock pulse for a 1-bit

data transfer. Since the master device is a receiver, the SDA line on the bus remains

high. The transmitter receives the high signal as an ACK signal. The receiver indicates

to the transmitter that data transfer is complete.

After the one data bit has been received and an interrupt request been generated,

the TMP91CU27/CP27/CK27 generates a stop condition (See Section 3.11.6 (4)) and

terminates data transfer.

9

1

2

3

4

5

6

7

8

1

SCL

D7

D6

D5

D4

D3

D2

D1

D0

SDA

Acknowledge signal

“H” to transmitter

<PIN>

INTSBI

interrupt request

After set “001” to

<BC2:0>, reading

receiving data.

After clear <ACK> to “0”, reading receiving data.

Output of master

Output of slave

Figure 3.11.16 Termination of Data Transfer (Master receiver mode)

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b. If <MST> = “0” (Slave mode)

In the slave mode the TMP91CU27/CP27/CK27 operates either in normal slave

mode or in slave mode after losing arbitration.

In the slave mode, an INTSBI interrupt request occurs when the

TMP91CU27/CP27/CK27 receives a slave address or a GENERAL CALL from the

master device, or when a GENERAL CALL is received and data transfer is

complete, or after matching received address. In the master mode, the

TMP91CU27/CP27/CK27 operates in a slave mode if it losing arbitration. An

INTSBI interrupt request generate when a word data transfer terminates after

losing arbitration. When an INTSBI interrupt request generate the <PIN> is

cleared to “0” and the SCL pin is pulled down to the low level. Either

reading/writing from/to the SBI0DBR or setting the <PIN> to “1” will release the

SCL pin after taking t

time.

LOW

Check the SBI0SR<AL>, <TRX>, <AAS>, and <AD0> and implements

processes according to conditions listed in the next table.

Table 3.11.1 Operation in the Slave Mode

Conditions

Process

The TMP91CU27/CP27/CK27 loses

arbitration when transmitting a slave

Set the number of bits of single word to

<BC2:0>, and write the transmit data to

1

0

address, and receives a slave address SBI0DBR

for which the value of the direction bit

sent from another master is “1”.

In slave receiver mode, the

TMP91CU27/CP27/CK27 receives a

slave address for which the value of the

direction bit sent from the master is “1”.

In slave transmitter mode, transmission Check the <LRB> setting. If <LRB> is

0

1

0

of data of single word is terminated.

set to “1”, set <PIN> to “1” since the

receiver win no request the data which

follows. Then, clear <TRX> to “0” to

release the bus. If <LRB> is cleared to

“0” of and write the transmitted data to

SBI0DBR since the receiver requests

next data.

The TMP91CU27/CP27/CK27 loses

arbitration when transmitting a slave

Read the SBI0DBR for setting the <PIN>

to “1” (reading dummy data) or set the

0

1

1/0

address, and receives a slave address <PIN> to “1”.

or GENERAL CALL for which the value

of the direction bit sent from another

master is “0”.

The TMP91CU27/CP27/CK27 loses

arbitration when transmitting a slave

address or data, and terminates word

data transfer.

0

1

0

In slave receiver mode the

0

1/0

TMP91CU27/CP27/CK27 receives a

slave address or GENERAL CALL for

which the value of the direction bit sent

from the master is “0”.

In slave receiver mode the

TMP91CU27/CP27/CK27 terminates

receiving word data.

Set <BC2:0> to the number of bits in a

word and read the received data from

SBI0DBR.

0

1/0

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(4) Stop condition generation

When SBI0SR<BB> = “1”, the sequence for generating a stop condition can be

initiated by writing “1” to SBI0CR2<MST, TRX, PIN> and “0” to SBI0CR2<BB>. Do

not modify the contents of SBI0CR2<MST, TRX, PIN, BB> until a stop condition has

been generated on the bus. When the bus’s SCL line has been pulled Low by another

device, the TMP91CU27/CP27/CK27 generates a stop condition when the other device

has released the SCL line and SDA pin rising.

When SBI0CR2<MST, TRX, PIN> are written “1” and <BB> is written “0” (Generate

stop condition in master mode), <BB> changes to “0” by internal SCL changes to “1”,

without waiting stop condition. To check whether SCL and SDA pin are “1” by sensing

their ports is needed to detect bus free condition.

“1” → <MST>

“1” → <TRX>

“0” → <BB>

“1” → <PIN>

Stop condition

Internal SCL

SDA pin

<PIN>

<BB> (read)

Figure 3.11.17 Stop Condition Generation (Single master)

“1” → <MST>

“1” → <TRX>

Stop condition

“0” → <BB>

“1” → <PIN>

Internal SCL

The case of pulled low

by another device

SCL pin

SDA pin

<PIN>

<BB> (Read)

Figure 3.11.18 Stop Condition Generation (Multi master)

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(5) Restart

Restart is used during data transfer between a master device and a slave device to

change the data transfer direction.

The following description explains how to restart when the TMP91CU27/CP27/CK27

is in master mode.

Clear SBI0CR2<MST, TRX, BB> to “0” and set SBI0CR2<PIN> to “1” to release the

bus. The SDA line remains high and the SCL pin is released. Since a stop condition has

not been generated on the bus, other devices assume the bus to be in busy state.

And confirm SCL pin, that SCL pin is released and become bus-free state by SBI0SR

<BB> = “0” or signal level “1” of SCL pin in port mode. Check the <LRB> until it

becomes “1” to check that the SCL line on a bus is not pulled down to the low level by

other devices. After confirming that the bus remains in a free state, generate a start

condition using the procedure described in 3.11.6 (2).

In order to satisfy the setup time requirements when restarting, take at least 4.7 μs

of waiting time by software from the time of restarting to confirm that the bus is free

until the time to generate the start condition.

“0” → <MST>

“0” → <TRX>

“0” → <BB>

“1” → <PIN>

“1” → <MST>

“1” → <TRX>

“1” → <BB>

“1” → <PIN>

4.7 μs (Min)

Start condition

SCL (Bus)

SCL pin

SDA pin

<LRB>

<BB>

<PIN>

Figure 3.11.19 Timing Chart for Generate Restart

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3.11.7 Clocked Synchronous 8-Bit SIO Mode Control

The following registers are used to control and monitor the operation status when the

serial bus interface (SBI) is being operated in clocked synchronous 8-bit SIO mode.

Serial Bus Interface Control Register 1

7

6

5

4

3

2

1

0

SBI0CR1

(0240H)

Bit symbol

Read/Write

Reset State

Function

SIOS

SIOINH

SIOM1

SIOM0

SCK2

SCK1

SCK0

W

0

A

Transfer

start/stop

0: Stop

1: Start

Continue/

abort

transfer

Transfer mode selection

00:Transmission mode

01:(Reserved)

Selection of serial clock frequency

read-modify

-write

0:Continue 10:Transmission/

operation

cannot be

performed.

transfer

1:Abort

transfer

receiving mode

11:Receiving mode

Serial clock selection <SCK2:0>

000 n = 4

001 n = 5

010 n = 6

011 n = 7

100 n = 8

101 n = 9

110 n = 10

1.7 MHz

843.8 kHz

421.9 kHz

210.9 kHz

105.5 kHz

52.7 kHz

System clock: fc

Clock gear: fc/1

fc = 27 MHz

(Output to SCK pin)

fc

frequency =

[Hz]

2ⁿ

26.4 kHz

(Input from SCK Pin)

External clock

111

−

Transfer mode selection

00 8-bit transmission mode

01 (Reserved)

10 8-bit transmission/receiving mode

11 8-bit receiving mode

Continue/Abort transfer

0

1

Continue transfer

Abort transfer (Automatically cleared after transfer

aborted)

Transfer start/stop

0

1

Stopped

Started

Note: Set the tranfer mode and the serial clock after setting <SIOS> to “0” and <SIOINH> to “1”.

Serial Bus Interface Data Buffer Register

7

6

5

4

3

2

1

0

SBI0DBR

(0241H)

Bit symbol

Read/Write

Reset State

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R (Receiver)/W (Transfer)

Undefined

A

read-modify

-write

operation

cannot be

performed.

Figure 3.11.20 Register for SIO Mode

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Serial Bus Interface Control Register 2

7

6

5

4

3

2

1

0

SBI0CR2

(0243H)

Bit symbol

Read/Write

Reset State

Function

SBIM1

SBIM0

−

W

0

−

W

0

W

0

Serial bus interface

operation mode

selection

00: Port mode

01: SIO mode

10: I²C bus mode

11: (Reserved)

Always write “0”.

Serial bus interface operation mode selection

00 Port mode (serial bus interface output disabled)

01 Clocked-synchronous 8-bit SIO mode

10 I²C bus mode

11 (Reserved)

Note 1: Set the SBI0CR1<BC2:0> to “000” before switching to a clocked-synchronous 8-bit SIO mode.

Note 2: Please always write “00” to SBICR2<1:0>.

Serial Bus Interface Status Register

7

6

5

4

3

2

1

0

SBI0SR

(0243H)

Bit symbol

Read/Write

Reset State

Function

SIOF

SEF

R

0

Serial

transfer

operation status

Shift

operation

status

monitor

Shift operation status monitor

0

1

Shift operation terminated

Shift operation in progress

Serial transfer operating status monitor

0

1

Transfer terminated

Transfer in progress

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Serial Bus Interface Baud Rate Register 0

7

6

5

4

3

2

1

0

SBI0BR0

Bit symbol

Read/Write

Reset State

Function

−

I2SBI0

R/W

0

IDLE2

0: Stop

(0244H)

A

read-modify

-write

operation

cannot be

performed.

W

0

Always

write “0”.

1: Operate

Operation in IDLE2 mode

0

1

Stop

Operate

Serial Bus Interface Baud Rate Register 1

7

6

5

4

3

2

1

0

SBI0BR1

Bit symbol

Read/Write

Reset State

Function

P4EN

W

−

W

(0245H)

A

read-modify

-write

operation

cannot be

performed.

0

Internal

clock

Always

write “0”.

0: Stop

1: Operate

Baud rate clock control

0

1

Stop

Operate

Figure 3.11.21 Register for SIO Mode

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(1) Serial clock

a. Clock source

SBI0CR1<SCK2:0> is used to select the following functions:

Internal clock

In internal clock mode one of seven frequencies can be selected. The serial clock

signal is output to the outside on the SCK pin.

When the device is writing (in transmit mode) or reading (in receive mode), data

cannot follow the serial clock rate, so an automatic wait function is executed

which automatically stops the serial clock and holds the next shift operation until

reading or writing has been completed.

Automatic wait

1

2

3

7

8

1

2

6

7

8

1

2

3

SCK pin output

SO pin output

a

0

a

1

a

5

a

6

a

7

b

0

b

4

b

5

b

6

b

7

c

2

1

0

1

Writing

transmission

data

a

b

c

Figure 3.11.22 Automatic Wait Function

External clock (<SCK2:0> = “111”)

An external clock input via the SCK pin is used as the serial clock. In order to

ensure the integrity of shift operations, both the high and low-level serial clock

pulse widths shown below must be maintained. The maximum data transfer

frequency is 1.7 MHz (when fc = 27 MHz).

SCK pin

t

SCKL SCKH

t , t > 8/fc

SCKL SCKH

Figure 3.11.23 Maximum Data Transfer Frequency When External Clock Input Used

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b. Shift edge

Data is transmitted on the leading edge of the clock and received on the trailing

edge.

Leading edge shift

Data is shifted on the leading edge of the serial clock (on the falling edge of the SCK

pin input/output).

Trailing edge shift

Data is shifted on the trailing edge of the serial clock (on the rising edge of the SCK

pin input/output).

SCK pin

SO pin

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

76543210 *7654321 **765432 ***76543 ****7654 *****765 ******76 ******7

Shift register

(a) Data is transmit at the falling edge of the clock.

SCK pin

SI pin

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

******** 0******* 10****** 210***** 3210**** 43210*** 543210** 6543210* 76543210

Shift register

(b) Data is transmit at the rising edge of the clock.

*: Don’t care

Figure 3.11.24 Shift Edge

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(2) Transfer modes

The SBI0CR1<SIOM1:0> is used to select a transmit, receive or transmit/receive

mode.

a. 8-bit transmit mode

Set a control register to a transmit mode and write transmit data to the

SBI0DBR.

After the transmit data is written, set the SBI0CR1<SIOS> to “1” to start data

transfer. The transmitted data is transferred from SBI0DBR to the shift register

and output to the SO pin in synchronized with the serial clock, starting from the

least significant bit (LSB). When the transmission data is transferred to the shift

register, the SBI0DBR becomes empty. An INTSBI (Buffer empty) interrupt

request is generated to request new data.

When the internal clock is used, the serial clock will stop and automatic-wait

function will be initiated if new data is not loaded to the data buffer register after

the specified 8-bit data is transmitted. When new transmit data is written,

automatic-wait function is canceled.

When the external clock is used, data should be written to SBI0DBR before new

data is shifted. The transfer speed is determined by the maximum delay time

between the time when an interrupt request is generated and the time when data

is written to SBI0DBR by the interrupt service program.

When the transmit is started, after the SBI0SR<SIOF> goes “1” output from the

SO pin holds final bit of the last data until falling edge of the SCK.

Transmitting data is ended by clearing the <SIOS> to “0” by the buffer empty

interrupt service program or setting the <SIOINH> to “1”. When the <SIOS> is

cleared, the transmitted mode ends when all data is output. In order to confirm if

data is surely transmitted by the program, set the <SIOF> (Bit3 of SBI0SR) to be

sensed. The SBI0SR<SIOF> is cleared to “0” when transmitting is complete.

When the <SIOINH> is set to “1”, transmitting data stops. SBI0SR<SIOF>

turns “0”.

When an external clock is used, it is also necessary to clear SBI0CR1<SIOS> to

“0” before new data is shifted; otherwise, dummy data is transmitted and

operation ends.

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Clear <SIOS>

<SIOS>

<SIOF>

<SEF>

SCK pin (Output)

SO pin

*

a

0

a

1

a

2

a

3

a

4

a

5

a

6

a

7

b

0

b

1

b

2

b

3

b

4

b

5

b

6

b

7

INTSBI

interrupt request

a

b

SBI0DBR

(a) Internal clock

Writing Transmission data

Clear <SIOS>

<SIOS>

<SIOF>

<SEF>

SCK pin (Input)

SO pin

*

a

0

a

1

a

2

a

3

a

4

a

5

a

6

a

7

b

0

b

1

b

2

b

3

b

4

b

5

b

6

b

7

INTSBI

interrupt request

SBI0DBR

a

b

(b) External clock

Writing Transmission data

Figure 3.11.25 Transmission Mode

Example: Program to stop data transmission (when an external clock is used)

STEST1

STEST2

:

BIT 2, (SBI0SR)

JR NZ, STEST1

BIT 0, (P6)

; If <SEF> = “1” then loop

; If SCK = “0” then loop

; <SIOS> ← 0

JR Z, STEST2

LD (SBI0CR1), 00000111B

SCK pin

<SIOF>

SO pin

Bit6

Bit7

t

= 3.5/f [s] (Min)

FPH

SODH

Figure 3.11.26 Transmission Data Hold Time at End Transmit

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b. 8-bit receive mode

Set the control register to receive mode and set SBI0CR1<SIOS> to “1” for

switching to receive mode. Data is received into the shift register via the SI pin

and synchronized with the serial clock, starting from the least significant bit

(LSB). When 8-bit data is received, the data is transferred from the shift register

to SBI0DBR. An INTSBI (Buffer full) interrupt request is generated to request

that the received data be read. The data is then read from SBI0DBR by the

interrupt service program.

When an internal clock is used, the serial clock will stop and the automatic wait

function will be in effect until the received data has been read from SBI0DBR.

When an external clock is used, since shift operation is synchronized with an

external clock pulse, the received data should be read from SBI0DBR before the

next serial clock pulse is input. If the received data is not read, any further data

which is to be received is canceled. The maximum transfer speed when an

external clock is used is determined by the delay time between the time when an

interrupt request is generated and the time when the received data is read.

Receiving of data ends when <SIOS> is cleared to “0” by the buffer full interrupt

service program or when <SIOINH> is set to “1”. If <SIOS> is cleared to “0”,

received data is transferred to SBI0DBR in complete blocks. The received mode

ends when the transfer is complete. In order to confirm whether data is being

received properly by the program, set SBI0SR<SIOF> to be sensed. <SIOF> is

cleared to “0” when receiving has been completed. When it is confirmed that

receiving has been completed, the last data is read. When <SIOINH> is set to “1”,

data receiving stops. <SIOF> is cleared to “0” (The received data becomes invalid,

therefore no need to read it).

Note: When the transfer mode is changed, the contents of SBI0DBR will be lost. If the mode must be changed,

conclude data receiving by clearing <SIOS> to “0”, read the last data, then change the mode.

Clear <SIOS>

<SIOS>

<SIOF>

<SEF>

SCK pin (Output)

SI pin

a

0

a

1

a

2

a

3

a

4

a

5

a

6

a

7

b

a

b

1

b

2

b

3

b

4

b

5

b

6

b

7

0

INTSBI

interrupt request

b

SBI0DBR

Reading receiving data

Figure 3.11.27 Receiving Mode (when an internal clock is used)

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c. 8-bit transmit/receive mode

Set a control register to a transmit/receive mode and write data to SBI0DBR.

After the data has been written, set SBI0CR1<SIOS> to “1” to start

transmitting/receiving. When data is transmitted, the data is output via the SO

pin, starting from the least significant bit (LSB) and synchronized with the

leading edge of the serial clock signal. When data is received, the data is input via

the SI pin on the trailing edge of the serial clock signal. 8-bit data is transferred

from the shift register to SBI0DBR and an INTSBI interrupt request is generated.

The interrupt service program reads the received data from the data buffer

register and writes the data that is to be transmitted. SBI0DBR is used for both

transmitting and receiving. Transmitted data should always be written after

received data has been read.

When an internal clock is used, the automatic wait function will be in effect

until the received data has been read and the next data has been written.

When an external clock is used, since the shift operation is synchronized with the

external clock, received data is read and transmitted data is written before a new

shift operation is executed. The maximum transfer speed when an external clock

is used is determined by the delay time between the time when an interrupt

request is generated and the time at which received data is read and transmitted

data is written.

When transmission is started, after the SBI0SR<SIOF> goes “1” output from

the SO pin holds final bit of the last data until falling edge of the SCK.

Transmitting/receiving data ends when <SIOS> is cleared to “0” by the INTSBI

interrupt service program or when SBI0CR1<SIOINH> is set to “1”. When

<SIOS> is cleared to “0”, received data is transferred to SBI0DBR in complete

blocks. The transmit/receive mode ends when the transfer is complete. In order to

confirm whether data is being transmitted/received properly by the program, set

SBI0SR<SIOF> to be sensed. <SIOF> is set to “0” when transmitting/receiving

has been completed. When <SIOINH> is set to “1”, data transmitting/receiving

stops. SBI0SR<SIOF> is then cleared to “0”.

Note: When the transfer mode is changed, the contents of SBI0DBR will be lost. If the mode must be changed,

conclude data transmitting/receiving by clearing <SIOS> to “0”, read the last data, then change the transfer

mode.

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Clear <SIOS>

<SIOS>

<SIOF>

<SEF>

SCK pin (Output)

SO pin

SI pin

*

a

b

d

b

d

b

d

b

d

b

d

b

d

b

d

b

d

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

c

7

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

INTSBI

interrupt request

SBI0DBR

a

c

b

d

Write transmission data (a)

Read receiving data (c)

Write transmission data (b)

Read receiving data (d)

Figure 3.11.28 Transmission/Receiving Mode (when an internal clock is used)

SCK pin

<SIOF>

SO pin

Bit6

Bit7 in last transmission word

t

= 4/f [s] (Min)

FPH

SODH

Figure 3.11.29 Transmission Data Hold Time at End of Transmission/Receiving

(Transmission/receiving mode)

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3.12 Analog/Digital Converter

The TMP91CU27/CP27/CK27 incorporate

a

10-bit successive approximation-type

analog/digital converter (AD converter) with 4-channel analog input.

Figure 3.12.1 is a block diagram of the AD converter. The 4-channel analog input pins (AN0 to

AN3) are shared with the input-only port 5 and can thus be used as an input port.

Note: When IDLE2, IDLE1 or STOP mode is selected, in order to reduce power consumption, the system may enter

a stand-by mode with some timings even though the internal comparator is still enabled. Therefore be sure to

check that AD converter operations are halted before a HALT instruction is executed.

Internal data bus

AD mode control register 1 ADMOD1

AD mode control register 0 ADMOD0

<ADCH2:0> <VREFON>

Scan

Repeat

Channel

selection

control circuit

Interrupt

ADTRG

Busy

Start

End

AD converter control

circuit

Interrupt

request

INTAD

Analog input

AN3/ ADTRG (P53)

AN2 (P52)

AD conversion result

register

AN1 (P51)

Sample and

hold

AN0 (P50)

+

−

ADREG04L to ADREG37L

ADREG04H to ADREG37H

Comparator

AVCC

AVSS

DA converter

Figure 3.12.1 Block Diagram of AD Converter

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3.12.1 Control Register

The AD converter is controlled by the two AD mode control registers: ADMOD0 and

ADMOD1. The AD conversion results are stored in 8 kinds of AD conversion data upper

and lower registers: ADREG04H/L, ADREG15H/L, ADREG26H/L and ADREG37H/L.

Figure 3.12.2 to Figure 3.12.5 shows the registers related to the AD converter.

AD Mode Control Register 0

7

6

5

4

3

2

1

0

ADMOD0

(02B0H)

Bit symbol

Read/Write

Reset State

Function

EOCF

ADBF

−

ITM0

REPEAT

SCAN

ADS

R

R/W

0

AD

conversion conversion

end flag busy flag

0:Conversion 0: Conversion

in progress stopped

1: Conversion 1: Conversion

complete in progress

AD

Always

write “0”.

Always

write “0”.

Interrupt

Repeat mode Scan mode

AD

specification specification specification conversion

in conversion 0: Single

0: Conversion start

channel fixed conversion

channel

0: Don’t care

repeat mode 1: Repeat

0: Every

fixed mode 1: Start

conversion 1:Conversion conversion

conversion

1: Every

mode

channel

scan mode Always “0”

When read.

Fourth

conversion

AD conversion start

0

1

Don’t care

Start AD conversion

Note: Always read as “0”.

AD scan mode setting

0

1

AD conversion channel fixed mode

AD conversion channel scan mode

AD repeat mode setting

0

1

AD single conversion mode

AD repeat conversion mode

Specify AD conversion interrupt for cannel fixed

repeat conversion mode

Channel fixed repeat conversion mode

<SCAN> = “0”, <REPEAT> = “1”

0

1

Generates interrupt every conversion.

Generates interrupt every fourth conversion.

AD conversion busy flag

0

1

AD conversion stopped

AD conversion in progress

AD conversion end flag

0

1

Before or during AD conversion

AD conversion complete

Figure 3.12.2 Register for AD Converter

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AD Mode Control Register 1

7

6

5

4

3

2

1

0

ADMOD1 Bit symbol

VREFON

R/W

I2AD

R/W

0

ADTRGE

ADCH2

ADCH1

ADCH0

(02B1H)

Read/Write

Reset State

Function

R/W

0

VREF

IDLE2

AD

Analog input channel selection

application 0: Stop

external

trigger

start

control

0: OFF

1: ON

1: Operate

control

0: Disable

1: Enable

Analog input channel selection

<SCAN>

0

1

Channel

fixed

Channel

scanned

<ADCH2:0>

000

AN0

AN1

AN2

AN3

AN0

001

010

AN0 → AN1

AN0 → AN1 → AN2

AN0 → AN1 → AN2 → AN3

011(Note)

100

Don’t select.

101

110

111

AD conversion start control by external trigger

( ADTRG input)

0

1

Disabled

Enabled

IDLE2 control

0

1

Stopped

In operation

Control of application of reference voltage to

AD converter

0

1

OFF

ON

Before starting conversion (Before writing “1” to

ADMOD0<ADS>), set the <VREFON> bit to

“1”.

Note: As pin AN3 also functions as the ADTRG input pin, do not set <ADCH2:0> = “011” when using ADTRG with

<ADTRGE> = “1”.

Figure 3.12.3 Register for AD Converter

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AD Conversion Data Lower Register 0/4

7

6

5

4

3

2

1

0

ADREG04L Bit symbol

ADR01

ADR00

ADR0RF

(02A0H)

Read/Write

Reset State

Function

R

0

Undefined

AD

Stores lower 2 bits of

AD conversion result

conversion

data storage

flag

1:Conversion

result

stored

AD Conversion Data Upper Register 0/4

7

6

5

4

3

2

1

0

ADREG04H Bit symbol

ADR09

ADR08

ADR07

ADR06

ADR05

ADR04

ADR03

ADR02

(02A1H)

Read/Write

Reset State

Function

R

Undefined

Stores upper 8 bits AD conversion result.

AD Conversion Data Lower Register 1/5

7

6

5

4

3

2

1

0

ADREG15L Bit symbol

ADR11

ADR10

ADR1RF

R

(02A2H)

Read/Write

Reset State

Function

R

Undefined

0

AD

Stores lower 2 bits of

AD conversion result

conversion

result flag

1:Conversion

result

stored

AD Conversion Data Upper Register 1/5

7

6

5

4

3

2

1

0

ADREG15H Bit symbol

ADR19

ADR18

ADR17

ADR16

ADR15

ADR14

ADR13

ADR12

(02A3H)

Read/Write

Reset State

Function

R

Undefined

Stores upper 8 bits of AD conversion result.

9

8

7

6

5

4

3

2

1

0

Channel x

Conversion result

ADREGxH

ADREGxL

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

•

Bits 5 to 1 are always read as “1”.

•

Bit0 is the AD conversion data storage flag <ADRxRF>. When the

AD conversion result is stored, the flag is set to “1”. When either of

the registers (ADREGxH, ADREGxL) is read, the flag is cleared to

“0”.

Figure 3.12.4 Register for AD Converter

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AD Conversion Result Lower Register 2/6

7

6

5

4

3

2

1

0

ADREG26L Bit symbol

ADR21

ADR20

ADR2RF

(02A4H)

Read/Write

Reset State

Function

R

0

Undefined

AD

Stores lower 2 bits of

AD conversion result.

conversion

data storage

flag

1:Conversion

result

stored

AD Conversion Data Upper Register 2/6

7

6

5

4

3

2

1

0

ADREG26H Bit symbol

ADR29

ADR28

ADR27

ADR26

ADR25

ADR24

ADR23

ADR22

(02A5H)

Read/Write

Reset State

Function

R

Undefined

Stores upper 8 bits of AD conversion result.

AD Conversion Data Lower Register 3/7

7

6

5

4

3

2

1

0

ADREG37L Bit symbol

ADR31

ADR30

ADR3RF

R

(02A6H)

Read/Write

Reset State

Function

R

Undefined

0

AD

Stores lower 2 bits of

Ad conversion result.

conversion

data storage

flag

1:Conversion

result

stored

AD Conversion Result Upper Register 3/7

7

6

5

4

3

2

1

0

ADREG37H Bit symbol

ADR39

ADR38

ADR37

ADR36

ADR35

ADR34

ADR33

ADR32

(02A7H)

Read/Write

Reset State

Function

R

Undefined

Stores upper 8 bits of AD conversion result.

9

8

7

6

5

4

3

2

1

0

Channel x

Conversion result

ADREGxH

ADREGxL

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

•

Bits 5 to 1 are always read as “1”.

Bit0 is the AD conversion data storage flag <ADRxRF>. When the

AD conversion result is stored, the flag is set to “1”. When either of

the registers (ADREGxH, ADREGxL) is read, the flag is cleared to

“0”.

Figure 3.12.5 Register for AD Converter

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3.12.2 Operation

(1) Analog reference voltage

A high-level analog reference voltage is applied to the AVCC pin; a low-level analog

reference voltage is applied to the AVSS pin. To perform AD conversion, the reference

voltage as the difference between AVCC and AVSS, is divided by 1024 using string

resistance. The result of the division is then compared with the analog input voltage.

To turn off the switch between AVCC and AVSS, write “0” to ADMOD1<VREFON> in

AD mode control register 1. To start AD conversion in the OFF state, first write “1” to

ADMOD1<VREFON>, wait 3 μs until the internal reference voltage stabilizes (this is

not related to fc), then set ADMOD0< ADS> to “1”.

(2) Analog input channel selection

The analog input channel selection varies depending on the operation mode of the

AD converter.

•

In analog input channel fixed mode (ADMOD0<SCAN> = “0”)

Setting ADMOD1<ADCH2:0> selects one of the analog input pins AN0 to AN3 as

the input channel.

•

In analog input channel scan mode (ADMOD0<SCAN> = “1”)

Setting ADMOD1<ADCH2:0> selects one of the 4 scan modes.

Table 3.12.1 Illustrates analog input channel selection in each operation mode.

After Reset, ADMOD0<SCAN> = “0” and ADMOD1<ADCH2:0> = “000”. Thus pin

AN0 is selected as the fixed input channel. Pins not used as analog input channels can

be used as standard input port pins.

Table 3.12.1 Analog Input Channel Selection

Channel Fixed

<SCAN> = “0”

Channel Scan

<SCAN> = “1”

<ADCH2:0>

000

001

010

011

100

101

110

111

AN0

AN1

AN2

AN3

AN0

AN0 → AN1

AN0 → AN1 → AN2

AN0 → AN1 → AN2 → AN3

Don’t select.

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(3) Starting AD conversion

To start AD conversion, write “1” to ADMOD0<ADS> in AD mode control register 0,

or ADMOD1<ADTRGE> in AD mode control register 1 and input falling edge on

ADTRG pin. When AD conversion starts, the AD conversion busy flag

ADMOD0<ADBF> will be set to “1”, indicating that AD conversion is in progress.

Writing “1” to ADMOD0<ADS> during AD conversion restarts conversion. At that

time, to determine whether the AD conversion results have been preserved, check the

value of the conversion data storage flag ADREGxL<ADRxRF>.

During AD conversion, a falling edge input on the ADTRG pin will be ignored.

(4) AD conversion modes and the AD conversion end interrupt

The 4 AD conversion modes are:

•

Channel fixed single conversion mode

Channel scan single conversion mode

Channel fixed repeat conversion mode

Channel scan repeat conversion mode

The ADMOD0<REPEAT> and ADMOD0<SCAN> settings in AD mode control

register 0 determine the AD mode setting.

Completion of AD conversion triggers an AD conversion end interrupt request

INTAD. Also, ADMOD0<EOCF> will be set to “1” to indicate that AD conversion has

been completed.

a. Channel fixed single conversion mode

Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to “00” selects channel fixed

single conversion mode.

In this mode, data on one specified channel is converted once only. When the

conversion has been completed, the ADMOD0<EOCF> flag is set to “1”,

ADMOD0<ADBF> is cleared to “0”, and an INTAD interrupt request is generated.

b. Channel scan single conversion mode

Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to “01” selects channel scan

single conversion mode.

In this mode, data on the specified scan channels is converted once only. When scan

conversion has been completed, ADMOD0<EOCF> is set to “1”, ADMOD0<ADBF> is

cleared to “0”, and an INTAD interrupt request is generated.

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c. Channel fixed repeat conversion mode

Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to “10” selects channel fixed

repeat conversion mode.

In this mode, data on one specified channel is converted repeatedly. When conversion

has been completed, ADMOD0<EOCF> is set to “1” and ADMOD0<ADBF> is not

cleared to “0” but held “1”. INTAD interrupt request generation timing is determined

by the setting of ADMOD0<ITM0>.

Clearing <ITM0> to “0” generates an interrupt request every time an AD conversion

is completed.

Setting <ITM0> to “1” generates an interrupt request on completion of every fourth

conversion.

d. Channel scan repeat conversion mode

Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to “11” selects channel scan

repeat conversion mode.

In this mode, data on the specified scan channels is converted repeatedly. When each

scan conversion has been completed, ADMOD0<EOCF> is set to “1” and an INTAD

interrupt request is generated. ADMOD0<ADBF> is not cleared to “0” but held “1”.

To stop conversion in a repeat conversion mode (e.g., in cases c. and d.), program a “0”

to ADMOD0<REPEAT>. After the current conversion has been completed, the repeat

conversion mode terminates and ADMOD0<ADBF> is cleared to “0”.

Switching to a halt state (IDLE2 mode with ADMOD1<I2AD> cleared to “0”, IDLE1

mode or STOP mode) immediately stops operation of the AD converter even when AD

conversion is still in progress. In repeat conversion modes (e.g., in cases c. and d.),

when the halt is released, conversion restarts from the beginning. In single conversion

modes (e.g., in cases a. and b.), conversion does not restart when the halt is released

(The converter remains stopped).

Table 3.12.2 shows the relationship between the AD conversion modes and interrupt

requests.

Table 3.12.2 Relationship between the AD Conversion Modes and Interrupt Requests AD

ADMOD0

Generation of

Interrupt Request

Mode

<ITM0>

Channel fixed single

conversion mode

Channel scan single

conversion mode

Channel fixed repeat

conversion mode

After completion of

conversion

X

0

1

0

1

0

1

After completion of scan

conversion

X

Every conversion

Every fourth conversion

After completion of every

scan conversion

0

1

Cannel scan repeat

conversion mode

X

X: Don’t care

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(5) AD conversion time

84 states (6.2 μs@ f_FPH= 27 MHz) are required for the AD conversion for one channel.

(6) Storing and reading the results of AD conversion

The AD conversion data upper and lower registers (ADREG04H/L to ADREG37H/L)

store the AD conversion results. (ADREG04H/L to ADREG37H/L are read-only

registers.)

In channel fixed repeat conversion mode with ADMOD0<ITM0> = “1”, the

conversion results are stored successively in registers ADREG04H/L to ADREG37H/L.

In other modes, the AN0, AN1, AN2 and AN3 conversion results are stored in

ADREG04H/L, ADREG15H/L, ADREG26H/L and ADREG37H/L respectively.

Table 3.12.3 shows the correspondence between the analog input channels and the

registers that are used to hold the results of AD conversion.

Table 3.12.3 Correspondence between Analog Input Channel and AD Conversion Result Register

AD Conversion Result Register

Analog Input Channel

(Port 5)

Channel Fixed Repeat

Conversion Mode

Conversion Mode Other

Than Right

(ADMOD0<ITM0> = “1”)

ADREG04H/L

AN0

AN1

AN2

AN3

ADREG04H/L

ADREG15H/L

ADREG26H/L

ADREG37H/L

ADREG15H/L

ADREG26H/L

ADREG37H/L

The AD conversion data storage flag <ADRxRF> indicates whether the AD

conversion result register has been read or not. When a conversion result is stored in

the AD conversion result register, the flag is set to “1”. When either of the AD

conversion result registers (ADREGxxH or ADREGxxL) is read, the flag is cleared to

“0”.

Reading the AD conversion result also clears the AD conversion end flag

ADMOD0<EOCF> to “0”.

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Example:

a. Channel fixed repeat conversion mode

Convert the analog input voltage on the AN3 pin and write the result to memory

address 1800H using the AD interrupt (INTAD) processing routine.

Setting of main routine

7 6 5 4 3 2 1 0

INTE0AD ← X 1 0 0 − − − −

ADMOD1 ← 1 − X X 0 0 1 1

ADMOD0 ← X X 0 0 0 0 0 1

Interrupt routine processing example

Enable INTAD and set it to interrupt level 4.

Set pin AN3 to the analog input channel.

Start conversion in channel fixed single conversion mode.

WA

← ADREG37

Read value of ADREG37L, ADREG37H to general purpose

register WA (16-bit).

WA

> > 6

Shift contents read into WA six times to right and zero-fill upper

bits.

(1800H)

← WA

Write contents of WA to memory address 1800H.

b. Channel scan repeat conversion mode

Converts repeatedly the analog input voltages on the three pins AN0, AN1 and AN2,

using channel scan repeat conversion mode.

INTE0AD ← X 0 0 0 − − − −

ADMOD1 ← 1 − X X 0 0 1 0

ADMOD0 ← X X 0 0 0 1 1 1

Disable INTAD.

Set pins AN0 to AN2 to be the analog input channels.

Start conversion in channel scan repeat conversion mode.

X: Don’t care, −: No change

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3.13 Watchdog Timer (Runaway detection timer)

The TMP91CU27/CP27/CK27 contains a watchdog timer of runaway detecting.

The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the

CPU has started to malfunction (Runaway) due to causes such as noise.

When the watchdog timer detects a malfunction, it generates a non-maskable interrupt

INTWD to notify the CPU. Connecting the watchdog timer out to the reset pin internally forces

a reset. (The level of external RESET pin is not changed)

3.13.1 Configuration

Figure 3.13.1 is a block diagram of watchdog timer.

WDMOD<RESCR>

Reset control

RESET pin

Internal reset

Interrupt request

INTWD

WDMOD

<WDTP1:0>

Selector

15 17 19 21

2

f

Binary counter

(22 stages)

Q

SYS

/2)

(f

FPH

R

S

Reset

Internal reset

Write

4EH

Write

B1H

WDMOD<WDTE>

Watchdog timer control register

WDCR

Internal data bus

Figure 3.13.1 Block Diagram of Watchdog Timer

Note: Care must be exercised in the overall design of the apparatus since the watchdog timer

may fail to function correctly due to external noise, etc.

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3.13.2 Operation

The watch dog timer generates an INTWD interrupt specified at WDMOD<WDTP1:0>

register. The binary counter for the watch dog timer must be cleared to “0” by an

instruction issued from software before the INTWD interrupt is generated. If the binary

counter is not cleared due to the CPU malfunction (runaway) such as noise, the binary

counter overflows and the INTWD interrupt is generated. CPU can detect the malfunction

by the INTWD interrupt and recover to the normal condition.

The watch dog timer starts operating immediately after releasing a reset. It does not

operate in IDLE1 or STOP mode.

At IDLE2 mode, its operation conforms to the setting in WDMOD<I2WDT>. Ensure that

WDMOD<I2WDT> is set before the device enters IDLE2 mode.

The watchdog timer consists of a 22-stage binary counter which uses the system clock

(f_SYS) as the input clock. The binary counter can output f_SYS/2¹⁵, f_SYS/2¹⁷, f_SYS/2¹⁹and f_SYS/2²¹.

WDT counter

WDT interrupt

Overflow

0

n

Write clear code

Clear WDT

(Software)

Figure 3.13.2 Normal Mode

In the overflow condition, resetting TMP91CU27/CP27/CK27 themselves is selectable. In

this case, the reset time will be between 22 and 29 states (26.1 to 34.4 μs @ f_OSCH= 27 MHz,

f_FPH= 1.7 MHz) as shown in Figure 3.13.3. Also, system clock f_SYS(1 cycle = 1 state) which

generated clock by dividing it into 2, that clock f_FPHdivide clock f_OSCHhigh-frequency

oscillator into 16 is used to resetting.

Overflow

WDT counter

n

WDT interrupt

Internal reset

22 to 29 states (26.1 to 34.4 μs @ f

= 27MHz, f

= 1.7MHz)

FPH

OSCH

Figure 3.13.3 Reset Mode

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3.13.3 Control Register

The watchdog timer WDT is controlled by two controls registers WDMOD and WDCR.

(1) Watchdog timer mode register (WDMOD)

a. Setting the detection time for the watchdog timer in <WDTP1:0>

This 2-bit register is used for setting the watchdog timer interrupt time used when

detecting runaway.

On a reset this register is initialized to WDMOD<WDTP1:0> = “00”.

The detection times for WDT are shown in Figure 3.13.4.

b. Watchdog timer enable/disable control register <WDTE>

At reset, the WDMOD<WDTE> is initialized to “1”, enabling the watchdog timer.

To disable the watchdog timer, it is necessary to set this bit to “0” before writing the

disable code (B1H) to the watchdog timer control register WDCR. This makes it

difficult for the watchdog timer to be disabled by runaway.

However, it is possible to return the watchdog timer from the disabled state to the

enabled state merely by setting <WDTE> to “1”.

c. Watchdog timer out reset connection <RESCR>

This register is used to connect the output of the watchdog timer with the RESET

terminal internally. Since WDMOD<RESCR>is initialized to “0” on Reset, a Reset by

the watchdog timer will not be performed.

(2) Watchdog timer control register (WDCR)

This register is used to disable and clear the binary counter for the watchdog timer.

•

Disable control

The watchdog timer can be disabled by clearing WDMOD<WDTE> to “0” and then

writing the disable code (B1H) to the WDCR register.

WDCR

WDMOD

WDCR

← 0 1 0 0 1 1 1 0

← 0 − − X X − − 0

← 1 0 1 1 0 0 0 1

Write the clear code (4EH).

Clear WDMOD<WDTE> to “0”.

Write the disable code (B1H).

•

Enable control

Set WDMOD<WDTE> to “1”.

Watchdog timer clear control

To clear the binary counter and cause counting to resume, write the clear code (4EH)

to the WDCR register.

WDCR

← 0 1 0 0 1 1 1 0

Write the clear code (4EH).

Note1: If the disable control is used, set the disable code (B1H) to WDCR after write the clear code (4EH) once.

(Please refer to setting example.)

Note2: If the watchdog timer setting is changed,change setting after setting to disabled condition once.

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7

6

5

4

3

2

1

0

WDMOD

(0300H)

Bit symbol

Read/Write

Reset State

Function

WDTE

R/W

1

WDTP1

WDTP0

I2WDT

RESCR

−

R/W

0

R/W

0

WDT

WDT detection time

selection

IDLE2

1:Internally Always

connects write “0”.

WDT out

control

0: Stop

00: 2¹⁵/f

0: Stop

1: Enable

1: Operate

SYS

01: 2¹⁷/f

to the

SYS

10: 2¹⁹/f

11: 2²¹/f

reset pin

SYS

Watchdog timer out control

0

1

−

Connect WDT out to reset

IDLE2 control

0

1

Stop

Operate

Watchdog timer detection time

@ fc = 27 MHz, fs = 32.768 kHz

System Clock

Selection

Clock Gear

Value

Watchdog Timer Detection Time

WDMOD<WDTP1:0>

SYSCR1

<GEAR2:0>

00

01

10

11

<SYSCK>

1 (fs)

XXX

2.00 s

2.43 ms

4.85 ms

9.71 ms

19.42 ms

38.84 ms

8.0 s

32.0s

128.0 s

000 (fc)

9.71 ms

38.84 ms

77.67 ms

155.34 ms

310.69 ms

621.38 ms

155.34 ms

310.69 ms

621.38 ms

1242.76 ms

2485.51 ms

001 (fc/2)

010 (fc/4)

011 (fc/8)

100 (fc/16)

19.42 ms

38.84 ms

77.67 ms

155.34 ms

0 (fc)

Watchdog timer enable/disable control

0

1

Disable

Enable

Figure 3.13.4 Watchdog Timer Mode Register

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7

6

5

4

3

2

1

0

WDCR

Bit symbol

Read/Write

Reset State

Function

−

W

−

(0301H)

A read-modify

-write

operation

cannot be

performed

B1H: WDT disable code

4EH: WDT clear code

Disable/clear WDT

B1H

4EH

Disable code

Clear code

−

Others

Figure 3.13.5 Watchdog Timer Control Register

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3.14 Special timer for CLOCK

The TMP91CU27/CP27/CK27 include a timer that is used for a clock operation.

An interrupt (INTRTC) can be generated each 0.0625 [s] or 0.125 [s] or 0.25 [s] or 0.50 [s] by

using a low frequency clock of 32.768 kHz. A clock function can be easily used.

Special timer for CLOCK can operate in all modes in which a low-frequency oscillation is

operated.

In addition, INTRTC can return from each standby mode except STOP mode.

Interrupt

RTCCR<RTCSEL1:0>

RTCCR<RTCRUN>

Selector

request

INTRTC

Run

/Clear

2¹¹2¹²2¹³2¹⁴

fs

14-stage binary counter

(32.768 kHz)

Figure 3.14.1 Block Diagram for Real Time Clock

The Special timer for CLOCK is controlled by the real time clock control register (RTCCR) as

shown in Figure 3.14.2.

7

6

5

4

3

2

1

0

RTCCR

(0310H)

Bit symbol

Read/Write

Reset State

Function

−

R/W

RTCSEL1 RTCSEL0 RTCRUN

R/W

0

Always

write “0”.

00: 2¹⁴/fs

01: 2¹³/fs

10: 2¹²/fs

11: 2¹¹/fs

0: Stop &

clear

1: Count

Counting operation

0

1

Stop & clear

Count

Interrupt generation cycle

(fs = 32.768 kHz)

00 0.50 s

01 0.25 s

10 0.125 s

11 0.0625 s

Figure 3.14.2 Real Time Clock Control Register

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4. Electrical Characteristics

4.1

Absolute Maximum Ratings

Parameter

Symbol

Rating

Unit

Power supply voltage

Input voltage

V

−0.5 to 4.0

CC

V

−0.5 to V + 0.5

IN

CC

Output current (1 pin)

Output current (Total)

Power dissipation (Ta = 85°C)

Soldering temperature (10 s)

Storage temperature

Operation temperature

I

2

−2

OL

OH

mA

ΣI

80

OL

ΣI

−80

OH

P

600

mW

°C

D

T

260

SOLDER

T

STG

−65 to 150

−40 to 85

T

OPR

Note: The absolute maximum ratings are rated values that must not be exceeded during operation, even for an

instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, the device

may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to

the user. Thus, when designing products that include this device, ensure that no absolute maximum rating

value will ever be exceeded.

Solderability of lead-free products

Test

parameter

Test condition

Note

Solderability

Use of Sn-37Pb solder Bath

Pass:

Solder bath temperature = 230°C, Dipping time = 5 seconds

The number of times = one, Use of R-type flux

solderability rate until forming ≥ 95%

Use of Sn-3.0Ag-0.5Cu solder bath

Solder bath temperature = 245°C, Dipping time = 5 seconds

The number of times = one, Use of R-type flux (use of lead-free)

2008-01-24

91CU27-213

TMP91CU27/CP27/CK27

4.2

DC Characteristics (1/2)

Parameter

Symbol

Condition

Min

Typ.(Note)

Max

3.6

Unit

Power supply voltage

AVCC = DVCC

AVSS = DVSS = 0 V

P00 to P17

fc = 4 to 27 MHz

fc = 2 to 10 MHz

2.7

fs = 30 to

34 kHz

V

CC

1.8

V

≥ 2.7 V

< 2.7 V

≥ 2.7 V

< 2.7 V

≥ 2.7 V

< 2.7 V

≥ 2.7 V

< 2.7 V

≥ 2.7 V

< 2.7 V

≥ 2.7 V

< 2.7 V

≥ 2.7 V

< 2.7 V

≥ 2.7

0.6

CC

V

IL

(AD0 to AD15)

0.2 V

0.3 V

0.2 V

CC

P20 to P97 (Except P63)

V

IL1

IL2

IL3

IL4

,

0.25 V

0.15 V

0.3

NMI

RESET

CC

−0.3

V

P63 (INT0)

AM0 and AM1

0.3

0.2 V

CC

X1

0.1 V

P00 to P17

2.0

V

IH

(AD0 to AD15)

0.7 V

0.8 V

CC

P20 to P97 (Except P63)

V

IH1

IH2

IH3

IH4

,

0.75 V

0.85 V

NMI

RESET

CC

Vcc + 0.3

Ｖ

P63 (INT0)

< 2.7 V

≥ 2.7 V

< 2.7 V

≥ 2.7 V

< 2.7 V

V

− 0.3

CC

AM0 and AM1

X1

0.8 V

0.9 V

CC

I

= 1.6mA

V

≥ 2.7 V

< 2.7 V

≥ 2.7 V

< 2.7 V

0.45

OL

OH

CC

Output low voltage

V

OL

= 0.4mA

0.15 V

CC

V

= −400 μA

= −200 μA

V

− 0.3

CC

Output high voltage

V

OH

0.8 V

CC

Note: Typical values are for when Ta = 25°C and V = 3.0 V uncles otherwise noted.

CC

2008-01-24

91CU27-214

TMP91CU27/CP27/CK27

Typ.

DC Characteristics (2/2)

Parameter

Symbol

Condition

Min

Max

Unit

(Note1)

Input leakage current

Output leakage current

I

0.0 ≤ VIN ≤ V

0.02

0.05

±5

LI

CC

μA

I

0.2 ≤ VIN ≤ V − 0.2

±10

LO

CC

Power down voltage

VIL2 = 0.2 V

,

CC

V

1.8

3.6

V

STOP

(@STOP, RAM back up)

VIH2 = 0.8 V

CC

V

= 2.7 V to 3.6 V

= 2 V ± 10%

100

200

400

1000

10

CC

pull-up resistor

R

kΩ

pF

V

RESET

RST

Pin capacitance

Schmitt width

C

fc = 1 MHz

IO

V

≥ 2.7 V

0.4

0.3

1.0

0.8

CC

V

TH

,

, INT0

NMI

RESET

< 2.7 V

V

= 2.7 V to 3.6 V

= 2 V ± 10%

100

200

400

1000

19.0

8.0

CC

Programmable pull-up resistor

NORMAL (Note 2), (Note 3)

R

kΩ

KH

11.5 (10.8)

5.5 (4.8)

2.5 (1.8)

11.5 (10.8)

5.5 (4.8)

2.5 (1.8)

3.5 (3.0)

2.0 (1.5)

0.9 (0.4)

V

= 2.7 V to 3.6 V

CC

mA

IDLE2

IDLE1

(Note 3)

fc = 27 MHz

4.0

NORMAL (Note 2), (Note 3)

16.0

7.5

V

= 3 V ± 10%

CC

mA

IDLE2

IDLE1

(Note 3)

fc = 27 MHz

3.5

NORMAL (Note 2), (Note 3)

5.0

V

= 2 V ± 10 %

CC

IDLE2

IDLE1

SLOW

(Note 3)

(Note 2)

3.0

fc = 10 MHz

(Typ. V = 2.0 V)

I

CC

1.8

14.5

7.0

30

19

V

= 2.7 V to 3.6 V

CC

μA

IDLE2

fs = 32.768 kHz

IDLE1

SLOW

IDLE2

IDLE1

STOP

5.0

10

15

20

13

10

(Note 2)

V

= 2 V ± 10 %

CC

μA

5.0

3.0

0.1

fs = 32.768 kHz

(Typ. V = 2.0 V)

CC

V

= 1.8 V to 3.6 V

CC

Note 1:Typical values are for when Ta = 25°C and V = 3.0 V unless otherwise noted.

CC

Note 2:Icc measurement conditions (NORMAL, SLOW):

All functions are operational; output pins are open and input pins are fixed.

Note 3:Power supply cuurent from AVCC pin is included in power supply current of V pin. Also, AVCC pin share

CC

with AD reference power supply in TMP91CU27/CP27/CK27. Therefore, it is included in power supply current

of V pin that not only power supply current from AVCC pin but also current to ladder resitster. Insert of ( ) is

CC

current value when V

is Off.

REF

2008-01-24

91CU27-215

TMP91CU27/CP27/CK27

4.3

AC Characteristics

(1) Vcc = 2.7 V to 3.6 V

Variable

Max

f_FPH= 27 MHz

No.

Parameter

Symbol

Unit

Min

Max

1

f

period ( = x)

t

37.0

31250

37.0

12

2

ns

FPH

2

A0 to A15 valid → ALE falling

ALE falling → A0 to A15 hold

ALE high pulse width

t

0.5x − 6

0.5x − 16

x −20

AL

3

t

LA

4

t

17

4

LL

5

ALE falling →

/

_WRfalling

t

0.5x − 14

0.5x − 10

x −10

RD

LC

6

_RDrising → ALE rising

_WRrising → ALE rising

t

8

CLR

7

t

27

14

29

5

CLW

8

A0 to A15 valid →

A0 to A21 valid →

/

_WRfalling

t

x − 23

RD

ACL

9

t

1.5x − 26

0.5x − 13

x − 13

ACH

10

11

12

13

14

15

16

17

18

19

20

21

22

23

_RDrising → A0 to A21 hold

t

CAR

_WRrising → A0 to A21 hold

t

24

CAW

A0 to A15 valid → D0 to D15 input

A0 to A21 valid → D0 to D15 input

_RDfalling → D0 to D15 input

t

3.0x − 38

3.5x − 41

2.0x − 30

73

88

44

ADL

t

ADH

t

RD

low pulse width

t

2.0x − 15

0

59

0

RD

RR

_RDrising → D0 to D15 hold

_RDrising → A0 to A15 output

t

HR

t

x − 15

22

40

20

12

RAE

low pulse width

t

1.5x − 15

1.5x − 35

x − 25

WR

WW

D0 to D15 valid → _WRrising

_WRrising → D0 to D15 hold

A0 to A21 valid → Port input

A0 to A21 valid → Port hold

A0 to A21 valid → Port valid

t

DW

t

WD

t

3.5x − 89

3.5x + 80

40

APH

t

3.5x

129

APH2

t

209

AP

AC measurement conditions

・Output level: High 0.7 × V /Low 0.3 × V , C = 50 pF

CC

L

・Input level: High 0.9 × V /Low 0.1 × V

CC

Note: Symbol [x] in the above table means the period of clock f

core.

. It’s half period the system clock f

FPH

for CPU

SYS

The period of clock f

depends on the clock gear setting or the selection of high/low oscillator frequency.

FPH

2008-01-24

91CU27-216

TMP91CU27/CP27/CK27

(2) Read cycle

t

FPH

f

FPH

A0 to A21

CS0 to CS2

t

APH

t

APH2

Port input

(Note)

t

ADH

t

CAR

RD

t

ACH

RR

RD

t

RAE

t

ACL

t

HR

t

LC

t

ADL

AD0 to AD15

ALE

A0 to A15

D0 to D15

t

LA

AL

t

CLR

t

LL

Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as

and are not enabled. Therefore, the above waveform diagram should be regarded as depicting

RD

CS

internal operation. Please also note that the timing and AC characteristics of port input/output shown above

are typical representation. For details, contact your local Toshiba sales representative.

2008-01-24

91CU27-217

TMP91CU27/CP27/CK27

(3) Write cycle

f

FPH

A0 to A21

CS0 to CS2

t

AP

Port output

(Note)

t

CAW

t

WW

WR , HWR

t

WD

t

DW

D0 to D15

AD0 to AD15

ALE

A0 to A15

t

CLW

Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as

and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting

WR

internal operation. Please also note that the timing and AC characteristics of port input/output shown above

are typical representation. For details, contact your local Toshiba sales representative.

2008-01-24

91CU27-218

TMP91CU27/CP27/CK27

4.4

AD Conversion Characteristics

AVCC = V , AVSS = V

CC

SS

Parameter

Symbol

Condition

Min

Typ.

Max

Unit

Analog input voltage

V

AVSS

AVCC

±4.0

V

AIN

Error

V

= 2.7 V to 3.6 V

= 2 V ± 10%

±1.0

CC

−

LSB

(Not including quantization

errors)

V

±4.0

CC

Note 1:1 LSB = (AVCC − AVSS)/1024 [V]

Note 2:Minimum operation frequency:

AD converter operation is guranteed only when using fc (High-frequency oscillator).

fs (Low-frequency oscillator) is not guranteed. However, operation is guaranteed if the clock frequency

selected by the clock gear is over 4 MHz.

Note 3:The value for I (Current of V pin) includes the current which flows through the AVCC pin.

CC

2008-01-24

91CU27-219

TMP91CU27/CP27/CK27

4.5

Serial Channel Timing (I/O interface mode)

(1) SCLK input mode

Variable

10 MHz

27 MHz

Parameter

Symbol

Unit

Min

Max

Min Max Min Max

SCLK period

t

16X

1.6

0.59

μs

SCY

t

/2 − 4X − 110

SCY

290

38

Output data

(V = 2.7 V to 3.6 V)

CC

t

ns

OSS

→ SCLK rising/falling*

t

/2 − 4X − 180

SCY

220

−

(V = 2 V ± 10%)

CC

SCLK rising/falling *

→ Output data hold

SCLK rising/falling *

→ Input data hold

SCLK rising/falling *

→ Valid data input

t

/2 + 2X + 0

SCY

1000

370

ns

OHS

t

3X + 10

310

121

HSR

SRD

t

− 0

1600

592

SCY

Valid data input

→ SCLK rising/falling *

t

0

ns

RDS

(2) SCLK output mode

Parameter Symbol

Variable

10 MHz

27 MHz

Unit

Min

Max

Min Max Min Max

SCLK period

Output data

t

16X

8192X

1.6

819 0.59 303

256

μs

SCY

t

/2 − 40

SCY

760

ns

OSS

OHS

→ SCLK rising/falling *

SCLK rising/falling *

→ Output data hold

SCLK rising/falling *

→ Input data hold

SCLK rising/falling *

→ Valid data input

t

/2 − 40

SCY

760

0

256

0

ns

t

0

HSR

SRD

RDS

t

− 1X − 180

1320

375

SCY

Valid data input

→ SCLK rising/falling *

1X + 180

280

217

t

SCY

SCLK

Output mode/

input rising mode

SCLK

(Input falling mode)

t

OSS

OHS

t

Output data

TXD

0

1

2

3

t

SRD

HSR

t

RDS

1

Input data

RXD

2

Valid

Note 1:SCLK rising/falling: The rising edge is used in SCLK rising mode.

The falling edge is used in SCLK falling mode.

Note 2:27 MHz and 10 MHz values are calculated from t

= 16X case.

SCY

Note 3:Symbol [x] in the above table means the period of clock f

CPU core.

. It’s a half period of the system clock f

for

FPH

SYS

The period of clock f

depends on the clock gear setting or the selection of high/low oscillator frequency.

FPH

2008-01-24

91CU27-220

TMP91CU27/CP27/CK27

4.6

Event Counter (TA0IN, TA4IN, TB0IN0 and TB0IN1)

Variable

Min Max

10 MHz

27 MHz

Unit

Parameter

Symbol

Min Max Min Max

Clock period

t

8X + 100

4X + 40

900

440

396

188

ns

VCK

Clock low level pulse width

Clock high level pulse width

t

VCKL

t

VCKH

4.7

Interrupt and Capture

(1) NMI and INT0 Interrupts

Variable

Max

10 MHz

27 MHz

Parameter

Symbol

Unit

Min

Min Max Min Max

NMI and INT0 low level pulse width

t

4X + 40

440

188

ns

INTAL

NMI and INT0 high level pulse

width

4X + 40

INTAH

(2)

INT5 and INT6 interrupts, capture

INT5 and INT6 input pulse width depend on the system clock selection and clock

selection for prescaler. Below table show pulse width of each operation clock.

System Clock Clock Selection

t

INTBL

INTBH

Selection

SYSCR1

<SYSCK>

for Prescaler

SYSCR0

(INT5 and INT6 low level pulse width)

(INT5 and INT6 high level pulse width )

Unit

Variable

Min

f

= 27 MHz

Min

Variable

Min

f

= 27MHz

Min

FPH

<PRCK1:0>

00 (f

)

8X + 100

128Xc + 0.1

8X + 0.1

396

8X + 100

128Xc + 0.1

8X + 0.1

396

ns

FPH

0 (fc)

1 (fs)

10 (fc/16)

00 (f

4.8

μs

)

244.3

FPH

Note 1:“Xc” shows period of clock fc in high frequency oscillator.

Note 2:Symbol [x] in the above table means the period of clock f

core.

. It’s half period the system clock f

for CPU

FPH

SYS

The period of clock f

depends on the clock gear setting or the selection of high/low oscillator frequency.

FPH

2008-01-24

91CU27-221

TMP91CU27/CP27/CK27

4.8

Recommended Oscillation Circuit

The TMP91CU27/CP27/CK27 have been evaluated the by the oscillator vender below. Use

this information when selecting external parts.

Note :The total load value of the oscillator is the sum of external loads (C1 and C2) and the floating load of the actual

assembled board. There is a possibility of operating error when using C1 and C2 values in the table below.

When designing the board, design the minimum length pattern around the oscillator. We also recommend that

oscillator evaluation be carried out using the actual board.

(1)

Connection example

X1

X2

XT1

XT2

Rd

C

2

C

2

C

1

C

1

High-frequency oscillation connection

Low-frequency oscillation connection

(2) TMP91CU27/CP27/CK27 Recommended ceramic oscillator

TMP91CU27/CP27/CK27 recommends the high-frequency oscillator by Murata

Manufacturing Co., Ltd.

Please refer to the following URL

http://www.murata.co.jp

2008-01-24

91CU27-222

TMP91CU27/CP27/CK27

5. Table of SFRs

The SFRs (Special function registers) include the I/O ports and peripheral control registers

allocated to the 4-Kbyte address space from 000000H to 000FFFH.

(1) I/O port

(2) I/O port control

(3) Interrupt control

(4) Chip select/wait control

(5) Clock control

(6) 8-bit timer control

(7) 16-bit timer control

(8) UART/serial channel control

(9) I²C bus/serial channel control

(10) AD converter control

(11) Watchdog timer control

(12) Special timer for CLOCK

Table layout

Symbol

Name

Address

7

6

1

0

→ Bit symbol

→ Read/Write

→ Initial value after reset

→ Remarks

Note: “Prohibit RMW” in the table means that you cannot use RMW instructions on these registers.

Example: When setting only bit0 of the register PxCR to “1”, the instruction “SET 0, (PxCR)” cannot be used.

The LD (Transfer) instruction must be used to write all eight bits.

Read/Write

R/W: Both read and write are possible.

R: Only read is possible

W: Only write is possible

W*: Both read and write are possible (when this bit is read as 1.)

Prohibit RMW: A read-modify-write operation cannot be performed^.(The EX, ADD, ADC,

BUS, SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TSET, RLC,

RRC, RL, RR, SLA, SRA, SLL, SRL, RLD and RRD instruction are

read-modify-write instructions.)

R/W*: A read-modify-write operation cannot be performed^.when controlling the pull-up

resistor.

2008-01-24

91CU27-223

TMP91CU27/CP27/CK27

Table 5.1 Address Map for SFRs

[1] Port

Address

Name

Address

Name

Address

Name

0000H P0

1H P1

0010H

1H

0020H

1H

2H P0CR

3H

2H P6

3H P7

2H

3H

4H P1CR

5H P1FC

6H P2

4H P6CR

5H P6FC

6H P7CR

7H P7FC

8H P8

4H

5H

6H

7H P3

7H

8H P2CR

9H P2FC

AH P3CR

BH P3FC

CH P4

8H

9H P9

9H

AH P8CR

BH P8FC

CH P9CR

DH P9FC

EH

AH

BH

CH

DH

EH

DH P5

EH P4CR

FH P4FC

FH

FH ODE

[2] INTC

Address

Name

Address

Name

Address

Name

0080H DMA0V

1H DMA1V

2H DMA2V

3H DMA3V

4H

0090H INTE0AD

1H

00A0H INTETC01

1H INTETC23

2H

3H

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

3H INTE56

4H

5H

5H INTETA01

6H INTETA23

7H INTETA45

8H

6H

7H

8H INTCLR

9H DMAR

AH DMAB

BH

9H INTETB0

AH

BH INTETB01V

CH INTES0

DH INTES1

EH INTES2RTC

FH

CH IIMC

DH

EH

FH

Note: Do not access to the unnamed addresses, e.g., addresses to which no register has been allocated.

2008-01-24

91CU27-224

TMP91CU27/CP27/CK27

Table 5.2 Address Map for SFRs

[3] CS/WAIT

[4] CGEAR

Address

Name

Address

Name

Address

Name

00C0H B0CS

00E0H SYSCR0

00F0H

1H

1H B1CS

2H B2CS

3H B3CS

4H

1H SYSCR1

2H SYSCR2

2H

3H EMCCR0

3H

4H EMCCR1

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

5H

6H

7H BEXCS

8H MSAR0

9H MAMR0

AH MSAR1

BH MAMR1

CH MSAR2

DH MAMR2

EH MSAR3

FH MAMR3

7H

8H

9H

AH

BH

CH

DH

EH

FH

[5] TMRA

Address

Name

Address

Name

0100H TA01RUN

0110H TA45RUN

1H

2H TA0REG

3H TA1REG

4H TA01MOD

5H TA1FFCR

6H

2H TA4REG

3H TA5REG

4H TA45MOD

5H TA5FFCR

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

7H

8H TA23RUN

9H

AH TA2REG

BH TA3REG

CH TA23MOD

DH TA3FFCR

EH

FH

Note: Do not access to the unnamed addresses, e.g., addresses to which no register has been allocated.

2008-01-24

91CU27-225

TMP91CU27/CP27/CK27

Table 5.3 Address Map for SFRs

[6] TMRB

Address

Name

Address

Name

0180H TB0RUN

0190H

1H

2H TB0MOD

3H TB0FFCR

4H

2H

3H

4H

5H

6H

7H

8H TB0RG0L

9H TB0RG0H

AH TB0RG1L

BH TB0RG1H

CH TB0CP0L

DH TB0CP0H

EH TB0CP1L

FH TB0CP1H

8H

9H

AH

BH

CH

DH

EH

FH

[7] UART/SIO

Address

[8] I²C bus/SIO

Name

Address

Name

0200H SC0BUF

0240H SBI0CR1

1H SC0CR

2H SC0MOD0

3H BR0CR

4H BR0ADD

5H SC0MOD1

6H

1H SBI0DBR

2H I2C0AR

3H SBI0CR2/SBI0SR

4H SBI0BR0

5H SBI0BR1

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

7H SIRCR

8H SC1BUF

9H SC1CR

AH SC1MOD0

BH BR1CR

CH BR1ADD

DH SC1MOD1

EH

FH

Note: Do not access to the unnamed addresses, e.g., addresses to which no register has been allocated.

2008-01-24

91CU27-226

TMP91CU27/CP27/CK27

Table 5.4 Address Map for SFRs

[9] 10-bit ADC

Address

Name

Address

Name

02A0H ADREG04L

02B0H ADMOD0

1H ADREG04H

1H ADMOD1

2H ADREG15L

2H

3H

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

3H ADREG15H

4H ADREG26L

5H ADREG26H

6H ADREG37L

7H ADREG37H

8H

9H

AH

BH

CH

DH

EH

FH

[10] WDT

Address

[11] Special timer for CLOCK

Name

Address

Name

0300H WDMOD

0310H RTCCR

1H WDCR

2H

1H

2H

3H

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

3H

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

Note: Do not access to the unnamed addresses, e.g., addresses to which no register has been allocated.

2008-01-24

91CU27-227

TMP91CU27/CP27/CK27

(1) I/O port

Symbol Name Address

7

6

5

4

3

2

1

0

P07

P06

P05

P04

P03

P02

P01

P00

P0

P1

P2

Port 0

Port 1

Port 2

00H

01H

06H

R/W

Data from external port (Output latch register is undefined)

P15 P14 P13 P12

P17

P16

P11

P10

P20

P30

R/W

Data from external port (Output latch register is cleared to “0”)

P25

P24

P23

P22

P21

R/W

Data from external port (Output latch register is set to “1”)

P32

P31

R/W∗

Data from

external

port

1

(Note1)

0 (output

latch

07H

register):

Pull-up

resistor

OFF

1 (output

latch

P3

Port 3

(Prohibit

RMW)

−

register):

Pull-up

resistor

ON

P42

P41

P40

R/W∗

0CH

(Prohibit

RMW)

Data from external port Note1

0(output latch register)

P4

Port 4

: Pull-up resistor OFF

1(output latch register)

: Pull-up resistor ON

P53

P63

P52

P51

P50

P5

P6

Port 5

Port 6

0DH

12H

R

Data from external port

P62 P61

P60

R/W

Data from external port

(Output latch register is set to “1”)

P74

P73

P72

R/W

P71

P70

P7

Port 7

13H

Data from external port

(Output latch register is set to “1”)

P83

P82

P81

P80

R/W

Data from external port

(Output latch register is set to “1”)

P93 P92 P91 P90

P8

P9

Port 8

Port 9

18H

19H

P97

R/W

1

P96

R/W

1

P95

P94

R/W

Data from external port (Output latch register is set to “1”)

Note: Output latch is set to “1”.

2008-01-24

91CU27-228

TMP91CU27/CP27/CK27

(2) I/O port control (1/2)

Symbol Name Address

7

6

5

4

3

2

1

0

P07C

P06C

P05C

P04C

P03C

P02C

P01C

P00C

02H

W

Port 0

P0CR

(Prohibit

RMW)

0

control

0: Input 1: Output

(When access to external, become AD7 to AD0 and this register is cleared to “0”.)

P17C

P16C

P15C

P14C

P13C

P12C

P11C

P10C

04H

Port 1

W

P1CR

P1FC

P2CR

P2FC

(Prohibit

RMW)

control

0

<<Refer to column of P1FC>>

P17F

0

P16F

0

P15F

0

P14F

P13F

P12F

0

P11F

0

P10F

0

05H

Port 1

W

(Prohibit

RMW)

function

0

P1FC/P1CR = 00: Input port, 01: Output port, 10: AD8 to AD15, 11: A8 to A15

P25C

P24C

P23C

P22C

P21C

P20C

0

08H

Port 2

W

(Prohibit

RMW)

control

0

<<Refer to column of P2FC>>

P25F

0

P24F

0

P23F

P22F

P21F

0

P20F

0

09H

Port 2

W

(Prohibit

RMW)

function

0

P2FC/P2CR = 00: Input port, 01: Output port, 10: A0 to A5, 11: A16 to A21

P32C

W

0AH

Port 3

P3CR

(Prohibit

RMW)

0

control

0: Input

1: Output

−

W

P32F

P31F

W

P30F

0

0BH

Port 3

P3FC

P4CR

P4FC

(Prohibit

RMW)

0

function

Always

write “0”.

0: Port

HWR

WR

RD

1:

P42C

P41C

W

P40C

0EH

Port 4

(Prohibit

RMW)

control

0

P42F

0

P40F

0

0: Input 1: Output

P41F

W

0FH

Port 4

(Prohibit

RMW)

0

function

0: Port

1: CS2

0: Port

1: CS1

0: Port

1: CS0

Note 1: When port 2 is used as address bus A21 to A16 or A5 to A0, set P2FC after set P2CR.

Note 2: “L” level is outputted from P30 pin also during reading internal area by setting P3<P30> to “0”, set

P3FC<P30F> to “1”.

Note 3: When port 4 is used as chip select signal CS0 to CS2 set P4CR to “1” after set P4FC to “1”.

2008-01-24

91CU27-229

TMP91CU27/CP27/CK27

I/O port control (2/2)

Symbol Name Address

7

6

5

4

3

2

1

0

P63C

P62C

P61C

P60C

14H

Port 6

W

P6CR

P6FC

P7CR

P7FC

P8CR

(Prohibit

RMW)

control

0

P63F

0

P60F

0

0: Input 1: Output

P62F

P61F

15H

W

Port 6

(Prohibit

RMW)

0

function

0: Port

1: SCL

P72C

0: Port

1: INT0

P73C

1: SDA/SO 1: SCK out

P74C

0

P71C

0

P70C

0

16H

Port 7

W

0

(Prohibit

RMW)

control

0

0: Input 1: Output

P74F

W

P72F

W

P71F

W

17H

Port 7

(Prohibit

RMW)

0

function

0: Port

1: TA5OUT

1: TA3OUT 1: TA1OUT

P83C

0

P82C

0

P81C

P80C

0

1AH

Port 8

W

(Prohibit

RMW)

control

0

0: Input 1: Output

P83F

P82F

P81F

P80F

0

W

1BH

Port 8

0

P8FC

(Prohibit

RMW)

function

0: Port

1:TB0OUT1 1:TB0OUT0 1:INT6

/TB0IN1

1: INT5/

TB0IN0

P97C

W

P96C

W

P95C

0

P94C

0

P93C

P92C

P91C

P90C

1CH

(Prohibit

RMW)

Port 9

W

P9CR

P9FC

ODE

control

1

0

0: Input 1: Output

P95F

W

P93F

W

P92F

W

P90F

W

1DH

(Prohibit

RMW)

Port 9

0

function

0: Port

1: SCLK1

0: Port

1: TXD1

1: SCLK0

ODE61

R/W

1: TXD0

ODE62

R/W

0

ODE93

R/W

0

ODE90

R/W

0

Open-drain

enable

2FH

0

1: P62ODE 1: P61ODE 1: P93ODE 1: P90ODE

Note 1: External interrupt INT0:

Input enable is controlled by P6FC<P63F>. Level/edge selection and rising/falling selection is controlled by

IIMC<I0LE, I0EDGE>.

Note 2: External interrupts INT5 and INT6:

Input enable is set by P8FC<P81F, P80F>. The setting of edge is controlled by TB0MOD.

Note 3: When P70 and P73 is used as an input port, the input signal is inputted to 8bit-timer

(TMRA0 and TMRA4) as TA0IN and TA4IN inputs.

Note 4: When P91 and P94 is used as an input port, the input signal is inputted to SIO as serial receiving data RXD0

and RXD1.

2008-01-24

91CU27-230

TMP91CU27/CP27/CK27

(3) Interrupt control (1/3)

Symbol Name Address

7

6

5

4

3

2

1

0

INTAD

INT0

IADC

IADM2

IADM1

R/W

0

IADM0

I0C

I0M2

I0M1

R/W

0

I0M0

INTE0AD & INTAD

enable

90H

93H

95H

96H

97H

R

0

R

0

1: INTAD

Interrupt request level

INT6

1: INT0

Interrupt request level

INT5

Interrupt

INTE56 enable

INT6/5

I6C

I6M2

I6M1

R/W

0

I6M0

I5C

I5M2

I5M1

I5M0

R

0

R

0

R/W

0

1: INT6

Interruput requeset level

INTTA1 (TMRA1)

1: INT5

Interrupt request level

INTTA0 (TMRA0)

INTTA0 &

INTETA01 INTTA1

enable

ITA1C

ITA1M2

ITA1M1

R/W

0

ITA1M0

ITA0C

ITA0M2

ITA0M1

R/W

0

ITA0M0

0

R

0

R

0

1: INTTA1

Interrupt request level

INTTA3 (TMRA3)

1: INTTA0

Interrupt request level

INTTA2 (TMRA2)

INTTA2 &

INTETA23 INTTA3

enable

ITA3C

ITA3M2

ITA3M1

R/W

0

ITA3M0

ITA2C

ITA2M2

ITA2M1

R/W

0

ITA2M0

R

0

R

0

1: INTTA3

Interrupt request level

INTTA5 (TMRA5)

1: INTTA2

Interrupt request level

INTTA4 (TMRA4)

INTTA4 &

INTETA45 INTTA5

enable

ITA5C

ITA5M2

ITA5M1

R/W

0

ITA5M0

ITA4C

ITA4M2

ITA4M1

R/W

0

ITA4M0

R

0

R

0

1: INTTA5

Interrupt request level

1: INTTA4

Interrupt request level

2008-01-24

91CU27-231

TMP91CU27/CP27/CK27

Interrupt control (2/3)

Symbol

Name Address

7

6

5

4

3

2

1

0

INTTB01 (TMRB0)

INTTB00 (TMRB0)

INTTB00 &

ITB01C

ITB01M2 ITB01M1 ITB01M0

R/W

ITB00C

ITB00M2 ITB00M1 ITB00M0

R/W

INTETB0 INTTB01

99H

9BH

9CH

9DH

9EH

A0H

A1H

R

enable

0

1: INTTB01

Interrupt request level

1: INTTB00

Interrupt request level

−

INTTBOF0 (TMRB0 over flow)

INTTBOF1

INTETB01V (over-flow)

enable

−

R

0

−

R/W

0

−

ITF0C

ITF0M2

ITF0M1

R/W

0

ITF0M0

R

0

Always write “0”.

INTTX0

Interrupt request level

INTRX0

1: INTTBOF0

INTRX0 &

INTES0 INTTX0

enable

ITX0C

ITX0M2

ITX0M1

R/W

0

ITX0M0

0

IRX0C

IRX0M2

IRX0M1

IRX0M0

R

0

R

0

R/W

0

1: INTTX0

Interrupt request level

INTTX1

1: INTRX0

Interrupt request level

INTRX1

ITX1C

ITX1M2

ITX1M1

ITX1M0

IRX1C

IRX1M2

IRX1M1

IRX1M0

INTRX1 &

INTES1 INTTX1

enable

R

0

R/W

R

0

R/W

0

1: INTTX1

Interrupt request level

INTRTC

1: INTRX1

Interrupt request level

INTSBI

INTSBI &

INTES2RTC INTRTC

enable

IRTCC

IRTCM2

IRTCM1

R/W

0

IRTCM0

ISBIC

ISBIM2

ISBIM1

ISBIM0

R

0

R

0

R/W

0

1: INTRTC

Interrupt request level

INTTC1

1: INTSBI

Interrupt request level

INTTC0

INTTC0 &

INTETC01 INTTC1

enable

ITC1C

ITC1M2

ITC1M1

ITC1M0

ITC0C

ITC0M2

ITC0M1

R/W

0

ITC0M0

R

0

R/W

R

0

1: INTTC1

Interrupt request level

INTTC3

1: INTTC0

Interrupt request level

INTTC2

INTTC2 &

INTETC23 INTTC3

enable

ITC3C

ITC3M2

ITC3M1

R/W

0

ITC3M0

ITC2C

ITC2M2

ITC2M1

ITC2M0

R

0

R

0

R/W

0

1: INTTC3

Interrupt request level

1: INTTC2

Interrupt request level

2008-01-24

91CU27-232

TMP91CU27/CP27/CK27

Interrupt control (3/3)

Symbol Name Address

7

6

5

4

3

2

1

0

DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1

R/W

DMA0V0

DMA0

DMA0V start

vector

80H

81H

82H

83H

0

DMA0 start vector

DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1

R/W

DMA1V0

DMA1

DMA1V start

0

vector

DMA1 start vector

DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1

R/W

DMA2V0

DMA2

DMA2V start

0

vector

DMA2 start vector

DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1

R/W

DMA3V0

DMA3

DMA3V start

0

CLRV5

0

CLRV4

0

CLRV1

0

CLRV0

0

vector

DMA3 start vector

CLRV3

CLRV2

Interrupt

88H

W

INTCLR clear

(Prohibit

RMW)

0

control

Clear interrupt request flag by writing DMA start vector

DMAR3

R/W

0

DMAR2

R/W

0

DMAR1

R/W

0

DMAR0

R/W

0

DMA

89H

software

request

register

DMAR

DMAB

(Prohibit

RMW)

1: DMA request in software

DMAB3

R/W

0

DMAB2

R/W

0

DMAB1

R/W

0

DMAB0

R/W

0

DMA

burst

8AH

request

register

1: DMA requesst on burst mode

−

W

0

−

W

0

−

W

0

−

W

0

−

W

0

I0EDGE

I0LE

W

NMIREE

W

0

Interrupt

input

0

8CH

(Prohibit

RMW)

INT0

1:Operation

even on

NMI

IIMC

mode

edge

0: Edge

1: Level

control

Always write “0”.

0: Rising

1: Falling

rising

edge

Note: Only one channel can be set once for DMAR register. (Don’t write “1” to plural bits.)

2008-01-24

91CU27-233

TMP91CU27/CP27/CK27

(4) Chip select/wait control (1/2)

Symbol Name Address

7

6

5

4

3

2

1

0

B0E

W

B0OM1

B0OM0

B0BUS

B0W2

B0W1

B0W0

W

0

W

0

W

0

W

0

W

0

W

0

Block 0

C0H

0

CS/WAIT

Data bus Set number of wait

width

selection

0:16 bits

1: 8 bits

B0CS

(Prohibit

RMW)

0: Disable

1: Enable

00: ROM/SRAM

control

000: 2 waits

001: 1 wait

010: (1+N) waits 110: 4 waits

100: Reserved

101: 3 waits

01:

register

10: Don’t care

11:

011: 0 waits

111: 8 waits

B1E

W

B1OM1

B1OM0

B1BUS

B1W2

B1W1 B1W0

W

0

W

0

W

0

W

0

W

0

Block 1

CS/WAIT

control

0

C1H

(Prohibit

RMW)

Data bus Set number of wait

width

selection

0: 16 bits

1: 8 bits

0: Disable

1: Enable

00: ROM/SRAM

B1CS

000: 2 waits

001: 1 wait

010: (1+N) waits 110: 4 waits

100: Reserved

101: 3 waits

01:

register

10: Don’t care

11:

011: 0 waits

111: 8 waits

B2E

W

B2M

W

B2OM1

B2OM0

B2BUS

B2W2

B2W1 B2W0

W

0

W

0

W

0

W

0

W

0

W

0

Block 2

CS/WAIT

control

1

0

C2H

(Prohibit

RMW)

Data bus Set number of wait

width

selection

0: 16 bits

1: 8 bits

B2CS

0: Disable 0: 16-MB

00: ROM/SRAM

000: 2 waits

001: 1 wait

010: (1+N) waits 110: 4 waits

100: Reserved

101: 3 waits

1: Enable

area

01:

register

1:Area

10: Don’t care

11:

setting

011: 0 waits

111: 8 waits

B3E

W

B3OM1

B3OM0

B3BUS

B3W2

B3W1 B3W0

W

0

W

0

W

0

W

0

W

0

Block 3

CS/WAIT

control

0

C3H

(Prohibit

RMW)

Data bus Set number of wait

width

selection

0: 16 bits

1: 8 bits

B3CS

0: Disable

1: Enable

00: ROM/SRAM

000: 2 waits

001: 1 wait

010: (1+N) waits 110: 4 waits

100: Reserved

101: 3 waits

01:

register

10: Don’t care

11:

011: 0 waits

111: 8 waits

BEXBUS

BEXW2

BEXW1 BEXW0

W

0

W

0

W

0

W

0

External

CS/WAIT

control

C7H

(Prohibit

RMW)

Data bus Set number of wait

width

selection

0: 16 bits

1: 8 bits

BEXCS

000: 2 waits

001: 1 wait

010: (1+N) waits 110: 4 waits

100: Reserved

101: 3 waits

register

011: 0 waits

111: 8 waits

S23

1

S22

1

S21

1

S20

1

S19

S18

S17

S16

1

Memory

start

address

register 0

R/W

MSAR0

MAMR0

MSAR1

MAMR1

C8H

C9H

CAH

CBH

1

V14~9

1

Start address A23 to A16 setting

V20

1

V19

1

V18

V17

V16

V15

V8

1

Memory

address

mask

R/W

1

register 0

CS0 block size. 0: The address compare logic uses this address bit

S23

1

S22

S21

S20

S19

S18

S17

S16

1

Memory

start

address

register 1

R/W

1

V15~9

1

Start address A23 to A16 setting

V21

1

V20

1

V19

V18

V17

V16

V8

Memory

address

mask

R/W

1

register 1

CS1 block size. 0: The address compare logic uses this address bit

Note: TMP91CU27/CP27/CK27 don’t include WAIT pin. Therefore, when select “(1 + N) waits”, operation is same

with “1 wait”.

2008-01-24

91CU27-234

TMP91CU27/CP27/CK27

Chip select/wait control (2/2)

Symbol Name Address

7

6

5

4

3

2

1

0

S23

S22

S21

S20

S19

S18

S17

S16

Memory

start

R/W

MSAR2

MAMR2

MSAR3

MAMR3

CCH

CDH

CEH

CFH

address

1

V22

1

V21

1

V20

1

V17

1

V16

1

V15

1

register 2

Start address A23 to A16 setting

V19

V18

Memory

address

mask

R/W

1

register 2

CS2 block size. 0: The address compare logic uses this address bit

S23

1

S22

S21

S20

S19

S18

S17

S16

1

Memory

start

R/W

address

register 3

1

Start address A23 to A16 setting

V22

1

V21

1

V20

1

V19

V18

V17

V16

1

V15

1

Memory

address

mask

R/W

1

register 3

CS3 block size. 0: The address compare logic uses this address bit

2008-01-24

91CU27-235

TMP91CU27/CP27/CK27

(5) Clock control

Symbol Name Address

7

6

5

4

3

2

1

0

XEN

XTEN

RXEN

RXTEN

RSYSCK

WUEF

PRCK1

PRCK0

R/W

1

0

1

0

High-

Low-

High-

Low-

Clock after Warm-up Select prescaler clock

00: f

frequency frequency frequency frequency release of (WUP)

FPH

System

clock

0 write:

oscillator oscillator oscillator oscillator STOP

01: Reserved

10: fc/16

Don’t care

1 write:

SYSCR0

E0H

(fc)

(fs)

(fc) after

(fs) after

mode

control

release of release of 0: fc

stop mode stop mode 1: fs

11: Reserved

0:Stopped

Warm-up

start

register 0

1:Oscillation 1:Oscillation

0 read: End

of WUP

1 read:

0:Stopped

1:Oscillation 1:Oscillation

Don’t end

WUP

SYSCK

0

GEAR2

GEAR1

GEAR0

0

R/W

1

0

System

clock

Clock

Select gear of high frequency clock

selection 000: fc

SYSCR1

E1H

control

register 1

0: fc

1: fs

001: fc/2

010: fc/4

011: fc/8

100: fc/16

Others : Setting is prohibited

−

R/W

WUPTM1 WUPTM0 HALTM1 HALTM0

DRVE

R/W

1

R/W

0

R/W

1

R/W

1

System

clock

0

Always

write “0”.

WUP time for oscillator HALT mode

00: Setting is prohibited 00: Setting is prohibited

1: Drive the

pin in the

stop

SYSCR2

E2H

control

register 2

8

01: 2 /input frequency

01: STOP mode

10: IDLE1 mode

11: IDLE2 mode

14

10: 2 /input frequency

mode

16

11: 2 /input frequency

PROTECT

−

R/W

0

−

R/W

−

R/W

ALEEN

R/W

0

EXTIN DRVOSCH DRVOSCL

R

0

R/W

0

R/W

1

R/W

1

EMC

1

0

EMCCR0 control

register 0

E3H

E4H

Protect flag Always

Always

write “1”.

Always

write “0”.

ALE Output 1: fc

0: Disable external

1: Enable clock

fc oscillator fs oscillator

drive ability drive ability

1: Normal 1: Normal

0: OFF

1: ON

write “0”.

0: Weak

EMC

Write “1FH”: Protect OFF

Write except “1FH”: Protect ON

EMCCR1 control

register 1

Note 1: If protection is on by writing except “1FH” code to EMCCR1 register, write operations to the following SFRs

are not possible.

(1) CS/WAIT controller

B0CS, B1CS, B2CS, B3CS, BEXCS,

MSAR0, MSAR1, MSAR2, MSAR3,

MAMR0, MAMR1, MAMR2, MAMR3

(2) Clock gear (EMCCR1 can be written to)

SYSCR0, SYSCR1, SYSCR2, EMCCR0

Note 2: When using internal SBI, set SYSCR0<PRCK1:0> to “00”.

2008-01-24

91CU27-236

TMP91CU27/CP27/CK27

(6) 8-bit timer control (1/2)

(6 −1) TMRA01

Symbol Name Address

7

6

5

4

3

2

1

0

TA0RDE

R/W

I2TA01 TA01PRUN TA1RUN

TA0RUN

R/W

0

R/W

0

R/W

0

R/W

0

8-bit timer

RUN

100H

TA01RUN

Double

buffer

0: Disable

1: Enable

IDLE2

0: Stopped prescaler

1:Operation

TMRA01

Up- counter Up-counter

(UC1) (UC0)

0: Stop and clear

1: Run (Count up)

102H

(Prohibit

RMW)

−

8-bit timer

register

W

Undefined

−

TA0REG

TA1REG

103H

(Prohibit

RMW)

8-bit timer

register

W

Undefined

TA01M1

0

Operation mode

00: 8-bit timer

01: 16-bit timer

10: 8-bit PPG

11: 8-bit PWM

TA01M0

0

PWM01

PWM00

TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0

R/W

8-bit timer

source

CLK &

0

PWM cycle

00: Reserved

01: 2⁶

Source clock for TMRA1 Source clock for TMRA0

104H

TA01MOD

00: TA0TRG

01: φT1

00: TA0IN pin input

01: φT1

mode

10: 2⁷

10: φT16

10: φT4

11: 2⁸

11: φT256

11: φT16

TA1FFC1 TA1FFC0 TA1FFIE

R/W R/W

TA1FFIS

8-bit timer

105H

(Prohibit

RMW)

1

0

TA1FFCR flip-flop

control

00: Invert TA1FF

01: SET TA1FF

10: Clear TA1FF

11: Don’t care

1: TA1FF Invertion by

invert

enable

0: TMRA0

1: TMRA1

(6−2) TMRA23

Symbol Name Address

7

6

5

4

3

2

1

0

TA2RDE

R/W

I2TA23 TA23PRUN TA3RUN

TA2RUN

R/W

0

R/W

0

R/W

0

R/W

0

8-bit timer

RUN

108H

TA23RUN

Double

buffer

IDLE2

TMRA23

Up-counter Up-counter

(UC2)

0: Stopped prescaler (UC3)

0: Disable

1: Enable

1:Operation

0: Stop and clear

1: Run (Count up)

10AH

(Prohibit

RMW)

−

W

8-bit timer

register

TA2REG

TA3REG

Undefined

10BH

(Prohibit

RMW)

−

W

8-bit timer

register

Undefined

TA23M1

0

TA23M0

0

PWM21

0

PWM20

TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0

R/W

8-bit timer

source

CLK &

0

Operation mode

00: 8-bit timer

01: 16-bit timer

10: 8-bit PPG

11: 8-bit PWM

PWM cycle

00: Reserved

01: 2⁶

Source clock for TMRA3 Source clock for TMRA2

10CH

TA23MOD

00: TA2TRG

00: Reserved

mode

01: φT1

10: 2⁷

10: φT16

10: φT4

11: 2⁸

11: φT256

11: φT16

TA3FFC1 TA3FFC0 TA3FFIE TA3FFIS

R/W R/W

10DH

(Prohibit

RMW)

8-bit timer

flip-flop

control

1

0

1: TA3FF

invert

0

TA3FFCR

00: Invert TA3FF

01: SET TA3FF

10: Clear TA3FF

11: Don’t care

Invert by

0: TMRA2

1: TMRA3

enable

2008-01-24

91CU27-237

TMP91CU27/CP27/CK27

8-bit timer control (2/2)

(6 − 3) TMRA45

Symbol Name Address

7

6

5

4

3

2

1

0

TA4RDE

R/W

I2TA45

R/W

0

TA45PRUN TA5RUN

TA4RUN

R/W

0

R/W

0

R/W

0

8-bit timer

RUN

TA45RUN

110H

Double

buffer

IDLE2

TMRA45

prescaler

Up-counter Up-counter

(UC5) (UC4)

0: Stopped

0: Disable

1: Enable

1: Operation

0: Stop and clear

1: Run (Count up)

112H

(Prohibit

RMW)

−

8-bit timer

register

TA4REG

TA5REG

W

Undefined

−

113H

(Prohibit

RMW)

8-bit timer

register

W

Undefined

TA45M1

0

TA45M0

0

PWM41

PWM40

TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0

R/W

0

8-bit timer

source

CLK &

Operation mode

00: 8-bit timer

01: 16-bit timer

10: 8-bit PPG

11: 8-bit PWM

PWM cycle

00 : Reserved

01: 2⁶

10: 2⁷

11: 2⁸

Source clock for TMRA5 Source clock for TMRA4

TA45MOD

114H

00: TA4TRG

01: φT1

00: TA4IN Pin input

01: φT1

mode

10: φT16

10: φT4

11: φT256

11: φT16

TA5FFC1 TA5FFC0

R/W

TA5FFIE

TA5FFIS

R/W

115H

(Prohibit

RMW)

8-bit timer

flip-flop

control

1

0

1:TA5FF

Invert

0

TA5FFCR

00: Invert TA5FF

01: SET TA5FF

10: Clear TA5FF

11: Don’t care

Invert by

0: TMRA4

1: TMRA5

enable

2008-01-24

91CU27-238

TMP91CU27/CP27/CK27

(7) 16-bit timer control

(7 − 1) TMRB0

Symbol

Name Address

7

6

5

4

3

2

1

0

TB0RDE

R/W

−

R/W

I2TB0

R/W

0

TB0PRUN

R/W

TB0RUN

R/W

0

16-bit timer

TB0RUN

180H

Run

Double

buffer

Always

write “0”.

IDLE2

TMRB

Up-counter

(UC10)

0: Stopped prescaler

0: Disable

1: Enable

1:Operation

0: Stop and clear

1: Run (Count up)

TB0CT1

TB0ET1

0

TB0CP0I TB0CPM1 TB0CPM0 TB0CLE

TB0CLK1 TB0CLK0

R/W

W*

1

R/W

0

182H

0

16-bit timer

source

CLK &

mode

TB0FF1 Inversion trigger 0: Software Capture timing

1:UC0 clear Source clock

TB0MOD

(Prohibit

RMW)

0: Disable

capture

1:Undefined

Always

enable

00: TB0IN0 input

01: φT1

00: Disable

1: Enable

01: ↑, ↑ (TB0IN0, TB0IN1)

10: ↑, ↓ (TB0IN0)

10: φT4

Capture to TB0RG1

read as “1”

11: φT16

11: ↑, ↓ (TA1OUT)

TB0CP1

matching

TB0FF1C1 TB0FF1C0 TB0C1T1 TB0C0T1 TB0E1T1

W*

R/W

TB0E0T1 TB0FF0C1 TB0FF0C0

W*

1

0

1

183H

00: Invert TB0FF1

01: Set TB0FF1

10: Clear TB0FF1

11: Don’t care

TB0FF0 invert trigger

0: Disable 1: Enable

00: Invert TB0FF0

01: Set TB0FF0

10: Clear TB0FF0

11: Don’t care

16-bit timer

flip-flop

TB0FFCR

(Prohibit

RMW)

control

Invert when Invert when Invert when Invert when

the UC10

value is

the UC10

value is

the UC10

matches

with

the UC10

matches

with

Always read as “11”.

loaded into

TB0CP1H/L TB0CP0H/L TB0RG1H/L TB0RG0H/L

−

188H

(Prohibit

RMW)

16-bit timer

register 0

Low

TB0RG0L

TB0RG0H

TB0RG1L

TB0RG1H

W

Undefined

−

189H

(Prohibit

RMW)

16-bit timer

register 0

High

W

Undefined

−

18AH

(Prohibit

RMW)

16-bit timer

register 1

Low

W

Undefined

−

18BH

(Prohibit

RMW)

16-bit timer

register 1

High

W

Undefined

16-bit timer

capture

register 0

Low

−

TB0CP0L

TB0CP0H

TB0CP1L

TB0CP1H

18CH

18DH

18EH

18FH

R

Undefined

16-bit timer

capture

register 0

High

−

R

Undefined

16-bit timer

capture

register 1

Low

−

R

Undefined

16-bit timer

capture

register 1

High

−

R

Undefined

Note: When programming “1” to TB0MOD<TB0CP0I> in condition of programmed “0”, present value of up-counter is

captured to TB0CP0 register.

2008-01-24

91CU27-239

TMP91CU27/CP27/CK27

(8) UART/serial channel control (1/2)

(8 − 1) UART/SIO channel 0

Symbol Name Address

7

6

5

4

3

2

1

0

Serial

200H

RB7/TB7

RB6/TB6

RB5/TB5

RB4/TB4

RB3/TB3

RB2/TB2

RB1/TB1 RB0/TB0

SC0BUF channel 0 (Prohibit

R (Receiving)/W (Transmission)

Undefined

buffer

RMW)

201H

RB8

R

EVEN

PE

OERR

PERR

FERR

SCLKS

0

IOC

0

R/W

R (Cleared to 0 by reading)

R/W

Undefined

0

1: Parity

enable

0

Overrun

error

0

Serial

SC0CR channel 0

control

Receiving Parity

Parity error Framing

0: Not error

detected 0: Not

Edge

selection

Input clock

selection

data bit8

0: Odd

1: Even

0: Not

0: SCLK0 ↑ 0: Baud rate

detected 1: Detected detected 1: SCLK0 ↓ generator

1: Detected

1: SCLK0

pin input

TB8

CTSE

RXE

0

WU

SM1

0

SM0

SC1

SC0

R/W

0

1: CTS

enable

0

Serial

SC0MOD0 channel 0

mode0

1: Receive 1: Wakeup 00: I/O interface

00: TA0TRG

Transmission

data bit8

202H

enable

01: 7-bit UART

10: 8-bit UART

11: 9-bit UART

01: Baud rate generator

10: Internal clock (f

11: External clock

(SCLK0 input)

)

SYS

−

BR0ADDE BR0CK1

BR0CK0

BR0S3

0

BR0S2

0

BR0S1

BR0S0

R/W

Serial

0

channel 0

BR0CR

203H

204H

Always

write “0”.

1:(16−K)/16 00: φT0

baud rate

divided

enable

01: φT2

10: φT8

11: φT32

Set the dividing value “N” (0 to F) of baud rate

generator.

control

BR0K3

0

BR0K2

0

BR0K1

0

BR0K0

0

Serial

channel 0

BR0ADD

R/W

K setting

register

Set the value of “K” (1 to F).

I2S0

R/W

FDPX0

R/W

0

Serial

SC0MOD1 channel 0

mode1

IDLE2

0: Stop

1: Operation

I/O

205H

interface

0: Half

duplex

1: Full

duplex

(8 − 2) IrDA

Symbol Name Address

7

6

5

4

3

2

1

0

PLSEL

RXSEL

TXEN

RXEN

SIRWD3

SIRWD2

SIRWD1

SIRWD0

R/W

0

IrDA

Receiving

data logic

Receiving Select effective pulse width

Transmission

pulse width

0: 3/16

Transmission

operation

SIRCR

control

207H

operation Pulse width of more than and equal

register

0: “H” pulse 0: Disable 0: Disable “2x × (Setting value + 1)”+100ns

1: “L” pulse 1: Enable 1: Enable Possible: 1 to 14

Not possible: 0, 15

1: 1/16

2008-01-24

91CU27-240

TMP91CU27/CP27/CK27

UART/serial channel control(2/2)

(8 − 3) UART/SIO channel 1

Symbol Name Address

7

6

5

4

3

2

1

0

Serial

208H

RB7/TB7 RB6/TB6

RB5/TB5

RB4/TB4

RB3/TB3

RB2/TB2

RB1/TB1

RB0/TB0

SC1BUF channel 1 (Prohibit

R (Receiving)/W (Transmission)

Undefined

buffer

RMW)

RB8

R

EVEN

0

PE

0

OERR

PERR

FERR

SCLKS

IOC

R/W

R (Cleared to 0 by reading)

R/W

Undefined

0

Overrun

error

0

Serial

Receiving Parity

data bit 8 0: Odd

1: Even

1: Parity

enable

Parity error Framing

0: Not error

detected 0: Not

detected 1: SCLK1 ↓ generator

Edge

Input clock

SC1CR channel 1 209H

control

selection

0: Not

0: SCLK1 ↑ 0: Baud rate

detected 1: Detected

1: Detected

1:SCLK1

pin input

TB8

CTSE

0

RXE

0

WU

SM1

0

SM0

0

SC1

SC0

R/W

0

Serial

SC1MOD0 channel 1 20AH

mode 0

1: CTS

1: Receive 1: Wakeup 00: I/O interface

00: TA0TRG

Transmission

data bit8

enable

01: 7-bit UART

10: 8-bit UART

11: 9-bit UART

01: Baud rate generator

10: Internal clock (f

11: External clock

(SCLK1 input)

)

SYS

−

BR1ADDE BR1CK1

BR1CK0

0

BR1S3

BR1S2

0

BR1S1

BR1S0

R/W

Serial

0

channel 1

BR1CR

20BH

20CH

Always

write “0”.

1:(16−K)/16 00: φT0

baud rate

control

divided

enable

01: φT2

10: φT8

11: φT32

Set the dividing value “N” (0 to F) of baud rate

generator.

BR1K3

0

BR1K2

0

BR1K1

0

BR1K0

0

Serial

channel 1

K setting

register

R/W

BR1ADD

Set the value of “K” (1 to F).

I2S1

R/W

FDPX1

R/W

0

Serial

IDLE2

0: Stop

1:Operation

I/O

SC1MOD1 channel 1 20DH

mode1

interface

0: Half

duplex

1: Full

duplex

Note 1: As all error flags SCxCR<OERR, PERR,FERR> are cleared after reading, do not test only a single bit with a

bit-testing instruction.

Note 2: The baud rate genetrator can be set N = “1” when UART mode and disable + (16 − K)/16 division function.

Don’t use in I/O interface mode.

Note 3: Set BRxCR<BRxADDE> to “0” and disable + (16 − K)/16 division function in I/O interface mode.

2008-01-24

91CU27-241

TMP91CU27/CP27/CK27

(9) I²C bus/serial channel control (1/2)

Symbol Name Address

7

6

5

4

3

2

1

0

SCK0

/SWRMON

BC2

BC1

BC0

ACK

SCK2

SCK1

240H

(I²C bus

mode)

W

0

R/W

W

0

W

0

R/W

0/1

0

Acknowledge

mode

Select number of transfer bit

Internal serial clock selector (When writing)

(Prohibit

000: 8

011: 3

110: 6

001: 1

100: 4

111: 7

010: 2

101: 5

000: 5

011: 8

110: 11

001: 6

100: 9

111: Reserved

010: 7

101: 10

Serial bus

0: Disable

1: Enable

RMW)

SBI0CR1 interface

control

SIOS

SIOINH

SIOM1

SIOM0

SCK2

SCK1

W

SCK0

240H

(SIO

register 1

W

0

W

0

W

0

Transfer

control

0: Stop

1: Start

0

mode)

Forcing stop Select transfer mode

of transfer 00: 8-bit transmit

0: Continue 01: Reserved

Select frequency of serial clock

000: 4

011: 7

110: 10

001: 5

100: 8

111: External SCK input

010: 6

101: 9

(Prohibit

RMW)

1: Stop

10: 8-bit transmit/receiving

11: 8-bit receiving

SBI

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

241H

(Prohibit

RMW)

data

R (Receiving)/W (Transmission)

SBI0DBR

buffer

register

Undefined

SA6

0

SA5

0

SA4

0

SA3

0

SA2

0

SA1

0

SA0

0

ALS

W

I²C bus

242H

(Prohibit

RMW)

0

I2C0AR address

register

Address

recognition

0: Enable

1: Disable

Setting slave address

AD0/

SWRST1

LRB/

SWRST0

MST

TRX

BB

0

AL/SBIM1 AAS/SBIM0

R/W

Serial bus

When read interface

SBI0SR status

register

0

1

0

0: Slave

1: Master

Bus status INTSBI

Arbitration Slave

GENERAL Monitor of

243H

(I²C bus

mode)

0: Receiver

1: Transmit

monitor

0: Free

1: Busy

request

monitor

0: Request monitor

1: Cancel 1: Detect

lost

address

CALL

the last bit

received

0: “0”

detection

match

detection

monitor

1: Detect

detection

monitor

1: Detect

1: “1”

(Prohibit

RMW)

Start/stop

condition

generation

Serial bus interface

operating mode selection

00: Port mode

Software reset generation:

write “10” and “01”, then an

internal reset signal is

generated.

Serial bus

When write interface

SBI0CR2 control

register 2

01: SIO mode

10: I²C bus mode

11: (Reserved)

SIOF/SBIM1 SEF/SBIM0

R/W

−

W

0

Transfer

status

0

Serial bus

When read interface

SBI0SR control

register

Shift

operation

status

monitor

243H

(SIO

monitor

0: Finished

mode)

0: Finished

1: In

1: In operation

(Prohibit

RMW)

operation

Serial bus interface

Always write Always write

Serial bus

When write interface

SBI0CR2 control

register 2

operating mode selection “0”.

00: Port mode

“0”.

01: SIO mode

10: I²C bus mode

11: (Reserved)

2008-01-24

91CU27-242

TMP91CU27/CP27/CK27

I²C bus/serial channel control (2/2)

Symbol Name Address

7

6

5

4

3

2

1

0

−

W

I2SBI0

R/W

0

Serial bus

244H

Interface

0

SBI0BR0

baud rate

(Prohibit

Always

write “0”.

IDLE2

register 0

RMW)

0: Stop

1: Operating

P4EN

−

W

Serial bus

interface

245H

0

Always

write “0”

Clock

SBI0BR1 baud rate (Prohibit

control

register 1

RMW)

0: Stop

1:Operating

Note 1: When use built-in SBI, set SYSCR0<PRCK1:0> to f

.

FPH

Note 2: Set the SBI0CR1<BC2:0> to “000” before switching to a clock-synchronous 8-bit SIO mode.

Note 3: Switch a mode to Port mode after confirming that the bus is free. And, switch from port mode to I²C bus mode

or SIO mode after confirming port conditon = “H”.

Note 4: Set the transfer mode and the serial clock in SIO mode after clearing SBI0CR1<SIOS> to “0” and <SIOINH>

to “1”.

Note 5: After reset, default value of SBI0CR1<SCK0> is cleared “0”, and default value of <SWRMON> is set “1”.

2008-01-24

91CU27-243

TMP91CU27/CP27/CK27

(10) AD converter control

Symbol Name Address

7

6

5

4

3

2

1

0

EOCF

ADBF

−

ITM0

R/W

REPEAT

R/W

SCAN

ADS

R/W

0

R

R/W

0

AD

Always

write “0”.

Interrupt

0: Single

0: Channel AD

conversion conversion write “0”.

end flag busy flag

0:Conversion 1:Conversion

specification conversion fixed mode conversion

AD

channel

fixed repeat

mode

1: Repeat

conversion scan mode 1: Start

conversion

1:Channel

0: Don’t care

mode

register 0

ADMOD0

2B0H

in progress

1:Conversion

complete

in progress

0: Every

conversion

1: Every

fourth

conversion

VREFON

I2AD

R/W

0

ADTRGE

R/W

ADCH2

0

ADCH1

R/W

0

ADCH0

0

R/W

0

0: VREF off IDLE2

1: VREF on 0: Stop

External

trigger

start

Input channel selection

Fixed/Scan

AD

1: Operation

000: AN0/AN0

mode

register 1

ADMOD1

2B1H

0: Disable

1: Enable

001: AN1/AN0 →AN1

010: AN2/AN0 → AN1 → AN2

011: AN3/AN0 → AN1 → AN2 → AN3

100:

101:

Don’t select

110:

111:

ADR01

ADR00

ADR0RF

AD result

register

0/4 low

2A0H

2A1H

2A2H

2A3H

2A4H

2A5H

2A6H

2A7H

ADREG04L

R

0

Undefined

ADR09

ADR08

ADR07

ADR17

ADR27

ADR37

ADR06

ADR05

ADR04

ADR14

ADR24

ADR34

ADR03

ADR13

ADR23

ADR33

ADR02

AD result

register

0/4 high

ADREG04H

ADREG15L

R

Undefined

ADR11

ADR10

ADR1RF

AD result

register

1/5 low

R

0

Undefined

ADR19

ADR18

ADR16

ADR15

ADR12

AD result

register

1/5 high

ADREG15H

ADREG26L

ADREG26H

ADREG37L

ADREG37H

R

Undefined

ADR21

ADR20

ADR2RF

AD result

register

2/6 low

R

0

Undefined

ADR29

ADR28

ADR26

ADR25

ADR22

AD result

register

2/6 high

R

Undefined

ADR31

ADR30

ADR3RF

AD result

register

3/7 low

R

0

Undefined

ADR39 ADR38

ADR36

ADR35

ADR32

AD result

register

3/7 high

R

Undefined

Note 1: ADMOD0<ADS> is always read as “0”.

Note 2: When using ADTRG with ADMOD1<ADTRGE> = “1”, do not set ADMOD1<ADCH2:0> = “011.

Note 3: When set ADMOD1<I2AD> to ”0”, operation is different by AD conversion mode after released HALT mode.

2008-01-24

91CU27-244

TMP91CU27/CP27/CK27

(11) Watchdog timer control

Symbol Name Address

7

6

5

4

3

2

1

0

WDTE

R/W

WDTP1

R/W

WDTP0

R/W

0

I2WDT

R/W

0

RESCR

R/W

0

−

R/W

0

1

0

WDT

00: 2¹⁵/f

1: WDT

enable

IDLE2

0: Stop

1:Internaly Always

connects write “0”.

SYS

WDMOD mode

register

300H

01: 2¹⁷/f

10: 2¹⁹/f

11: 2²¹/f

SYS

1:Operation WDT out

to the

reset pin

−

W

−

301H

(Prohibit

RMW)

WDT

WDCR

control

B1H: WDT disable

4EH: WDT clear

(12) Special timer for CLOCK

Symbol Name Address

7

6

5

4

3

2

1

0

−

R/W

RTCSEL1 RTCSEL0 RTCRUN

Special

R/W

0

timer for

0

00: 2¹⁴/fs

01: 2¹³/fs

10: 2¹²/fs

11: 2¹¹/fs

0:Stop and

clear

RTCCR CLOCK

control

310H

Always

write “0”.

register

1:RUN

2008-01-24

91CU27-245

TMP91CU27/CP27/CK27

6. Port Section Equivalent Circuit Diagram

•

Reading the circuit diagram

Basically, the gate symbols written are the same as those used for the standard CMOS logic IC

“74HC××” series.

The dedicated signal is described below.

STOP: This signal becomes active “1” when the halt mode setting register is set to the STOP

mode (SYSCR2<HALTM1:0> = “0”, “1”) and the CPU executes the HALT instruction.

When the drive enable bit SYSCR2<DRVE> is set to “1”, stop remains at “0”.

•

The input protection resistance ranges from several tens of ohms to several hundreds

of ohms.

■

P0 (AD0 to AD7), P1 (AD8 to AD15, A8 to A15), P2 (A16 to A21, A0 to A5), P60, P70 to P74, P80

to P83, P91 to P92 and P94 to P95

V

CC

P-ch

Output data

Output enable

N-ch

STOP

I/O

Input data

Input enable

■

P30 (RD ), P31 ( WR )

V

CC

Output

P-ch

Output

STOP

N-ch

2008-01-24

91CU27-246

TMP91CU27/CP27/CK27

■

P32, P40 to P42

V

CC

P-ch

Output data

Vcc

Programmable

pull-up resistor

Output enable

STOP

N-ch

I/O

Input data

Input enable

■

P5 (AN0 to AN3)

Analog input

Channel select

Analog input

Input

Input data

Input eable

■

P63 (INT0)

V

CC

P-ch

Output data

Output enable

STOP

N-ch

Input data

I/O

Schmitt

2008-01-24

91CU27-247

TMP91CU27/CP27/CK27

■

P61 (SO/SDA), P62 (SI/SCL), P90 (TXD0) and P93 (TXD1)

V

CC

Output data

P-ch

N-ch

Open drain output

enable

STOP

I/O

Input data

Input enable

■

P96 (XT1) and P97 (XT2)

Clock

Input enable

Oscillation

circuit

Input data

P97 (XT2)

P96 (XT1)

Output data

Output enable

N-ch

Input enable

Input data

Output data

Output enable

N-ch

STOP

Low

Frequency

oscillator

enable

■

NMI

Input

Schmitt

2008-01-24

91CU27-248

TMP91CU27/CP27/CK27

■

AM0 and AM1

Input

Input data

ALE

V

CC

Internal ALE

P-ch

Output

N-ch

Output enable

■

RESET

V

CC

P-ch

Input

Reset

Schmitt

WDTOUT

Reset enable

(WDMOD<RESCR>)

■

X1 and X2

Oscillation circuit

P-ch

X2

X1

High frequency

oscillator enable

STOP

N-ch

Clock

■

AVCC and AVSS

VREFON

P-ch

AVCC

Ladder resistor

AVSS

2008-01-24

91CU27-249

TMP91CU27/CP27/CK27

7. Notes and Restrictions

(1) Notation

1. The notation for built-in I/O registers is as follows: Register symbol<Bit symbol>

Example: TA01RUN<TA0RUN> denotes bit TA01RUN of register TA01RUN.

2. Read-modify-write instructions

An instruction in which the CPU reads data from memory and writes the data to the same

memory location in one instruction.

Example 1: SET 3, (TA01RUN) ................ Set bit 3 of TA01RUN.

Example 2: INC 1, (100H).......................... Increment the data at 100H.

•

Examples of read-modify-write instructions on the TLCS-900:

Exchange instruction

EX (mem), R

Arithmetic operations

ADD (mem), R/#

SUB (mem), R/#

INC #3, (mem)

ADC (mem), R/#

SBC (mem), R/#

DEC #3, (mem)

Logic operations

AND (mem), R/#

XOR (mem), R/#

OR (mem), R/#

Bit manipulation operations

STCF #3/A, (mem)

SET #3, (mem)

TSET #3, (mem)

RES #3, (mem)

CHG #3, (mem)

Rotate and shift operations

RLC (mem) RRC (mem)

RL (mem)

RR (mem)

SRA (mem)

SRL (mem)

RRD (mem)

SLA (mem)

SLL (mem)

RLD (mem)

3.

f

fc, fs, f

, f and one state

FPH SYS

OSCH,

The clock frequency input from X1 and X2 is referred to as f

.

OSCH

TMP91CU27/CP27/CK27 are not equipped with DFM. Therefore, fc equals f

clock frequency input from XT1/XT2 pin is referred to as fc.

. The

OSCH

The clock selected by SYSCR1<SYSCK> is referred to as f . The clock frequency given

FPH

by f_FPHdivided by 2 is referred to as f_SYS. One cycle of f

is referred to as one state.

SYS

2008-01-24

91CU27-250

TMP91CU27/CP27/CK27

(2) Notes

a. AM0 and AM1 pins

This pin is connected to the DVCC pin. Do not alter the level when the pin is active.

b. Warm-up counter

The warm-up counter operates when STOP Mode is released, even if the system is using

an external oscillator. As a result a time equivalent to the warm-up time elapses between

input of the release request and output of the system clock.

c. Programmable pull-up/pull-down resistor

The programmable pull-up/pull-down resistor can be turned ON/OFF by a program when

the ports are set for use as input ports. When the ports are set for use as output ports, they

cannot be turned ON/OFF by a program.

The data registers (e.g., P4 register) are used to turn the pull-up resistors ON/OFF.

Consequently read-modify-write instructions are prohibited. Therefore, use Transfer

instruction.

d. Watchdog timer

The watchdog timer is enabled immediately after a reset is released. Disable the

watchdog timer when it is not to be used.

e. AD converter

The string resistor between the AVCC to AVSS pins can be cut by program so as to reduce

power consumption.

When STOP mode is used as reduce consumption power supply, disable the resistor using

the program before the HALT instruction is executed.

f. CPU (Micro DMA)

Only the LDC cr, r and LDC r, cr instructions can be used to access the control registers

in the CPU (e.g., the transfer source address register (DMASn)).

g. Undefined SFR

The value of an undefined bit in an SFR (Special function register) is undefined when

read.

h. POP SR instruction

Please execute the POP SR instruction during DI condition.

i. Releasing the HALT mode by requesting an interruption

Usually, interrupts can release all halts status. However, the interrupts ( NMI , INT0,

INTRTC) which can release the HALT mode may not be able to do so if they are input

during the period CPU is shifting to the HALT mode (for about 5 clocks of f_FPH) with IDLE1

or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is

kept on hold internally)

If another interrupts is generated after it has shifted to HALT mode completely, halt

status can be released without difficulty. The priority of this interrupt is compared with

that of the interrupt kept on hold internally, and the interrupt with higher priority is

handled first followed by the other interrupt.

2008-01-24

91CU27-251

TMP91CU27/CP27/CK27

8. Package Dimensions

LQFP64-P-1010-0.50D

Unit: mm

12.0 0.2

10.0 0.2

48

33

49

32

64

17

1

16

0.08

0.6 0.15

2008-01-24

91CU27-252

TMP91CU27/CP27/CK27

Unit: mm

QFP64-P-1414-0.80A

2008-01-24

91CU27-253

TMP91CU27/CP27/CK27

2008-01-24

91CU27-254


型号：	TMP91CK27UG
厂家：	TOSHIBA
描述：	IC 16-BIT, MROM, 27 MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64, Microcontroller 微控制器
文件：	总256页 (文件大小：1726K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMP91CK27UG [TOSHIBA]

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