TPD7107F [TOSHIBA]
MOSFET Driver;
| 型号： | TPD7107F |
| 厂家： | 
TOSHIBA |
| 描述： | MOSFET Driver |
| 文件： | 总34页 (文件大小：1030K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD7107F
TOSHIBA Intelligent Power Device Silicon Power MOS Integrated Circuit
TPD7107F
1 channel High-Side N channel Power MOSFET Gate Driver
1. Description
TPD7107F is a 1channel high-side N channel power MOSFET gate
driver. This IC contains a charge pump circuit, allowing easy
configuration of a high-side switch for large-current applications.
TPD7107F
P-WSON10-0303-0.50-002
2. Uses
●
●
●
Junction Boxes for Automotive.
Power distribution modules for Automotive.
Semiconductor relays.
3. Features
●
●
●
AEC-Q100 qualified.
Built in the charge pump circuit.
Built in the various protection feature and diagnostic output function.
‒ The abnormalities in power supply voltage (a voltage fall, excess voltage, reverse connection of
power supply)
‒ Current sense of load line.
‒ Over current (short circuit of load line)
‒ Overheating
‒ The abnormalities in Drain-source voltage of external FET
‒ Active clamp of external FET
‒ Protection for disconnection of GND terminal.
‒ VDD short of load line (Short circuit between source of external FET and VDD)
‒ Disconnection of load line (open).
●
WSON10A package for surface mounting.
Note: Due to its MOS structure. This product is sensitive to static electricity.
Start of commercial production
2020-03
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4. Block Diagram
.
Note: Since a function is explained, it may have omitted in part and may have simplified the functional
block in a block, the circuit, the constant, etc.
Figure 4.1 Block Diagram
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5. Pin Assignments
10
9
1
2
3
4
VDD
GND
DIAG
MIRROR
N.C.
Die pad 1
Die pad 2
8
GND-TAB
STBY
7
SHUNT
6
GATE
IN
5
Figure 5.1 Pin Assignments (top view)
6. Pin Description
Table 6.1 Pin Description
Pin No
Symbol
Description
1
2
3
4
GND
Ground pin.
Current sense output and diagnostic output.
DIAG
GND-TAB Ground pin.
STBY
IN
Standby mode control pin.
5
Input pin. Built in pull down resistor.
Output pin for an external FET drive
6
7
GATE
SHUNT Input pin for shunt resistance connection.
N.C. No-Connect pin.
MIRROR An external FET source pin and a shunt resistance connect pin.
VDD Power supply pin.
8
9
10
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7. Operational Description
7.1. Protection for reverse connection of power supply
Reverse connection circuit turns on external FET via M1 in the figure and reduces external FET loss to
prevent thermal destruction.
Figure 7.1 Reverse connection circuit.
7.2. Active clamp
Active clamp is a function that keeps the voltage between drain and source of external FET below at the
break down voltage. When the surge voltage is generated by the inductive load, the voltage between VDD
and SHUNT increases and the active clamp circuit in Figure7.2 outputs the voltage to the GATE pin.
Therefore, the external FET will be in ON state and the voltage between drain and source of external FET
will be clamped.
Figure 7.2 Active clamp circuit.
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Active clamp.
VIN
VDD
VSHUNT
Vclamp
VGATE
●
●
●
●
VIN: IN pin input voltage
V
V
V
SHUNT: SHUNT pin input voltage
GATE: GATE pin output voltage
clamp: Active clamp voltage
Figure 7.3 Timing chart of Active clamp operation.
7.3. Gate drive of Power MOSFET (Off driver)
Three kinds of drive circuits which control the turn-off of external FET exist in this products. Operation of
each drive is explained below.
7.3.1. Normal off, rapid off
The normal off driver makes the external FET an OFF state via the IN pin. The rapid off driver operates
and draws out the gate charge of the external FET quickly, when the latch is stopped by the anomaly
detection. Whenever the rapid off driver operates, the normal off driver operates in parallel.
Figure 7.4 Off driver circuit.
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7.3.2. Protection for disconnection of GND terminal
GND disconnection protection is a function that keeps an OFF state in order to prevent a malfunction of
the external FET, when GND terminal wiring of a unit is disconnected.
In OPEN state as shown in Figure7.5, the off driver of GND disconnection operates, and turn off the
external FET regardless of the condition of an input signal.
Figure 7.5 Protection circuit for disconnection of GND terminal.
GND open.
VIN
VDD
VGND
< VUV3
VGATE
OFF drive for GND open.
Decrease of VGATE
●
VIN: IN pin input voltage
VGND: GND pin voltage
VGATE: GATE pin output voltage
●
●
●
V
UV3: Low voltage latch threshold
Figure 7.6 Protect operation of disconnection of GND terminal.
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7.4. Load current sense at time of Power MOSFET drive
For A/D-converter detection via the DIAG pin, the current sense amplifier and the pull up for diagnosis
circuit in Figure7.7 carry out the conversion from the current which flows into the shunt resistance Rs to
the voltage.
Figure 7.7 Current sense amp circuit.
Load current sense output voltage is calculated as below. In addition, when abnormalities are detected,
a load current sense output mode is changes to a diagnostic output mode. And the fixed voltage according
to the diagnosis results is outputted.
ꢅ2
( )
× ꢅꢆ × ꢇꢈ + ꢀ
ꢂꢈ
ꢀꢁꢂꢃꢄ
=
ꢅ1
●
●
●
V
DIAG: DIAG pin output voltage
IO: load current
VIO: Input offset voltage
7.5. The abnormalities in power supply voltage (VDD over voltage, VDD under voltage)
● When the voltage of a VDD terminal is more than the over voltage detection threshold (VOV), the off-
driver usually operates and the external FET turns off. After that, if the VDD terminal voltage is less than
the over voltage threshold voltage, the external FET is driven again.
‒ In the case of VIN=H and VDD>VOV, the off-driver operates after the mask time of TOV (200us max)
(VGATE=H to L).
‒ In the case of VDD>VOV and VIN=L to H, it keeps VGATE=L.
● When VDD terminal voltage is less than VUV3 (2.7V (typ.)), the rapid off-driver operates, carry out latch-
off of the external FET, and outputs H state to DIAG.
● In case VDD<VUV5, the off-driver operates and VDD goes up. After that, if VDD is more than VUV5, the off-
driver will change to normal operation.
● Even if VDD terminal voltage falls under the conditions of VGATE=H, VGATE keeps H state, and external
FET will be ON in VDD>VUV3.(Low-voltage extension operation)
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Normal
UV5
UV3
OV
VOV
26V
5.75V
VUV5
VUV3
0V
VDD
VIN
VGATE
VDIAG
TDIAG
TLATCH
TOV
●
●
●
●
●
●
●
●
●
VIN: IN pin input voltage
VGATE: GATE pin output voltage
V
DIAG: DIAG pin output voltage
VUV3: Low voltage latch threshold
VUV5: Low voltage detection threshold
VOV: Over voltage detection voltage
TDIAG: DIAG clear standby time
TLATCH: Latch clear standby time
TOV: Over voltage detection mask time
Figure 7.8 The abnormalities in power supply voltage
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7.6. Over current protection
● When the current sense voltage (VDIAG) turns into more than over-current detecting voltage (VOC), the
rapid off-driver operates to protect the external FET. After that, it becomes an OFF & latch state and
outputs diagnostic contents.
● The filter (Over current detection delay time 2.5us (typ.)) is built in so that the over-current caused by a
power supply variation may not be detected incorrectly.
● In case VIN=H to L, the over current protection circuit releases latches. When a latch of DIAG is
released, the clear standby time from the falling edge of VIN(TDIAG) is set to 10ms (minimum). In a
period of the standby time, the IN terminal cannot control the GATE terminal.
Normal.
OC.
Normal.
TDIAG
VIN
Latch off.
VGATE
VDIAG
VOC
VDIAG
TOC
TLATCH
●
●
●
●
●
●
●
●
VIN: IN pin input voltage
VGATE: GATE pin output voltage
DIAG: DIAG pin output voltage
VOC: Over current detection voltage
DIAG1: DIAG output voltage (High Level)
V
V
TOC: Over current detection delay time
TLATCH: Latch release mask time
T
DIAG: DIAG clear standby time
Figure 7.9 Over current protection
● The over current threshold voltage changes according to the power supply voltage and the junction
temperature.
‒ VOC1: VDD=3V,Tj=25°C
‒ VOC2: Tj=25°C
‒ VOC3: VDD=3V,Tj=125°C
‒ VOC4: Tj=125°C
● The over current detecting voltage falls to 66% (typ.) of VOC2 and VOC4, when the abnormalities in
voltage between drain and source of the external FET occur.
● The over current detection voltage falls to 50% (typ.) of VOC2 and VOC4, when the under voltage
detection (UV5) occurs.
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VOC2
VOC4
VOC1
VOC3
125℃
25℃
Tj(℃)
Figure 7.10 Junction Temperature dependency of over current detection
7.7. Over temperature protection.
The over temperature protection prevents destruction due to the temperature rise of this product and
MOSFET, so if junction temperature exceeds Thermal detection temperature, normal off driver operates
and turns the external FET off. When junction temperature drops below hysteresis set temperature, this
product returns to normal operation.
VIN
TOT
TOT - Thys
Tj
VGATE
VDIAG
●
●
●
●
●
VIN: IN pin input voltage
VGATE: GATE pin output voltage
VDIAG: DIAG pin output voltage
TOT: Over heat detection temperature
Thys: Hysteresis of thermal detection
Figure 7.11 Over temperature protection
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7.8. Abnormalities in voltage between Drain and source of the external FET (VDS error)
● The voltage between drain and source of the external FET supervises the differential voltage between
the VDD pin and the SHUNT pin. If the voltage between drain source exceeds the VDS error detection
threshold (1.5V (typ.)), the rapid off-driver operates and changes the external FET into the OFF & latch
state. Therefore, the diagnostic output will be in H state.
● When a low-voltage (UV5) state occurs simultaneously with the abnormalities of the voltage between
Drain and source, the rapid off-driver operates and makes the external FET into an OFF & latch state
because of no detection time. The diagnostic output will become the H state.
● GATE pin and DIAG pin latches are released by VIN=H to L.
● When an error is detected, it is judged as abnormal after the detection time (TVDSerr) to prevent
malfunction due to noise.
VDSerr
UV5 ＆VDSerr
VDD
VUV5
VIN
VGATE
VDD-VSHUNT
VDSerr
VDIAG
TVDSerr
●
●
●
●
●
VIN: IN pin input voltage
VGATE: GATE pin output voltage
VDD-VSHUNT: Voltage between VDD pin and SHUTN pin
VDIAG: DIAG pin output voltage
T
VDSerr: VDS error detection time
Figure 7.12 Abnormalities in voltage between Drain and source of external FET
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7.9. Load open / VDD short of load line and diagnosis output
The load open detects the disconnection of the load connected to SHUNT pin. The VDD short of load line
detects the VDD short of the load connected to SHUNT pin. A circuit example is shown below (figure
7.14). The detection condition and DIAG pin output voltage for each item are as shown in the table below.
Table 7.1 Load open detection / VDD short of load line detection
item
Detection condition
DIAG output voltage
VOP < VSHUNT
VDSerr < VDD-VSHUNT
Load open detection
2.3V(minimum)
VDDS < VSHUNT
VDD-VSHUNT < VDSerr
VDD short of load line
4.3V(minimum)
● The DIAG output voltage changes from rise edge of VIN to normal operation after a DIAG clear
waiting time (TDIAG). See the timing chart below.
VIN
VDSerr
VDD
VDDS
VSHUNT
VOP
VGATE
VDIAG1
VDIAG2
VDIAG
TDIAG
TDIAG
●
●
●
●
●
●
●
●
●
VIN: IN pin input voltage
VSHUNT: SHUNT pin input voltage
V
GATE: GATE pin output voltage
VDIAG: DIAG pin output voltage
VDIAG1: DIAG output voltage (High level)
DIAG2: DIAG output voltage (Load open)
V
VOP: Load open detection voltage
VDDS: VDD short detection voltage
T
DIAG: DIAG clear standby time
Figure 7.13 Load open / VDD short detection
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VDD
MIROR
N.C.
GND
DIAG
GND-TAB
STBY
IN
VDD short.
SHUNT
GATE
Load open.
Figure 7.14 Load open / VDD short circuit example
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7.10. Truth Table
Table 7.2 Truth Table
Operation.
STBY
IN
SHUNT,MIRROR
GATE
DIAG
Normal operation (Standby)
L
X
X
L
L
Normal operation
H
H
H
H
H
H
H
H
H
H
H
H
L
H (≈VDD
)
H
analog
Over voltage detection (1)
L
L
L
(VOV < VDD
)
Over voltage detection (2)
(VOV < VDD
H
X
X
X
X
X
X
L
H (≈VDD
)
L (Note1)
L (Note1)
)
Over temperature
X
X
X
X
L
L
L
L
UV5 (VDD < VUV5
UV3 (VDD < VUV3
)
)
L
H
(Latch off)
(Latch)
L
H
Over current detection
(Latch off)
(Latch)
L (Note2)
(Latch off)
H (Note2)
(Latch)
VDS abnormal
VDSerr > (VDD-VSHUNT
)
)
VDS abnormal && UV5
L
H
V
DSerr > (VDD-VSHUNT
(Latch off)
(Latch)
(VDD < VUV5
)
Load open detection.
VDD short.
VOP > VSHUNT
L
L
VDIAG2
L
H (≈VDD
)
H
Note1. Mask time 400μs (typ.)
Note2. Mask time 13ms (typ.)
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7.11. State Transition Diagram
11) Battery Reverse
connection.
-VDD
1) VDD open, GND open.
FET = OFF
FET = ON
DIAG = L
4) Abnormal off mode.
FET = OFF
IN = H
+VDD
OV = True |
OT = True
UV5 = False &&
OV = False &&
OT = False
STBY=H
STBY=L
2) Standby mode.
FET = OFF
8) Output open or VDD
short detection.
UV5 | OV | OT
DIAG = L
3) Normal operation.
FET = ON
STBY = L
IN = L
Output open |
VDD short
False
Over Current = True |
UV5 && VDSerr = True |
UV3 = True |
True
7) On Standby mode.
FET = OFF
DIAG = L
VDSerr = True
9) Output open or VDD short Detection
a) Output open : DIAG = VDIAG2
b) VDD short : DIAG = H
IN = L
6) Latch clear.
DIAG clear.(10ms)
5) Latch off mode..
FET = OFF (Latch)
IN = H
10) DIAG clear.(10ms)
Figure 7.15 State Transition Diagram
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8. Absolute Maximum Ratings
Table 8.1 Absolute Maximum Ratings
(Ta = 25°C unless otherwise specified)
Characteristics
Symbol
Rating
Unit
Comment(s)
VDD(1)
VDD(2)
VDD(3)
VIN(1)
-16 to 26
-36 to 36
-40 to 40
-16 to 26
V
V
V
V
Supply voltage
t≤400ms
Supply voltage
t≤20ms
IN,STBY,SHUNT,MIRROR
IN,STBY,SHUNT,MIRROR
VIN(2)
VIN(3)
IGATE(+)
IGATE(-)
-36 to 36
-40 to 40
V
V
Input voltage
t≤400ms
IN,STBY,SHUNT,MIRROR
t≤20ms
Output source current
Output sink current
Internal ability
5
mA
mA
GATE
GATE
Output voltage
VGATE
-0.3 to 40
V
GATE
DIAG Output voltage
DIAG Output current
Power dissipation
VDIAG
IDIAG
PD(1)
Topr
Tj
-0.3 to 6
5
V
mA
W
DIAG
DIAG
1.84
-
-
-
-
Operating temperature
Junction temperature
Storage temperature
-40 to 125
150
°C
°C
°C
Tstg
-55 to 150
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage
and the significant change in temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage,
etc.) are within the absolute maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability
Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability
data (i.e. reliability test report, estimated failure rate, etc.)
8.1. Thermal Resistance
Table 8.2 Thermal resistance
Charateristics
Symbol
Rth (j–a)
Rating
67.6
unit
Thermal resistance, junction to
ambient
°C / W
Note: Glass epoxy board
Material: FR-4(4 layer) Board size: 76.2mmx114.3mmx1.6mm
Via: φ0.3mm(2 points)
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9. Operating Ranges
Table 9.1 Operating Ranges
Characteristics
Symbol
Condition
Min
Typ.
Max
Unit
Operating supply voltage
VDD
Tj = -40 to 125°C
5.75
12.00
26.00
V
10. Electrical Characteristics
10.1. Electrical characteristics 1
Table 10.1 Electrical Characteristics 1
(Unless otherwise specified, Tj = -40 to 125°C, VDD = 5.75 to 26V)
Characteristics
Symbol
Pin
VDD
VDD
Test Condition
Min
5.75
-
Typ.
12.00
-
Max
26.00
3
Unit
V
Operating supply voltage VDD(opr)
-
VDD = 16V, Standby,
Tj=25°C
IDD(off)
μA
Supply current
VDD=12V,VIN = VIH,
Tj=25°C
IDD(on)
VDD
-
2
3
mA
High level input voltage
Low level input voltage
Hysteresis
VIH
VIL
VIhys
IIH
IN,STBY
IN,STBY
IN,STBY
IN,STBY
IN,STBY
-
2.4
-
-
-
0.6
-
V
V
-
-
-
-
0.5
21
-
VIN= 5V
VIN= 0V
-
50
1
Input current
μA
IIL
-1
VDD = 3V, VIN= VIH,
GATE-SHUNT =
200kΩ
VDD
+6.5
VDD
+8.6
High level output
voltage(1)
VGATEH1
GATE
-
V
VDD =5.75 to 26V,
VIN= VIH,
GATE-SHUNT =
200kΩ
VDD
+7.5
VDD
+10.0
VDD
+12.5
High level output
voltage(2)
VGATEH2
GATE
V
V
VDD=-12V
Measurement 1
High level output
voltage(3)
VGATEH3
VGATEL
Vclamp
GATE
GATE
6
-
-
Low level output voltage
Active clamp voltage
VIN = VIL
-
-
0.5
-
V
V
VDD
,
VIN=VIL,
VGATE=2V,VSHUNT=0V
35
39
SHUNT
Latch release mask time
TLATCH
Td-ON
Td-OFF
Tr
-
VIN= VIL
-
-
-
-
-
50
35
-
μs
55
154
321
138
195
460
176
Measurement 2,
Tj=25°C
Switching time
GATE
μs
Tf
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10.2. Electrical characteristics 2
Table 10.2 Electrical Characteristics 2
(Unless otherwise specified, Tj = -40 to 125°C, VDD = 5.75 to 26V)
Characteristics
Symbol
Pin
Test Condition
Min
Typ.
Max
Unit
Off impedance at GND
open
RGO
GATE
Measurement 3
25
51
80
kΩ
GATE-SHUNT resistance
Rapid off state current
RGSH
IGL
GATE
GATE
DIAG
DIAG
DIAG
DIAG
-
500
100
-
1000
237
1.75
3.45
1.4
2000
500
-
kΩ
mA
V
Latch off state.
VDD=3V,Tj=25°C
Tj=25°C
Over current detection(1)
Over current detection (2)
Over current detection (3)
Over current detection (4)
VOC1
VOC2
VOC3
VOC4
3.25
-
3.65
-
V
VDD=3V,Tj=125°C
Tj=125°C
V
2.6
2.8
3.2
V
Over current threshold
down rate at VDS error
-
-
VDSerr detection.
-
-
66
50
-
-
%
%
Over current threshold
down rate at Low voltage
-
-
UV5 detection.
Over current detection
delay time
TOC
TOT
Thys
VUV3
-
-
-
2.5
169
16
10.0
200
-
μs
°C
°C
V
Over heat detection
temperature
-
-
VSTBY = VIH
-
150
-
Hysteresis of thermal
detection
Low voltage latch threshold
(UV3)
VDD
VSTBY = VIH
2.5
2.7
3.0
Low voltage detection
threshold (UV5)
VUV5
VUV5R
VOV
VDD
VDD
VDD
VSTBY = VIH
VSTBY = VIH
VSTBY = VIH
4.15
4.9
4.40
5.1
4.65
5.4
V
V
V
UV5 release voltage
Over voltage detection voltage
(OV)
26.0
27.4
30.0
Over voltage detection mask
time
TOV
VDD
VSTBY = VIH
150
1.0
400
1.4
650
2.0
μs
VDD
SHUNT
VDS error detection threshold
VDS error detection time
SHUNT leakage currnet
VDSerr
VSTBY= VIH, VIN=VIH
V
VDD
SHUNT
TVDSerr
VSTBY= VIH, VIN=VIH
VIN=VSTBY=L,
10
13
20
ms
ISHUNTS
ROP
SHUNT
SHUNT
-
-
1.5
20
μA
kΩ
V
SHUNT=0V,VDD=16V
Load open detection
resistance
-
5
11
Load open detection voltage
VDD short detection voltage
VOP
SHUNT
SHUNT
VSTBY=VIH,VIN=VIL
VSTBY=VIH,VIN=VIL
VSTBY = VIH,
2.0
2.6
-
-
V
V
VDDS
VDD-2
VDD
DIAG clear standby time
TDIAG
DIAG
10
-
20
ms
Error detection is
canceled
DIAG output voltage
(High level)
Abnormality is detected
VDIAG1
VDIAG2
DIAG
DIAG
4.3
2.3
-
-
5.0
3.8
V
V
DIAG-GND = 10kΩ
DIAG output voltage
(Load open)
Open is detected.
DIAG-GND = 10kΩ
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10.3. Current sense amp Electrical Characteristics
Table 10.3 Current sense amp Electrical Characteristics
(Unless otherwise specified, Tj = -40 to 125°C, VDD = 5.25 to 26V)
Characteristics
Symbol
Pin
Test Condition
Min
Typ.
Max
Unit
SHUNT,
MIRROR
Common mode input
voltage range
CMVIN
-
2.5
-
VDD
V
SHUNT,
MIRROR
V
V
DD=13.5V,Tj=25°C
Measurement 4
Input offset voltage
VIO
VIOT
-2
-10
-
-
-
-
-
2
10
5
mV
μV/°C
μA
SHUNT,
MIRROR
DD=13.5V,Tj=25°C
Measurement 4
Input offset voltage
temperature drift
V
SHUNT=VDD
,
SHUNT terminal current
ISHUNT
SHUNT
VIN=5V
V
MIRROR=VDD
,
MIRROR terminal current IMIRROR
MIRROR
-
5
μA
VIN=5V
11. Test Circuit
11.1. Test circuit 1 High level output voltage (3)
Figure 11.1 Test circuit 1
11.2. Test circuit 2 Switching time (Td-ON, Td-OFF, Tr, Tf)
Figure 11.2 Test circuit 2
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TPD7107F
11.3. Test circuit 3 Off impedance at GND open
Figure 11.3 Test Circuit 3
11.4. Test circuit 4 Input offset voltage
Figure 11.4 Test Circuit 4
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TPD7107F
12. Characteristic curves
The below characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
IDD(off) - Tj
IDD(off) - VDD
10
8
10
8
VDD=16V
Standby
Tj=25℃
Standby
6
6
4
4
2
2
0
-80
-40
0
40
80
120
160
0
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD(V)
IDD(on) - Tj
IDD(on) - VDD
10
8
10
8
Tj=25℃
VDD=12V
VIN=VIH
VIN=VIH
6
6
4
4
2
2
0
0
-80
-40
0
40
80
120
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD(V)
VIH,VIL - Tj
VIH,VIL - VDD
4
3
2
1
0
4
3
2
1
0
VDD=12V
Tj=25℃
VIH
VIH
VIL
VIL
-80
-40
0
40
80
120
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD(V)
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VIhys - VDD
VIhys - Tj
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
Tj=25°C
VDD=6V
0
6
12
18
24
30
-80
-40
0
40
80
120
160
Operating supply voltage VDD(V)
Junction temperature Tj(℃)
IIH - Tj
IIH - VIN
100
80
60
40
20
0
100
80
60
40
20
0
VIN=5V
Tj=25°C
-80
-40
0
40
80
120 160
0
2
4
6
8
10
Channel temperature Tj(℃)
Terminal voltage VIN(V)
VGATEH - VDD
VGATEH - Tj
20
15
10
5
20
15
10
5
VDD = 12V
GATE - SHUNT=200kΩ
Tj=25°C
GATE - SHUNT = 200kΩ
0
0
-80
-40
0
40
80
120
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
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VGATEH3 - VDD
VGATEH3 - Tj
20
15
10
5
20
15
10
5
Tj =25℃
GATE - SHUNT = 200kΩ
VDD = -12V
GATE - SHUNT = 200kΩ
0
0
-80
-40
0
40
80
120
160
160
160
-30
-24
-18
-12
-6
0
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
VGATEL - Tj
VGATEL - VDD
0.5
0.4
0.3
0.2
0.1
0.0
0.5
0.4
0.3
0.2
0.1
0.0
Tj =25°C
VDD = 12V
IO = 1μA
IO = 1μA
-80
-40
0
40
80
120
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
Vclamp - Tj
50
45
40
35
30
VIN=VIL
VSHUNT=0V
VGATE=2V
-80
-40
0
40
80
120
Junction temperature Tj(℃)
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Td-off - Tj
Td-on - Tj
170
160
150
140
130
50
40
30
20
10
VDD=12V
VDD=12V
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
Junction temperature Tj(℃)
Junction temperature Tj(℃)
Tf - Tj
Tr - Tj
200
180
160
140
120
100
400
360
320
280
VDD=12V
VDD=12V
-80
-40
0
40
80
120 160
-80
-40
0
40
80
120 160
Junction temperature Tj(℃)
Junction temperature Tj(℃)
RGO - Tj
RGO - VDD
80
70
60
50
40
30
20
80
70
60
50
40
30
20
VDD=12V
Tj=25°C
-80
-40
0
40
80
120
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
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RGSH - Tj
2,000
1,700
1,400
1,100
800
VDD=12V
500
-80
-40
0
40
80
120 160
Junction temperature Tj(℃)
IGL - Tj
IGL - VDD
500
400
300
200
100
500
400
300
200
100
VDD=26V
Tj=25°C
-80
-40
0
40
80
120
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
VOC - VDD
VOC - Tj
5
4
3
2
1
5
4
3
2
1
0
Tj=25°C
VDD=12V
0
0
-80
-40
0
40
80
120
160
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
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TOC - VDD
TOC - Tj
5
4
3
2
1
0
5
4
3
2
1
0
Tj=25°C
VDD=12V
-80
-40
0
40
80
120
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
TOT - VDD
Thys - VDD
200
190
180
170
160
150
50
40
30
20
10
0
0
6
12
18
24
30
0
6
12
18
24
30
Operating supply voltage VDD (V)
Operating supply voltage VDD (V)
VUV3 - Tj
VUV5 - Tj
10
8
10
8
VDD=VUV5
VDD=VUV3
6
6
4
4
2
2
0
0
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
Junction temperature Tj(℃)
Junction temperature Tj(℃)
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VOV - Tj
VUV5R - Tj
30
28
26
24
22
20
10
8
VDD=VOV
VDD=VUV5R
6
4
2
0
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
Junction temperature Tj(℃)
Junction temperature Tj(℃)
TOV - Tj
600
500
400
300
200
100
VDD=VOV
-80
-40
0
40
80
120
160
Junction temperature Tj(℃)
VDSerr - VDD
VDSerr - Tj
2
2
1.8
1.6
1.4
1.2
1
Tj=25°C
VDD=12V
1.8
1.6
1.4
1.2
1
-80
-40
0
40
80
120
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
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TVDSerr - VDD
TVDSerr - Tj
20
18
16
14
12
10
20
18
16
14
12
10
Tj=25°C
VDD=12V
-80
-40
0
40
80
120
160
160
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
ISHUNTS - Tj
2
VDD=16V
1.5
1
0.5
0
-80
-40
0
40
80
120
Junction temperature Tj(℃)
ROP - VDD
ROP - Tj
20
15
10
5
20
15
10
5
Tj=25°C
VDD=12V
0
0
-80
-40
0
40
80
120
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
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VOP - VDD
VOP - Tj
5
4
3
2
1
0
5
4
3
2
1
0
Tj=25°C
VDD=12V
-80
-40
0
40
80
120
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
VDDS - VDD
VDDS - Tj
30
25
20
15
10
5
15
13
11
9
Tj=25°C
VDD=12V
7
5
0
-80
-40
0
40
80
120
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
VDIAG1 - VDD
VDIAG1 - Tj
5
5
T=25°C
j
VDD=12V
DIAG - GND = 10kΩ
DIAG - GND = 10kΩ
4.8
4.8
4.6
4.4
4.2
4
4.6
4.4
4.2
4
0
6
12
18
24
30
-80
-40
0
40
80
120
160
Operating supply voltage VDD (V)
Junction temperature Tj(℃)
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VDIAG2 - VDD
VDIAG2 - Tj
4
3.5
3
4
3.5
3
Tｊ=25°C
DIAG - GND = 10kΩ
VDD=12V
DIAG - GND = 10kΩ
2.5
2
2.5
2
-80
-40
0
40
80
120
160
0
6
12
18
24
30
Junction temperature Tj(℃)
Operating supply voltage VDD (V)
VIO - VDD
VIO - Tj
2
1
2
1
Tj=25°C
VDD=13.5V
0
0
-1
-2
-1
-2
0
6
12
18
24
30
-80
-40
0
40
80
120
160
Operating supply voltage VDD (V)
Junction temperature Tj(℃)
ISHUNT,IMIRROR - Tj
5
3
1
VSHUNT=VMIRROR=VDD
VIN=5V
MIRROR
-1
-3
-5
SHUNT
-80
-40
0
40
80
120 160
Junction temperature Tj(℃)
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TPD7107F
13. Package Information
13.1. Package Dimensions
Unit: mm
Weight: 0.02 g (typ.)
Figure 13.1 Package Dimensions
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TPD7107F
13.2. Marking
Part No.
7 1 0 7 F
1610
(or abbreviation code)
Lot No.
Last 2digits of the A.D. + week code (2 digits)
□□□□□□
●
Administrative code (6 digits)
●
The lower left marking No. 1 terminal is shown.
Figure 13.2 Marking
13.3. Land Pattern Dimensions for Reference only
Unit: mm
Figure 13.3 Land Pattern Dimensions for Reference only
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TPD7107F
14. IC Usage Notes
14.1. Notes on Handling of ICs
(1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
exceeded, even for a moment.
(2) The voltage more than current sense voltage or diagnostic output voltage may be outputted to a
DIAG output by the injection of a power supply, interception conditions, the input condition to
current sense amplifier, etc. Please confirm problem existence by a set in the case of use.
Moreover, please give me a measure by a capacitor etc. if needed.
14.2. Notes on mounting.
(1) Please make Die pad 1 into GND and the potential.
(2) Please make Die pad 2 into SHUNT (7pin) and the potential.
10
9
1
2
3
4
VDD
MIRROR
N.C.
GND
DIAG
Die pad 1
8
GND-TAB
STBY
7
SHUNT
Die pad 2
6
GATE
5
IN
Figure 14.1 Pin arrange (Bottom View)
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RESTRICTIONS ON PRODUCT USE
Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”.
Hardware, software and systems described in this document are collectively referred to as “Product”.
• TOSHIBA reserves the right to make changes to the information in this document and related Product without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's
written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for
complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which
minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to
property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the
Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information,
including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and
conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product
will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited
to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the
applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any
other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO
LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.
•
PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY
CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation,
equipment used in nuclear facilities, equipment used in the aerospace industry, lifesaving and/or life supporting medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, and devices related to power plant. IF YOU USE PRODUCT FOR UNINTENDED USE,
TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative or contact us via our
website.
• Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any
intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
•
ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR
PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER,
INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING
WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2)
DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR
INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for
the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass
destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations
including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export
and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and
regulations.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please
use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including
without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT
OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
https://toshiba.semicon-storage.com/
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