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TX19A [TOSHIBA]

32Bit TX System RISC; 32位TX RISC系统
TX19A
型号： TX19A
厂家： TOSHIBA    TOSHIBA
描述：

32Bit TX System RISC
32位TX RISC系统
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32Bit TX System RISC  
TX19A Family  
Architecture  
Rev１.0  
Semiconductor Company  
• The information contained herein is subject to change without notice. 021023_D  
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor  
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.  
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in  
making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such  
TOSHIBA products could cause loss of human life, bodily injury or damage to property.  
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as  
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and  
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability  
Handbook” etc. 021023_A  
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer,  
personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These  
TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high  
quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended  
Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments,  
transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types  
of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the  
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• The products described in this document shall not be used or embedded to any downstream products of which  
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is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its  
use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or the third  
parties. 021023_C  
• The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E  
• MIPS16,Application Specific Extensions ＆ R3000A are trademarks of MIPS Group , a division of Silicon  
Graphics, Inc.  
Preface  
This manual describes the architecture of the Toshiba TX19A family.  
Contents  
Chapter 1: Introduction  
Outline of TX19A  
Chapter 2: CPU Architecture Overview  
-Data load in the CPU registers and memory  
-Overview of the functionality of the registers  
Chapter 3: 32-Bit ISA Summary and Programming Tips  
-Summary of the 32-bit instruction set architecture (ISA)  
Chapter 4: 16-Bit ISA Summary and Programming Tips  
-Summary of the 16-bit ISA  
Chapter 5: CPU Pipeline  
-Information about the instruction pipeline  
Chapter 6: Memory Management  
-The virtual and physical address spaces and these mapping manners  
Chapter 7: Internal I/O Bus Operation  
-Outlines of the Harvard architecture and the protocols for internal bus transactions  
Chapter 8: System Control Coprocessor (CP0) Registers  
-A group of registers associated with system configuration and exception processing  
Chapter 9: CPU Exception Processing  
-The events that cause exceptions and the sequences to be handled  
Chapter 10: Power Consumption Management  
-The methods of dynamically controlling power consumption during operation  
Appendix A: 32-Bit ISA Details  
-Detailed description of each instruction available in 32-bit ISA mode  
Appendix B: 16-Bit ISA Details  
-Detailed description of each instruction available in 16-bit ISA mode  
Appendix C: Programming Restrictions  
-The restrictions need to be observed in writing assembly-language programs  
Appendix D: Compatibility Among TX19, TX19A and TX39 Architectures  
-Provides comparisons among the three RISC processor families  
Appendix E: 32-Bit ISA Instruction Bit Encoding  
-The opcode bit encoding for the 32-bit ISA  
Appendix F: 16-Bit ISA Instruction Bit Encoding  
-the opcode bit encoding for the 16-bit ISA  
March.2007  
i
Readers  
This manual is written for software and hardware developers who want to develop products using  
TX19A processors and controllers.  
RISC processors including TX19A have a number of features that make them stand out from CISC  
processors. If you are unfamiliar with RISC architecture, Chapter 1 should be useful for you. Please  
note that RISC processors have a small instruction set. There are no complex instructions such as  
LDIR (block transfer), CPIR (block search), BS1B (bit scan). Since RISC has very few instructions,  
a programmer or a compiler needs to implement additional instructions by using available RISC  
instructions.  
Chapter 2, the architecture overview, should help programmers who can use a high-level language  
such as C in developing software.  
Assembly language programmers must be well versed in the intricacies of the machine architecture.  
The performance of software systems is drastically affected by how well software designers  
understand the basic hardware technologies at work in a system. Therefore, we recommend  
assembly language programmers to read the entire manual that gives a detailed description of the  
TX19A architecture for overall understanding.  
Related Document  
Semiconductor Reliability Handbook (Integrated Circuits)  
This book describes the methodology used by Toshiba to achieve robust semiconductor designs  
before market introduction and to ensure high quality and reliability in volume production phase.  
ii  
Chapter 1 Introduction  
Chapter 1 Introduction  
This chapter provides the features of the TX19A and a general description of how the TX19A RISC  
design differs from CISC processors such as the Toshiba 900/L1.  
1.1 Processor General Features  
The TX19A, a high quality 32-bit RISC processor, is created based on MIPS Technologies Inc.’s  
R3000A architecture that contains reduced code size of 16 bit architecture “MIPS16e-TX”. The  
instruction set of the TX19A includes the 32-bit instructions of the TX39 as a subset. Thus the  
TX19A software preserves upward compatibility with TX39 and TX19.  
The TX19A family of integrated processors and controllers is built on the TX19A core processor,  
an on-chip bus and a selection of intelligent peripherals appropriate for specific applications. The  
TX19A is available as an ASIC-ready core and a family of standard ASSP products.  
Instruction sets of MIPS 16e-TX and MIPS S32  
z MIPS16e-TX instruction sets are object-code compatible with MIPS16 ASE except for the area  
that Toshiba extended MIPS16 ASE with permission of MIPS Technologies, Inc.  
Note: The TX19A does not provide support for MIPS16 ASE instructions for 64-bit operations.  
z The 32-bit instructions are object-code compatible with the high-performance TX39 family.  
-Switchable run-time between 16-bit and 32-bit ISA modes through an instruction. These  
conditions are respectively called as 16 bit ISA mode and 32 bit ISA mode.  
-Hardware interlocks enables to send an instruction to refer the data loaded in register  
immediately after the load instruction. This eliminates the need to insert a NOP (No Operation)  
instruction.  
-Branch-likely instructions allow the processor to execute the instruction at the target location  
immediately after the branch instruction. This eliminates the need to insert a NOP instruction.  
High Performance  
z Single clock cycle execution for most instructions  
z 3-operand computational instructions  
z Full 32-bit operations: Contains 32-bit general-purpose registers and a 32-bit program counter.  
z 8 sets of 32 general-purpose registers (shadow register sets): Automatically switched on entry  
to an interrupt, based on its priority level.  
z 5-stage pipeline  
z Independent on-chip instruction and data memory with an access time of one clock cycle  
applicable  
z An on-chip write buffer applicable  
z Harvard architecture  
The TX19A uses separate buses for code and data operands. In the TX19A, there are four sets of  
buses: a data bus for carrying data (operands) in and out of the processor core, an address bus for  
1-1  
Chapter 1 Introduction  
accessing data operands, a bus to carry the opcodes and an address bus to access the opcodes. The  
ability to access code and data simultaneously through separate buses increases instruction  
throughput.  
z Nonblocking loads function enables to execute the subsequent instruction in a load delay slot in  
case a large latency appeared during data loading from external memory.  
z On-chip multiplier/accumulator (MAC): Executes a (32-bit x 32-bit + 64-bit) and (64-bit –  
32-bit x 32-bit) operations in a single clock cycle.  
z 4-Gbyte virtual address space  
z Integrated coprocessor: The TX19A contains the system control coprocessor (CP0) for system  
configuration, exception handling and memory management.  
Low Power  
z Power-optimized design  
Programmable power management modes (Halt and Doze): In Doze mode, the processor senses  
external bus requests.  
1-2  
Chapter 1 Introduction  
Real-Time Interrupt Response  
z Distinct starting locations for each interrupt service routine  
z Automatically generated vectors for each interrupt source: Interrupt priorities are resolved upon  
reading the exception vector. Interruption exception is executed when its priority level is higher  
than the current one. It makes the TX19A effective for quick response to an interrupt request  
that needs immediate action.  
z
On an interrupt, register sets are automatically switched based on its priority level.  
Processor Core for System ASIC Applications  
z Unified manufacturing process and development environment as ASIC  
z Compact core design  
z The processor core can be directly connected to the G-Bus, the standard on-chip bus for the TX  
series.  
System Development Environments  
z Language tools: C compilers and assemblers  
Both Toshiba’s proprietary and third-party tools are offered.  
z Real-time operating systems  
Both Toshiba’s proprietary (⎧ITRON) and third-party real-time operating systems are offered.  
z Debug support systems  
-Both Toshiba’s proprietary and third-party real-time emulators are offered to support  
source-level debugging.  
-Support for utility software to insert debug support unit (DSU) circuitry into an ASIC design.  
1-3  
Chapter 1 Introduction  
1.2 What Is RISC?  
Until the early 1980s, all CPUs followed the complex instruction set computer (CISC) design  
philosophy. To preserve compatibility with the existing pool of software, CISC processors evolved  
by adding new types of machine instructions and more intricate operations. Generally, CISC refers  
to CPUs with hundreds of instructions designed for every possible situation. Designing CPUs with  
hundreds of instructions not only requires many transistors but is also very complicated, timing  
consuming and expensive.  
In the early 1980s, a controversy broke out in the computer design community. Proponents of a new  
type of computer design argued that no one was using so many instructions. As it was developed, it  
came to be known as reduced instruction set computer (RISC). RISC concepts emerged by  
statistical analysis of how software actually uses the resources of a processor. According to  
experiments, many of the complex instructions were never used by programmers and compilers.  
The huge costs of implementing numerous instructions made some designers think of streamlining  
the instruction set.  
„ Feature 1 Simple instructions  
RISC processors have a small instruction set. For example, there are no such complex instructions  
as block transfer, block search, bit scan and so forth.  
Additionally, RISC uses the load/store architecture. In CISC processors, data can be manipulated  
while it is still in memory. For example, “ADD A, (1000H)” contained in 16-bit CISC processor  
TLCS-900/L1, is an instruction to bring the contents memory location 1000H into the CPU, sum it  
up with data in register A and store the total in A. RISC did away with this kind of instructions. In  
RISC, a single instruction can either load from memory into a register or store from a register into  
memory. In other words, all operations are performed on operands held in CPU registers.  
Since CISC processors have a large number of instructions, each with so many different addressing  
modes, microcode is used to implement all of them. This feature of CISC makes the job of  
programmers easy and helps to reduce code size. However, the implementation of microcode  
requires more space on chip, creating a bottleneck in an effort to improve processor performance.  
„ Feature 2 Fixed instruction size  
RISC processors have a fixed instruction size. In a CISC microprocessor, instructions can be 1, 2 or  
even 7 bytes at the maximum. This variable instruction size makes the task of the instruction  
decoder very complicated since the size of the incoming instruction can never be known. In the  
TX19A microprocessor, the instruction size is fixed at 32 bits. The fixed instruction size enables the  
CPU to decode instructions quickly.  
1-4  
Chapter 1 Introduction  
„ Feature 3 Heavily pipelined  
Since RISC has only a limited number of simple instructions, most of the instructions can be  
executed in one clock cycle. Therefore, RISC is easier to pipeline than CISC that requires a  
different number of clock cycles for each instruction in pipeline. Generally, RISC processors are  
heavily pipelined.  
1.3 Features of the TX19A  
The previous section provided an overview of the RISC features which are different from CISC  
processors. In this section, we explore how the instruction set architecture (ISA) is implemented in  
the TX19A in comparison to the 870/X and the 900/L1, 8-bit and 16-bit CISC processors from  
Toshiba.  
The TX19A has two ISA modes, 16-bit and 32-bit. The condition that each mode is executed is  
respectively called as 16 bit ISA mode and 32 bit ISA mode. It provides for efficient run-time  
switching between 16-bit and 32-bit ISA modes through an instruction. The 16-bit instruction set  
(MIPS16e+) is not a separate instruction set indeed but a 16-bit extension of the full 32-bit MIPS  
architecture. The 32-bit ISA has 103 instructions, the 16-bit ISA 128 instructions. Programs will  
consist of procedures in 16-bit mode for density or in 32-bit mode for performance.  
On the other hand, the 870/X and the 900/L1 are both CISC processors having nearly 1000 types of  
instructions and many addressing modes. CISC processors are, in general, excel in code efficiency.  
1.3.1 Instruction Set Architecture  
z The TX19A did away with complex instructions.  
The TX19A has only the basic instructions such as load, store, add, subtract, multiply, divide, AND, OR,  
XOR, shift, jump and branch. There are no complex instructions like LDIR (block transfer) and CPIR  
(block search) available with the 900/L1. It is the responsibility of the compiler (or the programmer) to  
generate software routines to perform complex instructions that are done in hardware by CICS  
processors. As exceptions, are the multiply-and-add (MADD and MADDU) and multiply-and-subtract  
(MSUB and MSUBU) instructions that require very fast processing are included in instruction sets  
(these instructions are executed by the dedicated MAC circuitry.)  
z
The TX19A did away with instructions that can be implemented by some other  
instructions  
To reduce the size of the instruction set, the TX19A aggressively eliminated the instructions that  
can be implemented using other instructions. For example, the TX19A does not have the NOP (No  
Operation), INC (Increment) and DEC (Decrement) instructions. Instead of NOP, a shift instruction  
can be used as shown below for TX19A processors:  
SLL r0,r0,0  
In the TX19A, register r0 is hardwired to a constant value of 0. The above instruction actually shifts  
the contents of r0 by zero bits and places the result back in r0. (The assembler permits NOP as a  
1-5  
Chapter 1 Introduction  
pseudoinstruction for program readability; however, it turns NOP into a shift instruction.)  
A register increment can be implemented by using the ADDIU (Add Immediate Unsigned)  
instruction as shown below:  
ADDIU rt,rs,1  
In this condition, rt and rs are the target and source registers respectively. Likewise, a register  
decrement can be implemented as follows:  
ADDIU rt,rs,-1  
z The TX19A discarded instructions synthesizable from two or more simple instructions  
The TX19A further pared down the instruction set by discarding the instructions that can be  
performed by two or more simple instructions. For example, the TX19A does not have the POP and  
the PUSH instructions for accessing the stack. In CISC processors, as a PUSH instruction is  
executed, the contents of a register is saved on the stack and the stack pointer register is  
decremented by the amount of the register size. In the TX19A, one of the 32 general-purpose  
registers is used as a stack pointer; pushing onto the stack is accomplished by executing an add  
instruction on the stack pointer and a store instruction.  
z The TX19A uses the load/store architecture  
In CISC processors such as the 870/X and the 900/L1, data can be manipulated while it is still in  
memory, like ADD A, (1000H). The TX19 did away with this kind of instructions; in the TX19, the  
load and store instructions are the only instructions that move data between memory and CPU  
general registers. However, the TX19A enhanced the capability of the TX19 by adding a group of  
instructions that manipulate a specific bit in memory or add an immediate to a value in memory.  
z The TX19A has only a few memory addressing modes  
The 900/L1 and the 870/X1 have seven or more addressing modes for memory accesses. For example,  
there are register indirect, register indirect with autoincrement, indexed relative, based indexed  
relative, etc. These versatile addressing modes are very useful for assembly language programmers and  
contribute to a reduction in code size.  
In contrast, in 32-bit ISA mode, the TX19A has only one addressing mode for accessing memory  
locations in order to simplify hardware implementation: i.e., based relative. In 16-bit ISA  
mode, the TX19A has three more addressing modes called PC-relative, SP-relative and FP-relative;  
only three 16-bit instructions can use PC-and SP-relative addressing modes, however.  
1-6  
Chapter 1 Introduction  
z The TX19A has three-operand computational instructions 3  
In the TX19A, many computational instructions use triadic format. In triadic instruction format,  
there are two source registers and one destination register. An example of triadic format is:  
ADD rd,rs1,rs2  
This instruction adds the contents of two source registers, rs1 and rs2, and stores the results in rd.  
On the other hand, the 900/L1 adds the contents of XWA and XBC and puts the result in XWA.  
ADD XWA,XBC  
z The TX19A does not have a flag register  
The TX19A does not have a dedicated flag register with the carry, overflow and sign bits. For example,  
in the 900/L1, the carry flag is used to indicate whether or not there was a carry from an addition or a  
borrow as a result of subtraction. It is widely used in multibyte additions and subtractions. The 900/L1  
has the ADC instruction to add the carry bit to the sum of two registers.  
On the other hand, the TX19A can perform 32-bit additions at a time; so the flag bit is rarely  
needed. To perform an add-with-carry, a routine must first explicitly determine whether the addition  
has resulted in a carry, and then record the occurrence of a carry in a register. When doing  
multiword additions, two different code sequences are required: one for adding with a carry-in and  
one for adding without a carry-in.  
Additionally, the 900/L1 CP (compare) instruction uses the carry flag to indicate whether or not  
there was a borrow as a result of subtraction. In the TX19A, the result of compare instructions such  
as SLT (Set On Less Than) is placed into a general register.  
1.3.2  
Instruction Format  
The TX19A has two ISA modes, 16-bit and 32-bit. All the instructions for the 32-bit ISA mode, as  
the name suggests, consist of 32 bits. All the instructions for the 16-bit ISA mode consist of 16 bits,  
with a few exceptions. The 870/C instructions have the variable length: 1, 2, 3, 4, 5 and 6 bytes.  
Furthermore, the 900/L1 covers 7 byte-instruction as the longest. This variable instruction length  
is useful to reduce code size; however, it makes the task of the instruction decoder very complicated  
and slow.  
1.3.3 Instruction Pipelines  
The TX19A has a five-stage pipeline. The five-stage pipeline divides the execution of each  
instruction into five discrete portions and executes up to five instructions simultaneously. Each  
stage takes one clock cycle.  
The major characteristics of the TX19A is that the execution of most instructions requires a uniform  
number of clock cycles; thus the TX19A is relatively easy to pipeline. The TX19A achieves an  
instruction execution rate approaching one instruction per clock cycle.  
1-7  
Chapter 1 Introduction  
If the instruction stream includes a variety of different instruction lengths as in CISC processors,  
pipeline management becomes very complicated. Moreover, such a varied, complex instruction  
stream makes it almost impossible for a compiler to schedule instructions to reduce or eliminate  
pipeline stalls.  
1-8  
Chapter 2 CPU Architecture Overview  
Chapter 2 CPU Architecture Overview  
This chapter outlines the TX19A architecture, data formats, programming model, ISA modes,  
coprocessors, instruction pipeline and memory management.  
2.1 Data Formats  
This section describes the organization of data in registers and memory and how operands are  
signor zero-extended for operations.  
2.1.1 Byte Ordering  
The TX19A supports many data types including 8-bit, 16-bit, 32-bit and 64 bit. A byte is defined as  
8 bits. A halfword is two bytes, or 16 bits. A word is four bytes, or 32 bits. A doubleword is two  
words, or 64 bits.  
For multibyte data types, the TX19A supports both big-endian and little-endian formats. Byte  
ordering (endianness) can be set through the ENDIAN input pin during a reset sequence. (In some  
TX19A components, byte ordering is fixed to either big-endian or little-endian.)  
Figure 2-1 shows the ordering of bytes in a word for big-endian and little-endian formats. The  
TX19A processor uses a byte addressing. The big-endian ordering assigns the lowest address to the  
highest-order (leftmost) byte. The little-endian ordering assigns the lowest address to the  
lowest-order (rightmost) byte. Notice that, in the little-endian format, each byte of a multibyte  
integer is placed in the same memory location regardless of whether the integer is defined as a  
halfword or a word in size.  
Register  
Memory  
Byte  
0x45  
0x67  
Lower  
Address  
0x01  
0x23  
0x45  
0x67  
Higher  
Address  
Word Access Halfword Access  
Bit 31  
Bit 0  
(a) Big-Endian  
01  
23  
45  
67  
Lower  
Address  
Byte  
Halfword  
0x67  
0x45  
0x23  
0x01  
0x67  
0x45  
Word  
Higher  
Address  
Word Access Halfword Access  
(b) Little-Endian  
Figure 2-1 Byte Ordering  
2-1  
Chapter 2 CPU Architecture Overview  
2.1.2 Aligned and Misaligned Accesses  
The TX19A uses byte addressing for byte, halfword and word accesses. The address of a multibyte  
data item is the address of the lowest memory location for that data item; i.e. the address of the  
most-significant byte on a big-endian configuration and the address of the least-significant byte on a  
little-endian configuration.  
Memory access instructions have a natural alignment boundary equal to the operand length (see fig.  
2-2). In other words, the natural address of an operand is an integer multiple of the operand length.  
A memory operand is aligned if its address is a multiple of two for halfword accesses or a multiple  
of four for word accesses.  
Byte  
Byte  
Byte  
Lower Address  
Higher Address  
Memory  
Operand  
Address  
Byte Access  
Word Access  
Halfword Access  
(a) Memory Accesses  
Word Boundaries  
Halfword Boundaries  
0
1
2
3
4
5
6
7
(b) Data Alignment  
Figure 2-2 Aligned Data Items  
Most instructions require their memory operands to be aligned because alignment affects  
performance. Special instructions are provided for addressing words that cross a boundary between  
two words: LWL (Load Word Left), LWR (Load Word Right), SWL (Store Word Left) and SWR  
(Store Word Right). These instructions are used in pairs. Figure 2-3 illustrates how a word of  
aligned and misaligned data is loaded from memory into a CPU register.  
2-2  
Chapter 2 CPU Architecture Overview  
+0  
+1  
+2  
+3  
+0  
+1  
+2  
+3  
0x400  
0x404  
0x400  
0x404  
LW r8 0(r9)  
LWL r 8 3(r9)  
LWR r8 6(r9)  
Register r8  
Register r8  
(b) Misaligned Access (Big-Endian)  
(a) Aligned Access (Big-Endian)  
Figure 2-3 Aligned and Misaligned Accesses  
2.1.3 Data Extensions  
Figure 2-4 illustrates sign extension and zero extension. In signed numbers, the most-significant bit  
is the sign and the remaining bits are set aside for the magnitude of the number. Sign extension  
copies the most-significant bit (i.e., sign bit) of a 16-bit immediate or the loaded byte or halfword  
into the upper bits. Zero extension fills unused bits in a word with zeros irrespective of the value of  
the most-significant bit of a 16-bit immediate or the loaded byte or halfword.  
15  
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
Sign Bit  
31  
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
15  
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
Sign Bit  
31  
1
1
1
1
(a) 16-Bit to 32-Bit Sign Extension  
15  
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
The upper bits are always padded with zeros.  
31  
0
15  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(b) 16-Bit to 32-Bit Zero Extension  
Figure 2-4 Sign Extension and Zero Extension  
2-3  
Chapter 2 CPU Architecture Overview  
Sign extension is typically used to avoid problems associated with arithmetic operations. For  
example, the ADDI (Add Immediate Signed) instruction only can take a 16-bit immediate. The  
instruction "ADDI r3, r1, 0x1234" sign extends 0x1234 and adds it to the contents of register r1 to  
form a 32-bit result. The result is placed into register r3.  
The TX19A also applies sign extension to such instructions as LB (Load Byte), LBU (Load Byte  
Unsigned) LH (Load Halfword), LHU (Load Halfword Unsigned) LW (Load Word), SB (Store  
Byte), SH (Store Halfword), SW (Store Word) since the only addressing mode supported is base  
register plus 16-bit immediate (i.e., offset). For example, the instruction "LB r9, 4(r8)" sign-extends  
the offset (4 or binary 0100) and adds it to the contents of the base address held in r8 to form an  
effective address. The word in the addressed memory location is loaded into r9.  
To load byte data and halfword data in register, sign extension or zero extension is selected depend  
on the instructions. Therefore, the LB and LH instructions sign- extend the loaded byte and put it in  
the target register; the LBU instruction zero-extends the loaded byte.  
Additionally, there are two types of logical AND and logical OR instructions each, AND/ANDI and  
OR/ORI. The AND and OR instructions perform AND and OR operations with word data whereas  
the ANDI (AND Immediate) and ORI (OR Immediate) perform AND and OR operations with word  
data and halfword data. ANDI and ORI zero-extends a 16-bit immediate and combine it with the  
contents of a general register in a bitwise logical AND or OR operation.  
2.2 Programming Model  
The TX19A programming model consists of two groups of registers: CPU registers and system  
control coprocessor (CP0) registers.  
2.2.1 CPU Registers  
Figure 2-5 shows the CPU registers. The TX19A has eight sets of 32 general-purpose registers  
(GPRs) called shadow sets for a total of 256 GPRs, a program counter (PC) register and two special  
registers (HI/LO) that hold the results of integer multiply and divide operations. All CPU registers  
are 32 bits in length.  
2-4  
Chapter 2 CPU Architecture Overview  
(a) General-Purpose Registers  
(b) Multiply/Divide Registers  
Shadow  
Register  
Set No.  
0
1
2
3
4
5
6
7
HI  
r0  
r26 (k0)  
r27 (k1)  
r28 (gp)  
LO  
r29 (sp)  
r1 (at)  
r2 (v0)  
r3 (v1)  
r4 (a0)  
r5 (a1)  
r6 (a2)  
r7 (a3)  
r8 (t0)  
r9 (t1)  
r29 (sp)  
r1 (at)  
r2 (v0)  
r3 (v1)  
r4 (a0)  
r5 (a1)  
r6 (a2)  
r7 (a3)  
r8 (t0)  
r9 (t1)  
r1 (at)  
r2 (v0)  
r3 (v1)  
r3 (a0)  
r5 (a1)  
r6 (a2)  
r7 (a3)  
r8 (t0)  
r9 (t1)  
r1 (at)  
r2 (v0)  
r3 (v1)  
r4 (a0)  
r5 (a1)  
r6 (a2)  
r7 (a3)  
r8 (t0)  
r9 (t1)  
r1 (at)  
r2 (v0)  
r3 (v1)  
r4 (a0)  
r5 (a1)  
r6 (a2)  
r7 (a3)  
r8 (t0)  
r9 (t1)  
r1 (at)  
r2 (v0)  
r3 (v1)  
r4 (a0)  
r5 (a1)  
r6 (a2)  
r7 (a3)  
r8 (t0)  
r9 (t1)  
r1 (at)  
r2 (v0)  
r3 (v1)  
r4 (a0)  
r5 (a1)  
r6 (a2)  
r7 (a3)  
r8 (t0)  
r9 (t1)  
r1 (at)  
r2 (v0)  
r3 (v1)  
r4 (a0)  
r5 (a1)  
r6 (a2)  
r7 (a3)  
r8 (t0)  
r9 (t1)  
(c) Program Counter  
PC  
r10 (t2) r10 (t2) r10 (t2) r10 (t2) r10 (t2) r10 (t2) r10 (t2) r10 (t2)  
r11 (t3) r11 (t3) r11 (t3) r11 (t3) r11 (t3) r11 (t3) r11 (t3) r11 (t3)  
r12 (t4) r12 (t4) r12 (t4) r12 (t4) r12 (t4) r12 (t4) r12 (t4) r12 (t4)  
r13 (t5) r13 (t5) r13 (t5) r13 (t5) r13 (t5) r13 (t5) r13 (t5) r13 (t5)  
r14 (t6) r14 (t6) r14 (t6) r14 (t6) r14 (t6) r14 (t6) r14 (t6) r14 (t6)  
r15 (t7) r15 (t7) r15 (t7) r15 (t7) r15 (t7) r15 (t7) r15 (t7) r15 (t7)  
r16 (s0) r16 (s0) r16 (s0) r16 (s0) r16 (s0) r16 (s0) r16 (s0) r16 (s0)  
r17 (s1) r17 (s1) r17 (s1) r17 (s1) r17 (s1) r17 (s1) r17 (s1) r17 (s1)  
r18 (s2) r18 (s2) r18 (s2) r18 (s2) r18 (s2) r18 (s2) r18 (s2) r18 (s2)  
r19 (s3) r19 (s3) r19 (s3) r19 (s3) r19 (s3) r19 (s3) r19 (s3) r19 (s3)  
r20 (s4) r20 (s4) r20 (s4) r20 (s4) r20 (s4) r20 (s4) r20 (s4) r20 (s4)  
r21 (s5) r21 (s5) r21 (s5) r21 (s5) r21 (s5) r21 (s5) r21 (s5) r21 (s5)  
r22 (s6) r22 (s6) r22 (s6) r22 (s6) r22 (s6) r22 (s6) r22 (s6) r22 (s6)  
r23 (s7) r23 (s7) r23 (s7) r23 (s7) r23 (s7) r23 (s7) r23 (s7) r23 (s7)  
r24 (t8) r24 (t8) r24 (t8) r24 (t8) r24 (t8) r24 (t8) r24 (t8) r24 (t8)  
r25 (t9) r25 (t9) r25 (t9) r25 (t9) r25 (t9) r25 (t9) r25 (t9) r25 (t9)  
r30 (fp) r30 (fp) r30 (fp) r30 (fp) r30 (fp) r30 (fp) r30 (fp) r30 (fp)  
r31 (ra) r31 (ra) r31 (ra) r31 (ra) r31 (ra) r31 (ra) r31 (ra) r31 (ra)  
Figure 2-5 CPU Registers  
2-5  
Chapter 2 CPU Architecture Overview  
„
General-Purpose Registers  
The TX19A core processor contains eight sets of general-purpose registers known as the “Shadow  
Register Sets” numbered 0 to 7. Each shadow set consists of 32 registers (r0 to r31), except that all  
the shadow sets have r0, r26, r27 and r28 in common and that shadow sets 1 to 7 have r29 in  
common. All the other general-purpose registers are available in each shadow set. Switching to a  
new shadow set is automatically done by processor hardware via interrupt or can be done with an  
instruction (MTC0).  
The 32-bit ISA instructions can use any of the general-purpose registers shown in Figure 2-5. The  
general registers are numbered from r0 to r31. The general registers except r0 have symbol names  
(software names) like v0-v1, a0-a3, and so on that are used by an assembler. The 32-bit ISA  
instructions treat the general registers symmetrically, with the exception of r0 and r31. r0 is  
hardwired to a value of 0. As such, r0 can be used by any instruction as a target register when the  
result of an operation is to be discarded or as a source register when a zero value is necessary. r31  
(ra: return address) is a link register used by Jump-and-Link, Branch-and-Link and Branch-Likely  
and-Link instructions. These instructions are to store an address, which shows the restarting point  
after a subroutine has been executed, in r31.  
In the 16-bit instructions, only eight of the 32 general-purpose registers are normally visible, r2 to  
r7, r16 and r17. Since the processor includes the full 32 registers of the 32-bit ISA mode,  
MIPS16e+ contains move instructions to copy values between the eight MIPS16e+ registers and the  
remaining 24 registers of the full MIPS architecture. Additionally, specific instructions implicitly  
reference r24 (t8), r28 (gp), r29 (sp), r30 (fp) and r31 (ra). r24 serves as a special condition code  
register for handling compare results. r28 is the global pointer register. r29 maintains the program  
stack pointer. r30 is the frame pointer register. r31 is the link register.  
Note: Please do not use r1 while programming since r1 is reserved as a register for assembler.  
„
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Chapter 2 CPU Architecture Overview  
HI and LO Registers  
The HI and LO registers hold the results of integer multiply, divide, multiply-and-add and  
multiply-and-subtract operations. Integer multiply, multiply-and-add and multiply-and-subtract  
operations store the doubleword, 64-bit result, in the HI and LO registers. Integer divide operations  
store the quotient in the LO register and the remainder in the HI register. The MFHI, MFLO, MTHI  
and MTLO instructions are used to move data between the HI and the LO registers and the general  
registers.  
„
Program Counter (PC)  
The least-significant bit of the program counter is the ISA mode bit that determines the ISA mode  
instructions: 0 means 32-bit ISA and 1 means 16-bit ISA. ISA mode bit is not considered as a part  
of the address. The address of the on-going instruction is the total value of the entire 32 bit after  
erasing the least-significant bit.  
2.2.2 System Control Coprocessor (CP0) Registers  
The system control coprocessor, CP0, is an integral part of the TX19A processor. It has 17  
user-accessible registers shown in Figure 2-6.  
System  
Configuration  
Config Register  
Config2 Register  
BadVAddr Register  
Cause Register  
PRId Register  
Config1 Register  
Config3 Register  
Status Register  
EPC Register  
General  
Exception  
Processing  
ErrorEPC Register  
IER Register  
Count Register  
Compare Register  
SSCR Register  
Debug Register  
DEPC Register  
Debug Exception  
Processing  
DESAVE Register  
Figure 2-6 System Control Coprocessor (CP0) Registers  
The CP0 registers are classified into three groups: system configuration registers, general exception  
handling registers and debug exception handling registers. When the processor is in Kernel mode,  
the system control coprocessor instructions can always use the CP0 registers regardless of the  
setting of the CU0 bit in the Status register. If the processor is in User mode, the CP0 registers are  
accessible only when the CU0 bit is 1. Operating modes are explained in Section 2.7, Memory  
management Summary.  
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Chapter 2 CPU Architecture Overview  
Table 2-1 System Configuration Register  
Register Name  
Description  
Comfit､Config1､  
Config2､Config3  
System configurations, such as EJTAG and 16-bit ISA mode and cache configurations.  
Table 2-2 General Exception Handling Registers  
Description  
Register Name  
Bad virtual address that caused a virtual-to-physical address translation error.  
Read-only  
BadVAddr  
Status  
Cause  
Processor status, e.g., operating mode (User/Kernel), interrupt enable and other states.  
Cause of the last exception  
Exception program counter. Upper 31 bits of the address of the exception-causing  
instruction combined with the ISA mode bit.  
EPC  
Similar to the EPC register, except that ErrorEPC is used on Reset and NMI  
exceptions.  
ErrorEPC  
Count  
Compare  
PRId  
Acts as a timer, incrementing at 1/2 the rate of CPUCLK.  
Maintains a constant value compared against the Count register value.  
Processor revision identifier. Read-only  
IER  
Manipulates the interrupt enable/disable bit in the Status register.  
Indicates the previous and current shadow register sets.  
SSCR  
Table 2-3 Debug Exception Handling Registers  
Description  
Register Name  
Debug  
Cause and current status of a debug exception  
Debug exception program counter. Upper 31 bits of the address of the instruction that  
caused a debug exception, combined with the ISA mode bit.  
DEPC  
DESAVE  
Scratchpad register to save one of the general-purpose registers for context-switching  
2.3 32-Bit and 16-Bit ISA Modes  
The TX19A has two ISA modes, 16-bit and 32-bit. These operating conditions are respectively  
called as 16 bit ISA mode and 32 bit ISA mode. It provides an efficient run-time switching between  
16-bit and 32-bit ISA modes through an instruction. Programs will consist of procedures in 16-bit  
mode for density or in 32-bit mode for performance.  
The least-significant bit of the program counter (PC) is the ISA mode bit that determines the width  
of instructions: 0 means 32-bit ISA and 1 means 16-bit ISA. The JALX, JR, JRC or JALRC  
instructions can be used to switch from 32-bit mode to 16-bit mode or vice versa.  
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Chapter 2 CPU Architecture Overview  
When an exception occurs while the processor is in 16-bit mode, the processor automatically  
switches to 32-bit mode and saves the return address together with the ISA mode bit to the EPC,  
ErrorEPC or the DEPC register. The ERET instruction is used to jump back to the return address  
contained in the EPC or ErrorEPC register. In case of a debug exception, the DERET instruction is  
used to jump back to the return address contained in the DEPC register.  
The instruction set can be divided into the groups shown in Figure 2-7.  
32 Bit ISA  
16-Bit ISA  
Load and Store  
Load and Store  
Load Instructions  
Store Instructions  
SYNC Instructions  
Load Instructions  
Store Instructions  
SYNC Instructions*  
Computational  
Signed, Unsigned  
Computational  
Signed, Unsigned  
ALU Immediate Instructions  
Register-register Instructions  
Shift Instructions  
ALU Immediate Instructions  
Register-register Instructions  
Shift Instructions  
Multiply and Divide Instructions  
Saturate Instructions*  
Multiply and Divide Instructions  
Multiply-and-Add and  
Multiply-and-Subtract Instructions  
Multiply-and-Add Instructions*  
MAX and MIN Instructions *  
Sign-Extend and Zero-Extend Instructions*  
Bit-Field Instructions*  
Jump and Branch  
Jump Instructions  
Branch Instructions  
Branch-likely Instructions  
Bit Search Instructions*  
Jump and Branch  
Jump Instructions  
Branch Instructions  
Coprocessor  
System Control Coprocessor (CP0)  
Special  
Bit Manipulation*  
SAVE・RESTORE  
SYSCALL  
BREAK  
System Control Coprocessor (CP0)*  
SDBBP  
Special  
Trap Instructions  
* New instructions in the TX19A  
Figure 2-7 32-Bit and 16-Bit Instructions  
All the instruction length of 32-bit ISA is set as 32 bit. As a general rule, the instruction length of 16-bit  
ISA is set as 16 bit; however, it can be changed into 32 bit with a EXTEND instructions. The  
EXTEND instructions, of which bit size is 16, are consist of 5-bit opcodes and 11-bit immediate.  
In some cases, the 11-bit immediate field is replaced with an opcode. The EXTEND does not  
2-9  
Chapter 2 CPU Architecture Overview  
generate a MIPS machine instruction on its own, but16-bit immediate can be used by concatenating  
its immediate and an immediate of a subsequent instruction.  
The 16-bit ISA instruction with 32-bit instruction length is called EXTENDed instructions. The  
SYNC, ERET, DERET, WAIT, BS1F, MAX and MIN instructions are EXTENDed instructions  
and have no 16-bit equivalents.  
2.4 Coprocessors  
Coprocessors are secondary processors used to speed up operations by handling some of workload  
of the main CPU.  
The TX19A contains a system control coprocessor, CP0, which handles system configuration,  
exception handling and memory management. The basic capabilities of CP0 are incorporated into  
the processor core and the extended capabilities into the memory management unit (MMU).  
The CU0 bit in the Status register controls the usability of CP0 instructions in User mode.  
Coprocessor Unusable exception occurs due to CP0 instruction execution during a user-mode  
program when the CU0 bit is cleared. In Kernel and Debug modes, all CP0 instructions can be  
executed regardless of the setting of the CU0 bit.  
The CU [3:1] bits in the Status register control accesses to the respective coprocessors in User mode  
or in Kernel mode. Attempted execution of a coprocessor instruction causes a Coprocessor  
Unusable exception when its CU bit is cleared.  
The system control coprocessor (CP0) provides 17 user-visible registers. Chapter 8 gives a  
complete description of them.  
2.5 Pipeline Architecture  
The TX19A has a five-stage pipeline. That is, the execution of each instruction consists of five  
primary stages. Each stage takes approximately one clock cycle; thus the execution of each  
instruction takes at least five cycles. (The JAL and JALX instructions in the 16-bit ISA mode take  
longer.) The five-stage pipeline divides the execution of each instruction into five discrete portions  
and executes up to five instructions simultaneously, as shown in Figure 2-8. The five pipe stages are  
Fetch (F), Decode (D), Execute (E), Memory Access (M) and Register Write-back (W). The  
TX19A achieves an instruction execution rate approaching one instruction per clock cycle.  
2-10  
Chapter 2 CPU Architecture Overview  
F
D
E
M
W
Instruction  
Fetch  
Memory  
Access  
Register  
Decode  
Execute  
Write-back  
Time  
#1  
#2  
#3  
#4  
#5  
F
D
F
E
M
E
D
F
W
M
E
D
F
W
M
E
W
M
E
D
F
W
M
D
W
1 Clock  
Cycle  
Current CPU Cycle  
Figure 2-8 TX19A Pipeline  
2.6 Write Buffer  
A write buffer is a FIFO buffer with 4 entries. As explained in the previous chapter, each pipeline  
stage takes one clock cycle if the ongoing instruction requires writing areas other than the on-chip  
memory. Bus cycle for writing to the area other than the on-chip memory not always takes only one  
clock. The write buffer function can improve performance during the program operation by  
coordinate the speed differences.  
2.6.1 Instructions for Write Buffer  
Here are the instructions for the write buffer which generates write bus cycle to memory.  
・ All the store instructions  
32ISA: SW / SH / SB / SWL / SWR  
16ISA: SW / SH / SB  
・ A part of bit computational instructions, memory operand addition  
32ISA: none  
16ISA: BCLR / BSET / BINS  
・ Others  
32ISA: none  
16ISA: ADDMIU / SAVE  
Note: Please refer to Appendix A”32-Bit ISA Details” and Appendix B “16-Bit ISA Details” for further details.  
2-11  
Chapter 2 CPU Architecture Overview  
2.6.2 Instruction Procedure  
At the execution of the instruction to use the write buffer, a bus operation required for executing the  
instruction is placed in the write buffer. We call it as “entry in the write buffer”. The entry in the  
write buffer is executed in the order corresponding to instruction execution.  
When the write buffer has free space, it enters the bus operation if the instruction to use the write  
buffer is in the Execute (E) stage. The bus cycle and the entry in the write buffer starts  
simultaneously if there is no bus cycle executed in operand bus at that time, which means operand  
bus has free space. When the write buffer has no free space, the instruction stalls in the E stage until  
it gains appropriate free space.  
The earlier the operation is entered in the write buffer, the earlier it is executed when there is a free  
operand bus. The order will never be changed in the write buffer. The write bus cycle cannot be  
executed when there is no free operand bus. In case a subsequent instruction such as the LOAD  
requests the read bus cycle, the instruction stalls in the E stage until all the operations entered in the  
write buffer are completed.  
Figure 2-9 shows the procedure of the write buffer instruction. In this case, the third one is the  
LOAD instruction. Therefore the read bus cycle caused by the LOAD will not be executed as long  
as the write cycle during the write buffer operation is completed.  
Write cycle  
STORE 1  
Write cycle  
STORE 2  
Read cycle  
LOAD 3  
Bus cycle  
Write buffer  
STORE 1 sw r10,0x0000(r16)  
STORE 2 sw r11,0x0004(r16)  
LOAD 3 lw r20,0x0008(r16)  
F
D
F
E
D
F
M
E
W
M
W
D
Es  
Es  
Es  
Es  
E
--  
M
W
Stall cycle  
Figure 2-9 The procedure of the write buffer instruction  
2.6.3 Bit Computational Instructions/ ADDMIU Instructions  
The instructions accompanied by an operand read such as a bit computational or an ADDMIU  
instructions initiate the operand read bus cycle. The read bus cycle and the write bus cycle are  
always executed in succession since these cycles must be united as a read modify write operation.  
In this case, the write cycle of the bit computation gets priority over the subsequent instructions.  
Figure 2-10 shows the procedure of the bit computational instruction.  
2-12  
Chapter 2 CPU Architecture Overview  
Instruction 1  
Write cycle  
Instruction 2  
Read cycle  
Read cycle  
Bus cycle  
Write buffer  
F
Instruction 1 bset 0x00(fp),0  
Instruction 2 lw r20,0x0004(r22)  
D
F
E
D
M
W
Es  
Es  
Es  
Es  
E
--  
M
W
Stall cycle  
Figure 2-10 The procedure of the bit computational instruction  
2.6.4 SAVE Instruction  
The SAVE instruction can generate multiple stores. The write buffer starts to enter the save  
instructions from the earlier store. In the meantime, the SAVE instruction can occupy the execution  
stage; that is to say no operation caused by other instructions will be entered in the write buffer.  
2.6.5 SYNC Instructions  
With the SYNC instruction, all the write bus operations entered in the write buffer to maintain the  
consistency of memory data are executed. The SYNC instruction is effective to synchronize the  
condition of memory or IO with the instruction operation since this instruction stalls until all the  
bus cycle caused by the entered operations are completed.  
The contents in the write buffer are never automatically flashed when Interrupt/ Exception takes  
place or bus is opened. Consistency must be maintained by the SYNC instruction depend on the  
situation.  
2-13  
Chapter 2 CPU Architecture Overview  
2.7 Memory Management Summary  
The TX19A has two modes of operation, User mode and Kernel mode. The TX19A enters Kernel  
mode whenever an exception is taken. Since a reset exception occurs when a system is reset, the  
TX19A wakes up in Kernel mode. The processor switches to User mode when the ERET  
(Exception Return) or DERET (Debug Exception Return) instruction is executed.  
Kernel Mode  
User Mode  
Exception  
• System Programs  
• Application Programs  
• Operating System Routines  
Return from Exception  
• General Exception Handlers  
• ERET instruction  
• Debug Exception Handlers, etc  
• DERET instruction  
(Debug Processing)  
Figure 2-11 Operating Modes  
The operating mode determines the addresses, registers and instructions that are available to a  
program. Kernel mode has higher privileges than User mode. Kernel-mode programs are permitted  
to use all addresses, registers and instructions, but a User-mode program’s use of them are restricted.  
Operating system routines, general exception handlers and debug exception handlers are executed  
in Kernel mode. This scheme allows the kernel to protect system resources from uncontrolled  
access.  
Note: TX19A only allows using Kernel mode.  
2-14  
Chapter 2 CPU Architecture Overview  
The TX19A does not contain a translation lookaside buffer (TLB). Instead, the memory  
management unit (MMU) of the TX19A uses the direct segment mapping method. The mapping of  
virtual addresses to physical addresses is shown in Figure 2-12. The virtual address space is  
partitioned into four, fixed-size segments. kuseg is designed to be used by User-mode programs  
while it is accessible in Kernel mode. The other three segments, kseg0, kseg1 and kseg2, are  
available only to Kernel-mode programs. Chapter 6 describes the memory management features in  
greater details.  
Virtual Address Space  
16 MB Reserved  
Physical Address Space  
16 MB Reserved  
0xFFFF_FFFF  
0xFFFF_FFFF  
0xC000_0000  
Kernel Segment 2  
kseg2  
Kernel Segment 2  
kseg2 (1 GB)  
0xC000_0000  
0xA000_0000  
0x8000_0000  
Kernel Segment 1  
kseg1  
16 MB Reserved  
Kernel Segment 0  
kseg0  
Kernel/User Segment  
kuseg (2 GB)  
16 MB Reserved  
0x4000_0000  
Kernel/User Segment  
kuseg  
Unavailable  
512 MB  
0x2000_0000  
0x0000_0000  
0x0000_0000  
Figure 2-12 Virtual-to-Physical Address Mapping  
2-15  
Chapter 3 32-Bit ISA Summary and Programming  
Tips  
Chapter 3 32-Bit ISA Summary and Programming Tips  
This chapter gives an overview of the instructions and addressing modes supported by the TX19A in  
32-bit ISA mode. This chapter also presents many programming tips using 32-bit instructions.  
Instructions are grouped into the following categories:  
z Load and store instructions  
z Computational instructions  
z Jump, branch and branch-likely instructions  
z System control coprocessor (CP0) instructions  
z Special instructions  
3.1 Instruction Formats  
All TX19A instructions for the 32-bit ISA mode are 32-bits wide. There are three instruction formats  
as shown in Figure 3-1. Limiting instruction formats to these three dramatically simplifies instruction  
decoding. More complex instructions are synthesized by the compiler. All the 32-bit instructions  
must be aligned on a word boundary.  
I-Type (Immediate)  
31  
2625  
2120  
16 15  
0
0
0
op  
rs  
rt  
immediate  
J-Type (Jump)  
31 26 25  
op  
target  
R-Type (Register)  
31  
2625  
2120  
1615  
11 10  
6 5  
op  
rs  
rt  
rd  
shamt  
funct  
op  
rs  
rt  
6-bit operation code  
5-bit source register specifier  
5-bit target register specifier or branch condition  
16-bit immediate, or branch or address displacement (offset)  
26-bit jump target address  
immediate  
target  
rd  
5-bit destination register specifier  
5-bit shift amount  
shamt  
funct  
6-bit function code  
Figure 3-1 Instruction Formats  
3-1  
Chapter 3 32-Bit ISA Summary and Programming Tips  
3.2  
Load and Store Instructions  
Load and store instructions move data between memory and CPU general registers. Load and store  
instructions can only load from memory into registers or store registers into memory locations. There  
is no direct way of doing arithmetic or logical operations between registers and the contents of  
memory.  
3.2.1 Load and Store Address Calculation  
In 32-bit ISA mode, all load and store instructions are encoded as I-type instructions. They generate  
effective addresses using register indirect with offset addressing mode, as shown in Figure 3-2. The  
16-bit immediate is sign-extended to 32 bits and added to the contents of a general-purpose register to  
generate the effective address. For example, in the instruction  
LW r9,4(r8)  
4 (binary 0100) is the offset, r8 is a general-purpose register containing the base address, and r9 is the  
target register.  
This addressing mode shown in figure 3-2 can be used to implement immediate addressing using r0 as  
the base register or register direct addressing using an offset value of zero.  
Memory  
Base Register  
32-Bit Address  
16-Bit Offset  
16-Bit  
Ø
Sign Extension  
+
Figure 3-2 Register Indirect with Offset Addressing  
3.2.2 Load and Store Instructions for Aligned Accesses  
Table 3-1 gives the load and store instructions to perform byte, halfword and word accesses. The LB  
and LH instructions sign-extend the loaded byte and halfword. The LBU and LHU instructions,  
which have the “U” (unsigned) suffix, zero-extend the loaded byte and halfword.  
3-2  
Chapter 3 32-Bit ISA Summary and Programming  
Tips  
Table 3-1 Load and Store Instructions for Aligned Accesses  
Data Type  
Unsigned Load  
Signed Load  
Store  
Byte  
LBU  
LHU  
LW  
LB  
LH  
—
SB  
SH  
SW  
Halfword  
Word  
3.2.3 Load and Store Instructions for Misaligned Accesses  
An Address Error exception occurs when an instruction to load or store halfword or word that is not  
aligned on the natural alignment boundary is executed. Table 3-2 gives the instructions to perform  
loads and stores when the bytes in a word cross the natural boundary between two words. The LWL  
(Load Word Left) and LWR (Load Word Right) instructions are used in a pair. Likewise, the SWL  
(Store Word Left) and SWR (Store Word Right) instructions are used in a pair. These instructions  
provide a more efficient way of dealing with misaligned data than using a sequence of load/store and  
shift operations. They are useful for reusing old programs written for 8- and 16-bit machines.  
Table 3-2 Load and Store Instructions for Misaligned Accesses  
Signed Load  
Store  
Left (Upper Bytes)  
Right (Lower Bytes)  
LWL  
LWR  
SWL  
SWR  
3.2.4 Memory Synchronization Instruction  
The memory synchronization instruction, SYNC, guarantees the sequence of memory references by  
interlocking the instruction pipeline until loads, stores and instruction fetches performed prior to the  
present instruction are completed before loads or stores after this instruction are allowed to start.  
3.2.5 32-Bit Address Generation  
In 32-bit ISA mode, load and store instructions can only take a 16-bit signed immediate as an offset.  
The most-significant bit is the sign. A total of 15 bits designate the magnitude. This gives a range of  
-32768 to +32767. If the offset is outside this range, you must put it in a general register prior to the  
load or store instruction. Three examples are given below.  
z Example 1: Base address + 32-bit offset  
In the example below, the ADDU (Add Unsigned) instruction is used to add the offset held in register  
r5 to the base address in register r4. The result is placed back into r4. Then the LW instruction uses r4  
as the base register to address a memory location.  
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Chapter 3 32-Bit ISA Summary and Programming Tips  
ADDU  
LW  
r4,r4,r5  
r6,0(r4)  
z Example 2: Base address + 32-bit offset  
In the example below, the LUI (Load Upper Immediate) instruction loads the 16-bit immediate (in  
this case, the upper 16 bits of the offset) into the upper 16 bits of register r5. The lower 16 bits of r5  
are filled with zeros. Then ADDU (Add Unsigned) instruction is used to add r5 to the base address in  
r4. This way, the LW instruction can address a desired memory location by only using the lower 16  
bits of the offset.  
LUI  
ADDU  
LW  
r5,0x12  
r4,r4,r5  
r6,0x3454(r4)  
z Example 3: Arbitrary 32-bit absolute address  
In the example below, the LUI (Load Upper Immediate) instruction loads the 16-bit immediate into  
the upper 16 bits of register r4. The ADDIU (Add Immediate Unsigned) instruction adds r4 to the  
lower 16 bits of the offset, 0x3456. The LW instruction can then use r4 to directly address the desired  
memory location, with an offset of zero.  
LUI  
ADDIU r4,r4,0x3456  
LW r6,0(r4)  
r4,0x12  
0
0
0
0
1
0
2
0
0
3
0
4
0
5
0
6
LUI r4,0x12  
ADDIU  
3
4
5
6
0
0
1
2
3.3 Computational Instructions  
This section describes the computational instructions available in the 32-bit ISA. Section 3.3.1  
provides a category of computational instructions. Section 3.3.2 discusses computations that involve  
the use of 32-bit constants. Section 3.3.3 gives program examples to illustrate how to perform 64-bit  
addition and subtraction. In Section 3.3.4, we observe how to detect the integer overflow without  
using exception. In Section 3.3.5, we look at ways to execute a 64-bit x 64-bit multiply operation.  
Section 3.3.6 describes how to implement rotate operations using available instructions.  
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Chapter 3 32-Bit ISA Summary and Programming  
Tips  
3.3.1 Overview of Computational Instructions  
Computational instructions in the 32-bit ISA are categorized into five groups shown in Table 3-3.  
They consist of arithmetic, compare, logical, shift, multiply, divide and multiply-and-add instructions.  
Computational instructions use I-type format in which one operand is a 16-bit immediate or R-type  
format which take two or three register operands.  
Table 3-3 Computational Instructions  
Category  
Instructions  
Opcode  
ADDI・ADDIU  
ALU Immediate  
Add  
SLTI・SLTIU  
Set On Less Than  
Logical AND  
Logical OR  
ANDI  
ORI  
Logical XOR  
Load Upper Immediate  
Add  
XORI  
LUI  
ADD・ADDU  
SUB・SUBU  
2- and 3-Operand  
Register-Type  
Subtract  
SLT・SLTU  
Set On Less Than  
Logical AND  
Logical OR  
AND  
OR  
Logical XOR  
Logical NOR  
Count  
XOR  
NOR  
CLO・CLZ  
MOVN・MOVZ  
SLL・SLLV・SRL・SRLV  
SRA・SRAV  
Conditional Move  
Logical Shift  
Arithmetic Shift  
Multiply  
Shift  
MULT・MULTU・MUL  
DIV・DIVU  
Multiply and Divide  
Divide  
MFHI・MFLO・MTHI・MTLO  
MADD・MADDU・MSUB・MSUBU  
Move From/To HI/LO  
Multiply-and-Add and Multiply-and-Subtract  
In ALU immediate instructions, the source operands are a general-purpose register and a 16-bit  
signed immediate. For example, the Add Immediate instruction, "ADDI rd, rs, immediate," adds the  
contents of the source register (rs) and the sign-extended immediate, then places the result into the  
destination register (rd).  
Two- and three-operand Register-type instructions manipulate the values held in two general purpose  
registers and place the result into a general-purpose register.  
Shift instructions shift the contents of a general-purpose register right or left by the specified  
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Chapter 3 32-Bit ISA Summary and Programming Tips  
number of bits. There are two kinds of shift: logical and arithmetic. The Shift Variable instructions  
(SLLV, SRLV, and SRAV) do not have the shift amount (shamt) field; instead they specify a general  
purpose register containing a desired shift amount.  
Multiply and divide instructions operate on integer values in two general-purpose registers and place  
the result into special registers HI and LO. Generally, CPU instructions do not have access to the HI  
and LO registers. In the MIPS architecture, the MFHI, MFLO, MTHI and MTLO instructions are  
always required to move data between a general-purpose register and the HI or LO register. However,  
the TX19A provides an extension to the MIPS architecture to allow the lower 32 bits of the product to  
be placed into both the LO register and a general-purpose register at a time. Section 3.3.5, 64-Bit x  
64-Bit Multiplication, presents an application example of this extension.  
Multiply-and-add and multiply-and-subtract instructions multiply two 32-bit numbers, followed by  
the addition/subtraction of this product to/from the 64-bit value in the HO/LO registers. The lower 32  
bits of the result can be optionally copied into a general-purpose register simultaneously. The MAC  
unit executes the integer multiply-and-add and multiply-and-subtract operations at an accelerated  
speed. It is designed to provide a common set of digital signal processing (DSP) operations.  
3.3.2 32-Bit Constants  
The immediate field in the I-type instructions is only 16-bits long. If the immediate value is greater  
than 16 bits, you need to use two instructions to create a 32-bit constant and put it in a general register  
temporarily. In the example below, the LUI (Load Upper Immediate) instruction loads the immediate  
value into the upper 16 bits of r4 and fills the lower 16 bits with zeros. The ORI (OR Immediate)  
instruction zero-extends the immediate value, logical-ORs it with the contents of r4 and places the  
result back into r4.  
LUI  
ORI  
r4,0x12  
r4,r4,0x3456  
0
0
0
0
1
0
2
LUI r4,0x12  
0
3
0
4
0
5
0
6
0
ORI  
2
3
4
5
6
0
0
1
The following is an example of adding a 32-bit constant to the contents of a general register. The LUI  
instruction loads the upper 16 bits of r5 with 0x1234 and sets the lower 16 bits to 0x0000. Adding it to  
0x5678 with the ADDIU (Add Immediate Unsigned) instruction gives 0x12345678 that is placed  
back into r5. Finally, the ADDU (Add Unsigned) instruction adds the contents of r4 and r5 together  
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Chapter 3 32-Bit ISA Summary and Programming  
Tips  
and puts the result in r6.  
LUI  
r5,0x1234  
ADDIU r5,r5,0x5678  
ADDU r6,r4,r5  
Note: The ADDI and SLTI instructions sign-extend the immediate value to 32 bits. Although ADDIU  
and SLTIU stand for Add Immediate Unsigned and Set On Less Than Immediate Unsigned, they also  
sign-extend the immediate value to 32 bits. The only difference between the ADDI and ADDIU  
instructions is that ADDIU never causes an overflow exception. Therefore, you can use the ADDIU  
instruction to add a negative number to the contents of a general register without being worried about  
a possible overflow. It is useful since there is no Subtract Immediate instruction in the instruction set.  
The only difference between the SLTI and SLTIU instructions is that SLTI compares two values (rs  
and sign-extended immediate) as signed integers while SLTIU compares two values (rs and  
sign-extended immediate) as unsigned integers.  
3.3.3 64-Bit Addition and Subtraction  
In some cases, the numbers being added or subtracted can be more than 32-bits long. Since general  
purpose registers are only 32-bits wide, it is the job of the programmer (or the compiler) to write the  
code to break down large numbers into smaller chunks to be processed by the CPU. Figure 3–3  
illustrates this. In Figure 3–3, r3 contains the upper 32 bits of a 64-bit constant, and r2 contains the  
lower 32 bits of that 64-bit constant. Likewise, r5 and r4 together contain a 64-bit constant.  
r3  
r2  
r5  
r4  
r11  
r10  
±
Ö
Figure 3-3 64-Bit Addition and Subtraction  
Add with Carry  
Below is an example of code to add two 64-bit constants together:  
ADDU r10,r2,r4 # r10 ← r2 + r4  
SLTU r11,r10,r2 # r11=1 if r10 (sum) is less than r2  
ADD(U) r11,r11,r3 # r11 ← r11 (carry) + r3  
ADD(U) r11,r11,r5 # r11 ← r11 + r5  
The first ADDU instruction adds the lower 32 bits of two constants together and puts the result in r10.  
The TX19A architecture does not provide a flag bit to indicate whether an arithmetic operation results  
in a carry-out. Therefore, it is necessary to somehow record an occurrence of a carry-out resulting  
from an addition. In the case of two positives together, a carry-out occurred if the sum is less than one  
of the operands added. Then the next SLTU (Set on Less Than Unsigned) instruction sets r11 to 1 if  
r10 is less than r2. The following two ADD(U) instructions add the carry-out bit (1 or 0) and the upper  
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Chapter 3 32-Bit ISA Summary and Programming Tips  
32 bits of the two 64-bit constants.  
The last two instructions can be either ADD or ADDU. The only difference between these two  
instructions is that ADDU (Add Unsigned) never causes an integer overflow exception. When you  
use the ADDU instruction, you need to write the code to explicitly test for an occurrence of the  
overflow condition. This is discussed in the next section.  
„
Subtract with Borrow  
In 64-bit subtraction, the code must take care of the borrow of the lower operand. The technique for  
performing subtract-with-borrow is quite similar to add-with-carry. Below is an example of code to  
subtract a 64-bit constant from a 64-bit constant.  
SLTU r8,r2,r4 # r8=1 if r2 is less than r4  
SUBU r10,r2,r4 # r10 ← r2 – r4  
SUB(U) r11,r3,r5 # r11 ← r3 – r5  
SUB(U) r11,r11,r8 # r11 ← r11 - r8 (borrow)  
First of all, the SLTU instruction checks if r2 (minuend) is smaller than r4 (subtrahend). If it is, r8 is  
set to 1. That is, if there is a borrow resulting from the subtraction of the lower 32 bits, its occurrence  
is recorded in r8. The content of r8 is subtracted in the last SUB(U) instruction.  
Again, the only difference between the SUB and SUBU instructions is that SUBU (Subtract  
Unsigned) never causes an integer overflow exception.  
3.3.4 Testing for an Integer Overflow  
As explained in the previous section, the signed add and subtract instructions, ADD and SUB,  
generate an overflow exception if the addition/subtraction resulted in a two’s-complement overflow.  
On the other hand, the unsigned add and subtract instructions, ADDU and SUBU, never cause an  
overflow exception. If it is necessary to detect signed overflow without using exceptions or to detect  
overflow for unsigned operations, you need to write a software routine to check for overflow.  
It should be observed that, during addition, overflow occurs if the signs of the operands are the same  
and the sign of the sum is different. Below is an example of code that checks for overflow resulting  
from signed addition:  
ADDU r2,r3,r4 # r2 ← r3 + r4, no exception  
XOR r5,r3,r4 # Compare signs of r3 and r4; if different,  
# no overflow (r5 < 0)  
BLTZ r5, No_Ov # Branch on less than zero  
XOR r5,r2,r3 # Compare signs of sum and operand; if different,  
# overflow occurred (r5 < 0)  
BLTZ r5,Ov # Branch on less than zero  
No_Ov:  
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Chapter 3 32-Bit ISA Summary and Programming  
Tips  
During subtraction, overflow occurs if the signs of the operands are not the same and the sign of the  
remainder is not the same as the sign of the minuend. Below is an example of code that checks for  
overflow resulting from signed subtraction:  
SUBU r2,r3,r4 # r2 ← r3 – r4  
XOR r5,r3,r4 # Compare signs of r3 and r4; if same, no  
# overflow occurred  
BGEZ r5,No_Ov # Branch on greater than or equal to zero  
XOR r5,r2,r3 # Compare signs of remainder and minuend; if  
# different, overflow occurred  
BLTZ r5,Ov # Branch on less than zero  
No_Ov:  
3.3.5 64-Bit x 64-Bit Multiplication  
In multiplying two integer numbers in the TX19A, they must be in general-purpose registers. In  
doubleword-by-doubleword multiplication, each 64-bit operand takes two registers since all general  
purpose registers are only 32-bits wide.  
In Figure 3-4, the upper 32 bits of the multiplicand is placed in r3 and the lower 32 bits of it is in r2.  
Likewise, the multiplier is put in r5 and r4.  
r3  
r2  
×
r5  
r4  
Ö
r11  
r10  
r2  
r4  
r3  
r5  
×
r4 × r2 (High)  
r4 × r3 (Low)  
r4 × r2 (Low)  
r4 × r3 (High)  
r5 × r2 (High)  
r5 × r3 (Low)  
r5 × r2 (Low)  
r5 × r3 (High)  
r11  
r10  
Figure 3-4 64-Bit x 64-Bit Multiplication  
The following shows an example of code that performs 64-bit by 64-bit multiplication. Although the  
product can be a maximum of 128-bits long, the code below only deals with the lower two words of the  
product for the sake of simplicity.  
MULTU r10,r2,r4 # r4 x r2, Copy low word of product to r10  
MFHI r11 # Copy high word of product to r11  
MULTU r9,r3,r4 # r3 x r4, Copy low word of product to r9  
ADDU r11,r11,r9 # r11 ← r11 + r9  
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Chapter 3 32-Bit ISA Summary and Programming Tips  
MULTU r9,r2,r5 # r5 x r1, Copy low word of product to r9  
ADDU r11,r11,r9 # r11 ← r11 + r9  
Note that there is a slight difference in the functionality of the MULTU (Multiply Unsigned)  
instruction between the MIPS and the TX19A architectures. In the MIPS processor, MULTU is a  
two-operand instruction that specifies two source registers holding the multiplicand and the  
multiplier. The 64-bit doubleword product is placed into the HI and LO registers. In the TX19A,  
however, the MULTU can take a third operand. In the TX19A, MULTU can optionally copy the  
low-order word of the product to a general-purpose register. This eliminates the need to use the  
MFLO (Move From LO) instruction to move the contents of the LO register to a general register.  
The MFHI (Move From HI) instruction moves the contents of the HI register, i.e., the high-order  
word of the product, to a general register.  
3.3.6 Rotate Instructions  
In the TX19A, there are no rotate instructions at the machine level although it has the shift  
instructions instead. In shift left, bits that exit the left end (the right end in the case of shift right) are  
discarded and zeros are supplied to the vacated bits on the right (on the left in the case of shift right).  
In rotate left, as bits are shifted from right to left (from left to right in the case of rotate right), they exit  
from the left end, MSB, and enter the right end, LSB, (the left end in the case of rotate right).  
In the TX19A, a rotate operation must be implemented using shift and logical-OR instructions.  
Figure 3-5illustrates how to do this.  
Rotate left six bits  
r8  
SLL r9,r8,6  
r9  
r8  
00 0000  
SRL r8,r8,(32-6)  
0000 0000 0000 0000 0000 0000 00  
OR  
r8,r8,r9  
r8  
Figure 3-5 Rotate Left by 6 Bits  
In Figure 3-5, the SLL (Shift Left Logical) instruction shifts the contents of r8 left by six bits and puts  
the result in r9. The low-order bits are filled with zeros. Next, the SRL (Shift Right Logical)  
instruction is used to shift r8 right by 26 (32-6) bits. Finally, the OR instruction logical-ORs the  
contents of r8 and r9 and puts the result back in r8. The outcome is equivalent to rotating r8 by six  
bits.  
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Chapter 3 32-Bit ISA Summary and Programming  
Tips  
3.4 Jump, Branch and Branch-Likely Instructions  
It is often necessary to transfer program control to a different location in the sequence of  
instructions. There are many instructions to achieve this. The TX19A provides jump, branch and  
branch-likely instructions. Section 3.4.1 overviews these instructions. Section 3.4.2 describes the  
addressing modes supported by the jump, branch and branch-likely instructions. Section 3.4.3  
explains how to switch from 32-bit ISA mode to 16-bit ISA mode, or vice versa. In Section 3.4.4,  
the differences between regular branch instructions and branch-likely instructions are explained.  
Section 3.4.5 provides programming tips for branching on arithmetic comparisons. Section 3.4.6  
describes a technique for jumping to 32-bit addresses. Section 3.4.7 describes subroutine calls and  
returns.  
3.4.1 Overview of Jump, Branch and Branch-Likely Instructions  
In the TX19A, jump instructions are used to unconditionally transfer program control to the target  
location whereas branch and branch-likely instructions are what many microprocessors call  
conditional jumps and are used to transfer control to a new location only when a certain condition is  
met. Table 3-4 and Table 3-5 show the opcodes of the jump, branch and branch-likely instructions in  
the 32-bit ISA.  
Table 3-4 Jump Instructions (32-Bit ISA)  
Opcode  
Name  
Addressing  
Format  
Paged absolute  
Paged absolute  
Paged absolute  
Register indirect  
Register indirect  
J
Jump  
I-type  
I-type  
I-type  
R-type  
R-type  
JAL  
Jump And Link  
JALX  
JR  
Jump And Link exchange  
Jump Register  
JALR  
Jump And Link Register  
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Chapter 3 32-Bit ISA Summary and Programming Tips  
Table 3-5 Branch and Branch-Likely Instructions (32-Bit ISA)  
Name Condition Addressing Format  
Opcode  
B
Unconditional Branch  
Branch And Link  
always  
always  
rs = rt  
rs ≠ rt  
rs > 0  
rs ≥ 0  
rs < 0  
rs ≤ 0  
rs < 0  
rs ≥ 0  
PC-relative  
PC-relative  
PC-relative  
PC-relative  
PC-relative  
PC-relative  
PC-relative  
PC-relative  
PC-relative  
PC-relative  
I-type  
I-type  
I-type  
I-type  
I-type  
I-type  
I-type  
I-type  
I-type  
I-type  
BAL  
BEQ(L)  
BNE(L)  
BGTZ(L)  
BGEZ(L)  
BLTZ(L)  
BLEZ(L)  
BLTZAL(L)  
Branch On Equal (Likely)  
Branch On Not Equal (Likely)  
Branch On Greater Than Zero (Likely)  
Branch On Greater Than or Equal To Zero (Likely)  
Branch On Less Than Zero (Likely)  
Branch On Less Than or Equal To Zero (Likely)  
Branch On Less Than Zero And Link (Likely)  
BGEZAL(L) Branch On Greater Than or Equal To Zero And Link (Likely)  
Jump-and-link instructions and branch-and-link instructions save a return address in register r31.  
They are typically used for subroutine calls.  
With the jump and regular branch instructions, the instruction immediately following the jump or  
branch is always executed while the target instruction is being fetched from memory. This is true to  
all regular branch instructions regardless of whether the branch is to be taken or not. On the other  
hand, branch-likely instructions execute the instruction in the delay slot only when the branch is  
taken; if the branch is not taken, the instruction in the delay slot is nullified. For the jump and  
branch delay slots, see Chapter 5, CPU Pipeline.  
3.4.2 Jump and Branch Address Calculation  
As shown in Table 3-4 and Table 3-5, jump, branch and branch-likely instructions compute the  
effective address of the next instruction using the following addressing modes.  
z Paged absolute  
z Register indirect  
z
PC-relative with offset  
Paged Absolute Addressing  
The J, JAL and JALX instructions unconditionally transfer program control to a target address using  
paged absolute addressing. They generate the next instruction address by shifting the 26-bit  
immediate operand by two bits and merging the resultant value with the four most-significant bits of  
the program counter (PC). Figure 3-6 shows how the jump target address is generated by paged  
absolute addressing. The target address for a jump is computed from the  
address of the instruction immediately following the jump instruction, i.e., the address of the jump  
delay slot. The four most-significant bits of the PC indicate a specific page in a 16-page address  
space.  
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Chapter 3 32-Bit ISA Summary and Programming  
Tips  
Jump Instruction  
Jump Delay Slot  
4 Bits  
26-Bit Immediate  
Jump Target Address  
00  
26-Bit Immediate  
Figure 3-6 Paged Absolute Addressing (32-Bit ISA Mode)  
„
Register Indirect Addressing  
The JR and JALR instructions unconditionally transfer program control to a target address using a  
32-bit absolute address held in a general-purpose register. The effective address is generated by  
clearing the least-significant bit of the specified target register to zero. Since instructions must be  
word-aligned, the JR and JALR instructions must specify a target register of which two  
least-significant  
bits are zero.  
0
Jump Target Address  
Target Register  
Figure 3-7 Register Indirect Addressing (32-Bit ISA Mode)  
„
PC-Relative with Offset Addressing  
All the branch and branch-likely instructions transfer program control to a target address using a  
PC-relative address. They generate the next instruction address by sign-extending and appending  
b’00 to the 16-bit immediate displacement (offset) operand, and adding the resultant value to the  
contents of the program counter (PC). Figure 3-8 shows how the branch target address is generated.  
The target address for a branch is computed from the address of the instruction immediately  
following the branch instruction, i.e., the address of the branch delay slot.  
Branch Instruction  
Program Counter (PC)  
Branch Delay Slot  
16-Bit Offset  
+
16-Bit Offset  
Sign Extension  
00  
Branch Target Address  
Figure 3-8 PC-Relative with Offset Addressing (32-Bit ISA Mode)  
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Chapter 3 32-Bit ISA Summary and Programming Tips  
3.4.3 Run-Time Switching of the ISA Modes  
The TX19A has two ISA modes, 16-bit ISA and 32-bit ISA. The TX19A provides for efficient  
runtime switching between 16-bit and 32-bit ISA modes through the JALX, JR and JALR  
instructions.  
The least-significant bit of the program counter (PC) is the ISA mode bit: 0 for the 32-bit ISA and 1  
for the 16-bit ISA. The JALX instruction unconditionally toggles the ISA mode bit (the  
least-significant bit) of the PC to switch to the other ISA. The JR and JALR instructions set the ISA  
mode bit from the least-significant bit of the register containing the jump address; a jump address is  
generated by masking off the ISA mode bit to zero.  
In 32-bit ISA mode, instructions must be word-aligned. Thus, when switching from 16-bit ISA  
mode to 32-bit ISA mode, the JR and JALR instructions must specify a target register of which two  
least-significant bits are zero. If these bits are one-zero (10), an Address Error exception will occur  
when the jump target instruction is fetched.  
In a jump delay slot of the JRLX, JR or JALR instruction, the instruction in the previous ISA mode  
is executed.  
Link instructions save the return address in either register r31 (ra) or another destination register (rd)  
specified. Its least-significant bit keeps the ISA mode in which processing resumes after a subroutine  
has been executed. Then the same ISA mode as the one prior to the subroutine is set after returning  
from subroutine.  
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Chapter 3 32-Bit ISA Summary and Programming  
Tips  
3.4.4 Branch-Likely Instructions  
All the jump and branch instructions occur with a delay of one instruction (two pipeline cycles)  
before the program flow can change because the processor must calculate the effective destination  
of the jump or branch and fetch that instruction. This delay is called jump or branch delay. The  
TX19A architecture gives responsibility of dealing with delay slots to software. The compiler or the  
assembler makes an attempt to reorder instructions to execute the instruction immediately following  
the jump or branch while the target instruction is being fetched from  
memory.  
There is no problem in the case of jump instructions since jumps "always" transfer program control  
to the target instruction; the instruction immediately following the jump can always fill the delay  
slot. However, with branch instructions, the processor never knows whether the branch will be taken  
or not; so the instruction in the delay slot must be the one that logically precedes the branch  
instruction. If the delay slot can not be filled with any useful instruction, a NOP (No Operation)  
instruction must be inserted to keep the instruction pipeline filled. (NOP is a pseudoinstruction  
accepted by the assembler; the assembler actually turns it into a shift instruction to r0 register with a  
shift amount of zero as described in Chapter 1.)  
The code in Figure 3-9 implements the task of setting register r2 to 1 or 0, depending on whether the  
value of r8 is equal to 0 or not. Because the ADDI instruction can not logically precede the BEQ  
instruction, a NOP instruction is required immediately following BEQ.  
Branch Taken Branch Not Taken  
1
BEQ  
NOP  
r8,r0,L0  
1
2
3
4
5
2
ADDI r2,r0,1  
J
L1  
NOP  
L0:  
3
4
6
ADD  
r2,r0,0  
L1:  
Figure 3-9 Regular Branch Instruction  
Contrast this to the code in Figure 3-10 in which the branch-likely version of Branch On Equal  
(BEQL) is used instead of BEQ. If a branch-likely is taken, the instruction in the delay slot is  
executed. If a branch-likely is not taken, the instruction in the delay slot is nullified, or killed. This  
eliminates the need to insert a NOP instruction in the delay slot, and thus helps to reduce code size  
and speed up branch processing.  
3-15  
Chapter 3 32-Bit ISA Summary and Programming Tips  
Branch Taken  
Branch Not Taken  
1
1
2
BEQL r8,r0,L0  
ADDI r2,r0,0  
ADDI r2,r0,1  
2
3
3
L0:  
Figure 3-10 Branch-Likely Instruction  
3.4.5 Branching on Arithmetic Comparisons  
The Branch On Equal (BEQ) and Branch On Not Equal (BNE) instructions, and their branch-likely  
versions (BEQL/BNEL) are the branch instructions that execute a branch based on the  
magnitude of two values in registers. For example,  
BEQ r2,r3,Equal  
compares the contents of registers r2 and r3 and branches to Equal if they are equal. However, there  
is no instruction to branch based on whether r2 is greater than r3. To perform such an arithmetic  
comparison on a pair of registers or between a register and an immediate value, you must use a  
sequence of two instructions. Three examples are given below: set-on-less-than instructions  
comparing two registers or a register and an immediate and a comparison between a register and an  
immediate. (Some assemblers provide macro instructions for branching on arithmetic comparisons.  
The assembler expands macro instructions into a sequence of machine instructions.)  
z Example 1: Branch if r6 ε r7  
The following sequence of instructions checks if the contents of r6 is equal to or greater than the  
contents of r7. If the contents of r6 is less than that of r7, the SLT (Set On Less Than) instruction sets  
r24 to 1.  
Otherwise, r24 is set to 0. The BEQ instruction branches for magnitude relation by detecting r24  
value with BEC instruction (Remember r0 is  
hardwired to a constant value of zero).  
SLT  
BEQ  
r24,r6,r7  
r24,r0,Label  
z Example 2: Branch if r7 ε 0x1234  
The following sequence of instructions checks if the contents of r7 is equal to or greater than  
0x1234 or not. In this example, the SLTI (Set On Less Than Immediate) instruction is used to  
compare the contents of a register against an immediate value.  
SLTI r24,r7,0x1234  
BEQ r24,r0,Label  
3-16  
Chapter 3 32-Bit ISA Summary and Programming  
Tips  
z Example 3: Branch if r7 ⎯ 0x1234  
The following sequence of instructions checks the equality of the contents of a register and an  
immediate value. In this example, the ORI (OR Immediate) instruction temporarily loads r10  
with 0x1234. Then the BEQ instruction compares the contents of r10 and the contents of  
r7.  
ORI r10,r0,0x1234  
BEQ r10,r7,Label  
3.4.6 Jumping to 32-Bit Addresses  
As explained in Section 3.4.2, in paged absolute addressing, the J, JAL and JALX instructions can  
only take a 26-bit immediate. Since it is shifted left by two bits, the address of the target must be  
within a 256M byte segment. To jump to an arbitrary 32-bit address, load the desired address into a  
register by using a sequence of the LUI and ORI instructions and then use the JR (Jump Register)  
instruction. The following code transfers program control to address 0x76543210.  
LUI r8,0x7654  
ORI r8,0x3210  
JR r8  
3.4.7 Subroutine Calls  
In the 32-bit ISA, there are Jump-And-Link (JAL, JALX, JALR), Branch-And-Link (BLTZAL,  
BGEZAL) and Branch-Likely-And-Link (BLTZALL, BGEZALL) instructions. These are typically  
used as subroutine calls, where the subroutine return address is stored into register r31 (ra). The  
JALR (Jump-And-Link Register) instruction can use any general-purpose register (rd) as the link  
register.  
All the above instructions place the address of the instruction following the delay slot into r31 (ra)  
or rd. Jump-And-Link instructions set the ISA mode in the least-significant bit of r31 or rd.  
To return from a subroutine, use the JR instruction. The ISA mode bit (i.e., the least-significant bit  
of the PC) is restored from the least-significant bit of the link register.  
When subroutines are nested, the calling subroutine must save the return address in the link register  
onto the stack before making the call so that it can be overwritten by the callee.  
3-17  
Chapter 3 32-Bit ISA Summary and Programming Tips  
Running Program  
Subroutine  
(3)  
(1)  
(2)Entry Address  
PC  
r31  
(4)  
Return Address  
Subroutine Call  
Delay Slot  
Return Point  
(6)  
JR r31  
(5) Return from Subroutine  
Figure 3-11 Subroutine Calls and Returns  
Jump, branch and branch-likely instructions with link except JAL and JALX have a source register  
(rs) field. For example, in the instruction  
BGEZAL r8,PSUB  
r8 is the source register; BGEZAL checks if the value in r8 is greater than or equal to zero.  
An exception or interrupt could prevent the completion of a legal instruction in the jump or branch  
delay slot. If that happens, the address of the jump, branch or branch-likely instruction that precedes  
it is set to the Exception Program Counter (EPC) register. After the exception or interrupt handler  
routine has been executed, processing restarts with the jump, branch or branch-likely instruction. To  
permit this, they must be restartable. Therefore, r31 (ra) must not be used as a source register. See  
Chapter 9 for the exception handling mechanism.  
3.5 Coprocessor Instructions  
The system control coprocessor (CP0) is implemented as an integral part of the TX19A. No other  
coprocessor such as CP1 and CP2 can be connected to the TX19A.  
Attempts to execute coprocessor instructions (except CP0 instructions) defined in the MIPS32 cause  
either the Reserved Instruction or Coprocessor Unusable exception. If the corresponding CU bit in  
the Status register is cleared, a Coprocessor Unusable exception is taken. If the CU bit is set, a  
Reserved Instruction exception is taken.  
The Load Word To Coprocessor (LWCz) and Store Word From Coprocessor (SWCz) instructions  
available with the 32 bit ISA are not supported by the TX19A. Attempts to execute these  
load/store instructions cause a Reserved Instruction exception.  
3-18  
Chapter 3 32-Bit ISA Summary and Programming  
Tips  
System control coprocessor (CP0) instructions perform operations on the CP0 registers to  
manipulate the system configuration, memory management and exception handling. Therefore, CP0  
is given somewhat protected status. The CU0 bit in the Status register controls the usability of CP0  
instructions in User mode. Attempts by a User-mode program to execute a CP0 instruction when the  
CU0 bit is cleared causes a Coprocessor Unusable exception. In Kernel and Debug modes, all CP0  
instructions can be executed, regardless of the setting of the CU0 bit. Table 3-7 shows the CP0  
instructions.  
Table 3-7 System Control Coprocessor (CP0) Instructions  
Name  
Opcode  
Move To/From CP0  
Exception Return  
MTC0・MFC0  
ERET  
Debug Exception Return  
Enter Standby Mode  
DERET  
WAIT  
The TX19A performs direct segment mapping of virtual to physical addresses. It does not provide  
support for a table lookaside buffer (TLB).  
3.6  
Special Instructions  
Special instructions allow software to initiate exceptions, i.e., to test for a particular condition in a  
running program. All special instructions are R-type. Special instructions include SYSCALL  
(System Call), BREAK (Breakpoint), SDBBP (Software Debug Breakpoint) and a set of trap  
instructions. Special instructions transfer program control to an appropriate exception handler. For  
details on exception processing, see Chapter 9.  
3-19  
Chapter 3 32-Bit ISA Summary and Programming Tips  
Instruction Summary  
This section provides an overview of the instructions in the 32-bit ISA.  
„
Notational Conventions  
In this section, all variable fields in an instruction format are shown in italicized lowercase letters,  
like rt, rs, rd, immediate and sa (shift amount). For the sake of clarity, an alias is sometimes used to  
refer to a field in the formats of specific instructions. For example, base and offset are used instead  
of rs and immediate in the formats of load and store instructions. HI and LO are the special registers  
that hold the results of integer multiply and divide operations.  
„
Extensions  
There are several instructions in the TX19A that are not part of the TX19 or TX39 architecture. For  
a complete list of differences in the instruction set between the TX19A, the TX19 and the TX39, see  
Appendix D.  
3-20  
Chapter 3 32-Bit ISA Summary and Programming  
Tips  
Table 3-8 Load and Store Instructions (32-Bit ISA)  
Instruction  
Format  
Operation  
The effective address is the sum base + offset. The 16-bit offset is  
Load Byte  
LB  
rt, offset(base)  
sign-extended. The byte in memory addressed by the EA is  
sign-extended and loaded into rt.  
The effective address is the sum base + offset. The 16-bit offset is  
Load Byte Unsigned LBU  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
sign-extended. The byte in memory addressed by the EA is zero  
extended and loaded into rt.  
The effective address is the sum base + offset. The 16-bit offset is  
Load Halfword  
LH  
sign-extended. The halfword in memory addressed by the EA is  
sign-extended and loaded into rt.  
The effective address is the sum base + offset. The 16-bit offset is  
Load Halfword  
Unsigned  
LHU  
sign-extended. The halfword in memory addressed by the EA is  
zero-extended and loaded into rt.  
The effective address is the sum base + offset. The 16-bit offset is  
sign-extended. The word in memory addressed by the EA is loaded  
Load Word  
LW  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
into rt.  
The effective address is the sum base + offset. The 16-bit offset is  
sign-extended. The left portion of rt is loaded with the appropriate  
Load Word Left  
Load Word Right  
Store Byte  
LWL  
LWR  
SB  
part of the high-order word in memory addressed by the EA.  
The effective address is the sum base + offset. The 16-bit offset is  
sign-extended. The right portion of rt is loaded with the appropriate  
part of the low-order word in memory addressed by the EA.  
The effective address is the sum base + offset. The 16-bit offset is  
sign-extended. The least-significant byte in rt is stored in memory  
addressed by the EA.  
The effective address is the sum base + offset. The 16-bit offset is  
sign-extended. The low-order halfword in rt is stored in memory  
Store Halfword  
SH  
addressed by the EA.  
The effective address is the sum base + offset. The 16-bit offset is  
Store Word  
SW  
rt, offset(base)  
rt, offset(base)  
sign-extended. rt is stored in memory addressed by the EA.  
The effective address is the sum base + offset. The 16-bit offset is  
sign-extended. The left portion of rt is stored into the appropriate part  
Store Word Left  
SWL  
of high-order word of memory addressed by the EA.  
The effective address is the sum base + offset. The 16-bit offset is  
sign-extended. The right portion of rt is stored into the appropriate  
Store Word Right  
Sync  
SWR  
rt, offset(base)  
part of low-order word of memory addressed by the EA.  
The instruction pipeline is interlocked until any load or store fetched  
SYNC  
before the current instruction is completed.  
3-21  
Chapter 3 32-Bit ISA Summary and Programming Tips  
Table 3-9 ALU Immediate Instructions (32-Bit ISA)  
Instruction  
Format  
Operation  
The sum rs + immediate is placed into rt. The 16-bit immediate is  
Add Immediate  
ADDI  
rt, rs, immediate  
sign-extended. Exceptions on 2’s-complement overflow.  
The sum rs + immediate is placed into rt. The 16-bit immediate is  
Add Immediate  
Unsigned  
ADDIU rt, rs, immediate  
sign-extended. Does not cause exception on 2’s-complement  
overflow.  
rt = 1 if rs is less than immediate; otherwise rt = 0. The 16-bit  
immediate is sign-extended. Two values are compared as signed  
Set On Less Than  
Immediate  
SLTI  
rt, rs, immediate  
integers.  
rt = 1 if rs is less than immediate; otherwise rt = 0. The 16-bit  
immediate is sign-extended. Two values are compared as unsigned  
Set On Less Than  
SLTIU rt, rs, immediate  
Immediate Unsigned  
integers.  
The contents of rs is ANDed with immediate and the result is placed  
AND Immediate  
OR Immediate  
ANDI  
ORI  
rt, rs, immediate  
rt, rs, immediate  
into rt. The 16-bit immediate is zero-extended.  
The contents of rs is ORed with immediate and the result is placed  
into rt. The 16-bit immediate is zero-extended.  
The contents of rs is exclusive-ORed with immediate and the result is  
Exclusive-OR  
Immediate  
XORI rt, rs, immediate  
placed into rt. The 16-bit immediate is zero-extended.  
The 16-bit immediate is shifted left by 16 bits and concatenated to 16  
bits of zeros. The result is placed into rt.  
Load Upper  
Immediate  
LUI  
rt, immediate  
Table 3-10 Two- and Three-Operand Register-Type Instructions (32-Bit ISA)  
Instruction  
Format  
Operation  
Add  
ADD  
rd, rs, rt  
The sum rs + rt is placed into rd. Exceptions on 2’s-complement  
overflow.  
The sum rs + rt is placed into rd. Does not cause exception on  
2’s-complement  
Add Unsigned  
ADDU rd, rs, rt  
overflow.  
The remainder rs - rt is placed into rd. Exceptions on 2’s-complement  
Subtract  
SUB  
rd, rs, rt  
overflow.  
The remainder rs - rt is placed into rd. Does not cause exception on  
2’scomplement  
Subtract Unsigned  
SUBU rd, rs, rt  
overflow.  
rd = 1 if rs is less than rt; otherwise rd = 0. Two values are compared  
Set On Less Than  
SLT  
rd, rs, rt  
as signed integers.  
rd = 1 if rs is less than rt; otherwise rd = 0. Two values are compared  
Set On Less Than  
Unsigned  
SLTU rd, rs, rt  
as unsigned integers.  
The contents of rs is ANDed with the contents of rt and the result is  
AND  
AND  
OR  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs  
placed into rd.  
The contents of rs is ORed with the contents of rt and the result is  
OR  
placed into rd.  
The contents of rs is exclusive-ORed with the contents of rt and the  
Exclusive-R  
NOR  
XOR  
NOR  
CLO  
result is placed into rd.  
The contents of rs is NORed with the contents of rt and the result is  
placed into rd.  
rs scanned from bit 31 to bit 0. The number of leading ones is  
* Count Leading  
Ones in Word  
counted and the result is placed into rd.  
rs scanned from bit 31 to bit 0. The number of leading zeros is  
counted and the result is placed into rd.  
* Count Leading  
Zeros in Word  
CLZ  
rd, rs  
3-22  
Chapter 3 32-Bit ISA Summary and Programming  
Tips  
* Ｍover Conditional ＭOVN rd, rs, rt  
If rt ≠ 0, the contents of rs is placed into rd.  
If rt = 0, the contents of rs is placed into rd.  
on Not Zero  
ＭOVZ rd, rs, rt  
* Move Conditional  
on Zero  
* Enhancements from the TX19 to the TX19A  
3-23  
Chapter 3 32-Bit ISA Summary and Programming Tips  
Table 3-11 Shift Instructions (32-Bit ISA)  
Instruction  
Format  
Operation  
The contents of rt is shifted left by sa bits. Zeros are supplied to the  
Shift Left Logical  
SLL  
rd, rt, sa  
vacated positions on the right. The result is placed into rd.  
The contents of rt is shifted left by the number of bits specified by the  
five least-significant bits of rs. Zeros are supplied to the vacated  
Shift Left Logical  
Variable  
SLLV  
rd, rt, rs  
positions on the right. The result is placed into rd.  
The contents of rt is shifted right by sa bits. Zeros are supplied to the  
Shift Right Logical  
SRL  
rd, rt, sa  
rd, rt, rs  
vacated positions on the left. The result is placed into rd.  
The contents of rt is shifted right by the number of bits specified by the  
five least-significant bits of rs. Zeros are supplied to the vacated  
Shift Right Logical  
Variable  
SRLV  
positions on the left. The result is placed into rd.  
The contents of rt is shifted right by sa bits. The sign bit is copied to  
Shift Right Arithmetic SRA  
rd, rt, sa  
rd, rt, rs  
the vacated positions on the left. The result is placed into rd.  
The contents of rt is shifted right by the number of bits specified by the  
five least-significant bits of rs. The sign bit is copied to the vacated  
Shift Right Arithmetic SRAV  
Variable  
positions on the left. The result is placed into rd.  
Table 3-12 Multiply and Divide Instructions (32-Bit ISA)  
Instruction  
Format  
Operation  
The multiplicand is the signed value of rs. The multiplier is the signed  
value of rt. The low-order 32 bits of the product is placed into rd. The  
* Multiply  
MUL  
rd, rs, rt  
values of registers HI and LO become undefined.  
The multiplicand is the signed value of rs. The multiplier is the signed  
value of rt. The 64-bit product rs * rt is placed into registers HI and  
LO. The low-order 32 bits of the product can be optionally copied into  
Multiply  
MULT  
(rd,) rs, rt  
rd.  
The multiplicand is the unsigned value of rs. The multiplier is the  
unsigned value of rt. The 64-bit product rs * rt is placed into registers  
HI and LO. The low-order 32 bits of the product can be optionally  
Multiply Unsigned  
MULTU (rd,) rs, rt  
copied into rd.  
The dividend is the signed value of rs. The divisor is the signed value  
of rt. The quotient is placed into register LO and the remainder is  
Divide  
DIV  
rs, rt  
rs, rt  
placed into register HI.  
The dividend is the unsigned value of rs. The divisor is the unsigned  
value of rt. The quotient is placed into register LO and the remainder  
Divide Unsigned  
DIVU  
is placed into register HI.  
Move From HI  
Move From LO  
Move To HI  
MFHI  
MFLO  
MTHI  
MTLO  
rd  
rd  
rs  
rs  
The contents of register HI is copied to rd.  
The contents of register LO is copied to rd.  
The contents of rs is copied to register HI.  
The contents of rs is copied to register LO.  
Move To LO  
* Enhancement from the TX19 to the TX19A  
3-24  
Chapter 3 32-Bit ISA Summary and Programming  
Tips  
Table 3-13 Multiply-and-Add Instructions (32-Bit ISA)  
Instruction  
Format  
Operation  
The multiplicand is the signed value of rs. The multiplier is the signed  
value of rt. The 64-bit product rs * rt is added to the contents of  
registers HI and LO and the result is placed back into HI and LO. The  
Multiply and Add  
MADD  
(rd,) rs, rt  
low-order 32 bits of the result can be optionally copied to rd.  
The multiplicand is the unsigned value of rs. The multiplier is the  
unsigned value of rt. The 64-bit product rs * rt is added to the  
contents of registers HI and LO and the result is placed back into HI  
and LO. The low-order 32 bits of the result can be optionally copied  
Multiply and Add  
Unsigned  
MADDU (rd,) rs, rt  
to rd.  
The multiplicand is the signed value of rs. The multiplier is the signed  
value of rt. The 64-bit product rs * rt is subtracted from the contents  
of registers HI and LO and the result is placed back into HI and LO.  
* Multiply and  
MSUB  
(rd,) rs, rt  
Subtract  
The low-order 32 bits of the result can be optionally copied to rd.  
The multiplicand is the unsigned value of rs. The multiplier is the  
unsigned value of rt. The 64-bit product rs * rt is subtracted from the  
contents of registers HI and LO and the result is placed back into HI  
and LO. The low-order 32 bits of the result can be optionally copied  
* Multiply and  
MSUBU (rd,) rs, rt  
Subtract Unsigned  
to rd.  
* Enhancements from the TX19 to the TX19A  
Table 3-14 Jump Instructions (32-Bit ISA)  
Instruction  
Format  
Operation  
The program jumps to the address computed using paged absolute  
addressing, i.e., by shifting the 26-bit target left by two bits and  
Jump  
J
target  
combining it with the four most-significant bits of PC + 4.  
The program jumps to the address computed using paged absolute  
addressing, i.e., by shifting the 26-bit target left by two bits and  
combining it with the four most-significant bits of PC + 4. The  
Jump And Link  
JAL  
target  
target  
address of the instruction following the delay slot is saved in r31.  
The program jumps to the address using paged absolute addressing,  
i.e., by shifting the 26-bit target left by two bits and combining it with  
the four most-significant bits of PC + 4. The address of the instruction  
following the delay slot is saved in r31. The ISA mode bit in the PC  
Jump And Link  
exchange  
JALX  
toggles.  
Jump Register  
JR  
rs  
The program jumps to the address specified by rs, with the  
least-significant bit cleared. The least-significant bit of rs is interpreted  
as the ISA mode specifier.  
The program jumps to the address specified by rs, with the  
least-significant bit cleared. The least-significant bit of rs is interpreted  
as the ISA mode specifier. The address of the instruction following the  
Jump And Link  
Register  
JALR  
(rd,) rs  
delay slot is saved in rd. If rd is omitted, the default is r31.  
3-25  
Chapter 3 32-Bit ISA Summary and Programming Tips  
Table 3-15 Branch and Branch-Likely Instructions (32-Bit ISA)  
Instruction  
Format  
Operation  
If rs = rt, the program branches to the target address specified as a  
16-bit offset relative to PC + 4 (i.e., the address of the branch delay  
slot).  
Branch On Equal  
(Likely)  
BEQ(L) rs, rt, offset  
If rs ≠ rt, the program branches to the target address specified as a  
16-bit offset relative to PC + 4 (i.e., the address of the branch delay  
slot).  
Branch On Not Equal BNE(L) rs, rt, offset  
(Likely)  
If rs > 0, the program branches to the target address specified as a  
16-bit offset relative to PC + 4 (i.e., the address of the branch delay  
slot).  
If rs ≥ 0, the program branches to the target address specified as a  
16-bit offset relative to PC + 4 (i.e., the address of the branch delay  
slot).  
Branch On Greater  
Than Zero (Likely)  
BGTZ(L) rs, offset  
BGEZ(L) rs, offset  
Branch On Greater  
Than or Equal to  
Zero (Likely)  
If rs < 0, the program branches to the target address specified as a  
16-bit offset relative to PC + 4 (i.e., the address of the branch delay  
slot).  
If rs ≤ 0, the program branches to the target address specified as a  
16-bit offset relative to PC + 4 (i.e., the address of the branch delay  
slot).  
Branch On Less  
Than Zero (Likely)  
BLTZ(L) rs, offset  
BLEZ(L) rs, offset  
Branch On Less  
Than or Equal to  
Zero (Likely)  
If rs < 0, the program branches to the target address specified as a  
16-bit offset relative to PC + 4 (i.e., the address of the branch delay  
slot). The address of the instruction following the delay slot is saved  
in r31.  
If rs ≥ 0, the program branches to the target address specified as a  
16-bit offset relative to PC + 4 (i.e., the address of the branch delay  
slot). The address of the instruction following the delay slot is saved  
Branch On Less  
Than Zero And Link  
(Likely)  
BLTZAL(L) rs, offset  
BGEZAL(L) rs, offset  
Branch On Greater  
Than or Equal to  
Zero And Link  
(Likely)  
in r31.  
The program unconditionally branches to the target address  
specified as a 16-bit offset relative to PC + 4 (i.e., the address of the  
* Unconditional  
B
offset  
offset  
Branch  
branch delay slot).  
The program unconditionally branches to the target address  
specified as a 16-bit offset relative to PC + 4 (i.e., the address of the  
branch delay slot). The address of the instruction following the delay  
* Branch And Link  
BAL  
slot is saved in r31.  
* Enhancements from the TX19 to the TX19A  
✝ The "L" suffix in the opcodes indicates a branch-likely instruction.  
Table 3-16 System Control Coprocessor (CP0) Instructions (32-Bit ISA)  
Instruction  
Format  
Operation  
Move To CP0  
MTC0  
MFC0  
ERET  
rt, rd  
rt, rd  
The contents of general register rt is copied into CP0 register rd.  
Move From CP0  
The contents of CP0 register rt is copied into general register rd.  
If the ERL bit in the Status register is 1, the processor returns from  
an exception and then program execution continues at the address  
held in the Error EPC register. If the ERL bit is 0, the processor  
returns from an exception and then program execution continues at  
* Exception Return  
the address held in the EPC register.  
Program control is transferred back to a User program from a debug  
exception handler. The return address in the DEPC register is  
Debug Exception  
Return  
DERET  
WAIT  
restored into the PC.  
The processor enters either HALT or DOZE mode, depending on the  
* Enter Standby  
setting of the PR bit in the Status register.  
Mode  
* Enhancements from the TX19 to the TX19A  
3-26  
Chapter 3 32-Bit ISA Summary and Programming  
Tips  
Table 3-17 Special Instructions (32-Bit ISA)  
Instruction  
Format  
Operation  
A system call exception occurs, immediately and unconditionally  
System Call  
Breakpoint  
SYSCALL code  
transferring control to the exception handler.  
A breakpoint exception occurs, immediately and unconditionally  
BREAK code  
SDBBP code  
transferring control to the exception handler.  
A debug breakpoint exception occurs, immediately and  
Software Debug  
Breakpoint Exception  
Trap If Equal  
unconditionally transferring control to the exception handler.  
TEQ  
rs, rt  
If rs = rt, a Trap exception occurs.  
If rs = immediate, a Trap exception occurs. The 16-bit immediate is  
* Trap If Equal  
Immediate  
TEQI  
rs, immediate  
sign-extended. Two values are compared as signed integers.  
If rs ≥ rt, a Trap exception occurs. Two values are compared as  
signed integers.  
* Trap If Greater  
Than or Equal  
* Trap If Greater  
Than or Equal  
Immediate  
TGE  
rs, rt  
If rs ≥ immediate, a Trap exception occurs. The 16-bit immediate is  
sign-extended. Two values are compared as signed integers.  
TGEI  
rs, immediate  
If rs ε immediate, a Trap exception occurs. The 16-bit immediate is  
sign-extended. Two values are compared as unsigned integers.  
* Trap If Greater  
Than or Equal  
Immediate  
TGEIU rs, immediate  
Unsigned  
If rs ≥ rt, a Trap exception occurs. Two values are compared as  
* Trap If Greater  
Than or Equal  
Unsigned  
TGEU  
rs, rt  
unsigned integers.  
If rs < rt, a Trap exception occurs. Two values are compared as  
* Trap If Less Than  
TLT  
rs, rt  
signed integers.  
If rs < immediate, a Trap exception occurs. The 16-bit immediate is  
* Trap If Less Than  
Immediate  
TLTI  
rs, immediate  
sign-extended. Two values are compared as signed integers.  
If rs < immediate, a Trap exception occurs. The 16-bit immediate is  
sign-extended. Two values are compared as unsigned integers.  
* Trap If Less Than  
Immediate  
TLTIU  
TLTU  
rs, immediate  
rs, rt  
Unsigned  
If rs < rt, a Trap exception occurs. Two values are compared as  
* Trap If Less Than  
Unsigned  
unsigned integers.  
* Trap If Not Equal  
* Trap If Not Equal  
Immediate  
TNE  
rs, rt  
If rs ≠ rt, a Trap exception occurs.  
If rs ≠ immediate, a Trap exception occurs. The 16-bit immediate is  
TNEI  
rs, immediate  
sign-extended. Two values are compared as signed integers.  
* Enhancements from the TX19 to the TX19A  
3-27  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Chapter 4 16-Bit ISA Summary and Programming Tips  
This chapter gives an overview of the instructions and addressing modes supported by the TX19A  
in 16-bit ISA mode. This chapter also presents many programming tips using 16-bit ISA instructions.  
Instructions are grouped into the following categories. Branch-likely instructions are not supported  
by the 16-bit ISA.  
z Load and store instructions  
z Computational instructions  
z Jump and branch instructions  
z Bit manipulation instructions  
z SAVE and RESTORE instructions  
z System control coprocessor (CP0) instructions  
z
Special instructions  
Doubleword instructions available in the MIPS16 ASE are not implemented in the TX19A.  
To the 16-bit ISA, only eight of the 32 general-purpose registers are normally visible, r2 to  
r7, r16 and r17. Since the processor includes the full 32 registers of the 32-bit ISA mode, the 16-bit  
ISA includes MOVE instructions to copy values between the eight 16-bit-ISA registers and the  
remaining 24 registers of the full 32-bit architecture. Additionally, specific instructions implicitly  
reference r24 (t8), r28 (gp), r29 (sp), r30 (fp) and r31 (ra). r24 serves as a special condition code  
register for handling compare results. r28 is the global pointer register. r29 maintains the program  
stack pointer. r30 is the frame pointer register. r31 is the link register. Multiply and divide  
instructions use the special registers HI and LO.  
4.1 Instruction Formats  
There are 21 instruction formats shown in Figure 4-1 for the 16-bit instructions. There are 20  
instruction formats shown in Figure 4-2 for the 32-bit instructions.  
To fit within the 16-bit limit, immediate fields in the 16-bit instructions are only 3 to 11 bits. Thus,  
the 16-bit ISA provides a way to extend its shorter immediates into the full width of immediates in  
the 32-bit ISA mode. The EXTEND instruction in the 16-bit ISA is not really an instruction and  
does not generate a machine instruction on its own. It provides a prefix to be prepended to any 16-  
bit instruction with an address or immediate field. Therefore, EXTENDing typical 16-bit  
instructions to 32 bits gives several more instruction formats shown in Figure 4-2. For example, the  
EXTENDed version of the I-type format is called EXT-I.  
Additionally, the 16-bit ISA has several 32-bit instructions prepended with the EXTEND code. In  
such instructions, the 11-bit immediate field in the EXTEND code is replaced with an opcode.  
4-1  
Chapter 4 16-Bit ISA Summary and Programming Tips  
op  
rx  
5-bit operation code  
3-bit source/destination register specifier  
ry  
3-bit source/destination register specifier  
3-, 4-, 5-, 8- or 11-bit immediate, or branch or address displacement  
(offset)  
immediate, imm or  
ximm3  
rz  
3-bit source/destination register specifier  
1-, 2-, 3- or 5-bit function code  
32-bit ISA general-purpose register specifier  
r31 register  
F
r32  
ra  
s0  
r16 register  
s1  
r17 register  
pos3  
cpr32  
hase  
xsregs  
aregs  
framesize  
Bit number of a specific bit of a memory byte  
Coprocessor register  
fp, sp, gp or r0 register  
Registers saved or restored  
Registers saved or restored  
Size of frame required  
<< 16-Bit Instructions >>  
I Type  
15  
11 10  
11 10  
0
op  
op  
imm  
op:  
15  
B
RI Type  
8 7  
0
rx  
imm  
op: ADDIU8・ADDIUPC・ADDIUSP・BEQZ・BNEZ・CMPI・LI・LWPC・LWSP・SLTI・SLTIU SWSP  
RR Type  
RRI Type  
15  
15  
11 10  
11 10  
8 7  
8 7  
5 4  
5 4  
0
0
RR  
op  
rx  
rx  
ry  
ry  
F
imm  
op: LB・LBU・LH・LHU・LW・SB・SH・SW  
RRR Type 1  
RRR Type 2  
15  
15  
11 10  
11 10  
8 7  
5 4  
2 1  
2 1  
0
0
RRR  
op  
rx  
ry  
ry  
6
rz  
F
F
8 7  
F
imm  
op: SLL・SRL・SRA  
RRR Type 3  
RRR Type 4  
15  
11 10  
imm  
8 7  
6
6
2 1  
2 1  
0
0
op  
F
cpr32  
F
F
op: AC0IU  
15  
11 10  
8 7  
op  
rx  
F
00000  
op: MTHI・MTLO  
4-2  
Chapter 4 16-Bit ISA Summary and Programming Tips  
RRI-A Type  
15  
15  
11 10  
11 10  
8 7  
8 7  
5
3
0
0
RRI-A  
SHIFT  
rx  
rx  
ry  
ry  
F
imm  
2 1  
SHIFT Type 1  
5 4  
SA  
F
SA: The 3-bit sa field can specify a shift amount in the range of 1 to 8. The 16-bit ISA defines the value  
0 in the sa field to mean a shift of 8 bits.  
SHIFT Type 2  
15  
11 10  
8 7  
3 2  
0
op  
rx/ry  
cpr32  
F
op: MTC0・MFC0  
I8 Type  
15  
11 10  
8 7  
0
I8  
F
imm  
F: BTEQZ・BTNEZ・SWRASP・ADJSP・MOV32R・MOVR32・ADJFP  
I8_MOVR32 Type  
I8_MOV32R Type  
15  
15  
11 10  
11 10  
8 7  
5 4  
0
0
I8  
I8  
F
F
ry  
r32[4:0]  
3 2  
8 7  
r32[2:0, A4:3]  
rz  
r32: The r32 field uses special bit encoding. For example, encoding of register r7 (00111) is 11100 in the  
r32 field.  
I8_SVRS Type  
FP-B、SP-B Type  
FP-SP-H Type  
15  
15  
15  
15  
11 10  
11 10  
11 10  
11 10  
7
6
5
4
3
0
0
0
I8  
F
ra s0 s1  
imm  
8
8
8
7
F
6
op  
op  
op  
rx  
rx  
F
imm  
7
F
6
1
imm  
F
SPECIAL_SWFP、  
7
5
5
4
0
SPECIAL_LWFP  
Type  
ry  
imm  
op: SWFP・LWFP  
SPECIAL_BIT Type  
SPECIAL_BAL Type  
RRR_INT Type  
15  
11 10  
8
7
4
0
0
0
op  
F
pos3  
imm  
op: BTST・BEXT・BCLR・BSET・BINS  
15  
11 10  
8
7
op  
F
imm  
op: BAL  
15  
11 10 9  
00  
8
7
6
2 1  
op  
F
0000  
F
op: EI・DI  
Figure 4-1 16-Bit Instruction Formats  
4-3  
Chapter 4 16-Bit ISA Summary and Programming Tips  
<< 32-Bit Instructions >>  
JAL・JALX Type  
31  
27 26 25  
21 20  
16 15  
0
JAL  
X
TAR[20:16]  
TAR[25:21]  
TAR[15:0]  
X=0: JAL instruction, X=1: JALX instruction  
EXT-I Type  
31  
27 26  
27 26  
27 26  
27 26  
27 26  
27 26  
21 20  
16 15  
11 10 9  
8
7
6
5
4
4
0
0
0
0
EXTEND  
imm[10:5]  
imm[10:5]  
imm[10:5]  
imm[10:4]  
imm[15:11]  
op  
op  
0
0
0
0
0
0
imm[4:0]  
imm[4:0]  
imm[4:0]  
EXT-RI Type  
31  
21 20  
16 15  
16 15  
11 10  
8 7 6 5  
EXTEND  
imm[15:11]  
rx  
rx  
rx  
rx  
F
0 0 0  
EXT-RRI Type  
31  
21 20  
imm[15:11]  
11 10  
11 10  
11 10  
11 10  
11 10  
11 10  
11 10  
11 10  
11 10  
11 10  
8 7  
8 7  
5 4  
EXTEND  
op  
ry  
ry  
ry  
EXT-RRI-A Type  
31  
20 19  
16 15  
5 4  
3
EXTEND  
imm[14:11]  
RRI-A  
SHIFT  
I8  
F
imm[3:0]  
EXT-SHIFT Type  
31  
22 21 20 19 18 17 16 15  
8
7
5
4
0
3
0
2
0
1 0  
EXTEND  
SA[4:0]  
0
0
0
0
0
0
F
EXT-I8 Type  
31  
21 20  
16 15  
8 7  
6
0
5
4
0
EXTEND  
imm[10:5]  
imm[15:11]  
imm[15:11]  
imm[15:11]  
0
0
imm[4:0]  
EXT-FP-B、EXT-SP-B Type  
31 27 26  
21 20  
21 20  
16 15  
16 15  
16 15  
16 15  
8
8
8
8
8
8
7
F
6
5
4
4
0
EXTEND  
imm[10:5]  
imm[10:5]  
op  
rx  
rx  
F
00  
imm[4:0]  
1
EXT-FP-SP-H Type  
31 27 26  
7
F
6
5
0
F
EXTEND  
op  
00  
imm[4:1]  
EXT-SPECIAL-SWFP, EXT-SPECIAL-LWFP Type  
31 27 26 21 20  
imm[15:11]  
7
7
7
7
5
5
5
5
4
0
0
0
0
EXTEND  
imm[10:5]  
op  
ry  
pos3  
000  
F
imm[4:0]  
imm[4:0]  
imm[4:0]  
imm[4:0]  
EXT-SPECIAL-BIT Type  
31 27 26  
21 20 19 18  
base  
4
4
4
EXTEND  
imm[10:5]  
op  
F
imm[13:11]  
EXT-SPECIAL- BAL Type  
31 27 26  
21 20  
16 15  
EXTEND  
imm[10:5]  
imm[15:11]  
op  
F
EXT-ADDIU8 Type  
31 27 26  
21 20  
16 15  
EXTEND  
imm[10:5]  
imm[15:11]  
op  
ry  
op: ANDI・ORI・XORI・LUI  
EXT-ADDMIU Type  
31  
27 26  
21 20 19 18  
base  
16 15  
11 10  
8
7
5
4
0
EXTEND  
imm[10:5]  
op  
ximm3  
F
imm[4:0]  
imm[13:11]  
4-4  
Chapter 4 16-Bit ISA Summary and Programming Tips  
EXT-I8-SVRS Type  
31 27 26  
xsregs framesize  
24 23  
20 19  
16 15  
16 15  
11 10  
8
7
6
5
4
0
EXTEND  
aregs  
I8  
SVRS F ra s0 s1 framesize  
EXT-RR Type  
31  
27 26 25 24  
11 10  
5
4
0
EXTEND  
op2: ERET・DERET・WAIT  
0
1
000000000  
11101  
000000  
000000  
op2  
EXT-RR-SYSCALL Type  
31  
27 26  
22 21  
16 15  
16 15  
16 15  
16 15  
11 10  
11 10  
11 10  
11 10  
5
5
5
5
4
4
4
4
0
0
0
0
EXTEND  
imm[10:6]  
imm[16:11]  
11101  
op  
01100  
00111  
00111  
00101  
EXT-RR-BSIF Type  
31 27 26 25  
8
8
8
7
7
7
EXTEND  
1
0000000000  
21 20  
ry  
ry  
rz  
rx  
rx  
rx  
EXT-RR-BFINS Type  
31 27 26 25  
EXTEND  
0
bit2  
bit1  
op  
EXT-RR-MAX/MIN Type  
31 27 26 25 24 23  
00  
19 18  
EXTEND  
M
00000  
ry  
op  
M=0: MAX Instruction, M=1: MIN Instruction  
Figure 4-2 32-Bit Instruction Formats  
4.2 Load and Store Instructions  
In the 16-bit ISA, there are no load/store instructions for misaligned data. In the 16-bit ISA, the  
biggest saving in the instruction length comes from restrictions on the size of immediate values  
expressible. All 16-bit load and store instructions are restricted to 5 to 8 bits of unsigned values. To  
overcome this restriction, the 16-bit ISA contains a mechanism to EXTEND an address or offset  
field to 16 bits. For details on the EXTEND instruction, see Section 4.5, Special Instructions. To  
further address the supply of constants, the 16-bit ISA has new addressing modes.  
Section 4.2.1 describes the addressing modes supported by the 16-bit load and store instructions.  
Section 4.2.2 gives an overview of the load and store instructions. Section 4.2.3 explains how to get  
32-bit addresses using an addressing mode newly added to TX19A. Section 4.2.4 describes the  
SYNC instruction.  
4-5  
Chapter 4 16-Bit ISA Summary and Programming Tips  
4.2.1 Load and Store Address Calculation  
In the 16-bit ISA, there are four addressing modes supported by load and store instructions:  
z Register indirect with offset  
z SP-relative with offset  
z FP-relative with offset  
z PC-relative with offset  
Register Indirect with Offset Addressing  
In 16-bit ISA mode, most load and store instructions use register indirect with offset addressing.  
Instructions using this addressing mode is the RRI (register-register-immediate) type and include a  
base register and an unsigned 5-bit offset field. These instructions generate the target address by  
zero-extending the 5-bit offset and adding it to the contents of the base register. The base register  
can be any of the general-purpose registers visible to the 16-bit ISA (r2 to r7, r16, r17). In the 16-bit  
ISA, load and store offsets are shifted left until they are aligned to the data type being loaded or  
stored. This is done to provide a greater offset range. In the case of word accesses, the offset is left  
shifted by two bits. In the case of halfword accesses, the offset is left shifted by one bit.  
Memory  
Base Register  
32-Bit Address  
5-Bit Offset  
Ø
0
00  
+
Zero Extension  
Shifted left by 1 or 2 bits  
Effective Address  
Figure 4-3 Register Indirect with Offset Addressing (16-Bit ISA)  
SP-Relative with Offset Addressing  
In the 32-bit ISA, there is no hardware-designated stack pointer. Although r29 is conventionally  
used to maintain the program stack pointer, any general-purpose register (except r0) can be used  
from the point of view of hardware. In the 16-bit ISA, however, one of the general-purpose  
registers, r29, serves as a stack pointer and is called sp. The 16-bit ISA references r29 implicitly  
through a special function code, thereby eliminating the base register field. This made it possible to  
expand the offset field to eight bits. The instruction format is the RI (register-immediate) type. In  
SP-relative addressing, the effective address is formed from a eight-bit offset (shifted left by two  
4-6  
Chapter 4 16-Bit ISA Summary and Programming Tips  
bits) relative to the sp register. The LBU, LHU, LW, SB, SH and SW instructions can use this  
addressing mode. These instructions can address a range of 1 Kbytes (210) of memory without the  
need to EXTEND the instruction.  
Memory  
Stack Pointer Register (sp)  
32-Bit Address  
8-Bit Offset  
Ø
+
00  
Zero Extension  
Shifted Left by 1 or 2 bits  
Effective Address  
Figure 4-4 SP-Relative Addressing (16-Bit ISA))  
4-7  
Chapter 4 16-Bit ISA Summary and Programming Tips  
„
FP-Relative with Offset Addressing  
In the 16-bit ISA, r30 serves as a frame pointer (fp) register. The 16-bit ISA references r30  
implicitly through a special function code, thereby eliminating the base register field. This made it  
possible to expand the offset field to five bits. The instruction format is the RI (register-immediate)  
type. For example, for 32-bit word access, the effective address is formed from a five-bit offset  
(shifted left by two bits) relative to the fp register with the zero extended value. The LBU, LHU, LW,  
SB, SH and SW instructions can use this addressing mode. These instructions can address a range of  
128 bytes (27) of memory without the need to EXTEND the instruction.  
Memory  
Frame Pointer (fp)  
32-Bit Address  
5-Bit Offset  
Ø
+
00  
Zero Extension  
Shifted Left by 1 or 2 bits  
Effective Address  
Figure 4-5 FP-Relative with Offset Addressing (16-Bit ISA, Word Access)  
„
PC-Relative with Offset Addressing  
PC-relative with offset addressing is supported by the Load Word (LW) instruction. In PC-relative  
with offset addressing, the effective address is formed by shifting the eight-bit offset left by two bits  
with the zero extended value and adding the resultant value to the PC with the lower two bits cleared.  
A 32-bit constant is then loaded into a register from the addressed memory location. 32-bit constants  
can be embedded in the code segment to get the maximum benefit from this addressing mode.  
Memory  
Program Counter (PC)  
8-Bit Offset  
Ø
+
00  
Zero Extension  
Shifted Left by 2 bits  
Effective Address  
Figure 4-6 PC-Relative with Offset Addressing (16-Bit ISA)  
4-8  
Chapter 4 16-Bit ISA Summary and Programming Tips  
4.2.2 Overview of Load and Store Instructions  
Table 4-7 and Table 4-8 give the load and store instructions to perform byte, halfword and word  
accesses. The LB and LH instructions sign-extend the loaded byte and halfword respectively. The  
LBU and LHU instructions, which have the “U” (unsigned) suffix, zero-extend the loaded byte and  
halfword respectively and placed the result in the register.  
Table 4-7 Load Instructions  
Data Type Unsigned Load  
Signed Load  
Addressing  
Register-Indirect, SP-Relative,  
Byte  
LBU  
LHU  
LW  
LB  
LH  
—
FP-Relative  
Register-Indirect, SP-Relative,  
Halfword  
Word  
FP-Relative  
Register-Indirect, SP-Relative,  
FP-Relative, PC-Relative  
Table 4-8 Store Instructions  
Opcode  
Data Type  
Addressing  
Register-Indirect, SP-Relative,  
FP-Relative  
Register-Indirect, SP-Relative,  
Byte  
SB  
SH  
SW  
Halfword  
Word  
FP-Relative  
Register-Indirect, SP-Relative,  
FP-Relative, PC-Relative  
4.2.3 32-Bit Address Generation  
In 16-bit ISA mode, the offset field is restricted to only 5 to 8 bits. However, EXTENDing an  
instruction to 32 bits allows the same order of offset value magnitude as is available in the 32-bit  
ISA (-32768 to 32767). If the offset is outside this range, you must put it in a general register prior  
to the load or store instruction. Alternatively, for word loads, you can use PC-relative with offset  
addressing. Three examples are given below.  
z Example 1: Base address + 32-bit offset  
In the example below, the ADDU (Add Unsigned) instruction is used to add the offset held in  
register r5 to the base address in register r4. The result is placed back into r4. Then the LW  
instruction uses r4 as the base register to address a memory location.  
ADDU r4,r4,r5  
LW r6,0(r4)  
4-9  
Chapter 4 16-Bit ISA Summary and Programming Tips  
z Example 2: Base address + 32-bit offset  
For offsets greater than 16 bits, the 32-bit ISA uses the LUI (Load Upper Immediate) instruction  
to load the upper 16 bits of a register, followed by a concatenation with the lower 16 bits using  
a logical OR instruction. Since the previous TX19 does not have the LUI instruction, a 32-bit  
offset is embedded in code and loaded from memory using PC-relative addressing. On the other  
hand, the TX19A now provides the LUI and ORI instructions, enabling the same coding as for the  
32-bit ISA.  
– TX19: Code efficient – TX19A  
LW r5,16(pc)  
ADDU r4,r4,r5  
LW r6,0(r4)  
LUI r5,0x0008  
ORI r5,0x0234  
ADDU r4,r4,r5  
LW r6,0(r4)  
z Example 3: Arbitrary 32-bit absolute address  
In the example below, the first LW instruction loads a 32-bit absolute address from memory  
using PC-relative addressing. Then the second LW instruction can address a desired memory  
location, with an offset of zero.  
LW r4,16(pc)  
LW r6,0(r4)  
The LUI and ORI instructions can also be used in combination to form a 32-bit absolute  
address:  
LUI r4,0x0008  
ORI r4,0x0234  
4.2.4 SYNC Instruction  
The memory synchronization instruction, SYNC, guarantees the sequence of memory references by  
interlocking the instruction pipeline until loads, stores and instruction fetches which performed prior  
to the present instruction are completed before loads or stores after this instruction are allowed to  
start.  
4.3 Computational Instructions  
This section describes the computational instructions available in the 16-bit ISA. Section 4.3.1  
provides a category of computational instructions and an overview of the newly added instructions.  
Section 4.3.2 discusses computations that involve the use of 32-bit constants. For 64-bit arithmetic  
and rotate operations, see Chapter 3, 32-Bit ISA Summary and Programming Tips, since the same  
instructions can be used to implement them in both the 32-bit and 16-bit ISA modes.  
4-10  
Chapter 4 16-Bit ISA Summary and Programming Tips  
4.3.1 Overview of Computational Instructions  
Computational instructions in the 16-bit ISA are categorized into four groups shown in Table 4-9.  
They consist of arithmetic, compare, logical, shift, multiply, divide and multiply-and-add  
instructions. Multiply-and-subtract instructions are not available in the 16-bit ISA. The 16-bit ISA  
does not support MIPS16 instructions for 64-bit, doubleword arithmetic and shift operations.  
Table 4-9 Computational Instructions  
Category  
Instruction  
Opcode  
ALU Immediate  
Add  
ADDIU  
SLTI・SLTIU  
CMPI  
Set On Less Than  
Compare  
LI・LUI  
ANDI  
Load Immediate  
Logical AND  
Logical OR  
Logical XOR  
Add  
ORI  
XORI  
2-and 3-Operand  
Register Type  
ADDU  
SUBU  
Subtract  
SADD・SSUB  
Saturate  
SLT・SLTU  
Set On Less Than  
Compare  
CMP  
Negate  
NEG  
Logical AND  
Logical OR  
Logical XOR  
NOT  
AND  
OR  
XOR  
NOT  
MOVE  
MOVE  
Bit Search  
Bit Field  
BS1F  
BFINS  
MAX・MIN  
MAX/MIN  
SEB・SEH・ZEB・ZEH  
SLL・SLLV・SRL・SRLV  
SRA・SRAV  
Sign- and Zero-Extend  
Logical Shift  
Arithmetic Shift  
Shift  
MULT・MULTU・MADD・MADDU  
DIV・DIVU・DIVE・DIVEU  
MFHI・MFLO・MTHI・MTLO  
Multiply and Divide Multiply and Multiply-and-Add  
Divide  
Move From/To HI/LO  
4-11  
Chapter 4 16-Bit ISA Summary and Programming Tips  
In ALU immediate instructions, the source operands are a general-purpose register and a 4- or 8-bit  
immediate. The new instructions, ANDI, ORI, XORI and LUI, are 32 bits in length, prepended with  
the EXTEND code. There are no 16-bit codes for these instructions; as such, they have a 16-bit  
immediate that is zero-extended and treated as a 32-bit unsigned operand (except the LUI  
instruction). Except for the ADDIU and LUI instructions, the 8-bit immediate in ALU immediate  
instructions are zero-extended. However, when EXTENDed, the immediate in the ADDIU, SLTI  
and SLTIU instructions are treated as a 16-bit signed integer (in the same manner as for the 32-bit  
ISA), and the immediate in other instructions are treated as a 16-bit unsigned integer.  
Register-type instructions manipulate the values held in two general-purpose registers and place the  
result into a general-purpose register. The 16-bit ISA provides the CMP, NEG and NOT  
instructions. CMP compares the values in two registers. NEG performs two’s complement of a  
value in a register. The NOT instruction performs one’s complement of a value in a register.  
Additionally, the 16-bit ISA has the MOVE instruction to copy values between the eight registers  
plus the fp register and the remaining 24 registers of the full 32-bit architecture.  
The 16-bit ISA has the Compare (CMP), Negate (NEG) and Not (NOT) instructions since these  
operations can not be synthesized from other instructions using r0 as a source. Compare instructions  
(CMP, CMPI) and set-on-less-than instructions (SLTI, SLTIU, SLT, SLTU) implicitly use register t8  
(r24) as the destination.  
The 16-bit ISA provides the same set of shift instructions as the 32-bit ISA. In the previous TX19,  
the sa field is only 3-bits wide; thus the shift amount is restricted to 1 to 8 (000 is defined as a shift  
of 8 bits). EXTEND enlarges the 3-bit sa field into 5 bits for a shift of 0 to 31 as in the 32-bit ISA.  
Additionally, the TX19A has also new instructions with a 5-bit sa field for a shift of 1 to 31 bits (the  
sa value of 00000 is undefined).  
Multiply, divide and multiply-and-add instructions in the 16-bit ISA perform the same functionality  
as those in the 32-bit ISA. The multiply and multiply-and-add instructions in the 16-bit ISA can  
place the lower 32 bits of the result into a general-purpose register. The 16-bit ISA also provides the  
MTHI, MTLO, MFHI and MFLO instructions to access the HI and LO registers.  
The TX19A offers new divide instructions (DIVE and DIVEU). The signed divide instruction  
(DIVE) generates an Integer Overflow exception when divide-by-zero or overflow conditions are  
detected, whereas the unsigned divide instruction (DIVEU) generates an Integer Overflow exception  
when a divide-by-zero condition is detected.  
The TX19A provides the ZEB, ZEH, SEB and SHE instructions, new instructions that zero-extend  
or sign-extend a byte or halfword into 32 bits.  
4-12  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Additionally, the TX19A has saturate instructions (SADD and SSUB). For example, the SADD  
instruction adds the contents of general-purpose registers rx and ry; saturation clamps results to the  
largest representable positive number (0x7FFF_FFFF) on overflow and to the smallest representable  
negative number (0x8000_0000) on underflow. If overflow or underflow does not occur, the sum of  
rx and ry is placed into ry.  
The new instructions MIN and MAX perform an arithmetic comparison on a pair of registers (rx  
and ry). The MIN instruction, for example, places the value of register rx into register rz if rx is less  
than ry, and otherwise, the value of ry into rz.  
The bit field instruction (BFINS) helps the C compiler improve code density. C programs often deal  
with bit fields; the BFINS instruction copies a bit field from one register into another register with a  
single instruction. Also, the bit search instruction (BS1F) is convenient for scanning through an  
operand for a set bit, for example, for the purpose of key scanning in embedded control systems.  
4.3.2 32-Bit Constants  
With the previous TX19, even EXTEND can enlarge immediate fields in computational instructions  
to only 16 bits.  
Since the 16-bit ISA of the TX19A has the LUI and ORI instructions, you can deal with 32-bit  
constants in the same manner as for the 32-bit ISA. Following is an example of adding a 32-bit  
constant to the contents of a general-purpose register:  
LUI r5,0x8000  
ORI r5,0x1234  
ADDU r6,r6,r5  
For code density, 32-bit constants can be embedded in the code segment, typically between  
subroutine bodies, in the previous TX19 way. Then the LW instruction can reference those 32-bit  
constants using PC-relative addressing. Even with the overhead of the constant storage, this is more  
compact than using a pair of the LUI and ORI instructions.  
In the following example, the LW instruction loads a 32-bit constant into register r5 from memory.  
Then, the ADDU instruction adds the contents of r4 and r5 together and puts the results in r6.  
LW r5,offset(pc)  
ADDU r6,r4,r5  
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Chapter 4 16-Bit ISA Summary and Programming Tips  
Zero Value  
Generally, the 16-bit ISA does not have direct access to r0. When a value of zero is necessary, use  
the following LI (Load Immediate) instruction which zero-extends and loads the immediate value (0)  
into rx.  
LI rx,0  
Alternatively, you can use the MOVE instruction to get a value of zero. Since the MOVE instruction  
can move values between the eight registers visible to the 16-bit ISA and the remaining 24 registers  
of the full 32-bit architecture, the following gives you a value of zero:  
MOVE ry,r0  
4.4 Jump and Branch Instructions  
This section describes the jump and branch instructions available in the 16-bit ISA, focusing on the  
differences from the 32-bit instructions. Section 4.4.1 gives an overview of jump and branch  
instructions. Section 4.4.2 provides programming tips for branching on arithmetic comparisons.  
Section 4.4.3 describes a technique to jump to 32-bit addresses.  
4.4.1 Overview of Jump and Branch Instructions  
The 16-bit ISA has no branch instruction that compares two registers and then branches, such as  
BEQ, BNE, BGEZ, BGTZ, BLEZ and BLTZ. To compensate for the loss of these instructions, the  
16-bit ISA includes compare instructions (CMP, CMPI) to test if two registers or a register and an  
immediate are equal. Since these compare instructions and all set-on-less-than instructions set  
register t8, the 16-bit ISA provides branch instructions to test t8 and branch based on the zero or  
non-zero state of t8. The TX19A has a new branch-and-link instruction (BAL).  
Even in 16-bit ISA mode, the JAL and JALX instructions are 32-bit wide to provide a large enough  
address field to jump to far procedures. Table 4-10 and Table 4-11 show the opcodes of the jump and  
branch instructions in the 16-bit ISA.  
4-14  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Table 4-10 Jump Instructions (16-Bit ISA)  
Opcode Name  
Addressing  
JAL  
Jump And Link  
Paged Absolute  
Paged Absolute  
Register Indirect  
Register Indirect  
Register Indirect  
Register Indirect  
JALX  
JR  
Jump And Link Exchange  
Jump Register  
JRC  
Jump Register, Compact  
Jump And Link Register  
Jump And Link Register, Compact  
JALR  
JALRC  
Table 4-11 Branch Instructions (16-Bit ISA)  
Opcode  
Name  
Condition  
Addressing  
BEQZ  
BNEZ  
BTEQZ  
BTNEZ  
B
Branch On Equal to Zero  
Branch On Not Equal Zero  
Branch On T8 Equal To Zero  
Branch On T8 Not Equal To Zero  
Unconditional Branch  
rx = 0  
rx ≠ 0  
t8 > 0  
t8 ≠ 0  
⎯
PC-relative  
PC-relative  
PC-relative  
PC-relative  
PC-relative  
PC-relative  
BAL  
Branch And Link  
⎯
Jump-and-link and BAL instructions save a return address in register r31. They are typically used  
for subroutine calls.  
Branch instructions in the 16-bit ISA use the same addressing mode as those in the 32-bit ISA.  
However, since instructions are 16-bits wide, the branch address is shifted by one bit, not by  
two bits. The offset immediate is either 8-bits or 11-bits wide.  
„
Delayed Branch  
In the 16-bit ISA, there is no delayed branch. Branches always take effect before the next  
instruction. Therefore, there is no restriction on the instructions that follow a branch instruction.  
Instructions following a branch are executed only when the branch is not taken.  
As in the 32-bit ISA mode, jump instructions in the 16-bit ISA have a delay slot, except the JRC  
and JALRC instructions, new compact versions of JR and JALR.  
„
Run-Time Switching of the ISA Modes  
As shown in Table 4-1, the 16-bit ISA includes the JALX, JR, JALR, JRC and JALRC instructions.  
These instructions can be used in 16-bit ISA mode to toggle the ISA mode bit in the PC and switch  
to the other ISA mode. See Section 3.4.3, Run-Time Switching of the ISA Modes, for details on this.  
„
Subroutine Calls  
The 16-bit ISA has jump-and-link instructions (JALX, JALR) and a branch-and-link instruction  
(BAL). See Section 3.4.7, Subroutine Calls, for details on subroutine calls.  
4-15  
Chapter 4 16-Bit ISA Summary and Programming Tips  
4.4.2 Branching on Arithmetic Comparisons  
As mentioned in the previous section, the 16-bit ISA did away with instructions that compare two  
registers and branch like "BEQ r10, r7, Equal". Also, set-on-less-than instructions (SLT, SLTU) in  
the 16-bit ISA are two-register instructions instead of three. In the 16-bit ISA, the SLT and SLTU  
instructions implicitly set register t8 based on the equality of the values in two registers. Because of  
this, the 16-bit ISA has new instructions, BTEQZ and BTNEZ, to test the t8 register to see if it is  
zero or not.  
As explained in Section 3.4.5, Branching on Arithmetic Comparisons, in 32-bit ISA mode, ORI and  
BEQ (or BNE) are used in pair to compare the contents of a register and an immediate:  
ORI r10,r0,0x1234  
BEQ r10,r7,Label  
Since the TX19A now has the LUI and ORI instructions, the 16-bit ISA routine can use the same  
sequence of instructions to branch on an arithmetic comparison. Also, the 16-bit ISA provides the  
CMPI instruction that compares a register and an immediate and sets t8 based on their equality.  
The following gives three examples of compare and branch in 16-bit ISA mode.  
z Example 1: Branch if r6 ≥ r7  
The following sequence of instructions checks if the contents of r6 is equal to or greater than the  
contents of r7. If r6 is less than r7, the SLT (Set On Less Than) instruction sets t8 to one.  
Otherwise, t8 is set to zero. The BTEQZ instruction branches to Label if t8 is zero.  
SLT r6,r7  
BTEQZ Label  
z Example 2: Branch if r7 ≥ 0x1234  
The following sequence of instructions checks if the contents of r7 are equal to or greater than  
0x1234. In this example, the SLTI (Set On Less Than Immediate) instruction implicitly sets t8  
based on the magnitude of r7 and 0x1234. Then the BTEQZ instruction branches to Label if t8  
is equal to zero.  
SLTI r7,0x1234  
BTEQZ Label  
z Example 3: Branch if r7 = 0x1234  
The following sequence of instructions checks the equality of the contents of a register and an  
immediate value. In this example, the CMPI (Compare Immediate) instruction compares the  
contents of r7 to 0x1234 and sets t8 to 0 if they are equal. (CMPI actually exclusive-ORs two  
values.)  
CMPI r7,0x1234  
BTEQZ Label  
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Chapter 4 16-Bit ISA Summary and Programming Tips  
4.4.3 Jumping to 32-Bit Addresses  
Since the 16-bit ISA of the TX19A has the LUI and ORI instructions, you can deal with 32-bit  
addresses in the same manner as for the 32-bit ISA. For code density, 32-bit constants can be  
embedded in the code segment, typically between subroutine bodies, in the previous TX19 way;  
then the LW instruction can reference those 32-bit constants using PC-relative addressing.  
– For code density  
LW r4,0(pc)  
JR r4  
– For execution speed  
LUI r4,0x0008  
ORI r4,0x0234  
JR r4  
There is also an instruction (ADDIU, rx, pc, immediate) to calculate a PC-relative address and place  
it in a register.  
4.5 Bit Manipulation Instructions  
The TX19A provides bit manipulation instructions that test or modify a bit in memory. The previous  
TX19 not only requires multiple instructions to manipulate a bit in memory, but also may need  
additional instructions to disable interrupts during a bit manipulation operation. The TX19A  
performs memory bit manipulation with one instruction, helping to decrease code size and increase  
execution speed.  
Table 4-12 Bit Manipulation Instructions  
Opcode  
Name  
Destination  
BTST  
Bit Test  
t8register  
t8register  
Memory  
Memory  
Memory  
Memory  
BEXT  
BCLR  
BSET  
BINS  
Bit Extract  
Bit Clear  
Bit Set  
Bit Insert  
ADDMIU  
Add Immediate to Memory Word  
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Chapter 4 16-Bit ISA Summary and Programming Tips  
4.6 SAVE and RESTORE Instructions  
The TX19A provides the SAVE and RESTORE instructions for stack operations. The SAVE  
instruction saves a set of CPU registers to memory stack with one instruction. The RESTORE  
instruction restores a set of CPU registers from memory stack with one instruction. These  
instructions help to decrease code size, as compared to the TX19 that require multiple instructions  
for stack operations.  
Table 4-13 SAVE and RESTORE Instructions  
Opcode  
Name  
Registers Saved or Restored  
r4-r7, r16, r17, r18-r23, r30, r31  
r4-r7, r16, r17, r18-r23, r30, r31  
Save Registers and  
Set up Stack Frame  
SAVE  
RESTORE  
Restore Registers and Deal  
locate Stack Frame  
4.7 System Control Coprocessor (CP0) Instructions  
The previous TX19 does not have CP0 instructions; it requires that the ISA mode be switched to 32-  
bit ISA (with the JALX instruction, etc.) in order to access the system control coprocessor (CP0).  
The 16-bit ISA of the TX19A now provides CP0 instructions, with the restriction that the IER,  
Config1, Config2 and Config3 registers are inaccessible in 16-bit ISA mode.  
For example, in 32-bit ISA mode, the Interrupt Enable (IE) bit in the Status register can be modified  
by writing a zero or non-zero value to the IER register. However, in 16-bit ISA mode, the CP0  
instruction can not access the IER register, ; to compensate for this restriction, the 16-bit ISA  
provides the EI and DI instructions that sets or clears the IE bit.  
Table 4-14 System Control Coprocessor (CP0) Instructions  
Opcode  
Name  
MFC0  
Move from Coprocessor 0  
MTC0  
AC0IU  
Move to Coprocessor 0  
Add Coprocessor 0 Immediate Unsigned.  
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Chapter 4 16-Bit ISA Summary and Programming Tips  
4.8 Special Instructions  
Special instructions include the BREAK (Breakpoint) and SDBBP (Software Debug Breakpoint)  
instructions as well as the new EI (Enable Interrupt), DI (Disable Interrupt), SYSCALL (System  
Call), SYNC (Synchronize), ERET (Exception Return), DERET (Debug Exception Return) and  
WAIT (Enter Standby Mode) instructions.  
The 16-bit ISA provides an instruction called EXTEND. The purpose of the EXTEND instruction is  
twofold. First, the EXTEND instruction consists of a 5-bit opcode and an 11-bit immediate value. In  
this case, EXTEND does not generate a MIPS machine instruction on its own, but instead  
contributing the 11-bit immediate to be concatenated with the immediate data carried in the  
following 16-bit instruction. This way, EXTEND extends a 16-bit instruction to 32 bits, providing  
large immediate values, as shown in Table 4-9. Second, the 16-bit ISA has several 32-bit  
instructions prepended with the EXTEND code. In such instructions, the 11-bit immediate field is  
replaced with an opcode. The new SYNC, ERET, DERET, WAIT, BS1F, MAX and MIN  
instructions are EXTENDed instructions and have no 16-bit equivalents.  
Table 4-15 EXTENDable Instructions  
Immediate Bit Size  
16-Bit Instruction  
Before EXTENDed After EXTENDed  
LB・LBU  
LH・LHU  
LW  
5 (or 7)  
16  
16  
16  
16  
16  
16  
15  
16  
16  
16  
16  
16  
5
5 (or 6)  
5 (or 8)  
SB  
5 (or 7)  
SH  
5 (or 6)  
SW  
5 (or 8)  
ADDIU  
4
8
SLTI・SLTIU  
CMPI  
LI  
8
8
8
LUI  
⎯
3
SLL  
SRL  
3
5
SRA  
3
5
ANDI  
ORI  
⎯
⎯
⎯
⎯
⎯
16  
16  
16  
16  
14  
XORI  
LUI  
ADDMIU  
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Chapter 4 16-Bit ISA Summary and Programming Tips  
Immediate Bit Size  
Before EXTENDed After EXTENDed  
16-Bit Instruction  
BEQZ  
BNEZ  
BTEQZ  
BTNEZ  
B
8
8
8
8
11  
8
5
5
5
5
5
4
4
16  
16  
16  
16  
16  
16  
14  
14  
14  
14  
14  
8
BAL  
BTST  
BEXT  
BCLR  
BSET  
BINS  
SAVE・  
SAVE  
RESTORE  
RESTORE  
8
Bit  
Field  
BFINS  
⎯
5
EXTEND does not need to start on a word boundary. There is one restriction on the use of  
EXTEND; it may not be placed in a jump delay slot since its outcome is undefined. You do not need  
to explicitly place EXTEND before a 16-bit instruction with an immediate field. If  
you specify an immediate longer than permitted in the 16-bit ISA, the assembler will automatically  
break it down to smaller immediates using EXTEND. For example, the instruction:  
ADDIU r3,0x1234  
is an RI (register-immediate) type instruction, and the immediate field is only 8-bits long. Thus, this  
instruction is EXTENDed to 32 bits using the EXT-RI instruction format. This is illustrated in  
Figure 4-16.  
RI Type  
15  
1110  
8 7  
0
ADDIU8  
01001  
rx  
011  
imm  
EXT-RI Type  
31  
27 26  
21  
16 15  
11 10  
8 7  
5 4  
0
EXTEND  
11110  
imm[10:5]  
01000  
imm[15:11]  
00010  
ADDIU8  
01001  
rx  
imm[4:0]  
10010  
011  
000  
Figure 4-16 RI Format vs. EXT-RI Format  
"ADDIU, ry, rx, immediate" has a 4-bit immediate field. Since EXTEND can only supply 11 more  
bits, it enlarges the immediate only to 15 bits.  
Also, even when EXTENDed, the SLL, SRL and SRA instructions have a 5-bit immediate; the bit  
manipulation instructions have a 14-bit immediate; and the BFINS instruction has a 5-bit immediate  
(see Table 4-15).  
4-20  
Chapter 4 16-Bit ISA Summary and Programming Tips  
4.9 Instruction Summary  
This section provides an overview of the instructions in the 16-bit ISA.  
„
Notational Conventions  
In this section, all variable fields in an instruction format are shown in italicized lowercase letters,  
like rx, ry, rz, immediate and sa (shift amount). For the sake of clarity, an alias is sometimes used to  
refer to a field in the formats of specific instructions. For example, base and offset are used instead  
of rx and immediate in the formats of load and store instructions. Certain instructions can use r24  
(t8), r28 (gp), r29 (sp), r30 (fp) and r31 (ra) for specific purposes. These registers are shown as t8,  
gp, sp, fp and ra. HI and LO are the special registers that hold the results of integer multiply and  
divide operations.  
„
Instructions Not Implemented in the TX19A  
The TX19A does not provide support for the MIPS16eASE instructions that manipulate 64-bit  
doubleword operands. See Appendix D for a list of complete comparisons among the TX19A, the  
TX19 and the MIPS16.  
Table 4-17 Load and Store Instructions (16-Bit ISA)  
Instruction  
Format  
Operation  
The 5-bit offset is zero-extended and added to base to form an  
Load Byte  
LB  
ry, offset(base)  
effective address. The byte in memory addressed by the EA is  
sign-extended and loaded into ry.  
The 5-bit offset is zero-extended and added to base to form an  
Load Byte Unsigned LBU  
ry, offset(base)  
effective address. The byte in memory addressed by the EA is  
zero-extended and loaded into ry.  
The 7-bit offset is zero-extended and added to sp to form an effective  
address. The byte in memory addressed by the EA is zero-extended  
* LBU ry, offset(sp)  
* LBU ry, offset(fp)  
and loaded into ry.  
The 7-bit offset is zero-extended and added to fp to form an effective  
address. The byte in memory addressed by the EA is zero-extended  
and loaded into ry.  
The 5-bit offset is shifted left by one bit, zero-extended and added to  
base to form an effective address. The halfword in memory  
Load Halfword  
LH  
ry, offset(base)  
ry, offset(base)  
addressed by the EA is sign-extended and loaded into ry.  
The 5-bit offset is shifted left by one bit, zero-extended and added to  
base to form an effective address. The halfword in memory  
Load Halfword  
Unsigned  
LHU  
addressed by the EA is zero-extended and loaded into ry.  
The 6-bit offset is shifted left by one bit, zero-extended and added to  
sp to form an effective address. The halfword in memory addressed  
* LHU ry, offset(sp)  
* LHU ry, offset(fp)  
by the EA is zero-extended and loaded into ry.  
The 6-bit offset is shifted left by one bit, zero-extended and added to  
fp to form an effective address. The halfword in memory addressed  
by the EA is zero-extended and loaded into ry.  
* Enhancements from the TX19 to the TX19A  
4-21  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Instruction  
Format  
Operation  
The 5-bit offset is shifted left by two bits, zero-extended and added to  
base to form an effective address. The word in memory addressed by  
Load Word  
LW  
LW  
ry, offset(base)  
the EA is loaded into ry.  
The 8-bit offset is shifted left by two bits, zero-extended and added to  
the masked PC value (i.e., PC value with the lower two bits cleared)  
to form an effective address. The word in memory addressed by the  
rx, offset(pc)  
EA is loaded into rx.  
The 8-bit offset is shifted left by two bits, zero-extended and added to  
sp to form an effective address. The word in memory addressed by  
LW  
rx, offset(sp)  
ry, offset(fp)  
ry, offset(base)  
ry, offset(sp)  
ry, offset(fp)  
ry, offset(base)  
ry, offset(sp)  
ry, offset(fp)  
ry, offset(base)  
rx, offset(sp)  
ra, offset(sp)  
ry, offset(fp)  
the EA is loaded into rx.  
The 5-bit offset is shifted left by two bits, zero-extended and added to  
fp to form an effective address. The word in memory addressed by  
* LW  
SB  
the EA is loaded into ry.  
The 5-bit offset is zero-extended and added to base to form an  
effective address. The least-significant byte in ry is stored in memory  
Store Byte  
addressed by the EA.  
The 7-bit offset is zero-extended and added to sp to form an effective  
address. The least-significant byte in ry is stored in memory  
* SB  
* SB  
SH  
addressed by the EA.  
The 7-bit offset is zero-extended and added to fp to form an effective  
address. The least-significant byte in ry is stored in memory  
addressed by the EA.  
The 5-bit offset is shifted left by one bit, zero-extended and added to  
base to form an effective address. The low-order halfword in ry is  
Store Halfword  
stored in memory addressed by the EA.  
The 6-bit offset is shifted left by one bit, zero-extended and added to  
sp to form an effective address. The low-order halfword in ry is stored  
* SH  
* SH  
SW  
in memory addressed by the EA.  
The 6-bit offset is shifted left by one bit, zero-extended and added to  
fp to form an effective address. The low-order halfword in ry is stored  
in memory addressed by the EA.  
The 5-bit offset is shifted left by two bits, zero-extended and added to  
base to form an effective address. ry is stored in memory addressed  
Store Word  
by the EA.  
The 8-bit offset is shifted left by two bits, zero-extended and added to  
sp to form an effective address. rx is stored in memory addressed by  
SW  
the EA.  
The 8-bit offset is shifted left by two bits, zero-extended and added to  
sp to form an effective address. ra is stored in memory addressed by  
SW  
the EA.  
The 5-bit offset is shifted left by two bits, zero-extended and added to  
fp to form an effective address. ry is stored in memory addressed by  
* SW  
the EA.  
* Enhancements from the TX19 to the TX19A  
4-22  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Table 4-18 ALU Immediate Instructions (16-Bit ISA)  
Instruction  
Format  
Operation  
The 4-bit immediate is sign-extended and added to rx. The result is  
placed into ry. Does not cause an exception on 2’s-complement  
Add Immediate  
ADDIU ry, rx, immediate  
overflow.  
The 8-bit immediate is sign-extended and added to rx. The result is  
ADDIU rx, immediate  
placed back into rx. Does not cause an exception on 2’s-complement  
overflow.  
The 8-bit immediate is shifted left by three bits and sign-extended.  
The resultant value is added to sp and the sum is placed back into  
ADDIU sp, immediate  
* ADDIU fp, immediate  
ADDIU rx, pc, immediate  
sp. Does not cause an exception on 2’s-complement overflow.  
The 8-bit immediate is shifted left by two bits and sign-extended.  
The resultant value is added to fp and the sum is placed back into  
fp. Does not cause an exception on 2’s-complement overflow.  
The 8-bit immediate is shifted left by two bits and zero-extended.  
The resultant value is added to the masked PC value (i.e., PC value  
with the lower two bits cleared) and the sum is placed into rx. Does  
not cause an exception on 2’s-complement overflow.  
The 8-bit immediate is shifted left by two bits and zero-extended.  
The resultant value is added to sp and the sum is placed into rx.  
ADDIU rx, sp, immediate  
Does not cause an exception on 2’s-complement overflow.  
t8 = 1 if rx is less than immediate; otherwise t8 = 0. The 8-bit  
immediate is zero-extended. Two values are compared as signed  
Set On Less Than  
Immediate  
SLTI  
rx, immediate  
integers.  
t8 = 1 if rx is less than immediate; otherwise t8 = 0. The 8-bit  
immediate is zero-extended. Two values are compared as unsigned  
Set On Less Than  
SLTIU rx, immediate  
Immediate Unsigned  
integers.  
t8 = 0 if rx = immediate; otherwise t8 ꢀ 0. The 8-bit immediate is  
Compare Immediate CMPI rx, immediate  
zero-extended.  
Load Immediate  
* Logical AND  
Immediate  
LI  
rx, immediate  
ry, immediate  
The 8-bit immediate is zero-extended and loaded into rx.  
The contents of ry is ANDed with immediate and the result is placed  
ANDI  
back into ry. The 16-bit immediate is zero-extended.  
The contents of ry is ORed with immediate and the result is placed  
back into ry. The 16-bit immediate is zero-extended.  
* Logical OR  
Immediate  
ORI  
ry, immediate  
The contents of ry is exclusive-ORed with immediate and the result  
is placed back into ry. The 16-bit immediate is zero-extended.  
* Logical  
XORI ry, immediate  
Exclusive_OR  
Immediate  
The 16-bit immediate is shifted left by 16 bits and concatenated to  
16 bits of zeros. The result is placed into ry.  
* Load Upper  
Immediate  
LUI  
ry, immediate  
* Enhancements from the TX19 to the TX19A  
4-23  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Table 4-19 Register-Type Instructions (16-Bit ISA)  
Instruction  
Format  
Operation  
Add Unsigned  
ADDU rz, rx, ry  
The sum rx + ry is placed into rz. Does not cause an exception on  
2’s-complement overflow.  
Subtract Unsigned  
Set On Less Than  
SUBU rz, rx, ry  
The remainder rx - ry is placed into rz. Does not cause an exception on  
2’scomplement overflow.  
t8 = 1 if rx is less than ry; otherwise t8 = 0. Two values are compared  
SLT  
rx, ry  
as signed integers.  
t8 = 1 if rx is less than ry; otherwise t8 = 0. Two values are compared  
Set On Less Than  
Unsigned  
Compare  
Negate  
SLTU rx, ry  
as unsigned integers.  
CMP  
NEG  
AND  
rx, ry  
rx, ry  
rx, ry  
t8 = 0 if rx is equal to ry; otherwise t8 = 0.  
rx = 0 - ry (2’s-complement)  
The contents of rx is ANDed with the contents of ry and the result is  
AND  
placed back into rx.  
The contents of rx is ORed with the contents of ry and the result is  
OR  
OR  
rx, ry  
rx, ry  
rx, ry  
placed back into rx.  
The contents of rx is exclusive-ORed with the contents of ry and the  
Exclusive-OR  
XOR  
result is placed back into rx.  
Not  
NOT  
ry is inverted bitwise and the result is placed into rx. (1’scomplement)  
The contents of r32 is copied into ry.  
Move  
MOVE  
MOVE  
ry, r32  
r32, rz  
The contents of rz are copied into r32.  
* MOVE fp, r32  
BS1F ry, rx  
The contents of r32 is copied into fp.  
rx is searched for the first set bit, starting from bit 0 towards bit 31. If  
a set bit is found in rx, its bit position (bit number plus 1) is placed  
* Bit Search One  
Forward  
into ry. If no set bit is found in rx, the value written to ry is 0.  
A bit field indicated by [(bit2 – bit1):0] in rx is copied into a location  
* Bit Field Insert  
BFINS ry, rx, bit2, bit1  
indicated by (bit2:bit1) in ry.  
The contents of rx is compared to the contents of ry as signed  
values. If rx is greater than ry, the value of rx is written to rz.  
* Maximum Signed  
MAX  
MIN  
rz, rx, ry  
rz, rx, ry  
Otherwise, the value of ry is written to rz.  
The contents of rx is compared to the contents of ry as signed  
values. If rx is less than ry, the value of rx is written to rz. Otherwise,  
* Minimum Signed  
* Sign-Extend Byte  
the value of ry is written to rz.  
The least-significant byte in rx is sign-extended. The result is placed  
SEB  
SEH  
rx  
rx  
back into rx.  
The low-order halfword in rx is sign-extended. The result is placed  
* Sign-Extend  
Halfword  
back into rx.  
The least-significant byte in rx is zero-extended. The result is placed  
* Zero-Extend Byte  
ZEB  
ZEH  
rx  
rx  
back into rx.  
The low-order halfword in rx is zero-extended. The result is placed  
* Zero-Extend  
Halfword  
back into rx.  
The contents of rx are added to the contents of ry. The sum saturates  
to the largest representable positive number (0x7FFF_FFFF) on  
overflow and to the smallest representable negative number  
(0x8000_0000) on underflow. The result is placed into ry. If overflow  
* Saturated  
Additional  
SADD  
ry, rx, ry  
or underflow does not occur, the sum of rx and ry is placed into ry.  
The contents of ry are subtracted from the contents of rx. On overflow,  
the remainder saturates to the largest representable positive number  
(0x7FFF_FFFF) if rx is zero or a positive number and to the smallest  
representable negative number (0x8000_0000) if rx is a negative  
number. The result is placed into ry. If overflow does not occur, the  
* Saturated  
SSUB  
ry, rx, ry  
Subtraction  
remainder is placed into ry.  
* Enhancements from the TX19 to the TX19A  
4-24  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Table 4-20 Shift Instructions (16-Bit ISA)  
Instruction  
Format  
Operation  
The contents of ry are shifted left by sa bits. Zeros are supplied to the  
Shift Left Logical  
SLL  
rx, ry, sa  
ry, sa  
vacated positions on the right. The 32-bit result is placed into rx.  
The contents of ry are shifted left by sa bits. Zeros are supplied to the  
vacated positions on the right. The 32-bit result is placed back into  
* SLL  
ry.  
The contents of ry is shifted left the number of bits specified by the  
five least-significant bits of rx. Zeros are supplied to the vacated  
Shift Left Logical  
Variable  
SLLV  
ry, rx  
positions on the right.  
The contents of ry are shifted right by sa bits. Zeros are supplied to the  
Shift Right Logical  
SRL  
rx, ry, sa  
ry, sa  
vacated positions on the left. The 32-bit result is placed into rx.  
The contents of ry are shifted right by sa bits. Zeros are supplied to the  
* SRL  
SRLV  
vacated positions on the left. The 32-bit result is placed back into ry.  
The contents of ry is shifted right the number of bits specified by the  
Shift Right Logical  
Variable  
ry, rx  
five least-significant bits of rx. The 32-bit result is placed back into ry.  
The contents of ry are shifted right by sa bits. The sign bit is copied to  
Shift Right Arithmetic SRA  
rx, ry, sa  
ry, sa  
the vacated positions on the left. The 32-bit result is placed into rx.  
The contents of ry are shifted right by sa bits. The sign bit is copied to  
the vacated positions on the left. The 32-bit result is placed back into  
* SRA  
ry.  
The contents of ry is shifted right the number of bits specified by the  
five least-significant bits of rx. The sign bit is copied to the vacated  
Shift Right Arithmetic SRAV  
Variable  
ry, rx  
positions on the left.  
* Enhancements from the TX19 to the TX19A  
Table 4-21 SAVE and RESTORE Instructions (16-Bit ISA)  
Instruction  
Format  
Operation  
A set of registers indicated by reg_list3 is saved to memory, and the  
contents of sp are adjusted by framesize4.  
* SAVE  
SAVE  
SAVE  
reg_list3,  
framesize4  
reg_list3,  
A set of registers indicated by reg_list3, xsregs and aregs is saved to  
memory, and the contents of sp are adjusted by framesize8.  
xsregs, aregs,  
framesize8  
A set of registers indicated by reg_list3 is restored from memory, and  
the contents of sp are adjusted by framesize4.  
* RESTORE  
RESTORE reg_list3,  
framesize4  
A set of registers indicated by reg_list3, xsregs and aregs is restored  
from memory, and the contents of sp is adjusted by framesize8.  
RESTORE reg_list3,  
xsregs, aregs,  
framesize8  
* Enhancements from the TX19 to the TX19A  
4-25  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Table 4-22 Multiply and Divide Instructions (16-Bit ISA)  
Instruction  
Format  
Operation  
The multiplicand is the signed value of rx. The multiplier is the signed  
value of ry. The 64-bit product rx * ry is placed into registers HI and  
Multiply  
MULT  
rx, ry  
LO.  
The multiplicand is the signed value of rx. The multiplier is the signed  
value of ry. The 64-bit product rx * ry is placed into registers HI and  
* MULT ry, rx, ry  
MULTU rx, ry  
LO. The low-order 32 bits of the product are copied into ry.  
The multiplicand is the unsigned value of rx. The multiplier is the  
unsigned value of ry. The 64-bit product rx * ry is placed into  
Multiply Unsigned  
registers HI and LO.  
The multiplicand is the unsigned value of rx. The multiplier is the  
unsigned value of ry. The 64-bit product rx * ry is placed into  
registers HI and LO. The low-order 32 bits of the product are copied  
* MULTU ry, rx, ry  
into ry.  
The multiplicand is the signed value of rx. The multiplier is the signed  
value of ry. The 64-bit product rx * ry is added to the contents of  
* Multiply And Add  
MADD  
rx, ry  
registers HI and LO and the result is placed back into HI and LO.  
The multiplicand is the unsigned value of rx. The multiplier is the  
unsigned value of ry. The 64-bit product rx * ry is added to the  
contents of registers HI and LO and the result is placed back into HI  
* Multiply And Add  
MADDU rx, ry  
Unsigned  
and LO.  
The dividend is the signed value of rx. The divisor is the signed value  
of ry. The quotient is placed into register LO and the remainder is  
Divide  
DIV  
rx, ry  
rx, ry  
rx, ry  
placed into register HI.  
The dividend is the unsigned value of rx. The divisor is the unsigned  
value of ry. The quotient is placed into register LO and the remainder  
Divide Unsigned  
* Divide Exception  
DIVU  
DIVE  
is placed into register HI.  
The dividend is the signed value of rx. The divisor is the signed value  
of ry. The quotient is placed into register LO and the remainder is  
placed into register HI. An Integer Overflow exception occurs if  
divide-by-zero or overflow conditions are detected.  
The dividend is the unsigned value of rx. The divisor is the unsigned  
value of ry. The quotient is placed into register LO and the remainder  
is placed into register HI. An Integer Overflow exception occurs if a  
* Divide Exception  
DIVEU rx, ry  
Unsigned  
divide-by-zero condition is detected.  
Move From HI  
Move From LO  
* Move to HI  
* Move to LO  
MFHI  
MFLO  
MTHI  
MTLO  
rx  
rx  
rx  
rx  
The contents of register HI is copied to rx.  
The contents of register LO are copied to rx.  
The contents of rx are copied to register HI.  
The contents of rx are copied to register LO.  
* Enhancements from the TX19 to the TX19A  
4-26  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Table 4-23 Bit Manipulation Instructions (16-Bit ISA)  
Instruction  
Format  
Operation  
A bit specified by pos3 in a memory byte is negated and placed into  
the least-significant bit (LSB) of t8. The upper 31 bits of t8 are filled  
with zeros. The effective address is computed by zero-extending the  
* Bit Test  
BTST  
BTST  
BTST  
BEXT  
offset(base3),  
pos3  
14-bit offset and adding the resultant value to the contents of base3.  
A bit specified by pos3 in a memory byte is negated and placed into  
the least-significant bit (LSB) of t8. The upper 31 bits of t8 are filled  
with zeros. The effective address is computed by sign-extending the  
offset(r0), pos3  
14-bit offset and adding the resultant value to the contents of r0.  
A bit specified by pos3 in a memory byte is negated and placed into  
the least-significant bit (LSB) of t8. The upper 31 bits of t8 are filled  
with zeros. The effective address is computed by zero-extending the  
offset(fp), pos3  
5-bit offset and adding the resultant value to the contents of fp.  
* Bit Extract  
offset(base3), A bit specified by pos3 in a memory byte is copied into the  
pos3  
least-significant bit (LSB) of t8. The upper 31 bits of t8 are filled with  
zeros. The effective address is computed by zero-extending the 14-bit  
offset and adding the resultant value to the contents of base3.  
BEXT  
BEXT  
offset(r0), pos3 A bit specified by pos3 in a memory byte is copied into the  
least-significant bit (LSB) of t8. The upper 31 bits of t8 are filled with  
zeros. The effective address is computed by sign-extending the 14-bit  
offset and adding the resultant value to the contents of r0.  
offset(fp), pos3 A bit specified by pos3 in a memory byte is copied into the  
least-significant bit (LSB) of t8. The upper 31 bits of t8 are filled with  
zeros. The effective address is computed by zero-extending the 5-bit  
offset and adding the resultant value to the contents of fp.  
A bit specified by pos3 in a memory byte is cleared. The effective  
address is computed by zero-extending the 14-bit offset and adding  
* Bit Clear  
BCLR  
BCLR  
BCLR  
BSET  
BSET  
BSET  
offset(base3),  
pos3  
the resultant value to the contents of base3.  
A bit specified by pos3 in a memory byte is cleared. The effective  
address is computed by sign-extending the 14-bit offset and adding  
offset(r0), pos3  
the resultant value to the contents of r0.  
A bit specified by pos3 in a memory byte is cleared. The effective  
address is computed by zero-extending the 5-bit offset and adding  
offset(fp), pos3  
the resultant value to the contents of fp.  
A bit specified by pos3 in a memory byte is set. The effective address  
is computed by zero-extending the 14-bit offset and adding the  
* Bit Set  
offset(base3),  
pos3  
resultant value to the contents of base3.  
A bit specified by pos3 in a memory byte is set. The effective address  
is computed by sign-extending the 14-bit offset and adding the  
offset(r0), pos3  
resultant value to the contents of r0.  
A bit specified by pos3 in a memory byte is set. The effective address  
is computed by zero-extending the 5-bit offset and adding the  
offset(fp), pos3  
resultant value to the contents of fp.  
4-27  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Instruction  
Format  
Operation  
The least-significant bit (LSB) of t8 is copied into a bit position  
indicated by pos3 in a memory byte. The effective address is  
computed by zero-extending the 14-bit offset and adding the  
* Bit Insert  
BINS  
BINS  
BINS  
offset(base3),  
pos3  
resultant value to the contents of base3.  
The least-significant bit (LSB) of t8 is copied into a bit position  
indicated by pos3 in a memory byte. The effective address is  
computed by sign-extending the 14-bit offset and adding the resultant  
offset(r0), pos3  
value to the contents of r0.  
The least-significant bit (LSB) of t8 is copied into a bit position  
indicated by pos3 in a memory byte. The effective address is  
computed by zero-extending the 5-bit offset and adding the resultant  
offset(fp), pos3  
value to the contents of fp.  
The 14-bit offset is shifted left by two bits, zero-extended, then added  
to the contents of base3 to form an effective address (EA). The value  
indicated by imm is added to the memory word addressed by the EA,  
* Add Immediate to  
ADDMIU offset(base3),  
Memory Word  
imm  
and the sum is written back to the EA.  
The 14-bit offset is shifted left by two bits, sign-extended, then added  
to the contents of r0 to form an effective address (EA). The value  
indicated by imm is added to the memory word addressed by the EA,  
ADDMIU offset(r0), imm  
and the sum is written back to the EA.  
* Enhancements from the TX19 to the TX19A  
Table 4-24 System Control Coprocessor (CP0) Instructions (16-Bit ISA)  
Instruction  
Format  
Operation  
* Move To  
MTC0  
MFC0  
AC0IU  
rx, cp0rd32  
The contents of rx are loaded into CP0 register cp0rd32.  
Coprocessor 0  
* Move From  
Coprocessor 0  
* Add Coprocessor 0  
Immediate  
ry, cp0rs32  
The contents of CP0 register cp0rs32 is loaded into ry.  
The value indicated by immediate is added to the contents of CP0  
register cp0rt32. The result is placed back into cp0rt32.  
cp0rt32,  
immediate  
Unsigned  
* Enhancements from the TX19 to the TX19A  
4-28  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Table 4-25 Jump Instructions (16-Bit ISA)  
Instruction  
Format  
Operation  
The program jumps to the address computed using paged absolute  
addressing, i.e., by shifting the 26-bit target left by two bits and  
combining it with the four most-significant bits of PC + 4. The  
Jump And Link  
JAL  
target  
address of the instruction following the delay slot is saved in r31.  
The program jumps to the address using paged absolute addressing,  
i.e., by shifting the 26-bit target left by two bits and combining it with  
the four most-significant bits of PC + 4. The address of the instruction  
following the delay slot is saved in r31. The ISA mode bit in the PC  
Jump And Link  
exchange  
JALX  
target  
toggles.  
The program jumps to the address specified by the upper 31 bits of  
rx. The least-significant bit of rx is interpreted as the ISA mode  
Jump Register  
JR  
rx  
specifier.  
The program jumps to the address specified by the upper 31 bits of  
ra. The least-significant bit of ra is interpreted as the ISA mode  
JR  
ra  
specifier.  
The program jumps to the address specified by the upper 31 bits of  
rx. The least-significant bit of rx is interpreted as the ISA mode  
* Jump Register,  
JRC  
JRC  
JALR  
rx  
Compact  
specifier. This instruction does not have a delay slot.  
The program jumps to the address specified by the upper 31 bits of  
ra. The least-significant bit of ra is interpreted as the ISA mode  
ra  
specifier. This instruction does not have a delay slot.  
The program jumps to the address specified by the upper 31 bits of  
rx. The least-significant bit of rx is interpreted as the ISA mode  
specifier. The address of the instruction following the delay slot is  
Jump And Link  
Register  
ra, rx  
saved in ra.  
The program jumps to the address specified by the upper 31 bits of  
rx. The least-significant bit of rx is interpreted as the ISA mode  
specifier. The address of the instruction following the delay slot is  
* Jump And Link  
JALRC ra, rx  
Register, Compact  
saved in ra. This instruction does not have a delay slot.  
* Enhancements from the TX19 to the TX19A  
Table 4-26 Branch Instructions (16-Bit ISA)  
Instruction  
Format  
Operation  
If rx = 0, the program branches to the target address specified as a  
8-bit offset relative to PC + 2 (or PC + 4 when EXTENDed).  
If rx ≠ 0, the program branches to the target address specified as a  
8-bit offset relative to PC + 2 (or PC + 4 when EXTENDed).  
If t8 = 0, the program branches to the target address specified as a  
16-bit offset relative to PC + 2 (or PC + 4 when EXTENDed).  
If t8 ≠ 0, the program branches to the target address specified as a  
16-bit offset relative to PC + 2 (or PC + 4 when EXTENDed).  
Branch On Equal To BEQZ  
Zero  
rx, offset  
Branch On Not Equal BNEZ  
To Zero  
rx, offset  
Branch On T8 Equal BTEQZ offset  
To Zero  
Branch On T8 Not  
Equal To Zero  
BTNEZ offset  
The program unconditionally branches to the target address  
specified as a 16-bit offset relative to PC + 2 (or PC + 4 when  
Unconditional Branch B  
offset  
offset  
EXTENDed).  
The program unconditionally branches to the target address  
specified as a 16-bit offset relative to PC + 2 (or PC + 4 when  
EXTENDed). The address of the instruction following the delay slot is  
* Branch And Link  
BAL  
saved in r31.  
* Enhancements from the TX19 to the TX19A  
4-29  
Chapter 4 16-Bit ISA Summary and Programming Tips  
Table 4-27 Special Instructions (16-Bit ISA)  
Instruction  
Breakpoint  
Format  
Operation  
A breakpoint exception occurs, immediately and unconditionally  
transferring control to the exception handler.  
BREAK code  
A debug breakpoint exception occurs, immediately and  
unconditionally transferring control to the exception handler.  
Software Debug  
Breakpoint Exception  
SDBBP code  
* Disable Interrupt  
* Enable Interrupt  
* System Call  
DI  
The IE bit in the Status register is cleared.  
EI  
The IE bit in the Status register is set.  
A System Call exception occurs, immediately and unconditionally  
transferring control to the exception handler.  
SYSCALL code  
The instruction pipeline is interlocked until any load or store fetched  
before the current instruction is completed.  
* Synchronize  
SYNC  
ERET  
If the ERL bit in the Status register is set, the PC is restored from the  
Error PC register. Otherwise, the PC is restored from the EPC  
* Exception Return  
register  
Program control is transferred back to a User program from a debug  
exception handler. The return address in the DEPC register is  
* Debug Exception  
DERET  
WAIT  
Return  
restored into the PC.  
If the RP bit in the Status register is set, the processor enters DOZE  
mode. If the RP bit is cleared, the processor enters HALT mode.  
* Enter Standby  
Mode  
* Enhancements from the TX19 to the TX19A  
4-30  
Chapter 5 CPU Pipeline  
Chapter 5 CPU Pipeline  
5.1 Architecture Overview  
As described in Section 2.5, Pipeline Architecture, the processing of an instruction is broken down  
into a sequence of simpler suboperations. Because tasks required to process an instruction are  
fragmented, an instruction does not need the entire hardware resources of the execution unit. Each  
suboperation is performed by a separate hardware section called a stage, and each stage passes its  
result to a succeeding stage. The TX19A pipeline has five stages, Fetch (F), Decode (D), Execute  
(E), Memory Access (M) and Register Write-back (W). For example, after an instruction completes  
the D stage, it can proceed to the E stage while the subsequent instruction can advance into the D  
stage. Each of the five pipe stages requires approximately one clock cycle. Therefore, once the  
pipeline has been filled, the execution of five instructions is overlapped at a time, as shown in  
Figure 5-1.  
F
D
E
M
W
Instruction  
Fetch  
Memory  
Access  
Register  
Write-back  
Decode  
Execute  
Time  
#1  
#2  
#3  
#4  
#5  
F
D
F
E
D
F
M
E
D
F
W
M
E
W
M
E
W
M
E
D
F
W
M
D
W
1 Clock Cycle  
Current CPU Cycle  
Figure 5-1 Five CPU Pipeline Stages  
The following paragraphs describe the operations in each stage that occur for the most-commonly  
used instructions.  
Instruction Fetch (F): In this stage, the instruction is fetched from the instruction memory  
subsystem (i.e., instruction ROM or instruction RAM). Instructions are fetched in one-word units,  
whether in 16-bit or 32-bit ISA mode.  
Decode (D): During this stage, the instruction is decoded and required operands are  
read from the on-chip register file.  
Execute (E): In this stage, one of the following occurs:  
z The arithmetic logic unit (ALU) starts the integer arithmetic, logical  
or shift operation.  
z For load and store instructions, the ALU initiates the bus cycle and calculates the effective  
address by adding the offset value to the contents of the base register at the same time.  
z For jump instructions, the ALU calculates the jump target address.  
5-1  
Chapter 5 CPU Pipeline  
z For branch and branch-likely instructions, the ALU determines  
whether the branch condition is true and calculates the branch target address.  
Memory Access (M): For loads and stores, data memory is accessed.  
Register Write-back (W): In this stage, one of the following occurs:  
z The results of the ALU operation during the E stage is written back to  
the on-chip register file.  
z If the instruction is a jump-and-link, branch-and-link or branch-likely-and-link, the return  
address is written to register r31 (ra).  
In a pipelined machine like the TX19A, there are certain instructions that can potentially disrupt the  
smooth advance through the pipeline. This problem is referred to as pipeline hazards. The sections  
that follow describe when pipeline hazards occur and how they are handled by hardware and  
software.  
5.2 Load, Store and SYNC Instructions  
The performance of software systems is drastically affected by how well software designers,  
especially assembly-language programmers, understand the basic hardware technologies at work in  
the processor. This section describes load delays, non-blocking loads, shared memory  
synchronization and so on from the view point of the CPU pipeline.  
5.2.1  
Load Delays  
Figure 5-2 illustrates how the load instruction advances through the CPU pipeline.  
F
D
E
M
W
Effective Address  
Calculation &  
Bus Cycle Initiation  
Instruction  
Fetch  
Memory  
Access  
Resister  
Write-back  
Decode  
Figure 5-2 Load Instruction  
Load instructions read an operand from memory into a CPU register for a subsequent operation by  
other instructions. In the case of loads from the on-chip fast memory, an operand becomes available  
after completion of the Memory Access (M) stage of the load instruction because it is internally  
forwarded at the M stage before the Register Write-back (W) stage. Still, the operand is not  
immediately usable for the Execute (E) cycle of the subsequent instruction, as shown in Figure 5-3.  
This is called data dependency. In Figure 5-3, the TX19A handles data dependency by inserting a  
wait (or "stall") cycle into the E stage of the next instruction. Figure 5-3 depicts a delay (or latency)  
of one cycle. The instruction that immediately follows the load instruction is said to be in the load  
delay slot. Loads from external memory incur additional stall cycles.  
5-2  
Chapter 5 CPU Pipeline  
F
D
F
E
M
D
W
LW  
r3,0(r1)  
r3  
Ds  
E
M
W
ADD r8,r9,r3  
Stall Cycle  
Figure 5-3 Data Dependency Resulting from a Load Instruction  
However, this is not a very efficient use of the pipeline. The optimizer, which is executed as a part of  
the compiler or assembler, can rearrange the code to ensure that the instruction in the load delay slot  
does not require the operand loaded by the previous load instruction. Figure 5-4 gives an example of  
re-ordering instructions to remove data dependency. This is a part of the code to swap the contents of  
two memory locations.  
•
With data dependency  
LW r9,0(r8)  
LW r10,4(r8)  
SW r10,0(r8) ← Load delay slot  
SW r9,4(r8)  
•
Without data dependency  
LW r9,0(r8)  
LW r10,4(r8)  
SW r9,4(r8) ← Load delay slot  
SW r10,0(r8)  
Figure 5-4 Re-ordering Instructions to Remove Data Dependency  
In the rearranged code, the SW instruction does not depend on the availability of data from the  
immediately preceding LW instruction. Therefore, the load delay slot for "LW r10, 4 (r8)" can be  
filled with a useful instruction, "SW r9, 0(r8)," so that the pipeline is fully utilized.  
5-3  
Chapter 5 CPU Pipeline  
5.2.2 Non-blocking Loads  
If the instruction that immediately follows a load instruction does not access the target register (rt)  
of the load instruction, data dependency does not occur. The TX19A recognizes the presence of data  
dependency, and if there is no data dependency, it continues to execute subsequent instructions. This  
is called non-blocking loads. By virtue of non-blocking loads, external memory accesses do not stall  
the CPU pipeline. All the other parts of the pipeline can continue to work on non-dependent  
instructions while external memory is being accessed.  
In Figure 5-5 below, the TX19A continues to execute independent instructions (ADD, r6, r4, r2 and  
ADD r7, r5, r2) without stalling on the external memory access resulting from the LW  
Instruction. It defers execution of a dependent instruction (ADD, r8, r9, r3) until the data has been  
returned.  
Memory Read Cycles  
LW  
r3,0(r1)  
F
D
F
E
D
F
････  
M
W
ADD r6,r4,r2  
ADD r7,r5,r2  
ADD r8,r9,r3  
E
D
F
M
E
W
M
r3  
W
Ds  
Ds  
Ds  
D
E
M
W
Stall Cycles  
Figure 5-5 Non-blocking Loads  
The non-blocking load capability of the TX19A allows the optimizing compiler to rearrange the code  
to "prefetch" data from memory before a need actually arises to reference it. Selective use of  
prefetches based on the compiler’s optimization can yield significant performance improvement.  
5-4  
Chapter 5 CPU Pipeline  
5.2.3 Store Instructions (32 Bit ISA/ 16 Bit ISA)  
Figure 5-6 illustrates how the store instruction advances through the CPU pipeline.  
F
D
E
M
W
Effective Address  
Calculation &  
Bus Cycle Initiation  
Instruction  
Fetch  
Mempory Access  
in WAIT  
Decode  
―
Figure 5-6 Store Instruction  
Stores to the on-chip fast memory occur during the Memory Access (M) stage; no operation occurs  
in the Register Write-back (W) stage. Stores to external memory take more than one cycle.  
The store instruction is to store the data in CPU register to the memory. Figure 5-7 shows how to store  
to the on-chip fast memory. Stores to the on-chip fast memory occur during the Effective Address  
Calculation (E) stage and they take 1 clock as a write bus cycle. No operations occur in the Memory  
Access stage and the Register Write-back stage.  
Figure 5－8 shows the procedure to execute the instruction on the external memory access. Stores to  
the external memory take more than 2 clocks as a write bus cycle. With the TX19A, the pipelines  
never stall by the continuous memory access instructions because its on-chip write buffer can store 4  
write-data at the maximum. The instructions using subsequent write buffer stall when the write buffer  
space is full.  
Write Cycle  
Bus Cycle  
SW  
r3,4(r2)  
F
D
F
E
D
F
M
E
W
M
E
ADDU r4,r3,r2  
ADDU r5,r6,r7  
W
M
D
W
Figure 5-7 Access to the On-chip Fast Memory  
Write Cycle  
Bus Cycle  
Instruction3  
Instruction1 Instruction2  
Write Buffer  
Instruction 1 SW r4,4(r2)  
Instruction 2 SW r5,8(r2)  
Instruction 3 SW r6,12(r2)  
F
D
F
E
D
F
M
E
W
M
E
W
M
D
W
Figure 5-8 Continuous Access to the External Memory  
5-5  
Chapter 5 CPU Pipeline  
5.2.4 SYNC Instruction (32 Bit ISA/ 16 Bit ISA)  
Load and store instructions execute memory accesses during the M stage. In the meantime, the  
TX19A continues to execute other instructions in parallel.  
Figure 5-9 illustrate the SYNC instruction procedure. The SYNC instruction provides an ordering  
function for the effects of load/store and subsequent instructions. The SYNC instruction ensures that  
all loads and stores initiated prior to this instruction are completed before any instruction after this  
instruction is allowed to start. To enforce in-order execution, stall cycles are inserted into the M stage  
until the previously initiated loads and stores are completed.  
Memory Read Completed  
Read Cycles  
Load  
F
F
D
F
E
D
……  
M
W
Next Instruction  
E
M
W
Memory Read Completed  
Read Cycles  
Load  
D
F
E
D
F
……  
Es  
M
E
W
M
E
SYNC  
W
M
Next Instruction  
Ds  
D
W
Memory Write Completed  
Write Cycles  
Store  
F
D
F
E
D
F
M
W
SYNC  
Es  
Ds  
E
D
M
E
W
M
Next Instruction  
W
Figure 5-9 SYNC Instruction  
5.2.5 Bit Manipulation Instruction (16 Bit ISA)  
There are two kinds of the Bit Manipulation Instructions. One is to place the result back into the  
memory. Another is to place the result back into the CPU register. Figures 5-10 and 5-11 show each  
procedure.  
F
D
E
M
W
Effective Address  
Calculation &  
Bus Cycle Initiation  
Instruction  
Fetch  
Memory  
Access  
－
Decode  
Figure 5-10 Placing the result back into the memory  
F
D
E
M
Md  
W
Effective Address  
Calculation &  
Bus Cycle Initiation  
Instruction  
Fetch  
Memory  
Access  
Register  
Write-back  
Decode  
Computation  
Figure 5-11 Placing the result back into the CPU register  
5-6  
Chapter 5 CPU Pipeline  
As for the instruction illustrated in Figure 5-10, the write buffer enters the bus operation without any  
pipeline stall same as the store instruction. See Figure 5-12 for the detailed procedure.  
Instruction  
1
Instruction  
2
Read  
Write  
Read  
Write  
Bus cycle  
Write Buffer  
F
Instruction1 bset 0x00(fp),0  
Instruction 2 bset0x04(fp),4  
Instruction 3 addur2,r4,r5  
D
F
E
D
F
M
E
W
M
E
W
M
D
W
Figure 5-12 Detailed procedure of placing the result back into the memory  
The instruction shown in Figure 5-11 has the different operations depend on the contents.  
The pipelines do not stall during the subsequent instructions if the instruction immediately after the  
bit manipulation instruction does not access the target register (t8) of the bit manipulation instruction.  
At that time, the bit manipulation instructions, BTST and BEXT, are operating in non-blocking load.  
On the other hand, the pipelines stall during the subsequent instructions if the instruction immediately  
after the bit manipulation instruction accesses the target register (t8).  
Figure 5-13 shows the detailed procedure of the case with CPU. The two ADDU instructions do not  
access the target register. Therefore, these two immediately after the BTST can be executed without  
stall. The fourth BTEGZ, however, stalls since it needs to refer to the target register.  
Bus Cycle  
Read Cycle  
btst  
addu  
addu  
btegz  
0x00(fp),0  
r2,r4,r5  
r4,r5,r6  
loop_A  
F
D
F
E
D
F
M
D
W
－
E
－
M
－
W
M
－
Referring  
t8 Register  
D
F
E
W
Ds  
Ds  
Ds  
E
M
W
Stall Cycle  
Figure 5-13 Detailed procedure of placing the result back into the CPU register  
In non-blocking load, the W stage of the Bit Manipulation Instruction may conflict with the W stage  
of the subsequent instruction. Then the subsequent instructions stall.  
Bus Cycle  
Read Cycle  
btst  
addu  
addu  
addu  
addu  
0x00(fp),0  
r2,r4,r5  
r4,r5,r6  
r4,r5,r6  
r4,r5,r6  
F
D
F
E
D
F
M
E
D
F
W
－
M
E
－
W
M
E
－
－
W
M
E
D
F
W
D
W
Ms  
M
Stall Cycle  
Figure 5-14 W Stages Conflict  
5-7  
Chapter 5 CPU Pipeline  
5.3 Jump, Branch and Branch-Likely Instructions  
Jump and branch instructions involve a delay or latency of two instruction cycles. This section  
explains how this latency is reduced to one cycle by software intervention. This section also  
describes how branch-likely instructions are processed through the pipeline.  
5.3.1 Jump and Regular Branch Instructions (32-Bit ISA)  
Figure 5-15 shows how jump and regular branch instructions advance through the CPU pipeline.  
F
D
E
M
W
Target Address Calculation &  
Branch Condition Test  
PC Update  
Instruction  
Fetch  
Register  
Write-back  
Decode  
No Operation  
Figure 5-15 Jump and Branch Instructions  
For jump and branch instructions, one of the following occurs in the Execute (E) stage:  
z For jump instructions, the ALU calculates the jump target address.  
z For branch and branch-likely instructions, the ALU determines whether the branch condition  
is true and calculates the branch target address.  
No operation is performed in the M stage. If the instruction is a jump-and-link or a branch-and-link,  
a return address is written to register r31 (ra) in the Register Write-back (W) stage.  
See Figure 5-16 for the illustrated regular branch instruction. The jump or branch target address  
becomes available during the E stage. A jump or branch occurs with a delay of two instructions cycles  
since the fetch of the target instruction occurs after the target address calculation. the instruction in  
the delay slot occurs immediately after the jump or regular branch instruction is always executed  
prior to the jump/branch taking effect. Therefore, the delay cycle caused by the jump or branch  
instruction looks as if only 1 cycle. It is the responsibility of the compiler to rearrange the code to fill  
a jump or branch delay slot with a useful instruction. If there is no useful instruction, the compiler  
must fill the delay slot with a NOP.  
Jump or Branch  
Delay Slot  
F
D
F
E
D
M
E
F
W
M
D
W
E
Jump/Branch Target  
M
W
Figure 5-16 Jump and Branch Delay Slots  
5-8  
Chapter 5 CPU Pipeline  
Note 1:  
Note 2:  
Please do not fill a jump or branch delay slot with a jump or branch instruction to avoid instable hardware  
operation.  
Please do not fill a branch delay slot with any instruction may cause an effect to program logic since the regular  
branch instruction always executes the one in the delay slot regardless of whether the branch is taken or not.  
5-9  
Chapter 5 CPU Pipeline  
5.3.2 Branch-Likely Instructions (32-Bit ISA)  
A regular branch instruction causes the TX19A to always execute the instruction in a branch delay  
slot, regardless of whether the branch is to be taken or not. Therefore, the instruction in the branch  
delay slot must logically precede the branch instruction. for the difference.  
On the other hand, a branch-likely instruction causes the TX19A to nullify the instruction in the  
delay slot at the Execute (E) stage if the branch is not taken. If a branch is taken, the instruction in  
the delay slot is executed. This approach allows the compiler to fill a branch delay slot with the  
branch target instruction (see Figure 5-17).  
Regular Branch  
Branch-Likely  
Branch  
Taken  
Branch Not  
Branch  
Taken  
Branch Not  
Taken  
Taken  
Branch Instruction  
¦
§
¦
§
¦
§
¦
×
Branch Delay Slot  
…
×
¨
×
§
…
…
…
…
¨
Branch Destination  
¨
…
False Condition  
Nullified  
Branch-Likely  
Delay Slot  
F
D
E
D
F
M
(E)  
D
W
(M)  
E
F
(W)  
M
Next Instruction  
W
When a Branch-Likely is Not Taken  
Figure 5-17 Branch-Likely Instruction  
5.3.3 Jump Instructions (16-Bit ISA)  
The JAL and JALX instructions in the 16-bit ISA are still 32-bits wide; so in 16-bit ISA mode, the  
previous TX19 needs to execute a jump instruction in two steps as shown in Figure 5-18. The TX19  
performs no operation during the first D and E stages. Instead it waits for the second half of the  
instruction code to come in order to calculate the effective address of the jump destination. This  
address calculation occurs in the E stage of the second half of the jump instruction. As a  
consequence, jump instructions in the 16-bit ISA occur with a two-instruction delay.  
In contrast, the TX19A fetches and decodes a jump instruction in one go, thereby reducing a jump  
delay from two instruction cycles to one (see Figure 5-19).  
Note: Please do not fill a jump delay slot with a jump or branch instruction to avoid instable hardware operation.  
5-10  
Chapter 5 CPU Pipeline  
Jump Instruction(1st Half)  
Jump Instruction(2nd Half)  
F
(D)  
F
(E)  
D
(M)  
E
(W)  
M
W
Delay Slot  
F
D
E
F
M
D
W
E
Jump Target  
M
W
Figure 5-18 Jump Instruction (TX19 16-Bit ISA)  
Jump Instruction  
Delay Slot  
F
D
F
E
D
M
E
W
M
W
E
Jump Target  
F
D
M
W
Figure 5-19 Jump Instruction (TX19A 16-Bit ISA)  
5.3.4 Branch Instructions (16-Bit ISA)  
Unlike the 32-bit ISA, the 16-bit ISA has no delayed branches (see Figure 5-20). The branches take  
effect before the next instruction. Thus if the branch is taken, the following instructions are not  
executed. For this reason, any instruction can be placed immediately after a branch instruction.  
32-Bit ISA  
16-Bit ISA  
Branch  
Taken  
Branch Not  
Taken  
Branch Branch Not  
Taken  
¦
Taken  
Branch Instruction  
Branch Delay Slot  
…
¦
§
¦
’
¨
Branch Instruction  
Next Instruction  
…
¦
§
×
×
×
¨
…
…
Branch Destination  
…
¨
…
Branch Destination  
…
’
True Condition  
Nullified  
Branch  
F
D
F
E
D
M
(E)  
F
W
(M)  
D
Next Instruction  
(W)  
E
Branch Destination  
M
W
When the Branch is Taken  
Figure 5-20 Branch Instruction (16-Bit ISA)  
5-11  
Chapter 5 CPU Pipeline  
5.3.5 SAVE ・RESTORE Instructions (16-Bit ISA)  
One SAVE/RESTORE instruction can save or restore the data in multiple registers.  
See figure 5-21 and 5-22 for the details.  
The next instructions stall until the contents of the stack pointer register (r29) are rewritten with the  
final data restore or save.  
Write Write Write Write  
Bus Cycle  
SAVE Instruction  
Next Instruction  
F
D
F
Es  
Ds  
Es  
Ds  
Es  
Ds  
Es  
Ds  
Es  
Ds  
E
D
M
E
W
M
W
Stall Cycle  
Figure5-21 SAVE Instructions  
Read Read Read Read  
Bus Cycle  
RESTORE Instruction  
Next Instruction  
F
D
Es  
Ds  
Es  
Ds  
Es  
Ds  
Es  
Ds  
Es  
Ds  
E
D
M
E
W
M
F
W
Stall Cycle  
Figure 5-22 RESTORE Instructions  
5-12  
Chapter 5 CPU Pipeline  
5.4 Divide Instructions  
Any integer divide instruction is transferred to the dedicated divide unit as remaining instructions  
continue through the pipeline. The divide unit keeps running even when delay cycles and exceptions  
occur. The quotient and the remainder of the divide instruction are saved in the LO and HI registers.  
The TX19A starts a divide operation in the E stage; it takes 35 cycles for the divide operation to  
complete, independent of the magnitude and sign of the operands. If the divide instruction is  
followed by an MFHI, MFLO, MADD, MADDU, MSUB or MSUBU instruction before the  
quotient and the remainder are available, the pipeline stalls until they do become available.  
F
D
E
M
W
Instruction  
Fetch  
No  
No  
Decode  
Execute  
Operation Operation  
The result is written to HI and LO.  
E34 E35  
The contents of LO is read here.  
DIV r5,r1  
MFLO r4  
F
D
F
E
M
W
……  
E1  
E2  
35 Cycles  
……  
D
Es  
Es  
E
M
W
Pipeline Stalls  
Latency = 35 Cycles  
Figure 5-23 Divide Instructions  
5-13  
Chapter 5 CPU Pipeline  
5.5 Multiply, Multiply-and-Add and Multiply-and-Subtract Instructions  
Any integer multiply, multiply-and-add and multiply-and-subtract instructions are transferred to the  
dedicated MAC unit as remaining instructions continue through the pipeline. It takes a single cycle  
for a multiply, multiply-and-add or multiply-and-subtract instruction to complete.  
Because it takes only one cycle for a multiply, multiply-and-add or multiply-and-subtract instruction  
to complete the E stage, multiple multiply, multiply-and-add and multiply-and-subtract instructions  
can be executed back-to-back without causing pipeline stalls (see Figure 5-24).  
MADD r5,r1  
MADD r6,r2  
F
D
F
E
D
M
E
W
M
W
Figure 5-24 Back-to-Back Multiply-and-Add Instructions  
The MFHI and MFLO instructions read the contents of the HI and LO registers. Multiply,  
multiply-and-add and multiply-and-subtract instructions can be followed by an MFHI or MFLO  
instruction without causing pipeline stalls (see Figure 5-25).  
MULT r5,r6  
MFLO r4  
F
D
F
E
D
M
E
W
M
W
Figure 5-25 Multiply Instruction Followed by an MFLO Instruction  
Remember that the result of the multiply, multiply-and-add and multiply-and-subtract instructions  
becomes available after completion of the M stage instead of the E stage. If the multiply,  
multiply-and-add or multiply-and-subtract instruction specifies a general-purpose register as a  
destination register (rd), subsequent instructions should not access that register until the result is  
saved in rd. Otherwise, the pipeline stalls at the D stage until it does become available.  
MADD r3,r2,r1  
ADD r5,r4,r3  
F
D
F
E
M
D
W
E
Ds  
M
W
Stall Cycle  
Figure 5-26 Structural Hazard Involving a Multiply Instruction  
5-14  
Chapter 5 CPU Pipeline  
5.6 EXTENDed Instructions (16-Bit ISA)  
The EXTEND prefix turns 16-bit instructions in the 16-bit ISA into 32 bits. The machine code of an  
EXTENDed instruction consists of an 16-bit EXTEND code and the 16-bit instruction code that is  
to be EXTENDed. While the TX19 executes any EXTENDed instruction in two steps (Figure 5-28),  
the TX19A improves instruction throughput by executing each EXTENDed instruction in one go  
(Figure 5-27).  
Execution  
EXTENDed Instruction  
F
D
E
M
W
Figure 5-27 EXTENDed Instruction (TX19A 16-Bit ISA)  
31  
27 26  
20 19  
16 15  
11 10  
8
7
5 4  
0
3
0
11110  
imm  
imm  
01000  
rs  
rt  
imm  
[3:0]  
[10:4]  
[14:11]  
EXTEND Code  
EXTENDed Instruction Code  
Execution  
EXTEND Code  
F
(D)  
F
(E)  
D
(M)  
E
(W)  
EXTENDed Instruction Code  
M
W
Figure 5-28 EXTENDed Instruction (TX19 16-Bit ISA)  
5-15  
Chapter 6 Memory Management  
Chapter 6 Memory Management  
This chapter describes the operating modes of the TX19A processor, the virtual and physical  
address spaces and how they are mapped.  
6.1 Operating Modes  
The TX19A has two modes of operation, User mode and Kernel mode. The TX19A enters Kernel  
mode whenever an exception is taken. Since a Reset exception occurs when a system is reset, the  
TX19A wakes up in Kernel mode. The processor switches to User mode when the ERET  
(Exception Return) or DERET (Debug Exception Return) instruction is executed.  
„
User Mode  
The operating mode determines the addresses, registers and instructions that are available to a  
program. The use of them is restricted under User mode. While the processor is operating in  
User mode, it is permitted to access a linear address space of 2 GB (kuseg) starting at virtual address  
0x0000_0000. The CP0 registers are accessible only when the CU0 bit in the Status register is 1.  
When the processor is operating in User mode, both of the following conditions are true: 1) the UM  
bit in the Status register is set; and 2) the ERL and EXL bits in this register are cleared.  
„
Kernel Mode  
Kernel mode has higher privileges than User mode. Kernel-mode programs are permitted to use all  
addresses, registers and instructions. Operating system routines, general exception handlers and  
debug exception handlers are executed in Kernel mode.  
When the processor is operating in Kernel mode, any of the following conditions is true: 1) the DM  
bit in the Debug register is set; 2) the UM bit in the Status register is cleared; 3) the ERL bit in the  
Status register is set; or 4) the EXL bit in the Status register is set.  
Note: TX19A only allows using Kernel mode.  
6.2 Virtual Address Segments  
Figure 6-1 shows the virtual address segments available in User and Kernel modes. While the  
processor is operating in User mode, a single, uniform virtual address space (kuseg) of 2 GB is  
available. While the processor is operating Kernel mode, four distinct virtual address segments,  
kuseg, kseg0, kseg1 and kseg2, are simultaneously available.  
Each segment is architecturally predefined as cached or uncached; however, because the TX19A  
6-1  
Chapter 6 Memory Management  
does not have a cache on-chip, cacheability has no meaning.  
User mode  
Kernel mode  
0xFFFF_FFFF  
16 MB Reserved  
Uncached  
kseg2  
Cached  
0xC000_ 0000  
0xA000_0000  
kseg1  
Uncached  
kseg0  
Cached  
0x8000_0000  
0x7FFF_FFFF  
0x7FFF_FFFF  
16 MB Reserved  
16 MB Reserved  
Uncached  
kuseg  
kuseg  
Cached  
Cached  
0x0000_ 0000  
0x0000_0000  
Figure 6-1 Virtual Address Segments  
„
Kuseg (Kernel/User Segment)  
Kuseg is a 2-GB segment designed to be used by User-mode programs while providing accessibility  
in Kernel mode. This virtual address space begins at address 0x0000_0000 and runs up to 0x7FFF_  
FFFF; so all valid User-mode virtual addresses have the most-significant bit cleared to 0. A User  
program attempt to reference a Kernel address with the most-significant bit set to 1 causes an  
Address Error exception. The upper 16 MB of kuseg should not be used. This region is reserved for  
on-chip resources which map to these virtual addresses.  
„
Kseg0, kseg1 and kseg2 (Kernel Segments)  
The virtual address space accessible only in Kernel mode consists of three distinct segments called  
kseg0, kseg1 and kseg2, which total 2 GB in size. The Kernel segments start at virtual address  
0x8000_0000 and run up to  
0xFFFF_FFFF.  
z Kseg0 is a 512-MB segment, beginning at virtual address 0x8000_0000; all references through  
this segment are cacheable.  
z Kseg1 is also a 512-MB segment, beginning at virtual address 0xA000_0000, but unlike kseg0,  
all references through this segment are uncacheable.  
z Kseg2 is a 1-GB linear address space, beginning at virtual address 0xC000_0000. The upper 16  
MB of kseg2 should not be used. This region is reserved for on-chip resources which map to  
these virtual addresses; 2-MB addresses from 0xFF20_0000 to 0xFF3F_FFFF are reserved for  
6-2  
Chapter 6 Memory Management  
debugging. While the upper 16 MB is uncacheable, the remaining region of kseg2 is cacheable.  
6.3 Address Translation  
The virtual-to-physical address translation is done through a direct segment mapping, which allows  
Kernel-mode software to be protected from User-mode accesses without requiring virtual page  
management software. Direct segment mapping of virtual-to-physical addresses is illustrated in  
Figure 6-2.  
Physical Address Space  
Virtual Address Space  
16 MB Reserved  
0xFFFF_FFFF  
0xFFFF_FFFF  
Uncached  
16 MB Reserved  
kseg2  
1 GB  
Cached  
0xC000_ 0000  
0xA000_0000  
0x8000_0000  
0xC000_0000  
kseg1  
Uncached  
16 MB Reserved  
2 GB  
kseg0  
Cached  
16 MB Reserved  
Uncached  
0x4000_0000  
0x2000_0000  
0x0000_0000  
kuseg  
Cached  
Inaccessible  
512 MB  
0x0000_0000  
Figure 6-2 Virtual to Physical Address Translation  
Figure 6-3 shows the virtual address format used by the TX19A. The three highest bits represent  
segment numbers; only these three bits are involved in virtual-to-physical address translation.  
31 30 29  
0
0
1
1
1
x
0
0
1
x
0
1
x
kuseg  
kseg0  
kseg1  
kseg2  
Figure 6-3 Virtual Address Format  
z Kuseg is mapped to a contiguous 2-GB region of the physical address space starting at  
0x4000_0000. The physical address is constructed by replacing "0x" in the two highest-order bits  
with "01."  
z Virtual addresses in both kseg0 and kseg1 are mapped to the 512-MB physical address space  
starting at address 0x0000_0000. When the three highest-order bits of the virtual address are  
"100," that virtual address resides in kseg0. When the three highest-order bits of the virtual  
6-3  
Chapter 6 Memory Management  
address are "101," that virtual address resides in kseg1. The physical address is constructed by  
replacing these three bits with "000."  
z
Virtual addresses in kseg2 are directly output as physical addresses.  
Table 6-4 Segment Mapping from Virtual to Physical Addresses  
Operating  
Mode  
Segment  
Virtual Addresses  
Physical Addresses  
Cacheability  
kseg2 Reserved  
Free  
0xFF20_0000∼0xFFFF_FFFF 0xFF00_0000∼0xFFFF_FFFF Uncacheable  
0xC000_0000∼0xFEFF_FFFF 0xC000_0000∼0xFEFF_FFFF Cacheable  
0xA000_0000∼0xBFFF_FFFF 0x0000_0000∼0x1FFF_FFFF Uncacheable  
0x8000_0000∼0x9FFF_FFFF 0x0000_0000∼0x1FFF_FFFF Cacheable  
0x7F00_0000∼0x7FFF_FFFF 0xBF00_0000∼0xBFFF_FFFF Uncacheable  
Kernel  
Kernel  
Kernel  
Kernel  
kseg1  
kseg0  
kuseg Reserved  
Kernel/  
User  
Free  
0x0000_0000∼0x7EFF_FFFF 0x4000_0000∼0xBEFF_FFFF Cacheable  
Kernel/  
User  
It is prohibited to place programs across two segments. Jumps and branches must not transfer  
program control outside the current segment.  
6-4  
Chapter 7 Internal I/O Bus Operation  
Chapter 7 Internal I/O Bus Operation  
7.1 Internal Memory Interface  
Figure 7-1 shows an example of the bus interface inside the TX19A core. To maximize  
performance, the TX19A implements a Harvard architecture, wherein there are two separate sets of  
address and data buses for code (instructions) and data (operands). Additionally, the TX19A allows  
very fast access to the on-chip memory – one word of data per clock cycle. Consequently, an  
execution rate of one instruction for each clock cycle is achieved.  
Instruction Memory ROM  
Instruction  
BIU  
ACK  
Address  
CPU Core  
D (Instruction)  
Decoder  
ACK  
A (Instruction)  
Operand  
BIU  
G-Bus  
A (Operand)  
D (Operand)  
GBIF  
Bgnt-I  
Breq  
Bgnt-O  
Data RAM  
Figure 7-1 General Internal Memory Interface  
7-1  
Chapter 7 Internal I/O Bus Operation  
7.2 Operand Read and Instruction Fetch Operations  
Figure 7-2 and Figure 7-3 show the bus cycle timing for operand reads and instruction fetches. The  
TX19A core features pipelined addressing where it allows up to two outstanding bus cycles at any  
given time. While the TX19A core waits for the data for the first bus cycle, the address for a second  
bus cycle is issued. Using pipelined addressing, the TX19A provides support for zero-wait-state  
reads even for relatively slow memories like flash.  
CLK  
ADRS  
DATA  
ADRS1  
R
BSTART  
AS  
WRITE  
CS  
ACK  
The dotted circles indicate sampling points.  
Figure 7-2 Memory Read Timing (Zero-Wait State)  
CLK  
ADRS3  
ADRS  
DATA  
BSTART  
R
AS  
WRITE  
CS  
ACK  
The dotted circles indicate sampling points.  
Figure 7-3 Memory Read Timing (1 Wait State for ADRS3)  
7-2  
Chapter 7 Internal I/O Bus Operation  
7.3 Write Operation  
Basically, memory write cycles use much the same protocol as memory read cycles. The TX19A  
core drives out a memory address on the falling edge of the system clock. At the same time, Byte  
Enable, Bus Start (BSTART*), Address Strobe (AS*), Write (WRITE*) and Chip Select (CS) etc.  
are also asserted.  
CLK  
ADRS1  
Data  
ADRS  
DATA  
BSTART  
AS  
WRITE  
CS  
ACK  
The dotted circles indicate sampling points.  
Figure 7-4 Write Timing (Zero-Wait State)  
CLK  
ADRS3  
Data  
ADRS  
DATA  
BSTART  
AS  
WRITE  
CS  
ACK  
The dotted circles indicate sampling points.  
Figure 7-5 Write Timing (1 Wait State for ADR3)  
7-3  
Chapter 8 System Control Coprocessor (CP0) Registers  
Chapter 8 System Control Coprocessor (CP0)Registers  
This chapter describes the system control coprocessor (CP0) registers used for system configuration,  
memory management and exception processing.  
When the processor is in Kernel mode, the system control coprocessor instructions can always use  
the CP0 registers. When the processor is in User mode, the CP0 registers are accessible only when  
the CU0 bit in the Status register is set.  
8.1 Overview  
Table 8-1 provides a brief description of each of the CP0 registers. Register numbers are used by  
software when issuing the Move From CP0 (MFC0) and Move To CP0 (MTC0) instructions.  
Table 8-1 CP0 Registers  
Register  
Category Register Name  
Description  
Number  
System  
Config  
16 (SEL0) Specifies various configuration options for the TX19A processor.  
Configuration  
Config1  
Config2  
Config3  
BadVAddr  
16 (SEL1)  
16 (SEL2)  
16 (SEL3)  
General  
Displays the most recent virtual address that caused a virtual-to-physical  
address translation error. Read-only.  
8 (SEL0)  
Exception  
Handling  
Count  
9 (SEL0) Acts as a timer, incrementing at a constant rate.  
Compare  
Status  
11 (SEL0) Maintains a constant value compared against the Count register value.  
Contains operating mode (User/Kernel), interrupt enable and other states  
of the processor.  
12 (SEL0)  
Cause  
EPC  
13 (SEL0) Displays the cause of the last exception.  
Contains the upper 31 bits of the address of the exception-causing  
instruction, from which point processing resumes after the exception has  
been serviced, combined with the ISA mode bit that was in effect before  
the exception occurred.  
14 (SEL0)  
Similar to the EPC register except that ErrorEPC is used on Reset and  
NMI exceptions.  
ErrorEPC  
30 (SEL0)  
PRId  
IER  
15 (SEL0) Contains the revision identifier of the TX19A processor. Read-only.  
9 (SEL7) Manipulates the interrupt enable/disable bit in the Status register.  
Contains a two-level stack (current and previous) for the shadow register  
set used.  
SSCR  
22 (SEL0)  
／9 (SEL6)  
Debug  
Exception  
Handling  
Debug  
DEPC  
23 (SEL0) Displays the cause and the current status of a debug exception.  
Contains the address of the instruction that caused a debug exception,  
from which point processing resumes after the exception has been  
serviced. Also saves the ISA mode bit that was in effect before the  
exception occurred.  
24 (SEL0)  
Debug exception save register for exclusive use by an in-circuit emulator  
(ICE).  
DESAVE  
31 (SEL0)  
The sections in this chapter describe the CP0 register organizations and how data is represented in  
these registers. The number following a register name in the headings as in "8.2.1 Config Register  
(16:SEL0)" indicates the register number.  
8-1  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.2 System Configuration Registers  
8.2.1 Config Register (16:SEL0)  
31  
M
30  
16  
0
0
7
15  
14  
13  
12  
10  
9
6
3
2
BE  
AT  
AR  
0
2
Table 8-2 Config Register Field Descriptions  
Description  
Read/  
Write  
Reset  
Fields  
Value  
Name  
Bits  
Config1 Register Select Field  
In the TX19A, this field is fixed at 1.  
Reserved  
This field is always read as 0.  
Endian is selective and fixed at mounting.  
M
31  
R
R
R
1
－
30:16  
15  
0
BE  
Note 1  
Endian:  
0: Little-endian  
1: Big-endian  
Architecture Type:  
0: MIPS32  
1: MIPS64 with access only to 32-bit compatibility segments  
2: MIPS64 with access to all address segments  
3: Reserved  
In the TX19A, this field is fixed at 0.  
Architecture Revision Level:  
0: Revision 1  
AT  
AR  
14:13  
12:10  
R
R
0
0
1-7: Reserved  
In the TX19A, this field is fixed at 0.  
－
－
9:3  
2:0  
In the TX19A, this field is fixed at 0.  
In the TX19A, this field is fixed at 2.  
R
R
0
2
Note 1: Endian is fixed as 0 or 1 at mounting.  
8-2  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.2.2  
Config1 Register (16:SEL1)  
31  
M
30  
16  
0
15  
3
2
1
0
0
CA  
EP  
FP  
Table 8-3 Config1 Register Field Descriptions (1 of 3)  
Description  
Read/  
Write  
Reset  
Fields  
Value  
Name  
Bits  
Config2 Register Select Field:  
M
31  
R
1
In the TX19A, this bit is fixed at 1.  
－
30:3  
2
In the TX19A, this bit is fixed at 0.  
16-bit code Implemented.  
R
R
0
1
CA  
0: MIPS16ASE not implemented  
1: MIPS16ASE implemented  
In the TX19A, this bit is fixed at 1.  
EJTAG Implemented:  
0: No EJTAG implemented  
1: EJTAG implemented  
In the TX19A, this bit is fixed at 1.  
FPU Implemented:  
EP  
FP  
1
0
R
R
1
0
0: No FPU implemented  
1: FPU implemented  
In the TX19A, this bit is fixed at 0.  
Note: The Config1 register is read-only.  
8-3  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.2.3  
Config2 Register (16:SEL2)  
31  
30  
16  
0
M
0
15  
0
Table 8-4 Config2 Register Field Descriptions  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
Config3 Register Select Field:  
M
31  
R
1
In the TX19A, this bit is fixed at 0.  
－
30:0  
In the TX19A, this bit is fixed at 0.  
R
0
Note: The Config2 register is read-only.  
8-4  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.2.4 Config3 Register (16:SEL3)  
31  
M
30  
16  
0
15  
0
0
Table 8-5 Config3 Register Field Descriptions  
Field  
Read/  
Write  
Reset  
Value  
Description  
Name  
Bits  
Config4 Register Select Field:  
M
31  
R
0
In the TX19A, this bit is fixed at 0.  
－
30:0  
In the TX19A, this bit is fixed at 0.  
R
0
Note: The Config3 register is read-only.  
8-5  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.3 General Exception Handling Registers  
This section describes the CP0 registers that are used in general exception processing. The  
remaining CP0 registers are used for program debug and described in the next section.  
8.3.1 BadVAddr Register (8)  
The BadVAddr (Bad Virtual Address) register is a read-only register. It captures the most recent  
virtual address that caused a virtual-to-physical address translation error. The Address Error (AdEL  
or AdE) exception is taken.  
31  
0
BadVAddr  
Table 8-6 BadVAddr Register Field Descriptions  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
BadVAddr  
31:0  
Bad Virtual Address  
R
Undefined  
Note: BadVAddr register is read-only.  
8-6  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.3.2  
Count Register (9:SEL0)  
The Count register is a read/write register. It acts as a time, incrementing at 1/2 the rate of  
CPUCLK.  
If the processor input called GTINTDIS is held at logic 0, the Count register is incremented. If  
GTINTDIS is held at logic 1, the Count register remains inactive.  
The Count register can be written for diagnostic purposes or during system initialization.  
31  
0
Count  
Table 8-7 Count Register Field Descriptions  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
Count  
31:0  
Interval counter  
R/W  
Undefined  
8-7  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.3.3  
Compare Register (11)  
When the value of the Count register reaches the value programmed into the Compare register,  
interrupt bit IP[7] in the Cause register is set. This causes an Interrupt exception if the interrupt is  
enabled.  
Writing to the Compare register clears the timer interrupt.  
For diagnostic purposes, the Compare register is a read/write register. In normal use, the Compare  
register is write-only.  
31  
16  
Compare  
Table 8-8 Compare Regiser Field Descriptions  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
Compare  
31:0  
Interval count compare value  
R/W  
Undefined  
8-8  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.3.4 Status Register (12)  
31  
28  
27  
26  
25  
24  
23  
22  
21  
0
20  
0
19  
18  
0
17  
1
16  
CU  
RP  
FR  
RE  
MX  
PX  
BEV  
NMI  
Impl  
15  
8
7
6
5
4
3
2
0
IM7-IM0  
KX  
SX  
UX  
UM  
R0  
ERL EXL  
IE  
Table 8-9 Status Register Field Descriptions (1 of 2)  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
Controls the usability of coprocessors 3 to 0. In Kernel mode, CP0  
is always usable, regardless of the value of the CU0 bit. The CU3,  
CU2 and CU1 bits must always be written as 0s.  
0: Coprocessor not usable  
CU  
(CU3,  
…
31:28  
R/W  
Undefined  
CU0)  
1: Coprocessor usable  
Reduced Power Mode:  
RP  
27  
R/W  
0
0: Halt mode  
1: Doze Mode  
Selects which one of the reduced power modes is to be entered on  
execution of an WAIT instruction. The TX19A freezes the instruction  
pipeline in both Halt and Doze modes; however, the Halt mode  
provides more power savings than the Doze mode.  
FR  
RE  
26  
25  
24  
23  
22  
Ignored on write and returned as 0 on read  
Ignored on write and returned as 0 on read  
Ignored on write and returned as 0 on read  
Ignored on write and returned as 0 on read  
R
R
0
0
0
0
1
MX  
PX  
R
R
Bootstrap Exception Vector  
BEV  
R/W  
Set when the processor is reset. When BEV=1, all exception  
vectors reside in uncacheable kseg1 space. Typically, this is used  
to allow diagnostic tests to occur before the functionality of the  
cache is validated. When BEV=0, the Reset, NMI and Debug  
exception vectors reside in uncacheable kseg1 space and all the  
other exception vectors reside in cacheable kseg0 space.  
TS  
SR  
21  
20  
19  
Ignored on write and returned as 0 on read.  
R
0
0
Set when a non-maskable interrupt (NMI) signal is asserted low.  
Writing a 0 to this bit clears it. Writing a 1 to this bit has no effect.  
Note that the functionality of this bit differs between the TX19.  
NMI  
R/W  
－
Impl  
IM  
18  
Ignored on write and returned as 0 on read.  
Ignored on write and returned as 0 on read.  
Interrupt Mask:  
R
R
0
0
17:16  
15:8  
R/W  
0x00  
Enables and disables each of the external, timer and software  
interrupts. An interrupt is only accepted when the Interrupt Enable  
(IE) bit is set and the corresponding IM bit in the Status register and  
the IP bit in the Cause register are both set.  
0: Interrupt request disabled  
(IM7,  
…
IM0)  
1: Interrupt request enabled  
8-9  
Chapter 8 System Control Coprocessor (CP0) Registers  
Table 8-9 Status Register Field Descriptions (2 of 2)  
Field  
Read/  
Write  
Reset  
Value  
Description  
Name  
Bits  
KX  
SX  
UX  
UM  
7
6
5
4
Ignored on write and returned as 0 on read.  
Ignored on write and returned as 0 on read.  
Ignored on write and returned as 0 on read.  
Operating Mode:  
0: Kernel mode  
1: User mode  
R
R
0
0
0
0
R
R/W  
Only Kernel mode is available with TX19A.  
Ignored on write and returned as 0 on read.  
Error Level:  
－
3
2
R
0
1
ERL  
R/W  
Set when a Reset or NMI exception is taken.  
When this bit is set:  
• The processor is running is Kernel mode.  
• Interrupts are disabled.  
• The ERET instruction will use the return address held in the  
ErrorEPC register.  
Exception Level:  
EXL  
1
R/W  
0
Set when an exception other than Reset and NMI exceptions is  
taken.  
When this bit is set:  
• The processor is running in Kernel mode.  
• Interrupts are disabled.  
• The EPC register and the BD bit in the Cause register will not be  
updated if another exception is taken.  
Interrupt Enable:  
IE  
0
R/W  
0
0: Interrupts are disabled.  
1: Interrupts are enabled.  
The IE bit is not automatically set or cleared by the interrupt  
response sequence or the ERET instruction. (This bit is cleared  
upon reset.)  
8-10  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.3.5 Cause Register (13)  
The Cause register indicates the cause of the last exception. All the bits in this register is read-only,  
except the IP[1:0] and IV bits.  
31  
30  
0
29  
28  
27  
24  
23  
IV  
22  
21  
16  
BD  
CE  
0000  
WP  
000000  
15  
8
7
0
6
2
1
0
0
0
IP7:IP0  
Exc Code  
Table 8-10 Cause Register Field Descriptions  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
Set when an exception occurred in a jump or branch delay slot. The  
processor updates the BD bit only if the EXL bit is 0 when an  
interrupt or exception occurred.  
BD  
31  
R
Undefined  
－
30  
Ignored on write and returned as 0 on read.  
Coprocessor Error:  
R
R
0
CE[1:0]  
29:28  
Undefined  
Indicates the coprocessor unit number referenced when a  
Coprocessor Unusable exception was taken. The value in this field  
is undefined for any other exception.  
－
27:24  
23  
Ignored on write and returned as 0 on read.  
Interrupt Vector:  
R
0
IV  
R/W  
Undefined  
If this bit is set, an Interrupt exception uses a special interrupt  
vector different from the general exception vector.  
BEV (Status) IV  
Interrupt Vector  
0x8000_0180  
0x8000_0200  
0xBFC0_0380  
0xBFC0_0400  
0
0
1
1
0
1
0
1
WP  
－
22  
Ignored on write and returned as 0 on read.  
Ignored on write and returned as 0 on read.  
Interrupt Request (Hardware):  
R
R
R
0
0
21:16  
15:10  
IP[7:2]  
Undefined  
IP[7]: Hardware interrupt 5 or timer interrupt  
IP[6]: Hardware interrupt 4  
IP[5]: Hardware interrupt 3  
IP[4]: Hardware interrupt 2  
IP[3]: Hardware interrupt 1  
IP[2]: Hardware interrupt 0  
A timer interrupt occurs when the value of the Count register ($9)  
equals the value of the Compare register ($11).  
Interrupt Request (Software)  
IP[1:0]  
9:8  
R/W  
Undefined  
IP[1]: Request software interrupt 1  
IP[0]: Request software interrupt 0  
－
ExcCode  
－
7
Ignored on write and returned as 0 on read.  
Exception code (See Table 8-11.)  
R
R
R
0
Undefined  
0
6:2  
1:0  
Ignored on write and returned as 0 on read.  
8-11  
Chapter 8 System Control Coprocessor (CP0) Registers  
Table 8-11 Exception Code (ExcCode) Field  
Exception Code Value  
Mnemonic  
Description  
Decimal  
Hexadecimal  
0
4
0x00  
0x04  
0x05  
0x06  
0x07  
0x08  
0x09  
0x0a  
0x0b  
0x0c  
0x0d  
Int  
AdEL  
AdES  
IBE  
DBE  
Sys  
Bp  
Interrupt exception (software and hardware)  
Address Error exception (instruction fetch or load)  
Address Error exception (Store)  
Bus Error exception (instruction fetch)  
Bus Error exception (data load)  
System Call exception  
5
6
7
8
9
Breakpoint exception  
10  
11  
12  
13  
Other  
RI  
Reserved Instruction exception  
Coprocessor Unusable exception  
Integer Overflow exception  
Trap exception  
CpU  
Ov  
Tr  
(Reserved)  
8-12  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.3.6 EPC Register (14)  
The EPC register contains the address at which processing resumes after an exception has been  
serviced.  
For synchronous exceptions, the EPC register contains either one of the following:  
• the virtual address of the instruction that was the direct cause of the exception  
• the virtual address of the immediately preceding branch or jump instruction (When the  
exception-causing instruction is in a branch delay slot, the BD bit in the Cause register is set.)  
The processor does not write to the EPC register when the EXL bit in the Status register is set to  
one.  
31  
0
EPC  
Table 8-12 EPC Register Field Descriptions  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
EPC  
31:0  
Exception Program Counter  
R/W  
Undefined  
8-13  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.3.7  
PRId Register (15)  
The PRId register is a read-only register that indicates the implementation and revision identifier of  
the CPU and the CP0.  
31  
24  
23  
16  
15  
8
7
0
Company Options  
Company ID  
Processor ID  
Revision  
Table 8-13 PRId Register Field Descriptions  
Description  
Field  
Bits  
Read/  
Write  
Reset  
Value  
Name  
Company-dependent options  
Returned as 0 on read.  
Company  
Options  
Company  
ID  
31:24  
23:16  
15:8  
7:0  
R
R
R
R
0x00  
0x07  
0x40  
0x00  
Company ID  
In the TX19A, this field is fixed at 0x07.  
Processor ID  
In the TX19A, this field is fixed at 0x40.  
Processor  
ID  
Revision  
Revision  
In the TX19A, this field is fixed at 0x00.  
Note: PRId register is read-only.  
8-14  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.3.8 ErrorEPC Register (30)  
The ErrorEPC register is a read/write register that captures the value of the Program Counter (PC)  
on Reset and NMI exceptions.  
The ErrorEPC register contains one of the following addresses:  
• the virtual address of the instruction that was the direct cause of the exception  
• the virtual address of the immediately preceding branch or jump instruction when the error-causing  
instruction is in a branch delay slot  
31  
0
ErrorEPC  
Table 8-14 ErrorEPC Register Field Descriptions  
Field  
Read/  
Write  
Reset  
Value  
Description  
Name  
Bits  
ErrorEPC  
31:0  
Error Exception Program Counter  
R/W  
Undefined  
8-15  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.3.9 Shadow Register Set Control Register: SSCR (22 or 9：SEL6)  
31  
30  
16  
0
SSD  
0
7
15  
12  
11  
8
4
3
0
PSS  
0
CSS  
Table 8-15 SSCR Register Field Descriptions  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
SSD  
31  
Shadow Register Set Disable Signal  
0: MIPS32 Version.1.0 with Shadow Register Set  
1: MIPS32 Version.1.0  
R/W  
1
－
30:12  
11:8  
Reserved bits  
R
0
PSS  
Previous Shadow Register Set  
x000: Main GPRs  
R/W  
Undefined  
x001: Shadow Register 1  
x010: Shadow Register 2  
x011: Shadow Register 3  
x100: Shadow Register 4  
x101: Shadow Register 5  
x110: Shadow Register 6  
x111: Shadow Register 7  
Reserved bits  
－
7:4  
3:0  
R
0
CSS  
Current Shadow Register Set  
x000: Main GPRs  
R/W  
0000  
x001: Shadow Register 1  
x010: Shadow Register 2  
x011: Shadow Register 3  
x100: Shadow Register 4  
x101: Shadow Register 5  
x110: Shadow Register 6  
x111: Shadow Register 7  
Note 1: The SSCR register is a read/write register.  
Note 2: When the processor accepts an interrupt request from the interrupt controller, the value of the CSS field is  
copied to the PSS field, and the CSS field is updated with the value of the new interrupt request level.  
Note 3: On an ERET, the value of the PSS field is restored to the CSS field.  
Note 4: The instruction that modifies the contents of the SSCR register must be followed by two NOPs to avoid  
pipeline hazards.  
Example: MTC0  
NOP  
r18, SSCR  
NOP  
ADD  
r19, r12, r13  
Note 5: When the SSD bit is set, the Shadow Register Set is not updated by any interruptions.  
Note 6: When the SSD bit is set, only shadow set 0 is accessible, and the value of the CSS field is ignored.  
8-16  
Chapter 8 System Control Coprocessor (CP0) Registers  
PSS  
xxx  
CSS  
2
Before Interrupt  
After Interrupt  
Interrupt Level = 5  
5
2
2
After Return from  
Interrupt  
2
(ERET Instruction)  
Figure 8-16 Saving and Restoring the Shadow Register Set Number  
8-17  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.3.10 IER Register (9:SEL7)  
The IER register is used to set or clear the IE bit in the Status register. Writing a zero to the IER  
register causes the IE bit in the Status register to be cleared. Writing a non-zero value to the IER  
register causes the IE bit to be set. Use the instruction “MTC0 r0, IER” to disable interrupts. Use a  
register that contains a non-zero value as the target register like “MTC0 $sp, IER” to enable  
interrupts.  
31  
0
Interrupt Enable Register  
Table 8-17 IER Register Field Descriptions  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
Interrupt Enable Register  
IER  
31:0  
R/W  
Undefined  
This register is used to set or clear the IE bit in the Status register.  
Writing a 0 to this register causes the IE bit to be cleared. Writing a  
non-zero value to this register causes the IE bit to be set.  
8-18  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.4 Debug Exception Handling Registers  
The TX19A allows program instruction execution to arbitrarily stop to handle debugging events.  
This section provides explanations about the extra hardware-based features the TX19A incorporate to  
enhance program debug.  
8.4.1  
Debug Register (23)  
As a debugging aid, the Debug register reflects conditions that were in effect at the time a debug  
exception occurred and allows you to initiate debug processing. Code execution breakpoints can be  
generated by embedding Software Debug Breakpoint (SDBBP) instructions in the code at the time  
SDBBP instruction is executed.  
Additionally, the single-step feature may be enabled by setting the SSt bit in the Debug register;  
when single-step mode is enabled, a Single-Step exception occurs each time the processor executes  
an instruction.  
31  
30  
29  
28  
27  
26  
25  
24  
23  
M
22  
21  
20  
19  
18  
17  
EJTAG  
ver[2:0]  
16  
No  
DCR  
Count IBus  
Cache DBus  
DDBS DDBL  
Impr Impr  
DBD  
DM  
LSNM Doze Halt  
IEXI  
DM  
9
EP CheckP` EP  
EP  
5
15  
14  
10  
8
7
6
4
3
2
1
0
EJTAG  
ver[2:0]  
DexcCode  
NoSSt SSt  
0
DINT DIB DDBS DDBL DBp DSS  
Table 8-18 Debug Register Field Descriptions (1 of 3)  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
Debug Branch Delay:  
Set when a debug exception occurred in a jump or branch delay  
slot.  
Debug Mode:  
Indicates whether a debug exception occurred. This bit is set when  
a debug exception is taken and cleared on a DERET.  
dseg memory segment:  
0: Dseg is present  
1: No dseg present  
DBD  
31  
30  
29  
28  
R
R
R
R
Undefined  
DM  
0
0
0
NoDCR  
LSNM  
Controls access of load/store between dseg and remaining memory when  
dseg is present:  
0: Load/store in dseg address range go to dseg  
1: Load/store in dseg address range go to system memory  
8-19  
Chapter 8 System Control Coprocessor (CP0) Registers  
Table 8-18 Debug Register Field Descriptions (2 of 3)  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
Low-Power Mode Flag (Doze):  
Doze  
27  
Ｒ
Undefined  
Set if the processor was in low-power Doze mode when a debug  
exception occurred.  
Low-Power Mode Flag (Halt):  
Set if the processor was in low-power Halt mode when a debug  
exception occurred.  
Count Register in Debug Mode:  
0: Stops the Count register in Debug mode.  
1: Runs the Count register in Debug mode.  
Instruction Bus Error Pending:  
Halt  
26  
25  
24  
Ｒ
Undefined  
CountDM  
IBusEP  
R/W  
R/W1  
0
0
Set when a bus error (from an instruction fetch) is detected or a 1 is  
written to the bit by software in debug mode. Cleared when a Bus Error  
exception is taken by the processor. If the IEXI bit is cleared when the  
IBusEP bit is set, the pending Bus Error exception is taken by the  
processor, and the IBusEP bit is cleared.  
Writing a 0 to this bit has no effect.  
McheckP  
CacheEP  
DBusEP  
23  
22  
21  
Not implemented in the TX19A. Returned as 0 on read.  
Not implemented in the TX19A. Returned as 0 on read.  
Data Bus Error Pending:  
R
R
0
0
0
R/W1  
Set when a bus error (from a data access) is detected or a 1 is  
written to the bit by software in debug mode. Cleared when a Bus Error  
Exception is taken by the processor. If the IEXI bit is cleared when the  
DBusEP bit is set, the pending Bus Error exception is taken by the  
processor, and the DBusEP bit is cleared.  
Writing a 0 to this bit has no effect.  
An Imprecise Error eXception Inhibit (IEXI)  
IEXI  
20  
R/W  
0
Set when the processor takes a debug exception or an exception  
occurs in Debug mode. Cleared by the DERET instruction. Also  
modifiable by software.  
When the IEXI bit is set, Bus Error exceptions (from instruction  
fetches and data accesses) are inhibited or deferred until the bit is  
cleared.  
Debug Data Break Store Imprecise Exception:  
Set when a data address break occurred during a write bus cycle.  
Cleared when a general exception occurred in Debug mode.  
Debug Data Break Load Imprecise Exception:  
Set when a data address break occurred during a read bus cycle.  
Cleared when a general exception occurred in Debug mode.  
DDBS  
Impr  
19  
18  
R
R
R
Undefined  
Undefined  
010  
DDBL  
Impr  
EJATGver  
17:15  
EJTAG version:  
0: Version 1 and 2.0  
1: Version 2.5  
2: Version 2.6  
3-7: Reserved  
General Exception in Debug Mode:  
DExcCode  
NoSSt  
14:10  
R
R
Undefined  
Indicates the Exception Code (ExcCode) in the same manner as for  
the Cause register if a general exception occurs while a debug  
exception handler is being executed in Debug mode (i.e., DM=1).  
See Table 8-11 for a list of exception codes.  
Single-Step Feature Available:  
0: Single-step feature available  
1: No single-step feature available  
In the TX19A, this bit is fixed at 0.  
9
0
8-20  
Chapter 8 System Control Coprocessor (CP0) Registers  
Table 8-18 Debug Register Field Descriptions (3 of 3)  
Field  
Read/  
Write  
Reset  
Value  
Description  
Name  
Bits  
Single-Step:  
SSt  
8
R/W  
0
When set, the single-step feature is enabled. When cleared, the  
single-step feature is disabled. The single-step feature is disabled  
while a debug exception handler is being executed (i.e., DM=1).  
0
7:6  
5
Ignored on write and returned as 0 on read.  
Debug Interrupt Exception:  
0
0
DINT  
R
Undefined  
Set when a Debug Interrupt exception occurred. Cleared on a  
general exception in Debug mode.  
Debug Instruction Break:  
Set when an instruction address break occurred. Cleared on a  
general exception in Debug mode.  
DIB  
4
3
R
R
Undefined  
Undefined  
DDBS  
Debug Data Break Store Exception:  
Debug Data Break Store Exception:  
Set when a data address break occurred on a store. Cleared on a  
general exception in Debug mode. The Debug Data Break Store  
exception is not implemented in the TX19A.  
Debug Data Break Load Exception:  
DDBL  
2
R
Undefined  
Set when a data address break occurred on a load. The breakpoint  
match is evaluated on a load address, but not on the data value.  
Cleared on a general exception in Debug mode. The Debug Data  
Break Load exception is not implemented in the TX19A.  
Debug Breakpoint Exception:  
Set when an SDBBP instruction caused a Debug Breakpoint  
exception. Cleared on a general exception in Debug mode.  
Debug Single-Step Exception:  
DBp  
DSS  
1
0
R
R
Undefined  
Undefined  
Set when a Single-Step exception occurred. Cleared on a general  
exception in Debug mode.  
8-21  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.4.2  
DEPC Register (24)  
The DEPC register contains the address at which processing resumes after a debug exception has  
been serviced.  
The DEPC register contains either one of the following:  
• the virtual address of the instruction that was the direct cause of the debug exception.  
• the virtual address of the immediately preceding branch or jump instruction when the exception causing  
instruction is in a branch delay slot  
The DERET instruction causes a jump to DEPC address. The DEPC register is a read/write register.  
31  
0
DEPC  
Table 8-19 DEPC Register Field Descriptions  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
DEPC  
31:0  
Debug Exception Program Counter  
R/W  
Undefined  
8-22  
Chapter 8 System Control Coprocessor (CP0) Registers  
8.4.3 DESAVE Register (31)  
The debug exception handler uses the DESAVE register to save one of the general-purpose registers.  
The general-purpose register saved in DESAVE is used to save the rest of the context to a predetermined  
memory area, for example, in a processor probe. The DESAVE register allows the safe  
debugging of exception handlers and other types of code where the existence of a valid stack for  
context saving can not be assumed.  
The DESAVE register is for exclusive use by an in-circuit emulator (ICE).  
31  
0
DESAVE  
Table 8-20 DESAVE Register Field Descriptions  
Description  
Field  
Read/  
Write  
Reset  
Value  
Name  
Bits  
DESAVE  
31:0  
Debug Exception Save Register  
R/W  
Undefined  
8-23  
Chapter 8 System Control Coprocessor (CP0) Registers  
8-24  
Chapter 9 Exception Handling  
Chapter 9 Exception Handling  
This chapter discusses system resources related to exception and exception processing sequence.  
The main sections in this chapter are:  
‹
‹
‹
General Exceptions  
Interrupts  
Debug Exceptions  
9.1 General Exceptions  
Exceptions in the TX19A are broadly categorized into general exceptions or debug exceptions. This  
section explains details concerning sources of specific exceptions, how each arises and  
how each is processed.  
9.1.1 How General Exception Processing Works  
Exceptions are any conditions that alter the normal sequence of instructions as a result of external  
interrupt signals, errors or unusual conditions arising in the execution of instructions. When  
exceptions occur, the processor saves information about the state of the processor, enters Kernel  
mode and transfers control to a predefined address. This predefined location is called exception  
vector, which directly indicates the start of the actual exception handler routine.  
All exceptions other than Reset and NMI exceptions are processed in the sequence shown in Figure  
9-1. Reset and NMI exceptions are processed in the sequence shown in Figure 9-2.  
9-1  
Chapter 9 Exception Handling  
Exception detection  
1
EXL (Status [1])?  
0
YES  
NO  
Instr. In branch  
delay slot？  
･BD (Cause[31]) ←1  
･BD (Cause[31]) ←0  
･EPC ←PC  
･EPC ←PC of jump or  
branch instr.  
YES  
NO  
Maskable  
Interrupt？  
*
If BEV=0 & IV=0  
If BEV=0  
PC ←0x8000_0180  
PC ←0x8000_0180  
If BEV=0 & IV=1  
If BEV=1  
PC ←0x8000_0200  
PC ←0xBFC0_0380  
If BEV=1 & IV=0  
PC ←0xBFC0_0380  
*
BEV = Status [22]  
IV = Cause [23]  
If BEV=1 & IV=1  
PC ←0xBFC0_0400  
CE (Cause[29:28])  
ExcCode (Cause[6:2])  
EXL (Status[1])  
←
←
←
Fault Cop #  
Exception code  
1
Branch to the exception handler  
Figure 9-1 General Exception Processing  
The CE field consists of the Cause register bit 28 and 29 is only valid when a Coprocessor Unusable  
exception occurred.  
9-2  
Chapter 9 Exception Handling  
◆Reset Exception  
◆NMI Exception  
Status:  
Status:  
BEV ←1  
NMI ←0  
ERL ←1  
RP ←0  
NMI ←1  
ERL ←1  
YES  
NO  
Instr. in branch  
delay slot？  
･ErrorEPC ←Pc of jump  
or branch instr.  
･ErrorEPC ←PC  
PC ←0xBFC0_0000  
Figure 9-2 Reset and NMI Exception Processing  
9.1.2 General Exception Priorities  
While more than one exception can occur at a time, the TX19A reports only one exception with the  
priority order shown in Table 9-3.  
Table 9-3 General Exception Types  
Priority  
Exception  
Mnemonic  
Type  
Highest  
Reset  
Reset  
DSS  
Non_debug  
Debug  
Single-Step exception  
Nonmaskable Interrupt (NMI) exception  
Maskable Interrupt exception  
Nmi  
Non_debug  
Int  
Address Error exception (Instruction fetch)  
Bus Error exception (Instruction fetch)  
Debug Breakpoint exception (SDBBP)  
Coprocessor Unusable exception (see Note)  
AdEL  
IBE  
Non_debug  
Debug  
DBp  
CpU  
Reserved Instruction exception, Integer Overflow  
exception, Trap exception, System Call exception,  
Breakpoint exception  
RI、Ov、  
Tr、Sys、  
Bp  
Non_debug  
Non_debug  
Address Error exception (Load/store)  
Bus Error exception (Data access)  
AdEL/AdES  
DBE  
Lowest  
Note: When FPU instructions with the COP1 opcode are executed with the CU1 bit cleared, both CpU and RI  
exception conditions arise. The CpU exception occurs, however, based on the priority order shown above.  
9-3  
Chapter 9 Exception Handling  
9.1.3 Exception Vector Addresses (Exception Vectors)  
An exception vector is the entry address of a routine that handles an exception. The Reset and  
Nonmaskable Interrupt exceptions are always vectored to virtual address 0xBFC0_0000. The Debug  
exception is always vectored to virtual address 0xBFC0_0480. Values of the other vectors depend  
on the BEV bit (bit 23) in the Status register and the IV bit (bit 23) in the Cause register. Table 9-4  
shows the exception vector addresses.  
Table 9-4 Exception Vector Addresses  
BEV=0  
BEV=1  
Exception Type  
Virtual  
Physical  
Virtual  
Physical  
Reset、NMI  
0xBFC0_0000  
0xBFC0_0480  
0x8000_0180  
0x8000_0200  
0x8000_0180  
0x1FC0_0000  
0x1FC0_0480  
0x0000_0180  
0x0000_0200  
0x0000_0180  
0xBFC0_0000  
0xBFC0_0480  
0xBFC0_0380  
0xBFC0_0400  
0xBFC0_0380  
0x1FC0_0000  
0x1FC0_0480  
0x1FC0_0380  
0x1FC0_0400  
0x1FC0_0380  
Debug Breakpoint  
Interrupt (IV=0)  
Interrupt (IV=1)  
All others  
9.1.4 Reset Exception  
„
Cause  
This exception occurs when the processor’s reset signal is asserted and then negated.  
„
Handling  
1. All the CP0 registers are initialized.  
2. The ERL bit in the Status register is set.  
3. The ErrorEPC register is loaded with the restart PC.  
4. The processor jumps to the exception handler located at address 0xBFC0_0000.  
Note: If a Reset exception occurs during processor bus cycles, the processor immediately discontinues  
the ongoing bus cycle and takes a Reset exception.  
9-4  
Chapter 9 Exception Handling  
9.1.5 Nonmaskable Interrupt (NMI) Exception  
„
Cause  
This exception occurs when the processor’s non-maskable interrupt signal, GNMI, is asserted. This  
exception is not maskable; it occurs regardless of the settings of the EXL, ERL and IE bits in the  
Status register.  
„
Handling  
1. The values of the ExcCode and CE fields in the Cause register become undefined.  
2. The ERL and NMI bits in the Status register are set.  
3. The ErrorEPC register is loaded with the program counter (PC) on the interrupt. If the  
interrupt-causing instruction is in a jump or branch delay slot, the ErrorEPC register points at  
the preceding jump or branch instruction, and the BD bit in the Cause register is set. The  
least-significant bit in the ErrorEPC register saves the ISA mode that was in effect prior to the  
exception.  
4. If the processor is in a reduced power mode (either HALT or DOZE mode), the reduced power  
mode is exited and start to handle the NMI exception.  
5. If the exception occurs while the processor is in 16-bit ISA mode, the processor switches to  
32-bit ISA mode.  
6. The processor jumps to the exception handler located at address 0xBFC0_0000.  
Note: When an NMI interrupt request is generated during a bus cycle, the processor recognizes the  
request at the end of the current bus cycle, as is the case with all the other exceptions but the  
Reset exception.  
9-5  
Chapter 9 Exception Handling  
9.1.6 Address Error Exception  
„
Cause  
This exception occurs when an attempt is made to:  
z fetch a 32-bit ISA instruction that is not aligned on a word boundary (AdEL)  
z fetch a 16-bit ISA instruction that is not aligned on a halfword boundary (AdEL)  
z load or store a word that is not aligned on a word boundary (AdEL/AdES)  
z load or store a halfword that is not aligned on a halfword boundary (AdEL/AdES)  
z reference a Kernel-mode address space (kseg0, kseg1 or kseg2) in User mode (AdEL/AdES)  
„
Handling  
1. The AdEL code (4) or the AdES code (5) is set into the ExcCode field in the Cause register,  
depending on whether the exception occurred during an instruction fetch or a load operation  
(AdEL), or a store operation (AdES).  
2. The BadVAddr register stores the virtual address that is not properly aligned or the virtual address  
that improperly references a Kernel segment.  
3. The following operation only occurs when the EXL bit in the Status register is cleared. The EXL  
bit is set, and the EPC register is loaded with the address of the instruction that caused the  
exception unless this instruction is not in a jump or branch delay slot. If it is in a jump or branch  
delay slot, the EPC register points at the preceding jump or branch instruction and the BD bit in  
the Cause register is set. The least-significant bit of the EPC register saves the ISA mode that was  
in effect prior to the exception.  
4. If the exception occurs while the processor is in 16-bit ISA mode, the processor switches to 32-bit  
ISA mode.  
5. The processor jumps to an appropriate exception vector address (see Table 9-5).  
9-6  
Chapter 9 Exception Handling  
9.1.7 Bus Error Exception  
„
Cause  
This exception occurs when the bus error signal, GBUSERR, is asserted during memory read bus  
cycles. A Bus Error exception can occur during the fetching of any instruction or during a memory  
read bus cycle by a load or bit manipulation instruction.  
The handling of a write bus error differs between the TX19 and the TX19A. The assertion of the  
GBUSERR signal causes the TX19 to take a Bus Error exception whether or not it is during a read  
or write operation. In the TX19A, GBUSERR is not signaled to the processor during a write  
operation because of the on-chip write buffer; in case of a write bus error, the system hardware must  
terminate the write operation through use of an NMI interrupt.  
„
Handling  
1. The IBE code (6) or the DBE code (7) is set into the ExcCode field in the Cause register,  
depending on whether the exception occurred during an instruction fetch (IBE), or a data load or  
store operation (DBE).  
2. The following operation only occurs when the EXL bit in the Status register is cleared. The EXL  
bit is set, and the EPC register is loaded with the address of the instruction that caused the  
exception unless this instruction is not in a jump or branch delay slot. If it is in a jump or branch  
delay slot, the EPC register points at the preceding jump or branch instruction and the BD bit in  
the Cause register is set. The least-significant bit of the EPC register saves the ISA mode that was  
in effect prior to the exception.  
3. The EPC register saves the program counter (PC) on the exception for the following cases:  
z a load instruction is followed by a SYNC instruction  
z the instruction immediately following a load has dependency on the loaded data  
In such cases, the pipeline stalls until the load is complete; so the EPC register displays the  
address of the instruction immediately following the load instruction.  
4. If the exception occurs while the processor is in 16-bit ISA mode, the processor switches to  
32-bit ISA mode.  
5. The processor jumps to an appropriate exception vector address (see Table 9-4).  
9-7  
Chapter 9 Exception Handling  
9.1.8 Integer Overflow Exception  
„
Cause  
This exception occurs when the ADD, ADDI or SUB instruction in the 32-bit ISA or the DIVE  
instruction in the 16-bit ISA results in two’s-complement overflow or when the DIVE or DIVEU  
instruction in the 16-bit ISA attempts to divide by zero.  
„
Handling  
1. The Ov code (12) is set into the ExcCode field in the Cause register.  
2. The following operation only occurs when the EXL bit in the Status register is cleared. The  
EXL bit is set, and the EPC register is loaded with the address of the instruction that caused  
the exception unless this instruction is not in a jump or branch delay slot. If it is in a jump or  
branch delay slot, the EPC register points at the preceding jump or branch instruction and  
the BD bit in the Cause register is set. The least-significant bit of the EPC register saves the  
ISA mode that was in effect prior to the exception.  
3. If the exception occurs while the processor is in 16-bit ISA mode, the processor switches to  
32-bit ISA mode.  
4. The processor jumps to an appropriate exception vector address (see Table 9-4).  
9-8  
Chapter 9 Exception Handling  
9.1.9 Trap Exception  
„
Cause  
This exception occurs when the TGE, TGEU, TLT, TLTU, TEQ, TNE, TGEI, TGEIU, TLTI,  
TLTIU, TEQI or TNEI instruction results in a true condition.  
„
Handling  
The Tr code (13) is set into the ExcCode field in the Cause register.  
1. The following operation only occurs when the EXL bit in the Status register is cleared.  
2. The EXL bit is set, and the EPC register is loaded with the address of the instruction that caused  
the exception unless this instruction is not in a jump or branch delay slot. If it is in a jump or  
branch delay slot, the EPC register points at the preceding jump or branch instruction and the BD  
bit in the Cause register is set. The least-significant bit of the EPC register saves the ISA mode  
that was in effect prior to the exception.  
3. The processor jumps to the appropriate exception vector address (see Table 9-4).  
* The Trap exception occurs only in 32-bit ISA mode.  
9-9  
Chapter 9 Exception Handling  
9.1.10 System Call Exception  
„
Cause  
This exception occurs when a SYSCALL instruction is executed.  
„
Handling  
1. The Sys code (8) is set into the ExcCode field in the Cause register.  
2. The following operation only occurs when the EXL bit in the Status register is cleared. The EXL  
bit is set, and the EPC register is loaded with the address of the instruction that caused the exception  
unless this instruction is not in a jump or branch delay slot. If it is in a jump or branch delay slot, the  
EPC register points at the preceding jump or branch instruction and the BD bit in the Cause register is  
set. The least-significant bit of the EPC register saves the ISA mode that was in effect prior to the  
exception.  
3. If the exception occurs while the processor is in 16-bit ISA mode, the processor switches to 32-bit  
ISA mode.  
4. The processor jumps to an appropriate exception vector address (see Table 9-4).  
When a System Call exception occurs, control is transferred to an exception handler. The unused  
bits (bits 25-6 in the 32-bit ISA; bits 25-16 and 10-5 in the 16-bit ISA) in a SYSCALL instruction is  
available for use as software parameters to pass additional information. To examine these bits, load  
the contents of the instruction at which the EPC register points. If the instruction is in a jump or  
branch delay slot (i.e., the BD bit in the Cause register is set), add four to the contents of the EPC  
register to locate the instruction.  
To resume execution after the exception has been serviced, alter the contents of the EPC register by  
adding four so that the SYSCALL instruction is not re-executed. If the SYSCALL instruction is in a  
jump or branch delay slot (i.e., the BD bit in the Cause register is set), the instruction at the return  
address is a jump or branch instruction. In that case, the jump or branch instruction must be  
interpreted to set the EPC register before resuming execution.  
9-10  
Chapter 9 Exception Handling  
9.1.11 Breakpoint Exception  
„
Cause  
This exception occurs when a BREAK instruction is executed.  
„
Handling  
1. The Bp code (9) is set into the ExcCode field in the Cause register.  
2. The following operation only occurs when the EXL bit in the Status register is cleared. The  
EXL bit is set, and the EPC register is loaded with the address of the instruction that caused  
the exception unless this instruction is not in a jump or branch delay slot. If it is in a jump or  
branch delay slot, the EPC register points at the preceding jump or branch instruction and the  
BD bit in the Cause register is set. The least-significant bit of the EPC register saves the ISA  
mode that was in effect prior to the exception.  
3. If the exception occurs while the processor is in 16-bit ISA mode, the processor switches to  
32-bit ISA mode.  
4. The processor jumps to the appropriate exception vector address (see Table 9-4).  
When a Breakpoint exception occurs, control is transferred to an exception handler. The unused bits  
(bits 25-16 in the 32-bit ISA, bits 10-5 in the 16-bit ISA) in a BREAK instruction is available for  
use as software parameters to pass additional information. To examine these bits, load the contents  
of the instruction at which the EPC register points. If the instruction is in a jump or branch delay  
slot (i.e., the BD bit in the Cause register is set), add four (in the 32-bit ISA mode) or two (in the 16-  
bit ISA mode) to the contents of the EPC register to locate the instruction.  
To resume execution after the exception has been serviced, alter the contents of the EPC register by  
adding four (in 32-bit ISA mode) or two (in 16-bit ISA mode) so that the BREAK instruction is not  
re-executed. If the BREAK instruction is in a jump or branch delay slot (i.e., the BD bit in the Cause  
register is set), the instruction at the return address is a jump or branch instruction. In that case, the  
jump or branch instruction must be interpreted to set the EPC register before resuming execution.  
9-11  
Chapter 9 Exception Handling  
9.1.12 Reserved Instruction Exception  
„
Cause  
In 32-bit ISA mode, this exception occurs when an attempt is made to:  
z execute an instruction with an undefined major opcode (bits 31-26)  
z execute a SPECIAL instruction with an undefined minor opcode (bits 5-0)  
z execute a SPECIAL2 instruction with an undefined minor opcode (bits 5-0)  
z execute a REGIMM instruction with an undefined minor opcode (bits 20-16)  
z execute a COPz rs instruction (z=1 or 2) with an undefined minor opcode (bits 25-21)  
z execute a LWCz, SWCz, LDCz, SDCz (z=1 or 2) or MOVCI instruction  
In 16-bit ISA mode, this exception occurs when an attempt is made to:  
z execute an instruction with an undefined instruction code: 11101xxxxxx01001,  
11101xxxxxx10011, 11101xxxx1100000, 11101xxx01010001, 11101xxx01110001,  
11101xxx11010001 or 11101xxx11110001  
z execute an unimplemented instruction (LWU, LD, SD, DADDU, DSUBU, DADDIU,  
DMULT, DMULTU, DDIV, DDIVU, DSLL, DSRL, DSRA, DSLLV, DSRLV, DSRAV)  
z EXTEND an instruction that is not extensible  
z execute an instruction with an undefined EXTEND+RR minor opcode (bits 4-0)  
z execute an instruction with an undefined EXTEND+ADDIU8 minor opcode (bits 7-5 = 001  
or 011)  
z execute an instruction with an undefined EXTEND+INT minor opcode ([7][1:0] = 100 &  
[10:8] ≠ 00x)  
9-12  
Chapter 9 Exception Handling  
„
Handling  
1. The RI code (10) is set into the ExcCode field in the Cause register.  
2. The following operation only occurs when the EXL bit in the Status register is cleared. The  
EXL bit is set, and the EPC register is loaded with the address of the instruction that caused  
the exception unless this instruction is not in a jump or branch delay slot. If it is in a jump or  
branch delay slot, the EPC register points at the preceding jump or branch instruction and the  
BD bit in the Cause register is set. The least-significant bit of the EPC register saves the ISA  
mode that was in effect prior to the exception.  
3. If the exception occurs while the processor was in 16-bit ISA mode, the processor switches to  
32-bit ISA mode.  
4. The processor jumps to an appropriate exception vector address (see Table 9-4).  
9-13  
Chapter 9 Exception Handling  
9.1.13 Coprocessor Unusable Exception  
„
Cause  
This exception occurs when an attempt is made to:  
•
execute a CP0 instruction in User mode when the CU0 bit in the Status register is cleared  
(Kernel- and Debug-mode execution of CP0 instructions never causes this exception, regardless  
of the setting of the CU0 bit)  
•
•
execute COP1, LWC1, SWC1, LDC1, SDC1 or MOVCI instruction when the CU1 bit in the  
Status register is cleared  
execute COP2, LWC2, SWC2, LDC2 or SDC2 instruction when the CU2 bit in the Status  
register is cleared  
•
execute COP3 instruction when the CU3 bit in the Status register is cleared  
„
Handling  
The CpU code (11) is set into the ExcCode field in the Cause register.  
1. The CE field in the Cause register shows which of the coprocessor units was referenced when  
an exception occurred.  
2. The following operation only occurs when the EXL bit in the Status register is cleared. The  
EXL bit is set, and the EPC register is loaded with the address of the instruction that caused  
the exception unless this instruction is not in a jump or branch delay slot. If it is in a jump or  
branch delay slot, the EPC register points at the preceding jump or branch instruction and the  
BD bit in the Cause register is set. The least-significant bit of the EPC register saves the ISA  
mode that was in effect prior to the exception.  
3. If the exception occurs while the processor is in 16-bit ISA mode, the processor switches to  
32-bit ISA mode.  
4. The processor jumps to an appropriate exception vector address (see Table 9-4).  
9-14  
Chapter 9 Exception Handling  
9.1.14 Maskable Interrupt Exception (Interrupts)  
„
Cause  
The TX19A supports the following maskable interrupts:  
•
•
•
Two software interrupts (IP0 and IP1)  
Six hardware interrupts (IP2 to IP7)  
One timer interrupt (IP7)  
This exception occurs when all of the following conditions are met:  
1. An interrupt request bit in the IP [7:0] field of the Cause register is set (Cause).  
2. The corresponding interrupt mask bit in the IM [7:0] field of the Status register is set  
(Status).  
3. The Interrupt Enable (IE) bit in the Status register is set (Status).  
4. The processor is not in Debug mode; i.e., the DM bit in the Debug register is cleared  
(Debug).  
5. The Error Level (ERL) and Exception Level (EXL) bits in the Status register are cleared  
(Status).  
An interrupt is taken when all of these conditions are true and a higher-priority exception is not  
being serviced.  
IP7 can be configured for either a hardware interrupt (GINT [5] input) or an internal timer interrupt.  
The timer interrupt is valid when the GTINTDIS input is at logic 0, and GINT [5] is valid when it is  
at logic 1.  
„
Handling  
The interrupt vector address varies, depending on the settings of the BEV bit in the Status register  
and the IV bit in the Cause register.  
Table 9-5 Maskable Interrupt Vectors  
BEV (Status[22])  
IV (Cause[23])  
BEV=0  
BEV=1  
IV=0  
IV=1  
0x8000_0180  
0x8000_0200  
0xBFC0_0380  
0xBFC0_0400  
9-15  
Chapter 9 Exception Handling  
„
Servicing  
A software interrupt can be cleared by writing a 0 to the corresponding IP bit (IP1 or IP0) in the  
Cause register.  
A hardware interrupt can be cleared by clearing the cause of the interrupt.  
A timer interrupt can be cleared by altering the Compare register value.  
9.2 Interrupts  
The TX19A provides a non-maskable interrupt and maskable hardware and software interrupts. This  
section describes the types of interrupts, how interrupts are prioritized and how interrupts are  
recognized by the processor.  
9.2.1 Interrupt Types  
The TX19A recognizes a non-maskable interrupt, six maskable hardware interrupts and two  
maskable software interrupts. Interrupt exceptions are processed by hardware and then serviced by  
software (interrupt service routines). See 9.1.14, Maskable Interrupt Exception and  
9.1.5, Nonmaskable Interrupt (NMI) Exception for how interrupt exceptions are  
handled by processor hardware.  
Sources of non-maskable interrupts can be an assertion of the processor’s input or on-chip  
peripherals such as watchdog timers. See individual hardware user’s manuals for possible on-chip  
sources of non-maskable interrupts. Non-maskable interrupts are for implementation of critical  
interrupt routines and can not be masked (disabled) by software; they are always recognized  
regardless of CPU operation mode and forces the processor to restart at 0xBFC0_0000.  
Maskable hardware interrupts are detected with the processor’s 3-bit interrupt port. Interrupt  
requests originate from external or on-chip hardware resources. Interrupt requests are submitted to  
the interrupt controller, which then turns them into a 3-bit priority level. The priority-level signals  
are connected to the IP4, IP3 and IP2 ports of the TX19A processor core. The TX19A automatically  
switches to a specific shadow register set associated with the conditions of IP4, IP3 and IP2  
immediately after the interrupt receipt. Thus, for the processor to accept a maskable hardware  
interrupt, the IM [4:2] bits in the Status register must be 111.  
9-16  
Chapter 9 Exception Handling  
There are two software interrupts, IP1 and IP0. Software interrupts can be generated by setting the  
corresponding bit in the Cause register. The application program may use these bits to request  
interrupt service. There are corresponding bits in the Status register to mask respective software  
interrupts.  
9.2.2 Maskable Interrupt Vectors  
Maskable interrupts are vectored to the addresses shown in Table 9-5, depending on the register  
settings. The TX19A uses the same vector addresses for both hardware and software interrupts.  
When an interrupt occurs, the interrupt service routine must check the interrupt controller in order to  
determine the source of the interrupt, read the corresponding vector address and transfer control to it.  
9.2.3 Maskable Interrupt Recognition  
Maskable interrupts are taken when all of the following conditions are true:  
•
•
•
•
•
An interrupt request bit in the IP [7:0] field of the Cause register is set (Cause).  
The corresponding interrupt mask bit in the IM [7:0] field of the Status register is set (Status).  
The Interrupt Enable (IE) bit in the Status register is set (Status).  
The processor is not in Debug mode (Debug); i.e., the DM bit in the Debug register is cleared.  
The Error Level (ERL) and Exception Level (EXL) bits in the Status register are cleared.  
For the processor to accept a maskable hardware interrupt, the IM [4:2] bits in the Status register  
must be 111.  
In the event that both hardware- and software-requested interrupts are posted simultaneously, the  
hardware interrupt is delivered first while the software interrupt is left pending.  
9-17  
Chapter 9 Exception Handling  
Table 9-6 Mapping of Interrupts to the Cause and Status Registers  
Cause Register  
Bit  
Number  
Status Register  
Bit  
Number  
Interrupt  
Number  
Interrupt type  
Name  
Name  
0
1
0
1
2
3
4
[8]  
IP0  
[8]  
IM0  
Software Interrupt  
[9]  
IP1  
IP2  
IP3  
IP4  
IP5  
IP6  
[9]  
IM1  
IM2  
IM3  
IM4  
IM5  
IM6  
[10]  
[11]  
[12]  
[13]  
[14]  
[10]  
[11]  
[12]  
[13]  
[14]  
Hardware Interrupt  
Hardware Interrupt or  
Timer Interrupt  
5
[15]  
IP7  
[15]  
IM7  
Source #1  
Source #2  
Software Interrupt  
(Cause Register: IP1 or IP0 ? 1)  
Resolve hardware interrupt priority  
Hardware Interrupt Level  
Resolve interrupt priority  
3
Interrupt Controller  
Check interrupt enable conditions  
Accept an interrupt  
Source #3  
Switch shadow register set  
CSS  
PSS  
0
1
2
3
4
5
6
7
Figure 9-7 Maskable Interrupt Recognition  
9-18  
Chapter 9 Exception Handling  
9.2.4 Shadow Register Sets  
When a hardware interrupt occurs, the TX19A switches to a specific shadow register set associated  
with its priority level. The interrupt level is set to CSS bit (bit 3-0) in SSCR register. At the same time,  
CSS bit before update is set to PSS bit (bit11-8). The 3-bit priority-level signals from the interrupt  
controller are connected to the IP4, IP3 and IP2 ports of the processor. When the processor recognizes  
the interrupt, it switches to corresponding shadow register set depend on the signal conditions (see  
Table 9-8). Software interrupts, the internal timer interrupt or any other exceptions do not cause the  
TX19A to switch the shadow register set. The value of the PSS field is updated instead.  
On execution of the ERET instruction, the value of the PSS field is restored to the CSS field (see  
Figure 8-1).  
A debug exception and a return from a debug exception (via a DERET instruction) do not change  
the CSS and PSS fields.  
Table 9-8 Relationships Between IP[4:2] Signals and Shadow Register Sets  
IP4  
IP3  
IP2  
Shadow Register Set  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
–
1
2
3
4
5
6
7
9-19  
Chapter 9 Exception Handling  
9.3 Debug Exceptions  
There are Single-Step and Debug Breakpoint exceptions in the TX19A. This section provides  
details concerning sources of specific debug exceptions, how each arises and how each processed.  
9.3.1 How Debug Exception Processing Work  
The TX19A allows program instruction execution to arbitrarily stop to handle debugging events.  
Code execution breakpoints can be generated by the Software Debug Breakpoint (SDBBP)  
instruction. The single-step feature may be enabled by setting the SSt bit in the Debug register.  
Debug exception processing occurs in the sequence shown in Figure 9-9.  
Debug Exception Processing  
Running Program  
Debug Exception  
Debug  
(2) Capture cause and  
Handler  
current state of exception  
DEPC  
Set exception return address  
Debugger  
Command  
Processing  
(1)  
(6)  
(3) Change ISA mode to 32-bit  
(5) DERET  
(4) Set exception vector  
address  
Instruction  
PC  
Figure 9-9 Exception Operation  
5. The currently executing instruction and any subsequent instructions in the pipeline are aborted.  
6. The debug exception registers save information about the debugging event.  
•
•
The Debug register shows the cause of the debug exception and whether it is currently being  
serviced.  
The DEPC register captures the virtual address of the instruction that caused a debug exception.  
When the instruction is in a jump or branch delay slot, the DEPC register is rolled back to point to  
the jump or branch instruction so that it can be re-executed, and the DBD bit in the Debug  
register is set. The least-significant bit of the DEPC register is the ISA mode bit that indicates the  
ISA mode that as in effect when the exception occurred.  
9-20  
Chapter 9 Exception Handling  
3. The processor enters Kernel mode and disables all interrupts, independent of the setting of the  
Status register. If the exception occurs in 16-bit ISA mode, the least-significant bit (i.e., the  
ISA mode bit) of the PC is set to zero, bringing the processor into 32-bit ISA mode.  
4. The PC is loaded with the Debug exception vector address to jump to the starting location of  
the debug exception handler.  
5. At completion of the debug exception handler, the DERET instruction is executed to jump  
back to the return address saved in the DEPC register.  
6. Processing resumes from the point where the processor left off when the exception occurred.  
9.3.2 Debug Exception Types  
Table 9-10 gives the types of debug exceptions that can occur in the TX19A processor.  
Table 9-10 Debug Exception Types  
Exception Type  
Description  
A Single-step exception occurs before the next instruction starts execution when the  
SSt bit in the Debug register is set.  
Single-Step  
A Debug Breakpoint exception provides a code execution breakpoint; it occurs  
when an SDBBP instruction is executed. If the SSt bit in the Debug register is set, a  
Single-step exception takes precedence over a Debug Breakpoint exception. If the  
SDBBP instruction is executed while a debug exception is being serviced (i.e.,  
when the DM bit in the Debug register is 1), another debug exception is taken; in  
this case, the Break exception code is set into the DExcCode field in the Debug  
register.  
Debug Breakpoint  
9.3.3 Debug Exception Priorities  
A debug exception and a general exception may occur simultaneously. In that case, the processor  
services the exceptions in the order shown in Table 9-1.  
9-21  
Chapter 9 Exception Handling  
9.3.4 Exception Masking  
While a debug exception is being serviced (DM=1 and IEXI=1), the processor masks all the other  
exceptions.  
•
When a Bus Error event occurs on an instruction fetch, the IBusEP bit in the Debug register is set  
to flag its occurrence. When a Bus Error event occurs on a data access, the DBusEP bit in the  
Debug register is set.  
•
•
•
All maskable interrupts are disabled while a debug exception is being serviced. (Maskable  
interrupts are unmasked by the execution of a DERET instruction.)  
A non-maskable interrupt is left pending until a return from a debug exception is made through  
the DERET instruction.  
When the IEXI bit in the Debug register is cleared, the TX19A responds to a general exception  
event (except maskable and non-maskable interrupt requests). Even if a general-exception  
condition arises, a debug exception is processed, causing the processor to jump to the debug  
exception handler. In this case, the Debug register bits that indicate the cause of the exception  
(DINT, DIB, DBp, DSS, DDBSImpr and DDBLImpr) remain unchanged. Instead the DExcCode  
field shows the cause of the general exception that occurred in Debug mode.  
9.3.5 Executing a Debug Exception Handler  
A debug exception handler should operate the processor under controlled conditions for program  
debug. It should check the DSS and DBp bits in the Debug register to determine whether to perform  
single-step execution or code-execution breakpoint operations.  
9.3.6 Returning from Debug Exceptions  
Returning from the debug exception handler is made through the DERET instruction, which  
performs the following:  
1. Restores the return address in the DEPC register into the program counter (PC) so that the  
processor resumes processing from the point where a debug exception occurred. If the  
instruction that caused an exception is in a jump or branch delay slot, the PC points at the  
preceding jump or branch instruction so that it can be re-executed. The ISA mode bit of the  
PC is restored from bit 0 of the DEPC register to enter ISA mode that was in effect before the  
exception occurred.  
2. Clears the Debug Mode (DM) and IEXI bits in the Debug register.  
3. Gets out of the forced "Kernel mode" state.  
9-22  
Chapter 9 Exception Handling  
9.3.7 Single-Step Exception  
„
Cause  
This exception occurs when the SSt bit in the Debug register is set.  
„
Handling  
A Single-step exception takes place before executing the next instruction. Figure 9-11 highlights the  
CP0 register fields that are used to handle this exception.  
24  
21 20  
IEXI  
14  
10  
8
30  
31  
0
DBD DM  
31  
DExcCode  
IBusEP  
SSt  
DBusEP  
DSS  
Debug register  
DEPC register  
0
Figure 9-11 Single-Step Exception  
1. The DM and DSS bits in the Debug register are set. That a Single-Step exception occurred means  
the SSt bit had been set.  
2. The DEPC register stores the program counter on the exception. The least-significant bit in the  
DEPC register saves the ISA mode that was in effect prior to the exception.  
3. The processor enters Kernel mode and disables all interrupts, independent of the settings of the  
Status register.  
4. The processor jumps to the exception handler located at address 0xBFC0_0480.  
The processor does not take a Single-Step exception for the following cases:  
•
•
the instruction in a jump or branch delay slot  
the first instruction on returning from a debug instruction through the DERET instruction (see  
Figure 9-12)  
•
a debug exception is being serviced (i.e., the DM bit in the Debug register is set)  
9-23  
Chapter 9 Exception Handling  
Executed  
DERET  
NOP  
F
D
F
E
D
F
M
E
D
F
W
M
E
W
M
Not Executed  
Executed  
W
D
#1 after the return  
#2 after the return  
#3 after the return  
#4 after the return  
D
Single-step exception  
Nullified  
F
Not fetched  
Exception handler’s  
F
E
M
W
#1 in debug exception handler  
starting instruction  
The DEPC register points at instruction #2 after the return from the exception.  
Figure 9-12 CPU Pipeline Operation After the DERET Instruction  
9.3.8 Debug Breakpoint Exception  
„
Cause  
This exception occurs when an SDBBP instruction is executed.  
„
Handling  
Figure 9-13 highlights the CP0 register fields that are used to handle this exception.  
24  
21 20  
14  
10  
30  
31  
1
DBD DM  
31  
DExcCode  
IBusEP  
DBusEP IEXI  
DBp  
Debug register  
DEPC register  
0
Figure 9-13 Debug Breakpoint Exception  
1. The DM and DBp bits in the Debug register are set. That a Debug Breakpoint exception occurred  
means the SSt bit had been cleared.  
2. The DEPC register stores the program counter on the exception. If the processor is executing an  
instruction in a jump or branch delay slot, the DEPC register points at the preceding jump or  
branch instruction, and the DBD bit in the Debug register is set. The least-significant bit in the  
DEPC register saves the ISA mode that was in effect prior to the exception.  
3. The processor enters Kernel mode and disable all interrupts, independent of the settings of the  
Status register.  
4. If the exception occurs while the processor is in 16-bit ISA mode, the processor switches to 32-bit  
ISA mode.  
5. The processor jumps to the exception handler located at address 0xBFC0_0480.  
9-24  
Chapter 9 Exception Handling  
The unused bits (bits 25-6 in the 32-bit ISA, bits 10-5 in the 16-bit ISA) in an SDDBP instruction are  
available for use as software parameters to pass additional information to an exception handler. To  
examine these bits, load the contents of the instruction at which the DEPC register points. If the  
instruction is in a jump or branch delay slot (i.e., the DBD bit in the Debug register is set), add four to  
the contents of the DEPC register to locate the instruction.  
To resume execution after the exception has been serviced, alter the contents of the DEPC register by  
adding four (in 32-bit ISA mode) or two (in 16-bit ISA mode) so that the SDDBP instruction is not  
re-executed. If the SDDBP instruction is in a jump or branch delay slot (i.e., the DBD bit in the Debug  
register is set), the instruction at the return address is a jump or branch instruction. In that case, the  
jump or branch instruction must be interpreted to set the DEPC register before resuming execution.  
9-25  
Chapter 9 Exception Handling  
9-26  
Chapter 10 Power Consumption Management  
Chapter 10 Power Consumption Management  
The TX19A provides hardware support for several levels of power reduction. The Halt and Doze  
modes are entered by setting the RP bit in the CP0's Status register and executing the WAIT  
instruction. This chapter describes the power management features and capabilities provided by the  
TX19A.  
10.1 Power-Saving Modes  
Figure 10-1 illustrates the power-saving modes provided by the TX19A.  
Clock Stopped  
Free-Running Clock  
CPU Inactive  
CPU Active  
Doze  
(CPU bus requests  
monitored)  
Normal Operation  
(Full-On mode)  
Standby  
Halt  
(
CPU bus requests  
disabled)  
Figure 10-1 Power-Saving Modes  
10-1  
Chapter 10 Power Consumption Management  
The TX19A has the capability to dynamically control power consumption during operation. Table  
10-2 describes the available power-saving modes.  
Table 10-2 Power-Saving Modes  
Mode  
Description  
For lowest power operation, the processor clock can be removed altogether. There  
are two levels of power savings achieved through Standby mode.  
1. In one mode, both the processor and the oscillator circuitry are disabled  
altogether.  
Standby Mode  
2. In the other mode, the oscillator circuitry continues to run, but the clock input to  
the processor is disabled.  
For details on Standby mode, see respective hardware user’s manuals.  
In Halt mode, all activities of the processor stop, and the CPU bus monitoring is  
disabled. The TX19A processor assumes bus mastership. Halt mode can be  
entered by executing the WAIT instruction when the RP bit in the Status register is  
Halt Mode  
cleared.  
In Doze mode, all activities of the processor stop except for the CPU bus monitor  
that continues to operate and recognizes bus requests. Bus mastership is granted  
to an external agent. Doze mode can be entered by executing the WAIT instruction  
Doze Mode  
when the RP bit in the Status register is set.  
This is the default power state of the TX19A following a hardware reset, with the  
Normal Mode (Full-On  
Mode)  
processor fully powered and operating at full clock speed.  
There are components having additional power-saving capabilities, e.g., a very-low  
speed mode in which the clock runs at 32.768 kHz for time-of-day clocks. For  
Other Modes  
additional power-saving modes, see respective hardware user’s manuals.  
10-2  
Chapter 10 Power Consumption Management  
10.2 Halt Mode  
Figure 10-2 depicts how Halt mode can be entered.  
Exception  
(Reset, Nonmaskable Interrupt or Hardware Interrupt)  
Clock Restarted  
Standby  
Halt  
Full-On  
(Disabled Bus Monitoring)  
Status Register: RP ? 0  
WAIT Instruction  
Clock Stopped  
Figure 10-2 Halt Mode  
The processor enters Halt mode on execution of the WAIT instruction when the RP bit in the Status  
register is cleared during normal operation mode. Halt mode freezes the "processor core," preserving  
the pipeline state. In Halt mode, the processor ignores any external bus requests, as it monopolizes  
mastership of the bus.  
In Halt mode, the on-chip write buffer unit (if any) continues to operate until all entries in it have  
been written to external memory.  
A wakeup from Halt mode can be achieved by causing a Reset, Nonmaskable  
Interrupt or Maskable Hardware Interrupt exception. Any of these exceptions causes the processor  
to exit Halt mode and take an exception.  
Maskable interrupts are recognized even if they are masked in the Status register. In that case, after a  
wakeup, normal processing resumes with all register contents intact, i.e., the processor continues  
execution from the address following the instruction that brought the processor into Halt mode.  
In Halt mode, the processor may have its clock input shut down for additional power savings. The  
oscillator and/or clock stop causes the processor to enter Standby mode. Restarting the clock to the  
processor causes it to return to Halt mode.  
10-3  
Chapter 10 Power Consumption Management  
10.3 Doze Mode  
Figure 10-3 depicts how Doze mode can be entered.  
Exception  
(Reset, Nonmaskable Interrupt or Hardware Interrupt)  
Doze  
Full-On  
(Enabled Bus)  
Status Register: RP ? 1  
WAIT Instruction  
Figure 10-3 Doze Mode  
The processor enters Doze mode on execution of the WAIT instruction when the RP bit in the Status  
register is cleared during normal operation mode. Like Halt mode, Doze mode freezes the "processor  
core," preserving the pipeline state, but in Doze mode, the processor recognizes external bus requests.  
In Doze mode, the on-chip write buffer unit (if any) continues to operate until all entries in it have  
been written to external memory.  
A wakeup from Doze mode can be achieved by causing a Reset, Non-maskable  
Interrupt or Maskable Hardware Interrupt exception. Any of these exceptions causes the processor  
to exit Doze mode and take an exception.  
Maskable interrupts are recognized even if they are masked in the Status register. In that case, after a  
wakeup, normal processing resumes with all register contents intact, i.e., the processor continues  
execution from the address following the instruction that brought the processor into Doze mode.  
10-4  
Appendix A 32-Bit ISA Details  
Appendix A 32-Bit ISA Details  
This appendix presents detailed information concerning each instruction in the 32-bit ISA, including  
assembler syntax, instruction format, operation and exceptions that may occur due to the execution  
of the instruction. Each instruction is listed alphabetically by mnemonic. For the variations of  
instruction formats, see Section 3.1, Instruction Formats.  
A-1  
Appendix A 32-Bit ISA Details  
ADD rd, rs, rt  
Add  
Operation  
rd ⇐ rs + rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
ADD  
rs  
5
rt  
5
Rd  
5
00000  
100000  
6
5
6
Description  
The contents of general-purpose register rs is added to the contents of general-purpose register rt,  
and the result is placed into general-purpose register rd.  
In the case of c←a+b, an Interger Overflow exception occurs if a and b has the same sign and c has  
the different one. The destination register (rd) is not altered when an Integer Overflow exception  
occurs.  
Exceptions  
Interger Overflow exception  
Examples  
1. Assume that registers r2 and r3 contain 0x0200_0000 and 0x0123_4567 respectively. Then,  
executing the instruction:  
ADD r4,r2,r3  
places the sum (0x0323_4567) into r4.  
2.  
Assume that registers r2 and r3 contain 0x7FFF_FFFF and 0x0000_0001 respectively. Then, the  
addition of r2 and r3 gives the result 0x8000_0000, which is a negative number, indicating a  
2’s-complement overflow. Thus executing the instruction:  
ADD r4,r2,r3  
causes an Integer Overflow exception. Register r4 is not modified as a result of this instruction.  
A-2  
Appendix A 32-Bit ISA Details  
ADDI rt, rs, immediate  
Add Immediate  
Operation  
rt ⇐ rs + ((immediate15)16 || immediate15..0  
)
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
ADDI  
rs  
5
rt  
5
immediate  
16  
001000  
6
Description  
The 16-bit immediate is sign-extended and added to the contents of general-purpose register rs. The  
result is placed into general-purpose register rt.  
An Integer Overflow exception is taken on 2’s-complement overflow. The destination register (rt) is  
not altered when an Integer Overflow exception occurs.  
With the 16-bit signed immediate, the immediate range is -32768 to +32767. If a number is outside  
this range, you need to put it in a general-purpose register and use the ADD or ADDU instruction  
(see Section 3.3.2, 32-Bit Constants).  
Exceptions  
Integer Overflow exception  
Example  
Assume that register r2 contains 0x0200_F000. Then, executing the instruction:  
ADDI r3,r2,0x1234  
places the sum 0x0201_0234 into r3.  
0
0
2
0
0
0
0
0
F
1
0
2
0
3
0
4
r2  
r3  
+
Sign-Extended  
0
2
0
1
0
2
3
4
A-3  
Appendix A 32-Bit ISA Details  
ADDIU rt, rs, immediate  
Add Immediate Unsigned  
Operation  
rt ⇐ rs + ((immediate15)16 || immediate15..0  
)
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
ADDIU  
001001  
Rs  
5
rt  
5
immediate  
16  
6
Description  
The term "Add Immediate Unsigned" is a misnomer; the 16-bit immediate is sign-extended and added  
to the contents of general-purpose register rs. The result is placed into general-purpose register rt.  
The only difference between this instruction and the ADDI instruction is that this instruction never  
causes an Integer Overflow exception.  
Exceptions  
None  
A-4  
Appendix A 32-Bit ISA Details  
ADDU rd, rs, rt  
Add Unsigned  
Operation  
rd ⇐ rs + rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
ADDU  
rs  
5
rt  
5
rd  
5
00000  
100001  
6
5
6
Description  
The contents of general-purpose register rs is added to the contents of general-purpose register rt, and  
the result is placed into general-purpose register rd.  
The only difference between this instruction and the ADD instruction is that this instruction never  
causes an Integer Overflow exception.  
Exceptions  
None  
A-5  
Appendix A 32-Bit ISA Details  
AND rd, rs, rt  
AND  
Operation  
rd ⇐ rs AND rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
AND  
rs  
5
rt  
5
rd  
5
00000  
100100  
6
5
6
Description  
The contents of general-purpose register rs is ANDed with the contents of general-purpose register  
rt, and the result is placed into general-purpose register rd.  
Exceptions  
None  
Example  
Assume that registers r2 and r3 contain 0x8000_7350 and 0x0000_3456 respectively. Then, the  
instruction:  
AND r4,r2,r3  
performs the logical AND between r2 and r3 and puts the result (0x0000_3050) in r4, as shown  
below.  
1000 0000 0000 0000 0111 0011 0101 0000  
r2  
AND  
0000 0000 0000 0000 0011 0100 0101 0110  
r3  
0000 0000 0000 0000 0011 0000 0101 0000  
r4  
A-6  
Appendix A 32-Bit ISA Details  
ANDI rt, rs, immediate  
Logical AND Immediate  
Operation  
rt ⇐ rs AND (016 || immediate15..0  
)
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
ANDI  
rs  
5
rt  
5
immediate  
16  
001100  
6
Description  
The 16-bit immediate is zero-extended and ANDed with the contents of general-purpose register rs.  
The result is placed into general-purpose register rt.  
The immediate field is 16 bits in length. If the immediate size is larger than that, you need to put it in  
a general-purpose register and use the AND instruction (see Section 3.3.2, 32-Bit Constants).  
Exceptions  
None  
Example  
Assume that register r2 contains 0x0000_7350. Then, the instruction:  
ANDI r3,r2,0x1234  
performs the logical AND between 0x0000_7350 and 0x0000_1234 and puts the result  
(0x0000_1210) in r3, as shown below.  
0000 0000 0000 0000 0111 0011 0101 0000  
r2  
r3  
AND  
0000 0000 0000 0000 0001 0010 0011 0100  
Zero-Extended  
0000 0000 0000 0000 0001 0010 0001 0000  
A-7  
Appendix A 32-Bit ISA Details  
Assembly Idiom  
B offset  
Unconditional Branch  
Operation  
pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
BEQ  
0
0
offset  
16  
000100  
00000  
00000  
6
5
5
Description  
The program unconditionally branches to the target address with a delay of one instruction (or two  
pipeline cycles). The target address is computed relative to the address of the instruction in the branch  
delay slot (PC+4); the 16-bit immediate offset is shifted left by two bits, sign-extended and added to  
PC+4 to form the target address.  
Exceptions  
None  
Example  
B SGEZERO  
Assume that the B instruction resides at address 0x2000 and that label SGEZERO points to absolute  
address 0x1C04. Then the assembler/linker turns this label into a relative offset of 0xFF00 (see the  
figure below).  
The processor unconditionally transfers program control to 0x1C04. The instruction in the branch  
delay slot is executed before the branch is taken.  
0x1C04  
Branch Destination  
0x2000  
0x2004  
B
SGEZERO  
Branch Delay Slot  
+
0xFFFF_FC00  
The offset, 0xFF00, is shifted left  
by 2 bits and sign-extended.  
A-8  
Appendix A 32-Bit ISA Details  
Assembly Idiom  
BAL offset  
Branch And Link  
Operation  
r31 ⇐ pc + 8; pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
0
BGEZAL  
10001  
Offset  
16  
00000  
6
5
5
Description  
The program unconditionally branches to the target address with a delay of one instruction (or two  
pipeline cycles). The address of the instruction after the branch delay slot (PC+8) is saved in the link  
register, r31 (ra). The target address is computed relative to the address of the instruction in the  
branch delay slot (PC+4); the 16-bit immediate offset is shifted left by two bits, sign-extended and  
added to PC+4 to form the target address.  
Exceptions  
None  
Example  
BAL PSUB  
Assume that the BAL instruction resides at address 0x2000 and that label PSUB points to absolute  
address 0x2404. Then the assembler/linker turns this label into a relative offset of 0x0100 (see the  
figure below).  
The processor unconditionally transfers program control to address 0x2404. The instruction in the  
branch delay slot is executed before the branch is taken.  
The JR instruction is used at the end of the called subroutine to return control to the instruction after  
the branch delay slot (PC+8).  
JR r31  
A-9  
Appendix A 32-Bit ISA Details  
0x2000  
0x2004  
0x2008  
BAL PSUB  
Branch Delay Slot  
PC+8 is saved in r31.  
+
0x0400  
r31  
0x0000 2008  
The offset, 0x0100, is shift left by  
2 bits and sign-extended.  
0x2404  
Branch Destination  
‚
‚
‚
PC+8 is restored from r31.  
JR  
r31  
Subroutine  
A-10  
Appendix A 32-Bit ISA Details  
BEQ rs, rt, offset  
Branch On Equal  
Operation  
if rs = rt then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
BEQ  
rs  
5
rt  
5
offset  
16  
000100  
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt. If the two registers are equal, then the program branches to the target address with a delay of one  
instruction (or two pipeline cycles). The instruction in the branch delay slot is always executed,  
regardless of whether the branch is taken or not. The target address is computed relative to the  
address of the instruction in the branch delay slot (PC+4); the 16-bit immediate offset is shifted left  
by two bits, sign-extended and added to PC+4 to form the target address.  
Exceptions  
None  
A-11  
Appendix A 32-Bit ISA Details  
BEQL rs, rt, offset  
Branch On Equal Likely  
Operation  
if rs = rt then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
BEQL  
rs  
5
rt  
5
offset  
16  
010100  
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt. If the two registers are equal, then the program branches to the target address with a delay of one  
instruction (or two pipeline cycles). If the branch condition is true, the instruction in the branch  
delay slot is executed before the branch; otherwise, it is nullified. The target address is computed  
relative to the address of the instruction in the branch delay slot (PC+4); the 16-bit immediate offset  
is shifted left by two bits, sign-extended and added to PC+4 to form the target address.  
Exceptions  
None  
A-12  
Appendix A 32-Bit ISA Details  
BGEZ rs, offset  
Branch On Greater Than Or Equal To Zero  
Operation  
if rs ≥ 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
BGEZ  
00001  
rs  
5
offset  
16  
6
5
Description  
If the contents of general-purpose register rs are greater than or equal to zero, then the program  
branches to the target address with a delay of one instruction (or two pipeline cycles). The instruction  
in the branch delay slot is always executed, regardless of whether the branch is taken or not. The  
target address is computed relative to the address of the instruction in the branch delay slot (PC+4);  
the 16-bit immediate offset is shifted left by two bits, sign-extended and added to PC+4 to form the  
target address.  
Exceptions  
None  
Example  
BGEZ r8,SGEZERO  
Assume that this branch instruction resides at address 0x2000 and that label SGEZERO points to  
absolute address 0x1C04. Then the assembler/linker turns this label into a relative offset of 0xFF00  
(see the figure below).  
If the contents of r8 is greater than or equal to zero (i.e., r8 has the sign bit cleared), the processor  
transfers program control to address 0x1C04. The branch takes effect after the instruction in the  
branch delay slot is executed.  
A-13  
Appendix A 32-Bit ISA Details  
0x1C04  
Branch Destination  
0x2000  
0x2004  
BGEZ  
r8, SGEZERO  
Branch Delay Slot  
+
The offset, 0xFF00, is shifted left  
by 2 bits and sign-extended.  
A-14  
Appendix A 32-Bit ISA Details  
BGEZAL rs, offset  
Branch On Greater Than or Equal To Zero And Link  
Operation  
r31 ⇐ pc +8; if rs ≥ 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
BGEZAL  
10001  
rs  
5
offset  
16  
6
5
Description  
If the contents of general-purpose register rs is greater than or equal to zero, then the program  
branches to the target address with a delay of one instruction (or two pipeline cycles), and saves the  
address of the instruction following the branch delay slot (PC+8) in the link register, r31. The  
instruction in the branch delay slot is always executed, regardless of whether the branch is taken or  
not. The target address is computed relative to the address of the instruction in the branch delay slot  
(PC+4); the 16-bit immediate offset is shifted left by two bits, sign-extended and added to PC+4 to  
form the target address.  
General-purpose register rs may not be r31 because such an instruction cannot be restarted, with the  
contents of rs altered by the return address. An exception or interrupt could prevent the completion  
of a legal instruction in the branch delay slot. If that happens, after the exception handler routine has  
been executed, processing must restart with the branch instruction.  
Exceptions  
None  
Example  
BGEZAL r8,PSUB  
Assume that this branch instruction resides at address 0x2000 and that label PSUB points to  
absolute address 0x2404. Then the assembler/linker turns this label into a relative offset of 0x0100  
(see the figure below).  
If the contents of r8 is greater than or equal to zero (i.e., r8 has the sign bit cleared), the processor  
transfers program control to address 0x2404. The branch takes effect after the instruction in the  
branch delay slot is executed.  
A-15  
Appendix A 32-Bit ISA Details  
The JR instruction is used at the end of the called subroutine to return control to the instruction after  
the branch delay slot (PC+8).  
JR r31  
0x2000  
BGEZAL r8, PSUB  
0x2004  
Branch Delay Slot  
0x2008  
PC+8 is saved in r31.  
+
0x0400  
r31  
0x0000 2008  
The offset, 0x0100, is shifted left  
by 2 bits and sign-extended.  
0x2404  
Branch Destination  
‚
‚
‚
PC+8 is restored from r31.  
JR  
r31  
Subroutine  
A-16  
Appendix A 32-Bit ISA Details  
BGEZALL rs, offset  
Branch On Greater Than Or Equal To Zero And Link Likely  
Operation  
r31 ⇐ pc +8; if rs ≥ 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
BGEZALL  
10011  
rs  
5
offset  
16  
6
5
Description  
If the contents of general-purpose register rs is greater than or equal to zero, then the program  
branches to the target address with a delay of one instruction (or two pipeline cycles), and saves the  
address of the instruction following the branch delay slot (PC+8) in the link register, r31. If the  
branch condition is true, the instruction in the branch delay slot is executed before the branch;  
otherwise, it is nullified. The target address is computed relative to the address of the instruction in  
the branch delay slot (PC+4); the 16-bit immediate offset is shifted left by two bits, sign-extended  
and added to PC+4 to form the target address.  
General-purpose register rs may not be r31 because such an instruction cannot be restarted, with the  
contents of rs altered by the return address. An exception or interrupt could prevent the completion  
of a legal instruction in the branch delay slot. If that happens, after the exception handler routine has  
been executed, processing must restart with the branch instruction.  
Exceptions  
None  
Example  
BGEZALL r8,PSUB  
Assume that this branch instruction resides at address 0x2000 and that label PSUB points to  
absolute address 0x2404. Then the assembler/linker turns this label into a relative offset of 0x0100.  
If the contents of r8 is greater than or equal to zero (i.e., r8 has the sign bit cleared), the processor  
transfers program control to address 0x2404. The branch takes effect after the instruction in the  
branch delay slot is executed. When the branch is not taken, the instruction in the branch delay is  
nullified.  
A-17  
Appendix A 32-Bit ISA Details  
The JR instruction is used at the end of the called subroutine to return control to the instruction after  
the branch delay slot (i.e., PC+8).  
JR r31  
0x2000  
BGEZALL r8, PSUB  
0x2004  
Branch Delay Slot  
0x2008  
PC+8 is saved in r31.  
+
0x0400  
r31  
0x0000 2008  
The offset, 0x0100, is shifted left  
by 2 bits and sign-extended.  
0x2404  
Branch Destination  
‚
‚
‚
PC+8 is restored from r31.  
JR  
r31  
Subroutine  
A-18  
Appendix A 32-Bit ISA Details  
BGEZL rs, offset  
Branch On Greater Than Or Equal To Zero Likely  
Operation  
if rs ≥ 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
BGEZL  
00011  
rs  
5
offset  
16  
6
5
Description  
If the contents of general-purpose register rs is greater than or equal to zero, then the program  
branches to the target address with a delay of one instruction (or two pipeline cycles). If the branch  
condition is true, the instruction in the branch delay slot is executed before the branch; otherwise, it  
is nullified. The target address is computed relative to the address of the instruction in the branch  
delay slot (PC+4); the 16-bit immediate offset is shifted left by two bits, sign-extended and added to  
PC+4 to form the target address.  
Exceptions  
None  
Example  
BGEZL r8,SGEZERO  
Assume that this branch instruction resides at address 0x2000 and that label SGEZERO points to  
absolute address 0x1C04. Then the assembler/linker turns this label into a relative offset of 0xFF00  
(see the figure below).  
If the contents of r8 is greater than or equal to zero (i.e., r8 has the sign bit cleared), the processor  
transfers program control to address 0x1C04. The branch takes effect after the instruction in the  
branch delay slot is executed. When the branch is not taken, the instruction in the branch delay slot  
is nullified.  
A-19  
Appendix A 32-Bit ISA Details  
0x1C04  
Branch Destination  
0x2000  
0x2004  
BGEZ  
r8, SGEZERO  
Branch Delay Slot  
0xFFFF_FC00  
The offset, 0xFF00, is shifted left  
by 2 bits and sign-extended.  
+
A-20  
Appendix A 32-Bit ISA Details  
BGTZ rs, offset  
Branch On Greater Than Zero  
Operation  
if rs > 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
BGTZ  
0
rs  
5
offset  
16  
000111  
00000  
6
5
Description  
If the contents of general-purpose register rs is greater than zero, then the program branches to the  
target address with a delay of one instruction (or two pipeline cycles). The instruction in the branch  
delay slot is always executed, regardless of whether the branch is taken or not. The target address is  
computed relative to the address of the instruction in the branch delay slot (PC+4); the 16-bit  
immediate offset is shifted left by two bits, sign-extended and added to PC+4 to form the target  
address.  
Exceptions  
None  
A-21  
Appendix A 32-Bit ISA Details  
BGTZL rs, offset  
Branch On Greater Than Zero Likely  
Operation  
if rs > 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
BGTZL  
010111  
0
rs  
5
offset  
16  
00000  
6
5
Description  
If the contents of general-purpose register rs is greater than zero, then the program branches to the  
target address with a delay of one instruction (or two pipeline cycles). If the branch condition is true,  
the instruction in the branch delay slot is executed before the branch; otherwise, it is nullified. The  
target address is computed relative to the address of the instruction in the branch delay slot (PC+4);  
the 16-bit immediate offset is shifted left by two bits, sign-extended and added to PC+4 to form the  
target address.  
Exceptions  
None  
A-22  
Appendix A 32-Bit ISA Details  
BLEZ rs, offset  
Branch On Less Than Or Equal To Zero  
Operation  
if rs ≤ 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
BLEZ  
0
rs  
5
offset  
16  
000110  
00000  
6
5
Description  
If the contents of general-purpose register rs is less than or equal to zero, then the program branches  
to the target address with a delay of one instruction (or two pipeline cycles). The instruction in the  
branch delay slot is always executed, regardless of whether the branch is taken or not. The target  
address is computed relative to the address of the instruction in the branch delay slot (PC+4); the  
16-bit immediate offset is shifted left by two bits, sign-extended and added to PC+4 to form the  
target address.  
Exceptions  
None  
A-23  
Appendix A 32-Bit ISA Details  
BLEZL rs, offset  
Branch On Less Than Or Equal To Zero Likely  
Operation  
if rs ≤ 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
BLEZL  
010110  
0
rs  
5
offset  
16  
00000  
6
5
Description  
If the contents of general-purpose register rs is less than or equal to zero, then the program branches  
to the target address with a delay of one instruction (or two pipeline cycles). If the branch condition  
is true, the instruction in the branch delay slot is executed before the branch; otherwise, it is  
nullified. The target address is computed relative to the address of the instruction in the branch  
delay slot (PC+4); the 16-bit immediate offset is shifted left by two bits, sign-extended and added to  
PC+4 to form the target address.  
Exceptions  
None  
A-24  
Appendix A 32-Bit ISA Details  
BLTZ rs, offset  
Branch On Less Than Zero  
Operation  
if rs < 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
BLTZ  
rs  
5
offset  
16  
00000  
6
5
Description  
If the contents of general-purpose register rs is less than zero, then the program branches to the  
target address with a delay of one instruction (or two pipeline cycles). The instruction in the branch  
delay slot is always executed, regardless of whether the branch is taken or not. The target address is  
computed relative to the address of the instruction in the branch delay slot (PC+4); the 16-bit  
immediate offset is shifted left by two bits, sign-extended and added to PC+4 to form the target  
address.  
Exceptions  
None  
A-25  
Appendix A 32-Bit ISA Details  
BLTZAL rs, offset  
Branch On Less Than Zero And Link  
Operation  
r31 ⇐ pc +8; if rs < 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
BLTZAL  
10000  
rs  
5
offset  
16  
6
5
Description  
If the contents of general-purpose register rs is less than zero, then the program branches to the  
target address with a delay of one instruction (or two pipeline cycles). The instruction in the branch  
delay slot is always executed, regardless of whether the branch is taken or not. The target address is  
computed relative to the address of the instruction in the branch delay slot (PC+4); the 16-bit  
immediate offset is shifted left by two bits, sign-extended and added to PC+4 to form the target  
address. The address of the instruction following the branch delay slot (PC+8) is unconditionally  
saved in the link register, r31.  
General-purpose register rs may not be r31 because such an instruction is not restart able, with the  
contents of rs altered by the return address. An exception or interrupt could prevent the completion  
of a legal instruction in the branch delay slot. If that happens, after the exception handler routine has  
been executed, processing must restart with the branch instruction.  
Exceptions  
None  
A-26  
Appendix A 32-Bit ISA Details  
BLTZALL rs, offset  
Branch On Less Than Zero And Link Likely  
Operation  
r31 ⇐ pc +8; if rs < 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
BLTZALL  
10010  
rs  
5
offset  
16  
6
5
Description  
If the contents of general-purpose register rs is less than zero, then the program branches to the  
target address with a delay of one instruction (or two pipeline cycles), and saves the address of the  
instruction following the branch delay slot (PC+8) in the link register, r31. If the branch condition is  
true, the instruction in the branch delay slot is executed before the branch; otherwise, it is nullified.  
The target address is computed relative to the address of the instruction in the branch delay slot  
(PC+4); the 16-bit immediate offset is shifted left by two bits, sign-extended and added to PC+4 to  
form the target address.  
General-purpose register rs may not be r31 because such an instruction cannot be restarted, with the  
contents of rs altered by the return address. An exception or interrupt could prevent the completion  
of a legal instruction in the branch delay slot. If that happens, after the exception handler routine has  
been executed, processing must restart with the branch instruction.  
Exceptions  
None  
A-27  
Appendix A 32-Bit ISA Details  
BLTZL rs, offset  
Branch On Less Than Zero Likely  
Operation  
if rs < 0 then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
BLTZL  
00010  
rs  
5
offset  
16  
6
5
Description  
If the contents of general-purpose register rs is less than zero, then the program branches to the  
target address with a delay of one instruction (or two pipeline cycles). If the branch condition is true,  
the instruction in the branch delay slot is executed before the branch; otherwise, it is nullified. The  
target address is computed relative to the address of the instruction in the branch delay slot (PC+4);  
the 16-bit immediate offset is shifted left by two bits, sign-extended and added to PC+4 to form the  
target address.  
Exceptions  
None  
A-28  
Appendix A 32-Bit ISA Details  
BNE rs, rt, offset  
Branch On Not Equal  
Operation  
if rs ≠ rt then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
BNE  
rs  
5
rt  
5
offset  
16  
000101  
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt. If the two registers are not equal, then the program branches to the target address with a delay of  
one instruction (or two pipeline cycles). The instruction in the branch delay slot is always executed,  
regardless of whether the branch is taken or not. The target address is computed relative to the  
address of the instruction in the branch delay slot (PC+4); the 16-bit immediate offset is shifted left  
by two bits, sign-extended and added to PC+4 to form the target address.  
Exceptions  
None  
A-29  
Appendix A 32-Bit ISA Details  
BNEL rs, rt, offset  
Branch On Not Equal Likely  
Operation  
if rs ≠ rt then pc ⇐ pc + 4 + sign-extend(offset || 00)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
BNEL  
rs  
5
rt  
5
offset  
16  
010101  
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt. If the two registers are not equal, then the program branches to the target address with a delay of  
one instruction (or two pipeline cycles). If the branch condition is true, the instruction in the branch  
delay slot is executed before the branch; otherwise, it is nullified. The target address is computed  
relative to the address of the instruction in the branch delay slot (PC+4); the 16-bit immediate offset  
is shifted left by two bits, sign-extended and added to PC+4 to form the target address.  
Exceptions  
None  
A-30  
Appendix A 32-Bit ISA Details  
BREAK code  
Breakpoint  
Operation  
Breakpoint exception  
Instruction Encoding  
31  
26 25  
6 5  
0
SPECIAL  
000000  
BREAK  
001101  
code  
20  
6
6
Description  
When this instruction is executed, a Breakpoint exception occurs, immediately and unconditionally  
transferring control to the exception handler.  
The code field in the BREAK instruction is available for use as software parameters to pass  
additional information. The exception handler can retrieve it by loading the contents of the memory  
word containing the instruction. For more on this, see Section 9.1.11, Breakpoint Exception.  
Exceptions  
Breakpoint exception  
A-31  
Appendix A 32-Bit ISA Details  
CLO rd, rs  
Count Leading Ones in Word  
Operation  
rd ⇐ count_leading_ones rs  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL2  
011100  
0
CLO  
rs  
5
00000  
5
rd  
5
00000  
100001  
6
5
6
Description  
The contents of general-purpose register rs is scanned from bit 31 to bit 0, and the number of  
leading ones is written to general-purpose register rd. If all 32 bits in rs are set, the result written to  
rd is 32.  
Exceptions  
None  
Example  
Assume that register r2 contains 0xFE23_DE67. Then, the instruction:  
CLO  
r4, r2  
counts the number of leading ones in r2 and puts the result, 0x0000_0007, in r4.  
A-32  
Appendix A 32-Bit ISA Details  
CLZ rd, rs  
Count Leading Zeros in Word  
Operation  
rd ⇐ count_leading_zeros rs  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL2  
011100  
0
CLZ  
rs  
5
00000  
5
rd  
5
00000  
100000  
6
5
6
Description  
The contents of general-purpose register rs is scanned from bit 31 to bit 0, and the number of  
leading zeros is written to general-purpose register rd. If all 32 bits in rs are set, the result written to  
rd is 32.  
Exceptions  
None  
Example  
Assume that register r2 contains 0x07EF_45CD. Then, the instruction:  
CLZ  
r4, r2  
counts the number of leading zeros in r2 and puts the result, 0x0000_0005, in r4.  
A-33  
Appendix A 32-Bit ISA Details  
DERET  
Debug Exception Return  
Operation  
pc ⇐ DEPC, Debug[DM] ⇐ 0, Debug[IEXI] ⇐ 0  
Instruction Encoding  
31  
26 25 24  
6 5  
0
COP0  
CO  
1
0
DERET  
011111  
010000  
000 0000 0000 0000 0000  
6
1
19  
6
Description  
The DERET instruction is used to return control from a debug exception handler to a user program.  
This is accomplished by loading the contents of the DEPC register into the program counter (PC).  
See Section 9.3.6, Returning from Debug Exceptions, for details.  
The DERET instruction does not have a delay slot. It is executed with a delay of one instruction (or  
two pipeline cycles).  
The DERET instruction restores the ISA mode bit (bit 0) of the PC from bit 0 of the DEPC register,  
bringing the processor into the ISA mode that had been in effect before the debug exception was  
taken.  
The DERET instruction may not be in a jump or branch delay slot.  
The operation of the DERET instruction is unpredictable if the processor is not in Debug mode (i.e.,  
if the DM bit in the Debug register is cleared).  
Typically, the DEPC register automatically captures the address of the exception-causing instruction  
on a debug exception. If you want to use the MTC0 instruction to load the DEPC register with a  
return address, the debug exception handler must execute at least two instructions before issuing the  
DERET instruction.  
Exceptions  
None  
A-34  
Appendix A 32-Bit ISA Details  
DIV rs, rt  
Divide  
Operation  
LO ⇐ rs ÷ rt;  
HI ⇐ rs MOD rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
6 5  
0
SPECIAL  
000000  
0
DIV  
rs  
5
rt  
00 0000 0000  
10  
011010  
6
5
6
Description  
The contents of general-purpose register rs is divided by the contents of general-purpose register rt.  
Both operands are treated as signed integers. The quotient is placed into register LO and the  
remainder is placed into register HI. The DIV instruction never causes an Integer Overflow  
exception.  
The result of the DIV instruction is undefined if the divisor is zero. Typically, it is necessary to  
check for a zero divisor and an overflow condition after a DIV instruction.  
Any divide instruction is transferred to the dedicated divide unit as remaining instructions continue  
through the pipeline. The divide unit keeps running even when delay cycles and exceptions occur.  
If the DIV instruction is followed by an MFHI, MFLO, MADD, MADDU, MSUB or MSUBU  
instruction before the quotient and the remainder are available, the pipeline stalls until they do  
become available (see Section 5.4, Divide Instructions).  
Exceptions  
None  
A-35  
Appendix A 32-Bit ISA Details  
DIVU rs, rt  
Divide Unsigned  
Operation  
LO ⇐ rs ÷ rt;  
HI ⇐ rs MOD rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
6 5  
0
SPECIAL  
000000  
0
DIVU  
rs  
5
rt  
5
00 0000 0000  
011011  
6
10  
6
Description  
The contents of general-purpose register rs is divided by the contents of general-purpose register rt.  
The quotient is placed into register LO and the remainder is placed into register HI. The DIVU  
instruction never causes an Integer Overflow exception. The only difference between the DIV  
instruction and this instruction is that this instruction treats both operands as unsigned integers.  
Exceptions  
None  
A-36  
Appendix A 32-Bit ISA Details  
ERET  
Exception Return  
Operation  
if Status[ERL] = 1 then pc ⇐ ErrorEPC  
Status[ERL] ⇐ 0  
else pc ⇐ EPC  
Status[EXL] ⇐ 0  
SSCR[CSS] ⇐ SSCR[PSS]  
Instruction Encoding  
31  
26 25 24  
6 5  
0
COP0  
CO  
1
0
ERET  
010000  
000 0000 0000 0000 0000  
19  
011000  
6
1
6
Description  
ERET is an instruction for returning from an interrupt, exception or error trap.  
The ERET instruction does not have a delay slot. It is executed with a delay of one instruction (two  
pipeline cycles).  
The ERET instruction restores the ISA mode bit (bit 0) of the PC from bit 0 of the ErrorEPC  
register, bringing the processor into the ISA mode that had been in effect before the exception was  
taken.  
An attempt to execute the ERET instruction in User mode when the CU0 bit in the Status register is  
cleared causes a Coprocessor Unusable exception. If you want to use the MTC0 instruction to load  
the ErrorEPC or EPC register with a return address or if you have modified the contents of the  
Status register, the exception handler must execute at least two instructions before issuing the ERET  
instruction.  
If the ERL bit in the Status register is set, ERET restores the PC from the ErrorPC register and then  
clears the ERL bit. Otherwise, ERET restores the PC from the EPC register and then clears the EXL  
bit.  
Also, the PSS field in the SSCR register is popped to the CSS field.  
ERET must not be placed in a branch or jump delay slot.  
A-37  
Appendix A 32-Bit ISA Details  
Exceptions  
Coprocessor Unusable exception  
A-38  
Appendix A 32-Bit ISA Details  
J target  
Jump  
Operation  
pc ⇐ pc[31:28] || target || 00  
Instruction Encoding  
31  
26 25  
0
J
target  
26  
000010  
6
Description  
The program unconditionally jumps to the target address with a delay of one instruction (or two  
pipeline cycles). The target address is computed relative to the address of the instruction in the jump  
delay slot (PC+4). The 26-bit target is shifted left by two bits and combined with the four  
most-significant bits of PC+4 to form the target address.  
With the J instruction, the address of the target must be within a 228-byte segment. To jump to an  
arbitrary 32-bit address, load the desired address into a register and use the JR instruction (see  
Section 3.4.6, Jumping to 32-Bit Addresses).  
Exceptions  
None  
Example  
J SJUMP  
Assume that this jump instruction resides at address 0x2000 and that label SJUMP points to  
absolute address 0x2_4000. Then the assembler/linker turns this label into target operand 0x1_2000  
(see the figure below).  
The processor unconditionally transfers program control to address 0x2_4000. The jump takes  
effect after the instruction in the jump delay slot is executed.  
A-39  
Appendix A 32-Bit ISA Details  
0x2000  
0x2004  
J
SJUMP  
Jump Delay Slot  
0x0 (Four MSBs of the Delay Slot Address)  
+
0x002_4000  
The target operand, 0x1_2000,  
is shifted left by two bits.  
0x2_4000  
Jump Destination  
A-40  
Appendix A 32-Bit ISA Details  
JAL target  
Jump And Link  
Operation  
r31 ⇐ pc + 8; pc ⇐ pc[31:28] || target || 00  
Instruction Encoding  
31  
26 25  
0
JAL  
target  
26  
000011  
6
Description  
The program unconditionally jumps to the target address with a delay of one instruction (or two  
pipeline cycles). The target address is computed relative to the address of the instruction in the jump  
delay slot (PC+4). The 26-bit target is shifted left by two bits and combined with the four  
most-significant bits of PC+4 to form the target address. The JAL instruction never toggles the ISA  
mode bit of the program counter (PC).  
The address of the instruction after the jump delay slot (PC+8) is saved in the link register, r31 (ra).  
The least-significant bit of r31 stores the ISA mode bit that was in effect before the jump.  
With the JAL instruction, the address of the target must be within a 228-byte segment. To jump to an  
arbitrary 32-bit address, load the desired address into a register and use the JALR instruction (see  
Section 3.4.6, Jumping to 32-Bit Addresses).  
Exceptions  
None  
Example  
JAL PSUB  
Assume that this jump instruction resides at address 0x2000 and that label PSUB points to absolute  
address 0x2_4000. Then the assembler/linker turns this label into target operand 0x1_2000 (see the  
figure below).  
The processor unconditionally transfers program control to address 0x2_4000. The jump takes  
effect after the instruction in the jump delay slot is executed. The address of the instruction after the  
jump delay slot is saved in the link register, r31.  
A-41  
Appendix A 32-Bit ISA Details  
0x2000  
0x2004  
0x2008  
JAL PSUB  
MIPS32 ISA Mode  
Jump Delay Slot  
0x0 (Four MSBs of the Delay Slot Address)  
0000 0000 0000 0000 0010 0000 0000 100 0  
r31  
+
×
0x002_4000  
0
The target operand, 0x1_2000,  
is shifted left by two bits.  
MIPS32 ISA Mode  
0x2_4000  
Jump Destination  
MIPS32 ISA Mode  
A-42  
Appendix A 32-Bit ISA Details  
JALR (rd,) rs  
Jump And Link Register  
Operation  
rd or r31 ⇐ pc + 8; pc ⇐ rs  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
0
JALR  
rs  
5
rd  
5
00000  
00000  
001001  
6
5
5
6
Description  
The program unconditionally jumps to the address contained in general-purpose register rs, with the  
least-significant bit cleared, with a delay of one instruction (or two pipeline cycles). The  
least-significant bit of rs is interpreted as the ISA mode specifier. The address of the instruction after  
the jump delay slot (PC+8) is saved in general-purpose register rd. If rd is omitted, the default is r31  
(ra).  
Register specifies rd and rs must not be equal because such an instruction cannot be restarted, with  
the  
contents of rs altered by the return address. An exception or interrupt could prevent the completion  
of a legal instruction in the jump delay slot. If that happens, after the exception handler routine has  
been executed, processing must restart with the jump instruction.  
In 32-bit ISA mode, all instructions must be aligned on word boundaries. Therefore, when jumping  
to a 32-bit routine, the two low-order bits of the target register (rs) must be zero. If the two low-order  
bits are not zero, an Address Error exception will occur when the processor fetches the instruction at  
the jump destination.  
Exceptions  
None  
Example  
Assume that register r2 contains 0x0012_3457 and that the following jump instruction resides at  
address 0x0000_2000. Then, executing the instruction:  
JALR r2  
transfers program control to address 0x0012_3456, with the least-significant bit of 0x0012_3457  
A-43  
Appendix A 32-Bit ISA Details  
cleared. The jump takes effect after the instruction in the jump delay slot is executed. Since register  
r2 has the least-significant bit set to 1, the ISA mode bit toggles to 1 after the jump, bringing the  
processor into 16-bit ISA mode. The return address, 0x0000_2008, is saved in the link register, r31,  
combined with the ISA mode bit.  
0x2000  
JALR  
r2  
0x2004  
0x2008  
MIPS32 ISA Mode  
Jump Delay Slot  
0000 0000 0000 0000 0010 0000 0000 100 0  
r31  
0x12_3456  
Jump Destination  
×
MIPS16 ISA Mode  
0
MIPS32 ISA Mode  
A-44  
Appendix A 32-Bit ISA Details  
JALX target  
Jump And Link eXchange  
Operation  
r31 ⇐ pc + 8; pc[31:1] ⇐ pc[31:28] || target || 00; pc[0] ⇐ NOT pc[0]  
Instruction Encoding  
31  
26 25  
0
JALX  
target  
26  
011101  
6
Description  
The program unconditionally jumps to the target address with a delay of one instruction (or two  
pipeline cycles). The target address is computed relative to the address of the instruction in the jump  
delay slot (PC+4). The 26-bit target is shifted left by two bits and combined with the four  
most-significant bits of PC+4 to form the target address. The JALX instruction unconditionally  
toggles the ISA mode bit of the program counter (PC).  
The address of the instruction after the jump delay slot (PC+8) is saved in the link register, r31 (ra).  
The least-significant bit of r31 stores the ISA mode bit that was in effect before the jump.  
Exceptions  
None  
Example  
JALX PSUB  
Assume that this jump instruction resides at address 0x0000_2000 and that label PSUB points to  
absolute address 0x2_4000. Then, the assembler/linker turns this label into target operand 0x1_2000  
(see the figure below).  
The processor unconditionally transfers program control to address 0x2_4000. The jump takes  
effect after the instruction in the jump delay slot is executed. The ISA mode bit unconditionally  
toggles, bringing the processor into 16-bit ISA mode. The return address, 0x0000_2008, is saved in  
the link register, r31, combined with the ISA mode bit.  
A-45  
Appendix A 32-Bit ISA Details  
0x2000  
0x2004  
0x2008  
JALX PSUB  
MIPS32 ISA Mode  
Jump Delay Slot  
0x0 (Four MSBs of the Delay Slot Address)  
0000 0000 0000 0000 0010 0000 0000 100 0  
r31  
+
×
0x002_4000  
0
The target operand, 0x1_2000,  
is shifted left by two bits.  
MIPS32 ISA Mode  
0x2_4000  
Jump Destination  
MIPS16 ISA Mode  
A-46  
Appendix A 32-Bit ISA Details  
JR rs  
Jump Register  
Operation  
pc ⇐ rs  
Instruction Encoding  
31  
26 25  
21 20  
6 5  
0
SPECIAL  
000000  
0
JR  
rs  
5
000 0000 000 0000  
15  
001000  
6
6
Description  
The program unconditionally jumps to the address contained in general-purpose register rs, with the  
least-significant bit cleared, with a delay of one instruction (or two pipeline cycles). The  
least-significant bit of rs is interpreted as the ISA mode specifier.  
In 32-bit ISA mode, all instructions must be aligned on word boundaries. Therefore, when jumping  
to a 32-bit routine, the two low-order bits of the target register (rs) must be zero. If the two low-order  
bits are not zero, an Address Error exception will occur when the processor fetches the  
instruction at the jump destination.  
Exceptions  
None  
Example  
In the following example, the JALR instruction in a 16-bit routine transfers control to a 32-bit  
routine. At the end of the 32-bit routine, the JR instruction restores the return address into the  
program counter (PC) from the link register, r31 (ra). Since the JALR instruction saves the ISA  
mode specifier in the least-significant bit of ra, executing the JR instruction at the end of the 32-bit  
routine restores it into the PC, causing the processor to revert to 16-bit ISA mode.  
A-47  
Appendix A 32-Bit ISA Details  
0x2000  
0x2004  
0x2008  
JALR  
ra, r2  
MIPS16 ISA Mode  
Jump Delay Slot  
Return Point  
Jump to a 32-bit  
routine through the  
JALR instruction  
Return to the 16-bit  
routine through the  
JR instruction  
0000 0000 0000 0000 0010 0000 0000 100 1  
ra  
×
1
MIPS16 ISA Mode  
0x12_3458  
Jump Destination  
MIPS32 ISA Mode  
JR ra  
A-48  
Appendix A 32-Bit ISA Details  
LB rt, offset (base)  
Load Byte  
Operation  
rt ⇐ {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
LB  
base  
5
rt  
5
offset  
16  
100000  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The byte in memory addressed by EA is sign-extended and  
loaded into general-purpose register rt.  
Exceptions  
Address Error exception  
Example  
Assume that register r8 contains 0x0000_0400 and that the memory location at address 0x404  
contains 0xF2. Then, executing the instruction:  
LB r9,4(r8)  
loads register r9 with 0xFFFF_FFF2.  
Memory  
Byte  
0x0000 0400  
0x400  
0x401  
0x402  
0x403  
0x404  
r8  
+4  
11110010  
Memory  
1 Byte  
Ø
CPU  
Register  
Sign-Extended  
Load (Sign-Extend)  
r9  
0xFFFF FFF2  
A-49  
Appendix A 32-Bit ISA Details  
LBU rt, offset (base)  
Load Byte Unsigned  
Operation  
rt ⇐ {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
LBU  
base  
5
rt  
5
offset  
16  
100100  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The byte in memory addressed by EA is zero-extended and  
loaded into general-purpose register rt.  
Exceptions  
Address Error exception  
Example  
Assume that register r8 contains 0x0000_0400 and that the memory location at address 0x404  
contains 0xF2. Then, executing the instruction:  
LBU r9,4(r8)  
loads register r9 with 0x0000_00F2.  
Memory  
Byte  
0x0000 0400  
r8  
0x400  
0x401  
+4 0x402  
0x403  
11110010  
Memory  
0x404  
1 Byte  
Ø
CPU  
Register  
Zero-Extended  
Load (Zero-Extend)  
r9  
0x0000 00F2  
A-50  
Appendix A 32-Bit ISA Details  
LH rt, offset (base)  
Load Halfword  
Operation  
rt ⇐ {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
LH  
base  
5
rt  
5
offset  
16  
100001  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The halfword in memory addressed by EA is sign-extended  
and loaded into general-purpose register rt.  
If the least-significant bit of the effective address is not zero (i.e., the effective address is not on a  
halfword boundary), an Address Error exception occurs.  
Exceptions  
Address Error exception  
Example  
Assume that register r8 contains 0x0000_0400 and that the memory locations at addresses 0x404  
and 0x405 contain 0xFF and 0x02 respectively. Then, executing the instruction:  
LH r9,4(r8)  
loads register r9 with 0xFFFF_FF02 in big-endian mode and with 0x0000_02FF in little-endian  
mode.  
Executing the instruction:  
LH r9,3(r8)  
causes an Address Error exception since 0x403 is not on a halfword boundary.  
A-51  
Appendix A 32-Bit ISA Details  
Memory  
Byte  
Halfword Boundary  
Halfword Boundary  
0x0000 0400  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
r8  
+4  
Halfword Boundary  
Memory  
11111111  
00000010  
Halfword  
r9  
r9  
0xFFFF FF02  
Big-Endian  
Load (Sign-Extend)  
Ø
CPU  
Register  
Sign-Extended  
0x0000 02FF  
Little-Endian  
A-52  
Appendix A 32-Bit ISA Details  
LHU rt, offset (base)  
Load Halfword Unsigned  
Operation  
rt ⇐ {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
LHU  
base  
5
rt  
5
offset  
16  
100101  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The halfword in memory addressed by EA is zero-extended  
and loaded into general-purpose register rt.  
If the least-significant bit of the effective address is not zero (i.e., the effective address is not on a  
halfword boundary), an Address Error exception occurs.  
Exceptions  
Address Error exception  
Example  
Assume that register r8 contains 0x0000_0400 and that the memory locations at addresses 0x404  
and 0x405 contain 0xFF and 0x02 respectively. Then, executing the instruction:  
LHU r9,4(r8)  
loads register r9 with 0x0000_FF02 in big-endian mode and with 0x0000_02FF in little-endian  
mode.  
Executing the instruction:  
LH r9,3(r8)  
causes an Address Error exception since 0x403 is not on a halfword boundary.  
A-53  
Appendix A 32-Bit ISA Details  
Memory  
Byte  
Halfword Boundary  
0x0000 0400  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
r8  
Halfword Boundary  
Halfword Boundary  
Memory  
+4  
11111111  
00000010  
Halfword  
r9  
r9  
0x0000 FF02  
Big-Endian  
Load (Zero-Extend)  
Ø
CPU  
Register  
Zero-Extended  
0x0000 02FF  
Little-Endian  
A-54  
Appendix A 32-Bit ISA Details  
LUI rt, immediate  
Load Upper Immediate  
Operation  
rt ⇐ immediate || 0x0000  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
LUI  
0
rt  
5
immediate  
16  
001111  
00000  
6
5
Description  
The 16-bit immediate is shifted left by 16 bits and concatenated to 16 bits of zeros. The result is  
placed into general-purpose register rt.  
Exceptions  
None  
Example  
The instruction:  
LUI r9,0x1234  
loads register r9 with 0x1234_0000.  
A-55  
Appendix A 32-Bit ISA Details  
LW rt, offset (base)  
Load Word  
Operation  
rt ⇐ {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
LW  
base  
5
rt  
5
offset  
16  
100011  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The word in memory addressed by EA is loaded into  
general-purpose register rt.  
If the two low-order bits of the effective address is not zero (i.e., the effective address is not on a  
word boundary), an Address Error exception occurs.  
Exceptions  
Address Error exception  
Example  
Assume that register r8 contains 0x0000_0400 and that the memory locations at addresses 0x404 to  
0x407 contain 0x01, 0x23, 0x45 and 0x67 respectively. Then, executing the instruction:  
LW r9,4(r8)  
loads register r9 with 0x0123_4567 in big-endian mode and with 0x6745_2301 in little-endian  
mode.  
Executing the instruction:  
LW r9,5(r8)  
causes an Address Error exception since 0x405 is not on a word boundary.  
A-56  
Appendix A 32-Bit ISA Details  
Memory  
Byte  
Word Boundary  
0x0000 0400  
0x400  
0x401  
0x402  
0x403  
r8  
+4  
Word Boundary  
0x01  
0x23  
0x45  
0x67  
0x404  
0x405  
0x406  
0x407  
r9  
r9  
0x0123 4567  
Big-Endian  
Load  
0x6745 2301  
Little-Endian  
A-57  
Appendix A 32-Bit ISA Details  
LWL rt, offset (base)  
Load Word Left  
Operation  
rt ⇐ rt MERGE {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
LWL  
base  
5
rt  
5
offset  
16  
100010  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The appropriate high-order part of the word in memory  
addressed by EA that crosses a natural word boundary is loaded into the left portion of general  
purpose register rt.  
No Address Error exception occurs due to misalignment.  
An immediately preceding load instruction and the following LWL instruction can specify the same  
general-purpose register as rt. The contents of general-purpose register rt is internally bypassed (or  
forwarded) within the processor so that no NOP instruction is needed between the two instructions.  
The LWL and LWR instructions are used in combination to load a misaligned word from memory  
into a general-purpose register.  
Exceptions  
Address Error exception  
Example  
Assume that register r8 contains 0x0000_0400 and that the memory locations at addresses 0x402 to  
0x405 contains 0x01, 0x23, 0x45 and 0x67 respectively.  
A-58  
Appendix A 32-Bit ISA Details  
Byte  
0x0000 0400  
r8  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
+2  
+5  
0x01  
0x23  
0x45  
0x67  
Word Boundary  
• Big-endian mode  
The instruction:  
LWL r9,2(r8)  
starts at address 0x402 and loads that byte into the leftmost byte of register r9. Then it loads  
bytes from memory to r9, going in the higher-address direction, until it reaches a word  
boundary in memory. The operation of this LWL instruction is as follows.  
r9  
r9  
AA BB CC DD  
Before  
01 23 CC DD  
After  
(a) Big-Endian  
• Little-endian mode  
The instruction:  
LWL r9,5(r8)  
starts at address 0x405 and loads that byte into the leftmost byte of register r9. Then it loads  
bytes from memory to r9, going in the lower-address direction, until it reaches a word  
boundary in memory. The operation of this LWL instruction is as follows.  
r9  
r9  
AA BB CC DD  
Before  
67 45 CC DD  
After  
(b) Little-Endian  
A-59  
Appendix A 32-Bit ISA Details  
LWR rt, offset (base)  
Load Word Right  
Operation  
rt ⇐ rt MERGE {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
LWR  
base  
5
rt  
5
offset  
16  
100110  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The appropriate low-order part of the word in memory  
addressed by EA that crosses a natural word boundary is loaded into the right portion of general  
purpose register rt.  
No Address Error exception occurs due to misalignment.  
An immediately preceding load instruction and the following LWR instruction can specify the same  
general-purpose register as rt. The contents of general-purpose register rt is internally bypassed (or  
forwarded) within the processor so that no NOP instruction is needed between the two instructions.  
The LWL and LWR instructions are used in combination to load a misaligned word from memory  
into a general-purpose register.  
Exceptions  
Address Error exception  
Example  
Assume that register r8 contains 0x0000_0400 and that the memory locations at addresses 0x402 to  
0x405 contains 0x01, 0x23, 0x45 and 0x67 respectively.  
A-60  
Appendix A 32-Bit ISA Details  
Byte  
0x0000 0400  
r8  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
+2  
+5  
0x01  
0x23  
0x45  
0x67  
Word Boundary  
• Big-endian mode  
The instruction:  
LWR r9,5(r8)  
starts at address 0x405 and loads that byte into the rightmost byte of register r9. Then it loads  
bytes from memory to r9, going in the lower-address direction, until it reaches a word boundary in  
memory. The operation of this LWR instruction is as follows.  
r9  
r9  
01 23 CC DD  
Before  
01 23 45 67  
After  
(a) Big-Endian  
• Little-endian mode  
The instruction:  
LWR r9,2(r8)  
starts at address 0x402 and loads that byte into the rightmost byte of register r9. Then it loads  
bytes from memory to r9, going in the higher-address direction, until it reaches a word boundary in  
memory. The operation of this LWR instruction is as follows.  
r9  
r9  
67 45 CC DD  
Before  
67 45 23 01  
After  
(b) Little-Endian  
A-61  
Appendix A 32-Bit ISA Details  
MADD (rd,) rs, rt  
Multiply and Add  
Operation  
HI ⇐ high-order word of (HI || LO) + (rs ⋅ rt);  
LO ⇐ low-order word of (HI || LO) + (rs ⋅ rt);  
rd ⇐ low-order word of (HI || LO) + (rs ⋅ rt)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL2  
011100  
0
MADD  
rs  
5
rt  
5
rd  
5
00000  
000000  
6
5
6
Description  
The contents of general-purpose register rs is multiplied by the contents of general-purpose register  
rt, and then the product is added to the 64-bit, doubleword contents of the HI and LO registers. Both  
rs and rt are treated as signed integers. The high-order word of the result is placed into the HI  
register, and the low-order word of the result is placed into the LO register. If destination register rd  
is specified, the low-order word of the result is also copied into rd.  
If rd is omitted, the default is r0; thus the low-order word of the result is not copied into a  
general-purpose register.  
This instruction never causes an Integer Overflow exception.  
Exceptions  
None  
Example  
Assume that the HI and LO registers contain 0x0000_0000 and 0xFFFF_FFFF respectively and that  
general-purpose registers r2 and r3 contain 0x0123_4567 and 0x89AB_CDEF respectively. Then,  
the instruction:  
MADD r4,r2,r3  
evaluates:  
0x0000_0000_FFFF_FFFF + (0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0x0000_0000_FFFF_FFFF + 0xFF79_5E36_C94E_4629  
= 0xFF79_5E37_C94E_4628  
Hence, the high-order word of the result, 0xFF79_5E37, is placed into the HI register, and the  
A-62  
Appendix A 32-Bit ISA Details  
low-order word of the result, 0xC94E_4628, is placed into the LO and r4 registers.  
A-63  
Appendix A 32-Bit ISA Details  
MADDU (rd,) rs, rt  
Multiply and Add Unsigned  
Operation  
HI ⇐ (HI || LO) + (rs × rt) の上位ワード  
LO ⇐ (HI || LO) + (rs × rt) の下位ワード  
rd ⇐ (HI || LO) + (rs × rt) の下位ワード  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL2  
011100  
0
MADDU  
000001  
rs  
5
rt  
5
rd  
5
00000  
6
5
6
Description  
The contents of general-purpose register rs is multiplied by the contents of general-purpose register  
rt, and then the product is added to the 64-bit, doubleword contents of the HI and LO registers. Both  
rs and rt are treated as unsigned integers. The high-order word of the result is placed into the HI  
register, and the low-order word of the result is placed into the LO register. If destination register rd  
is specified, the low-order word of the result is also copied into rd.  
If rd is omitted, the default is r0; thus the low-order word of the result is not copied into a  
general-purpose register.  
This instruction never causes an Integer Overflow exception.  
Exceptions  
None  
Example  
Assume that the HI and LO registers contain 0x_0000_0000 and 0xFFFF_FFFF respectively and  
that general-purpose registers r2 and r3 contain 0x0123_4567 and 0x89AB_CDEF respectively.  
Then, the instruction:  
MADDU r4,r2,r3  
evaluates:  
0x0000_0000_FFFF_FFFF + (0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0x0000_0000_FFFF_FFFF + 0x009C_A39D_C94E_4629  
= 0x009C_A39E_C94E_4628  
Hence, the high-order word of the result, 0x009C_A39E, is placed into the HI register, and the  
A-64  
Appendix A 32-Bit ISA Details  
low-order word of the result, 0xC94E_4628, is placed into the LO and r4 registers.  
A-65  
Appendix A 32-Bit ISA Details  
MFC0 rt, rd  
Move From Coprocessor 0  
Operation  
rt ⇐ coprocessor register rd of CP0  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
3 2  
0
COP0  
MF  
0
rt  
5
rd  
5
sel  
3
010000  
00000  
0000 0000  
6
5
8
Description  
The contents of CP0 register rd is loaded into general-purpose register rt.  
Exceptions  
Coprocessor Unusable exception  
A-66  
Appendix A 32-Bit ISA Details  
MFHI rd  
Move From HI  
Operation  
rd ⇐ HI  
Instruction Encoding  
31  
26 25  
21 20  
0
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
MFHI  
rd  
00 0000 0000  
10  
00000  
010000  
6
5
5
6
Description  
The contents of HI register is loaded into general-purpose register rd.  
Exceptions  
None  
A-67  
Appendix A 32-Bit ISA Details  
MFLO rd  
Move From LO  
Operation  
rd ⇐ LO  
Instruction Encoding  
31  
26 25  
21 20  
0
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
MFLO  
rd  
00 0000 0000  
10  
00000  
010010  
6
5
5
6
Description  
The contents of the LO register is loaded into general-purpose register rd.  
Exceptions  
None  
A-68  
Appendix A 32-Bit ISA Details  
MOVN rd, rs, rt  
Move Conditional on Not Zero  
Operation  
if rt ≠0 then rd ⇐ rs  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
MOVN  
001011  
rs  
5
rt  
5
rd  
5
00000  
6
5
6
Description  
If the contents of general-purpose register rt is not equal to zero, the contents of general-purpose  
register rs is loaded into general-purpose register rd.  
Exceptions  
None  
A-69  
Appendix A 32-Bit ISA Details  
MOVZ rd, rs, rt  
Move Conditional on Zero  
Operation  
if rt = 0 then rd ⇐ rs  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
MOVZ  
rs  
5
rt  
5
rd  
5
00000  
001010  
6
5
6
Description  
If the contents of general-purpose register rt is equal to zero, the contents of general-purpose  
register rs is loaded into general-purpose register rd.  
Exceptions  
None  
A-70  
Appendix A 32-Bit ISA Details  
MSUB (rd), rs, rt  
Multiply and Subtract  
Operation  
HI ⇐ high-order word of (HI || LO) – (rs ⋅ rt)  
LO ⇐ low-order word of (HI || LO) – (rs ⋅ rt)  
rd ⇐ low-order word of (HI || LO) – (rs ⋅ rt)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL2  
011100  
0
MSUB  
rs  
5
rt  
5
rd  
5
00000  
000100  
6
5
6
Description  
The contents of general-purpose register rs is multiplied by the contents of general-purpose register  
rt, and then the product is subtracted from the 64-bit, doubleword contents of the HI and LO  
registers. Both rs and rt are treated as signed integers. The high-order word of the result is placed  
into the HI register, and the low-order word of the result is placed into the LO register. If destination  
register rd is specified, the low-order word of the result is also copied into rd.  
If rd is omitted, the default is r0; thus the low-order word of the result is not copied into a  
general-purpose register.  
This instruction never causes an Integer Overflow exception.  
Exceptions  
None  
Example  
Assume that the HI and LO registers contain 0xFF79_5E37 and 0xC94E_4628 respectively and that  
general-purpose registers r2 and r3 contain 0x0123_4567 and 0x89AB_CDEF respectively. Then,  
the instruction:  
MSUB r2,r3  
evaluates:  
0xFF79_5E37_C94E_4628 – (0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0xFF79_5E37_C94E_4628 – 0xFF79_5E36_C94E_4629  
= 0x0000_0000_FFFF_FFFF  
A-71  
Appendix A 32-Bit ISA Details  
Hence, the high-order word of the result, 0x0000_0000, is placed into the HI register, and the  
low-order word of the result, 0xFFFF_FFFF, is placed into the LO register.  
A-72  
Appendix A 32-Bit ISA Details  
MSUBU (rd), rs, rt  
Multiply and Subtract Unsigned  
Operation  
HI ⇐ high-order word of (HI || LO) – (rs ⋅ rt)  
LO ⇐ low-order word of (HI || LO) – (rs ⋅ rt)  
rd ⇐ low-order word of (HI || LO) – (rs ⋅ rt)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL2  
011100  
0
MSUBU  
000101  
rs  
5
rt  
5
rd  
5
00000  
6
5
6
Description  
The contents of general-purpose register rs is multiplied by the contents of general-purpose register  
rt, and then the product is subtracted from the 64-bit, doubleword contents of the HI and LO  
registers. Both rs and rt are treated as unsigned integers. The high-order word of the result is placed  
into the HI register, and the low-order word of the result is placed into the LO register. If destination  
register rd is specified, the low-order word of the result is also copied into rd.  
If rd is omitted, the default is r0; thus the low-order word of the result is not copied into a  
general-purpose register.  
This instruction never causes an Integer Overflow exception.  
Exceptions  
None  
Example  
Assume that the HI and LO registers contain 0x009C_A39E and 0xC94E_4628 respectively and  
that general-purpose registers r2 and r3 contain 0x0123_4567 and 0x89AB_CDEF respectively.  
Then, the instruction:  
MSUBU r2,r3  
evaluates:  
0x009C_A39E_C94E_4628 – (0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0x009C_A39E_C94E_4628 – 0x009C_A39D_C94E_4629  
= 0x0000_0000_FFFF_FFFF  
A-73  
Appendix A 32-Bit ISA Details  
Hence, the high-order word of the result, 0x0000_0000, is placed into the HI register, and the  
low-order word of the result, 0xFFFF_FFFF, is placed into the LO register.  
A-74  
Appendix A 32-Bit ISA Details  
MTC0 rt, rd  
Move To Coprocessor 0  
Operation  
Coprocessor register rd of CP0 ⇐ rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
3 2  
0
COP0  
MT  
0
rt  
5
rd  
5
sel  
3
010000  
00100  
0000 0000  
6
5
8
Description  
The contents of general-purpose register rt is loaded into CP0 register rd.  
Once the MTC0 instruction writes to the Status, EPC or ErrorEPC register, at least two instructions  
must be executed before the ERET instruction. Otherwise, the operation is undefined.  
Likewise, once the MTC0 instruction writes to the DEPC register, at least two instructions must be  
executed before the DERET instruction. Otherwise, the operation is undefined.  
Because this instruction may alter the state of the virtual address translation system, the operation of  
load and store instructions immediately before and after this instruction is undefined.  
The MTC0 instruction that modifies the contents of the SSCR register must be followed by two  
NOPs.  
Exceptions  
Coprocessor Unusable exception  
A-75  
Appendix A 32-Bit ISA Details  
MTHI rs  
Move To HI  
Operation  
HI ⇐ rs  
Instruction Encoding  
31  
26 25  
21 20  
6 5  
0
SPECIAL  
000000  
0
MTHI  
rs  
5
000 0000 0000 0000  
15  
010001  
6
6
Description  
The contents of general-purpose register rs is loaded into the HI register.  
Exceptions  
None  
A-76  
Appendix A 32-Bit ISA Details  
MTLO rs  
Move To LO  
Operation  
LO ⇐ rs  
Instruction Encoding  
31  
26 25  
21 20  
6 5  
0
SPECIAL  
000000  
0
MTLO  
rs  
5
000 0000 0000 0000  
15  
010011  
6
6
Description  
The contents of general-purpose register rs is loaded into the LO register.  
Exceptions  
None  
A-77  
Appendix A 32-Bit ISA Details  
MUL rd, rs, rt  
Multiply  
Operation  
rd ⇐ low-order word of (rs ⋅ rt)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL2  
011100  
0
MUL  
rs  
5
rt  
5
rd  
5
00000  
000010  
6
5
6
Description  
The contents of general-purpose register rs is multiplied by the contents of general-purpose register  
rt. Both rs and rt are treated as signed integers. The low-order word of the result is placed into  
general-purpose register rd. The contents of the HI and LO registers become undefined.  
This instruction never causes an Integer Overflow exception.  
Exceptions  
None  
Example  
Assume that general-purpose registers r2 and r3 contain 0x0123_4567 and 0x89AB_CDEF  
respectively. Then, the instruction:  
MUL r4,r2,r3  
evaluates:  
(0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0xFF79_5E36_C94E_4629  
Hence, the low-order word of the result, 0xC94E_4629, is placed into the r4 register.  
A-78  
Appendix A 32-Bit ISA Details  
MULT (rd,) rs, rt  
Multiply  
Operation  
HI ⇐ high-order word of (rs ⋅ rt);  
LO ⇐ low-order word of (rs ⋅ rt);  
rd ⇐ low-order word of (rs ⋅ rt)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
MULT  
rs  
5
rt  
5
rd  
5
00000  
011000  
6
5
6
Description  
The contents of general-purpose register rs is multiplied by the contents of general-purpose register  
rt. Both rs and rt are treated as signed integers. The high-order word of the result is placed into the  
HI register, and the low-order word of the result is placed into the LO register. If destination register  
rd is specified, the low-order word of the result is also copied into rd.  
If rd is omitted, the default is r0; thus the low-order word of the result is not copied into a  
general-purpose register.  
This instruction never causes an Integer Overflow exception.  
Exceptions  
None  
Example  
Assume that general-purpose registers r2 and r3 contain 0x0123_4567 and 0x89AB_CDEF  
respectively. Then, the instruction:  
MULT r4,r2,r3  
evaluates:  
(0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0xFF79_5E36_C94E_4629  
Hence, the high-order word of the result, 0xFF79_5E36, is placed into the HI register, and the  
low-order word of the result, 0xC94E_4629, is placed into the LO and r4 registers.  
A-79  
Appendix A 32-Bit ISA Details  
MULTU (rd,) rs, rt  
Multiply Unsigned  
Operation  
HI ⇐ high-order word of (rs ⋅ rt);  
LO ⇐ low-order word of (rs ⋅ rt);  
rd ⇐ low-order word of (rs ⋅ rt)  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
MULTU  
011001  
rs  
5
rt  
5
rd  
5
00000  
6
5
6
Description  
The contents of general-purpose register rs is multiplied by the contents of general-purpose register  
rt. Both rs and rt are treated as unsigned integers. The high-order word of the result is placed into  
the HI register, and the low-order word of the result is placed into the LO register. If destination  
register rd is specified, the low-order word of the result is also copied into rd.  
If rd is omitted, the default is r0; thus the low-order word of the result is not copied into a  
general-purpose register.  
This instruction never causes an Integer Overflow exception.  
Exceptions  
None  
Example  
Assume that general-purpose registers r2 and r3 contain 0x0123_4567 and 0x89AB_CDEF  
respectively. Then, the instruction:  
MULTU r4,r2,r3  
(0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0x009C_A39D_C94E_4629  
Hence, the high-order word of the result, 0x009C_A39D, is placed into the HI register, and the  
low-order word of the result, 0xC94E_4629, is placed into the LO and r4 registers.  
A-80  
Appendix A 32-Bit ISA Details  
NOR rd, rs, rt  
NOR  
Operation  
rd ⇐ rs NOR rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
NOR  
rs  
5
rt  
5
rd  
5
00000  
100111  
6
5
6
Description  
The contents of general-purpose register rs is NORed with the contents of general-purpose register  
rt, and the result is placed into general-purpose register rd.  
Exceptions  
None  
Example  
Assume that registers r2 and r3 contain 0x8000_7350 and 0x0000_3456 respectively. Then, the  
instruction:  
NOR r4,r2,r3  
performs the logical NOR between r2 and r3 and puts the result (0x7FFF_88A9) in r4, as shown  
below.  
1000 0000 0000 0000 0111 0011 0101 0000  
r2  
NOR  
0000 0000 0000 0000 0011 0100 0101 0110  
r3  
0111 1111 1111 1111 1000 1000 1010 1001  
r4  
A-81  
Appendix A 32-Bit ISA Details  
OR rd, rs, rt  
OR  
Operation  
rd ⇐ rs OR rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
CR  
rs  
5
rt  
5
rd  
5
00000  
100101  
6
5
6
Description  
The contents of general-purpose register rs is ORed with the contents of general-purpose register rt,  
and the result is placed into general-purpose register rd.  
Exceptions  
None  
Example  
Assume that registers r2 and r3 contain 0x8000_7350 and 0x0000_3456 respectively. Then, the  
instruction:  
OR r4,r2,r3  
performs the logical OR between r2 and r3 and puts the result (0x8000_7756) in r4, as shown  
below.  
1000 0000 0000 0000 0111 0011 0101 0000  
r2  
OR  
0000 0000 0000 0000 0011 0100 0101 0110  
r3  
1000 0000 0000 0000 0111 0111 0101 0110  
r4  
A-82  
Appendix A 32-Bit ISA Details  
ORI rt, rs, immediate  
OR Immediate  
Operation  
rt ⇐ rs OR (016 || immediate15..0  
)
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
ORI  
rs  
5
rt  
5
immediate  
16  
001101  
6
Description  
The 16-bit immediate is zero-extended and ORed with the contents of general-purpose register rs.  
The result is placed into general-purpose register rt.  
The immediate field is 16 bits in length. If the immediate size is larger than that, you need to put it  
in a general-purpose register and use the OR instruction (see Section 3.3.2, 32-Bit Constants).  
Exceptions  
None  
Example  
Assume that register r2 contains 0x0000_7350. Then, the instruction:  
ORI r3,r2,0x1234  
performs the logical OR between 0x0000_7350 and 0x0000_1234 and puts the result  
(0x0000_7374) in r3, as shown below.  
0000 0000 0000 0000 0111 0011 0101 0000  
r2  
r3  
OR  
0000 0000 0000 0000 0001 0010 0011 0100  
Zero-Extended  
0000 0000 0000 0000 0111 0011 0111 0100  
A-83  
Appendix A 32-Bit ISA Details  
SB rt, offset (base)  
Store Byte  
Operation  
rt ⇒ {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
SB  
base  
5
rt  
5
offset  
16  
101000  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The least-significant byte in general-purpose register rt is  
stored at the memory location addressed by EA.  
The three high-order bytes in rt are simply ignored; so there is no distinction between signed and  
unsigned stores.  
Exceptions  
Address Error exception  
Example  
Assume that registers r8 and r9 contain 0x0000_0400 and 0x0123_4567 respectively. Then,  
executing the instruction:  
SB r9,4(r8)  
stores 0x67 to the memory location at address 0x404.  
Memory  
Byte  
0x0000 0400  
0x400  
0x401  
0x402  
0x403  
0x404  
r8  
+4  
0x67  
Store  
CPU  
Register  
Ø
Memory  
1 Byte  
r9  
0x0123 4567  
A-84  
Appendix A 32-Bit ISA Details  
EJTAG  
SDBBP code  
Software Debug Breakpoint Exception  
Operation  
Software debug breakpoint exception  
Instruction Encoding  
31  
26 25  
6 5  
0
SPECIAL2  
011100  
SDBBP  
111111  
code  
20  
6
6
Description  
A debug breakpoint occurs, immediately and unconditionally transferring control to the exception  
handler.  
The code field in the SDBBP instruction is available for use as software parameters to pass  
additional information. The exception handler can retrieve it by loading the contents of the memory  
word containing the instruction. See Section 9.3, Debug Exceptions, for details.  
The SDBBP instruction may not be used within the user’s program; it is intended for use by  
development tools. Executing the SDBBP instruction on a device without EJTAG causes a  
Reserved Instruction exception.  
Exceptions  
Debug Breakpoint exception  
Reserved Instruction exception  
A-85  
Appendix A 32-Bit ISA Details  
SH rt, offset (base)  
Store Halfword  
Operation  
rt ⇒ {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
SH  
base  
5
rt  
5
offset  
16  
101001  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The least-significant halfword in general-purpose register rt  
is stored at the memory location addressed by EA.  
The higher-order halfword in rt is simply ignored; so there is no distinction between signed and  
unsigned stores.  
If the least-significant bit of the effective address is not zero (i.e., the effective address is not on a  
halfword boundary), an Address Error exception occurs.  
Exceptions  
Address Error exception  
Example  
Assume that registers r8 and r9 contain 0x0000_0400 and 0x0123_4567 respectively. In big-endian  
mode, executing the instruction:  
SH r9,4(r8)  
stores 0x45 and 0x67 to the memory locations at addresses 0x404 and 0x405 respectively. In  
little-endian mode, this instruction stores 0x67 and 0x45 to the memory locations at addresses 0x404  
and 0x405 respectively.  
Executing the instruction:  
SH r9,3(r8)  
causes an Address Error exception since 0x403 is not on a halfword boundary.  
A-86  
Appendix A 32-Bit ISA Details  
Memory  
Byte  
Byte  
Halfword Boundary  
Halfword Boundary  
Halfword Boundary  
0x0000 0400  
r8  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
+4  
0x45  
0x67  
0x67  
0x45  
Big-Endian  
Little-Endian  
r9  
0x0123 4567  
Store  
CPU  
Register  
Ø
Memory  
Halfword  
A-87  
Appendix A 32-Bit ISA Details  
SLL rd, rt, sa  
Shift Left Logical  
Operation  
rd ⇐ rt << sa  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
SLL  
rt  
5
rd  
5
sa  
5
000000  
000000  
6
5
6
Description  
The contents of general-purpose register rt is shifted left by sa bits. Zeros are supplied to the  
vacated positions on the right. The result is placed into general-purpose register rd.  
Exceptions  
None  
Example  
Assume that register r2 contains 0x2170_ADC5. Then, executing the instruction:  
SLL r3,r2,4  
places 0x170A_DC50 in register r3, as shown below.  
r2 0000  
Shifted left  
0001 0111 0000 1010 1101 1100 0101  
by 4 bits  
Padded with zeros  
r3  
0001 0111 0000 1010 1101 1100 0101 0000  
A-88  
Appendix A 32-Bit ISA Details  
SLLV rd, rt, rs  
Shift Left Logical Variable  
Operation  
rd ⇐ rt << 5 LSBs of rs  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
SLLV  
rs  
5
rt  
5
rd  
5
000000  
000100  
6
5
6
Description  
The contents of general-purpose register rt is shifted left the number of bits specified by the five  
least-significant bits of general-purpose register rs. Zeros are supplied to the vacated positions on  
the right. The result is placed into general-purpose register rd.  
Exceptions  
None  
A-89  
Appendix A 32-Bit ISA Details  
SLT rd, rs, rt  
Set On Less Than  
Operation  
if rs < rt then rd ⇐ 1; else rd ⇐ 0  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
SLT  
rs  
5
rt  
5
rd  
5
000000  
101010  
6
5
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt. Both rs and rt are treated as signed integers. If rs is less than rt, general-purpose register rd is set  
to one. Otherwise, rd is set to zero.  
No Integer Overflow exception occurs under any circumstances. The comparison is valid even if the  
subtraction performed for comparison results in overflow.  
Exceptions  
None  
A-90  
Appendix A 32-Bit ISA Details  
SLTI rt, rs, immediate  
Set On Less Than Immediate  
Operation  
if rs < ((immediate15)16 || immediate15..0) then rt ⇐ 1; else rt ⇐ 0  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
SLTI  
rs  
5
rt  
5
immediate  
16  
001010  
6
Description  
The 16-bit immediate is sign-extended and compared to the contents of general-purpose register rs.  
The immediate and rs are compared as signed integers. If rs is less than immediate, general-purpose  
register rt is set to one. Otherwise, rt is set to zero.  
No Integer Overflow exception occurs under any circumstances. The comparison is valid even if the  
subtraction performed for comparison results in overflow.  
With the 16-bit immediate, the immediate range is -32768 to +32767. If a number is outside this  
range, you need to put it in a general-purpose register and use the SLT instruction (see Section 3.3.2,  
32-Bit Constants).  
Exceptions  
None  
A-91  
Appendix A 32-Bit ISA Details  
SLTIU rt, rs, immediate  
Set On Less Than Immediate Unsigned  
Operation  
if (0 || rs) < ((immediate15)17 || immediate15..0) then rt ⇐ 1; else rt ⇐ 0  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
SLTIU  
rs  
5
rt  
5
immediate  
16  
001011  
6
Description  
The 16-bit immediate is sign-extended and compared to the contents of general-purpose register rs.  
The immediate and rs are compared as unsigned integers. If rs is less than immediate,  
general-purpose register rt is set to one. Otherwise, rt is set to zero.  
No Integer Overflow exception occurs under any circumstances. The comparison is valid even if the  
subtraction performed for comparison results in overflow.  
The immediate field is 16 bits in length. If a number is outside this range, you need to put it in a  
general-purpose register and use the SLTU instruction (see Section 3.3.2, 32-Bit Constants).  
Exceptions  
None  
A-92  
Appendix A 32-Bit ISA Details  
SLTU rd, rs, rt  
Set On Less Than Unsigned  
Operation  
if (0 || rs) < (0 || rt) then rd ⇐ 1; else rd ⇐ 0  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
SLTU  
rs  
5
rt  
5
rd  
5
00000  
101011  
6
5
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt. Both rs and rt are treated as unsigned integers. If rs is less than rt, general-purpose register rd is  
set to one. Otherwise, rd is set to zero.  
No Integer Overflow exception occurs under any circumstances. The comparison is valid even if the  
subtraction performed for comparison results in overflow.  
Exceptions  
None  
A-93  
Appendix A 32-Bit ISA Details  
SRA rd, rt, sa  
Shift Right Arithmetic  
Operand  
rd ⇐ rt >> sa  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
SRA  
rs  
5
rt  
5
rd  
5
sa  
5
000011  
6
6
Description  
The contents of general-purpose register rt is shifted right by sa bits. The sign bit is copied to the  
vacated positions on the left. The result is placed into general-purpose register rd.  
Exceptions  
None  
Example  
Assume that register r2 contains 0xB521_4C5E. Then, executing the instruction:  
SRA r3,r2,16  
places 0xFFFF_B521 into r3, as shown below.  
r2  
1 011 0101 0010 0001 0100 1100 0101 1110  
Shifted right by 16 bits  
1011 0101 0010 0001  
Sign Bit  
1111 1111 1111 1111  
r3  
A-94  
Appendix A 32-Bit ISA Details  
SRAV rd, rt, rs  
Shift Right Arithmetic Variable  
Operation  
rd ⇐ rt >> 5 LSBs of rs  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
SRAV  
rs  
5
rt  
5
rd  
5
00000  
000111  
6
5
6
Description  
The contents of general-purpose register rt is shifted right the number of bits specified by the five  
least-significant bits of general-purpose register rs. The sign bit is copied to the vacated positions on  
the left. The result is placed into general-purpose register rd.  
Exceptions  
None  
A-95  
Appendix A 32-Bit ISA Details  
SRL rd, rt, sa  
Shift Right Logical  
Operation  
rd ⇐ rt >> sa  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
SRL  
rt  
5
rd  
5
sa  
5
00000  
000010  
6
5
6
Description  
The contents of general-purpose register rt is shifted left by sa bits. Zeros are supplied to the  
vacated positions on the left. The result is placed into general-purpose register rd.  
Exceptions  
None  
Example  
Assume that register r2 contains 0xB521_4C5E. Then, executing the instruction:  
SRL r3,r2,16  
places 0x0000_B521 in register r3, as shown below.  
r2  
1011 0101 0010 0001 0100 1100 0101 1110  
Shifted right by 16 bits  
Padded with zeros  
r3  
0000 0000 0000 0000 1011 0101 0010 0001  
A-96  
Appendix A 32-Bit ISA Details  
SRLV rd, rt, rs  
Shift Right Logical Variable  
Operation  
rd ⇐ rt >> 5 LSBs of rs  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
SRLV  
rs  
5
rt  
5
rd  
5
00000  
000110  
6
5
6
Description  
The contents of general-purpose register rt (32 bits) is shifted right the number of bits specified by the  
five least-significant bits of general-purpose register rs. Zeros are supplied to the vacated positions on  
the left. The result is placed into general-purpose register rd.  
Exceptions  
None  
A-97  
Appendix A 32-Bit ISA Details  
SUB rd, rs, rt  
Subtract  
Operation  
rd ⇐ rs – rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
SUB  
rs  
5
rt  
5
rd  
5
00000  
100010  
6
5
6
Description  
The contents of general-purpose register rt is subtracted from the contents of general-purpose  
register rs. Both rs and rt are treated as signed integers. The remainder is placed into general-purpose  
register rd.  
An Integer Overflow exception is taken on 2’s-complement overflow, which occurs if the signs of  
the operands are not the same and the sign of the remainder is not the same as the sign of the  
minuend (rs). The destination register (rd) is not altered when an Integer Overflow exception  
occurs.  
Exceptions  
Interger Overflow exception  
Example  
1.  
Assume that registers r2 and r3 contain 0x7654_3210 and 0x5000_0000 respectively. Then,  
executing the instruction:  
SUB r4,r2,r3  
places the remainder (0x2654_3210) into r4.  
2.  
Assume that registers r2 and r3 contain 0x7FFF_FFFF and 0x8FFF_FFFF respectively.  
Then, the subtraction of r3 from r2 gives the result 0xF000_0000. So, the signs of r2 and r3  
are different, and the signs of r2 and the remainder are also different. This indicates a  
2’scomplement overflow. Thus executing the instruction:  
SUB r4,r2,r3  
causes an Integer Overflow exception. Register r4 is not modified as a result of this  
instruction.  
A-98  
Appendix A 32-Bit ISA Details  
SUBU rd, rs, rt  
Subtract Unsigned  
Operation  
rd ⇐ rs – rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
SUBU  
rs  
5
rt  
5
rd  
5
00000  
100011  
6
5
6
Description  
The contents of general-purpose register rt is subtracted from the contents of general-purpose  
register rs. The remainder is placed into general-purpose register rd.  
The only difference between this instruction and the SUB instruction is that this instruction never  
causes an Integer Overflow exception.  
Exceptions  
None  
A-99  
Appendix A 32-Bit ISA Details  
SW rt, offset (base)  
Store Word  
Operation  
rt ⇒ {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
SW  
base  
5
rt  
5
offset  
16  
101011  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The contents of general-purpose register rt is stored at the  
memory location addressed by EA.  
If the two least-significant bits of the effective address is not zero (i.e., the effective address is not  
on a word boundary), an Address Error exception occurs.  
Exceptions  
Address Error exception  
Example  
Assume that registers r8 and r9 contain 0x0000_0400 and 0x0123_4567 respectively. In big-endian  
mode, executing the instruction:  
SW r9,4(r8)  
stores 0x01, 0x23, 0x45 and 0x67 to the memory locations at addresses 0x404 to 0x407  
respectively. In little-endian mode, this instruction stores 0x67, 0x45, 0x23 and 0x01 to the memory  
locations at addresses 0x404 to 0x407 respectively.  
Executing the instruction:  
SW r9,5(r8)  
causes an Address Error exception since 0x405 is not on a word boundary.  
A-100  
Appendix A 32-Bit ISA Details  
Memory  
Byte  
Byte  
Word Boundary  
Word Boundary  
0x0000 0400  
r8  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
+4  
0x01  
0x23  
0x45  
0x67  
0x67  
0x45  
0x23  
0x01  
Big-Endian  
Little-Endian  
r9  
0x0123 4567  
Store  
A-101  
Appendix A 32-Bit ISA Details  
SWL rt, offset (base)  
Store Word Left  
Operation  
rt ⇒ {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
SWL  
base  
5
rt  
5
offset  
16  
101010  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The left portion of general-purpose register rt is stored into  
the appropriate high-order part of the word at the memory locations addressed by EA that cross a  
natural word boundary.  
No Address Error exception occurs due to misalignment.  
The SWL and SWR instructions are used in combination to store a word into memory locations that  
are not on a natural word boundary.  
Exceptions  
Address Error exception  
Example  
Assume that registers r8 and r9 contain 0x0000_0400 and 00123_4567 respectively.  
r9  
0x0123 4567  
A-102  
Appendix A 32-Bit ISA Details  
• Big-endian mode  
The instruction:  
SWL r9,2(r8)  
starts at the leftmost byte in register r9 and stores that byte at address 0x0402. Then it stores  
bytes in register r9, going in the higher-address direction, until it reaches a word boundary in  
memory. The operation of this SWL instruction is as follows.  
Memory  
Byte  
0xAA  
0xBB  
0xCC  
0xDD  
Byte  
0x01  
0x23  
0xCC  
0xDD  
0x402  
0x403  
0x404  
0x405  
Word  
Boundary  
Before  
After  
(a) Big-Endian  
• Little-endian mode  
The instruction:  
SWL r9,5(r8)  
starts at the leftmost byte in register r9 and stores that byte at address 0x0405. Then it stores  
bytes in register r9, going in the lower-address direction, until it reaches a word boundary in  
memory. The operation of this SWL instruction is as follows.  
Memory  
Byte  
0xAA  
0xBB  
0xCC  
0xDD  
Byte  
0xAA  
0xBB  
0x23  
0x01  
0x402  
0x403  
0x404  
0x405  
Word  
Boundary  
Before  
After  
(b) Little-Endian  
A-103  
Appendix A 32-Bit ISA Details  
SWR rt, offset (base)  
Store Word Right  
Operation  
rt ⇒ {sign-extend(offset) + (base)}  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
SWR  
base  
5
rt  
5
offset  
16  
101110  
6
Description  
The 16-bit immediate offset is sign-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The right-portion of general-purpose register rt is stored into  
the appropriate low-order part of the word at the memory locations addressed by EA that cross a  
natural word boundary.  
No Address Error exception occurs due to misalignment.  
The SWL and SWR instructions are used in combination to store a word into memory locations that  
are not on a natural word boundary.  
Exceptions  
Address Error exception  
Example  
Assume register r9 contains 0x123_4567.  
r9  
0x0123 4567  
The following shows how to store the right portion of a general-purpose register after storing the left  
portion as described on the previous SWL pages.  
A-104  
Appendix A 32-Bit ISA Details  
• Big-endian mode  
The instruction:  
SWR r9,5(r8)  
starts at the rightmost byte in register r9 and stores that byte at address 0x0405. Then it stores  
bytes in register r9, going in the lower-address direction, until it reaches a word boundary in  
memory. The operation of this SWR instruction is as follows.  
After execution of "SWL r9, 2(r8)"  
Ø
Byte  
0x01  
0x23  
0xCC  
0xDD  
0x01  
0x23  
0x45  
0x67  
0x402  
0x403  
0x404  
0x405  
Word  
Boundary  
Before  
After  
(a) Big-Endian  
• Little-endian mode  
The instruction:  
SWR r9,2(r8)  
starts at the rightmost byte in register r9 and stores that byte at address 0x0402. Then it stores  
bytes in register r9, going in the higher-address direction, until it reaches a word boundary in  
memory. The operation of this SWR instruction is as follows.  
After execution of "SWL r9, 5(r8)"  
Ø
Byte  
0xAA  
0xBB  
0x23  
0x01  
0x67  
0x45  
0x23  
0x01  
0x402  
0x403  
0x404  
0x405  
Word  
Boundary  
Before  
After  
(b) Little-Endian  
A-105  
Appendix A 32-Bit ISA Details  
SYNC  
Synchronize  
Operation  
Synchronize operation  
Instruction Encoding  
31  
26 25  
6 5  
0
SPECIAL  
000000  
0
SYNC  
0000 0000 0000 0000  
001111  
6
20  
6
Description  
The SYNC instruction interlocks the instruction pipeline until loads and stores performed prior to  
the present instruction are completed before any instructions after this instruction are allowed to  
start. See Section 5.2.4, SYNC Instruction (32-Bit ISA).  
If there is no data dependency, the TX19A continues to execute subsequent instructions. This is  
called non-blocking loads. By virtue of non-blocking loads, the instruction pipeline can continue to  
work on non-dependent instructions.  
Exceptions  
None  
A-106  
Appendix A 32-Bit ISA Details  
SYSCALL code  
System Call  
Operation  
System call exception  
Instruction Encoding  
31  
26 25  
6 5  
0
SPECIAL  
000000  
SYSCALL  
001100  
Code  
20  
6
6
Description  
A System Call exception occurs, immediately and unconditionally transferring control to the  
exception handler.  
The code field in a SYSCALL instruction is available for use as software parameters to pass  
additional information. To examine these bits, load the contents of the instruction at which the EPC  
register points. For details on System Call exceptions, see Section 9.1.10, System Call Exception.  
Exceptions  
System call exception  
A-107  
Appendix A 32-Bit ISA Details  
TEQ rs, rt, code  
Trap If Equal  
Operation  
if rs = rt then Trap Exception; else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
6 5  
0
SPECIAL  
000000  
TEQ  
rs  
5
rt  
5
code  
10  
110100  
6
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt. If rs is equal to rt, a Trap exception occurs. The code field in a TEQ instruction is available for  
use as software parameters to pass additional information. To examine these bits, system software  
must load the instruction word from memory.  
Exceptions  
Trap exception  
A-108  
Appendix A 32-Bit ISA Details  
TEQI rs, immediate  
Trap If Equal Immediate  
Operation  
if rs = (immediate15)16 || immediate15..0 then Trap Exception else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
TEQI  
rs  
5
immediate  
16  
01100  
6
5
Description  
The 16-bit immediate is sign-extended and compared to the contents of general-purpose register rs.  
If rs is equal to immediate, a Trap exception occurs.  
Exceptions  
Trap exception  
A-109  
Appendix A 32-Bit ISA Details  
TGE rs, rt, code  
Trap If Greater Than or Equal  
Operation  
if rs ≧rt then Trap Exception; else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
6 5  
0
SPECIAL  
000000  
TGE  
rs  
5
rt  
5
code  
10  
110000  
6
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt as signed integers. If rs is greater than or equal to rt, a Trap exception occurs. The code field in a  
TGE instruction is available for use as software parameters to pass additional information. To  
examine these bits, system software must load the instruction word from memory.  
Exceptions  
Trap exception  
A-110  
Appendix A 32-Bit ISA Details  
TGEI rs, immediate  
Trap If Greater Than Or Equal Immediate  
Operation  
if rs ≧(immediate15)16 || immediate15..0 then Trap Exception else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
TGEI  
rs  
5
immediate  
16  
01000  
6
5
Description  
The 16-bit immediate is sign-extended and compared to the contents of general-purpose register rs  
as signed integers. If rs is greater than or equal to immediate, a Trap exception occurs.  
Exceptions  
Trap exception  
A-111  
Appendix A 32-Bit ISA Details  
TGEIU rs, immediate  
Trap If Greater Than Or Equal Immediate Unsigned  
Operation  
if (0 || rs) ≧0 || (immediate15)16 || immediate15..0 then Trap Exception else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
TGEIU  
01001  
rs  
5
immediate  
16  
6
5
Description  
The 16-bit immediate is sign-extended and compared to the contents of general-purpose register rs  
as unsigned integers. If rs is greater than or equal to immediate, a Trap exception occurs.  
Exceptions  
Trap exception  
A-112  
Appendix A 32-Bit ISA Details  
TGEU rs, rt, code  
Trap If Greater Than or Equal Unsigned  
Operation  
if (0 || rs) ≧(0 || rt) then Trap Exception; else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
6 5  
0
SPECIAL  
000000  
TGEU  
rs  
5
rt  
5
Code  
10  
110001  
6
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt as unsigned integers. If rs is greater than or equal to rt, a Trap exception occurs. The code field in  
a TGEU instruction is available for use as software parameters to pass additional information. To  
examine these bits, system software must load the instruction word from memory.  
Exceptions  
Trap exception  
A-113  
Appendix A 32-Bit ISA Details  
TLT rs, rt, code  
Trap If Less Than  
Operation  
if rs < rt then Trap Exception; else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
6 5  
0
SPECIAL  
000000  
TLT  
rs  
5
rt  
5
code  
10  
110010  
6
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt as signed integers. If rs is less than rt, a Trap exception occurs. The code field in a TLT  
instruction is available for use as software parameters to pass additional information. To examine  
these bits, system software must load the instruction word from memory.  
Exceptions  
Trap exception  
A-114  
Appendix A 32-Bit ISA Details  
TLTI rs, immediate  
Trap If Less Than Immediate  
Operation  
if rs < (immediate15)16 || immediate15..0 then Trap Exception else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
TLTI  
rs  
5
Immediate  
16  
01010  
6
5
Description  
The 16-bit immediate is sign-extended and compared to the contents of general-purpose register rs  
as signed integers. If rs is less than immediate, a Trap exception occurs.  
Exceptions  
Trap exception  
A-115  
Appendix A 32-Bit ISA Details  
TLTIU rs, immediate  
Trap If Less Than Immediate Unsigned  
Operation  
if (0 || rs) < 0 || (immediate15)16 || immediate15..0 then Trap Exception else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
TLTIU  
01011  
rs  
5
Immediate  
16  
6
5
Description  
The 16-bit immediate is sign-extended and compared to the contents of general-purpose register rs  
as unsigned integers. If rs is less than immediate, a Trap exception occurs.  
Exceptions  
Trap exception  
A-116  
Appendix A 32-Bit ISA Details  
TLTU rs, rt, code  
Trap If Less Than Unsigned  
Operation  
if (0 || rs) < (0 || rt) then Trap Exception; else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
6 5  
0
SPECIAL  
000000  
TLTU  
rs  
5
rt  
5
code  
10  
110011  
6
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt unsigned integers. If rs is less than rt, a Trap exception occurs. The code field in a TLTU  
instruction is available for use as software parameters to pass additional information. To examine  
these bits, system software must load the instruction word from memory.  
Exceptions  
Trap exception  
A-117  
Appendix A 32-Bit ISA Details  
TNE rs, rt, code  
Trap If Not Equal  
Operation  
if rs ≠rt then Trap Exception; else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
6 5  
0
SPECIAL  
000000  
TNE  
rs  
5
rt  
5
code  
10  
110110  
6
6
Description  
The contents of general-purpose register rs is compared to the contents of general-purpose register  
rt. If rs is not equal to rt, a Trap exception occurs. The code field in a TNE instruction is available  
for use as software parameters to pass additional information. To examine these bits, system  
software must load the instruction word from memory.  
Exceptions  
Trap exception  
A-118  
Appendix A 32-Bit ISA Details  
TNEI rs, immediate  
Trap If Not Equal Immediate  
Operation  
if rs ≠(immediate15)16 || immediate15..0 then Trap Exception else Next Instruction  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
REGIMM  
000001  
TNEI  
rs  
5
immediate  
16  
01110  
6
5
Description  
The 16-bit immediate is sign-extended and compared to the contents of general-purpose register rs.  
If rs is not equal to immediate, a Trap exception occurs.  
Exceptions  
Trap exception  
A-119  
Appendix A 32-Bit ISA Details  
WAIT  
Enter Standby Mode  
Operation  
if Status[RP] = 1 then DOZE mode  
else HALT mode  
Instruction Encoding  
31  
26 25 24  
6 5  
0
COP0  
CO  
1
0
WAIT  
010000  
000 0000 0000 0000 0000  
100000  
6
1
19  
6
Description  
The WAIT instruction is used to stall the instruction pipeline to reduce the processor’s power  
consumption. If the RP bit in the Status register is set, the processor enters DOZE mode. If the RP  
bit is cleared, the processor enters HALT mode. Refer to Chapter 10, Low-Power Modes.  
The WAIT instruction must not be set in a delay slot of the branch or jump instruction.  
Once the MTC0 instruction writes to the Status, EPC or ErrorEPC register, at least two instructions  
must be executed before the WAIT instruction. Otherwise, the operation is undefined.  
Exceptions  
Coprocessor Unusable exception  
A-120  
Appendix A 32-Bit ISA Details  
XOR rd, rs, rt  
Exclusive OR  
Operation  
rd ⇐ rs XOR rt  
Instruction Encoding  
31  
26 25  
21 20  
16 15  
11 10  
6 5  
0
SPECIAL  
000000  
0
XOR  
rs  
5
rt  
5
rd  
5
00000  
100110  
6
5
6
Description  
The contents of general-purpose register rs is exclusive-ORed with the contents of general-purpose  
register rt. The result is placed back into general-purpose register rd.  
Exceptions  
None  
Example  
Assume that registers r2 and r3 contain 0x1000_7350 and 0x0000_3456 respectively. Then,  
executing the instruction:  
XOR r4,r2,r3  
places 0x1000_4706 back in register r4, as shown below.  
0001 0000 0000 0000 0111 0011 0101 0000  
r2  
XOR  
0000 0000 0000 0000 0011 0100 0101 0110  
r3  
0001 0000 0000 0000 0100 0111 0000 0110  
r4  
A-121  
Appendix A 32-Bit ISA Details  
XORI rt, rs, immediate  
Exclusive OR Immediate  
Operation  
rt ⇐ rs XOR (016 || immediate15..0  
)
Instruction Encoding  
31  
26 25  
21 20  
16 15  
0
XORI  
rs  
5
rt  
5
immediate  
16  
001110  
6
Description  
The 16-bit immediate is zero-extended and exclusive-ORed with the contents of general-purpose  
register rs. The result is placed back into rt.  
The immediate field is 16 bits in length. If the immediate size is larger than that, you need to put it  
in a general-purpose register and use the XOR instruction (see Section 3.3.2, 32-Bit Constants).  
Exceptions  
None  
Example  
Assume that register r2 contains 0x0000_7350. Then, executing the instruction:  
XORI r3,r2,0x1234  
places 0x0000_6164 back in register r3, as shown below.  
0000 0000 0000 0000 0111 0011 0101 0000  
r1  
XOR  
0000 0000 0000 0000 0001 0010 0011 0100  
Zero-Extended  
0000 0000 0000 0000 0110 0001 0110 0100  
r3  
A-122  
Appendix B 16-Bit ISA Details  
Appendix B 16-Bit ISA Details  
This appendix presents detailed information concerning each instruction in the 16-bit ISA. Each  
instruction is listed alphabetically by mnemonic. Each listing contains complete information about  
assembler syntax, instruction format, operation and exceptions that may occur due to the execution  
of the instruction. For the variations of instruction formats, see Section 4.1, Instruction Formats.  
To fit within the 16-bit limit, the register fields (rx, ry, rz and base) in the 16-bit instructions are  
only 3 bits. Therefore, to the 16-bit instructions, only eight of the 32 general-purpose registers are  
normally visible, r2 to r7, r16 and r17. These registers are encoded as follows.  
Code  
Register  
Code  
Register  
000  
001  
010  
011  
r16  
r17  
r2  
100  
101  
110  
111  
r4  
r5  
r6  
r7  
r3  
Additionally, specific instructions implicitly reference r24 (t8), r28 (gp), r29 (sp), r30 (fp) and r31  
(ra). r24 serves as the condition code register for handling compare results. r28 is the global pointer.  
r29 maintains the program stack pointer. r30 is the frame pointer. r31 is the link register to store the  
subroutine return address. These registers are implicitly referred to through special function codes.  
B-1  
Appendix B 16-Bit ISA Details  
AC0IU cp0rt32, imm3  
Add Coprocessor 0 Immediate Unsigned  
Operation  
cp0rt32 ⇐ cp0rt32 + imm3  
Instruction Encoding  
15  
11 10  
8
7
0
1
6
2 1 0  
RRR  
ximm3  
cp0rt32  
5
00  
11100  
5
3
2
Description  
The encoding used for the 3-bit imm3 field is shown below. The value indicated by imm3 is added  
to the contents of CP0 register cp0rt32. The result is placed back into cp0rt32. imm3 can only be  
one of these: –8, –4, –2, –1, +1, +2, +4, +8.  
ximm3  
1 1 1  
1 1 0  
1 0 1  
1 0 0  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
imm3  
－8  
－4  
－2  
－1  
+1  
+2  
+4  
+8  
No Integer Overflow exception occurs under any circumstances.  
Once the AC0IU instruction writes to the Status, EPC or ErrorEPC register, at least two instructions  
must be executed before the ERET instruction. Otherwise, the operation is undefined.  
The AC0IU instruction that modifies the contents of the SSCR register must be followed by two  
NOPs.  
Exceptions  
Coprocessor Unusable exception  
B-2  
Appendix B 16-Bit ISA Details  
Example  
Assume that the EPC register contains 0x8001_0060. Then, the instruction:  
AC0IU EPC, -8  
writes the result of 0x8001_0058 into EPC.  
B-3  
Appendix B 16-Bit ISA Details  
ADDIU fp, immediate  
Add Immediate Unsigned  
Operation  
r30 ⇐ r30 + (immediate7)22 || (immediate7..0)|| 00  
(EXTENDED)  
r30 ⇐ r30 + (immediate15)16 || (immediate15..0  
)
Instruction Encoding  
15  
11 10  
8
7
7
0
0
I8  
ADJFP  
110  
Immediate[7:0]  
8
01100  
5
3
EXTENDED  
EXTENDED  
31  
27 26  
19 18  
16 15  
11 10  
8
5 4  
EXTEND  
11110  
imm  
I8  
imm [10:5]  
8
110  
3
000  
3
Imm[4:0]  
5
[15:11]  
3
01100  
5
5
Description  
The term "unsigned" in the instruction name is a misnomer. The 8-bit immediate is shifted left by  
two bits and sign-extended. The resultant value is added to the contents of the fp (r30) register.  
No Integer Overflow exception occurs under any circumstances.  
Since the 8-bit immediate is shifted left by two bits, the immediate range is –512 to +504, in  
increments of four. If the immediate is outside this range, the instruction is EXTENDed to provide a  
16-bit signed immediate in the range of –32768 to +32767. When EXTENDed, the immediate  
operand is not shifted at all.  
Exceptions  
None  
Example  
Assume that frame pointer register fp contains 0x0000_2000. Then, the instruction:  
ADDIU fp,8  
places the result 0x0000_2008 in fp.  
B-4  
Appendix B 16-Bit ISA Details  
ADDIU rx, immediate  
Add Immediate Unsigned  
Operation  
rx ⇐ rx + (immediate7)24 || (immediate7..0  
)
(EXTENDED)  
rx ⇐ rx + (immediate15)16 || (immediate15..0  
)
Instruction Encoding  
15  
11 10  
11 10  
8 7  
0
ADDIU8  
01001  
rx  
3
immediate  
8
5
31  
27 26  
21 20  
16 15  
8
7
5
4
0
EXTEND  
11110  
ADDIU8  
01001  
EXTENDED  
imm[10:5]  
6
imm[15:11]  
rx  
3
000  
3
imm[4:0]  
5
5
5
5
Description  
The term "unsigned" in the instruction name is a misnomer. The 8-bit immediate is sign-extended  
and added to the contents of general-purpose register rx. The result is placed back into  
general-purpose  
register rx.  
No Integer Overflow exception occurs under any circumstances.  
With the 8-bit immediate field, the immediate range is -128 to +127. If the immediate is outside this  
range, the instruction is EXTENDed to provide a 16-bit signed immediate in the range of -32768 to  
+32767.  
Exceptions  
None  
B-5  
Appendix B 16-Bit ISA Details  
ADDIU rx, pc, immediate  
Add Immediate Unsigned  
Operation  
rx ⇐ Masked base PC + 022 || (immediate7..0) || 00  
(EXTENDED)  
rx ⇐ Masked base PC + (immediate15)16 || (immediate15..0  
)
Instruction Encoding  
15  
11 10  
11 10  
8 7  
0
ADDIUPC  
00001  
rx  
3
immediate  
5
8
31  
27 26  
21 20  
16 15  
8
7
5
4
0
EXTEND  
11110  
ADDIUPC  
00001  
EXTENDED  
imm[10:5]  
6
imm[15:11]  
rx  
3
000  
3
imm[4:0]  
5
5
5
5
Description  
The PC value used as the base for address calculation is called base PC value. The two low-order  
bits of the PC are cleared to form a "masked base PC value." The 8-bit immediate is shifted left by  
two bits, zero-extended and then added to the masked base PC value to form a virtual address. This  
address is placed into general-purpose register rx. This instruction is used to calculate the PC relative  
address of an instruction or data in its proximity and place it in a register.  
No Integer Overflow exception occurs under any circumstances.  
The 32-bit PC-relative instruction is not a valid 32-bit ISA instruction; thus the operation of this  
instruction differs from that of the ADDIU instruction in the 32-bit ISA.  
Since the 8-bit immediate is shifted left by two bits, the immediate range is 0 to 1020, in increments  
of four. If the immediate is outside this range, the instruction is EXTENDed to provide a 16-bit  
signed immediate in the range of -32768 to +32767. When EXTENDed, the immediate operand is  
not shifted at all.  
The base PC value differs as follows, depending on whether this instruction is in a delay slot and  
whether it is prepended with an EXTEND prefix.  
B-6  
Appendix B 16-Bit ISA Details  
ADDIUPC  
Base PC Value  
Delay slot of a JR or JALR instruction  
Delay slot of a JAL or JALX instruction  
EXTENDed  
Address of the JR or JALR instruction  
Address of the upper halfword of the JAL or JALX instruction  
Address of the EXTEND instruction code  
Address of the ADDIUPC instruction  
Not EXTENDed  
Exceptions  
None  
Example  
ADDIU r3,pc,16  
Assume that this instruction is at address 0x0123_456A which is not a delay slot. Then, the masked  
PC value of 0x0123_4568 is obtained by clearing its two low-order bits. Since the immediate value  
is shifted left by two bits by the processor hardware, the assembler turns the specified operand (16)  
into a code of 4. Thus the instruction code for this ADDIU instruction becomes 0x0B04. The offset  
is added to the masked PC value as shown below, and the result is placed in register r3.  
Memory Word  
0x0123_4568  
ADDIU r3, pc, 16  
Masked Base PC  
0x1234568  
0x123456C  
0x123457C  
0x1234574  
0x1234578  
0x123457C  
The immediate value, 4, is  
shifted left by two bits.  
+16  
0x0123_4578  
r3  
B-7  
Appendix B 16-Bit ISA Details  
ADDIU rx, sp, immediate  
Add Immediate Unsigned  
Operation  
rx ⇐ sp + 022 || (immediate7..0) || 00  
(EXTENDED)  
rx ⇐ sp + (immediate15)16 || (immediate15..0  
)
Instruction Encoding  
15  
11 10  
11 10  
8 7  
0
ADDIUSP  
00000  
rx  
3
immediate  
8
5
31  
27 26  
21 20  
16 15  
8
7
5
4
0
EXTEND  
11110  
ADDIUSP  
00000  
EXTENDED  
imm[10:5]  
6
imm[15:11]  
rx  
3
000  
3
imm[4:0]  
5
5
5
5
Description  
In this instruction format, the 8-bit immediate is shifted left by two bits and zero-extended. The  
resultant value is added to the contents of stack pointer register sp (r29), and the result is placed into  
general-purpose register rx.  
No Integer Overflow exception occurs under any circumstances.  
Since the 8-bit immediate is shifted left by two bits, the immediate range is 0 to 1020, in increments  
of four. If the immediate is outside this range, the instruction is EXTENDed to provide a 16-bit  
signed immediate in the range of -32768 to +32767. When EXTENDed, the immediate operand is  
not shifted at all.  
Exceptions  
None  
B-8  
Appendix B 16-Bit ISA Details  
ADDIU ry, rx, immediate  
Add Immediate Unsigned  
Operation  
ry ⇐ rx + (immediate3)28 || (immediate3..0  
)
(EXTENDED)  
ry ⇐ rx + (immediate14)17 || (immediate14..0  
)
Instruction Encoding  
15  
11 10  
11 10  
8 7  
5
5
4 3  
0
RRI-A  
01000  
0
1
rx  
3
ry  
3
immediate  
5
4
31  
27 26  
20 19  
16 15  
8
7
4
0
1
3
0
EXTEND  
11110  
PRI-A  
01000  
EXTENDED  
imm[10:4]  
7
imm[14:11]  
rx  
3
ry  
3
imm[3:0]  
4
5
4
5
Description  
The term "unsigned" in the instruction name is a misnomer. The 4-bit immediate is sign-extended  
and added to the contents of general-purpose register rx. The result is placed into general-purpose  
register ry.  
No Integer Overflow exception occurs under any circumstances.  
With the 4-bit immediate field, the immediate range is -8 to +7. If the immediate is outside this  
range, the instruction is EXTENDed to provide a 15-bit signed immediate in the range of -16384 to  
+16833.  
Exceptions  
None  
B-9  
Appendix B 16-Bit ISA Details  
Example  
Assume that register r2 contains 0x0000_1234. Then, executing the instruction:  
ADDIU r3,r2,-6  
places the sum 0x0000_122E into r3.  
r2  
0
0
0
F
0
F
1
F
2
F
3
F
4
+
F
F
A
Sign-Extended  
r3  
0
0
0
0
1
2
2
E
B-10  
Appendix B 16-Bit ISA Details  
ADDIU sp, immediate  
Add Immediate Unsigned  
Operation  
sp ⇐ sp + (immediate7)21 || (immediate7..0) || 000  
(EXTENDED)  
sp ⇐ sp + (immediate15)16 || (immediate15..0  
)
Instruction Encoding  
15  
11 10  
8 7  
0
I8  
ADJSP  
immediate  
8
01100  
011  
3
5
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
18  
ADJSP  
011  
EXTENDED  
imm[10:5]  
6
imm[15:11]  
000  
3
imm[4:0]  
5
01100  
5
5
5
3
Description  
The term "unsigned" in the instruction name is a misnomer. The 8-bit immediate is shifted left by  
three bits and sign-extended. The resultant value is added to the contents of stack pointer register sp  
(r29).  
No Integer Overflow exception occurs under any circumstances.  
Since the 8-bit immediate is shifted left by three bits, the immediate range is -1024 to +1016, in  
increments of eight. If the immediate is outside this range, the instruction is EXTENDed to provide  
a 16-bit signed immediate in the range of -32768 to +32767. When EXTENDed, the immediate  
operand is not shifted at all.  
Exceptions  
None  
B-11  
Appendix B 16-Bit ISA Details  
Example  
Assume stack pointer register sp contains 0x0000_2000. Then, the instruction:  
ADDIU sp,8  
places the result 0x0000_2008 in sp, as shown below.  
r2 0  
0
0
0
0
0
0
0
2
0
0
0
0
0
0
8
+
Sign-extended  
r3 0  
0
0
0
2
0
0
8
B-12  
Appendix B 16-Bit ISA Details  
ADDMIU offset (base3), imm3  
Add Immediate to Memory Word  
Operation  
{zero-extend (offset || 00) + (base3)} ⇐ {zero-extend (offset || 00) + (base3)} + imm3  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
offset  
[13:11]  
11 10  
8
7
5
4
0
EXTEND  
11110  
ADDMIU  
010  
EXTENDED  
base3  
2
offset[10:5]  
6
01001  
5
ximm3  
offset[4:0]  
5
5
3
3
3
Description  
The 14-bit offset is shifted left by two bits, zero-extended, then added to the contents of the general  
purpose register specified by base3 to form an effective address (EA). The value indicated by the  
3-bit imm3 is added to the memory word addressed by the EA, and the sum is written back to the EA.  
base3  
01  
10  
GPR  
r28 (gp)  
r29 (sp)  
r30 (fp)  
11  
imm3 can only be one of these: –8, –4, –2, –1, +1, +2, +4, +8.  
ximm3  
1 1 1  
1 1 0  
1 0 1  
1 0 0  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
imm3  
－8  
－4  
－2  
－1  
+1  
+2  
+4  
+8  
No Integer Overflow exception occurs under any circumstances.  
Since the 14-bit offset is shifted left by two bits, the offset range is 0 to 65532, in increments of  
four.  
B-13  
Appendix B 16-Bit ISA Details  
Exceptions  
Address Error exception  
Example  
Assume that the fp register contains 0x0000_0400 and that the memory word at address 0x0404 is  
0xFFFF_FFFC. Then, the instruction:  
ADDMIU 4(fp), 8  
adds 8 to the contents of the memory word at 0x404, as shown below.  
Memory  
Byte  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
0x0000_0400  
r30  
+4  
The offset, 1, is shifted  
left by two bits.  
FC  
FF  
FF  
FF  
04  
00  
00  
00  
+8  
Before  
After  
Little-Endian  
B-14  
Appendix B 16-Bit ISA Details  
ADDMIU offset (r0), imm3  
Add Immediate to Memory Word  
Operation  
{sign-extend (offset || 00)} ⇐ {sign-extend (offset || 00)} + imm3  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
offset  
[13:11]  
11 10  
8
7
5
4
0
EXTEND  
11110  
ADDMIU  
010  
EXTENDED  
offset[10:5]  
6
00  
2
01001  
5
ximm3  
offset[4:0]  
5
5
3
3
3
Description  
The 14-bit offset is shifted left by two bits, sign-extended, then added to the contents of general  
purpose register r0 to form an effective address (EA). The value indicated by the 3-bit imm3 is  
added to the memory word addressed by the EA, and the sum is written back to the EA.  
imm3 can only be one of these: –8, –4, –2, –1, +1, +2, +4, +8.  
ximm3  
1 1 1  
1 1 0  
1 0 1  
1 0 0  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
imm3  
－8  
－4  
－2  
－1  
+1  
+2  
+4  
+8  
No Integer Overflow exception occurs under any circumstances.  
Since the 14-bit offset is shifted left by two bits, the offset range is –32768 to +32764, in increments  
of four.  
Exceptions  
Address Error exception  
B-15  
Appendix B 16-Bit ISA Details  
Example  
Assume that the memory word at address 0x0404 is 0x0000_0104. Then, the instruction:  
ADDMIU 0x404(r0), -8  
adds –8 to the contents of the memory word at 0x404, as shown below:  
Memory  
Byte  
Memory  
Byte  
0x404  
0x405  
0x406  
0x407  
0x408  
0x404  
0x405  
0x406  
0x407  
0x408  
0x04  
0x01  
0x00  
0x00  
0xFC  
0x00  
0x00  
0x00  
Target Address  
The offset is shifted  
left by two bits to form  
the target address.  
－8  
Before  
After  
Little-Endian  
B-16  
Appendix B 16-Bit ISA Details  
ADDU rz, rx, ry  
Add Unsigned  
Operation  
rz ⇐ rx + ry  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
2 1  
0
RRR  
ADDU  
01  
rx  
3
ry  
3
rz  
3
11100  
5
2
Description  
The contents of general-purpose register rx is added to the contents of general-purpose register ry,  
and the result is placed into general-purpose register rz. No Integer Overflow exception occurs  
under any circumstances.  
Exceptions  
None  
Example  
Assume that registers r2 and r3 contain 0x2000_0000 and 0x0123_4567 respectively. Then,  
executing the instruction:  
ADDU r4,r2,r3  
places the sum (0x323_4567) into r4.  
B-17  
Appendix B 16-Bit ISA Details  
AND rx, ry  
AND  
Operation  
rx ⇐ rx AND ry  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
AND  
rx  
3
ry  
3
11101  
01100  
5
5
Description  
The contents of general-purpose register rx is ANDed with the contents of general-purpose register  
ry, and the result is placed back into general-purpose register rx.  
Exceptions  
None  
B-18  
Appendix B 16-Bit ISA Details  
ANDI ry, immediate  
Logical AND Immediate  
Operation  
ry ⇐ ry AND (016 || immediate15..0  
)
Instruction Encoding  
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
ANDI  
100  
Imm[10:5]  
6
Imm[15:11]  
01001  
5
ry  
3
Imm[4:0]  
5
EXTENDED  
5
5
3
Description  
The 16-bit immediate is zero-extended and ANDed with the contents of general-purpose register ry.  
The result is placed back into ry.  
The immediate field is 16 bits in length. If the immediate size is larger than that, you need to put it  
in a general-purpose register and use the AND instruction (see 3.3.2, 32-Bit Constants).  
Exceptions  
None  
Example  
Assume that register r4 contains 0x0000_7350. Then, the instruction:  
ANDI r4,0x1234  
performs the logical AND between 0x0000_7350 and 0x0000_1234 and puts the result  
(0x0000_1210) in r4, as shown below.  
r4 0000 0000 0000 0000 0111 0011 0101 0000  
AND  
0000 0000 0000 0000 0001 0010 0011 0100  
Zero-Extended  
r4 0000 0000 0000 0000 0001 0010 0001 0000  
B-19  
Appendix B 16-Bit ISA Details  
B offset  
Unconditional Branch  
Operation  
pc ⇐ pc + 2 + sign-extend (offset || 0)  
pc ⇐ pc + 4 + sign-extend (offset || 0)  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
0
B
offset  
11  
00010  
5
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
B
EXTENDED  
offset[10:5]  
6
offset[15:11]  
000  
3
000  
3
offset[4:0]  
5
00010  
5
5
5
Description  
The program unconditionally branches to the target address with a delay of one instruction (or two  
pipeline cycles). See Section 5.3.4, Branch Instructions (16-Bit ISA), for pipeline delays. This  
instruction does not have a delay slot. If the branch is taken, the instruction that immediately follows  
this instruction is not executed. The target address is computed relative to the address of the  
immediately following instruction, i.e., PC+2 when the instruction is not EXTENDED and PC+4  
when EXTENDed.  
Since the 11-bit offset is shift left by one bit, the branch range is -2048 to +2046. If the offset is  
outside this range, the instruction is EXTENDed to provide a 17-bit signed immediate in the range  
of -65536 to +65534. Whether EXTENDed or not, the target address is computed in the same  
manner.  
Exceptions  
None  
B-20  
Appendix B 16-Bit ISA Details  
Example  
B SBRANCH  
Assume that this branch instruction resides at address 0x2000 and that label SBRANCH points to  
absolute address 0x1FFA. Then the assembler/linker turns this label into an offset operand of  
0x7FC (see the figure below). Thus the instruction code for this branch instruction becomes  
0x17FC.  
The processor unconditionally transfers program control to address 0x1FFA. The instruction  
following the B instruction is never executed.  
0x1FFA  
Branch Destination  
0x2000  
0x2002  
B
SBRANCH  
Next Instruction  
+
0xFFFF_FFF8  
The offset, 0x7FC, is shifted left  
by one bit and sign-extended.  
B-21  
Appendix B 16-Bit ISA Details  
BAL offset  
Branch And Link  
Operation  
r31 ⇐ pc + 3; pc ⇐ pc + 2 + sign-extend (offset || 0)  
r31 ⇐ pc + 5; pc ⇐ pc + 4 + sign-extend (offset || 0)  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8
8
7
7
0
0
SPECIAL  
11111  
100  
3
offset[7:0]  
8
5
31  
27 26  
21 20  
16 15  
5 4  
EXTEND  
11110  
offset  
SPECIAL  
11111  
EXTENDED  
offset[10:5]  
6
100  
3
000  
3
offset[4:0]  
5
[15:11]  
5
5
5
Description  
The program unconditionally branches to the target address with a delay of one instruction (or two  
pipeline cycles). See Section 5.3.4, Branch Instructions (16-Bit ISA), for pipeline delays. This  
instruction does not have a delay slot. If the branch is taken, the instruction that immediately follows  
this instruction is not executed. The target address is computed relative to the address of the  
immediately following instruction, i.e., PC+2 when the instruction is not EXTENDED and PC+4  
when EXTENDed.  
The address of the instruction following the BAL instruction (PC+2) is saved in the link register,  
r31 (ra). The least-significant bit of r31 stores the ISA mode bit that was in effect before the branch  
(16-bit ISA = 1).  
Since the 8-bit offset is shifted left by one bit, the branch range is –256 to +254. If the offset is  
outside this range, the instruction is EXTENDed to provide a 17-bit signed immediate in the range  
of –65536 to –65534. In this case also, the target address is computed the same way.  
Exceptions  
None  
B-22  
Appendix B 16-Bit ISA Details  
Example  
BAL PSUB  
Assume that this branch instruction resides at address 0x2000 and that label PSUB points to  
absolute address 0x2022. Then, the assembler/linker turns this label into an offset operand of  
0x0010 (see the figure below).  
The program unconditionally branches to address 0x2022.  
The JR instruction is used at the end of the called subroutine to return control to the instruction after  
the BAL instruction.  
JR r31  
0x2000  
BAL PSUB  
0x2002  
0x2004  
PC+2 is saved in r31.  
+
0x0020  
r31  
0x0000_2002  
The offset, 0x0010, is shifted left  
by 1 bit and sign-extended.  
0x2022  
Branch Destination  
‚
‚
‚
PC+2 is restored from r31.  
JR  
r31  
Subroutine  
B-23  
Appendix B 16-Bit ISA Details  
BCLR offset (base3), pos3  
Bit Clear  
Operation  
{zero-extend (offset) + (base3)} [pos3] ⇐ 0  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
offset  
EXTENDED  
offset[10:5]  
6
base3  
2
11111  
5
001  
3
pos3  
3
offset[4:0]  
5
[13:11]  
3
5
Description  
A bit specified by pos3 in a memory byte is cleared. The effective address is computed by  
zero-extending the 14-bit offset and adding the resultant value to the contents of a general-purpose  
register indicated by base3. The encoding used for base3 is as follows:  
base3  
01  
10  
GPR  
gp(r28)  
sp(r29)  
fp(r30)  
11  
With the 14-bit offset field, the offset range is 0 to +16383.  
Exceptions  
Address Error exception  
B-24  
Appendix B 16-Bit ISA Details  
Example  
Assume that the sp register (r29) contains 0x0000_0400 and that the byte position at address  
0x0404 contains 0xF2. Then, the instruction:  
BCLR 4(sp),7  
clears bit 7 of byte data 0xF2 as shown below.  
Memory  
Byte  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r29  
+4  
01110010  
11110010  
Before  
Bit 7 is cleared.  
After  
B-25  
Appendix B 16-Bit ISA Details  
BCLR offset (r0), pos3  
Bit Clear  
Operation  
{sign-extend (offset)} [pos3] ⇐ 0  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
offset  
EXTENDED  
offset[10:5]  
6
00  
2
11111  
5
001  
3
pos3  
3
offset[4:0]  
5
[13:11]  
3
5
Description  
A bit specified by pos3 in a memory byte is cleared. The effective address is computed by  
sign-extending the 14-bit offset and adding the resultant value to the contents of general-purpose  
register r0, which is hardwired to a value of zero.  
With the 14-bit offset field, the offset range is -8192 to +8191.  
Exceptions  
Address Error exception  
Example  
Assume that the byte position at address 0x0404 contains 0xF2. Then, the instruction:  
BCLR 0x404(r0), 6  
clears bit 6 of byte data 0xF2 as shown below.  
Memory  
Byte  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x400  
0x401  
0x402  
0x403  
0x404  
10110010  
11110010  
Before  
Target Address  
Bit 6 is cleared.  
After  
B-26  
Appendix B 16-Bit ISA Details  
BCLR offset (fp), pos3  
Bit Clear  
Operation  
{zero-extend (offset) + (fp)} [pos3] ⇐ 0  
Instruction Encoding  
15  
11 10  
8
7
6
pos3  
3
5
4
0
bclr  
001  
11111  
offset[4:0]  
5
5
3
Description  
A bit specified by pos3 in a memory byte is cleared. The effective address is computed by  
zero-extending the 5-bit offset and adding the resultant value to the contents of the fp register (r30).  
With the 5-bit offset field, the offset range is 0 to +31.  
Exceptions  
Address Error exception  
Example  
Assume that the fp register (r30) contains 0x0000_0400 and that the byte position at address 0x0404  
contains 0xF2. Then, the instruction:  
BCLR 4(fp), 7  
clears bit 7 of byte data 0xF2 as shown below.  
Memory  
Byte  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r30  
+4  
01110010  
11110010  
Before  
Bit 7 is cleared.  
After  
B-27  
Appendix B 16-Bit ISA Details  
BEQZ rx, offset  
Branch On Equal To Zero  
Operation  
if rx = 0 then pc ⇐ pc + 2 + sign-extend (offset || 0)  
if rx = 0 then pc ⇐ pc + 4 + sign-extend (offset || 0)  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8 7  
0
BEQZ  
00100  
rx  
3
offset  
8
5
31  
27 26  
21 20  
16 15  
8
7
5
4
0
EXTEND  
11110  
BEQZ  
00100  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
rx  
3
000  
3
offset[4:0]  
5
5
5
5
Description  
If the contents of general-purpose register rx is equal to zero, then the program branches to the  
target address with a delay of one instruction (or two pipeline cycles). See Section 5.3.4, Branch  
Instructions (16-Bit ISA), for pipeline delays. This instruction does not have a delay slot. If the  
branch is taken, the instruction that immediately follows this instruction is not executed. The target  
address is computed relative to the address of the immediately following instruction, i.e., PC+2  
when the instruction is not EXTENDED and PC+4 when EXTENDed.  
Since the 8-bit offset is shifted left by one bit, the branch range is -256 to +254. If the offset is  
outside this range, the instruction is EXTENDed to provide a 17-bit signed immediate in the range  
of -65536 to +65534. Whether EXTENDed or not, the target address is computed in the same  
manner.  
Exceptions  
None  
B-28  
Appendix B 16-Bit ISA Details  
Example  
BEQZ r2,SZERO  
Assume that this branch instruction resides at address 0x2000 and that label SZERO points to  
absolute address 0x1FFC. Then the assembler/linker turns this label into an offset operand of 0xFD  
(see the figure below). Thus the instruction code for this branch instruction becomes 0x22FD.  
If the contents of r2 are equal to zero, the processor transfers program control to address 0x1FFC.  
Otherwise, the program just continues to the next instruction at 0x2002.  
0x1FFC  
Branch Destination  
0x2000  
0x2002  
BEQZ  
r2, SZERO  
Next Instruction  
+
0xFFFF_FFFA  
The offset, 0xFD, is shifted left  
by one bit and sign-extended.  
B-29  
Appendix B 16-Bit ISA Details  
BEXT offset (base3), pos3  
Bit Extract  
Operation  
t8 ⇐ 31’b 000_0000_0000_0000_0000_0000_0000_0000 || {zero-extend (offset) + (base3)} [pos3]  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
offset  
[13:11]  
11 10  
8
7
5
4
0
EXTEND  
11110  
EXTENDED  
offset[10:5]  
6
base3  
2
11111  
5
101  
3
pos3  
3
offset[4:0]  
5
5
3
Description  
A bit specified by pos3 in a memory byte is copied into the least-significant bit (LSB) of general  
purpose register t8 (r24). The upper 31 bits of t8 are filled with zeros. The effective address is  
computed by zero-extending the 14-bit offset and adding the resultant value to the contents of a  
general-purpose register indicated by base3. The encoding used for base3 is as follows:  
base3  
01  
10  
GPR  
gp(r28)  
sp(r29)  
fp(r30)  
11  
With the 14-bit offset field, the offset range is 0 to +16383.  
Exceptions  
Address Error exception  
B-30  
Appendix B 16-Bit ISA Details  
Example  
Assume that the sp register (r29) contains 0x0000_0400 and that the byte position at address  
0x0404 contains 0xF2. Then, the instruction:  
BEXT 4(sp), 3  
loads r24 with 0x0000_0000.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r29  
+4  
11110010  
Bit 3 is loaded into r24.  
r24  
0x0000_0000  
B-31  
Appendix B 16-Bit ISA Details  
BEXT offset (r0), pos3  
Bit Extract  
Operation  
t8 ⇐ 31’b 000_0000_0000_0000_0000_0000_0000_0000 || {sign-extend (offset)} [pos3]  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
offset  
[13:11]  
11 10  
8
7
5
4
0
EXTEND  
11110  
EXTENDED  
offset[10:5]  
6
00  
2
11111  
5
101  
3
pos3  
3
offset[4:0]  
5
5
3
Description  
A bit specified by pos3 in a memory byte is copied into the least-significant bit (LSB) of general  
purpose register t8 (r24). The upper 31 bits of t8 are filled with zeros. The effective address is  
computed by sign-extending the 14-bit offset and adding the resultant value to the contents of  
general-purpose register r0, which is hardwired to a value of zero.  
With the 14-bit offset field, the offset range is -8192 to +8191.  
Exceptions  
Address Error exception  
Example  
Assume that the byte position at address 0x0404 contains 0xF2. Then, the instruction:  
BEXT 0x404(r0), 1  
loads r24 with 0x0000_0001.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
11110010  
0x404  
Target Address  
0x0000_0001  
Bit 1 is loaded into r24.  
r24  
B-32  
Appendix B 16-Bit ISA Details  
BEXT offset (fp), pos3  
Bit Extract  
Operation  
t8 ⇐ 31’b 000_0000_0000_0000_0000_0000_0000_0000 || {zero-extend (offset) + (fp)} [pos3]  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
bext  
101  
11111  
5
pos3  
3
offset[4:0]  
5
3
Description  
A bit specified by pos3 in a memory byte is copied into the least-significant bit (LSB) of general  
purpose register t8 (r24). The upper 31 bits of t8 are filled with zeros. The effective address is  
computed by zero-extending the 5-bit offset and adding the resultant value to the contents of the fp  
register (r30).  
With the 5-bit offset5 field, the offset range is 0 to +31.  
Exceptions  
Address Error exception  
Example  
Assume that the fp register (r30) contains 0x0000_0400 and that the byte position at address 0x0404  
contains 0xF2. Then, the instruction:  
BEXT 4(fp), 3  
loads r24 with 0x0000_0000.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r30  
+4  
11110010  
Bit 3 is loaded into r24.  
r24  
0x0000_0000  
B-33  
Appendix B 16-Bit ISA Details  
BFINS ry, rx, bit2, bit1  
Bit Field Insert  
Operation  
ry[bit2:bit1] ⇐ rx[bit2-bit1 : 0] ;  
Instruction Encoding  
31  
27 26 25  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
EXTENDED  
0
1
bit2  
5
bit1  
5
11101  
5
ry  
3
rx  
3
00111  
5
5
Description  
A bit field indicated by [(bit2 – bit1):0] in general-purpose register rx is copied into a location  
indicated by (bit2:bit1) in general-purpose register ry.  
Exceptions  
None  
Example  
Assume that general-purpose registers r4 and r5 contain 0x0123_4567 and 0x89AB_CDEF  
respectively. Then, the instruction:  
bfins r4, r5, 15, 8  
reads bits 7-0 in r5 and deposits them in bits 15-8 in r4, as shown below.  
7
0
Before  
r4 0000 0001 0010 0011 0100 0101 0110 0111 r5 1000 1001 1010 1011 1100 1101 1110 1111  
After  
r4 0000 0001 0010 0011 1110 1111 0110 0111  
15  
8
B-34  
Appendix B 16-Bit ISA Details  
BINS offset (base3), pos3  
Bit Insert  
Operation  
{zero-extend (offset) + (base3)} [pos3] ⇐ t8[0]  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
offset  
EXTENDED  
offset[10:5]  
6
base3  
2
11111  
5
011  
3
pos3  
3
offset[4:0]  
5
[13:11]  
3
5
Description  
The least-significant bit (LSB) of general-purpose register t8 (r24) is copied into a bit position  
indicated by pos3 in a memory byte. The effective address is computed by zero-extending the 14-bit  
offset and adding the resultant value to the contents of a general-purpose register indicated by base3.  
The encoding used for base3 is as follows:  
base3  
01  
10  
GPR  
gp(r28)  
sp(r29)  
fp(r30)  
11  
With the 14-bit offset field, the offset range is 0 to +16383.  
Exceptions  
Address Error exception  
B-35  
Appendix B 16-Bit ISA Details  
Example  
Assume that the sp register (r29) contains 0x0000_0400, that the byte position at address 0x0404  
contains 0xF2 and that r24 contains 0x0000_0001. Then, the instruction:  
BINS 4(sp), 2  
replaces bit 2 at address 0x0404 with a 1.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r29  
+4  
11110110  
The LSB of r24 is copied into bit 2.  
r24  
0x0000_0001  
B-36  
Appendix B 16-Bit ISA Details  
BINS offset (r0), pos3  
Bit Insert  
Operation  
{sign-extend (offset)} [pos3] ⇐ t8[0]  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
offset  
EXTENDED  
offset[10:5]  
6
00  
2
11111  
5
011  
3
pos3  
3
offset[4:0]  
5
[13:11]  
3
5
Description  
The least-significant bit (LSB) of general-purpose register t8 (r24) is copied into a bit position  
indicated by pos3 in a memory byte. The effective address is computed by sign-extending the 14-bit  
offset and adding the resultant value to the contents of general-purpose register r0, which is  
hardwired to a value of zero.  
With the 14-bit offset field, the offset range is -8192 to +8191.  
Exceptions  
Address Error exception  
Example  
Assume that the byte position at address 0x0404 contains 0xF2 and that r24 contains 0x0000_0000.  
Then, the instruction:  
BINS 0x404(r0), 1  
replaces bit 1 at address 0x0404 with a 0.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
11110000  
0x404  
Target Address  
0x0000_0000  
The LSB of r24 is copied into bit 1.  
r24  
B-37  
Appendix B 16-Bit ISA Details  
BINS offset (fp), pos3  
Bit Insert  
Operation  
{zero-extend (offset) + (fp)} [pos3] ⇐ t8[0]  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
11111  
011  
3
pos3  
3
offset[4:0]  
5
5
Description  
The least-significant bit (LSB) of general-purpose register t8 (r24) is copied into a bit position  
indicated by pos3 in a memory byte. The effective address is computed by zero-extending the 5-bit  
offset and adding the resultant value to the contents of the fp register (r30).  
With the 5-bit offset field, the offset range is 0 to +31.  
Exceptions  
Address Error exception  
Example  
Assume that the fp register (r30) contains 0x0000_0400, that the byte position at address 0x0404  
contains 0xF2 and that r24 contains 0x0000_0001. Then, the instruction:  
BINS 4(fp), 2  
replaces bit 2 at address 0x0404 with a 1.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r30  
+4  
11110110  
The LSB of r24 is copied into bit 2.  
r24  
0x0000_0001  
B-38  
Appendix B 16-Bit ISA Details  
BNEZ rx, offset  
Branch On Not Equal To Zero  
Operation  
if rx ≠ 0 then pc ⇐ pc + 2 + sign-extend (offset || 0)  
if rx ≠ 0 then pc ⇐ pc + 4 + sign-extend (offset || 0)  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8 7  
0
BNEZ  
00101  
rx  
3
offset  
8
5
31  
27 26  
21 20  
16 15  
8
7
5
4
0
EXTEND  
11110  
BNEZ  
00101  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
rx  
3
000  
3
offset[4:0]  
5
5
5
5
Description  
If the contents of general-purpose register rx is not equal to zero, then the program branches to the  
target address with a delay of one instruction (or two pipeline cycles). See Section 5.3.4, Branch  
Instructions (16-Bit ISA), for pipeline delays. This instruction does not have a delay slot. If the  
branch is taken, the instruction that immediately follows this instruction is not executed. The target  
address is computed relative to the address of the immediately following instruction, i.e., PC+2  
when the instruction is not EXTENDED and PC+4 when EXTENDed.  
With the 8-bit offset field, the branch range is -256 to +254. If the offset is outside this range, the  
instruction is EXTENDed to provide a 17-bit signed immediate in the range of -65536 to +65534.  
Whether EXTENDed or not, the target address is computed in the same manner.  
Exceptions  
None  
B-39  
Appendix B 16-Bit ISA Details  
Example  
BNEZ r2,SNOTZERO  
Assume that this branch instruction resides at address 0x2000 and that label SNOTZERO points to  
absolute address 0x1FFC. Then the assembler/linker turns this label into an offset operand of 0xFD  
(see the figure below). Thus the instruction code for this branch instruction becomes 0x2AFD.  
If the contents of r2 are not equal to zero, the processor transfers program control to address 0x1FFC.  
Otherwise, the program just continues to the next instruction at 0x2002.  
0x1FFC  
Branch Destination  
0x2000  
0x2002  
BNEZ  
r2, SNOTZERO  
Next Instruction  
+
0xFFFF_FFFA  
The offset, 0xFD, is shifted left  
by one bit and sign-extended.  
B-40  
Appendix B 16-Bit ISA Details  
BREAK code  
Breakpoint Exception  
Operation  
Breakpoint exception  
Instruction Encoding  
15  
11 10  
5 4  
0
RR  
BREAK  
00101  
code  
6
11101  
5
5
Description  
When this instruction is executed, a breakpoint exception occurs, immediately and unconditionally  
transferring control to the exception handler.  
The code field in the BREAK instruction is available for use as software parameters to pass  
additional information. The exception handler can retrieve it by loading the contents of the memory  
halfword containing the instruction. For more on this, see Section 9.1.11, Breakpoint Exception.  
Exceptions  
Breakpoint exception  
B-41  
Appendix B 16-Bit ISA Details  
BS1F ry, rx  
Bit Search One Forward  
Operation  
if rx == 0 then ry ⇐ 0 ;  
else ry ⇐ ( bit position of rx[bit position] == 1 ) + 1 ;  
Instruction Encoding  
31  
27 26  
22 21  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
EXTENDED  
10000  
5
000000  
6
11101  
5
ry  
3
rx  
3
00111  
5
5
Description  
General-purpose register rx is searched for the first set bit, starting from bit 0 towards bit 31. If a set  
bit is found in rx, its bit position (bit number plus 1) is placed into general-purpose register ry. If no  
set bit is found in rx, the value written to ry is 0.  
Exceptions  
None  
Example  
Assume that general-purpose register r4 contains 0x1234_1200 (bit 9 is set). Then, the instruction:  
BS1F r3, r4  
loads general-purpose register r3 with 0x0000_000A.  
r4  
0001  
0000  
0010  
0000  
0011  
0000  
0100  
0001  
0010  
0000  
0000  
0000  
1010  
r4 is searched for a 1,  
starting with the LSB.  
r3  
0000  
0000  
0000  
B-42  
Appendix B 16-Bit ISA Details  
BSET offset (base3), pos3  
Bit Set  
Operation  
{zero-extend (offset) + (base3)} [pos3] ⇐ 1  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
offset  
[13:11]  
EXTENDED  
offset[10:5]  
6
base3  
2
11111  
010  
3
pos3  
3
offset[4:0]  
5
5
3
5
Description  
A bit specified by pos3 in a memory byte is set. The effective address is computed by zero-extending  
the 14-bit offset and adding the resultant value to the contents of a general-purpose  
register indicated by base3. The encoding used for base3 is as follows:  
base3  
01  
10  
GPR  
gp(r28)  
sp(r29)  
fp(r30)  
11  
With the 14-bit offset field, the offset range is 0 to +16383.  
Exceptions  
Address Error exception  
B-43  
Appendix B 16-Bit ISA Details  
Example  
Assume that the sp register (r29) contains 0x0000_0400 and that the byte position at address  
0x0404 contains 0xF2. Then, the instruction:  
BSET 4(sp), 0  
sets bit 0 of byte data 0xF2 as shown below.  
Memory  
Byte  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r29  
+4  
11110011  
After  
11110010  
Before  
Bit 0 is set.  
B-44  
Appendix B 16-Bit ISA Details  
BSET offset (r0), pos3  
Bit Set  
Operation  
{sign-extend (offset)} [pos3] ⇐ 1  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
offset  
[13:11]  
EXTENDED  
offset[10:5]  
6
00  
2
11111  
010  
3
pos3  
3
offset[4:0]  
5
5
3
5
Description  
A bit specified by pos3 in a memory byte is negated and placed into the least-significant bit (LSB)  
of general-purpose register t8 (r24). The upper 31 bits of t8 are filled with zeros. The effective  
address is computed by sign-extending the 14-bit offset and adding the resultant value to the  
contents of general-purpose r0, which is hardwired to a value of zero.  
With the 14-bit offset field, the offset range is -8192 to +8191.  
Exceptions  
Address Error exception  
Example  
Assume that the byte position at address 0x0404 contains 0xF2. Then, the instruction:  
BSET 0x404(r0), 2  
sets bit 2 of byte data 0xF2 as shown below.  
Memory  
Byte  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x400  
0x401  
0x402  
0x403  
0x404  
11110110  
After  
11110010  
Before  
Target Address  
Bit 2 is set.  
B-45  
Appendix B 16-Bit ISA Details  
BSET offset (fp), pos3  
Bit Set  
Operation  
{zero-extend (offset) + (fp)} [pos3] ⇐ 1  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
bset  
010  
11111  
pos3  
3
offset[4:0]  
5
5
3
Description  
A bit specified by pos3 in a memory byte is set. The effective address is computed by zero-extending  
the 5-bit offset and adding the resultant value to the contents of the fp register (r30).  
With the 5-bit offset field, the offset range is 0 to +31.  
Exceptions  
Address Error exception  
Example  
Assume that the fp register (r30) contains 0x0000_0400 and that the byte position at address 0x0404  
contains 0xF2. Then, the instruction:  
BSET 4(fp), 0  
sets bit 0 of byte data 0xF2 as shown below.  
Memory  
Byte  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r30  
+4  
11110011  
After  
11110010  
Before  
Bit 0 is set.  
B-46  
Appendix B 16-Bit ISA Details  
BTEQZ offset  
Branch On T8 Equal To Zero  
Operation  
if t8 == 0 then pc ⇐ pc + 2 + sign-extend (offset || 0)  
if t8 == 0 then pc ⇐ pc + 4 + sign-extend (offset || 0)  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
8 7  
0
I8  
BTEQZ  
offset  
8
01100  
000  
3
5
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
I8  
BTEQZ  
000  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
000  
3
offset[4:0]  
01100  
5
5
5
3
5
Description  
If the contents of condition code register t8 (r24) is equal to zero, then the program branches to the  
target address with a delay of one instruction (or two pipeline cycles). See Section 5.3.4, Branch  
Instructions (16-Bit ISA), for pipeline delays. This instruction does not have a delay slot. If the  
branch is taken, the instruction that immediately follows this instruction is not executed. The target  
address is computed relative to the address of the immediately following instruction, i.e., PC+2  
when the instruction is not EXTENDED and PC+4 when EXTENDed.  
Since the 8-bit offset is shifted left by one bit, the branch range is -256 to +254. If the offset is  
outside this range, the instruction is EXTENDed to provide a 17-bit signed immediate in the range  
of -65536 to +65534. Whether EXTENDed or not, the target address is computed in the same  
manner.  
Exceptions  
None  
B-47  
Appendix B 16-Bit ISA Details  
Example  
BTEQZ SZERO  
Assume that this branch instruction resides at address 0x2000 and that label SZERO points to  
absolute address 0x1FFC. Then the assembler/linker turns this label into an offset operand of 0xFD  
(see the figure below). Thus the instruction code for this branch instruction becomes 0x60FD.  
If the contents of t8 are equal to zero, the processor transfers program control to address 0x1FFC.  
Otherwise, the program just continues to the next instruction at 0x2002.  
0x1FFC  
Branch Destination  
0x2000  
0x2002  
BTEQZ SZERO  
Next Instruction  
+
0xFFFF_FFFA  
The offset, 0xFD, is shifted left  
by one bit and sign-extended.  
B-48  
Appendix B 16-Bit ISA Details  
BTNEZ offset  
Branch On T8 Not Equal To Zero  
Operation  
if t8 ≠ 0 then pc ⇐ pc + 2 + sign-extend (offset || 0)  
if t8 ≠ 0 then pc ⇐ pc + 4 + sign-extend (offset || 0)  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
8 7  
0
I8  
BTNEZ  
offset  
8
01100  
001  
3
5
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
I8  
BTNEZ  
001  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
000  
3
offset[4:0]  
01100  
5
5
5
3
5
Description  
If the contents of condition code register t8 (r24) is not equal to zero, then the program branches to  
the target address with a delay of one instruction (or two pipeline cycles). See Section 5.3.4, Branch  
Instructions (16-Bit ISA), for pipeline delays. This instruction does not have a delay slot. If the  
branch is taken, the instruction that immediately follows this instruction is not executed. The target  
address is computed relative to the address of the immediately following instruction, i.e., PC+2  
when the instruction is not EXTENDED and PC+4 when EXTENDed.  
Since the 8-bit offset is shifted left by one bit, the branch range is -256 to +254. If the offset is  
outside this range, the instruction is EXTENDed to provide a 17-bit signed immediate in the range  
of -65536 to +65534. Whether EXTENDed or not, the target address is computed in the same  
manner.  
Exceptions  
None  
B-49  
Appendix B 16-Bit ISA Details  
Example  
BTNEZ SNOTZERO  
Assume that this branch instruction resides at address 0x2000 and that label SNOTZERO points to  
absolute address 0x1FFC. Then the assembler/linker turns this label into an offset operand of 0xFD  
(see the figure below). Thus the instruction code for this branch instruction becomes 0x61FD.  
If the contents of t8 are equal to zero, the processor transfers program control to address 0x1FFC.  
Otherwise, the program just continues to the next instruction at 0x2002.  
0x1FFC  
Branch Destination  
0x2000  
0x2002  
BTNEZ SNOTZERO  
Next Instruction  
+
0xFFFF_FFFA  
The offset, 0xFD, is shifted left  
by one bit and sign-extended.  
B-50  
Appendix B 16-Bit ISA Details  
BTST offset (base3), pos3  
Bit Test  
Operation  
t8 ⇐ 31’b 000_0000_0000_0000_0000_0000_0000_0000 || NOT ({zero-extend (offset) + (base3)}  
[pos3])  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
offset  
[13:11]  
11 10  
8
7
5
4
0
EXTEND  
11110  
EXTENDED  
offset[10:5]  
6
base3  
2
11111  
5
000  
3
pos3  
3
offset[4:0]  
5
5
3
Description  
A bit specified by pos3 in a memory byte is negated and placed into the least-significant bit (LSB)  
of general-purpose register t8 (r24). The upper 31 bits of t8 are filled with zeros. The effective  
address is computed by zero-extending the 14-bit offset and adding the resultant value to the  
contents of a general-purpose register indicated by base3. The encoding used for base3 is as  
follows:  
base3  
01  
10  
GPR  
gp (r28)  
sp (r29)  
fp (r30)  
11  
With the 14-bit offset field, the offset range is 0 to +16383.  
Exceptions  
Address Error exception  
B-51  
Appendix B 16-Bit ISA Details  
Example  
Assume that the sp register (r29) contains 0x0000_0400 and that the byte position at address  
0x0404 contains 0xF2. Then, the instruction:  
BTST 4(sp), 3  
loads r24 with 0x0000_0001.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r29  
+4  
11110010  
Bit 3 is negated and placed into r24.  
r24  
0x0000_0001  
B-52  
Appendix B 16-Bit ISA Details  
BTST offset (r0), pos3  
Bit Test  
Operation  
t8 ⇐ 31’b 000_0000_0000_0000_0000_0000_0000_0000 || NOT ({sign-extend (offset)} [pos3])  
Instruction Encoding  
31  
27 26  
21 20 19 18  
16 15  
offset  
[13:11]  
11 10  
8
7
5
4
0
EXTEND  
11110  
EXTENDED  
offset[10:5]  
6
00  
2
11111  
5
000  
3
pos3  
3
offset[4:0]  
5
5
3
Description  
A bit specified by pos3 in a memory byte is negated and placed into the least-significant bit (LSB)  
of general-purpose register t8 (r24). The upper 31 bits of t8 are filled with zeros. The effective  
address is computed by sign-extending the 14-bit offset and adding the resultant value to the  
contents of general-purpose r0, which is hardwired to a value of zero.  
With the 14-bit offset field, the offset range is -8192 to +8191.  
Exceptions  
Address Error exception  
Example  
Assume that the byte position at address 0x0404 contains 0xF2. Then, the instruction:  
BTST 0x404(r0), 1  
loads r24 with 0x0000_0000.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
11110010  
0x404  
Target Address  
0x0000_0000  
Bit 1 is negated and placed into r24.  
r24  
B-53  
Appendix B 16-Bit ISA Details  
BTST offset (fp), pos3  
Bit Test  
Operation  
t8 ⇐ 31’b 000_0000_0000_0000_0000_0000_0000_0000 || NOT ({zero-extend (offset) + (fp)}  
[pos3])  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
btst  
000  
11111  
5
pos3  
3
offset[4:0]  
5
3
Description  
A bit specified by pos3 in a memory byte is negated and placed into the least-significant bit (LSB)  
of general-purpose register t8 (r24). The upper 31 bits of t8 are filled with zeros. The effective  
address is computed by zero-extending the 5-bit offset and adding the resultant value to the contents  
of the fp register (r30).  
With the 5-bit offset field, the offset range is 0 to +31.  
Exceptions  
Address Error exception  
B-54  
Appendix B 16-Bit ISA Details  
Example  
Assume that the fp register (r30) contains 0x0000_0400 and that the byte position at address 0x0404  
contains 0xF2. Then, the instruction:  
BTST 4(fp), 3  
loads r24 with 0x0000_0001.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r30  
+4  
11110010  
Bit 3 is negated and placed into r24.  
r24  
0x0000_0001  
B-55  
Appendix B 16-Bit ISA Details  
CMP rx, ry  
Compare  
Operation  
if rx == ry then t8 ⇐ 0; else t8 ⇐ non-zero value  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
CMP  
rx  
3
ry  
3
11101  
01010  
5
5
Description  
The contents of general-purpose register rx is exclusive-ORed with the contents of general-purpose  
register ry. The result is placed into condition code register t8 (r24). In other words, if rx and ry are  
equal, t8 is loaded with a value of zero.  
Exceptions  
None  
B-56  
Appendix B 16-Bit ISA Details  
CMPI rx, immediate  
Compare Immediate  
Operation  
if rx == 016 || (immediate15..0) then t8 ⇐ 0; else t8 ⇐ non-zero value  
Instruction Encoding  
15  
11 10  
11 10  
8 7  
0
CMPI  
01110  
rx  
3
immediate  
8
5
31  
27 26  
21 20  
16 15  
8
7
5
4
0
EXTEND  
11110  
CMPI  
01110  
EXTENDED  
imm[10:5]  
6
imm[15:11]  
rx  
3
000  
3
imm[4:0]  
5
5
5
5
Description  
The 8-bit immediate is zero-extended and exclusive-ORed with the contents of general-purpose  
register rx. The result is placed into condition code register t8 (r24). In other words, if rx and  
immediate are equal, t8 is loaded with a value of zero.  
With the 8-bit immediate field, the immediate range is 0 to 255. If the immediate is larger than 255,  
the instruction is EXTENDed to provide a 16-bit unsigned immediate in the range of 0 to 65535.  
Exceptions  
None  
B-57  
Appendix B 16-Bit ISA Details  
DERET  
Debug Exception Return  
Operation  
pc ⇐ DEPC, Debug[DM] ⇐ 0, Debug[IEXI] ⇐ 0  
Instruction Encoding  
31  
27 26  
22 21  
16 15  
11 10  
5
4
0
EXTEND  
11110  
EXTENDED  
01000  
5
000000  
6
11101  
5
000000  
6
11111  
5
5
Description  
The DERET instruction is used to return control from a debug exception handler to a user program.  
This is accomplished by loading the contents of the DEPC register into the program counter (PC).  
See Section 9.3.6, Returning from Debug Exceptions, for details.  
The DERET instruction does not have a delay slot. It is executed with a delay of one instruction (or  
two pipeline cycles).  
The DERET instruction restores the ISA mode bit (bit 0) of the PC from bit 0 of the DEPC register,  
bringing the processor into the ISA mode that had been in effect before the debug exception was  
taken.  
The DERET instruction may not be in a jump or branch delay slot.  
The operation of the DERET instruction is unpredictable if the processor is not in Debug mode (i.e.,  
if the DM bit in the Debug register is cleared).  
Typically, the DEPC register automatically captures the address of the exception-causing instruction  
on a debug exception. If you want to use the MTC0 instruction to load the DEPC register with a  
return address, the debug exception handler must execute at least two instructions before issuing the  
DERET instruction.  
Exceptions  
None  
B-58  
Appendix B 16-Bit ISA Details  
DI  
Disable Interrupt  
Operation  
Status[IE] ⇐ 0  
Instruction Encoding  
15  
11 10  
8
7
1
6
0
RRR  
000  
3
0000000  
7
11100  
5
1
Description  
The IE bit in the Status register is cleared.  
Exceptions  
Coprocessor Unusable exception  
B-59  
Appendix B 16-Bit ISA Details  
DIV rx, ry  
Divide  
Operation  
LO ⇐ rx ÷ ry;  
HI ⇐ rx MOD ry  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
DIV  
rx  
3
ry  
3
11101  
11010  
5
5
Description  
The contents of general-purpose register rx is divided by the contents of general-purpose register ry.  
Both operands are treated as signed integers. The quotient is placed into register LO and the  
remainder is placed into register HI. The DIV instruction never causes an Integer Overflow  
exception.  
The result of the DIV instruction is undefined if the divisor is zero. Typically, it is necessary to  
check for a zero divisor and an overflow condition after a DIV instruction.  
Any divide instruction is transferred to the dedicated divide unit as remaining instructions continue  
through the pipeline. The divide unit keeps running even when delay cycles and exceptions occur.  
If the divide instruction is followed by an MFHI, MFLO, MADD, MADDU, MSUB or MSUBU  
instruction before the quotient and the remainder are available, the pipeline stalls until they do  
become available (see Section 5.5, Divide Instructions).  
Exceptions  
None  
B-60  
Appendix B 16-Bit ISA Details  
DIVE rx, ry  
Divide Exception  
Operation  
LO ⇐ rx ÷ ry  
HI ⇐ rx MOD ry  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
DIVE  
11110  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register rx is divided by the contents of general-purpose register ry.  
Both operands are treated as signed integers. The quotient is placed into register LO and the  
remainder is placed into register HI.  
An Integer Overflow exception occurs if divide-by-zero or overflow conditions are detected.  
Any divide instruction is transferred to the dedicated divide unit as remaining instructions continue  
through the pipeline. The divide unit keeps running even when delay cycles and exceptions occur.  
If the divide instruction is followed by an MFHI, MFLO, MADD, MADDU, MSUB or MSUBU  
instruction before the quotient and the remainder are available, the pipeline stalls until they do  
become available (see Section 5.5, Divide Instructions).  
Exceptions  
Integer Overflow exception  
B-61  
Appendix B 16-Bit ISA Details  
DIVEU rx, ry  
Divide Exception Unsigned  
Operation  
LO ⇐ rx ÷ ry  
HI ⇐ rx MOD ry  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
DIVEU  
11111  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register rx is divided by the contents of general-purpose register ry.  
Both operands are treated as unsigned integers. The quotient is placed into register LO and the  
remainder is placed into register HI.  
An Integer Overflow exception occurs if divide-by-zero is detected.  
Any divide instruction is transferred to the dedicated divide unit as remaining instructions continue  
through the pipeline. The divide unit keeps running even when delay cycles and exceptions occur.  
If the divide instruction is followed by an MFHI, MFLO, MADD, MADDU, MSUB or MSUBU  
instruction before the quotient and the remainder are available, the pipeline stalls until they do  
become available (see Section 5.5, Divide Instructions).  
Exceptions  
Integer Overflow exception  
B-62  
Appendix B 16-Bit ISA Details  
DIVU rx, ry  
Divide Unsigned  
Operation  
LO ⇐ rx ÷ ry;  
HI ⇐ rx MOD ry  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
DIV  
rx  
3
ry  
3
11101  
11011  
5
5
Description  
The contents of general-purpose register rx is divided by the contents of general-purpose register ry.  
Both operands are treated as unsigned integers. The quotient is placed into register LO and the  
remainder is placed into register HI. The DIV instruction never causes Integer Overflow exceptions.  
The only difference between the DIV instruction and this instruction is that this instruction treats  
both operands as unsigned integers.  
Exceptions  
None  
B-63  
Appendix B 16-Bit ISA Details  
EI  
Enable Interrupt  
Operation  
Status[IE] ⇐ 1  
Instruction Encoding  
15  
11 10  
8
7
1
1
6
0
RRR  
001  
3
0000000  
7
11100  
5
Description  
The IE bit in the Status register is set.  
Exceptions  
Coprocessor Unusable exception  
B-64  
Appendix B 16-Bit ISA Details  
ERET  
Exception Return  
Operation  
if Status[ERL] = 1 then pc ⇐ Error EPC  
Status[ERL] ⇐ 0  
else pc ⇐ EPC  
Status[EXL] ⇐ 0  
SSCR[CSS] ⇐ SSCR[PSS]  
Instruction Encoding  
31  
27 26  
22 21  
16 15  
11 10  
5
4
0
EXTEND  
11110  
EXTENDED  
01000  
000000  
6
11101  
5
000000  
6
11000  
5
5
5
Description  
ERET is an instruction for returning from an interrupt, exception or error trap.  
The ERET instruction does not have a delay slot. It is executed with a delay of one instruction (two  
pipeline cycles).  
The ERET instruction restores the ISA mode bit (bit 0) of the PC from bit 0 of the ErrorEPC  
register, bringing the processor into the ISA mode that had been in effect before the exception was  
taken.  
An attempt to execute the ERET instruction in User mode when the CU0 bit in the Status register is  
cleared causes a Coprocessor Unusable exception. If you want to use the MTC0 instruction to load  
the ErrorEPC or EPC register with a return address or if you have modified the contents of the  
Status register, the exception handler must execute at least two instructions before issuing the ERET  
instruction.  
If the ERL bit in the Status register is set, ERET restores the PC from the ErrorPC register and then  
clears the ERL bit. Otherwise, ERET restores the PC from the EPC register and then clears the EXL  
bit.  
Also, the PSS field in the SSCR register is popped to the CSS field.  
ERET must not be placed in a branch or jump delay slot.  
B-65  
Appendix B 16-Bit ISA Details  
Exceptions  
Coprocessor Unusable exception  
B-66  
Appendix B 16-Bit ISA Details  
JAL target  
Jump And Link  
Operation  
ra ⇐ pc + 7; pc ⇐ pc[31:28] || target || 00  
Instruction Encoding  
31  
27 26 25  
21 20  
16 15  
0
JAL  
x
target  
target  
target  
[15:0]  
00011  
0
[20:16]  
[25:21]  
5
1
5
5
16  
Description  
Although this instruction is in the 16-bit ISA, it is 32-bits wide. The program unconditionally jumps  
to the target address with a delay of one instruction (or two pipeline cycles). See Section 5.3.3,  
Jump Instructions (16-Bit ISA). The target address is computed relative to the address of the  
instruction in the jump delay slot (PC+4). The 26-bit target is shifted left by two bits and combined  
with the four most-significant bits of PC+4 to form the target address. The JAL instruction never  
toggles the ISA mode bit of the program counter (PC).  
The address of the instruction after the jump delay slot is saved in the link register, ra (r31). The  
ISA mode specifier (i.e., a 1 for the 16-bit ISA mode) is saved in the least-significant bit of ra.  
B-67  
Appendix B 16-Bit ISA Details  
Example  
JAL PSUB  
Assume that this jump instruction resides at address 0x2000 and that label PSUB points to absolute  
address 0x2_4000. Then the assembler/linker turns this label into a target operand of 0x1_2000 (see  
the figure below).  
The processor unconditionally transfers program control to address 0x2_4000. The jump takes  
effect after the instruction in the jump delay slot is executed. The address of the instruction after the  
jump delay slot is saved in ra, combined with the ISA mode bit value; thus the ra value becomes  
0x0000_2007.  
0x2000  
JAL PSUB  
0x2002  
0x2004  
0x2006  
16-Bit ISA Mode  
Jump Delay Slot  
0 (Four MSBs of the Delay Slot Address)  
0000 0000 0000 0000 0010 0000 0000 001 1  
ra  
+
×
0x002_4000  
1
The target operand, 0x1_2000,  
is shifted left by two bits.  
16-Bit ISA Mode  
0x2_4000  
Jump Destination  
16-Bit ISA Mode  
B-68  
Appendix B 16-Bit ISA Details  
JALR ra, rx  
Jump And Link Register  
Operation  
ra ⇐ pc + 5; pc ⇐ rx  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
JALR  
rx  
3
010  
3
11101  
00000  
5
5
Description  
The program unconditionally jumps to the address contained in general-purpose register rx, with the  
least-significant bit cleared, with a delay of one instruction (or two pipeline cycles). The  
least-significant bit of rx is interpreted as the ISA mode specifier. The address of the instruction after  
the jump delay slot is saved in the link register, ra (r31), combined with the value of the ISA mode  
that was in effect before the jump.  
In 32-bit ISA mode, all instructions must be aligned on word boundaries. Therefore, when jumping  
to a 32-bit routine, the two low-order bits of the target register (rx) must be zero. If the two low-order  
bits are not zero, an Address Error exception will occur when the processor fetches the  
instruction at the jump destination.  
Exceptions  
None  
B-69  
Appendix B 16-Bit ISA Details  
Example  
Assume that register r2 contains 0x0012_3458 and that the following jump instruction resides at  
address 0x0000_2000. Then, executing the instruction:  
JALR ra,r2  
transfers program control to address 0x0012_3458. Since r2 has the least-significant bit cleared, the  
ISA mode bit toggles to 0 after the jump, bringing the processor into 32-bit ISA mode. The address  
of the instruction after the jump delay slot is saved in ra, combined with the ISA mode bit value;  
thus the ra value becomes 0x0000_2005.  
0x2000  
JALR  
ra, r2  
0x2002  
0x2004  
16-Bit ISA Mode  
Jump Delay Slot  
0000 0000 0000 0000 0010 0000 0000 010 1  
ra  
0x12_3458  
Jump Destination  
×
32-Bit ISA Mode  
1
16-Bit ISA Mode  
B-70  
Appendix B 16-Bit ISA Details  
JALRC ra, rx  
Jump And Link Register, Compact  
Operation  
ra ⇐ pc + 3; pc ⇐ rx  
Instruction Encoding  
15  
11 10  
8
7
6
5
4
0
RR  
nd  
1
l
ra J (AL) R (C)  
rx  
3
11101  
1
0
1
00000  
5
5
1
1
Description  
The program unconditionally jumps to the address contained in general-purpose register rx, with the  
least-significant bit cleared, with a delay of one instruction (or two pipeline cycles). This instruction  
does not have a delay slot; the address of the instruction following this instruction is saved in the  
link register, ra (r31), combined with the ISA mode bit.  
In 32-bit ISA mode, all instructions must be aligned on word boundaries. Therefore, when jumping  
to a 32-bit routine, the two low-order bits of the target register (rx) must be zero. If the two low order  
bits are not zero, an Address Error exception will occur when the processor fetches the  
instruction at the jump destination.  
Exceptions  
None  
B-71  
Appendix B 16-Bit ISA Details  
Example  
Assume that register r2 contains 0x0012_3458 and that the following jump instruction resides at  
address 0x0000_2000. Then, executing the instruction:  
JALRC ra,r2  
transfers program control to address 0x0012_3458. Since r2 has the least-significant bit cleared, the  
ISA mode bit toggles to 0 after the jump, bringing the processor into 32-bit ISA mode. The address  
of the instruction after this instruction is saved in ra, combined with the ISA mode bit value; thus  
the ra value becomes 0x0000_2003.  
0x2000  
0x2002  
0x2004  
JALRC  
ra, r2  
16-Bit ISA Mode  
Next Instruction  
0000 0000 0000 0000 0010 0000 0000 001 1  
ra  
0x12_3458  
Jump Destination  
×
32-Bit ISA Mode  
1
16-Bit ISA Mode  
B-72  
Appendix B 16-Bit ISA Details  
JALX target  
Jump And Link eXchange  
Operation  
ra ⇐ pc + 7; pc[31:1] ⇐ pc[31:28] || target || 00; pc[0] ⇐ NOT pc[0]  
Instruction Encoding  
31  
27 26 25  
21 20  
16 15  
0
JAL  
x
target  
target  
target  
[15:0]  
00011  
1
[20:16]  
[25:21]  
5
1
5
5
16  
Description  
Although this instruction is in the 16-bit ISA, it is 32-bits wide. The program unconditionally jumps  
to the target address with a delay of one instruction (or two pipeline cycles). See Section 5.3.3,  
Jump Instructions (16-Bit ISA). The target address is computed relative to the address of the  
instruction in the jump delay slot (PC+4). The 26-bit target is shifted left by two bits and combined  
with the four most-significant bits of PC+4 to form the target address. The JALX instruction  
unconditionally toggles the ISA mode bit of the program counter (PC).  
The address of the instruction after the jump delay slot is saved in the link register, ra (r31). The  
least-significant bit of ra stores the ISA mode bit that was in effect before the jump.  
Exceptions  
None  
B-73  
Appendix B 16-Bit ISA Details  
Example  
JALX PSUB  
Assume that this jump instruction resides at address 0x0000_2000 and that label PSUB points to  
absolute address 0x2_4000. Then, the assembler/linker turns this label into a target operand of  
0x1_2000 (see the figure below).  
The processor unconditionally transfers program control to address 0x2_4000. The jump takes  
effect after the instruction in the jump delay slot is executed. The ISA mode bit unconditionally  
toggles, bringing the processor into 32-bit ISA mode. The address of the instruction after the jump  
delay slot is saved in ra, combined with the ISA mode bit value; thus the ra value becomes  
0x0000_2007.  
0x2000  
JALX PSUB  
0x2002  
0x2004  
0x2006  
16-Bit ISA Mode  
Jump Delay Slot  
0 (Four MSBs of the Delay Slot Address)  
0000 0000 0000 0000 0010 0000 0000 001 1  
ra  
+
×
0x002_4000  
1
The target operand, 0x1_2000,  
is shifted left by two bits.  
16-Bit ISA Mode  
0x2_4000  
Jump Destination  
32-Bit ISA Mode  
B-74  
Appendix B 16-Bit ISA Details  
JR rx  
Jump Register  
Operation  
pc ⇐ rx  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
JR  
rx  
3
000  
3
11101  
00000  
5
5
Description  
The program unconditionally jumps to the address contained in general-purpose register rx, with the  
least-significant bit cleared, with a delay of one instruction (or two pipeline cycles). The  
least-significant bit of rx is interpreted as the ISA mode specifier.  
In 32-bit ISA mode, all instructions must be aligned on word boundaries. Therefore, when jumping  
to a 32-bit routine, the two low-order bits of the target register (rx) must be zero. If the two low-order  
bits are not zero, an Address Error exception will occur when the processor fetches the  
instruction at the jump destination.  
Exceptions  
None  
B-75  
Appendix B 16-Bit ISA Details  
Example  
Assume that register r2 contains 0x0012_3458. Then, executing the instruction:  
JR r2  
transfers program control to address 0x0012_3458. Since r2 has the least-significant bit cleared, the  
processor switches to 32-bit ISA mode. The jump takes effect after the instruction in the jump delay  
slot is executed.  
0x2000  
JR r2  
0x2002  
0x2004  
16-Bit ISA Mode  
Jump Delay Slot  
0x12_3458  
Jump Destination  
32-Bit ISA Mode  
B-76  
Appendix B 16-Bit ISA Details  
JR ra  
Jump Register  
Operation  
pc ⇐ ra  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
JR  
000  
3
001  
3
11101  
00000  
5
5
Description  
The program unconditionally jumps to the address contained in the link register, ra (r31), with the  
least-significant bit cleared, with a delay of one instruction (or two pipeline cycles). The  
least-significant bit of ra is interpreted as the ISA mode specifier.  
Exceptions  
None  
B-77  
Appendix B 16-Bit ISA Details  
Example  
In the following example, the JALR instruction in a 32-bit routine transfers program control to a 16-  
bit routine. At the end of the 16-bit routine, the JR instruction restores the return address into the  
program counter (PC) from the link register, ra (r31). Since the ISA mode has been saved in the  
least-significant bit of ra by the 32-bit JALR instruction, executing the JR instruction at the end of  
the 16-bit routine restores it into the PC, causing the processor to revert to 32-bit ISA mode.  
0x2000  
JALR r2  
0x2004  
0x2008  
32-Bit ISA Mode  
Jump Delay Slot  
Return Point  
Jump to a 16-bit  
routine through the  
JALR instruction  
Return to the 32-bit  
routine through the  
JR instruction  
0000 0000 0000 0000 0010 0000 0000 100 0  
ra  
×
0
32-Bit ISA Mode  
0x12_3456  
Jump Destination  
‚
‚
‚
16-Bit ISA Mode  
JR  
ra  
B-78  
Appendix B 16-Bit ISA Details  
JRC ra  
Jump Register ra, Compact  
Operation  
pc ⇐ ra  
Instruction Encoding  
15  
11 10  
8
7
6
5
4
0
RR  
nd  
1
l
ra J (AL) R (C)  
000  
3
11101  
0
1
1
00000  
5
5
1
1
Description  
The program unconditionally jumps to the address contained in the link register, ra (r31), with the  
least-significant bit cleared, with a delay of one instruction (or two pipeline cycles). The  
least-significant bit of ra is interpreted as the ISA mode specifier.  
This instruction does not have a delay slot.  
Exceptions  
None  
B-79  
Appendix B 16-Bit ISA Details  
Example  
In the following example, the JALR instruction in a 32-bit routine transfers program control to a 16-  
bit routine. At the end of the 16-bit routine, the JRC instruction restores the return address into the  
program counter (PC) from the link register, ra (r31). Since the ISA mode has been saved in the  
least-significant bit of ra by the 32-bit JALR instruction, executing the JRC instruction at the end of  
the 16-bit routine restores it into the PC, causing the processor to revert to 32-bit ISA mode.  
0x2000  
JALR r2  
0x2004  
0x2008  
32-Bit ISA Mode  
Jump Delay Slot  
Return Point  
Jump to a 16-bit  
routine through the  
JALR instruction  
Return to the 32-bit  
routine through the  
JR instruction  
0000 0000 0000 0000 0010 0000 0000 100 0  
ra  
×
0
32-Bit ISA Mode  
0x12_3456  
Jump Destination  
‚
‚
‚
16-Bit ISA Mode  
JRC  
ra  
B-80  
Appendix B 16-Bit ISA Details  
JRC rx  
Jump Register, Compact  
Operation  
pc ⇐ rx  
Instruction Encoding  
15  
11 10  
8
7
6
5
4
0
RR  
nd  
1
l
ra J (AL) R (C)  
rx  
3
11101  
0
0
1
00000  
5
5
1
1
Description  
The program unconditionally jumps to the address contained in general-purpose register rx, with the  
least-significant bit cleared, with a delay of one instruction (or two pipeline cycles). The  
least-significant bit of rx is interpreted as the ISA mode specifier.  
This instruction does not have a delay slot.  
In 32-bit ISA mode, all instructions must be aligned on word boundaries. Therefore, when jumping  
to a 32-bit routine, the two low-order bits of the target register (rx) must be zero. If the two low-order  
bits are not zero, an Address Error exception will occur when the processor fetches the  
instruction at the jump destination.  
Exceptions  
None  
B-81  
Appendix B 16-Bit ISA Details  
Example  
Assume that register r2 contains 0x0012_3458. Then, executing the instruction:  
JRC r2  
transfers program control to address 0x0012_3458. Since r2 has the least-significant bit cleared, the  
ISA mode bit toggles to 0 after the jump, bringing the processor into 32-bit ISA mode. The  
instruction following this instruction is not executed.  
0x2000  
JRC  
r2  
0x2002  
16-Bit ISA Mode  
Next Instruction  
0x12_3458  
Jump Destination  
32-Bit ISA Mode  
B-82  
Appendix B 16-Bit ISA Details  
LB ry, offset (base)  
Load Byte  
Operation  
ry = {zero-extend (offset) + (base)}  
ry = {sign-extend (offset) + (base)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
base  
8 7  
5 4  
0
LB  
ry  
3
offset  
5
10000  
5
3
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
LB  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
base  
3
ry  
3
offset[4:0]  
5
10000  
5
5
5
Description  
The 5-bit immediate offset is zero-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The byte in memory addressed by the EA is sign-extended  
and loaded into general-purpose register ry.  
With the 5-bit offset field, the offset range is 0 to 31. If the offset is outside this range, the  
instruction is EXTENDed to provide a 16-bit signed immediate in the range of -32768 to +32767.  
Exceptions  
Address Error exception  
B-83  
Appendix B 16-Bit ISA Details  
Example  
Assume that register r2 contains 0x0000_0400 and that the memory location at address 0x404  
contains 0xF2. Then, executing the instruction:  
LB r3,4(r2)  
loads register r3 with 0xFFFF_FFF2.  
Memory  
Byte  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
r2  
+4  
11110010  
Memory  
1 Byte  
Ø
CPU  
Register  
Sign-Extended  
Load (Sign-Extended)  
r3  
0xFFFF_FFF2  
B-84  
Appendix B 16-Bit ISA Details  
LBU ry, offset (base)  
Load Byte Unsigned  
Operation  
ry = {zero-extend (offset) + (base)}  
ry = {sign-extend (offset) + (base)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
base  
8 7  
5 4  
0
LBU  
ry  
3
offset  
5
10100  
5
3
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
LBU  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
base  
3
ry  
3
offset[4:0]  
5
10100  
5
5
5
Description  
The 5-bit immediate offset is zero-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The byte in memory addressed by the EA is zero-extended  
and loaded into general-purpose register ry.  
With the 5-bit offset field, the offset range is 0 to 31. If the offset is outside this range, the  
instruction is EXTENDed to provide a 16-bit signed immediate in the range of -32768 to +32767.  
Exceptions  
Address Error exception  
B-85  
Appendix B 16-Bit ISA Details  
Example  
Assume that register r2 contains 0x0000_0400 and that the memory location at address 0x404  
contains 0xF2. Then, executing the instruction:  
LBU r3,4(r2)  
loads register r3 with 0x0000_00F2.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r2  
+4  
11110010  
Memory  
1 Byte  
Ø
CPU  
Register  
Zero-Extended  
Load (Zero-Extended)  
r3  
0x0000_00F2  
B-86  
Appendix B 16-Bit ISA Details  
LBU ry, offset (fp)  
Load Byte Unsigned  
Operation  
ry = {zero-extend (offset) + (fp)}  
(EXTENDED)  
ry = {sign-extend (offset) + (fp)}  
Instruction Encoding  
15  
11 10  
11 10  
8
8
7
0
1
6
6
0
0
FP-B  
ry  
3
offset[6:0]  
7
00111  
5
31  
27 26  
21 20  
16 15  
7
0
1
5
4
EXTEND  
11110  
offset[10:5]  
6
offset[15:11]  
00111  
5
ry  
3
00  
offset[4:0]  
EXTENDED  
5
5
2
5
Description  
The 7-bit immediate offset is zero-extended and added to the contents of the fp register (r30) to form  
an effective address (EA). The byte in memory addressed by the EA is zero-extended and loaded  
into general-purpose register ry.  
With the 7-bit offset field, the offset range is 0 to 127. If the offset is outside this range, the  
instruction is EXTENDed to provide a 16-bit signed immediate in the range of -32768 to +32767.  
Exceptions  
Address Error exception  
B-87  
Appendix B 16-Bit ISA Details  
Example  
Assume that fp register (r30) contains 0x0000_0400 and that the memory location at address 0x404  
contains 0xF2. Then, executing the instruction:  
LBU r3,4(fp)  
loads register r3 with 0x0000_00F2.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r30  
+4  
11110010  
Memory  
1 Byte  
Ø
CPU  
Register  
Zero-Extended  
Load (Zero-Extended)  
r3  
0x0000_00F2  
B-88  
Appendix B 16-Bit ISA Details  
LBU ry, offset (sp)  
Load Byte Unsigned  
Operation  
ry = {zero-extend (offset) + (sp)}  
ry = {sign-extend (offset) + (sp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8
8
7
0
1
6
6
0
0
SP-B  
01111  
ry  
3
offset[6:0]  
7
5
31  
27 26  
21 20  
16 15  
7
0
1
5
4
EXTEND  
11110  
offset[10:5]  
6
offset[15:11]  
01111  
5
ry  
3
00  
offset[4:0]  
EXTENDED  
5
5
2
5
Description  
The 7-bit immediate offset is zero-extended and added to the contents of the sp register (r29) to  
form an effective address (EA). The byte in memory addressed by the EA is zero-extended and  
loaded into general-purpose register ry.  
With the 7-bit offset field, the offset range is 0 to 127. If the offset is outside this range, the  
instruction is EXTENDed to provide a 16-bit signed immediate in the range of -32768 to +32767.  
Exceptions  
Address Error exception  
B-89  
Appendix B 16-Bit ISA Details  
Example  
Assume that sp register (r29) contains 0x0000_0400 and that the memory location at address x404  
contains 0xF2. Then, executing the instruction:  
LBU r3,4(sp)  
loads register r3 with 0x0000_00F2.  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x0000_0400  
r29  
+4  
11110010  
Memory  
1 Byte  
Ø
CPU  
Register  
Zero-Extended  
Load (Zero-Extended)  
r3  
0x0000_00F2  
B-90  
Appendix B 16-Bit ISA Details  
LH ry, offset (base)  
Load Halfword  
Operation  
ry ⇐ {zero-extend (offset || 0) + (base)}  
ry ⇐ {sign-extend (offset) + (base)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
base  
8 7  
5 4  
0
LH  
ry  
3
offset  
5
10001  
5
3
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
LH  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
base  
3
ry  
3
offset[4:0]  
5
10001  
5
5
5
Description  
The 5-bit immediate offset is shifted left by one bit, zero-extended and added to the contents of  
general-purpose register base to form an effective address (EA). The halfword in memory addressed  
by the EA is sign-extended and loaded into general-purpose register ry.  
Since the 5-bit offset is shifted left by one bit, the offset range is 0 to 62, in increments of two. If the  
offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate in  
the range of -32768 to +32767. When EXTENDed, the offset operand is not shifted at all.  
Exceptions  
Address Error exception  
B-91  
Appendix B 16-Bit ISA Details  
Example  
LH r3,4(r2)  
Assume that register r2 contains 0x0000_0400 and that the memory locations at addresses 0x404  
and 0x405 contain 0xFF and 0x02 respectively. Since the offset value is shifted left by one bit by  
the processor hardware, the assembler/linker turns the specified offset (4 or binary 0100) into a code  
of 2 (binary 0010). Thus the instruction code for this load instruction becomes 0x8A62.  
This load instruction loads register r3 with 0xFFFF_FF02 in big-endian mode and with  
0x0000_02FF in little-endian mode.  
Memory  
Byte  
Halfword Boundary  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
r2  
+4  
Halfword Boundary  
Halfword Boundary  
Memory  
The offset, 2, is  
shifted left by 1 bit.  
11111111  
0x404  
0x405  
00000010  
Halfword  
r3  
r3  
0xFFFF_FF02  
Big-Endian  
Load (Sign-Extended)  
Ø
CPU  
Register  
Sign-Extended  
0x0000_02FF  
Little-Endian  
B-92  
Appendix B 16-Bit ISA Details  
LHU ry, offset (base)  
Load Halfword Unsigned  
Operation  
ry ⇐ {zero-extend (offset || 0) + (base)}  
ry ⇐ {sign-extend (offset) + (base)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
base  
8 7  
5 4  
0
LHU  
ry  
3
offset  
5
10101  
5
3
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
LHU  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
base  
3
ry  
3
offset[4:0]  
5
10101  
5
5
5
Description  
The 5-bit immediate offset is shifted left by one bit, zero-extended and added to the contents of  
general-purpose register base to form an effective address (EA). The halfword in memory addressed  
by the EA is zero-extended and loaded into general-purpose register ry.  
Since the 5-bit offset is shifted left by one bit, the offset range is 0 to 62, in increments of two. If the  
offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate in  
the range of -32768 to +32767. When EXTENDed, the offset operand is not shifted at all.  
Exceptions  
Address Error exception  
B-93  
Appendix B 16-Bit ISA Details  
Example  
LHU r3,4(r2)  
Assume that register r2 contains 0x0000_0400 and that the memory locations at addresses 0x404  
and 0x405 contain 0xFF and 0x02 respectively. Since the offset value is shifted left by one bit by  
the processor hardware, the assembler/linker turns the specified offset (4 or binary 0100) into a code  
of 2 (binary 0010). Thus the instruction code for this load instruction becomes 0xAA62.  
This load instruction loads register r3 with 0x0000_FF02 in big-endian mode and with  
0x0000_02FF in little-endian mode.  
Memory  
Byte  
Halfword Boundary  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
r2  
+4  
Halfword Boundary  
Halfword Boundary  
Memory  
The offset, 2, is  
shifted left by 1 bit.  
11111111  
0x404  
0x405  
00000010  
Halfword  
r3  
r3  
0x0000_FF02  
Big-Endian  
Load (Zero-Extended)  
Ø
CPU  
Register  
Zero-Extended  
0x0000_02FF  
Little-Endian  
B-94  
Appendix B 16-Bit ISA Details  
LHU ry, offset (fp)  
Load Halfword Unsigned  
Operation  
ry ⇐ {zero-extend (offset || 0) + (fp)}  
ry ⇐ {sign-extend (offset || 0) + (fp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8
8
7
0
1
6
6
1
1
0
1
1
FP-SP-H  
10111  
ry  
3
offset[6:1]  
6
5
31  
27 26  
21 20  
16 15  
7
0
1
5
4
0
1
1
EXTEND  
11110  
offset[10:5]  
6
offset[15:11]  
10111  
5
ry  
3
00  
offset[4:1]  
EXTENDED  
5
5
2
4
Description  
The 6-bit immediate offset is shifted left by one bit, zero-extended and added to the contents of the  
fp register (r30) to form an effective address (EA). The halfword in memory addressed by the EA is  
zero-extended and loaded into general-purpose register ry.  
Since the 6-bit offset is shifted left by one bit, the offset range is 0 to 126, in increments of two. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate.  
When EXTENDed, the offset operand is shifted left by one bit to allow an offset of -32768 to  
+32766.  
Exceptions  
Address Error exception  
B-95  
Appendix B 16-Bit ISA Details  
Example  
LHU r3,4(fp)  
Assume that the fp register (r30) contains 0x0000_0400 and that the memory locations at addresses  
0x404 and 0x405 contain 0xFF and 0x02 respectively. Since the offset value is shifted left by one  
bit by the processor hardware, the assembler/linker turns the specified offset (4 or binary 0100) into  
a code of 2 (binary 0010). Thus the instruction code for this load instruction becomes 0xBB05.  
This load instruction loads register r3 with 0x0000_FF02 in big-endian mode and with  
0x0000_02FF in little-endian mode.  
Memory  
Byte  
Halfword Boundary  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
r30  
+4  
Halfword Boundary  
Halfword Boundary  
Memory  
The offset, 2, is  
shifted left by 1 bit.  
11111111  
0x404  
0x405  
00000010  
Halfword  
r3  
r3  
0x0000_FF02  
Big-Endian  
Load (Zero-Extended)  
Ø
CPU  
Register  
Zero-Extended  
0x0000_02FF  
Little-Endian  
B-96  
Appendix B 16-Bit ISA Details  
LHU ry, offset (sp)  
Load Halfword Unsigned  
Operation  
ry ⇐ {zero-extend (offset || 0) + (sp)}  
ry ⇐ {sign-extend (offset || 0) + (sp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8
8
7
0
1
6
6
1
1
0
0
1
FP-SP-H  
10111  
ry  
3
offset[6:1]  
6
5
31  
27 26  
21 20  
16 15  
7
0
1
5
4
0
0
1
EXTEND  
11110  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
10111  
5
rt8  
3
00  
offset[4:1]  
5
5
2
4
Description  
The 6-bit immediate offset is shifted left by one bit, zero-extended and added to the contents of the  
sp register (r29) to form an effective address (EA). The halfword in memory addressed by the EA is  
zero-extended and loaded into general-purpose register ry.  
Since the 6-bit offset is shifted left by one bit, the offset range is 0 to 126, in increments of two. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate.  
When EXTENDed, the offset operand is shifted left by one bit to allow an offset of -32768 to  
+32766.  
Exceptions  
Address Error exception  
B-97  
Appendix B 16-Bit ISA Details  
Example  
LHU r3,4(sp)  
Assume that the sp register (r29) contains 0x0000_0400 and that the memory locations at addresses  
0x404 and 0x405 contain 0xFF and 0x02 respectively. Since the offset value is shifted left by one  
bit by the processor hardware, the assembler/linker turns the specified offset (4 or binary 0100) into  
a code of 2 (binary 0010). Thus the instruction code for this load instruction becomes 0xBB04.  
This load instruction loads register r3 with 0x0000_FF02 in big-endian mode and with  
0x0000_02FF in little-endian mode.  
Memory  
Byte  
Halfword Boundary  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
r29  
Halfword Boundary  
Halfword Boundary  
Memory  
+4  
The offset, 2, is  
11111111  
0x404  
0x405  
shifted left by 1 bit.  
00000010  
Halfword  
r3  
r3  
0x0000_FF02  
Big-Endian  
Load (Zero-Extended)  
Ø
CPU  
Register  
Zero-Extended  
0x0000_02FF  
Little-Endian  
B-98  
Appendix B 16-Bit ISA Details  
LI rx, immediate  
Load Immediate  
Operation  
rx ⇐ 016|| (immediate15..0  
)
Instruction Encoding  
15  
11 10  
11 10  
8 7  
0
LI  
rx  
3
immediate  
8
01101  
5
31  
27 26  
21 20  
16 15  
8
7
5
4
0
EXTEND  
11110  
LI  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
rx  
3
000  
3
imm[4:0]  
5
01101  
5
5
5
Description  
The 8-bit immediate is zero-extended and loaded into general-purpose register rx.  
With the 8-bit immediate field, the immediate range is 0 to 255. If the immediate is outside this  
range, the instruction is EXTENDed to provide a 16-bit unsigned immediate in the range of 0 to  
65535.  
Exceptions  
None  
Example  
The instruction:  
LI r3,0x12  
loads register r3 with 0x0000_0012.  
B-99  
Appendix B 16-Bit ISA Details  
LUI ry, immediate  
Load Upper Immediate  
Operation  
ry ⇐ immediate || 0x0000  
Instruction Encoding  
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
LUI  
111  
Imm[10:5]  
6
Imm[15:11]  
01001  
5
ry  
3
Imm[4:0]  
5
EXTENDED  
5
5
3
Description  
The 16-bit immediate is shifted left by 16 bits and concatenated to 16 bits of zeros. The result is  
placed into general-purpose register ry.  
Exceptions  
None  
Example  
The instruction:  
LUI r4,0x1234  
loads register r4 with 0x1234_0000.  
B-100  
Appendix B 16-Bit ISA Details  
LW rx, offset (pc)  
Load Word  
Operation  
rx ⇐ {zero-extend (offset || 00) + (Masked Base PC)}  
rx ⇐ {sign-extend (offset) + (Masked Base PC)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8 7  
0
LWPC  
10110  
rx  
3
offset  
8
5
31  
27 26  
21 20  
16 15  
8
7
5
4
0
EXTEND  
11110  
LWPC  
10110  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
rx  
3
000  
3
offset[4:0]  
5
5
5
5
Description  
The 8-bit immediate offset is shifted left by two bits, zero-extended and added to the contents of the  
program counter (PC) with the lower two bits cleared to form an effective address (EA). A 32-bit  
constant in memory addressed by the EA is then loaded into general-purpose register rx.  
By virtue of this instruction, 32-bit constants can be embedded in the code segment. The LW  
instructions within the nearby routines can reference this data with a single instruction.  
Since the 8-bit offset is shifted left by two bits, the offset range is 0 to 1020, in increments of four. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate  
in the range of -32768 to +32767. Given the PC-relative addressing mode, there is also an  
instruction (ADDIUPC) to calculate a PC-relative address and place it in a general-purpose register.  
Because the PC value is used as the base value, it is commonly referred to as the base PC value. The  
base PC value with the lower two bits cleared is referred to as the masked base PC value. The base  
PC value varies, depending on whether the instruction is in a delay slot and whether it is to be  
EXTENDed.  
LWPC  
Base PC Value  
Delay slot of the JR or JALR instruction  
Delay slot of the JAL or JALX instruction  
EXTENDed  
Address of the JR or JALR instruction  
Address of the upper halfword of the JAL or JALX instruction  
Address of the EXTEND code  
Not EXTENDed (nor in a delay slot)  
Address of the LWPC instruction  
B-101  
Appendix B 16-Bit ISA Details  
Exceptions  
Address error exception  
Example  
Assume that the masked base PC points at address 0x0123_4568 and that addresses 0x1234_5678  
to 0x0123_457B contain 0x01, 0x23, 0x45 and 0x67 respectively. Given the instruction:  
LW r3,16(pc)  
the assembler turns the specified offset value (16 or binary 0001_0000) into a code of 4 (binary  
0000_ 0100) since it is to be shifted left by two bits by the processor hardware. Thus the instruction  
code for the above load instruction becomes 0xB304. Executing the above instruction loads register  
r3 with 0x0123_4567 in big-endian mode and with 0x6745_2301 in little-endian mode.  
Memory  
Word  
0x0123_4568  
+16  
0x123_4568  
0x123_456C  
0x123_4570  
0x123_4574  
0x123_4578  
0x123_457C  
LW r3 16 (pc)  
Masked Base PC  
The offset, 4, is  
shifted left by two  
bits.  
0x01  
0x23  
0x45  
0x67  
0x0123_4567  
Big-Endian  
r3  
r3  
Load  
0x6745_2301  
Little-Endian  
B-102  
Appendix B 16-Bit ISA Details  
LW rx, offset (sp)  
Load Word  
Operation  
rx ⇐ {zero-extend (offset || 00) + (sp)}  
rx ⇐ {sign-extend (offset) + (sp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
8 7  
0
LWSP  
10010  
rx  
3
offset  
8
5
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
LWSP  
10010  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
rx  
3
000  
3
offset[4:0]  
5
5
5
5
Description  
The 8-bit immediate offset is shifted left by two bits, zero-extended and added to the contents of  
stack pointer register sp (r29) to form an effective address (EA). The word in memory addressed by  
the EA is loaded into general-purpose register rx.  
Since the 8-bit offset is shifted left by two bits, the offset range is 0 to 1020, in increments of four. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate  
in the range of -32768 to +32767.  
Exceptions  
Address Error exception  
B-103  
Appendix B 16-Bit ISA Details  
Example  
Assume that stack pointer register sp points at address 0x0000_0400 and that addresses 0x404 to  
0x407 contain 0x01, 0x23, 0x45 and 0x67 respectively. Given the instruction:  
LW r3,4(sp)  
the assembler/linker turns the specified offset value (4 or binary 0100) into a code of 1 (binary  
0001) since it is to be shifted left by two bits by the processor hardware. Thus the instruction code  
for the above load instruction becomes 0x9301. Executing the above instruction loads register r3  
with 0x0123_4567 in big-endian mode and with 0x6745_2301 in little-endian mode.  
Memory  
Byte  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
sp  
+4  
The offset, 1, is shifted  
left by two bits.  
0x01  
0x23  
0x45  
0x67  
r3  
r3  
0x0123_4567  
Big-Endian  
Load  
0x6745_2301  
Little-Endian  
B-104  
Appendix B 16-Bit ISA Details  
LW ry, offset (base)  
Load Word  
Operation  
ry ⇐ {zero-extend (offset || 00) + (base)}  
ry ⇐ {sign-extend (offset) + (base)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
base  
8 7  
5 4  
0
LW  
ry  
3
offset  
5
10011  
5
3
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
LW  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
base  
3
ry  
3
offset[4:0]  
5
10011  
5
5
5
Description  
The 5-bit immediate offset is shifted left by two bits, zero-extended and added to the contents of  
general-purpose register base to form an effective address (EA). The word in memory addressed by  
the EA is loaded into general-purpose register ry.  
Since the 5-bit offset is shifted left by two bits, the offset range is 0 to 124, in increments of four. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate  
in the range of -32768 to +32767. When EXTENDed, the offset operand is not shifted at all.  
Exceptions  
Address Error exception  
B-105  
Appendix B 16-Bit ISA Details  
Example  
LW r3,4(r2)  
Assume that register r2 contains 0x0000_0400 and that the memory locations at addresses 0x404 to  
0x407 contain 0x01, 0x23, 0x45 and 0x67 respectively. Since the offset value is shifted left by two  
bits by the processor hardware, the assembler/linker turns the specified offset (4 or binary 0100) into  
a code of 1 (binary 0001). Thus the instruction code for this load instruction becomes 0x9A61.  
This load instruction loads register r3 with 0x0123_4567 in big-endian mode and with  
0x6745_2301 in little-endian mode.  
Memory  
Byte  
Word Boundary  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
r2  
+4  
The offset, 1, is shifted  
left by two bits.  
Word Boundary  
0x01  
0x23  
0x45  
0x67  
r3  
r3  
0x0123_4567  
Big-Endian  
Load  
0x6745_2301  
Little-Endian  
B-106  
Appendix B 16-Bit ISA Details  
LW ry, offset (fp)  
Load Word  
Operation  
ry ⇐ {zero-extend (offset || 00) + (fp)}  
ry ⇐ {sign-extend (offset) + (fp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8
8
7
7
5
5
4
4
0
0
LWFP  
11111  
110  
3
ry  
3
offset[4:0]  
5
5
31  
27 26  
21 20  
16 15  
EXTEND  
11110  
offset[10:5]  
6
offset[15:11]  
11111  
5
110  
3
ry  
3
offset[4:0]  
5
EXTENDED  
5
5
Description  
The 5-bit immediate offset is shifted left by two bits, zero-extended and added to the contents of the  
fp register (r30) to form an effective address (EA). The word in memory addressed by the EA is  
loaded into general-purpose register ry.  
Since the 5-bit offset is shifted left by two bits, the offset range is 0 to 124, in increments of four. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate  
in the range of -32768 to +32767.  
Exceptions  
Address Error exception  
B-107  
Appendix B 16-Bit ISA Details  
Example  
Assume that the fp register (r30) points at address 0x0000_0400 and that addresses 0x404 to 0x407  
contain 0x01, 0x23, 0x45 and 0x67 respectively. Given the instruction:  
LW r3,4(fp)  
the assembler/linker turns the specified offset value (4 or binary 0100) into a code of 1 (binary  
0001) since it is to be shifted left by two bits by the processor hardware. Thus the instruction code  
for the above load instruction becomes 0xFE61.  
Executing the above instruction loads register r3 with 0x0123_4567 in big-endian mode and with  
0x6745_2301 in little-endian mode.  
Memory  
Byte  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
fp  
+4  
The offset, 1, is shifted  
left by 2 bits.  
0x01  
0x23  
0x45  
0x67  
r3  
r3  
0x0123_4567  
Big-Endian  
Load  
0x6745_2301  
Little-Endian  
B-108  
Appendix B 16-Bit ISA Details  
MADD rx, ry  
Multiply and Add  
Operation  
HI ⇐ high-order word of (HI || LO) + (rx × ry)  
LO ⇐ low-order word of (HI || LO) + (rx × ry) の下位ワード  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
MADD  
10110  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register rx is multiplied by the contents of general-purpose register  
ry, and then the product is added to the 64-bit, doubleword contents of the HI and LO registers.  
Both rx and ry are treated as signed integers. The high-order word of the result is placed into the HI  
register, and the low-order word of the result is placed into the LO register.  
No Integer Overflow exception occurs under any circumstances.  
Exceptions  
None  
Example  
Assume that the HI and LO registers contain 0x0000_0000 and 0xFFFF_FFFF respectively and that  
general-purpose registers r3 and r4 contain 0x0123_4567 and 0x89AB_CDEF respectively. Then,  
the instruction:  
MADD r3,r4  
evaluates:  
0x0000_0000_FFFF_FFFF + (0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0x0000_0000_FFFF_FFFF + 0xFF79_5E36_C94E_4629  
= 0xFF79_5E37_C94E_4628  
Hence, the high-order word of the result, 0xFF79_5E37, is placed into the HI register, and the  
low-order word of the result, 0xC94E_4628, is placed into the LO register.  
B-109  
Appendix B 16-Bit ISA Details  
MADDU rx, ry  
Multiply and Add Unsigned  
Operation  
HI ⇐ high-order word of (HI || LO) + (rx × ry)  
LO ⇐ low-order word of (HI || LO) + (rx × ry)  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
MADDU  
10111  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register rx is multiplied by the contents of general-purpose register  
ry, and then the product is added to the 64-bit, doubleword contents of the HI and LO registers.  
Both rx and ry are treated as unsigned integers. The high-order word of the result is placed into the  
HI register, and the low-order word of the result is placed into the LO register.  
No Integer Overflow exception occurs under any circumstances.  
Exceptions  
None  
Example  
Assume that the HI and LO registers contain 0x0000_0000 and 0xFFFF_FFFF respectively and that  
general-purpose registers r3 and r4 contain 0x0123_4567 and 0x89AB_CDEF respectively. Then,  
the instruction:  
MADDU r3,r4  
evaluates:  
0x0000_0000_FFFF_FFFF + (0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0x0000_0000_FFFF_FFFF + 0x009C_A39D_C94E_4629  
= 0x009C_A39E_C94E_4628  
Hence, the high-order word of the result, 0x009C_A39E, is placed into the HI register, and the  
low-order word of the result, 0xC94E_4628, is placed into the LO register.  
B-110  
Appendix B 16-Bit ISA Details  
MAX rz, rx, ry  
Maximum Signed  
Operation  
if rx ＞ry then rz ⇐ rx ;  
else rz ⇐ ry ;  
Instruction Encoding  
31  
27 26  
19 18  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
EXTENDED  
00000000  
8
ry  
3
11101  
5
rz  
3
rx  
3
00101  
5
5
Description  
The contents of general-purpose register rx is compared to the contents of general-purpose register  
ry as signed values. If rx is greater than ry, the value of rx is written to general-purpose register rz.  
Otherwise, the value of ry is written to rz.  
Exceptions  
None  
B-111  
Appendix B 16-Bit ISA Details  
MFC0 ry, cp0rs32  
Move from Coprocessor 0  
Operation  
ry ⇐ CP0 register cp0rs32  
Instruction Encoding  
15  
11 10  
8
7
3
2
0
SHIFT  
00110  
ry  
3
cp0rs32  
5
001  
3
5
Description  
The contents of CP0 register cp0rs32 is loaded into general-purpose register ry.  
In 16-bit ISA mode, this instruction can not access the Config1, Config2, Config3 and IER  
registers.  
Exceptions  
Coprocessor Unusable exception  
B-112  
Appendix B 16-Bit ISA Details  
MFHI rx  
Move From HI  
Operation  
rx ⇐ HI  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
0
MFHI  
rx  
3
11101  
000  
10000  
5
3
5
Description  
The contents of the HI register is loaded into general-purpose register rx.  
Exceptions  
None  
B-113  
Appendix B 16-Bit ISA Details  
MFLO rx  
Move From LO  
Operation  
rx ⇐ LO  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
0
MFLO  
10010  
rx  
3
11101  
000  
5
3
5
Description  
The contents of the LO register is loaded into general-purpose register rx.  
Exceptions  
None  
B-114  
Appendix B 16-Bit ISA Details  
MIN rz, rx, ry  
Minimum Signed  
Operation  
if rx ＜ry then rz ⇐ rx ;  
else rz ⇐ ry ;  
Instruction Encoding  
31  
27 26  
19 18  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
EXTENDED  
10000000  
8
ry  
3
11101  
5
rz  
3
rx  
3
00101  
5
5
Description  
The contents of general-purpose register rx is compared to the contents of general-purpose register  
ry as signed values. If rx is less than ry, the value of rx is written to general-purpose register rz.  
Otherwise, the value of ry is written to rz.  
Exceptions  
None  
B-115  
Appendix B 16-Bit ISA Details  
MOVE fp, r32  
Move  
Operation  
fp ⇐ r32  
Instruction Encoding  
15  
11 10 9  
5
4
0
RR  
1
r32  
01000  
5
11101  
5
3
3
Description  
The contents of general-purpose register r32 is copied into the fp register (r30), where r32 is any of  
the 32 registers (r0 to r31).  
The encoding of the r32 field in the 16-bit instruction code is as follows.  
Code  
00000  
00001  
Register  
Code  
10000  
10001  
Register  
r16  
r0  
r1  
r17  
00010  
00011  
00100  
00101  
00110  
00111  
01000  
01001  
01010  
01011  
01100  
01101  
01110  
01111  
r2  
r3  
r4  
r5  
r6  
r7  
r8  
r9  
r10  
r11  
r12  
r13  
r14  
r15  
10010  
10011  
10100  
10101  
10110  
10111  
11000  
11001  
11010  
11011  
11100  
11101  
11110  
11111  
r18  
r19  
r20  
r21  
r22  
r23  
r24  
r25  
r26  
r27  
r28  
r29  
r30  
r31  
Exceptions  
None  
B-116  
Appendix B 16-Bit ISA Details  
MOVE ry, r32  
Move  
Operation  
ry ⇐ r32  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
I8  
movr32  
ry  
3
r32  
5
01100  
111  
3
5
Description  
The contents of general-purpose register r32 is copied to general-purpose register ry, where r32 is  
any of the 32 registers (r0 to r31) and ry is one of the eight registers visible to the 16-bit ISA.  
To the 16-bit instructions, only eight of the 32 general-purpose registers are normally visible, r2 to  
r7, r16 and r17. Since the processor includes the full 32 registers of the 32-bit ISA mode, the 16-bit  
ISA includes the MOVE instructions to copy values between the eight 16-bit ISA registers and the  
remaining 24 registers of the full processor architecture. By virtue of the MOVE instructions, 16-bit  
routines can utilize all of the 32 general-purpose registers.  
The encoding of the r32 field in the 16-bit instruction code is as follows.  
Code  
00000  
00001  
Register  
Code  
10000  
10001  
Register  
r16  
r0  
r1  
r17  
00010  
00011  
00100  
00101  
00110  
00111  
01000  
01001  
01010  
01011  
01100  
01101  
01110  
01111  
r2  
r3  
r4  
r5  
r6  
r7  
r8  
r9  
r10  
r11  
r12  
r13  
r14  
r15  
10010  
10011  
10100  
10101  
10110  
10111  
11000  
11001  
11010  
11011  
11100  
11101  
11110  
11111  
r18  
r19  
r20  
r21  
r22  
r23  
r24  
r25  
r26  
r27  
r28  
r29  
r30  
r31  
Exceptions  
None  
B-117  
Appendix B 16-Bit ISA Details  
MOVE r32, rz  
Move  
Operation  
r32 ⇐ rz  
Instruction Encoding  
15  
11 10  
8 7  
3
2
0
I8  
mov32r  
r32  
5
rz  
3
01100  
101  
3
5
Description  
The contents of general-purpose register rz is copied to general-purpose register r32, where rz is one  
of the eight registers visible to the 16-bit ISA and r32 is any of the 32 registers (r0 to r31).  
To the 16-bit instructions, only eight of the 32 general-purpose registers are normally visible, r2 to  
r7, r16 and r17. Since the processor includes the full 32 registers of the 32-bit ISA mode, the 16-bit  
ISA includes the MOVE instructions to copy values between the eight 16-bit ISA registers and the  
remaining 24 registers of the full processor architecture. By virtue of the MOVE instructions, 16-bit  
routines can utilize all of the 32 general-purpose registers.  
The encoding of the r32 field in this 16-bit instruction code differs from that of the 32-bit ISA. The  
r32 field, encoded as [2:0][4:3], denotes a general-purpose register as shown below.  
Code  
Register  
Code  
Register  
00000  
00001  
00010  
00011  
00100  
00101  
00110  
00111  
01000  
01001  
01010  
01011  
01100  
01101  
01110  
01111  
r0  
r8  
10000  
10001  
10010  
10011  
10100  
10101  
10110  
10111  
11000  
11001  
11010  
11011  
11100  
11101  
11110  
11111  
r4  
r12  
r20  
r28  
r5  
r16  
r24  
r1  
r9  
r13  
r21  
r29  
r6  
r17  
r25  
r2  
r10  
r18  
r26  
r3  
r14  
r22  
r30  
r7  
r11  
r19  
r27  
r15  
r23  
r31  
Exceptions  
None  
B-118  
Appendix B 16-Bit ISA Details  
MTC0 rx, cp0rd32  
Move to System Coprocessor 0 (CP0)  
Operation  
CP0 レジスタのcp0rd32 ⇐ rx  
Instruction Encoding  
15  
11 10  
8
7
3
2
0
SHIFT  
00110  
rx  
3
cp0rd32  
5
101  
5
5
Description  
The contents of general-purpose register rx is loaded into CP0 register cp0rd32.  
In 16-bit ISA mode, this instruction can not access the Config1, Config2, Config3, IER and SSCR  
registers.  
Once the MTC0 instruction writes to the Status, EPC or ErrorEPC register, at least two instructions  
must be executed before the ERET instruction. Otherwise, the operation is undefined.  
Likewise, once the MTC0 instruction writes to the DEPC register, at least two instructions must be  
executed before the ERET instruction. Otherwise, the operation is undefined.  
Because this instruction may alter the state of the virtual address translation system, the operation of  
load and store instructions immediately before and after this instruction is undefined.  
Exceptions  
Coprocessor Unusable exception  
B-119  
Appendix B 16-Bit ISA Details  
MTHI rx  
Move To HI  
Operation  
HI ⇐ rx  
Instruction Encoding  
15  
11 10  
8
7
0
1
6
0
RRR  
rx  
3
0000010  
7
11100  
5
Description  
The contents of general-purpose register rx is loaded into the HI register.  
Exceptions  
None  
B-120  
Appendix B 16-Bit ISA Details  
MTLO rx  
Move To LO  
Operation  
LO ⇐ rx  
Instruction Encoding  
15  
11 10  
8
7
1
6
0
RRR  
rx  
3
0000010  
7
11100  
5
1
Description  
The contents of general-purpose register rx is loaded into the LO register.  
Exceptions  
None  
B-121  
Appendix B 16-Bit ISA Details  
MULT ry, rx, ry  
Multiply  
Operation  
HI ⇐ high-order word of (rx × ry);  
LO ⇐ low-order word of (rx × ry);  
ry ⇐ low-order word of (rx × ry);  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
MULT  
11100  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register rx is multiplied by the contents of general-purpose register  
ry. Both rx and ry are treated as signed integers. The high-order word of the result is placed into the  
HI register, and the low-order word of the result is placed into the LO register and ry.  
No Integer Overflow exception occurs under any circumstances.  
Exceptions  
None  
Example  
Assume that general-purpose registers r3 and r4 contain 0x0123_4567 and 0x89AB_CDEF  
respectively. Then, the instruction:  
MULT r4,r3,r4  
evaluates:  
(0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0xFF79_5E36_C94E_4629  
Hence, the high-order word of the result, 0xFF79_5E36, is placed into the HI register, and the  
low-order word of the result, 0xC94E_4629, is placed into the LO and r4 registers.  
B-122  
Appendix B 16-Bit ISA Details  
MULT rx, ry  
Multiply  
Operation  
HI ⇐ high-order word of (rx × ry);  
LO ⇐ high-order word of (rx × ry);  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
MULT  
11000  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register rx is multiplied by the contents of general-purpose register  
ry. Both rx and ry are treated as signed integers. The high-order word of the result is placed into the  
HI register, and the low-order word of the result is placed into the LO register.  
No Integer Overflow exception occurs under any circumstances.  
Exceptions  
None  
Example  
Assume that general-purpose registers r3 and r4 contain 0x0123_4567 and 0x89AB_CDEF  
respectively. Then, the instruction:  
MULT r3,r4  
evaluates:  
(0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0xFF79_5E36_C94E_4629  
Hence, the high-order word of the result, 0xFF79_5E36, is placed into the HI register, and the  
low-order word of the result, 0xC94E_4629, is placed into the LO register.  
B-123  
Appendix B 16-Bit ISA Details  
MULTU rx, ry  
Multiply Unsigned  
Operation  
HI ⇐ high-order word of (rx × ry);  
LO ⇐ low-order word of (rx × ry);  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
MULTU  
11001  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register rx is multiplied by the contents of general-purpose register  
ry. Both rx and ry are treated as unsigned integers. The high-order word of the result is placed into  
the HI register, and the low-order word of the result is placed into the LO register.  
No Integer Overflow exception occurs under any circumstances.  
Exceptions  
None  
Example  
Assume that general-purpose registers r3 and r4 contain 0x0123_4567 and 0x89AB_CDEF  
respectively. Then, the instruction:  
MULTU r3,r4  
evaluates:  
(0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0x009C_A39D_C94E_4629  
Hence, the high-order word of the result, 0x009C_A39D, is placed into the HI register, and the  
low-order word of the result, 0xC94E_4629, is placed into the LO register.  
B-124  
Appendix B 16-Bit ISA Details  
MULTU ry, rx, ry  
Multiply  
Operation  
HI ⇐ high-order word of (rx × ry);  
LO ⇐ low-order word of (rx × ry);  
ry ⇐ low-order word of (rx × ry);  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
MULTU  
11101  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register rx is multiplied by the contents of general-purpose register  
ry. Both rx and ry are treated as unsigned integers. The high-order word of the result is placed into  
the HI register, and the low-order word of the result is placed into the LO register and ry.  
No Integer Overflow exception occurs under any circumstances.  
Exceptions  
None  
Example  
Assume that general-purpose registers r3 and r4 contain 0x0123_4567 and 0x89AB_CDEF  
respectively. Then, the instruction:  
MULTU r4,r3,r4  
evaluates:  
(0x0123_4567 ⋅ 0x89AB_CDEF)  
= 0x009C_A39D_C94E_4629  
Hence, the high-order word of the result, 0x009C_A39D, is placed into the HI register, and the  
low-order word of the result, 0xC94E_4629, is placed into the LO and r4 registers.  
B-125  
Appendix B 16-Bit ISA Details  
NEG rx, ry  
Negate  
Operation  
rx = 0 – ry  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
NEG  
rx  
3
ry  
3
11101  
01011  
5
5
Description  
This instruction performs 2’s complement of the contents of general-purpose register ry and places  
the result into general-purpose register rx. It is implemented as the subtraction of ry from a value of  
zero.  
Exceptions  
None  
B-126  
Appendix B 16-Bit ISA Details  
NOT rx, ry  
NOT  
Operation  
rx ⇐ ry NOR 0x0000_0000  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
NOT  
rx  
3
ry  
3
11101  
01111  
5
5
Description  
This instruction performs 1’s complement of the contents of general-purpose register ry and places  
the result into general-purpose register rx. Each bit in ry is inverted. It is implemented as the logical  
NOR of ry and a value of zero.  
Exceptions  
None  
B-127  
Appendix B 16-Bit ISA Details  
OR rx, ry  
OR  
Operation  
rx ⇐ rx OR ry  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
OR  
rx  
3
ry  
3
11101  
01101  
5
5
Description  
The contents of general-purpose register rx is ORed with the contents of general-purpose register ry,  
and the result is placed back into general-purpose register rx.  
Exceptions  
None  
B-128  
Appendix B 16-Bit ISA Details  
ORI ry, immediate  
Logical OR Immediate  
Operation  
ry ⇐ ry OR (016|| immediate15..0  
)
Instruction Encoding  
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
ORI  
101  
Imm[10:5]  
6
Imm[15:11]  
01001  
5
ry  
3
Imm[4:0]  
5
EXTENDED  
5
5
3
Description  
The 16-bit immediate is zero-extended and ORed with the contents of general-purpose register ry.  
The result is placed back into ry.  
The immediate field is 16 bits in length. If the immediate size is larger than that, you need to put it  
in a general-purpose register and use the OR instruction (see 3.3.2, 32-Bit Constants).  
Exceptions  
None  
Example  
Assume that register r4 contains 0x0000_7350. Then, the instruction:  
ORI r4,0x1234  
performs the logical OR between 0x0000_7350 and 0x0000_1234 and puts the result  
(0x0000_7374) back in r4, as shown below.  
r4 0000 0000 0000 0000 0111 0011 0101 0000  
OR  
0000 0000 0000 0000 0001 0010 0011 0100  
Zero-Extended  
r4 0000 0000 0000 0000 0111 0011 0111 0100  
B-129  
Appendix B 16-Bit ISA Details  
RESTORE reg_list3, framesize4  
Restore Registers and Deallocate Stack Frame  
Operation  
ra(r31) ⇐ Stack and/or s1(r17) ⇐ Stack and/or s0(r16) ⇐ Stack ;  
if framesize4 == 0 then sp(r29) ⇐ sp + 128 ;  
else sp(r29) ⇐ sp + (0 || framesize4 << 3) ;  
Instruction Encoding  
15  
11 10  
8
7
6
5
4
3
0
I8  
SVRS  
s
framesize  
ra s0 s1  
01100  
100  
3
0
[3:0]  
4
5
1
1 1 1  
Description  
The r31 (ra), r16 (s0) and/or r17 (s1) registers are restored from the memory stack if the  
corresponding ra, s0 and s1 bits of the instruction are set, and the stack pointer register (sp) is  
adjusted by the framesize4 value. Higher numbered registers are loaded from higher stack addresses.  
The encoding used for the reg_list3 field is as follows:  
reg_list3  
0x1  
ra s0 s1  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
0x2  
0x3  
0x4  
0x5  
0x6  
0x7  
The reg_list3 field must be non-zero; otherwise, the operation is unpredictable.  
The 4-bit framesize4 value is shifted left by three bits and zero-extended. A framesize4 value of 0 is  
interpreted as a stack pointer adjustment of 128. Thus framesize4 can be between +8 and +128 in  
increments of eight. If framesize4 is outside this range, the instruction is EXTENDed, providing an  
8-bit framesize field for stack pointer adjustment between 0 and +2040. The framesize field in the  
EXTENDed instruction is also shifted left by three bits.  
If either of the two least-significant bits of the stack pointer is not zero, an Address Error exception  
occurs.  
B-130  
Appendix B 16-Bit ISA Details  
Operation Details  
if framesize[3:0] = 0 then  
temp ⇐ sp (r29) + 128  
else  
temp ⇐ sp (r29) + (0 || (framesize[3:0] << 3))  
endif  
temp2 ⇐ temp  
if ra = 1 then  
temp ⇐ temp - 4  
r31 ⇐ Memory [temp]  
endif  
if s1 = 1 then  
temp ⇐ temp - 4  
r17 ⇐ Memory [temp]  
endif  
if s0 = 1 then  
temp ⇐ temp - 4  
r16 ⇐ Memory [temp]  
endif  
sp (r29) ⇐ temp2  
Exceptions  
Address Error exception  
Programming Notes  
The time required to execute this instruction varies, depending on the number of memory loads and  
the memory access time. In case of any interrupt during execution, the full sequence of operations  
will be restarted upon return from the interrupt.  
B-131  
Appendix B 16-Bit ISA Details  
RESTORE reg_list3, xsregs, aregs, framesize8  
Restore Registers and Deallocate Stack Frame  
Operation  
ra(r31) ⇐ Stack and/or [r18-r23, r30] ⇐ Stack and/or  
s1(r17) ⇐ Stack and/or s0(r16) ⇐ Stack and/or [r4-r7] ⇐ Stack ;  
sp(r29) ⇐ sp + (0 || framesize8 << 3) ;  
Instruction Encoding  
31  
27 26  
24 23  
20 19  
16 15  
11 10  
8
7
6
5
4
3
0
EXTEND  
11110  
framesize  
I8  
SVRS  
s
framesize  
xsregs  
aregs  
4
ra s0 s1  
EXTENDED  
[7:4]  
4
01100  
100  
3
0
[3:0]  
4
5
3
5
1
1 1 1  
Description  
The r31 (ra) register is restored from the memory stack if the ra bit in the instruction is set. The r30  
and r23-r18 registers are restored from the memory stack, as indicated by the value of the xsregs  
field. The r17 and/or r16 registers are restored from the memory stack if the corresponding s1 and s0  
bits in the instruction are set. The r7 to r4 registers are restored from the memory stack, as indicated  
by the aregs field. The stack pointer register (sp) is adjusted by the framesize8 value. Higher  
numbered registers are loaded from higher stack addresses.  
For the interpretation of the xsregs field, see the Operation Details section. For the interpretation of  
the aregs field, see the Interpretation of the aregs Field section.  
The encoding used for the reg_list3 field is as follows:  
reg_list3  
0x0  
ra s0 s1  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
0x1  
0x2  
0x3  
0x4  
0x5  
0x6  
0x7  
At least one register must be specified in any of the reg_list3, xsregs and aregs fields to be restored.  
If no register is specified, the behavior of the processor is unpredictable.  
The 8-bit framesize8 value is shifted left by three bits and zero-extended. Thus framesize8 can be  
between 0 and +2040, in increments of eight.  
B-132  
Appendix B 16-Bit ISA Details  
If either of the two least-significant bits of the stack pointer is not zero, an Address Error exception  
occurs.  
Interpretation of the aregs Field  
In the standard MIPS ABIs (Application Binary Interfaces), registers r4-r7 are designated as a0-a3  
for passing arguments to functions. When they are so used, they are saved on the stacks allocated  
not only by the caller of the routine being entered but also by its callee. In the standard MIPS ABIs,  
however, registers r4-r7 need not be restored on subroutine exit.  
In other MIPS16e calling sequences, registers r4-r7 may be saved as static registers (i.e., registers  
preserved throughout the function) on the callee stack instead of the caller stack, and restored before  
return from the function.  
The encoding used for the aregs field of the extended RESTORE instruction is the same as that  
used for the extended SAVE instruction, except that the RESTORE instruction ignores argument  
registers and handles only the registers treated as static.  
The following table shows the encoding of the aregs field of the RESTORE instruction.  
aregs  
Registers Restored as Static  
Encoding  
Registers  
(binary)  
0000  
0001  
0010  
0011  
1011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1100  
1101  
1110  
1111  
–
r7  
r6, r7  
r5, r6, r7  
r4, r5, r6, r7  
–
r7  
r6, r7  
r5, r6, r7  
–
r7  
r6, r7  
–
r7  
–
Reserved  
B-133  
Appendix B 16-Bit ISA Details  
Operation Details  
temp ⇐ sp (r29) + (0 || (framesize[7:0] << 3))  
temp2 ⇐ temp  
if ra = 1 then  
temp ⇐ temp - 4  
r31 ⇐ Memory [temp]  
endif  
if xsregs > 0 then  
if xsregs > 1 then  
if xsregs > 2 then  
if xsregs > 3 then  
if xsregs > 4 then  
if xsregs > 5 then  
if xsregs > 6 then  
temp ⇐ temp - 4  
r30 ⇐ Memory [temp]  
endif  
temp⇐ temp - 4  
r23 ⇐ Memory [temp]  
endif  
temp⇐ temp - 4  
r22 ⇐ Memory [temp]  
endif  
temp ⇐ temp - 4  
r21 ⇐ Memory [temp]  
endif  
temp ⇐ temp - 4  
r20 ⇐ Memory [temp]  
endif  
temp ⇐ temp - 4  
r19 ⇐ Memory [temp]  
endif  
temp ⇐ temp - 4  
r18 ⇐ Memory [temp]  
endif  
if s1 = 1 then  
temp ⇐ temp - 4  
r17 ⇐ Memory [temp]  
endif  
if s0 = 1 then  
temp ⇐ temp - 4  
r16 ⇐ Memory [temp]  
endif  
case aregs of (in binary)  
0000, 0100, 1000, 1100, 1110 : astatic ⇐ 0  
0001, 0101, 1001, 1101 : astatic ⇐ 1  
0010, 0110, 1010 : astatic ⇐ 2  
0011, 0111 : astatic ⇐ 3  
B-134  
Appendix B 16-Bit ISA Details  
1011 : astatic ⇐ 4  
otherwise : UNPREDICTABLE  
endcase  
if astatic > 0 then  
temp ⇐ temp - 4  
r7  
⇐ Memory [temp]  
if astatic > 1 then  
temp ⇐ temp - 4  
r6  
⇐ Memory [temp]  
if astatic > 2 then  
temp ⇐ temp - 4  
r5  
⇐ Memory [temp]  
if astatic > 3 then  
temp ⇐ temp - 4  
r4  
endif  
endif  
endif  
endif  
sp (r29) ⇐ temp2  
⇐ Memory [temp]  
Exceptions  
Address Error exception  
Programming Notes  
The time required to execute this instruction varies, depending on the number of memory loads and  
the memory access time. In case of any interrupt during execution, the full sequence of operations  
will be restarted upon return from the interrupt.  
The behavior of the processor is unpredictable if a reserved value of 1111 is given in the aregs field.  
B-135  
Appendix B 16-Bit ISA Details  
SADD ry, rx, ry  
Saturated Add  
Operation  
if overflow on rx + ry then ry ⇐ 0x7FFF_FFFF ( rx ≧0) or 0x8000_0000 ( rx < 0 )  
else ry ⇐ rx + ry  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
SADD  
10100  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register rx is added to the contents of general-purpose register ry.  
The sum saturates to the largest representable positive number (0x7FFF_FFFF) on overflow and to  
the smallest representable negative number (0x8000_0000) on underflow. The result is placed into  
ry. If neither overflow nor underflow occurs, the sum of rx and ry is placed into ry. Both rx and ry  
are treated as signed integers.  
An Integer Overflow exception never occurs on overflow.  
Exceptions  
None  
B-136  
Appendix B 16-Bit ISA Details  
SAVE reg_list3, framesize4  
Save Registers and Set up Stack Frame  
Operation  
Stack ⇐ ra(r31)  
and/or Stack ⇐ s1(r17) and/or Stack ⇐ s0(r16) ;  
if framesize4 == 0 then sp(r29) ⇐ sp - 128 ;  
else sp(r29) ⇐ sp - (0 || framesize4 << 3) ;  
Instruction Encoding  
15  
11 10  
8
7
6
5
4
3
0
I8  
SVRS  
s
framesize  
ra s0 s1  
01100  
100  
3
1
[3:0]  
4
5
1
1 1 1  
Description  
The r31 (ra), r16 (s0) and/or r17 (s1) registers are saved to the memory stack if the corresponding ra,  
s0 and s1 bits of the instruction are set, and the stack pointer register (sp) is adjusted by the  
framesize4 value. Higher numbered registers are stored to higher stack addresses.  
The encoding used for the reg_list3 field is as follows:  
reg_list3  
0x1  
ra s0 s1  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
0x2  
0x3  
0x4  
0x5  
0x6  
0x7  
The reg_list3 field must be non-zero; otherwise, the operation is unpredictable.  
The 4-bit framesize4 value is shifted left by three bits and zero-extended. A framesize4 value of 0 is  
interpreted as a stack pointer adjustment of 128. Thus framesize4 can be between +8 and +128 in  
increments of eight. If framesize4 is outside this range, the instruction is EXTENDed, providing an  
8-bit framesize field for stack pointer adjustment between 0 and +2040. The framesize field in the  
EXTENDed instruction is also shifted left by three bits.  
If either of the two least-significant bits of the stack pointer is not zero, an Address Error exception  
occurs.  
B-137  
Appendix B 16-Bit ISA Details  
Operation Details  
temp ⇐ sp (r29)  
if ra = 1 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r31  
endif  
if s1 = 1 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r17  
endif  
if s0 = 1 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r16  
endif  
if framesize[3:0] = 0 then  
temp ⇐ sp (r29) - 128  
else  
temp ⇐ sp (r29) - (0 || (framesize[3:0] << 3))  
endif  
sp (r29) ⇐ temp  
Exceptions  
Address Error exception  
Programming Notes  
The time required to execute this instruction varies, depending on the number of memory loads and  
the memory access time. In case of any interrupt during execution, the full sequence of operations  
will be restarted upon return from the interrupt.  
B-138  
Appendix B 16-Bit ISA Details  
SAVE reg_list3, xsregs, aregs, framesize8  
Save Registers and Set up Stack Frame  
Operation  
Stack ⇐ ra(r31) and/or Stack ⇐ [r18-r23, r30] and/or  
Stack ⇐ s1(r17) and/or Stack ⇐ s0(r16) and/or Stack ⇐ [r4-r7] ;  
sp(r29) ⇐ sp - (0 || framesize8 << 3) ;  
Instruction Encoding  
31  
27 26  
24 23  
20 19  
16 15  
11 10  
8
7
6
5
4
3
0
EXTEND  
11110  
framesize  
I8  
SVRS  
s
framesize  
EXTENDED  
xsregs  
aregs  
4
ra s0 s1  
[7:4]  
4
01100  
100  
3
1
[3:0]  
4
5
3
5
1
1 1 1  
Description  
Registers r4-r7 are saved on the memory stack as arguments, as indicated by the value of the aregs  
field. Register r31 (ra) is saved on the memory stack if the corresponding ra bit in the instruction is  
set. Registers r18-r23 and r30 are saved on the memory stack, as indicated by the xsregs field.  
Registers r16 (s0) and/or r17 (s1) are saved on the memory stack if the corresponding s0 and s1 bits  
in the instruction are set. Registers r4-r7 are saved on the stack as static registers as indicated by the  
aregs field. The stack pointer register (sp) is adjusted by the framesize8 value. Higher numbered  
registers are loaded from higher stack addresses.  
For the interpretation of the xsregs field, see the Operation Details section. For the interpretation of  
the aregs field, see the Interpretation of the aregs Field section.  
The encoding used for the reg_list3 field is as follows:  
reg_list3  
0x0  
ra s0 s1  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
0x1  
0x2  
0x3  
0x4  
0x5  
0x6  
0x7  
At least one register must be specified in any of the reg_list3, xsregs and aregs fields to be saved. If  
no register is specified, the behavior of the processor is unpredictable.  
B-139  
Appendix B 16-Bit ISA Details  
The 8-bit framesize8 value is shifted left by three bits and zero-extended. Thus framesize8 can be  
between 0 and +2040, in increments of eight.  
If either of the two least-significant bits of the stack pointer is not zero, an Address Error exception  
occurs.  
Interpretation of the aregs Field  
In the standard MIPS ABIs (Application Binary Interfaces), registers r4-r7 are designated as a0-a3  
for passing arguments to functions. When they are so used, they are saved on the stacks allocated  
not only by the caller of the routine being entered but also by its callee.  
In other MIPS16e calling sequences, registers r4-r7 may be saved as static registers (i.e., registers  
preserved throughout the function) on the callee stack instead of the caller stack.  
The encoding of the aregs field allows for zero to four argument registers, zero to four static  
registers and mixtures of the two. Registers are bound to arguments (a0, a1, a2 and a3) in ascending  
order, and thus assigned to static values (r7, r6, r5 and r4) in the reverse order.  
The following table shows the encoding of the aregs field of the SAVE instruction.  
aregs  
Encoding  
(binary)  
Registers Saved as Argument  
Registers  
Registers Saved as Static  
Registers  
0000  
0001  
0010  
0011  
1011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1100  
1101  
1110  
1111  
–
–
–
r7  
–
r6, r7  
–
–
r5, r6, r7  
r4, r5, r6, r7  
a0(r4)  
–
a0(r4)  
r7  
a0(r4)  
r6, r7  
a0(r4)  
r5, r6, r7  
a0(r4), a1(r5)  
a0(r4), a1(r5)  
a0(r4), a1(r5)  
a0(r4), a1(r5), a2(r6)  
a0(r4), a1(r5), a2(r6)  
a0(r4), a1(r5), a2(r6), a3(r7)  
Reserved  
–
r7  
r6, r7  
–
r7  
–
Reserved  
B-140  
Appendix B 16-Bit ISA Details  
Operation Details  
temp ⇐ sp (r29)  
case aregs of (in binary)  
0000, 0001, 0010, 0011, 1011 : args ⇐ 0  
0100, 0101, 0110, 0111 : args ⇐ 1  
1000, 1001, 1010 : args ⇐ 2  
1100, 1101 : args ⇐ 3  
1110 : args ⇐ 4  
otherwise : UNPREDICTABLE  
endcase  
if args > 0 then  
Memory [temp] ⇐ r4  
if args > 1 then  
Memory [temp + 4] ⇐ r5  
if args > 2 then  
Memory [temp + 8] ⇐ r6  
if args > 3 then  
Memory [temp + 12] ⇐ r7  
endif  
endif  
endif  
endif  
if ra = 1 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r31  
endif  
if xsregs > 0 then  
if xsregs > 1 then  
if xsregs > 2 then  
if xsregs > 3 then  
if xsregs > 4 then  
if xsregs > 5 then  
if xsregs > 6 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r30  
endif  
temp ⇐ temp - 4  
Memory [temp] ⇐ r23  
endif  
temp ⇐ temp - 4  
Memory [temp] ⇐ r22  
endif  
temp ⇐ temp - 4  
Memory [temp] ⇐ r21  
endif  
temp ⇐ temp - 4  
Memory [temp] ⇐ r20  
endif  
temp ⇐ temp - 4  
Memory [temp] ⇐ r19  
B-141  
Appendix B 16-Bit ISA Details  
endif  
temp ⇐ temp - 4  
Memory [temp] ⇐ r18  
endif  
if s1 = 1 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r17  
endif  
if s0 = 1 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r16  
endif  
case aregs of (in binary)  
0000, 0100, 1000, 1100, 1110 : astatic ⇐ 0  
0001, 0101, 1001, 1101 : astatic ⇐ 1  
0010, 0110, 1010 : astatic ⇐ 2  
0011, 0111 : astatic ⇐ 3  
1011 : astatic ⇐ 4  
otherwise : UNPREDICTABLE  
endcase  
if astatic > 0 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r7  
if astatic > 1 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r6  
if astatic > 2 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r5  
if astatic > 3 then  
temp ⇐ temp - 4  
Memory [temp] ⇐ r4  
endif  
endif  
endif  
endif  
temp ⇐ sp (r29) - (0 || (framesize[7:0] << 3))  
sp (r29) ⇐ temp  
Exceptions  
Address Error exception  
Programming Notes  
The time required to execute this instruction varies, depending on the number of memory loads and  
the memory access time. In case of any interrupt during execution, the full sequence of operations  
will be restarted upon return from the interrupt.  
The behavior of the processor is unpredictable if a reserved value of 1111 is given in the aregs field.  
B-142  
Appendix B 16-Bit ISA Details  
SB ry, offset (base)  
Store Byte  
Operation  
ry = {zero-extend (offset) + (base)}  
ry = {sign-extend (offset) + (base)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
base  
8 7  
5 4  
0
SB  
ry  
3
offset  
5
11000  
5
3
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
SB  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
base  
3
ry  
3
offset[4:0]  
5
11000  
5
5
5
Description  
The 5-bit immediate offset is zero-extended and added to the contents of general-purpose register  
base to form an effective address (EA). The least-significant byte in general-purpose register ry is  
stored at the memory location addressed by the EA.  
The three high-order bytes in ry is simply ignored; so there is no distinction between signed and  
unsigned stores.  
With the 5-bit offset field, the offset range is 0 to 31. If the offset is outside this range, the  
instruction is EXTENDed to provide a 16-bit signed immediate in the range of -32768 to +32767.  
Exceptions  
Address Error exception  
B-143  
Appendix B 16-Bit ISA Details  
Example  
Assume that registers r2 and r3 contain 0x0000_0400 and 0x0123_4567 respectively. Then,  
executing the instruction:  
SB r3,4(r2)  
stores 0x67 to the memory location at address 0x404.  
Memory  
Byte  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
r2  
+4  
0x67  
Store  
CPU  
Register  
Ø
Memory  
1 Byte  
r3  
0x0123_4567  
B-144  
Appendix B 16-Bit ISA Details  
SB ry, offset (fp)  
Store Byte  
Operation  
ry = {zero-extend (offset) + (fp)}  
ry = {sign-extend (offset) + (fp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8
8
7
1
1
6
6
0
0
FP-B  
ry  
3
Offset[6:0]  
7
00111  
5
31  
27 26  
21 20  
16 15  
7
1
1
5
4
EXTEND  
11110  
offset[10:5]  
6
offset[15:11]  
00111  
5
ry  
3
00  
offset[4:0]  
EXTENDED  
5
5
2
5
Description  
The 7-bit immediate offset is zero-extended and added to the contents of the fp register (r30) to form  
an effective address (EA). The least-significant byte in general-purpose register ry is stored at the  
memory location addressed by the EA.  
The three high-order bytes in ry are simply ignored; so there is no distinction between signed and  
unsigned stores.  
With the 7-bit offset field, the offset range is 0 to 127. If the offset is outside this range, the  
instruction is EXTENDed to provide a 16-bit signed immediate in the range of -32768 to +32767.  
Exceptions  
Address Error exception  
B-145  
Appendix B 16-Bit ISA Details  
Example  
Assume that the fp (r30) and r3 registers contain 0x0000_0400 and 0x0123_4567 respectively.  
Then, executing the instruction:  
B r3,4(fp)  
stores 0x67 to the memory location at address 0x0404.  
Memory  
Byte  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
r30  
+4  
0x67  
Store  
CPU  
Register  
Ø
Memory  
1 Byte  
r3  
0x0123_4567  
B-146  
Appendix B 16-Bit ISA Details  
SB ry, offset (sp)  
Store Byte  
Operation  
ry = {zero-extend (offset) + (sp)}  
ry = {sign-extend (offset) + (sp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8
8
7
1
1
6
6
0
0
SP-B  
01111  
ry  
3
Offset[6:0]  
7
5
31  
27 26  
21 20  
16 15  
7
1
1
5
4
EXTEND  
11110  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
01111  
5
ry  
3
00  
offset[4:0]  
5
5
2
5
Description  
The 7-bit immediate offset is zero-extended and added to the contents of the sp register (r29) to  
form an effective address (EA). The least-significant byte in general-purpose register ry is stored at  
the memory location addressed by the EA.  
The three high-order bytes in ry are simply ignored; so there is no distinction between signed and  
unsigned stores.  
With the 7-bit offset field, the offset range is 0 to 127. If the offset is outside this range, the  
instruction is EXTENDed to provide a 16-bit signed immediate in the range of -32768 to +32767.  
Exceptions  
Address Error exception  
B-147  
Appendix B 16-Bit ISA Details  
Example  
Assume that the sp (r29) and r3 registers contain 0x0000_0400 and 0x0123_4567 respectively.  
Then, executing the instruction:  
SB r3,4(sp)  
stores 0x67 to the memory location at address 0x404.  
Memory  
Byte  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
r29  
+4  
0x67  
Store  
CPU  
Register  
Ø
Memory  
1 Byte  
r3  
0x0123_4567  
B-148  
Appendix B 16-Bit ISA Details  
SDBBP code  
Software Debug Breakpoint  
Operation  
Software debug breakpoint exception  
Instruction Encoding  
15  
11 10  
5 4  
0
RR  
SDBBP  
00001  
code  
6
11101  
5
5
Description  
A debug breakpoint occurs, immediately and unconditionally transferring control to the exception  
handler.  
The code field in the SDBBP instruction is available for use as software parameters to pass  
additional information. The exception handler can retrieve it by loading the contents of the memory  
word containing the instruction. See Section 9.3, Debug Exceptions, for details.  
The SDBBP instruction may not be used within the user’s program; it is intended for use by  
development tools. Executing the SDBBP instruction on a device without EJTAG causes a  
Reserved Instruction exception.  
Exceptions  
Debug Breakpoint exception  
Reserved Instruction exception  
B-149  
Appendix B 16-Bit ISA Details  
SEB rx  
Sign-Extend Byte  
Operation  
rx ⇐ (rx[7])24 || rx[7:0]  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
SEB  
100  
rx  
3
10001  
5
11101  
5
3
Description  
The least-significant byte in general-purpose register rx is sign-extended. The result is placed back  
into rx.  
Exceptions  
None  
B-150  
Appendix B 16-Bit ISA Details  
SEH rx  
Sign-Extend Halfword  
Operation  
rx ⇐ (rx[15])16 || rx[15:0];  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
SEH  
101  
rx  
3
10001  
5
11101  
5
3
Description  
The low-order halfword in general-purpose register rx is sign-extended. The result is placed back  
into rx.  
Exceptions  
None  
B-151  
Appendix B 16-Bit ISA Details  
SH ry, offset (base)  
Store Halfword  
Operation  
ry = {zero-extend (offset || 0) + (base)}  
ry = {sign-extend (offset) + (base)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
SH  
base  
3
ry  
3
offset  
5
11001  
5
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
SH  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
base  
3
ry  
3
offset[4:0]  
5
11001  
5
5
5
Description  
The 5-bit immediate offset is shifted left by one bit, zero-extended and added to the contents of  
general-purpose register base to form an effective address (EA). The low-order halfword in  
general-purpose register ry is stored at the memory location addressed by the EA.  
The high-order halfword in ry is simply ignored; so there is no distinction between signed and  
unsigned stores.  
Since the 5-bit offset is shifted left by one bit, the offset range is 0 to 62, in increments of two. If the  
offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate in  
the range of -32768 to +32767. When EXTENDed, the offset operand is not shifted at all.  
Exceptions  
Address Error exception  
B-152  
Appendix B 16-Bit ISA Details  
Example  
SH r3,4(r2)  
Assume that registers r2 and r3 contain 0x0000_0400 and 0x0123_4567 respectively. Since the  
offset value is shifted left by one bit by the processor hardware, the assembler/linker turns the  
specified offset (4 or binary 0100) into a code of 2 (binary 0010). Thus the instruction code for this  
store instruction becomes 0xCA62.  
In big-endian mode, 0x45 and 0x67 are stored to the memory locations at addresses 0x404 and  
0x405 respectively. In little-endian mode, 0x67 and 0x45 are stored to the memory locations at  
addresses 0x404 and 0x405 respectively.  
Memory  
Byte  
Byte  
Halfword Boundary  
Halfword Boundary  
Halfword Boundary  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
r2  
+4  
The offset, 1, is shifted  
left by 1 bit.  
0x45  
0x67  
0x67  
0x45  
Big-Endian  
Little-Endian  
r3  
0x0123_4567  
Store  
CPU  
Register  
Ø
Memory  
Halfword  
B-153  
Appendix B 16-Bit ISA Details  
SH ry, offset (fp)  
Store Halfword  
Operation  
ry = {zero-extend (offset || 0) + (fp)}  
ry = {sign-extend (offset || 0) + (fp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
8
8
7
1
1
6
6
1
1
0
1
1
FP-H  
ry  
3
offset[6:1]  
6
10111  
5
31  
27 26  
21 20  
16 15  
11 10  
7
1
1
5
4
0
1
1
EXTEND  
11110  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
10111  
5
ry  
3
00  
offset[4:1]  
5
5
2
4
Description  
The 6-bit immediate offset is shifted left by one bit, zero-extended and added to the contents of the  
fp register (r30) to form an effective address (EA). The low-order halfword in general-purpose  
register ry is stored at the memory location addressed by the EA.  
The high-order halfword in ry is simply ignored; so there is no distinction between signed and  
unsigned stores.  
Since the 6-bit offset is shifted left by one bit, the offset range is 0 to 126, in increments of two. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate.  
When EXTENDed, the offset operand is shifted left by one bit to allow an offset of -32768 to  
+32766.  
Exceptions  
Address Error exception  
B-154  
Appendix B 16-Bit ISA Details  
Example  
SH r3,4(fp)  
Assume that fp (r30) and r3 registers contain 0x0000_0400 and 0x0123_4567 respectively. Since  
the offset value is shifted left by one bit by the processor hardware, the assembler/linker turns the  
specified offset (4 or binary 0100) into a code of 2 (binary 0010). Thus the instruction code for this  
store instruction becomes 0xBB85.  
In big-endian mode, 0x45 and 0x67 are stored to the memory locations at addresses 0x404 and  
0x405 respectively. In little-endian mode, 0x67 and 0x45 are stored to the memory locations at  
addresses 0x404 and 0x405 respectively.  
Memory  
Byte  
Byte  
Halfword Boundary  
Halfword Boundary  
Halfword Boundary  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
r30  
+4  
The offset, 1, is shifted  
left by 1 bit.  
0x45  
0x67  
0x67  
0x45  
Big-Endian  
Little-Endian  
r3  
0x0123_4567  
Store  
CPU  
Register  
Ø
Memory  
Halfword  
B-155  
Appendix B 16-Bit ISA Details  
SH ry, offset (sp)  
Store Halfword  
Operation  
ry = {zero-extend (offset || 0) + (sp)}  
ry = {sign-extend (offset || 0) + (sp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
8
8
7
1
1
6
6
1
1
0
0
1
SP-H  
ry  
3
offset[6:1]  
6
10111  
5
31  
27 26  
21 20  
16 15  
11 10  
7
1
1
5
4
0
0
1
EXTEND  
11110  
offset[10:5]  
6
offset[15:11]  
10111  
5
ry  
3
00  
offset[4:1]  
EXTENDED  
5
5
2
4
Description  
The 6-bit immediate offset is shifted left by one bit, zero-extended and added to the contents of the  
sp (r29) register to form an effective address (EA). The low-order halfword in general-purpose  
register ry is stored at the memory location addressed by the EA.  
The high-order halfword in ry is simply ignored; so there is no distinction between signed and  
unsigned stores.  
Since the 6-bit offset is shifted left by one bit, the offset range is 0 to 126, in increments of two. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate.  
When EXTENDed, the offset operand is shifted left by one bit allow an offset of -32768 to +32766.  
Exceptions  
Address Error exception  
B-156  
Appendix B 16-Bit ISA Details  
Example  
SH r3,4(sp)  
Assume that the sp (r29) and r3 registers contain 0x0000_0400 and 0x0123_4567 respectively.  
Since the offset value is shifted left by one bit by the processor hardware, the assembler/linker turns  
the specified offset (4 or binary 0100) into a code of 2 (binary 0010). Thus the instruction code for  
this store instruction becomes 0xBB84.  
In big-endian mode, 0x45 and 0x67 are stored to the memory locations at addresses 0x404 and  
0x405 respectively. In little-endian mode, 0x67 and 0x45 are stored to the memory locations at  
addresses 0x404 and 0x405 respectively.  
Memory  
Byte  
Byte  
Halfword Boundary  
Halfword Boundary  
Halfword Boundary  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
r29  
+4  
The offset, 1, is shifted  
left by 1 bit.  
0x45  
0x67  
0x67  
0x45  
Big-Endian  
Little-Endian  
r3  
0x0123_4567  
Store  
CPU  
Register  
Ø
Memory  
Halfword  
B-157  
Appendix B 16-Bit ISA Details  
SLL rx, ry, sa  
Shift Left Logical  
Operation  
rx ⇐ ry << sa  
Instruction Encoding  
15  
11 10  
11 10  
8 7  
5 4  
2 1  
0
SHIFT  
00110  
SLL  
rx  
3
ry  
3
sa  
3
00  
2
5
31  
27 26  
22 21  
16 15  
8
7
5
4
0
EXTEND  
11110  
SHIFT  
00110  
EXTENDED  
sa[4:0]  
5
000000  
6
rx  
3
ry  
3
000000  
5
5
5
Description  
The contents of general-purpose register ry is shifted left by sa bits. Zeros are supplied to the  
vacated positions on the right. The result is placed into general-purpose register rx. The sa field is  
only 3-bits wide. Thus the shift amount is restricted to 1 to 8. The sa value of 000 is defined as a  
shift of 8 bits.  
If the shift amount does not fit in the sa field, the instruction is EXTENDed to provide a full 5-bit  
field for a shift of 0 to 31.  
Example  
Assume that register r2 contains 0x2170_ADC5. Then, executing the instruction:  
SLL r3,r2,4  
places 0x170A_DC50 in register r3, as shown below.  
r2  
0010 0001 0111 0000 1010 1101 1100 0101  
Shifted left  
by 4 bits  
Padded with zeros  
r3  
0001 0111 0000 1010 1101 1100 0101 0000  
B-158  
Appendix B 16-Bit ISA Details  
SLL ry, sa5  
Shift Left Logical  
Operation  
ry ⇐ ry << sa5  
Instruction Encoding  
15  
11 10  
8
7
1
1
6
2 1 0  
RRR  
ry  
3
sa[4:0]  
5
00  
11100  
5
2
Description  
The contents of general-purpose register ry is shifted left by sa bits. Zeros are supplied to the  
vacated positions on the right. The result is placed back into ry. The sa field is 5-bits wide; thus the  
possible shift amount is 1 to 31. The sa value may not be 00000.  
Example  
Assume that register r2 contains 0x2170_ADC5. Then, executing the instruction:  
SLL r2,4  
places 0x170A_DC50 in register r2, as shown below.  
r2  
0010 0001 0111 0000 1010 1101 1100 0101  
Shifted left  
by 4 bits  
Padded with zeros  
r2  
0001 0111 0000 1010 1101 1100 0101 0000  
B-159  
Appendix B 16-Bit ISA Details  
SLLV ry, rx  
Shift Left Logical Variable  
Operation  
ry << 5 LSBs of rx  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
SLLV  
rx  
3
ry  
3
11101  
00100  
5
5
Description  
The contents of general-purpose register ry is shifted left the number of bits specified by the five  
least-significant bits of general-purpose register rx. Zeros are supplied to the vacated positions on  
the right. The result is placed back into general-purpose register ry.  
Exceptions  
None  
B-160  
Appendix B 16-Bit ISA Details  
SLT rx, ry  
Set On Less Than  
Operation  
if rx < ry then t8 ⇐ 1; else t8 ⇐ 0  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
SLT  
rx  
3
ry  
3
11101  
00010  
5
5
Description  
The contents of general-purpose register rx is compared to the contents of general-purpose register  
ry. Both rx and ry are treated as signed integers. If rx is less than ry, condition code register t8 (r24)  
is set to one. Otherwise, t8 is set to zero.  
No Integer Overflow exception occurs under any circumstances. The comparison is valid even if the  
subtraction performed for comparison results in overflow.  
Exceptions  
None  
B-161  
Appendix B 16-Bit ISA Details  
SLTI rx, immediate  
Set On Less Than Immediate  
Operation  
if rx < 024 || (immediate7..0) then t8 ⇐ 1; else t8 ⇐ 0  
(EXTENDED)  
if rx < (immediate15)16|| (immediate15..0) then t8 ⇐ 1; else t8 ⇐ 0  
Instruction Encoding  
15  
11 10  
11 10  
8 7  
0
SLTI  
rx  
3
immediate  
8
01010  
5
31  
27 26  
21 20  
16 15  
8
7
5
4
0
EXTEND  
11110  
SLTI  
EXTENDED  
imm[10:5]  
6
imm[15:11]  
rx  
3
000  
3
imm[4:0]  
5
01010  
5
5
5
Description  
The 8-bit immediate is zero-extended and compared to the contents of general-purpose register rx.  
The immediate and rx are compared as signed integers. If rx is less than immediate, condition code  
register t8 (r24) is set to 1. Otherwise, t8 is set to zero.  
No Integer Overflow exception occurs under any circumstances. The comparison is valid even if the  
subtraction performed for comparison results in overflow.  
With the 8-bit immediate field, the immediate range is 0 to 255. If a number is outside this range,  
the instruction is EXTENDed to provide a 16-bit signed immediate in the range of -32768 to  
+32767.  
Exceptions  
None  
B-162  
Appendix B 16-Bit ISA Details  
SLTIU rx, immediate  
Set On Less Than Immediate Unsigned  
Operation  
if (0 || rx) < 025 || (immediate7..0) then t8 ⇐ 1; else t8 ⇐ 0  
(EXTENDED)  
if (0 || rx) < (immediate15)17|| (immediate15..0) then t8 ⇐ 1; else t8 ⇐ 0  
Instruction Encoding  
15  
11 10  
11 10  
8 7  
0
SLTIU  
01011  
rx  
3
immediate  
8
5
31  
27 26  
21 20  
16 15  
8
7
5
4
0
EXTEND  
11110  
SLTIU  
01011  
EXTENDED  
imm[10:5]  
6
imm[15:11]  
rx  
3
000  
3
imm[4:0]  
5
5
5
5
Description  
The 8-bit immediate is zero-extended and compared to the contents of general-purpose register rx.  
The immediate and rx are compared as unsigned integers. If rx is less than immediate, condition  
code register t8 (r24) is set to one. Otherwise, t8 is set to zero.  
No Integer Overflow exception occurs under any circumstances. The comparison is valid even if the  
subtraction performed for comparison results in overflow.  
With the 8-bit immediate field, the immediate range is 0 to 255. If a number is outside this range,  
the instruction is EXTENDed to provide a 16-bit signed immediate in the range of -32768 to  
+32767.  
Exceptions  
None  
B-163  
Appendix B 16-Bit ISA Details  
SLTU rx, ry  
Set On Less Than Unsigned  
Operation  
if (0 || rx) < (0 || ry) then t8 ⇐ 1; else t8 ⇐ 0  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
SLTU  
00011  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register rx is compared to the contents of general-purpose register  
ry. Both rx and ry are treated as unsigned integers. If rx is less than ry, condition code register t8  
(r24) is set to one. Otherwise, t8 is set to zero.  
No Integer Overflow exception occurs under any circumstances. The comparison is valid even if the  
subtraction performed for comparison results in overflow.  
Exceptions  
None  
B-164  
Appendix B 16-Bit ISA Details  
SRA rx, ry, sa  
Shift Right Arithmetic  
Operation  
rx ⇐ ry >> sa  
Instruction Encoding  
15  
11 10  
11 10  
8 7  
5 4  
2 1  
0
SHIFT  
00110  
SRA  
rx  
3
ry  
3
sa  
3
11  
2
5
31  
27 26  
22 21  
16 15  
8
7
5
4
0
EXTEND  
11110  
SHIFT  
00110  
EXTENDED  
sa[4:0]  
5
000000  
6
rx  
3
ry  
3
000011  
5
5
5
Description  
The contents of general-purpose register ry is shifted right by sa bits. The sign bit is copied to the  
vacated positions on the left. The result is placed into general-purpose register rx. The sa field is  
only 3-bits wide. Thus the shift amount is restricted to 1 to 8. The sa value of 000 is defined as a  
shift of 8 bits.  
If the shift amount does not fit in the sa field, the instruction is EXTENDed to provide a full 5-bit  
field for shift of 0 to 31.  
Example  
Assume that register r2 contains 0xB521_AE5E. Then, executing the instruction:  
SRA r3,r2,8  
places 0xFFB5_21AE in register r3, as shown below.  
r2 1 011 0101 0010 0001 1010 0101 1110  
Shifted right by 8 bits  
1011 0101 0010 0001 1010  
Sign Bit  
r3 1111 1111  
B-165  
Appendix B 16-Bit ISA Details  
SRA ry, sa5  
Shift Right Arithmetic  
Operation  
ry ⇐ ry >> sa5  
Instruction Encoding  
15  
11 10  
8
7
0
6
2 1 0  
RRR  
ry  
3
sa[4:0]  
5
10  
11100  
5
1
2
Description  
The contents of general-purpose register ry is shifted right by sa bits. The sign bit is copied to the  
vacated positions on the left. The result is placed back into ry. The sa field is 5-bits wide; thus the  
possible shift amount is 1 to 31. The sa value may not be 00000.  
Example  
Assume that register r2 contains 0xB521_AE5E. Then, executing the instruction:  
SRA r2,8  
places 0xFFB5_21AE back in register r2, as shown below.  
r2 1 011 0101 0010 0001 1010 0101 1110  
Shifted right by 8 bits  
1011 0101 0010 0001 1010  
Sign Bit  
r2 1111 1111  
B-166  
Appendix B 16-Bit ISA Details  
SRAV ry, rx  
Shift Right Arithmetic Variable  
Operation  
ry >> 5 LSBs of rx  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
SRAV  
00111  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register ry is shifted right the number of bits specified by the five  
least-significant bits of general-purpose register rx. The sign bit is copied to the vacated positions on  
the left. The result is placed back into general-purpose register ry.  
Exceptions  
None  
B-167  
Appendix B 16-Bit ISA Details  
SRL rx, ry, sa  
Shift Right Logical  
Operation  
rx ⇐ ry >> sa  
Instruction Encoding  
15  
11 10  
11 10  
8 7  
5 4  
2 1  
0
SHIFT  
00110  
SRL  
rx  
3
ry  
3
sa  
3
10  
2
5
31  
27 26  
22 21  
16 15  
8
7
5
4
0
EXTEND  
11110  
SHIFT  
00110  
EXTENDED  
sa[4:0]  
5
000000  
6
rx  
3
ry  
3
000010  
5
5
5
Description  
The contents of general-purpose register ry is shifted right by sa bits. Zeros are supplied to the  
vacated positions on the left. The result is placed into general-purpose register rx. The sa field is  
only 3-bits wide. Thus the shift amount is restricted to 1 to 8. The sa value of 000 is defined as a  
shift of 8 bits.  
If the shift amount does not fit in the sa field, the instruction is EXTENDed to provide a full 5-bit  
field for a shift of 0 to 31.  
Example  
Assume that register r2 contains 0xB521_4C5E. Then, executing the instruction:  
SRL r3,r2,8  
places 0x00B5_214C in register r3, as shown below.  
r2 1011 0101 0010 0001 1000 1100 0101 1110  
Padded with zeros  
r3 0000 0000 1011 0101 0010 0001 0100 1100  
Shifted right by 8 bits  
B-168  
Appendix B 16-Bit ISA Details  
SRL ry, sa5  
Shift Right Logical  
Operation  
ry ⇐ ry >> sa5  
Instruction Encoding  
15  
11 10  
8
7
1
1
6
2 1 0  
RRR  
ry  
3
sa[4:0]  
5
10  
11100  
5
2
Description  
The contents of general-purpose register ry is shifted right by sa bits. Zeros are supplied to the  
vacated positions on the left. The result is placed back into ry. The sa field is 5-bits wide; thus the  
possible shift amount is 1 to 31. The sa value may not be 00000.  
Example  
Assume that register r2 contains 0xB521_4C5E. Then, executing the instruction:  
SRL r2,8  
places 0x00B5_214C back in register r2, as shown below.  
r2 1011 0101 0010 0001 0100 1100 0101 1110  
Padded with zeros  
r2 0000 0000 1011 0101 0010 0001 0100 1100  
Shifted right by 8 bits  
B-169  
Appendix B 16-Bit ISA Details  
SRLV ry, rx  
Shift Right Logical Variable  
Operation  
ry >> 5 LSBs of rx  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
SRLV  
00110  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register ry is shifted right the number of bits specified by the five  
least-significant bits of general-purpose register rx. Zeros are supplied to the vacated positions on  
the left. The result is placed back into general-purpose register ry.  
Example  
None  
B-170  
Appendix B 16-Bit ISA Details  
SSUB ry, rx, ry  
Saturated Subtract  
Operation  
if overflow on rx －ry then ry ⇐ 0x7FFF_FFFF ( rx ≥ 0) or 0x8000_0000 ( rx < 0 )  
else ry ⇐ rx －ry  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
SSUB  
10101  
rx  
3
ry  
3
11101  
5
5
Description  
The contents of general-purpose register ry is subtracted from the contents of general-purpose  
register rx. On overflow, the remainder saturates to the largest representable positive number  
(0x7FFF_FFFF) if rx is zero or a positive number and to the smallest representable negative number  
(0x8000_0000) if rx is a negative number. The result is placed into ry. If overflow does not occur,  
the remainder is placed into ry. Both rx and ry are treated as signed integers.  
An Integer Overflow exception never occurs on overflow.  
Exceptions  
None  
B-171  
Appendix B 16-Bit ISA Details  
SUBU rz, rx, ry  
Subtract Unsigned  
Operation  
rz ⇐ rx – ry  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
2 1  
0
RRR  
SUBU  
11  
rx  
3
ry  
3
rz  
3
11100  
5
2
Description  
The contents of general-purpose register ry is subtracted from the contents of general-purpose  
register rx. The remainder is placed into general-purpose register rz.  
No Integer Overflow exception occurs under any circumstances.  
Exceptions  
None  
B-172  
Appendix B 16-Bit ISA Details  
SW ra, offset (sp)  
Store Word  
Operation  
ra = {zero-extend (offset || 00) + (sp)}  
ra = {sign-extend (offset) + (sp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
8 7  
0
I8  
SWRASP  
offset  
8
01100  
010  
3
5
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
I8  
SWRASP  
010  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
000  
3
offset[4:0]  
01100  
5
5
5
3
5
Description  
The 8-bit immediate offset is shifted left by two bits, zero-extended and added to the contents of  
stack pointer register sp (r29) to form an effective address (EA). The word in link register ra (r31) is  
stored at the memory location addressed by the EA.  
Since the 8-bit offset is shifted left by two bits, the offset range is 0 to 1024, in increments of four. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate  
in the range of –32768 to +32767.  
Exceptions  
Address Error exception  
Example  
SW ra,4(sp)  
Assume that the sp and ra registers contain 0x0000_0400 and 0x0123_4567 respectively. Since the  
offset value is shifted left by two bits by the processor hardware, the assembler/linker turns the  
specified offset (4 or binary 0100) into a code of 1 (binary 0001). Thus the instruction code for this  
store instruction is 0x3101.  
In big-endian mode, 0x0123_4567 is stored to the memory locations at addresses 0x0404 to 0x0407.  
B-173  
Appendix B 16-Bit ISA Details  
Memory  
Byte  
0x0000_0400  
+4  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
sp  
The offset, 1, is shifted  
left by 2 bits.  
0x01  
0x23  
0x45  
0x67  
ra  
0x0123_4567  
Big-Endian  
B-174  
Appendix B 16-Bit ISA Details  
SW ry, offset (fp)  
Store Word  
Operation  
ry = {zero-extend (offset || 00) + (fp)}  
ry = {sign-extend (offset) + (fp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
11 10  
8
8
7
7
5
5
4
4
0
0
SWFP  
11111  
111  
3
ry  
3
offset[4:0]  
5
5
31  
27 26  
21 20  
16 15  
EXTEND  
11110  
SWFP  
11111  
offset[10:5]  
6
offset[15:11]  
111  
3
ry  
3
offset[4:0]  
5
EXTENDED  
5
5
5
Description  
The 5-bit immediate offset is shifted left by two bits, zero-extended and added to the contents of  
fp register (r30) to form an effective address (EA). The word in general-purpose  
register ry is stored at the memory location addressed by the EA.  
Since the 5-bit offset is shifted left by two bits, the offset range is 0 to 124, in increments of four. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate  
in the range of -32768 to +32767.  
Exceptions  
Address Error exception  
Example  
SW r3,4(fp)  
Assume that registers fp and r3 contain 0x0000_0400 and 0x0123_4567 respectively. Since the  
offset value is shifted left by two bits by the processor hardware, the assembler/linker turns the  
specified offset (4 or binary 0100) into a code of 1 (binary 0001). Thus the instruction code for this  
store instruction becomes 0xFF61.  
In big-endian mode, 0x123_4567 is stored to the memory locations at addresses 0x404 to 0x407. In  
little-endian mode, 0x6745_2301 is stored to the memory locations at addresses 0x404 to 0x407.  
B-175  
Appendix B 16-Bit ISA Details  
Memory  
Byte  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
0x0000_0400  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
r30  
+4  
The offset, 1, is shifted  
left by 2 bits.  
0x67  
0x45  
0x23  
0x01  
0x01  
0x23  
0x45  
0x67  
r3  
0x0123_4567  
Little-Endian  
Big-Endian  
B-176  
Appendix B 16-Bit ISA Details  
SW rx, offset (sp)  
Store Word  
Operation  
rx = {zero-extend (offset || 00) + (sp)}  
rx = {sign-extend (offset) + (sp)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
8 7  
0
SWSP  
11010  
rx  
3
offset  
8
5
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
SWSP  
11010  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
rx  
3
000  
3
offset[4:0]  
5
5
5
5
Description  
The 8-bit immediate offset is shifted left by two bits, zero-extended and added to the contents of  
stack pointer register sp (r29) to form an effective address (EA). The word in general-purpose  
register rx is stored at the memory location addressed by the EA.  
Since the 8-bit offset is shifted left by two bits, the offset range is 0 to 1020, in increments of four. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate  
in the range of –32768 to +32767.  
Exceptions  
Address Error exception  
Example  
SW r3,4(sp)  
Assume that the sp and r3 registers contain 0x0000_0400 and 0x0123_4567 respectively. Since the  
offset value is shifted left by two bits by the processor hardware, the assembler/linker turns the  
specified offset (4 or binary 0100) into a code of 1 (binary 0001). Thus the instruction code for this  
store instruction is 0xD301.  
In big-endian mode, 0x0123_4567 is stored to the memory locations at addresses 0x404 to 0x407.  
B-177  
Appendix B 16-Bit ISA Details  
Memory  
Byte  
0x0000_0400  
+4  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
sp  
The offset, 1, is shifted  
left by 2 bits.  
0x01  
0x23  
0x45  
0x67  
r3  
0x0123_4567  
Big-Endian  
B-178  
Appendix B 16-Bit ISA Details  
SW ry, offset (base)  
Store Word  
Operation  
ry = {zero-extend (offset || 00) + (base)}  
ry = {sign-extend (offset) + (base)}  
(EXTENDED)  
Instruction Encoding  
15  
11 10  
base  
8 7  
5 4  
0
SW  
ry  
3
offset  
5
11011  
5
3
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
SW  
EXTENDED  
offset[10:5]  
6
offset[15:11]  
base  
3
ry  
3
offset[4:0]  
5
11011  
5
5
5
Description  
The 5-bit immediate offset is shifted left by two bits, zero-extended and added to the contents of  
general-purpose register base to form an effective address (EA). The word in general-purpose  
register ry is stored at the memory location addressed by the EA.  
Since the 5-bit offset is shifted left by two bits, the offset range is 0 to 124, in increments of four. If  
the offset is outside this range, the instruction is EXTENDed to provide a 16-bit signed immediate  
in the range of -32768 to +32767. When EXTENDed, the offset operand is not shifted at all.  
Exceptions  
Address Error exception  
Example  
SW r3,4(r2)  
Assume that registers r2 and r3 contain 0x0000_0400 and 0x0123_4567 respectively. Since the  
offset value is shifted left by two bits by the processor hardware, the assembler/linker turns the  
specified offset (4 or binary 0100) into a code of 1 (binary 0001). Thus the instruction code for this  
store instruction becomes 0xDAE1.  
In big-endian mode, 0x123_4567 is stored to the memory locations at addresses 0x0404 to 0x0407. In  
little-endian mode, 0x6745_2301 is stored to the memory locations at addresses 0x0404 to 0x0407.  
B-179  
Appendix B 16-Bit ISA Details  
Memory  
Byte  
Memory  
Byte  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
0x0000_0400  
r2  
0x400  
0x401  
0x402  
0x403  
0x404  
0x405  
0x406  
0x407  
+4  
The offset, 1, is shifted  
left by 2 bits.  
0x67  
0x45  
0x23  
0x01  
0x01  
0x23  
0x45  
0x67  
r3  
0x0123_4567  
Little-Endian  
Big-Endian  
B-180  
Appendix B 16-Bit ISA Details  
SYNC  
Synchronize  
Operation  
メモリ同期操作  
Instruction Encoding  
31  
27 26  
22 21  
16 15  
11 10  
5
4
0
EXTEND  
11110  
EXTENDED  
00000  
5
000000  
11101  
5
000000  
6
01111  
5
5
6
Description  
The SYNC instruction interlocks the instruction pipeline until loads and stores performed prior to  
the present instruction are completed before any instructions after this instruction are allowed to  
start. See 5.2.4, SYNC Instruction.  
If there is no data dependency, the TX19A continues to execute subsequent instructions. This is  
called non-blocking loads. By virtue of non-blocking loads, the instruction pipeline can work on  
nondependent instructions.  
Exceptions  
None  
B-181  
Appendix B 16-Bit ISA Details  
SYSCALL code  
System Call  
Operation  
System call exception  
Instruction Encoding  
31  
27 26  
22 21  
16 15  
11 10  
5
4
0
EXTEND  
11110  
EXTENDED  
code[10:6]  
5
code[16:11]  
6
11101  
5
code[5:0]  
6
01100  
5
5
Description  
A System Call exception occurs, immediately and unconditionally transferring control to the  
exception handler.  
The code field in a SYSCALL instruction is available for use as software parameters to pass  
additional information. To examine these bits, load the contents of the instruction at which the EPC  
register points. For details on System Call exceptions, see Section 9.1.10, System Call Exceptions.  
Exceptions  
System call exception  
B-182  
Appendix B 16-Bit ISA Details  
WAIT  
Enter Standby Mode  
Operation  
if Status[RP] = 1 then DOZE mode  
else HALT mode  
Instruction Encoding  
31  
27 26  
22 21  
16 15  
11 10  
5
4
0
EXTEND  
11110  
EXTENDED  
01000  
5
000000  
6
11101  
5
000000  
6
00000  
5
5
Description  
The WAIT instruction is used to freeze the instruction pipeline to reduce the processor’s power  
consumption. If the RP bit in the Status register is set, the processor enters DOZE mode. If the RP  
bit is cleared, the processor enters HALT mode. See Chapter 10, Low-Power Modes.  
The WAIT instruction must not be set in a delay slot of the branch or jump instruction.  
Once the MTC0 instruction writes to the Status register, at least two instructions  
must be executed before the WAIT instruction. Otherwise, the operation is undefined.  
Exceptions  
Coprocessor Unusable exception  
B-183  
Appendix B 16-Bit ISA Details  
XOR rx, ry  
Exclusive OR  
Operation  
rx ⇐ rx XOR ry  
Instruction Encoding  
15  
11 10  
8 7  
5 4  
0
RR  
XOR  
rx  
3
ry  
3
11101  
01110  
5
5
Description  
The contents of general-purpose register rx is exclusive-ORed with the contents of general-purpose  
register ry. The result is placed back into general-purpose register rx.  
Exceptions  
None  
B-184  
Appendix B 16-Bit ISA Details  
XORI ry, immediate  
Exclusive OR Immediate  
Operation  
ry ⇐ ry XOR (016 || immediate15..0  
)
Instruction Encoding  
31  
27 26  
21 20  
16 15  
11 10  
8
7
5
4
0
EXTEND  
11110  
XORI  
110  
Imm[10:5]  
6
Imm[15:11]  
01001  
5
ry  
3
Imm[4:0]  
5
EXTENDED  
5
5
3
Description  
The 16-bit immediate is zero-extended and exclusive-ORed with the contents of general-purpose  
register ry. The result is placed back into ry.  
The immediate field is 16 bits in length. If the immediate size is larger than that, you need to put it  
in a general-purpose register and use the XOR instruction (see Section 3.3.2, 32-Bit Constants).  
Exceptions  
None  
Example  
Assume that register r4 contains 0x0000_7350. Then, executing the instruction:  
XORI r4,0x1234  
places 0x0000_6164 back in register r4, as shown below.  
r4 0000 0000 0000 0000 0111 0011 0101 0000  
XOR  
0000 0000 0000 0000 0001 0010 0011 0100  
Zero-Extended  
r4 0000 0000 0000 0000 0110 0001 0110 0100  
B-185  
Appendix B 16-Bit ISA Details  
ZEB rx  
Zero-Extend Byte  
Operation  
rx ⇐ 024 || rx[7:0]  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
ZEB  
000  
rx  
3
10001  
5
11101  
5
3
Description  
The least-significant byte in general-purpose register rx is zero-extended. The result is placed back  
into rx.  
Exceptions  
None  
B-186  
Appendix B 16-Bit ISA Details  
ZEH rx  
Zero-Extend Halfword  
Operation  
rx ⇐ 016 || rx[15:0];  
Instruction Encoding  
15  
11 10  
8
7
5
4
0
RR  
ZEH  
001  
rx  
3
10001  
5
11101  
5
3
Description  
The low-order halfword in general-purpose register rx is zero-extended. The result is placed back  
into rx.  
Exceptions  
None  
B-187  
Appendix C Programming Restrictions  
Appendix C Programming Restrictions  
In a pipelined machine like the TX19A, there are certain instructions which may disrupt the smooth  
operation of the pipeline due to the very pipeline structure. This appendix lists the restrictions that  
need to be observed in writing assembly-language programs.  
C.1 32-Bit ISA Restrictions  
Table C-1 Load and Store Instructions  
Instructions  
Restrictions  
The target address generated by these instructions must be on a halfword boundary;  
i.e., it must have the least-significant bit cleared. Otherwise, an Address Error  
exception occurs.  
LH  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
LHU  
SH  
The target address generated by these instructions must be on a word boundary;  
i.e., it must have the two least-significant bits cleared. Otherwise, an Address Error  
exception occurs.  
LW  
LWU  
SW  
Table C-2 Jump Instructions  
Restrictions  
Instructions  
• Register rd may not be the same one as register rs because such an instruction is  
not restartable after the exception has been serviced.  
JALR  
(rd,) rs  
• In 32-bit ISA mode, all instructions must be word-aligned. Therefore, when  
jumping to a 32-bit routine, the two least-significant bits of the target register (rs)  
must be zero. Otherwise, an Address Error exception occurs when the processor  
fetches the instruction at the jump destination.  
In 32-bit ISA mode, all instructions must be word-aligned. Therefore, when jumping  
to a 32-bit routine, the two least-significant bits of the target register (rs) must be  
zero. Otherwise, an Address Error exception occurs when the processor fetches the  
JR  
rs  
instruction at the jump destination.  
Any jump instruction may not be in a jump or branch delay slot. The operation of the  
jump instruction is undefined if it is in a jump or branch delay slot.  
All jump instructions  
Table C-3 Branch and Branch-Likely Instructions  
Restrictions  
Instructions  
Register rs may not be r31 because such an instruction is not restartable after the  
exception has been serviced.  
BGEZAL(L) rs, offset  
BLTZAL(L) rs, offset  
All branch instructions  
All the branch instructions may not be in a jump or branch delay slot. The operation of  
the branch instructions are undefined if they are in a jump or branch delay slot.  
C-1  
Appendix C Programming Restrictions  
Table C-4 System Control Coprocessor (CP0) Instructions  
Instructions  
Restrictions  
Attempts by a User-mode program to execute these instructions when the CU0 bit in  
the Status register is cleared causes a Coprocessor Unusable exception. Kernel mode  
programs can execute these instructions, regardless of the setting of the CU0  
bit.  
MTC0  
MFC0  
ERET  
WAIT  
rt, rd  
rt, rd  
• The DERET instruction does not have a delay slot.  
DERET  
• The operation of this instruction is undefined if the processor is not is in Debug  
mode (i.e., when the DM bit in the Debug register is cleared).  
• If you have used the MTC0 instruction to load the DEPC register with a return  
address, the debug exception handler must execute at least two instructions  
before issuing the DERET instruction.  
• Once the MTC0 instruction writes to the Status, EPC or ErrorEPC register, at  
MTC0  
rt, rd  
least two instructions must be executed before the ERET instruction. Otherwise,  
contents of the register become undefined.  
• Once the MTC0 instruction writes to the DEPC register, at least two instructions  
must be executed before the DERET instruction. Otherwise, the contents of the  
register become undefined.  
• The MTC0 instruction that modifies the contents of the SSCR register must be  
followed by two NOPs.  
These instructions may not be placed in a delay slot.  
WAIT  
ERET  
DERET  
WAIT  
Once the MTC0 instruction writes to the Status register, at  
least two instructions must be executed before the WAIT instruction. Otherwise,  
contents of the register become undefined.  
Table C-5 Special Instructions  
Restrictions  
Instructions  
The SDBBP instruction may not be used within the user’s program; it is intended for  
use by development tools.  
SDBBP  
C-2  
Appendix C Programming Restrictions  
C.2 16-Bit ISA Restrictions  
Table C-6 Load and Store Instructions  
Instructions  
Restrictions  
The target address generated by these instructions must be on a halfword boundary;  
i.e., it must have the least-significant bit cleared. Otherwise, an Address Error  
exception occurs.  
LH  
ry, offset(base)  
ry, offset(base)  
ry, offset(sp)  
ry, offset(fp)  
LHU  
LHU  
LHU  
SH  
ry, offset(base)  
ry, offset(sp)  
ry, offset(fp)  
SH  
SH  
The target address generated by these instructions must be on a word boundary;  
i.e., it must have the two least-significant bits cleared. Otherwise, an Address Error  
exception occurs.  
LW  
ry, offset(base)  
ry, offset(pc)  
ry, offset(sp)  
ry, offset(fp)  
LW  
LW  
LW  
SW  
SW  
SW  
SW  
ry, offset(base)  
ry, offset(sp)  
ry, offset(fp)  
ra, offset(sp)  
Table C-7 Jump Instructions  
Restrictions  
Instructions  
• Register rx may not be ra because such an instruction is not restartable after the  
exception has been serviced.  
• In 32-bit ISA mode, all instructions must be word-aligned. Therefore, when  
jumping to a 32-bit routine, the two least-significant bits of the target register (rx)  
must be zero. Otherwise, an Address Error exception occurs when the processor  
fetches the instruction at the jump destination.  
JALR  
ra, rx  
JALRC ra, rx  
In 32-bit ISA mode, all instructions must be word-aligned. Therefore, when jumping  
to a 32-bit routine, the two least-significant bits of the target register (rx) must be  
zero. Otherwise, an Address Error exception occurs when the processor fetches the  
instruction at the jump destination.  
JR  
rx  
rx  
JRC  
In 32-bit ISA mode, all instructions must be word-aligned. Therefore, when jumping  
to a 32-bit routine, the two least-significant bits of ra must be zero. Otherwise, an  
Address Error exception occurs when the processor fetches the instruction at the  
jump destination.  
JR  
ra  
ra  
JRC  
All jump instructions  
Any jump instructions may not be in a jump delay slot.  
Table C-8 Branch Instructions  
Instructions  
Restrictions  
All branch instructions  
Any branch instructions may not be in a jump delay slot.  
C-3  
Appendix C Programming Restrictions  
Table C-9 Special Instructions  
Instructions  
Restrictions  
The SDBBP instruction may not be used within the user’s program; it is intended for  
use by development tools.  
SDBBP  
Table C-10 EXTENDed Instructions  
Instructions  
Restrictions  
Any EXTENDed instructions may not be in a jump delay slot.  
All EXTENDed instructions  
Table C-11 System Control Coprocessor (CP0) Instructions  
Restrictions  
Instructions  
Attempts by a User-mode program to execute these instructions when the CU0 bit in  
the Status register is cleared causes a Coprocessor Unusable exception. Kernel mode  
programs can execute these instructions, regardless of the setting of the CU0  
bit.  
MTC0  
MFC0  
ERET  
WAIT  
rt, rd  
rt, rd  
• The DERET instruction does not have a delay slot.  
DERET  
• The operation of this instruction is undefined if the processor is not is in Debug  
mode (i.e., when the DM bit in the Debug register is cleared).  
• If you have used the MTC0 instruction to load the DEPC register with a return  
address, the debug exception handler must execute at least two instructions  
before issuing the DERET instruction.  
• Once the MTC0 instruction writes to the Status, EPC or ErrorEPC register, at  
least two instructions must be executed before the ERET instruction. Otherwise,  
contents of the register become undefined.  
MTC0  
rt, rd  
• Once the MTC0 instruction writes to the DEPC register, at least two instructions  
must be executed before the DERET instruction. Otherwise, contents of the  
register become undefined.  
The MTC0 instruction can not access the Config1, Config2, Config3, IER registers.  
MFC0  
MTC0  
WAIT  
rt, rd  
rt, rd  
These instructions may not be placed in a delay slot.  
ERET  
DERET  
WAIT  
Once the MTC0 instruction writes to the Status register, at  
least two instructions must be executed before the WAIT instruction. Otherwise,  
contents of the register become undefined.  
Table C-12 SAVE and RESTORE Instructions  
Instructions  
Restrictions  
At least one register must be specified to be saved or restored.  
All SAVE instructions  
All RESTORE instructions  
C-4  
Appendix D Compatibility Among TX19, TX19A and TX39 Architectures  
Appendix D Compatibility Among TX19, TX19A and  
TX39 Architectures  
Table D-1 shows the differences between Toshiba’s TX19A and TX19.  
Table D-1 Comparisons Between the TX19A and the TX19  
Feature  
TX19A  
TX19  
Application  
Low power, high code density  
Instruction Set  
CPU Register  
CP0 Registers  
MIPS16e-TX  
• 8 sets of general-purpose registers  
• Same as for TX19 in all other respects  
MIPS II + MIPS16 ASE  
• 32 general-purpose registers  
• Program counter (PC)  
• Least-significant bit of the PC represents current ISA  
mode.  
• 2 multiply-divide registers (HI/LO)  
• TX19A and TX19 assign coprocessor register numbers differently.  
• TX19A complies with the MIPS32 CP0; its register numbers and bit assignments greatly differ from those of  
TX19.  
Register Number  
TX19A  
TX19  
3
8
9
11  
12  
13  
14  
15  
16  
⎯
Config  
BadVAddr  
⎯
BadVAddr  
Count/IER  
Compare  
Status  
Cause  
EPC  
PRId  
Config/Config  
1,2,3  
⎯
Status  
Cause  
EPC  
PRId  
Debug  
17  
22  
23  
24  
30  
31  
⎯
SSCR  
Debug  
DEPC  
ErrorEPC  
DESAVE  
DEPC  
⎯
DESAVE  
⎯
⎯
IE  
Instruction  
Pipeline  
5-stage  
WBU  
32-bit wide, 4-deep  
None  
Multiply  
Latency / Execution = 2 / 1 cycles  
Latency / Execution = 2 / 1 cycles  
Instructions  
Multiply-and-Add  
Instructions  
Multiply-and-  
Subtract  
Latency / Execution = 2 / 1 cycles  
Latency / Execution = 35 / 24 cycles  
None  
Instructions  
Divide Instructions If the divide instruction is followed by an MFHI or MFLO instruction before the result is available, the pipeline  
stalls until the result does become available.  
16-Bit ISA  
EXTENDed  
Instructions  
1 cycle  
2 cycles  
• 2 software interrupts (IP[1:0])  
• 4 software interrupts (Sw[3:0])  
• 1 hardware interrupt from interrupt controller (7  
prioritized levels)  
Maskable  
Interrupts  
• 3 hardware interrupts from interrupt controller (IP[4:2])  
• GPR shadow sets are automatically switched, based  
on interrupt level.  
D-1  
Appendix D Compatibility Among TX19, TX19A and TX39 Architectures  
Feature  
TX19A  
TX19  
TX19A  
TX19  
Exception  
BEV = 1  
BEV = 0  
BEV = 1  
BEV = 0  
0xBFC0_0000  
0xBFC0_0480  
0xFF20_0200  
0xBFC0_0000  
0xBFC0_0200  
0xFF20_0200  
Reset/NMI  
Debug  
Exception  
Vector  
Addresses  
0xBFC0_0240  
0x8000_0140  
0x8000_0130  
0x8000_0120  
0x8000_0110  
0x8000_0160  
0x8000_0080  
Swi3  
Swi2  
Swi1  
Swi0  
−
−
−
−
0xBFC0_0230  
0xBFC0_0220  
0xBFC0_0210  
0xBFC0_0260  
0xBFC0_0380  
0xBFC0_0380  
or  
0x8000_0180  
or  
Interrupts  
0xBFC0_0400  
0x8000_0200  
Hardware  
Others  
0xBFC0_0380  
0x8000_0180  
D-2  
Appendix D Compatibility Among TX19, TX19A and TX39 Architectures  
Table D-2 gives comparisons of the 32-bit ISA of the TX19A, the TX19 and the TX39. Differences  
are highlighted in shaded boxes.  
Table D-2 Instruction Sets of the TX19A, the TX19 and the TX39  
Category  
Instruction  
TX19A 32-Bit ISA  
TX19 32-Bit ISA  
TX39  
Load Byte  
LB  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
LB  
rt, offset(base)  
LB  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
⎯
Load Byte Unsigned  
Load Halfword  
LBU  
LH  
LBU  
LH  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
rt, offset(base)  
LBU  
LH  
Load Halfword Unsigned  
Load Word  
LHU  
LW  
LHU  
LW  
LHU  
LW  
Load Word Left  
Load Word Right  
Store Byte  
LWL  
LWR  
SB  
LWL  
LWR  
SB  
LWL  
LWR  
SB  
Load/Store  
Store Halfword  
Store Word  
SH  
SH  
SH  
SW  
SW  
SW  
SWL  
SWR  
Store Word Left  
Store Word Right  
Synchronize  
SWL  
SWR  
SYNC  
ADDI  
ADDIU  
SWL  
SWR  
SYNC  
Add Immediate  
Add Immediate Unsigned  
rt, rs, immediate ADDI  
rt, rs, immediate ADDIU  
rt, rs, immediate ADDI  
rt, rs, immediate ADDIU  
rt, rs, immediate  
rt, rs, immediate  
Set On Less Than  
Immediate  
SLTI  
rt, rs, immediate SLTI  
rt, rs, immediate SLTIU  
rt, rs, immediate SLTI  
rt, rs, immediate SLTIU  
rt, rs, immediate  
rt, rs, immediate  
Set On Less Than  
Immediate Unsigned  
ALU  
Immediate  
SLTIU  
AND Immediate  
OR Immediate  
Exclusive-OR Immediate  
Load Upper Immediate  
Add  
ANDI  
ORI  
rt, rs, immediate ANDI  
rt, rs, immediate ORI  
rt, rs, immediate XORI  
rt, rs, immediate LUI  
rt, rs, immediate ANDI  
rt, rs, immediate ORI  
rt, rs, immediate XORI  
rt, rs, immediate LUI  
rt, rs, immediate  
rt, rs, immediate  
rt, rs, immediate  
rt, rs, immediate  
rd, rs, rt  
XORI  
LUI  
ADD  
ADDU  
SUB  
SUBU  
SLT  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
ADD  
ADDU  
SUB  
SUBU  
SLT  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
ADD  
ADDU  
SUB  
SUBU  
SLT  
Add Unsigned  
rd, rs, rt  
Subtract  
rd, rs, rt  
Subtract Unsigned  
Set On Less Than  
rd, rs, rt  
rd, rs, rt  
Set On Less Than Unsigned SLTU  
SLTU  
AND  
OR  
SLTU  
AND  
OR  
rd, rs, rt  
AND  
AND  
OR  
rd, rs, rt  
2/3-Operand  
Register  
Type  
OR  
rd, rs, rt  
Exclusive-OR  
NOR  
XOR  
NOR  
XOR  
NOR  
XOR  
NOR  
rd, rs, rt  
rd, rs, rt  
Count Leading Ones in  
Word  
CLO  
CLZ  
rd, rs  
rd, rs  
⎯
⎯
⎯
⎯
Count Leading Zeros in  
Word  
Move Conditional on Not  
Zero  
MOVN  
MOVZ  
rd, rs, rt  
rd, rs, rt  
⎯
⎯
⎯
⎯
Move Conditional on Zero  
D-3  
Appendix D Compatibility Among TX19, TX19A and TX39 Architectures  
Category  
Instruction  
TX19A 32-Bit ISA  
TX19 32-Bit ISA  
TX39  
Shift Left Logical  
SLL  
rd, rs, ra  
rd, rs, rt  
rd, rs, sa  
rd, rs, rt  
rd, rs, sa  
SLL  
rd, rs, ra  
rd, rs, rt  
rd, rs, sa  
rd, rs, rt  
rd, rs, sa  
SLL  
rd, rs, ra  
rd, rs, rt  
rd, rs, sa  
rd, rs, rt  
rd, rs, sa  
Shift Left Logical Variable  
Shift Right Logical  
SLLV  
SRL  
SLLV  
SRL  
SLLV  
SRL  
Shift  
Shift Right Logical Variable SRLV  
SRLV  
SRA  
SRLV  
SRA  
Shift Right Arithmetic  
SRA  
Shift Right Arithmetic  
Variable  
SRAV  
rd, rs, rt  
SRAV  
rd, rs, rt  
SRAV  
rd, rs, rt  
MUL  
rd, rs, rt  
rs, rt  
⎯
⎯
Multiply  
MULT  
MULT  
MULT  
MULT  
rs, rt  
MULT  
MULT  
rs, rt  
rd, rs, rt  
rd, rs, rt  
rd, rs, rt  
MULTU rs, rt  
MULTU rs, rt  
MULTU rs, rt  
Multiply Unsigned  
MULTU rd, rs, rt  
MULTU rd, rs, rt  
MULTU rd, rs, rt  
Divide  
DIV  
rs, rt  
rs, rt  
rd  
DIV  
rs, rt  
rs, rt  
rd  
DIV  
rs, rt  
rs, rt  
rd  
Divide Unsigned  
Move From HI  
Move From LO  
Move To HI  
Move To LO  
DIVU  
MFHI  
MFLO  
MTHI  
MTLO  
MADD  
MADD  
DIVU  
MFHI  
MFLO  
MTHI  
MTLO  
MADD  
MADD  
DIVU  
MFHI  
MFLO  
MTHI  
MTLO  
MADD  
MADD  
Multiply,  
Divide,  
Multiply-and-  
Add and  
Multiply-and-  
rd  
rd  
rd  
rd  
rd  
rd  
rd  
rd  
rd  
Subtract  
rs, rt  
rd, rs, rt  
rs, rt  
rd, rs, rt  
rs, rt  
rd, rs, rt  
Multiply-and-Add  
MADDU rs, rt  
MADDU rs, rt  
MADDU rs, rt  
Multiply-and-Add Unsigned  
Multiply and Subtract  
MADDU rd, rs, rt  
MADDU rd, rs, rt  
MADDU rd, rs, rt  
MSUB  
MSUB  
rs, rt  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
rd, rs, rt  
MSUBU rs, rt  
Multiply and Subtract  
Unsigned  
MSUBU rd, rs, rt  
Jump  
J
target  
J
target  
target  
target  
rs  
J
target  
target  
⎯
Jump And Link  
JAL  
JALX  
JR  
target  
JAL  
JALX  
JR  
JAL  
Jump  
Jump and Link exchange  
Jump Register  
target  
rs  
JR  
rs  
Jump And Link Register  
Unconditional Branch  
Branch On Equal  
Branch On Not Equal  
JALR  
B
(rd), rs  
offset  
JALR  
(rd), rs  
⎯
JALR  
(rd), rs  
⎯
BEQ  
BNE  
rs, rt, offset  
rs, rt, offset  
BEQ  
BNE  
rs, rt, offset  
rs, rt, offset  
BEQ  
BNE  
rs, rt, offset  
rs, rt, offset  
Branch On Greater Than  
Zero  
BGTZ  
BGEZ  
rs, offset  
BGTZ  
rs, offset  
BGTZ  
rs, offset  
Branch On Greater Than  
Zero or Equal to Zero  
rs, offset  
rs, offset  
rs, offset  
BGEZ  
BLTZ  
BLEZ  
rs, offset  
rs, offset  
rs, offset  
BGEZ  
BLTZ  
BLEZ  
rs, offset  
rs, offset  
rs, offset  
Branch  
Branch On Less Than Zero BLTZ  
Branch On Less Than Zero  
BLEZ  
or Equal to Zero  
Branch On Less Than Zero  
And Link  
BLTZAL rs, offset  
BGEZAL rs, offset  
BLTZAL rs, offset  
BGEZAL rs, offset  
BLTZAL rs, offset  
BGEZAL rs, offset  
Branch On Greater Than  
Zero And Link  
D-4  
Appendix D Compatibility Among TX19, TX19A and TX39 Architectures  
Category  
Instruction  
TX19A 32-Bit ISA  
TX19 32-Bit ISA  
TX39  
Branch And Link  
Branch On Equal Likely  
BAL  
BEQL  
offset  
⎯
⎯
rs, rt, offset  
rs, rt, offset  
BEQL  
rs, rt, offset  
rs, rt, offset  
BEQL  
BNEL  
rs, rt, offset  
rs, rt, offset  
Branch On Not Equal Likely BNEL  
BNEL  
Branch On Greater Than  
BGTZL  
rs, offset  
rs, offset  
rs, offset  
rs, offset  
BGTZL  
rs, offset  
rs, offset  
rs, offset  
rs, offset  
BGTZL  
BGEZL  
BLTZL  
BLEZL  
rs, offset  
rs, offset  
rs, offset  
rs, offset  
Zero Likely  
Branch On Greater Than  
BGEZL  
BGEZL  
BLTZL  
BLEZL  
Zero or Equal to Zero Likely  
Branch-Likel  
y
Branch On Less Than Zero  
BLTZL  
Likely  
Branch On Less Than Zero  
BLEZL  
or Equal to Zero Likely  
Branch On Less Than Zero  
And Link Likely  
BLTZALL rs, offset  
BGEZALL rs, offset  
BLTZALL rs, offset  
BGEZALL rs, offset  
BLTZALL rs, offset  
BGEZALL rs, offset  
Branch On Greater Than  
Zero And Link Likely  
Trap If Equal  
TEQ  
rs, rt  
⎯
⎯
⎯
⎯
Trap If Equal Immediate  
TEQI  
rs, Immediate  
Trap If Greater Than or  
Equal  
TGE  
rs, rt  
⎯
⎯
⎯
⎯
⎯
⎯
Trap If Greater Than or  
Equal Immediate  
TGEI  
TGEU  
rs, Immediate  
rs, rt  
Trap If Greater Than or  
Equal Unsigned  
Trap If Greater Than or  
Equal Immediate Unsigned  
TGEIU  
TLT  
rs, Immediate  
rs, rt  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Trap  
Trap If Less Than  
Trap If Less Than  
Immediate  
TLTI  
rs, Immediate  
rs, rt  
Trap If Less Than Unsigned TLTU  
Trap If Less Than  
TLTIU  
rs, Immediate  
Immediate Unsigned  
Trap If Not Equal  
TNE  
rs, rt  
⎯
⎯
⎯
⎯
Trap If Not Equal Immediate TNEI  
Move To Coprocessor  
rs, Immediate  
⎯
⎯
MTCz  
MFCz  
rt, rd  
rt, rd  
MTCz  
MFCz  
rt, rd  
rt, rd  
Move From Coprocessor  
Move Control To  
Coprocessor  
⎯
CTCz  
rt, rd  
CTCz  
rt, rd  
Move Control From  
Coprocessor  
⎯
⎯
⎯
CFCz  
COPz  
BCzT  
rt, rd  
CFCz  
COPz  
BCzT  
rt, rd  
Coprocessor Operation  
cofun  
offset  
cofun  
offset  
Coprocessor  
Branch On Coprocessor z  
True  
Branch On Coprocessor z  
True Likely  
⎯
⎯
⎯
BCzTL  
BCzF  
offset  
offset  
offset  
BCzTL  
BCzF  
offset  
offset  
offset  
Branch On Coprocessor z  
False  
Branch On Coprocessor z  
False Likely  
BCzFL  
BCzFL  
D-5  
Appendix D Compatibility Among TX19, TX19A and TX39 Architectures  
Category  
Instruction  
TX19A 32-Bit ISA  
TX19 32-Bit ISA  
TX39  
Move To CP0  
MTC0  
rt, rd  
rt, rd  
⎯
MTC0  
rt, rd  
rt, rd  
MTC0  
MFC0  
RFE  
rt, rd  
rt, rd  
Move From CP0  
Restore From Exception  
Exception Return  
Debug Exception Return  
Cache  
MFC0  
MFC0  
RFE  
ERET  
⎯
⎯
DERET  
DERET  
DERET  
⎯
⎯
CACHE op, offset(base) CACHE op, offset(base)  
System  
Control  
Coprocessor  
Read Indexed TLB Entry  
(*1)  
(TLBR)  
(TLBR)  
Write Indexed TLB Entry  
(*1)  
⎯
⎯
⎯
(TLBWI)  
(TLBWR)  
(TLBP)  
(TLBWI)  
(TLBWR)  
(TLBP)  
Write Random TLB Entry  
(*1)  
Probe TLB for Matching  
Entry (*1)  
System Call  
Breakpoint  
SYSCALL code  
BREAK code  
SYSCALL code  
BREAK code  
SYSCALL code  
BREAK code  
Special  
Software Debug Breakpoint  
Exception  
SDBBP code  
WAIT  
SDBBP code  
SDBBP code  
Enter Standby Mode  
⎯
⎯
(*1) Treated as a NOP.  
D-6  
Appendix D Compatibility Among TX19, TX19A and TX39 Architectures  
Table D-3 gives comparisons of the 16-bit ISA of the TX19A and the TX19, and the MIPS16 ASE.  
Table D-3 Instruction Sets of the TX19A 16-bit ISA, the TX19 16-bit ISA and the MIPS16 ASE  
Category  
Instruction  
TX19A16-Bit ISA  
TX19 16-Bit ISA  
MIPS16 ASE  
Load Byte  
LB  
ry, offset(base)  
ry, offset(base)  
ry, offset(sp)  
ry, offset(fp)  
ry, offset(base)  
ry, offset(base)  
ry, offset(sp)  
ry, offset(fp)  
ry, offset(base)  
ry, offset(pc)  
ry, offset(sp)  
ry, offset(fp)  
⎯
LB  
ry, offset(base)  
LB  
ry, offset(base)  
LBU  
LBU  
LBU  
LH  
LBU  
ry, offset(base)  
LBU  
ry, offset(base)  
⎯
Load Byte Unsigned  
Load Halfword  
⎯
⎯
⎯
LH  
ry, offset(base)  
LH  
ry, offset(base)  
ry, offset(base)  
⎯
LHU  
LHU  
LHU  
LW  
LHU  
ry, offset(base)  
LHU  
Load Halfword Unsigned  
⎯
⎯
⎯
LW  
LW  
LW  
ry, offset(base)  
LW  
LW  
LW  
ry, offset(base)  
ry, offset(pc)  
ry, offset(sp)  
⎯
LW  
ry, offset(pc)  
Load Word  
LW  
ry, offset(sp)  
LW  
⎯
Load Word Unsigned  
Load Doubleword  
⎯
LWU  
LD  
ry, offset(sp)  
ry, offset(base)  
ry, offset(pc)  
ry, offset(sp)  
ry, offset(base)  
⎯
⎯
⎯
⎯
⎯
LD  
Load/Store  
⎯
⎯
LD  
SB  
SB  
SB  
SH  
SH  
SH  
SW  
SW  
SW  
SW  
ry, offset(base)  
ry, offset(sp)  
ry, offset(fp)  
ry, offset(base)  
ry, offset(sp)  
ry, offset(fp)  
ry, offset(base)  
ry, offset(sp)  
ra, offset(sp)  
ry, offset(fp)  
⎯
SB  
SH  
ry, offset(base)  
SB  
Store Byte  
⎯
⎯
⎯
ry, offset(base)  
SH  
ry, offset(base)  
⎯
Store Halfword  
⎯
⎯
⎯
SW  
SW  
SW  
ry, offset(base)  
SW  
SW  
SW  
ry, offset(base)  
ry, offset(sp)  
ra, offset(sp)  
⎯
ry, offset(sp)  
Store Word  
ra, offset(sp)  
⎯
⎯
⎯
⎯
⎯
SD  
SD  
SD  
ry, offset(base)  
ry, offset(pc)  
ry, offset(sp)  
⎯
Store Doubleword  
Synchronize  
⎯
⎯
SYNC  
D-7  
Appendix D Compatibility Among TX19, TX19A and TX39 Architectures  
Category  
Instruction  
TX19A 16-Bit ISA  
TX19 16-Bit ISA  
MIPS16 ASE  
ADDIU  
ry, rx, immediate ADDIU  
ry, rx, immediate ADDIU  
ry, rx, immediate  
ADDIU  
ADDIU  
rx, immediate  
sp, immediate  
ADDIU  
ADDIU  
rx, immediate  
sp, immediate  
ADDIU  
ADDIU  
rx, immediate  
sp, immediate  
Add Immediate  
ADDIU rx, pc, immediate ADDIU rx, pc, immediate ADDIU rx, pc, immediate  
ADDIU rx, sp, immediate ADDIU rx, sp, immediate ADDIU rx, sp, immediate  
ADDIU  
fp, immediate  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DADDIU ry, rx, immediate  
DADDIU ry, immediate  
DADDIU sp, immediate  
DADDIU ry, pc, immediate  
DADDIU ry, sp, immediate  
Doubleword Add Immediate  
ALU  
Immediate  
Set On Less Than  
Immediate  
SLTI  
rx, immediate  
rx, immediate  
SLTI  
rx, immediate  
rx, immediate  
SLTI  
rx, immediate  
rx, immediate  
Set On Less Than  
Immediate Unsigned  
SLTIU  
SLTIU  
SLTIU  
Compare Immediate  
Load Immediate  
CMPI  
LI  
rx, immediate  
rx, immediate  
rx, immediate  
rx, immediate  
CMPI  
LI  
rx, immediate  
CMPI  
LI  
rx, immediate  
rx, immediate  
rx, immediate  
Logical AND Immediate  
Logical OR Immediate  
ANDI  
ORI  
⎯
⎯
⎯
⎯
Logical Exclusive-OR  
Immediate  
XORI  
rx, immediate  
⎯
⎯
Load Upper Immediate  
Add Unsigned  
LUI  
rx, immediate  
rz, rx, ry  
⎯
⎯
⎯
ADDU  
ADDU  
SUBU  
rz, rx, ry  
⎯
ADDU  
rz, rx, ry  
Doubleword Add Unsigned  
Subtract Unsigned  
DADDU rz, rx, ry  
SUBU rz, rx, ry  
SUBU  
rz, rx, ry  
rz, rx, ry  
Doubleword Subtract  
Unsigned  
⎯
⎯
DSUBU rz, rx, ry  
Set On Less Than  
SLT  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
ry, r32  
r32, rz  
fp, r32  
ry, rx  
ry, rx, bit2, bit1  
rz, rx, ry  
rz, rx, ry  
rx  
SLT  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
ry, r32  
r32, rz  
⎯
SLT  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
rx, ry  
ry, r32  
r32, rz  
⎯
Set On Less Than Unsigned SLTU  
SLTU  
CMP  
NEG  
AND  
OR  
SLTU  
CMP  
NEG  
AND  
OR  
Compare  
Negate  
AND  
CMP  
NEG  
AND  
OR  
OR  
2/3-Operand  
Register  
Exclusive-OR  
Not  
XOR  
NOT  
MOVE  
MOVE  
MOVE  
BS1F  
BFINS  
MAX  
MIN  
XOR  
NOT  
MOVE  
MOVE  
XOR  
NOT  
MOVE  
MOVE  
Type  
Move  
Bit Search One Forward  
Bit Field Insert  
⎯
⎯
⎯
⎯
Maximum Signed  
Minimum Signed  
⎯
⎯
⎯
⎯
Sign-Extend Byte  
Sign-Extend Halfword  
Zero-Extend Byte  
Zero-Extend Halfword  
SEB  
⎯
⎯
SEH  
rx  
⎯
⎯
ZEB  
rx  
⎯
⎯
ZEH  
rx  
⎯
⎯
D-8  
Appendix D Compatibility Among TX19, TX19A and TX39 Architectures  
Category  
Instruction  
TX19A 16-Bit ISA  
TX19 16-Bit ISA  
MIPS16 ASE  
SLL  
rx, ry, sa  
ry, sa5  
ry, rx  
SLL  
rx, ry, sa  
⎯
SLL  
rx, ry, sa  
⎯
Shift Left Logical  
SLL  
Shift Left Logical Variable  
Shift Right Logical  
SLLV  
SRL  
SRL  
SLLV  
SRL  
ry, rx  
rx, ry, sa  
⎯
SLLV  
SRL  
ry, rx  
rx, ry, sa  
⎯
rx, ry, sa  
ry, sa5  
ry, rx  
Shift Right Logical Variable SRLV  
SRLV  
SRA  
ry, rx  
rx, ry, sa  
⎯
SRLV  
SRA  
ry, rx  
rx, ry, sa  
⎯
SRA  
Shift Right Arithmetic  
SRA  
rx, ry, sa  
ry, sa5  
Shift Right Arithmetic  
SRAV  
ry, rx  
⎯
SRAV  
ry, rx  
⎯
SRAV  
DSLL  
ry, rx  
rx, ry, sa  
ry, rx  
rx, ry, sa  
ry, rx  
rx, ry, sa  
ry, rx  
⎯
Variable  
Shift  
Doubleword Shift Left  
Logical  
Doubleword Shift Left  
Logical Variable  
⎯
⎯
DSLLV  
DSRL  
Doubleword Shift Right  
Logical  
⎯
⎯
Doubleword Shift Right  
Logical Variable  
⎯
⎯
DSRLV  
DSRA  
DSRAV  
Doubleword Shift Right  
Arithmetic  
⎯
⎯
Doubleword Shift Right  
Arithmetic Variable  
⎯
⎯
SAVE  
reg_list3,  
⎯
framesize4  
SAVE  
SAVE  
reg_list3,  
⎯
⎯
SAVE/  
xsregs, aregs, framesize8  
RESTORE  
RESTORE reg_list3,  
framesize4  
⎯
⎯
RESTORE  
Mutiply  
RESTORE reg_list3,  
xsregs, aregs, framesize8  
⎯
⎯
MULT  
rx, ry  
MULT  
rx, ry  
⎯
MULT  
rx, ry  
⎯
MULT  
ry, rx, ry  
rx, ry  
MULTU  
MULTU  
MULTU  
rx, ry  
⎯
MULTU  
DMULT  
rx, ry  
⎯
Multiply Unsigned  
ry, rx, ry  
⎯
Doubleword Mutiply  
⎯
rx, ry  
Doubleword Multiply  
Unsigned  
⎯
⎯
DMULTU rx, ry  
Mutiply And Add  
Mutiply And Add Unsigned  
Saturated Add  
MADD  
rx, ry  
⎯
⎯
⎯
⎯
⎯
⎯
MADDU rx, ry  
SADD  
SSUB  
DIV  
ry, rx, ry  
⎯
Multiply,  
Divide and  
Multiply-and-  
Saturated Subtract  
Divide  
ry, rx, ry  
rx, ry  
rx, ry  
⎯
⎯
DIV  
rx, ry  
rx, ry  
⎯
DIV  
rx, ry  
rx, ry  
rx, ry  
Add  
Divide Unsigned  
Doubleword Divide  
DIVU  
DIVU  
DIVU  
DDIV  
Doubleword Divide  
Unsigned  
⎯
⎯
DDIVU  
rx, ry  
Divide Exception  
Divide Exception Unsigned  
Move From HI  
DIVE  
rx, ry  
rx, ry  
rx  
⎯
⎯
rx  
⎯
⎯
rx  
DIVEU  
MFHI  
MFLO  
MTHI  
MTLO  
MFHI  
MFHI  
Move From LO  
Move To HI  
rx  
MFLO  
rx  
MFLO  
rx  
rx  
⎯
⎯
⎯
⎯
Move To LO  
rx  
D-9  
Appendix D Compatibility Among TX19, TX19A and TX39 Architectures  
Category  
Instruction  
TX19A 16-Bit ISA  
TX19 16-Bit ISA  
MIPS16 ASE  
BTST offset(base3), pos3  
BTST offset(r0), pos3  
BTST offset(fp), pos3  
BEXT offset(base3), pos3  
BEXT offset(r0), pos3  
BEXT offset(fp), pos3  
BCLR offset(base3), pos3  
BCLR offset(r0), pos3  
BCLR offset(fp), pos3  
BSET offset(base3), pos3  
BSET offset(r0), pos3  
BSET offset(fp), pos3  
BINS offset(base3), pos3  
BINS offset(r0), pos3  
BINS offset(fp), pos3  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Bit Test  
Bit Extract  
Bit Clear  
Bit Set  
Bit  
Manipulation  
Bit Insert  
ADDMIU offset(base3),  
imm3  
⎯
⎯
Add Immediate to Memory  
Word  
ADDMIU offset(r0), imm3  
MTC0 rx, cp0rd32  
⎯
⎯
⎯
⎯
⎯
⎯
Move To Coprocessor 0  
Move From Coprocessor 0  
MFC0 ry, cp0rs32  
Coprocessor  
Add Coprocessor 0  
Immediate Unsigned  
AC0IU cp0rt32, imm3  
⎯
⎯
Jump And Link  
JAL  
JALX  
JR  
target  
target  
rx  
JAL  
target  
target  
rx  
JAL  
JALX  
JR  
target  
target  
rx  
Jump And Link exchange  
JALX  
JR  
Jump Register  
JR  
ra  
JR  
ra  
JR  
ra  
Jump  
JRC  
JRC  
JALR  
rx  
⎯
⎯
Jump Register Compact  
Jump And Link Register  
ra  
⎯
⎯
ra, rx  
JALR  
ra, rx  
JALR  
ra, rx  
Jump And Link Register  
Compact  
JALRC  
BEQZ  
BNEZ  
ra, rx  
⎯
⎯
Branch On Equal To Zero  
rx, offset  
rx, offset  
BEQZ  
BNEZ  
rx, offset  
rx, offset  
BEQZ  
BNEZ  
rx, offset  
rx, offset  
Branch On Not Equal To  
Zero  
Branch On T8 Equal To  
Zero  
BTEQZ  
BTNEZ  
offset  
offset  
BTEQZ  
offset  
offset  
BTEQZ  
offset  
offset  
Branch  
Branch On T8 Not Equal To  
Zero  
BTNEZ  
B
BTNEZ  
B
Branch Unconditional  
Branch And Link  
Breakpoint  
B
offset  
offset  
code  
offset  
⎯
offset  
⎯
BAL  
BREAK  
BREAK  
SDBBP  
code  
BREAK  
SDBBP  
code  
Software Debug Breakpoint  
Exception  
SDBBP  
code  
code  
code  
Extend  
EXTEND immediate  
EXTEND immediate  
EXTEND immediate  
Disable Interrupt  
Enable Interrupt  
System Call  
DI  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Special  
EI  
SYSCALL code  
ERET  
Exception Return  
Debug Exception Return  
Enter Standby Mode  
DERET  
WAIT  
D-10  
Appendix E 32-Bit ISA Instruction Bit Encodings  
Appendix E 32-Bit ISA Instruction Bit Encodings  
This appendix shows the encoding used for the 32-bit ISA.  
Table E-1 Symbols Used in the Instruction Encoding Tables  
Symbol  
Meaning  
Opcodes marked with this symbol are reserved for future use. Executing  
such an instruction causes a Reserved Instruction Exception.  
*
Executing instructions marked with this symbol causes a Reserved  
Instruction Exception.  
Executing instructions with an opcode marked with this symbol causes a  
Coprocessor Unusable Exception or a Reserved  
Instruction Exception.  
β
θ
Opcodes marked with this symbol represent an EJTAG support instruction.  
If EJTAG is not implemented, executing such an instruction causes a  
Reserved Instruction Exception.  
σ
E-1  
Appendix E 32-Bit ISA Instruction Bit Encodings  
Table 0-1 MIPS32 Encoding of the Opcode Field  
opcode  
bits 28..26  
0
1
2
010  
3
011  
4
100  
5
101  
6
110  
7
bits 31..29  
000  
001  
111  
0
1
2
3
4
5
6
7
000  
001  
010  
011  
100  
101  
110  
111  
SPECIAL  
ADDI  
COP0  
β
REGIMM  
ADDIU  
(COP1) θ  
β
J
JAL  
BEQ  
ANDI  
BEQL  
SPECIAL2  
LBU  
β
BNE  
BLEZ  
XORI  
BLEZL  
β
BGTZ  
SLTI  
SLTIU  
(COP3) θ  
β
ORI  
LUI  
(COP2) θ  
β
LWL  
BNEL  
JALX  
LHU  
BGTZL  
*
LB  
LH  
LW  
LWR  
β
SB  
SH  
SWL  
SW  
β
SWR  
(LDC2) β  
(SDC2) β  
(CACHE)  
(LL)  
(LWC1) β  
(SWC1) β  
(LWC2) β  
(SWC2) β  
(PREF)  
*
β
β
(LDC1) β  
(SDC1) β  
β
β
(SC)  
Table 0-2 MIPS32 SPECIAL Opcode Encoding of Function Field  
function  
bits 5..3  
bits 2..0  
0
000  
SLL  
JR  
1
001  
2
010  
3
4
5
6
110  
SRLV  
*
7
011  
100  
101  
111  
0
000  
001  
010  
011  
100  
101  
110  
111  
β
SRL  
MOVZ  
MFLO  
DIV  
SRA  
MOVN  
MTLO  
DIVU  
SUBU  
SLTU  
TLTU  
β
SLLV  
*
SRAV  
1
2
3
4
5
6
7
JALR  
MTHI  
MULTU  
ADDU  
*
SYSCALL  
BREAK  
SYNC  
MFHI  
MULT  
ADD  
*
β
β
AND  
β
TEQ  
β
*
β
OR  
β
β
β
XOR  
β
TNE  
β
β
β
SUB  
SLT  
TLT  
NOR  
β
*
β
TGE  
β
TGEU  
*
*
β
*
Table 0-3 MIPS32 REGIMM Encoding of rt Field  
rt  
bits 20..19  
bits 18..16  
0
1
001  
2
010  
3
011  
4
100  
*
5
101  
*
6
110  
*
7
111  
*
000  
0
1
2
3
00  
01  
10  
11  
BLTZ  
TGEI  
BLTZAL  
*
BGEZ  
TGEIU  
BGEZAL  
*
BLTZL  
TLTI  
BGEZL  
TLTIU  
BGEZALL  
*
TEQI  
*
*
TNEI  
*
*
BLTZALL  
*
*
*
*
*
*
*
Table 0-4 MIPS32 SPECIAL2 Encoding of Function Field  
function  
bits 5..3  
bits 2..0  
0
1
2
3
011  
θ
θ
θ
θ
θ
θ
θ
4
5
6
110  
θ
θ
θ
θ
θ
θ
θ
7
000  
001  
010  
100  
101  
111  
0
000  
001  
010  
011  
100  
101  
110  
111  
MADD  
MADDU  
MUL  
MSUB  
MSUBU  
θ
θ
θ
θ
θ
θ
θ
1
2
3
4
5
6
7
θ
θ
θ
CLZ  
θ
θ
θ
θ
θ
CLO  
θ
θ
θ
θ
θ
θ
θ
θ
θ
θ
θ
θ
β
θ
θ
θ
θ
θ
θ
β
θ
θ
θ
θ
θ
θ
θ
SDBBPσ  
E-2  
Appendix E 32-Bit ISA Instruction Bit Encodings  
Table 0-5 MIPS32 COP0 Encoding of rs Field  
rs  
bits 23..21  
0
000  
MFC0  
*
1
001  
β
2
010  
*
3
011  
*
4
100  
MTC0  
*
5
101  
β
6
110  
*
7
111  
*
bits 25..24  
0
1
2
3
00  
01  
10  
11  
*
*
*
*
*
*
CO  
Table 0-6 MIPS32 COP0 Encoding of Function Field When rs = CO  
function  
bits 5..3  
bits 2..0  
0
1
2
3
011  
*
4
100  
*
5
101  
*
6
7
000  
001  
010  
110  
111  
0
000  
001  
010  
011  
100  
101  
110  
111  
*
(TLBR)  
(TLBWI)  
(TLBWR)  
*
1
2
3
4
5
6
7
(TLBP)  
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
ERET  
*
*
*
DERETσ  
WAIT  
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
E-3  
Appendix E 32-Bit ISA Instruction Bit Encodings  
E-4  
Appendix F 16-Bit ISA Instruction Bit Encodings  
Appendix F 16-Bit ISA Instruction Bit Encodings  
This appendix shows the encoding used for the 16-bit ISA. Opcodes marked with * cause an  
Reserved Instruction exception.  
Table F-1 Major Opcode Map  
Instruction Bits [13:11]  
[15:14]  
00  
000  
addiusp  
RRI-A  
lb  
001  
addiupc  
addiu8  
lh  
010  
b
011  
JAL(X)  
sltiu  
lw  
100  
beqz  
I8  
101  
bnez  
li  
110  
SHIFT  
cmpi  
111  
FP-B  
slti  
SP-B  
01  
lwsp  
swsp  
lbu  
lhu  
lwpc  
FP-SP-H  
SPECIAL  
10  
sb  
sh  
sw  
RRR  
RR  
extend  
11  
Table F-2 JAL(X) Minor Opcode Map  
Instruction Bit [26]  
0
1
jal  
jalx  
Table F-3 FP-B and extend + FP-B Minor Opcode Map  
Instruction Bit [7]  
0
1
lbfp  
sbfp  
Table F-4 SP-B and extend + SP-B Minor Opcode Map  
Instruction Bit [7]  
0
1
lbsp  
sbsp  
Table F-5 FP-SP-H and extend + FP-SP-H Minor Opcode Map  
Instruction Bit [0]  
[7]  
0
0
1
lhsp  
shsp  
lhfp  
shfp  
1
F-1  
Appendix F 16-Bit ISA Instruction Bit Encodings  
Table F-6 SPECIAL and extend + SPECIAL Minor Opcode Map  
Instruction Bits [10:8]  
000  
001  
010  
011  
100  
101  
110  
111  
btst  
bclr  
bset  
bins  
bal  
bext  
lwfp  
swfp  
Table F-7 extend + addiu8 Minor Opcode Map  
Instruction Bits [7:5]  
000  
001  
010  
011  
100  
101  
110  
111  
addiu8  
*
addmiu  
*
andi  
ori  
xori  
lui  
Table F-8 RRI-A Minor Opcode Map  
Instruction Bit [4]  
0
1
addiu  
*
Table F-9 I8 and extend + I8 Minor Opcode Map  
Instruction Bits [10:8]  
000  
001  
010  
011  
100  
101  
110  
111  
bteqz  
btnez  
swrasp  
adjsp  
SVRS  
mov32r  
adjfp  
movr32  
Table F-10 I8 + SVRS and extend + I8 + SVRS Minor Opcode Map  
Instruction Bits [7]  
0
1
restore  
save  
Table F-11 RRR Minor Opcode Map  
Instruction Bits [1:0]  
[7]  
0
00  
01  
10  
11  
ac0iu  
sll/INT  
sra/mthi  
srl/mtlo  
addu  
subu  
1
Note: mthi, mtlo and INT must have instruction bits [6:2] cleared.  
F-2  
Appendix F 16-Bit ISA Instruction Bit Encodings  
Table F-12 RRR + INT Minor Opcode Map  
Instruction Bits [10:8]  
000  
001  
010  
011  
100  
101  
110  
111  
di  
ei  
*
*
*
*
*
*
Table F-13 SHIFT Minor Opcode Map  
Instruction Bits [1:0]  
[2]  
0
00  
01  
10  
11  
mfc0  
sll  
srl  
sra  
mtc0  
1
Table F-14 RR Minor Opcode Map  
Instruction Bits [2:0]  
[4:3]  
00  
000  
001  
sdbbp  
*
010  
slt  
011  
sltu  
neg  
*
100  
sllv  
101  
break  
or  
110  
srlv  
111  
srav  
J(AL)R(C)  
movfp  
mfhi  
cmp  
mflo  
div  
and  
xor  
not  
01  
CNVT  
multu  
sadd  
mult  
ssub  
multu  
madd  
dive  
maddu  
diveu  
10  
mult  
divu  
11  
Table F-15 RR + J(AL)R(C) Minor Opcode Map  
Instruction Bits [7:5]  
000  
001  
010  
011  
100  
101  
110  
111  
jr rs  
jr ra  
jalr ra,rs  
*
jrc rs  
jrc ra  
jalrc ra,rs  
*
Table F-16 RR + CNVT Minor Opcode Map  
Instruction Bits [7:5]  
000  
001  
010  
011  
100  
101  
110  
111  
zeh  
*
*
seb  
seh  
*
*
zeb  
Table F-17 extend + RR Minor Opcode Map  
Instruction Bits [2:0]  
[4:3]  
00  
000  
wait  
(tlbp)  
*
001  
010  
011  
100  
101  
110  
111  
(tlbr)  
(tlbwi)  
*
*
*
*
*
MAX/MIN  
(tlbwr)  
BS1F/BFINS  
sync  
*
*
*
*
*
*
syscall  
*
*
*
*
*
*
01  
*
*
(cache)  
deret  
10  
eret  
11  
F-3  
Appendix F 16-Bit ISA Instruction Bit Encodings  
Table F-18 extend + RR + MAX/MIX Minor Opcode Map  
Instruction Bit [26]  
0
1
max  
min  
Table F-19 extend + RR + BS1F/BFINS Minor Opcode Map  
Instruction Bit [26]  
0
1
bfins  
bs1f  
F-4  

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