TLD4012 [TRIPATH]
ADSL LINE DRIVER USING TRIPATH DIGITAL POWER PROCESSING (DPP⑩) TECHNOLOGY; ADSL线路驱动器使用TRIPATH数字功率处理（ DPP⑩ ）技术
| 型号： | TLD4012 |
| 厂家： | 
TRIPATH TECHNOLOGY INC. |
| 描述： | ADSL LINE DRIVER USING TRIPATH DIGITAL POWER PROCESSING (DPP⑩) TECHNOLOGY |
| 文件： | 总13页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Tripath Technology, Inc. - Technical Information
TLD4012
ADSL LINE DRIVER USING TRIPATH DIGITAL POWER
PROCESSING (DPP™) TECHNOLOGY
T e c h n i c a l I n f o r m a t i o n
R e vi s i o n 2 . 0 a – M a y 2 0 0 2
G E N E R A L D E S C R I P T I O N
T he T LD4012 is an ADSL line driver that provides very low power consumption and
low distortion in a very small package as a result of T ripath’s proprietary power
processing technology. T his device accepts differential input signals from an analog
front-end (AF E), and can be used in full-rate ( G. dmt), or G. lite systems. T his T LD4012
offers a low power consumption of 650mW for full-rate, full-power, CO-side, F DM
(non-overlapped) transmissions.
A P P L I C A T I O N S
F E A T U R E S
ꢀ
ꢀ
ꢀ
ꢀ
Full-rate or G.lite line cards
DSLAMs
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Tripath Proprietary Power Processing technology
Very low power consumption
DLC equipment
P
CONS(Full-rate ADSL) = 650 mW (typ)
CONS (G.lite) = 390 mW (typ)
Central office switches
P
Low distortion
ꢀ
Spurious free dynamic range = -80 dBc 26kHz to 138kHz,
B E N E F I T S
R
LINE=100Ω, PLINE=19.8dBm
ꢀ
ꢀ
ꢀ
ꢀ
Reduced line card power
ꢀ
Third harmonic distortion = -83 dBc at f = 100 kHz,
-82 dBc at f = 500 kHz, -63 dBc at f = 1 MHz, VOUT = 10Vpp
(differential), 70Ω load
Reduced system power
Increased line card density
More ports per cubic foot of system
space
ꢀ
ꢀ
ꢀ
500 mA minimum output current into a 71Ω load
Digitally programmable gain (from 12.8 to 27.8 dB in 1 dB steps)
Low-power mode -130 mW typical (line terminated -allows
reception of incoming signals)
ꢀ
ꢀ
Improved system performance
Simplifies thermal management on
PCB
ꢀ
ꢀ
ꢀ
Disabled mode - 10 mW typical (no line termination)
Over-temperature and over-current protection with Fault output
5x5 mm 32-pin TQFP with exposed die pad
ꢀ
ꢀ
Improved reliability
Flexible solution
VDD5
25
VSS5
16
VDD15 VSS15
21 20
30 FBP
3
4
INP
INN
32 31 30 29 28 27 26 25
23 OUTP
18 OUTN
Power
EN_AC
GND
INP
INN
GND
G0
1
2
3
4
5
6
7
8
24
NC
OUTP
NC
VDD15
VSS15
NC
Processing
Block
23
22
21
20
19
18
17
29 FBN
G1
G2
OUTN
NC
9
8
7
6
G3
G2
G1
Output
REXT
27
9
10 11 12 13 14 15 16
current
limit
Control
&
11 FAULT
G0
Logic
14
15
1
RESETB
LOPWR
EN_AC
AUTO_CLR
31
12
FORC_BIAS
13
2
GND
5
28
GND
GND
TH_FAULT
Bloc k Dia g ra m
1
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
O V E R V I E W
TLD4012 is a low-power, low-distortion ADSL line driver. This driver offers power consumption ranging
from 600mW to 650mW, and provides active, or synthetic, output impedance matching to reduce power
consumption. This driver supports an impedance synthesis factor of 2.55 (refer to Figure 1 in the
“Test/Applications Circuits” section of this document). The table below summarizes the total power
consumption of this device for FDM and overlapped transmissions. Power consumption is reduced by
using +/-14V supplies for VDD15/VSS15.
Power consumption FDM
(non-overlapped)
(19.8dBm)
Power consumption
overlapped
(20.4dBm)
High supplies
VDD15/VSS15
+/- 14.0 V
+/- 15.0 V
650 mW
710 mW
675 mW
740 mW
Power consumption values given above, and in the following specifications, are for total power consumed
from the supplies. This includes power dissipated in the device and power delivered to the load, where the
load includes both the line and the matching resistors. Power dissipation in the driver can be determined
by subtracting power delivered to the load (line and matching resistors) from the power consumption given
in the specifications. The power consumption provided above does not account for loading due to the
hybrid which will vary with application.
With +/-14V supplies, the maximum output swing, VOUTMAX, is at least 40VPPDIFF over process, temperature
and a 5% supply tolerance. This is sufficient for full-power FDM signals with a PAR of 6.45. Note that
when using +/-14V supplies with a 5% tolerance the worst-case spurious free dynamic range in the
receiving band, and intermodulation distortion may be degraded slightly from the values given in the
specifications below. When using 14V nominal supplies the maximum degradation expected when the +/-
14V supplies are 5% low (minimum +/-13.3V) versus +/-15V supplies 5% low (minimum +/-14.25V) is less
than 4dB worse case.
All other minimum and maximum specifications in the tables that follow are valid from +/-13.3 to +/-15.75V
on VSS15/VDD15. This allows the use of +/-14V supplies with a 5% tolerance for VSS15/VDD15.
Lower PAR (peak-to-average ratio) values allow the high voltage supplies (VSS15 and VDD15) to be
reduced further, thus reducing power consumption. For example, for a 5.3 PAR VSS15/VDD15 can be
reduced to +/-12V. This will reduce power consumption to about 600mW for full-rate, 19.8dBm ADSL
FDM (non-overlapped) transmissions. Contact Tripath regarding use of the TLD4012 below +/-13.3V.
The recommended values for the line-matching resistors, RS, and the recommended transformer turns
ratios to properly match the line are (see Figure 1 in “Test/Application” section below):
RS = 10Ω
N = 1:1.4
The 2.55 synthesis factor of the TLD4012 and the values above for RS and N will result in a match to the
100Ω line impedance. The synthesis factor, k, is defined as the factor by which the line driver multiplies the
line-matching resistor, RS.
If your application can take advantage of higher synthesis factors, contact Tripath regarding options that
can reduce power consumption still further.
2
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
A B S O L U T E M A X I M U M R A T I N G S
SYMBOL
VDD5
VSS5
VDD15
VSS15
TJ
TA
TSTORE
TSOLDER
PARAMETER
Value
+ 6
- 6
+ 18
- 18
150
-40 to +85
-55 to 150
UNITS
V
V
V
V
ºC
ºC
ºC
ºC
Positive 5V Supply Voltage
Negative 5V Supply Voltage
Positive 15V Supply Voltage
Negative 15V Supply Voltage
Maximum Junction Temperature
Operating Free-air Temperature Range
Storage Temperature Range
Manual soldering for three seconds
Reflow soldering for five seconds
Output current limit, OUTP or OUTN
350
245
1.1
IOUT
VIN
VCMR
A
V
V
Input voltage, INP or INN
VSS5 to VDD5
VSS5 to VDD5
Common mode input voltage range
Notes:
1. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
2. The absolute value of VDD5 and VSS5 must always be less than or equal to the absolute value of VDD15 and
VSS15.
3. The TLD4012 incorporates an exposed die pad on the underside of its package. This acts as a heat sink
and must be connected to a copper plane on the printed circuit board for proper heat dissipation.
Failure to do so may result in exceeding the maximum junction temperature which could permanently
damage the device. This copper plane must be connected to VSS15. See the Application Information
section of this document for additional information.
4. Application must insure that VSS15 is applied before VSS5. A clamp diode connected between VSS5 and
VSS15 can be used to insure proper application of supply voltages to the TLD4012 (see Test/Application
Circuits of this document). Note that only one diode is needed per board for multi-channel line cards, but diode
selection should account for the increased current transient that the diode must carry for multiple channels. If
the +/-5V rail’s rise time is fast, for example in applications in which the driver’s supplies might be hot-plugged,
this method may not be sufficient and supply sequencing may be necessary.
R E C O M M E N D E D O P E R A T I N G C O N D I T I O N S
SYMBOL
VDD5
VSS5
VDD15
VSS15
VIH
PARAMETER
MIN.
+ 4.75
- 5.25
+ 13.3
- 15.75
2.7
TYP.
+ 5
- 5
+ 15 + 15.75
- 15
MAX. UNITS
Positive 5V Supply Voltage
Negative 5V Supply Voltage
Positive 15V Supply Voltage
Negative 15V Supply Voltage
High-level Input Voltage, all digital inputs
Low-level Input Voltage, all digital inputs
+ 5.25
V
V
V
V
V
V
- 4.75
- 13.3
+VDD5
0.8
VIL
0
IODLEAK
IODMAX
Open drain leakage current, FAULT output
Open drain sink current at VOL=0.4V max, FAULT output
1
µA
mA
1
Note: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical
Characteristics for guaranteed specific performance limits.
3
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
E L E C T R I C A L C H A R A C T E R I S T I C S
Unless otherwise specified, TA = 25°C, VDD5 = +5V, VSS5 = -5V, VDD15 = +15V, VSS15 = -15V. Also, see
Test/Application Circuits. See functional description for details regarding synthetic output impedance. Minimum and
maximum limits are guaranteed but may not be 100% tested.
SYMBOL
PARAMETER
Power Consumption
CONDITIONS
MIN.
TYP.
MAX.
UNITS
PCONS1
740
mW
RLOAD = 71Ω, POUT = 154 mW,
Full-rate, overlapped ADSL signal, line
power = 110 mW (20.4 dBm), with
synthetic output impedance (see Fig. 1)
PCONS3
PCONS4
PCONS5
Power Consumption, no signal
250
130
390
mW
mW
mW
RLOAD = 50Ω, No Input Signal,
LOPWR = Low (see Fig. 1)
Power Consumption, no signal, low power
mode
G.Lite
R
LOAD = 50Ω, No Input Signal,
LOPWR = High (see Fig. 1)
RLOAD = 71Ω, POUT = 58 mW,
G.Lite signal, line power = 41.6 mW
(16.2 dBm). See Fig. 1.
PCONS6
IDD5
Disable mode
RESETB = Low
10
mW
mA
Operating Current VDD5
47.0
R
LOAD = 71Ω, POUT = 154 mW,
Full-rate, overlapped ADSL signal with
synthetic output impedance (see Fig. 1)
ISS5
Operating Current VSS5
Operating Current VDD15
Operating Current VSS15
49.0
8.0
mA
mA
mA
RLOAD = 71Ω, POUT = 154 mW,
Full-rate, overlapped ADSL signal with
synthetic output impedance (see Fig. 1)
IDD15
R
LOAD = 71Ω, POUT = 154 mW,
Full-rate, overlapped ADSL signal with
synthetic output impedance (see Fig. 1)
ISS15
9.5
RLOAD = 71Ω, POUT = 154 mW,
Full-rate, overlapped ADSL signal with
synthetic output impedance (see Fig. 1)
Iq1
Quiescent Current (VDD5 and VSS5)
Quiescent Current (VDD15 and VSS15)
21.7
1.1
mA
mA
mA
mA
R
LOAD = 71Ω, No input signal, LOPWR =
Low
Iq2
RLOAD = 71Ω, No input signal,
LOPWR = Low
Iq1LP
Iq2LP
Quiescent Current (VDD5 and VSS5), low
power mode
11.0
0.68
1.28
RLOAD = 71Ω, No input signal,
LOPWR = High
Quiescent Current (VDD15 and VSS15),
RLOAD = 71Ω, No input signal,
low power mode
LOPWR = High
VBG
Band-gap Voltage
V
V
VOUTmax
Differential Output Voltage, peak-to-peak
differential
42
20
500
Gain = 17.8 to 27.8 dB, RLOAD = 71Ω
Gain = 12.8 to 16.8 dB, RLOAD = 71Ω
RLOAD = 71Ω
IOUTmax
ISC
Differential Output Current
Short-circuit Output Current
Differential Input Offset Voltage
Offset Voltage Drift
mA
mA
800
600
30
REXT = 24kΩ
VIO
µV
µV/°C
mV
∆VOS
VOSHI
Differential Output Offset Voltage
-100
100
Gain = 27.8dB, EN_AC = High, 5kΩ
across INN and INP
EN_AC = Low
Ib
Input Bias Current
0.5
0.2
800
2
µA
µA
kΩ
pF
Differential Input Bias Current
Differential Input Resistance
Differential Input Capacitance
∆Ib
RIDIFF
CIDIFF
ROUTLP
Output Resistance (while in Low-power
mode)
LOPWR = High
0.5
Ω
4
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
P E R F O R M A N C E C H A R A C T E R I S T I C S
Unless otherwise specified, TA = 25°C, VDD5 = +5V, VSS5 = -5V, VDD15 = +15V, VSS15 = -15V. Also,
see Test/Application Circuit. Minimum and maximum limits are guaranteed but may not be 100% tested.
SYMBOL
BWSS
SFDR
PARAMETER
CONDITIONS
MIN.
TYP.
10
-80
MAX.
UNITS
MHz
dB
Small-signal Bandwidth, -3 dB Gain = 20.8dB, VOUT = 1VPPDIFF
Spurious Free Dynamic Range
in the receive band with
respect to –40dBm ADSL
transmit signal
Gain = 20.8 dB, RLINE = 100Ω,
P
LINE = 20.4 dBm,
f = 26 kHz to 138 kHz
IMD
Intermodulation Distortion
Gain = 22.8dB
@ 50 kHz
-84
-84
-75
-90
-77
-70
-83
-82
-63
dBc
10VPPDIFF each tone
@ 100 kHz
SFDR >1MHz
f = 1.025MHz, ∆f = 50kHz
Gain = 17.8 to 27.8dB
RLOAD = 71Ω
HD2
HD3
HD5
SR
2nd Harmonic Distortion
3rd Harmonic Distortion
5th Harmonic Distortion
Slew Rate
f = 100 kHz
f = 500 kHz
f = 1 MHz
f = 100 kHz
f = 500 kHz
f = 1 MHz
f = 100 kHz
f = 500 kHz
f = 1 MHz
dBc
dBc
dBc
V/µs
VOUT = 10VPPDIFF
Gain = 17.8 to 27.8dB
RLOAD = 71Ω
VOUT = 10VPPDIFF
Gain = 17.8 to 27.8dB
RLOAD = 71Ω
-93
-67
-55
VOUT = 10VPPDIFF
VOUT from –10V to +10V, measured from
–7.5V to +7.5V, Gain = 20.8 dB
Gain = 20.8dB, f = 10 KHz
200
eN
iN
eNOTOT
Input Noise Voltage
Input Noise Current
Overall Output Noise Voltage Gain = 20.8dB, f = 30kHz to 1.1MHz,
8
2.9
188
nV/ √Hz
pA/ √Hz
nV/ √Hz
Gain = 20.8dB, f = 10 kHz
RIN = 5kΩ
CMRR
Common Mode Rejection
Ratio
Gain = 27.8 dB
VIN = 100 mVPP
EN_AC = High
@ 100 kHz
@ 500 kHz
@ 1 MHz
65
83
70
65
70
60
50
60
52
45
82
76
67
75
59
51
dB
dB
dB
dB
dB
dB
PSRRVDD5 Power Supply Rejection Ratio, Gain = 22.8 dB
@ 100 kHz
@ 500 kHz
@ 1 MHz
VDD5
VSUPPLYAC = 100 mVPP
PSRRVSS5 Power Supply Rejection Ratio, Gain = 22.8 dB
@ 100 kHz
@ 500 kHz
@ 1 MHz
VSS5
VSUPPLYAC = 100 mVPP
PSRRVDD15 Power Supply Rejection Ratio, Gain = 22.8 dB
@ 100 kHz
@ 500 kHz
@ 1 MHz
VDD15
VSUPPYAC = 100 mVPP
PSRRVSS15 Power Supply Rejection Ratio, Gain = 22.8 dB
@ 100 kHz
@ 500 kHz
@ 1 MHz
VSS15
VSUPPLYAC = 100 mVPP
Gain accuracy
Output=TBDVPPDIFF, 500kHz
-0.4
0.4
∆Gain
5
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
P I N D E S C R I P T I O N
PIN
PIN DESCRIPTION
P I N
PIN NAME
FUNCTION
Digital input
1
EN_AC
A logic high enables the input common-mode feedback loop,
and input bias current cancellation circuit
Device Ground
2
3
GND
INP
INN
GND
G0
Ground
Analog input
Analog input
Ground
Positive terminal of differential input
4
Negative terminal of differential input
5
Device Ground
6
Digital input
Digital input
Digital input
Digital input
No Connect
Least Significant Bit of programmable gain select
Second Least Significant Bit of programmable gain select
Third Least Significant Bit of programmable gain select
Most Significant Bit of programmable gain select
7
G1
8
G2
9
G3
10
11
NC
FAULT
Digital output A logic level high indicates that the device has an output short
(open drain)
Digital input
circuit or that a thermal overload has occurred
12
13
14
FORC_BIAS
TH_FAULT
RESETB
When set to a logic high, the device forces the bias on
regardless of fault conditions Intended for test only
When set to a logic high, the device simulates a thermal fault.
Intended for test only
Analog input
Digital input
When AUTO_CLR is set to a logic low, a logic low pulse on
RESETB clears the internal Fault latch; otherwise, connect
RESETB to VDD5; Logic low puts device in disabled mode
When set to logic high, the device goes into low-power mode
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LOPWR
VSS5
NC
Digital input
Power supply Negative 5V supply voltage
No Connect
OUTN
NC
Analog output Negative terminal of differential output
No Connect
VSS15
VDD15
NC
Power supply Negative 15V supply voltage
Power supply Positive 15V supply voltage
No Connect
OUTP
NC
Analog output Positive terminal of differential output
No Connect
VDD5
NC
Power supply Positive 5V supply voltage
No Connect
REXT
Analog input
Ground
Sets over-current limit
GND
Device Ground
FBN
Analog input
Analog input
Digital input
Feedback path for synthesized output impedance
Feedback path for synthesized output impedance
A logic high forces an immediate reset of the fault latch when
RESETB is a logic high. A logic low requires that the RESETB
pin be pulsed low to reset the fault latch
FBP
AUTO_CLR
32
NC
No Connect
Substrate
EP Exposed pad
Exposed pad at underside of device; must be connected to
VSS15. Internally connected to the substrate.
6
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
TLD4012
32-PIN TQFP WITH
EXPOSED DIE PAD
(Top View)
25
32 31 30 29 28 27 26
EN_AC
GND
INP
INN
GND
G0
1
2
3
4
5
6
7
8
24
NC
OUTP
NC
VDD15
VSS15
NC
23
22
21
20
19
18
17
G1
G2
OUTN
NC
9
10 11 12 13 14 15 16
7
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
F U N C T I O N A L D E S C R I P T I O N
Programmable Gain
The gain of the TLD4012 is programmed by the digital inputs G3, G2, G1 and G0. The gain given below is
the gain from the input to the output of the TLD4012 with RS=10Ω and RLOAD=50Ω as shown in Figure 1.
Note that output voltage swing is limited for gains less than 17.8 dB (see parameter VOUTMAX in Electrical
Characteristics).
G3 G2 G1 G0 Gain, dB Gain, V/V
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12.8
13.8
14.8
15.8
16.8
17.8
18.8
19.8
20.8
21.8
22.8
23.8
24.8
25.8
26.8
27.8
4.37
4.90
5.50
6.17
6.92
7.76
8.71
9.77
10.96
12.30
13.80
15.49
17.38
19.50
21.88
24.55
Protection Circuits
The TLD4012 has built-in protection against over-temperature and over-current conditions. There are two
modes in which the fault protection circuits can operate depending on the state of the AUTO_CLR pin.
The two modes operate as follows:
1. AUTO_CLR pin is set to a logic low level - When the device goes into an over-temperature or over-
current condition, the FAULT pin is latched into a logic HIGH state indicating a fault condition. When
this occurs, the amplifier outputs enter disable mode and are in a high-impedance state provided
OUTP and OUTN are not driven externally to exceed approximately +/-2.0Vppdiff. After the fault
condition has been removed, a logic LOW pulse must be applied to the RESETB pin for a minimum of
100 ns to reset the FAULT output to a logic low level, and re-enable the output to a normal, low
impedance mode.
2. AUTO_CLR pin is set to a logic high level - After a fault occurs and the fault condition is removed, the
device will enable the outputs, and reset the FAULT pin every 1 micro-second. In this mode the fault
latch is reset internally on power up so an external reset is not required. Note that in the case of an
over-current fault, if the cause of the over-current condition has not actually cleared, the output stage
will cycle continuously between the normal, enabled state, and the fault, or disabled state. In this
mode the FAULT output pin can cycle continuously until the cause of the fault is cleared. If this
operation is not desirable, see the “Over-current Protection” section below. If a microcontroller or DMT
processor is used to monitor the FAULT output, and to control the device, AUTO_CLR should be set
to a logic low level. Otherwise, AUTO_CLR should be set to a logic high level and the device will reset
itself on power-up and after a fault condition has been removed.
8
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
Over-temperature Protection
An over-temperature fault occurs if the junction temperature of the device exceeds approximately 160°C.
When a fault occurs the TLD4012 output driver enters the disabled mode, and asserts a logic HIGH on the
FAULT pin. An over-temperature fault can only be cleared after the junction temperature drops below
approximately 120°C.
Over-current Protection
An over-current fault occurs when current delivered from either of the output pins, OUTP or OUTN,
exceeds the current limit value. When a fault occurs, the TLD4012’s output driver enters disabled mode,
and asserts a logic HIGH on the FAULT pin. The level at which the current limit occurs is set by REXT
The relationship between the over-current limit and REXT is:
.
REXT = 19.2 / ICL , where ICL is the short circuit current limit in A, and REXT is in kΩ.
The acceptable range of REXT is 19.2 kΩ to 32 kΩ, or 1.0 A to 600 mA, respectively. A typical value for
REXT in most ADSL applications is 24kΩ which results in an 800mA current limit.
If the device is operated with AUTO_CLR set to a logic high level, and an over-current condition occurs,
the device will cycle between the fault state and normal state as described in the “Protection Circuits”
section above.
If the cycling mode described above is not desirable, the over-current limit can be set to 1.0 A, (i.e. REXT
19.2 kΩ). With this current limit value, the device will not enter the cycling mode if a short occurs on the
twisted pair because the matching resistors, RS, will limit the current to less than 1.0A. The over-
temperature protection will eventually act to protect the device, and in the event of a short on the board,
the over-current protection will still take affect to protect the device.
=
Low-Power Mode
The TLD4012 can be placed into a low-power consumption mode by asserting a logic HIGH on the
LOPWR input. In this mode the device consumes approximately 130 mW, but still provides a low output
resistance to allow reception of incoming signals.
Disable Mode
The TLD4012 can be placed in a lower power disabled mode by holding RESETB to a logic low level. In
this mode the power dissipation is only 10 mW, and the line is not terminated so reception of incoming
signals is not reliable. In this mode the outputs are high impedance as long as they are not driven
externally more than about +/-2.0Vppdiff around ground. Beyond this voltage the outputs become low
impedance.
Upon power-up the TLD4012 does not exit disabled mode until the VDD5/VSS5 power supply pins are
greater than about 4.2V. It will automatically enter disabled mode when the VDD5/VSS5 supply pins are
less than about 4.0V.
Input Common-mode Feedback Loop and Input-Bias-Current Cancellation
The TLD4012 has a common-mode feedback loop on the input stage and an input-bias-current
cancellation circuit. Setting the EN_AC input to a logic high level enables both features. When enabled
the common-mode feedback loop will set the common-mode input voltage. This allows use of a
differential filter (i.e. not referenced to ground) between the AFE and the driver. When the common-mode
feedback loop is disabled (EN_AC = Low) the application should replace the single input resistor, RIN,
shown in Figure 1 with two input resistors connected from the inputs, INN and INP, to ground.
9
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
T E S T / A P P L I C A T I O N C I R C U I T
Synthesized Output Impedance
Device TLD4012 employs synthesized output impedance with a synthesis factor of 2.55. As with any line
driver, using synthesized impedance reduces power consumption, but may compromise receive-signal
strength in some applications. The 10Ω matching resistors will properly terminate a 100Ω line when a
1:1.4 transformer is used (see Figure 1). Note that, for simplicity, the hybrid and other filtering associated
with the receive signal path are not shown.
VDD5
VDD15
VSS15
VSS5
10 F 0.1
µ
F
10 F
µ
0.1
F
1 F
µ
0.1
D1
F
1 F
µ
0.1 F
µ
µ
µ
µ
TLD4012
VDD5
25
VSS5
16
VDD15
21
VSS15
20
RLOAD
30 FBP
INP 3
INN 4
RS
RS
CIN
CIN
From Analog
Front End
Power
OUTP
23
RIN
Processing
Block
RLINE
18 OUTN
T1
29 FBN
G3 9
Output
REXT
REXT
27
G2
G1
8
current
limit
7
6
Control
&
G0
Micro
Controller
FAULT
11
RESETB
LOPWR
EN_AC
14
15
1
VLOGIC
25k
Logic
AUTO_CLR
31
12
FORC_BIAS TH_FAULT
2
5
28
13
GND GND GND
T1 = 1:1.4 Transformer
CIN = 0.1 µF
RIN = 5 kΩ
RS = 10 Ω
REXT = 24 KΩ
R
LINE = 100 Ω
D1 = One UPS840 schottky diode or equivalent per 48 drivers.
Test/Application Circuit – with synthesized output impedance, TLD4012
Figure 1
10
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
A P P L I C A T I O N I N F O R M A T I O N
Power Dissipation Derating for 5x5mm TQFP with Exposed Die Pad
For operating at ambient temperatures above 25°C the device power dissipation, PDISS, must be de-rated
based on a 150°C maximum junction temperature TJ (max) as given by the following equation:
PDISS = (TJ(max) – TA)/θJA
Where θJA of the package is determined from the table, and TA is the ambient temperature.
θJA,C/W
Airflow
(Copper Pad Soldered To PCB)
(LFPM)
5x5mm
0
34.5
29.1
27.2
200
500
Values apply when the exposed pad is soldered to a JEDEC standard test board.
Note that PDISS is the power dissipated on the chip, not PCONS which is the power consumed from the
supplies.
The TLD4012 incorporates an exposed die pad on the underside of its package. This acts as a heat sink
and should be connected to a copper plane on the printed circuit board for optimum heat dissipation. This
copper plane must be connected to VSS15.
11
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
P A C K A G E I N F O R M A T I O N
5x5mm TQFP with exposed die pad
D1
E1
f1
f2
Pin 1
e
b
A2
c
S
A1
L1
L
All dimensions in mm
BOD
LEAD
LEAD
LEAD
SHOU
L
EXPOSE
D PAD
Y
LEAD
LENGT
H
LEAD
WIDT
H
LEAD
PITC
H
BOTTO
LEAD
COUN
T
BODY
SIZE
STAN
THIC
K
THIC
K
M
ATTAC
H
D-OFF
(BOTTOM
SIDE)
NESS
DER
NESS
D1 E1
A1
A2
L1
b
c
e
L
S
f1
f2
5.
5.
0.45-
32
0.04
1.0
1.0
0.22
0.15
0.5
Min0.2
3.5
3.5
0
0
0.75
12
TLD4012 – JB/Rev. 2.0a/05.02
Tripath Technology, Inc. - Technical Information
Tripath and Digital Power Processing are trademarks of Tripath Technology, Inc. Other trademarks referenced in
this document are owned by their respective companies.
Tripath Technology, Inc. reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. Tripath does not assume any liability arising out of the application of use of
any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of
others.
TRIPATH’S PRODUCT ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH
TECHONOLOGY, INC. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance
with instructions for use provided in this labeling, can be reasonably expected to result in significant
injury of the user.
2. A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
Contact Information
TRIPATH TECHNOLOGY, INC
2560 Orchard Parkway, San Jose, CA 95131
408.750.3000 - P
408.750.3001 - F
For more Sales Information, please visit us @ www.tripath.com/cont_s.htm
For more Technical Information, please visit us @ www.tripath.com/data.htm
13
TLD4012 – JB/Rev. 2.0a/05.02
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